624 files changed, 322400 insertions, 7638 deletions

diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c
index 5691f165a952..8dff236f7ed3 100644
--- a/drivers/acpi/osl.c
+++ b/drivers/acpi/osl.c
@@ -1182,7 +1182,13 @@ int acpi_check_resource_conflict(struct resource *res)
 			       res_list_elem->name,
 			       (long long) res_list_elem->start,
 			       (long long) res_list_elem->end);
-			printk(KERN_INFO "ACPI: Device needs an ACPI driver\n");
+			if (acpi_enforce_resources == ENFORCE_RESOURCES_LAX)
+				printk(KERN_NOTICE "ACPI: This conflict may"
+				       " cause random problems and system"
+				       " instability\n");
+			printk(KERN_INFO "ACPI: If an ACPI driver is available"
+			       " for this device, you should use it instead of"
+			       " the native driver\n");
 		}
 		if (acpi_enforce_resources == ENFORCE_RESOURCES_STRICT)
 			return -EBUSY;
diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index 55b5b90c2a44..97fad2979920 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -400,6 +400,17 @@ struct pci_dev *acpi_get_pci_dev(acpi_handle handle)
 
 		pbus = pdev->subordinate;
 		pci_dev_put(pdev);
+
+		/*
+		 * This function may be called for a non-PCI device that has a
+		 * PCI parent (eg. a disk under a PCI SATA controller).  In that
+		 * case pdev->subordinate will be NULL for the parent.
+		 */
+		if (!pbus) {
+			dev_dbg(&pdev->dev, "Not a PCI-to-PCI bridge\n");
+			pdev = NULL;
+			break;
+		}
 	}
 out:
 	list_for_each_entry_safe(node, tmp, &device_list, node)
diff --git a/drivers/acpi/pci_slot.c b/drivers/acpi/pci_slot.c
index 12158e0d009b..da9d6d25cf6d 100644
--- a/drivers/acpi/pci_slot.c
+++ b/drivers/acpi/pci_slot.c
@@ -57,7 +57,7 @@ ACPI_MODULE_NAME("pci_slot");
 				MY_NAME , ## arg);		\
 	} while (0)
 
-#define SLOT_NAME_SIZE 20		/* Inspired by #define in acpiphp.h */
+#define SLOT_NAME_SIZE 21		/* Inspired by #define in acpiphp.h */
 
 struct acpi_pci_slot {
 	acpi_handle root_handle;	/* handle of the root bridge */
@@ -149,7 +149,7 @@ register_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
 		return AE_OK;
 	}
 
-	snprintf(name, sizeof(name), "%u", (u32)sun);
+	snprintf(name, sizeof(name), "%llu", sun);
 	pci_slot = pci_create_slot(pci_bus, device, name, NULL);
 	if (IS_ERR(pci_slot)) {
 		err("pci_create_slot returned %ld\n", PTR_ERR(pci_slot));
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index 66393d5c4c7c..f6d84694f17f 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -876,12 +876,14 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev,
 		return(acpi_idle_enter_c1(dev, state));
 
 	local_irq_disable();
-	current_thread_info()->status &= ~TS_POLLING;
-	/*
-	 * TS_POLLING-cleared state must be visible before we test
-	 * NEED_RESCHED:
-	 */
-	smp_mb();
+	if (cx->entry_method != ACPI_CSTATE_FFH) {
+		current_thread_info()->status &= ~TS_POLLING;
+		/*
+		 * TS_POLLING-cleared state must be visible before we test
+		 * NEED_RESCHED:
+		 */
+		smp_mb();
+	}
 
 	if (unlikely(need_resched())) {
 		current_thread_info()->status |= TS_POLLING;
@@ -961,12 +963,14 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
 	}
 
 	local_irq_disable();
-	current_thread_info()->status &= ~TS_POLLING;
-	/*
-	 * TS_POLLING-cleared state must be visible before we test
-	 * NEED_RESCHED:
-	 */
-	smp_mb();
+	if (cx->entry_method != ACPI_CSTATE_FFH) {
+		current_thread_info()->status &= ~TS_POLLING;
+		/*
+		 * TS_POLLING-cleared state must be visible before we test
+		 * NEED_RESCHED:
+		 */
+		smp_mb();
+	}
 
 	if (unlikely(need_resched())) {
 		current_thread_info()->status |= TS_POLLING;
diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index 781435d7e369..5dd702c9c1fa 100644
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -1264,16 +1264,6 @@ acpi_add_single_object(struct acpi_device **child,
 	acpi_device_set_id(device, parent, handle, type);
 
 	/*
-	 * The ACPI device is attached to acpi handle before getting
-	 * the power/wakeup/peformance flags. Otherwise OS can't get
-	 * the corresponding ACPI device by the acpi handle in the course
-	 * of getting the power/wakeup/performance flags.
-	 */
-	result = acpi_device_set_context(device, type);
-	if (result)
-		goto end;
-
-	/*
 	 * Power Management
 	 * ----------------
 	 */
@@ -1303,6 +1293,8 @@ acpi_add_single_object(struct acpi_device **child,
 			goto end;
 	}
 
+	if ((result = acpi_device_set_context(device, type)))
+		goto end;
 
 	result = acpi_device_register(device, parent);
 
diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c
index 42159a28f433..1caac3b1a558 100644
--- a/drivers/acpi/sleep.c
+++ b/drivers/acpi/sleep.c
@@ -405,6 +405,46 @@ static struct dmi_system_id __initdata acpisleep_dmi_table[] = {
 		},
 	},
 	{
+	.callback = init_set_sci_en_on_resume,
+	.ident = "Hewlett-Packard HP Pavilion dv3 Notebook PC",
+	.matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion dv3 Notebook PC"),
+		},
+	},
+	{
+	.callback = init_set_sci_en_on_resume,
+	.ident = "Hewlett-Packard Pavilion dv4",
+	.matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion dv4"),
+		},
+	},
+	{
+	.callback = init_set_sci_en_on_resume,
+	.ident = "Hewlett-Packard Pavilion dv7",
+	.matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion dv7"),
+		},
+	},
+	{
+	.callback = init_set_sci_en_on_resume,
+	.ident = "Hewlett-Packard Compaq Presario C700 Notebook PC",
+	.matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Compaq Presario C700 Notebook PC"),
+		},
+	},
+	{
+	.callback = init_set_sci_en_on_resume,
+	.ident = "Hewlett-Packard Compaq Presario CQ40 Notebook PC",
+	.matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Compaq Presario CQ40 Notebook PC"),
+		},
+	},
+	{
 	.callback = init_old_suspend_ordering,
 	.ident = "Panasonic CF51-2L",
 	.matches = {
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index ae02b4114a6f..d7198890cdd3 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -55,6 +55,14 @@ config SATA_AHCI
 
 	  If unsure, say N.
 
+config SATA_AHCI_PLATFORM
+	tristate "Platform AHCI SATA support"
+	help
+	  This option enables support for Platform AHCI Serial ATA
+	  controllers.
+
+	  If unsure, say N.
+
 config SATA_SIL24
 	tristate "Silicon Image 3124/3132 SATA support"
 	depends on PCI
@@ -72,6 +80,7 @@ config SATA_FSL
 
 	  If unsure, say N.
 
+
 config ATA_SFF
 	bool "ATA SFF support"
 	default y
@@ -759,6 +768,14 @@ config PATA_FSL
          ATA interface.
          If you are unsure, say N to this.
 
+config PATA_FSL_DISABLE_DMA
+	bool "Disable DMA on Freescale on-chip PATA devices"
+	depends on PATA_FSL
+	default y
+	help
+	  Say yes to disable the Ultra DMA and Multi Word DMA transfers on
+	  Freescale PATA SoC interface.
+
 endif # ATA_SFF
 
 endif # ATA
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index de9fda120642..69bcefa0df6b 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -1,7 +1,8 @@
 
 obj-$(CONFIG_ATA)		+= libata.o
 
-obj-$(CONFIG_SATA_AHCI)		+= ahci.o
+obj-$(CONFIG_SATA_AHCI)		+= ahci.o libahci.o
+obj-$(CONFIG_SATA_AHCI_PLATFORM) += ahci_platform.o libahci.o
 obj-$(CONFIG_SATA_SVW)		+= sata_svw.o
 obj-$(CONFIG_ATA_PIIX)		+= ata_piix.o
 obj-$(CONFIG_SATA_PROMISE)	+= sata_promise.o
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index fe3eba5d6b3e..38f4d0fc46a8 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -45,64 +45,13 @@
 #include <scsi/scsi_host.h>
 #include <scsi/scsi_cmnd.h>
 #include <linux/libata.h>
+#include "ahci.h"
 
 #define DRV_NAME	"ahci"
 #define DRV_VERSION	"3.0"
 
-/* Enclosure Management Control */
-#define EM_CTRL_MSG_TYPE              0x000f0000
-
-/* Enclosure Management LED Message Type */
-#define EM_MSG_LED_HBA_PORT           0x0000000f
-#define EM_MSG_LED_PMP_SLOT           0x0000ff00
-#define EM_MSG_LED_VALUE              0xffff0000
-#define EM_MSG_LED_VALUE_ACTIVITY     0x00070000
-#define EM_MSG_LED_VALUE_OFF          0xfff80000
-#define EM_MSG_LED_VALUE_ON           0x00010000
-
-static int ahci_skip_host_reset;
-static int ahci_ignore_sss;
-
-module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
-MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
-
-module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
-MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
-
-static int ahci_enable_alpm(struct ata_port *ap,
-		enum link_pm policy);
-static void ahci_disable_alpm(struct ata_port *ap);
-static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
-static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
-			      size_t size);
-static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
-					ssize_t size);
-
 enum {
 	AHCI_PCI_BAR		= 5,
-	AHCI_MAX_PORTS		= 32,
-	AHCI_MAX_SG		= 168, /* hardware max is 64K */
-	AHCI_DMA_BOUNDARY	= 0xffffffff,
-	AHCI_MAX_CMDS		= 32,
-	AHCI_CMD_SZ		= 32,
-	AHCI_CMD_SLOT_SZ	= AHCI_MAX_CMDS * AHCI_CMD_SZ,
-	AHCI_RX_FIS_SZ		= 256,
-	AHCI_CMD_TBL_CDB	= 0x40,
-	AHCI_CMD_TBL_HDR_SZ	= 0x80,
-	AHCI_CMD_TBL_SZ		= AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
-	AHCI_CMD_TBL_AR_SZ	= AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
-	AHCI_PORT_PRIV_DMA_SZ	= AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
-				  AHCI_RX_FIS_SZ,
-	AHCI_IRQ_ON_SG		= (1 << 31),
-	AHCI_CMD_ATAPI		= (1 << 5),
-	AHCI_CMD_WRITE		= (1 << 6),
-	AHCI_CMD_PREFETCH	= (1 << 7),
-	AHCI_CMD_RESET		= (1 << 8),
-	AHCI_CMD_CLR_BUSY	= (1 << 10),
-
-	RX_FIS_D2H_REG		= 0x40,	/* offset of D2H Register FIS data */
-	RX_FIS_SDB		= 0x58, /* offset of SDB FIS data */
-	RX_FIS_UNK		= 0x60, /* offset of Unknown FIS data */
 
 	board_ahci		= 0,
 	board_ahci_vt8251	= 1,
@@ -113,280 +62,20 @@ enum {
 	board_ahci_mcp65	= 6,
 	board_ahci_nopmp	= 7,
 	board_ahci_yesncq	= 8,
-
-	/* global controller registers */
-	HOST_CAP		= 0x00, /* host capabilities */
-	HOST_CTL		= 0x04, /* global host control */
-	HOST_IRQ_STAT		= 0x08, /* interrupt status */
-	HOST_PORTS_IMPL		= 0x0c, /* bitmap of implemented ports */
-	HOST_VERSION		= 0x10, /* AHCI spec. version compliancy */
-	HOST_EM_LOC		= 0x1c, /* Enclosure Management location */
-	HOST_EM_CTL		= 0x20, /* Enclosure Management Control */
-
-	/* HOST_CTL bits */
-	HOST_RESET		= (1 << 0),  /* reset controller; self-clear */
-	HOST_IRQ_EN		= (1 << 1),  /* global IRQ enable */
-	HOST_AHCI_EN		= (1 << 31), /* AHCI enabled */
-
-	/* HOST_CAP bits */
-	HOST_CAP_EMS		= (1 << 6),  /* Enclosure Management support */
-	HOST_CAP_SSC		= (1 << 14), /* Slumber capable */
-	HOST_CAP_PMP		= (1 << 17), /* Port Multiplier support */
-	HOST_CAP_CLO		= (1 << 24), /* Command List Override support */
-	HOST_CAP_ALPM		= (1 << 26), /* Aggressive Link PM support */
-	HOST_CAP_SSS		= (1 << 27), /* Staggered Spin-up */
-	HOST_CAP_SNTF		= (1 << 29), /* SNotification register */
-	HOST_CAP_NCQ		= (1 << 30), /* Native Command Queueing */
-	HOST_CAP_64		= (1 << 31), /* PCI DAC (64-bit DMA) support */
-
-	/* registers for each SATA port */
-	PORT_LST_ADDR		= 0x00, /* command list DMA addr */
-	PORT_LST_ADDR_HI	= 0x04, /* command list DMA addr hi */
-	PORT_FIS_ADDR		= 0x08, /* FIS rx buf addr */
-	PORT_FIS_ADDR_HI	= 0x0c, /* FIS rx buf addr hi */
-	PORT_IRQ_STAT		= 0x10, /* interrupt status */
-	PORT_IRQ_MASK		= 0x14, /* interrupt enable/disable mask */
-	PORT_CMD		= 0x18, /* port command */
-	PORT_TFDATA		= 0x20,	/* taskfile data */
-	PORT_SIG		= 0x24,	/* device TF signature */
-	PORT_CMD_ISSUE		= 0x38, /* command issue */
-	PORT_SCR_STAT		= 0x28, /* SATA phy register: SStatus */
-	PORT_SCR_CTL		= 0x2c, /* SATA phy register: SControl */
-	PORT_SCR_ERR		= 0x30, /* SATA phy register: SError */
-	PORT_SCR_ACT		= 0x34, /* SATA phy register: SActive */
-	PORT_SCR_NTF		= 0x3c, /* SATA phy register: SNotification */
-
-	/* PORT_IRQ_{STAT,MASK} bits */
-	PORT_IRQ_COLD_PRES	= (1 << 31), /* cold presence detect */
-	PORT_IRQ_TF_ERR		= (1 << 30), /* task file error */
-	PORT_IRQ_HBUS_ERR	= (1 << 29), /* host bus fatal error */
-	PORT_IRQ_HBUS_DATA_ERR	= (1 << 28), /* host bus data error */
-	PORT_IRQ_IF_ERR		= (1 << 27), /* interface fatal error */
-	PORT_IRQ_IF_NONFATAL	= (1 << 26), /* interface non-fatal error */
-	PORT_IRQ_OVERFLOW	= (1 << 24), /* xfer exhausted available S/G */
-	PORT_IRQ_BAD_PMP	= (1 << 23), /* incorrect port multiplier */
-
-	PORT_IRQ_PHYRDY		= (1 << 22), /* PhyRdy changed */
-	PORT_IRQ_DEV_ILCK	= (1 << 7), /* device interlock */
-	PORT_IRQ_CONNECT	= (1 << 6), /* port connect change status */
-	PORT_IRQ_SG_DONE	= (1 << 5), /* descriptor processed */
-	PORT_IRQ_UNK_FIS	= (1 << 4), /* unknown FIS rx'd */
-	PORT_IRQ_SDB_FIS	= (1 << 3), /* Set Device Bits FIS rx'd */
-	PORT_IRQ_DMAS_FIS	= (1 << 2), /* DMA Setup FIS rx'd */
-	PORT_IRQ_PIOS_FIS	= (1 << 1), /* PIO Setup FIS rx'd */
-	PORT_IRQ_D2H_REG_FIS	= (1 << 0), /* D2H Register FIS rx'd */
-
-	PORT_IRQ_FREEZE		= PORT_IRQ_HBUS_ERR |
-				  PORT_IRQ_IF_ERR |
-				  PORT_IRQ_CONNECT |
-				  PORT_IRQ_PHYRDY |
-				  PORT_IRQ_UNK_FIS |
-				  PORT_IRQ_BAD_PMP,
-	PORT_IRQ_ERROR		= PORT_IRQ_FREEZE |
-				  PORT_IRQ_TF_ERR |
-				  PORT_IRQ_HBUS_DATA_ERR,
-	DEF_PORT_IRQ		= PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
-				  PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
-				  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
-
-	/* PORT_CMD bits */
-	PORT_CMD_ASP		= (1 << 27), /* Aggressive Slumber/Partial */
-	PORT_CMD_ALPE		= (1 << 26), /* Aggressive Link PM enable */
-	PORT_CMD_ATAPI		= (1 << 24), /* Device is ATAPI */
-	PORT_CMD_PMP		= (1 << 17), /* PMP attached */
-	PORT_CMD_LIST_ON	= (1 << 15), /* cmd list DMA engine running */
-	PORT_CMD_FIS_ON		= (1 << 14), /* FIS DMA engine running */
-	PORT_CMD_FIS_RX		= (1 << 4), /* Enable FIS receive DMA engine */
-	PORT_CMD_CLO		= (1 << 3), /* Command list override */
-	PORT_CMD_POWER_ON	= (1 << 2), /* Power up device */
-	PORT_CMD_SPIN_UP	= (1 << 1), /* Spin up device */
-	PORT_CMD_START		= (1 << 0), /* Enable port DMA engine */
-
-	PORT_CMD_ICC_MASK	= (0xf << 28), /* i/f ICC state mask */
-	PORT_CMD_ICC_ACTIVE	= (0x1 << 28), /* Put i/f in active state */
-	PORT_CMD_ICC_PARTIAL	= (0x2 << 28), /* Put i/f in partial state */
-	PORT_CMD_ICC_SLUMBER	= (0x6 << 28), /* Put i/f in slumber state */
-
-	/* hpriv->flags bits */
-	AHCI_HFLAG_NO_NCQ		= (1 << 0),
-	AHCI_HFLAG_IGN_IRQ_IF_ERR	= (1 << 1), /* ignore IRQ_IF_ERR */
-	AHCI_HFLAG_IGN_SERR_INTERNAL	= (1 << 2), /* ignore SERR_INTERNAL */
-	AHCI_HFLAG_32BIT_ONLY		= (1 << 3), /* force 32bit */
-	AHCI_HFLAG_MV_PATA		= (1 << 4), /* PATA port */
-	AHCI_HFLAG_NO_MSI		= (1 << 5), /* no PCI MSI */
-	AHCI_HFLAG_NO_PMP		= (1 << 6), /* no PMP */
-	AHCI_HFLAG_NO_HOTPLUG		= (1 << 7), /* ignore PxSERR.DIAG.N */
-	AHCI_HFLAG_SECT255		= (1 << 8), /* max 255 sectors */
-	AHCI_HFLAG_YES_NCQ		= (1 << 9), /* force NCQ cap on */
-	AHCI_HFLAG_NO_SUSPEND		= (1 << 10), /* don't suspend */
-	AHCI_HFLAG_SRST_TOUT_IS_OFFLINE	= (1 << 11), /* treat SRST timeout as
-							link offline */
-
-	/* ap->flags bits */
-
-	AHCI_FLAG_COMMON		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
-					  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
-					  ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
-					  ATA_FLAG_IPM,
-
-	ICH_MAP				= 0x90, /* ICH MAP register */
-
-	/* em constants */
-	EM_MAX_SLOTS			= 8,
-	EM_MAX_RETRY			= 5,
-
-	/* em_ctl bits */
-	EM_CTL_RST			= (1 << 9), /* Reset */
-	EM_CTL_TM			= (1 << 8), /* Transmit Message */
-	EM_CTL_ALHD			= (1 << 26), /* Activity LED */
-};
-
-struct ahci_cmd_hdr {
-	__le32			opts;
-	__le32			status;
-	__le32			tbl_addr;
-	__le32			tbl_addr_hi;
-	__le32			reserved[4];
+	board_ahci_nosntf	= 9,
 };
 
-struct ahci_sg {
-	__le32			addr;
-	__le32			addr_hi;
-	__le32			reserved;
-	__le32			flags_size;
-};
-
-struct ahci_em_priv {
-	enum sw_activity blink_policy;
-	struct timer_list timer;
-	unsigned long saved_activity;
-	unsigned long activity;
-	unsigned long led_state;
-};
-
-struct ahci_host_priv {
-	unsigned int		flags;		/* AHCI_HFLAG_* */
-	u32			cap;		/* cap to use */
-	u32			port_map;	/* port map to use */
-	u32			saved_cap;	/* saved initial cap */
-	u32			saved_port_map;	/* saved initial port_map */
-	u32 			em_loc; /* enclosure management location */
-};
-
-struct ahci_port_priv {
-	struct ata_link		*active_link;
-	struct ahci_cmd_hdr	*cmd_slot;
-	dma_addr_t		cmd_slot_dma;
-	void			*cmd_tbl;
-	dma_addr_t		cmd_tbl_dma;
-	void			*rx_fis;
-	dma_addr_t		rx_fis_dma;
-	/* for NCQ spurious interrupt analysis */
-	unsigned int		ncq_saw_d2h:1;
-	unsigned int		ncq_saw_dmas:1;
-	unsigned int		ncq_saw_sdb:1;
-	u32 			intr_mask;	/* interrupts to enable */
-	/* enclosure management info per PM slot */
-	struct ahci_em_priv	em_priv[EM_MAX_SLOTS];
-};
-
-static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
-static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
-static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
-static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
-static int ahci_port_start(struct ata_port *ap);
-static void ahci_port_stop(struct ata_port *ap);
-static void ahci_qc_prep(struct ata_queued_cmd *qc);
-static void ahci_freeze(struct ata_port *ap);
-static void ahci_thaw(struct ata_port *ap);
-static void ahci_pmp_attach(struct ata_port *ap);
-static void ahci_pmp_detach(struct ata_port *ap);
-static int ahci_softreset(struct ata_link *link, unsigned int *class,
-			  unsigned long deadline);
 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
 			  unsigned long deadline);
-static int ahci_hardreset(struct ata_link *link, unsigned int *class,
-			  unsigned long deadline);
 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 				 unsigned long deadline);
 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 				unsigned long deadline);
-static void ahci_postreset(struct ata_link *link, unsigned int *class);
-static void ahci_error_handler(struct ata_port *ap);
-static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
-static int ahci_port_resume(struct ata_port *ap);
-static void ahci_dev_config(struct ata_device *dev);
-static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
-			       u32 opts);
 #ifdef CONFIG_PM
-static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
 static int ahci_pci_device_resume(struct pci_dev *pdev);
 #endif
-static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
-static ssize_t ahci_activity_store(struct ata_device *dev,
-				   enum sw_activity val);
-static void ahci_init_sw_activity(struct ata_link *link);
-
-static struct device_attribute *ahci_shost_attrs[] = {
-	&dev_attr_link_power_management_policy,
-	&dev_attr_em_message_type,
-	&dev_attr_em_message,
-	NULL
-};
-
-static struct device_attribute *ahci_sdev_attrs[] = {
-	&dev_attr_sw_activity,
-	&dev_attr_unload_heads,
-	NULL
-};
-
-static struct scsi_host_template ahci_sht = {
-	ATA_NCQ_SHT(DRV_NAME),
-	.can_queue		= AHCI_MAX_CMDS - 1,
-	.sg_tablesize		= AHCI_MAX_SG,
-	.dma_boundary		= AHCI_DMA_BOUNDARY,
-	.shost_attrs		= ahci_shost_attrs,
-	.sdev_attrs		= ahci_sdev_attrs,
-};
-
-static struct ata_port_operations ahci_ops = {
-	.inherits		= &sata_pmp_port_ops,
-
-	.qc_defer		= sata_pmp_qc_defer_cmd_switch,
-	.qc_prep		= ahci_qc_prep,
-	.qc_issue		= ahci_qc_issue,
-	.qc_fill_rtf		= ahci_qc_fill_rtf,
-
-	.freeze			= ahci_freeze,
-	.thaw			= ahci_thaw,
-	.softreset		= ahci_softreset,
-	.hardreset		= ahci_hardreset,
-	.postreset		= ahci_postreset,
-	.pmp_softreset		= ahci_softreset,
-	.error_handler		= ahci_error_handler,
-	.post_internal_cmd	= ahci_post_internal_cmd,
-	.dev_config		= ahci_dev_config,
-
-	.scr_read		= ahci_scr_read,
-	.scr_write		= ahci_scr_write,
-	.pmp_attach		= ahci_pmp_attach,
-	.pmp_detach		= ahci_pmp_detach,
-
-	.enable_pm		= ahci_enable_alpm,
-	.disable_pm		= ahci_disable_alpm,
-	.em_show		= ahci_led_show,
-	.em_store		= ahci_led_store,
-	.sw_activity_show	= ahci_activity_show,
-	.sw_activity_store	= ahci_activity_store,
-#ifdef CONFIG_PM
-	.port_suspend		= ahci_port_suspend,
-	.port_resume		= ahci_port_resume,
-#endif
-	.port_start		= ahci_port_start,
-	.port_stop		= ahci_port_stop,
-};
 
 static struct ata_port_operations ahci_vt8251_ops = {
 	.inherits		= &ahci_ops,
@@ -433,7 +122,8 @@ static const struct ata_port_info ahci_port_info[] = {
 	[board_ahci_sb600] =
 	{
 		AHCI_HFLAGS	(AHCI_HFLAG_IGN_SERR_INTERNAL |
-				 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255),
+				 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
+				 AHCI_HFLAG_SECT255),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
@@ -473,7 +163,7 @@ static const struct ata_port_info ahci_port_info[] = {
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
-	/* board_ahci_yesncq */
+	[board_ahci_yesncq] =
 	{
 		AHCI_HFLAGS	(AHCI_HFLAG_YES_NCQ),
 		.flags		= AHCI_FLAG_COMMON,
@@ -481,6 +171,14 @@ static const struct ata_port_info ahci_port_info[] = {
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
+	[board_ahci_nosntf] =
+	{
+		AHCI_HFLAGS	(AHCI_HFLAG_NO_SNTF),
+		.flags		= AHCI_FLAG_COMMON,
+		.pio_mask	= ATA_PIO4,
+		.udma_mask	= ATA_UDMA6,
+		.port_ops	= &ahci_ops,
+	},
 };
 
 static const struct pci_device_id ahci_pci_tbl[] = {
@@ -496,7 +194,7 @@ static const struct pci_device_id ahci_pci_tbl[] = {
 	{ PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
 	{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
 	{ PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
-	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
+	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
 	{ PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
 	{ PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
 	{ PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
@@ -644,12 +342,6 @@ static struct pci_driver ahci_pci_driver = {
 #endif
 };
 
-static int ahci_em_messages = 1;
-module_param(ahci_em_messages, int, 0444);
-/* add other LED protocol types when they become supported */
-MODULE_PARM_DESC(ahci_em_messages,
-	"Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
-
 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
 static int marvell_enable;
 #else
@@ -659,112 +351,15 @@ module_param(marvell_enable, int, 0644);
 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
 
 
-static inline int ahci_nr_ports(u32 cap)
-{
-	return (cap & 0x1f) + 1;
-}
-
-static inline void __iomem *__ahci_port_base(struct ata_host *host,
-					     unsigned int port_no)
+static void ahci_pci_save_initial_config(struct pci_dev *pdev,
+					 struct ahci_host_priv *hpriv)
 {
-	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-
-	return mmio + 0x100 + (port_no * 0x80);
-}
+	unsigned int force_port_map = 0;
+	unsigned int mask_port_map = 0;
 
-static inline void __iomem *ahci_port_base(struct ata_port *ap)
-{
-	return __ahci_port_base(ap->host, ap->port_no);
-}
-
-static void ahci_enable_ahci(void __iomem *mmio)
-{
-	int i;
-	u32 tmp;
-
-	/* turn on AHCI_EN */
-	tmp = readl(mmio + HOST_CTL);
-	if (tmp & HOST_AHCI_EN)
-		return;
-
-	/* Some controllers need AHCI_EN to be written multiple times.
-	 * Try a few times before giving up.
-	 */
-	for (i = 0; i < 5; i++) {
-		tmp |= HOST_AHCI_EN;
-		writel(tmp, mmio + HOST_CTL);
-		tmp = readl(mmio + HOST_CTL);	/* flush && sanity check */
-		if (tmp & HOST_AHCI_EN)
-			return;
-		msleep(10);
-	}
-
-	WARN_ON(1);
-}
-
-/**
- *	ahci_save_initial_config - Save and fixup initial config values
- *	@pdev: target PCI device
- *	@hpriv: host private area to store config values
- *
- *	Some registers containing configuration info might be setup by
- *	BIOS and might be cleared on reset.  This function saves the
- *	initial values of those registers into @hpriv such that they
- *	can be restored after controller reset.
- *
- *	If inconsistent, config values are fixed up by this function.
- *
- *	LOCKING:
- *	None.
- */
-static void ahci_save_initial_config(struct pci_dev *pdev,
-				     struct ahci_host_priv *hpriv)
-{
-	void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
-	u32 cap, port_map;
-	int i;
-	int mv;
-
-	/* make sure AHCI mode is enabled before accessing CAP */
-	ahci_enable_ahci(mmio);
-
-	/* Values prefixed with saved_ are written back to host after
-	 * reset.  Values without are used for driver operation.
-	 */
-	hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
-	hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
-
-	/* some chips have errata preventing 64bit use */
-	if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
-		dev_printk(KERN_INFO, &pdev->dev,
-			   "controller can't do 64bit DMA, forcing 32bit\n");
-		cap &= ~HOST_CAP_64;
-	}
-
-	if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
-		dev_printk(KERN_INFO, &pdev->dev,
-			   "controller can't do NCQ, turning off CAP_NCQ\n");
-		cap &= ~HOST_CAP_NCQ;
-	}
-
-	if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
-		dev_printk(KERN_INFO, &pdev->dev,
-			   "controller can do NCQ, turning on CAP_NCQ\n");
-		cap |= HOST_CAP_NCQ;
-	}
-
-	if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
-		dev_printk(KERN_INFO, &pdev->dev,
-			   "controller can't do PMP, turning off CAP_PMP\n");
-		cap &= ~HOST_CAP_PMP;
-	}
-
-	if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
-	    port_map != 1) {
-		dev_printk(KERN_INFO, &pdev->dev,
-			   "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
-			   port_map, 1);
-		port_map = 1;
+	if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
+		dev_info(&pdev->dev, "JMB361 has only one port\n");
+		force_port_map = 1;
 	}
 
 	/*
@@ -774,466 +369,25 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
 	 */
 	if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 		if (pdev->device == 0x6121)
-			mv = 0x3;
+			mask_port_map = 0x3;
 		else
-			mv = 0xf;
-		dev_printk(KERN_ERR, &pdev->dev,
-			   "MV_AHCI HACK: port_map %x -> %x\n",
-			   port_map,
-			   port_map & mv);
-		dev_printk(KERN_ERR, &pdev->dev,
+			mask_port_map = 0xf;
+		dev_info(&pdev->dev,
 			  "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
-
-		port_map &= mv;
-	}
-
-	/* cross check port_map and cap.n_ports */
-	if (port_map) {
-		int map_ports = 0;
-
-		for (i = 0; i < AHCI_MAX_PORTS; i++)
-			if (port_map & (1 << i))
-				map_ports++;
-
-		/* If PI has more ports than n_ports, whine, clear
-		 * port_map and let it be generated from n_ports.
-		 */
-		if (map_ports > ahci_nr_ports(cap)) {
-			dev_printk(KERN_WARNING, &pdev->dev,
-				   "implemented port map (0x%x) contains more "
-				   "ports than nr_ports (%u), using nr_ports\n",
-				   port_map, ahci_nr_ports(cap));
-			port_map = 0;
-		}
-	}
-
-	/* fabricate port_map from cap.nr_ports */
-	if (!port_map) {
-		port_map = (1 << ahci_nr_ports(cap)) - 1;
-		dev_printk(KERN_WARNING, &pdev->dev,
-			   "forcing PORTS_IMPL to 0x%x\n", port_map);
-
-		/* write the fixed up value to the PI register */
-		hpriv->saved_port_map = port_map;
-	}
-
-	/* record values to use during operation */
-	hpriv->cap = cap;
-	hpriv->port_map = port_map;
-}
-
-/**
- *	ahci_restore_initial_config - Restore initial config
- *	@host: target ATA host
- *
- *	Restore initial config stored by ahci_save_initial_config().
- *
- *	LOCKING:
- *	None.
- */
-static void ahci_restore_initial_config(struct ata_host *host)
-{
-	struct ahci_host_priv *hpriv = host->private_data;
-	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-
-	writel(hpriv->saved_cap, mmio + HOST_CAP);
-	writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
-	(void) readl(mmio + HOST_PORTS_IMPL);	/* flush */
-}
-
-static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
-{
-	static const int offset[] = {
-		[SCR_STATUS]		= PORT_SCR_STAT,
-		[SCR_CONTROL]		= PORT_SCR_CTL,
-		[SCR_ERROR]		= PORT_SCR_ERR,
-		[SCR_ACTIVE]		= PORT_SCR_ACT,
-		[SCR_NOTIFICATION]	= PORT_SCR_NTF,
-	};
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-
-	if (sc_reg < ARRAY_SIZE(offset) &&
-	    (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
-		return offset[sc_reg];
-	return 0;
-}
-
-static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
-{
-	void __iomem *port_mmio = ahci_port_base(link->ap);
-	int offset = ahci_scr_offset(link->ap, sc_reg);
-
-	if (offset) {
-		*val = readl(port_mmio + offset);
-		return 0;
-	}
-	return -EINVAL;
-}
-
-static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
-{
-	void __iomem *port_mmio = ahci_port_base(link->ap);
-	int offset = ahci_scr_offset(link->ap, sc_reg);
-
-	if (offset) {
-		writel(val, port_mmio + offset);
-		return 0;
-	}
-	return -EINVAL;
-}
-
-static void ahci_start_engine(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 tmp;
-
-	/* start DMA */
-	tmp = readl(port_mmio + PORT_CMD);
-	tmp |= PORT_CMD_START;
-	writel(tmp, port_mmio + PORT_CMD);
-	readl(port_mmio + PORT_CMD); /* flush */
-}
-
-static int ahci_stop_engine(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 tmp;
-
-	tmp = readl(port_mmio + PORT_CMD);
-
-	/* check if the HBA is idle */
-	if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
-		return 0;
-
-	/* setting HBA to idle */
-	tmp &= ~PORT_CMD_START;
-	writel(tmp, port_mmio + PORT_CMD);
-
-	/* wait for engine to stop. This could be as long as 500 msec */
-	tmp = ata_wait_register(port_mmio + PORT_CMD,
-				PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
-	if (tmp & PORT_CMD_LIST_ON)
-		return -EIO;
-
-	return 0;
-}
-
-static void ahci_start_fis_rx(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	struct ahci_port_priv *pp = ap->private_data;
-	u32 tmp;
-
-	/* set FIS registers */
-	if (hpriv->cap & HOST_CAP_64)
-		writel((pp->cmd_slot_dma >> 16) >> 16,
-		       port_mmio + PORT_LST_ADDR_HI);
-	writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
-
-	if (hpriv->cap & HOST_CAP_64)
-		writel((pp->rx_fis_dma >> 16) >> 16,
-		       port_mmio + PORT_FIS_ADDR_HI);
-	writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
-
-	/* enable FIS reception */
-	tmp = readl(port_mmio + PORT_CMD);
-	tmp |= PORT_CMD_FIS_RX;
-	writel(tmp, port_mmio + PORT_CMD);
-
-	/* flush */
-	readl(port_mmio + PORT_CMD);
-}
-
-static int ahci_stop_fis_rx(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 tmp;
-
-	/* disable FIS reception */
-	tmp = readl(port_mmio + PORT_CMD);
-	tmp &= ~PORT_CMD_FIS_RX;
-	writel(tmp, port_mmio + PORT_CMD);
-
-	/* wait for completion, spec says 500ms, give it 1000 */
-	tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
-				PORT_CMD_FIS_ON, 10, 1000);
-	if (tmp & PORT_CMD_FIS_ON)
-		return -EBUSY;
-
-	return 0;
-}
-
-static void ahci_power_up(struct ata_port *ap)
-{
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 cmd;
-
-	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
-
-	/* spin up device */
-	if (hpriv->cap & HOST_CAP_SSS) {
-		cmd |= PORT_CMD_SPIN_UP;
-		writel(cmd, port_mmio + PORT_CMD);
-	}
-
-	/* wake up link */
-	writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
-}
-
-static void ahci_disable_alpm(struct ata_port *ap)
-{
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 cmd;
-	struct ahci_port_priv *pp = ap->private_data;
-
-	/* IPM bits should be disabled by libata-core */
-	/* get the existing command bits */
-	cmd = readl(port_mmio + PORT_CMD);
-
-	/* disable ALPM and ASP */
-	cmd &= ~PORT_CMD_ASP;
-	cmd &= ~PORT_CMD_ALPE;
-
-	/* force the interface back to active */
-	cmd |= PORT_CMD_ICC_ACTIVE;
-
-	/* write out new cmd value */
-	writel(cmd, port_mmio + PORT_CMD);
-	cmd = readl(port_mmio + PORT_CMD);
-
-	/* wait 10ms to be sure we've come out of any low power state */
-	msleep(10);
-
-	/* clear out any PhyRdy stuff from interrupt status */
-	writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
-
-	/* go ahead and clean out PhyRdy Change from Serror too */
-	ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
-
-	/*
- 	 * Clear flag to indicate that we should ignore all PhyRdy
- 	 * state changes
- 	 */
-	hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
-
-	/*
- 	 * Enable interrupts on Phy Ready.
- 	 */
-	pp->intr_mask |= PORT_IRQ_PHYRDY;
-	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-
-	/*
- 	 * don't change the link pm policy - we can be called
- 	 * just to turn of link pm temporarily
- 	 */
-}
-
-static int ahci_enable_alpm(struct ata_port *ap,
-	enum link_pm policy)
-{
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 cmd;
-	struct ahci_port_priv *pp = ap->private_data;
-	u32 asp;
-
-	/* Make sure the host is capable of link power management */
-	if (!(hpriv->cap & HOST_CAP_ALPM))
-		return -EINVAL;
-
-	switch (policy) {
-	case MAX_PERFORMANCE:
-	case NOT_AVAILABLE:
-		/*
- 		 * if we came here with NOT_AVAILABLE,
- 		 * it just means this is the first time we
- 		 * have tried to enable - default to max performance,
- 		 * and let the user go to lower power modes on request.
- 		 */
-		ahci_disable_alpm(ap);
-		return 0;
-	case MIN_POWER:
-		/* configure HBA to enter SLUMBER */
-		asp = PORT_CMD_ASP;
-		break;
-	case MEDIUM_POWER:
-		/* configure HBA to enter PARTIAL */
-		asp = 0;
-		break;
-	default:
-		return -EINVAL;
 	}
 
-	/*
- 	 * Disable interrupts on Phy Ready. This keeps us from
- 	 * getting woken up due to spurious phy ready interrupts
-	 * TBD - Hot plug should be done via polling now, is
-	 * that even supported?
- 	 */
-	pp->intr_mask &= ~PORT_IRQ_PHYRDY;
-	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-
-	/*
- 	 * Set a flag to indicate that we should ignore all PhyRdy
- 	 * state changes since these can happen now whenever we
- 	 * change link state
- 	 */
-	hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
-
-	/* get the existing command bits */
-	cmd = readl(port_mmio + PORT_CMD);
-
-	/*
- 	 * Set ASP based on Policy
- 	 */
-	cmd |= asp;
-
-	/*
- 	 * Setting this bit will instruct the HBA to aggressively
- 	 * enter a lower power link state when it's appropriate and
- 	 * based on the value set above for ASP
- 	 */
-	cmd |= PORT_CMD_ALPE;
-
-	/* write out new cmd value */
-	writel(cmd, port_mmio + PORT_CMD);
-	cmd = readl(port_mmio + PORT_CMD);
-
-	/* IPM bits should be set by libata-core */
-	return 0;
+	ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
+				 mask_port_map);
 }
 
-#ifdef CONFIG_PM
-static void ahci_power_down(struct ata_port *ap)
-{
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 cmd, scontrol;
-
-	if (!(hpriv->cap & HOST_CAP_SSS))
-		return;
-
-	/* put device into listen mode, first set PxSCTL.DET to 0 */
-	scontrol = readl(port_mmio + PORT_SCR_CTL);
-	scontrol &= ~0xf;
-	writel(scontrol, port_mmio + PORT_SCR_CTL);
-
-	/* then set PxCMD.SUD to 0 */
-	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
-	cmd &= ~PORT_CMD_SPIN_UP;
-	writel(cmd, port_mmio + PORT_CMD);
-}
-#endif
-
-static void ahci_start_port(struct ata_port *ap)
-{
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ata_link *link;
-	struct ahci_em_priv *emp;
-	ssize_t rc;
-	int i;
-
-	/* enable FIS reception */
-	ahci_start_fis_rx(ap);
-
-	/* enable DMA */
-	ahci_start_engine(ap);
-
-	/* turn on LEDs */
-	if (ap->flags & ATA_FLAG_EM) {
-		ata_for_each_link(link, ap, EDGE) {
-			emp = &pp->em_priv[link->pmp];
-
-			/* EM Transmit bit maybe busy during init */
-			for (i = 0; i < EM_MAX_RETRY; i++) {
-				rc = ahci_transmit_led_message(ap,
-							       emp->led_state,
-							       4);
-				if (rc == -EBUSY)
-					msleep(1);
-				else
-					break;
-			}
-		}
-	}
-
-	if (ap->flags & ATA_FLAG_SW_ACTIVITY)
-		ata_for_each_link(link, ap, EDGE)
-			ahci_init_sw_activity(link);
-
-}
-
-static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
-{
-	int rc;
-
-	/* disable DMA */
-	rc = ahci_stop_engine(ap);
-	if (rc) {
-		*emsg = "failed to stop engine";
-		return rc;
-	}
-
-	/* disable FIS reception */
-	rc = ahci_stop_fis_rx(ap);
-	if (rc) {
-		*emsg = "failed stop FIS RX";
-		return rc;
-	}
-
-	return 0;
-}
-
-static int ahci_reset_controller(struct ata_host *host)
+static int ahci_pci_reset_controller(struct ata_host *host)
 {
 	struct pci_dev *pdev = to_pci_dev(host->dev);
-	struct ahci_host_priv *hpriv = host->private_data;
-	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-	u32 tmp;
-
-	/* we must be in AHCI mode, before using anything
-	 * AHCI-specific, such as HOST_RESET.
-	 */
-	ahci_enable_ahci(mmio);
-
-	/* global controller reset */
-	if (!ahci_skip_host_reset) {
-		tmp = readl(mmio + HOST_CTL);
-		if ((tmp & HOST_RESET) == 0) {
-			writel(tmp | HOST_RESET, mmio + HOST_CTL);
-			readl(mmio + HOST_CTL); /* flush */
-		}
-
-		/*
-		 * to perform host reset, OS should set HOST_RESET
-		 * and poll until this bit is read to be "0".
-		 * reset must complete within 1 second, or
-		 * the hardware should be considered fried.
-		 */
-		tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
-					HOST_RESET, 10, 1000);
-
-		if (tmp & HOST_RESET) {
-			dev_printk(KERN_ERR, host->dev,
-				   "controller reset failed (0x%x)\n", tmp);
-			return -EIO;
-		}
-
-		/* turn on AHCI mode */
-		ahci_enable_ahci(mmio);
 
-		/* Some registers might be cleared on reset.  Restore
-		 * initial values.
-		 */
-		ahci_restore_initial_config(host);
-	} else
-		dev_printk(KERN_INFO, host->dev,
-			   "skipping global host reset\n");
+	ahci_reset_controller(host);
 
 	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
+		struct ahci_host_priv *hpriv = host->private_data;
 		u16 tmp16;
 
 		/* configure PCS */
@@ -1247,267 +401,10 @@ static int ahci_reset_controller(struct ata_host *host)
 	return 0;
 }
 
-static void ahci_sw_activity(struct ata_link *link)
-{
-	struct ata_port *ap = link->ap;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-
-	if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
-		return;
-
-	emp->activity++;
-	if (!timer_pending(&emp->timer))
-		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
-}
-
-static void ahci_sw_activity_blink(unsigned long arg)
-{
-	struct ata_link *link = (struct ata_link *)arg;
-	struct ata_port *ap = link->ap;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-	unsigned long led_message = emp->led_state;
-	u32 activity_led_state;
-	unsigned long flags;
-
-	led_message &= EM_MSG_LED_VALUE;
-	led_message |= ap->port_no | (link->pmp << 8);
-
-	/* check to see if we've had activity.  If so,
-	 * toggle state of LED and reset timer.  If not,
-	 * turn LED to desired idle state.
-	 */
-	spin_lock_irqsave(ap->lock, flags);
-	if (emp->saved_activity != emp->activity) {
-		emp->saved_activity = emp->activity;
-		/* get the current LED state */
-		activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
-
-		if (activity_led_state)
-			activity_led_state = 0;
-		else
-			activity_led_state = 1;
-
-		/* clear old state */
-		led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
-
-		/* toggle state */
-		led_message |= (activity_led_state << 16);
-		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
-	} else {
-		/* switch to idle */
-		led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
-		if (emp->blink_policy == BLINK_OFF)
-			led_message |= (1 << 16);
-	}
-	spin_unlock_irqrestore(ap->lock, flags);
-	ahci_transmit_led_message(ap, led_message, 4);
-}
-
-static void ahci_init_sw_activity(struct ata_link *link)
-{
-	struct ata_port *ap = link->ap;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-
-	/* init activity stats, setup timer */
-	emp->saved_activity = emp->activity = 0;
-	setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
-
-	/* check our blink policy and set flag for link if it's enabled */
-	if (emp->blink_policy)
-		link->flags |= ATA_LFLAG_SW_ACTIVITY;
-}
-
-static int ahci_reset_em(struct ata_host *host)
-{
-	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-	u32 em_ctl;
-
-	em_ctl = readl(mmio + HOST_EM_CTL);
-	if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
-		return -EINVAL;
-
-	writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
-	return 0;
-}
-
-static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
-					ssize_t size)
-{
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	struct ahci_port_priv *pp = ap->private_data;
-	void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
-	u32 em_ctl;
-	u32 message[] = {0, 0};
-	unsigned long flags;
-	int pmp;
-	struct ahci_em_priv *emp;
-
-	/* get the slot number from the message */
-	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
-	if (pmp < EM_MAX_SLOTS)
-		emp = &pp->em_priv[pmp];
-	else
-		return -EINVAL;
-
-	spin_lock_irqsave(ap->lock, flags);
-
-	/*
-	 * if we are still busy transmitting a previous message,
-	 * do not allow
-	 */
-	em_ctl = readl(mmio + HOST_EM_CTL);
-	if (em_ctl & EM_CTL_TM) {
-		spin_unlock_irqrestore(ap->lock, flags);
-		return -EBUSY;
-	}
-
-	/*
-	 * create message header - this is all zero except for
-	 * the message size, which is 4 bytes.
-	 */
-	message[0] |= (4 << 8);
-
-	/* ignore 0:4 of byte zero, fill in port info yourself */
-	message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
-
-	/* write message to EM_LOC */
-	writel(message[0], mmio + hpriv->em_loc);
-	writel(message[1], mmio + hpriv->em_loc+4);
-
-	/* save off new led state for port/slot */
-	emp->led_state = state;
-
-	/*
-	 * tell hardware to transmit the message
-	 */
-	writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
-
-	spin_unlock_irqrestore(ap->lock, flags);
-	return size;
-}
-
-static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
-{
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ata_link *link;
-	struct ahci_em_priv *emp;
-	int rc = 0;
-
-	ata_for_each_link(link, ap, EDGE) {
-		emp = &pp->em_priv[link->pmp];
-		rc += sprintf(buf, "%lx\n", emp->led_state);
-	}
-	return rc;
-}
-
-static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
-				size_t size)
-{
-	int state;
-	int pmp;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_em_priv *emp;
-
-	state = simple_strtoul(buf, NULL, 0);
-
-	/* get the slot number from the message */
-	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
-	if (pmp < EM_MAX_SLOTS)
-		emp = &pp->em_priv[pmp];
-	else
-		return -EINVAL;
-
-	/* mask off the activity bits if we are in sw_activity
-	 * mode, user should turn off sw_activity before setting
-	 * activity led through em_message
-	 */
-	if (emp->blink_policy)
-		state &= ~EM_MSG_LED_VALUE_ACTIVITY;
-
-	return ahci_transmit_led_message(ap, state, size);
-}
-
-static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
-{
-	struct ata_link *link = dev->link;
-	struct ata_port *ap = link->ap;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-	u32 port_led_state = emp->led_state;
-
-	/* save the desired Activity LED behavior */
-	if (val == OFF) {
-		/* clear LFLAG */
-		link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
-
-		/* set the LED to OFF */
-		port_led_state &= EM_MSG_LED_VALUE_OFF;
-		port_led_state |= (ap->port_no | (link->pmp << 8));
-		ahci_transmit_led_message(ap, port_led_state, 4);
-	} else {
-		link->flags |= ATA_LFLAG_SW_ACTIVITY;
-		if (val == BLINK_OFF) {
-			/* set LED to ON for idle */
-			port_led_state &= EM_MSG_LED_VALUE_OFF;
-			port_led_state |= (ap->port_no | (link->pmp << 8));
-			port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
-			ahci_transmit_led_message(ap, port_led_state, 4);
-		}
-	}
-	emp->blink_policy = val;
-	return 0;
-}
-
-static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
-{
-	struct ata_link *link = dev->link;
-	struct ata_port *ap = link->ap;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-
-	/* display the saved value of activity behavior for this
-	 * disk.
-	 */
-	return sprintf(buf, "%d\n", emp->blink_policy);
-}
-
-static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
-			   int port_no, void __iomem *mmio,
-			   void __iomem *port_mmio)
-{
-	const char *emsg = NULL;
-	int rc;
-	u32 tmp;
-
-	/* make sure port is not active */
-	rc = ahci_deinit_port(ap, &emsg);
-	if (rc)
-		dev_printk(KERN_WARNING, &pdev->dev,
-			   "%s (%d)\n", emsg, rc);
-
-	/* clear SError */
-	tmp = readl(port_mmio + PORT_SCR_ERR);
-	VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
-	writel(tmp, port_mmio + PORT_SCR_ERR);
-
-	/* clear port IRQ */
-	tmp = readl(port_mmio + PORT_IRQ_STAT);
-	VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
-	if (tmp)
-		writel(tmp, port_mmio + PORT_IRQ_STAT);
-
-	writel(1 << port_no, mmio + HOST_IRQ_STAT);
-}
-
-static void ahci_init_controller(struct ata_host *host)
+static void ahci_pci_init_controller(struct ata_host *host)
 {
 	struct ahci_host_priv *hpriv = host->private_data;
 	struct pci_dev *pdev = to_pci_dev(host->dev);
-	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-	int i;
 	void __iomem *port_mmio;
 	u32 tmp;
 	int mv;
@@ -1528,222 +425,7 @@ static void ahci_init_controller(struct ata_host *host)
 			writel(tmp, port_mmio + PORT_IRQ_STAT);
 	}
 
-	for (i = 0; i < host->n_ports; i++) {
-		struct ata_port *ap = host->ports[i];
-
-		port_mmio = ahci_port_base(ap);
-		if (ata_port_is_dummy(ap))
-			continue;
-
-		ahci_port_init(pdev, ap, i, mmio, port_mmio);
-	}
-
-	tmp = readl(mmio + HOST_CTL);
-	VPRINTK("HOST_CTL 0x%x\n", tmp);
-	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
-	tmp = readl(mmio + HOST_CTL);
-	VPRINTK("HOST_CTL 0x%x\n", tmp);
-}
-
-static void ahci_dev_config(struct ata_device *dev)
-{
-	struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
-
-	if (hpriv->flags & AHCI_HFLAG_SECT255) {
-		dev->max_sectors = 255;
-		ata_dev_printk(dev, KERN_INFO,
-			       "SB600 AHCI: limiting to 255 sectors per cmd\n");
-	}
-}
-
-static unsigned int ahci_dev_classify(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	struct ata_taskfile tf;
-	u32 tmp;
-
-	tmp = readl(port_mmio + PORT_SIG);
-	tf.lbah		= (tmp >> 24)	& 0xff;
-	tf.lbam		= (tmp >> 16)	& 0xff;
-	tf.lbal		= (tmp >> 8)	& 0xff;
-	tf.nsect	= (tmp)		& 0xff;
-
-	return ata_dev_classify(&tf);
-}
-
-static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
-			       u32 opts)
-{
-	dma_addr_t cmd_tbl_dma;
-
-	cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
-
-	pp->cmd_slot[tag].opts = cpu_to_le32(opts);
-	pp->cmd_slot[tag].status = 0;
-	pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
-	pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
-}
-
-static int ahci_kick_engine(struct ata_port *ap, int force_restart)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
-	u32 tmp;
-	int busy, rc;
-
-	/* do we need to kick the port? */
-	busy = status & (ATA_BUSY | ATA_DRQ);
-	if (!busy && !force_restart)
-		return 0;
-
-	/* stop engine */
-	rc = ahci_stop_engine(ap);
-	if (rc)
-		goto out_restart;
-
-	/* need to do CLO? */
-	if (!busy) {
-		rc = 0;
-		goto out_restart;
-	}
-
-	if (!(hpriv->cap & HOST_CAP_CLO)) {
-		rc = -EOPNOTSUPP;
-		goto out_restart;
-	}
-
-	/* perform CLO */
-	tmp = readl(port_mmio + PORT_CMD);
-	tmp |= PORT_CMD_CLO;
-	writel(tmp, port_mmio + PORT_CMD);
-
-	rc = 0;
-	tmp = ata_wait_register(port_mmio + PORT_CMD,
-				PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
-	if (tmp & PORT_CMD_CLO)
-		rc = -EIO;
-
-	/* restart engine */
- out_restart:
-	ahci_start_engine(ap);
-	return rc;
-}
-
-static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
-				struct ata_taskfile *tf, int is_cmd, u16 flags,
-				unsigned long timeout_msec)
-{
-	const u32 cmd_fis_len = 5; /* five dwords */
-	struct ahci_port_priv *pp = ap->private_data;
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u8 *fis = pp->cmd_tbl;
-	u32 tmp;
-
-	/* prep the command */
-	ata_tf_to_fis(tf, pmp, is_cmd, fis);
-	ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
-
-	/* issue & wait */
-	writel(1, port_mmio + PORT_CMD_ISSUE);
-
-	if (timeout_msec) {
-		tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
-					1, timeout_msec);
-		if (tmp & 0x1) {
-			ahci_kick_engine(ap, 1);
-			return -EBUSY;
-		}
-	} else
-		readl(port_mmio + PORT_CMD_ISSUE);	/* flush */
-
-	return 0;
-}
-
-static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
-			     int pmp, unsigned long deadline,
-			     int (*check_ready)(struct ata_link *link))
-{
-	struct ata_port *ap = link->ap;
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	const char *reason = NULL;
-	unsigned long now, msecs;
-	struct ata_taskfile tf;
-	int rc;
-
-	DPRINTK("ENTER\n");
-
-	/* prepare for SRST (AHCI-1.1 10.4.1) */
-	rc = ahci_kick_engine(ap, 1);
-	if (rc && rc != -EOPNOTSUPP)
-		ata_link_printk(link, KERN_WARNING,
-				"failed to reset engine (errno=%d)\n", rc);
-
-	ata_tf_init(link->device, &tf);
-
-	/* issue the first D2H Register FIS */
-	msecs = 0;
-	now = jiffies;
-	if (time_after(now, deadline))
-		msecs = jiffies_to_msecs(deadline - now);
-
-	tf.ctl |= ATA_SRST;
-	if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
-				 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
-		rc = -EIO;
-		reason = "1st FIS failed";
-		goto fail;
-	}
-
-	/* spec says at least 5us, but be generous and sleep for 1ms */
-	msleep(1);
-
-	/* issue the second D2H Register FIS */
-	tf.ctl &= ~ATA_SRST;
-	ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
-
-	/* wait for link to become ready */
-	rc = ata_wait_after_reset(link, deadline, check_ready);
-	if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
-		/*
-		 * Workaround for cases where link online status can't
-		 * be trusted.  Treat device readiness timeout as link
-		 * offline.
-		 */
-		ata_link_printk(link, KERN_INFO,
-				"device not ready, treating as offline\n");
-		*class = ATA_DEV_NONE;
-	} else if (rc) {
-		/* link occupied, -ENODEV too is an error */
-		reason = "device not ready";
-		goto fail;
-	} else
-		*class = ahci_dev_classify(ap);
-
-	DPRINTK("EXIT, class=%u\n", *class);
-	return 0;
-
- fail:
-	ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
-	return rc;
-}
-
-static int ahci_check_ready(struct ata_link *link)
-{
-	void __iomem *port_mmio = ahci_port_base(link->ap);
-	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
-
-	return ata_check_ready(status);
-}
-
-static int ahci_softreset(struct ata_link *link, unsigned int *class,
-			  unsigned long deadline)
-{
-	int pmp = sata_srst_pmp(link);
-
-	DPRINTK("ENTER\n");
-
-	return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
+	ahci_init_controller(host);
 }
 
 static int ahci_sb600_check_ready(struct ata_link *link)
@@ -1795,38 +477,6 @@ static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
 	return rc;
 }
 
-static int ahci_hardreset(struct ata_link *link, unsigned int *class,
-			  unsigned long deadline)
-{
-	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
-	struct ata_port *ap = link->ap;
-	struct ahci_port_priv *pp = ap->private_data;
-	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
-	struct ata_taskfile tf;
-	bool online;
-	int rc;
-
-	DPRINTK("ENTER\n");
-
-	ahci_stop_engine(ap);
-
-	/* clear D2H reception area to properly wait for D2H FIS */
-	ata_tf_init(link->device, &tf);
-	tf.command = 0x80;
-	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
-
-	rc = sata_link_hardreset(link, timing, deadline, &online,
-				 ahci_check_ready);
-
-	ahci_start_engine(ap);
-
-	if (online)
-		*class = ahci_dev_classify(ap);
-
-	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
-	return rc;
-}
-
 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 				 unsigned long deadline)
 {
@@ -1890,453 +540,17 @@ static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 		rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
 					  ahci_check_ready);
 		if (rc)
-			ahci_kick_engine(ap, 0);
+			ahci_kick_engine(ap);
 	}
 	return rc;
 }
 
-static void ahci_postreset(struct ata_link *link, unsigned int *class)
-{
-	struct ata_port *ap = link->ap;
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 new_tmp, tmp;
-
-	ata_std_postreset(link, class);
-
-	/* Make sure port's ATAPI bit is set appropriately */
-	new_tmp = tmp = readl(port_mmio + PORT_CMD);
-	if (*class == ATA_DEV_ATAPI)
-		new_tmp |= PORT_CMD_ATAPI;
-	else
-		new_tmp &= ~PORT_CMD_ATAPI;
-	if (new_tmp != tmp) {
-		writel(new_tmp, port_mmio + PORT_CMD);
-		readl(port_mmio + PORT_CMD); /* flush */
-	}
-}
-
-static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
-{
-	struct scatterlist *sg;
-	struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
-	unsigned int si;
-
-	VPRINTK("ENTER\n");
-
-	/*
-	 * Next, the S/G list.
-	 */
-	for_each_sg(qc->sg, sg, qc->n_elem, si) {
-		dma_addr_t addr = sg_dma_address(sg);
-		u32 sg_len = sg_dma_len(sg);
-
-		ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
-		ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
-		ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
-	}
-
-	return si;
-}
-
-static void ahci_qc_prep(struct ata_queued_cmd *qc)
-{
-	struct ata_port *ap = qc->ap;
-	struct ahci_port_priv *pp = ap->private_data;
-	int is_atapi = ata_is_atapi(qc->tf.protocol);
-	void *cmd_tbl;
-	u32 opts;
-	const u32 cmd_fis_len = 5; /* five dwords */
-	unsigned int n_elem;
-
-	/*
-	 * Fill in command table information.  First, the header,
-	 * a SATA Register - Host to Device command FIS.
-	 */
-	cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
-
-	ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
-	if (is_atapi) {
-		memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
-		memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
-	}
-
-	n_elem = 0;
-	if (qc->flags & ATA_QCFLAG_DMAMAP)
-		n_elem = ahci_fill_sg(qc, cmd_tbl);
-
-	/*
-	 * Fill in command slot information.
-	 */
-	opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
-	if (qc->tf.flags & ATA_TFLAG_WRITE)
-		opts |= AHCI_CMD_WRITE;
-	if (is_atapi)
-		opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
-
-	ahci_fill_cmd_slot(pp, qc->tag, opts);
-}
-
-static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
-{
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ata_eh_info *host_ehi = &ap->link.eh_info;
-	struct ata_link *link = NULL;
-	struct ata_queued_cmd *active_qc;
-	struct ata_eh_info *active_ehi;
-	u32 serror;
-
-	/* determine active link */
-	ata_for_each_link(link, ap, EDGE)
-		if (ata_link_active(link))
-			break;
-	if (!link)
-		link = &ap->link;
-
-	active_qc = ata_qc_from_tag(ap, link->active_tag);
-	active_ehi = &link->eh_info;
-
-	/* record irq stat */
-	ata_ehi_clear_desc(host_ehi);
-	ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
-
-	/* AHCI needs SError cleared; otherwise, it might lock up */
-	ahci_scr_read(&ap->link, SCR_ERROR, &serror);
-	ahci_scr_write(&ap->link, SCR_ERROR, serror);
-	host_ehi->serror |= serror;
-
-	/* some controllers set IRQ_IF_ERR on device errors, ignore it */
-	if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
-		irq_stat &= ~PORT_IRQ_IF_ERR;
-
-	if (irq_stat & PORT_IRQ_TF_ERR) {
-		/* If qc is active, charge it; otherwise, the active
-		 * link.  There's no active qc on NCQ errors.  It will
-		 * be determined by EH by reading log page 10h.
-		 */
-		if (active_qc)
-			active_qc->err_mask |= AC_ERR_DEV;
-		else
-			active_ehi->err_mask |= AC_ERR_DEV;
-
-		if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
-			host_ehi->serror &= ~SERR_INTERNAL;
-	}
-
-	if (irq_stat & PORT_IRQ_UNK_FIS) {
-		u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
-
-		active_ehi->err_mask |= AC_ERR_HSM;
-		active_ehi->action |= ATA_EH_RESET;
-		ata_ehi_push_desc(active_ehi,
-				  "unknown FIS %08x %08x %08x %08x" ,
-				  unk[0], unk[1], unk[2], unk[3]);
-	}
-
-	if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
-		active_ehi->err_mask |= AC_ERR_HSM;
-		active_ehi->action |= ATA_EH_RESET;
-		ata_ehi_push_desc(active_ehi, "incorrect PMP");
-	}
-
-	if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
-		host_ehi->err_mask |= AC_ERR_HOST_BUS;
-		host_ehi->action |= ATA_EH_RESET;
-		ata_ehi_push_desc(host_ehi, "host bus error");
-	}
-
-	if (irq_stat & PORT_IRQ_IF_ERR) {
-		host_ehi->err_mask |= AC_ERR_ATA_BUS;
-		host_ehi->action |= ATA_EH_RESET;
-		ata_ehi_push_desc(host_ehi, "interface fatal error");
-	}
-
-	if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
-		ata_ehi_hotplugged(host_ehi);
-		ata_ehi_push_desc(host_ehi, "%s",
-			irq_stat & PORT_IRQ_CONNECT ?
-			"connection status changed" : "PHY RDY changed");
-	}
-
-	/* okay, let's hand over to EH */
-
-	if (irq_stat & PORT_IRQ_FREEZE)
-		ata_port_freeze(ap);
-	else
-		ata_port_abort(ap);
-}
-
-static void ahci_port_intr(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	struct ata_eh_info *ehi = &ap->link.eh_info;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
-	u32 status, qc_active;
-	int rc;
-
-	status = readl(port_mmio + PORT_IRQ_STAT);
-	writel(status, port_mmio + PORT_IRQ_STAT);
-
-	/* ignore BAD_PMP while resetting */
-	if (unlikely(resetting))
-		status &= ~PORT_IRQ_BAD_PMP;
-
-	/* If we are getting PhyRdy, this is
- 	 * just a power state change, we should
- 	 * clear out this, plus the PhyRdy/Comm
- 	 * Wake bits from Serror
- 	 */
-	if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
-		(status & PORT_IRQ_PHYRDY)) {
-		status &= ~PORT_IRQ_PHYRDY;
-		ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
-	}
-
-	if (unlikely(status & PORT_IRQ_ERROR)) {
-		ahci_error_intr(ap, status);
-		return;
-	}
-
-	if (status & PORT_IRQ_SDB_FIS) {
-		/* If SNotification is available, leave notification
-		 * handling to sata_async_notification().  If not,
-		 * emulate it by snooping SDB FIS RX area.
-		 *
-		 * Snooping FIS RX area is probably cheaper than
-		 * poking SNotification but some constrollers which
-		 * implement SNotification, ICH9 for example, don't
-		 * store AN SDB FIS into receive area.
-		 */
-		if (hpriv->cap & HOST_CAP_SNTF)
-			sata_async_notification(ap);
-		else {
-			/* If the 'N' bit in word 0 of the FIS is set,
-			 * we just received asynchronous notification.
-			 * Tell libata about it.
-			 */
-			const __le32 *f = pp->rx_fis + RX_FIS_SDB;
-			u32 f0 = le32_to_cpu(f[0]);
-
-			if (f0 & (1 << 15))
-				sata_async_notification(ap);
-		}
-	}
-
-	/* pp->active_link is valid iff any command is in flight */
-	if (ap->qc_active && pp->active_link->sactive)
-		qc_active = readl(port_mmio + PORT_SCR_ACT);
-	else
-		qc_active = readl(port_mmio + PORT_CMD_ISSUE);
-
-	rc = ata_qc_complete_multiple(ap, qc_active);
-
-	/* while resetting, invalid completions are expected */
-	if (unlikely(rc < 0 && !resetting)) {
-		ehi->err_mask |= AC_ERR_HSM;
-		ehi->action |= ATA_EH_RESET;
-		ata_port_freeze(ap);
-	}
-}
-
-static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
-{
-	struct ata_host *host = dev_instance;
-	struct ahci_host_priv *hpriv;
-	unsigned int i, handled = 0;
-	void __iomem *mmio;
-	u32 irq_stat, irq_masked;
-
-	VPRINTK("ENTER\n");
-
-	hpriv = host->private_data;
-	mmio = host->iomap[AHCI_PCI_BAR];
-
-	/* sigh.  0xffffffff is a valid return from h/w */
-	irq_stat = readl(mmio + HOST_IRQ_STAT);
-	if (!irq_stat)
-		return IRQ_NONE;
-
-	irq_masked = irq_stat & hpriv->port_map;
-
-	spin_lock(&host->lock);
-
-	for (i = 0; i < host->n_ports; i++) {
-		struct ata_port *ap;
-
-		if (!(irq_masked & (1 << i)))
-			continue;
-
-		ap = host->ports[i];
-		if (ap) {
-			ahci_port_intr(ap);
-			VPRINTK("port %u\n", i);
-		} else {
-			VPRINTK("port %u (no irq)\n", i);
-			if (ata_ratelimit())
-				dev_printk(KERN_WARNING, host->dev,
-					"interrupt on disabled port %u\n", i);
-		}
-
-		handled = 1;
-	}
-
-	/* HOST_IRQ_STAT behaves as level triggered latch meaning that
-	 * it should be cleared after all the port events are cleared;
-	 * otherwise, it will raise a spurious interrupt after each
-	 * valid one.  Please read section 10.6.2 of ahci 1.1 for more
-	 * information.
-	 *
-	 * Also, use the unmasked value to clear interrupt as spurious
-	 * pending event on a dummy port might cause screaming IRQ.
-	 */
-	writel(irq_stat, mmio + HOST_IRQ_STAT);
-
-	spin_unlock(&host->lock);
-
-	VPRINTK("EXIT\n");
-
-	return IRQ_RETVAL(handled);
-}
-
-static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
-{
-	struct ata_port *ap = qc->ap;
-	void __iomem *port_mmio = ahci_port_base(ap);
-	struct ahci_port_priv *pp = ap->private_data;
-
-	/* Keep track of the currently active link.  It will be used
-	 * in completion path to determine whether NCQ phase is in
-	 * progress.
-	 */
-	pp->active_link = qc->dev->link;
-
-	if (qc->tf.protocol == ATA_PROT_NCQ)
-		writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
-	writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
-
-	ahci_sw_activity(qc->dev->link);
-
-	return 0;
-}
-
-static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
-{
-	struct ahci_port_priv *pp = qc->ap->private_data;
-	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
-
-	ata_tf_from_fis(d2h_fis, &qc->result_tf);
-	return true;
-}
-
-static void ahci_freeze(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-
-	/* turn IRQ off */
-	writel(0, port_mmio + PORT_IRQ_MASK);
-}
-
-static void ahci_thaw(struct ata_port *ap)
-{
-	void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 tmp;
-	struct ahci_port_priv *pp = ap->private_data;
-
-	/* clear IRQ */
-	tmp = readl(port_mmio + PORT_IRQ_STAT);
-	writel(tmp, port_mmio + PORT_IRQ_STAT);
-	writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
-
-	/* turn IRQ back on */
-	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-}
-
-static void ahci_error_handler(struct ata_port *ap)
-{
-	if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
-		/* restart engine */
-		ahci_stop_engine(ap);
-		ahci_start_engine(ap);
-	}
-
-	sata_pmp_error_handler(ap);
-}
-
-static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
-{
-	struct ata_port *ap = qc->ap;
-
-	/* make DMA engine forget about the failed command */
-	if (qc->flags & ATA_QCFLAG_FAILED)
-		ahci_kick_engine(ap, 1);
-}
-
-static void ahci_pmp_attach(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	struct ahci_port_priv *pp = ap->private_data;
-	u32 cmd;
-
-	cmd = readl(port_mmio + PORT_CMD);
-	cmd |= PORT_CMD_PMP;
-	writel(cmd, port_mmio + PORT_CMD);
-
-	pp->intr_mask |= PORT_IRQ_BAD_PMP;
-	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-}
-
-static void ahci_pmp_detach(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	struct ahci_port_priv *pp = ap->private_data;
-	u32 cmd;
-
-	cmd = readl(port_mmio + PORT_CMD);
-	cmd &= ~PORT_CMD_PMP;
-	writel(cmd, port_mmio + PORT_CMD);
-
-	pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
-	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-}
-
-static int ahci_port_resume(struct ata_port *ap)
-{
-	ahci_power_up(ap);
-	ahci_start_port(ap);
-
-	if (sata_pmp_attached(ap))
-		ahci_pmp_attach(ap);
-	else
-		ahci_pmp_detach(ap);
-
-	return 0;
-}
-
 #ifdef CONFIG_PM
-static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
-{
-	const char *emsg = NULL;
-	int rc;
-
-	rc = ahci_deinit_port(ap, &emsg);
-	if (rc == 0)
-		ahci_power_down(ap);
-	else {
-		ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
-		ahci_start_port(ap);
-	}
-
-	return rc;
-}
-
 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 {
 	struct ata_host *host = dev_get_drvdata(&pdev->dev);
 	struct ahci_host_priv *hpriv = host->private_data;
-	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
+	void __iomem *mmio = hpriv->mmio;
 	u32 ctl;
 
 	if (mesg.event & PM_EVENT_SUSPEND &&
@@ -2370,11 +584,11 @@ static int ahci_pci_device_resume(struct pci_dev *pdev)
 		return rc;
 
 	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
-		rc = ahci_reset_controller(host);
+		rc = ahci_pci_reset_controller(host);
 		if (rc)
 			return rc;
 
-		ahci_init_controller(host);
+		ahci_pci_init_controller(host);
 	}
 
 	ata_host_resume(host);
@@ -2383,72 +597,6 @@ static int ahci_pci_device_resume(struct pci_dev *pdev)
 }
 #endif
 
-static int ahci_port_start(struct ata_port *ap)
-{
-	struct device *dev = ap->host->dev;
-	struct ahci_port_priv *pp;
-	void *mem;
-	dma_addr_t mem_dma;
-
-	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
-	if (!pp)
-		return -ENOMEM;
-
-	mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
-				  GFP_KERNEL);
-	if (!mem)
-		return -ENOMEM;
-	memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
-
-	/*
-	 * First item in chunk of DMA memory: 32-slot command table,
-	 * 32 bytes each in size
-	 */
-	pp->cmd_slot = mem;
-	pp->cmd_slot_dma = mem_dma;
-
-	mem += AHCI_CMD_SLOT_SZ;
-	mem_dma += AHCI_CMD_SLOT_SZ;
-
-	/*
-	 * Second item: Received-FIS area
-	 */
-	pp->rx_fis = mem;
-	pp->rx_fis_dma = mem_dma;
-
-	mem += AHCI_RX_FIS_SZ;
-	mem_dma += AHCI_RX_FIS_SZ;
-
-	/*
-	 * Third item: data area for storing a single command
-	 * and its scatter-gather table
-	 */
-	pp->cmd_tbl = mem;
-	pp->cmd_tbl_dma = mem_dma;
-
-	/*
-	 * Save off initial list of interrupts to be enabled.
-	 * This could be changed later
-	 */
-	pp->intr_mask = DEF_PORT_IRQ;
-
-	ap->private_data = pp;
-
-	/* engage engines, captain */
-	return ahci_port_resume(ap);
-}
-
-static void ahci_port_stop(struct ata_port *ap)
-{
-	const char *emsg = NULL;
-	int rc;
-
-	/* de-initialize port */
-	rc = ahci_deinit_port(ap, &emsg);
-	if (rc)
-		ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
-}
-
 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 {
 	int rc;
@@ -2481,30 +629,12 @@ static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 	return 0;
 }
 
-static void ahci_print_info(struct ata_host *host)
+static void ahci_pci_print_info(struct ata_host *host)
 {
-	struct ahci_host_priv *hpriv = host->private_data;
 	struct pci_dev *pdev = to_pci_dev(host->dev);
-	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-	u32 vers, cap, impl, speed;
-	const char *speed_s;
 	u16 cc;
 	const char *scc_s;
 
-	vers = readl(mmio + HOST_VERSION);
-	cap = hpriv->cap;
-	impl = hpriv->port_map;
-
-	speed = (cap >> 20) & 0xf;
-	if (speed == 1)
-		speed_s = "1.5";
-	else if (speed == 2)
-		speed_s = "3";
-	else if (speed == 3)
-		speed_s = "6";
-	else
-		speed_s = "?";
-
 	pci_read_config_word(pdev, 0x0a, &cc);
 	if (cc == PCI_CLASS_STORAGE_IDE)
 		scc_s = "IDE";
@@ -2515,46 +645,7 @@ static void ahci_print_info(struct ata_host *host)
 	else
 		scc_s = "unknown";
 
-	dev_printk(KERN_INFO, &pdev->dev,
-		"AHCI %02x%02x.%02x%02x "
-		"%u slots %u ports %s Gbps 0x%x impl %s mode\n"
-		,
-
-		(vers >> 24) & 0xff,
-		(vers >> 16) & 0xff,
-		(vers >> 8) & 0xff,
-		vers & 0xff,
-
-		((cap >> 8) & 0x1f) + 1,
-		(cap & 0x1f) + 1,
-		speed_s,
-		impl,
-		scc_s);
-
-	dev_printk(KERN_INFO, &pdev->dev,
-		"flags: "
-		"%s%s%s%s%s%s%s"
-		"%s%s%s%s%s%s%s"
-		"%s\n"
-		,
-
-		cap & (1 << 31) ? "64bit " : "",
-		cap & (1 << 30) ? "ncq " : "",
-		cap & (1 << 29) ? "sntf " : "",
-		cap & (1 << 28) ? "ilck " : "",
-		cap & (1 << 27) ? "stag " : "",
-		cap & (1 << 26) ? "pm " : "",
-		cap & (1 << 25) ? "led " : "",
-
-		cap & (1 << 24) ? "clo " : "",
-		cap & (1 << 19) ? "nz " : "",
-		cap & (1 << 18) ? "only " : "",
-		cap & (1 << 17) ? "pmp " : "",
-		cap & (1 << 15) ? "pio " : "",
-		cap & (1 << 14) ? "slum " : "",
-		cap & (1 << 13) ? "part " : "",
-		cap & (1 << 6) ? "ems ": ""
-		);
+	ahci_print_info(host, scc_s);
 }
 
 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
@@ -2602,51 +693,6 @@ static void ahci_p5wdh_workaround(struct ata_host *host)
 	}
 }
 
-/*
- * SB600 ahci controller on ASUS M2A-VM can't do 64bit DMA with older
- * BIOS.  The oldest version known to be broken is 0901 and working is
- * 1501 which was released on 2007-10-26.  Force 32bit DMA on anything
- * older than 1501.  Please read bko#9412 for more info.
- */
-static bool ahci_asus_m2a_vm_32bit_only(struct pci_dev *pdev)
-{
-	static const struct dmi_system_id sysids[] = {
-		{
-			.ident = "ASUS M2A-VM",
-			.matches = {
-				DMI_MATCH(DMI_BOARD_VENDOR,
-					  "ASUSTeK Computer INC."),
-				DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
-			},
-		},
-		{ }
-	};
-	const char *cutoff_mmdd = "10/26";
-	const char *date;
-	int year;
-
-	if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
-	    !dmi_check_system(sysids))
-		return false;
-
-	/*
-	 * Argh.... both version and date are free form strings.
-	 * Let's hope they're using the same date format across
-	 * different versions.
-	 */
-	date = dmi_get_system_info(DMI_BIOS_DATE);
-	year = dmi_get_year(DMI_BIOS_DATE);
-	if (date && strlen(date) >= 10 && date[2] == '/' && date[5] == '/' &&
-	    (year > 2007 ||
-	     (year == 2007 && strncmp(date, cutoff_mmdd, 5) >= 0)))
-		return false;
-
-	dev_printk(KERN_WARNING, &pdev->dev, "ASUS M2A-VM: BIOS too old, "
-		   "forcing 32bit DMA, update BIOS\n");
-
-	return true;
-}
-
 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
 {
 	static const struct dmi_system_id broken_systems[] = {
@@ -2789,6 +835,55 @@ static bool ahci_broken_online(struct pci_dev *pdev)
 	return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
 }
 
+#ifdef CONFIG_ATA_ACPI
+static void ahci_gtf_filter_workaround(struct ata_host *host)
+{
+	static const struct dmi_system_id sysids[] = {
+		/*
+		 * Aspire 3810T issues a bunch of SATA enable commands
+		 * via _GTF including an invalid one and one which is
+		 * rejected by the device.  Among the successful ones
+		 * is FPDMA non-zero offset enable which when enabled
+		 * only on the drive side leads to NCQ command
+		 * failures.  Filter it out.
+		 */
+		{
+			.ident = "Aspire 3810T",
+			.matches = {
+				DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
+				DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
+			},
+			.driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
+		},
+		{ }
+	};
+	const struct dmi_system_id *dmi = dmi_first_match(sysids);
+	unsigned int filter;
+	int i;
+
+	if (!dmi)
+		return;
+
+	filter = (unsigned long)dmi->driver_data;
+	dev_printk(KERN_INFO, host->dev,
+		   "applying extra ACPI _GTF filter 0x%x for %s\n",
+		   filter, dmi->ident);
+
+	for (i = 0; i < host->n_ports; i++) {
+		struct ata_port *ap = host->ports[i];
+		struct ata_link *link;
+		struct ata_device *dev;
+
+		ata_for_each_link(link, ap, EDGE)
+			ata_for_each_dev(dev, link, ALL)
+				dev->gtf_filter |= filter;
+	}
+}
+#else
+static inline void ahci_gtf_filter_workaround(struct ata_host *host)
+{}
+#endif
+
 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
 	static int printed_version;
@@ -2857,40 +952,22 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
 		hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
 
-	/* apply ASUS M2A_VM quirk */
-	if (ahci_asus_m2a_vm_32bit_only(pdev))
-		hpriv->flags |= AHCI_HFLAG_32BIT_ONLY;
+	if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
+		pci_intx(pdev, 1);
 
-	if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
-		pci_enable_msi(pdev);
+	hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
 
 	/* save initial config */
-	ahci_save_initial_config(pdev, hpriv);
+	ahci_pci_save_initial_config(pdev, hpriv);
 
 	/* prepare host */
 	if (hpriv->cap & HOST_CAP_NCQ)
-		pi.flags |= ATA_FLAG_NCQ;
+		pi.flags |= ATA_FLAG_NCQ | ATA_FLAG_FPDMA_AA;
 
 	if (hpriv->cap & HOST_CAP_PMP)
 		pi.flags |= ATA_FLAG_PMP;
 
-	if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
-		u8 messages;
-		void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
-		u32 em_loc = readl(mmio + HOST_EM_LOC);
-		u32 em_ctl = readl(mmio + HOST_EM_CTL);
-
-		messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
-
-		/* we only support LED message type right now */
-		if ((messages & 0x01) && (ahci_em_messages == 1)) {
-			/* store em_loc */
-			hpriv->em_loc = ((em_loc >> 16) * 4);
-			pi.flags |= ATA_FLAG_EM;
-			if (!(em_ctl & EM_CTL_ALHD))
-				pi.flags |= ATA_FLAG_SW_ACTIVITY;
-		}
-	}
+	ahci_set_em_messages(hpriv, &pi);
 
 	if (ahci_broken_system_poweroff(pdev)) {
 		pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
@@ -2920,7 +997,6 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
 	if (!host)
 		return -ENOMEM;
-	host->iomap = pcim_iomap_table(pdev);
 	host->private_data = hpriv;
 
 	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
@@ -2954,17 +1030,20 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	/* apply workaround for ASUS P5W DH Deluxe mainboard */
 	ahci_p5wdh_workaround(host);
 
+	/* apply gtf filter quirk */
+	ahci_gtf_filter_workaround(host);
+
 	/* initialize adapter */
 	rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
 	if (rc)
 		return rc;
 
-	rc = ahci_reset_controller(host);
+	rc = ahci_pci_reset_controller(host);
 	if (rc)
 		return rc;
 
-	ahci_init_controller(host);
-	ahci_print_info(host);
+	ahci_pci_init_controller(host);
+	ahci_pci_print_info(host);
 
 	pci_set_master(pdev);
 	return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
new file mode 100644
index 000000000000..111a878d9188
--- /dev/null
+++ b/drivers/ata/ahci.h
@@ -0,0 +1,332 @@
+/*
+ *  ahci.h - Common AHCI SATA definitions and declarations
+ *
+ *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *    		    Please ALWAYS copy linux-ide@vger.kernel.org
+ *		    on emails.
+ *
+ *  Copyright 2004-2005 Red Hat, Inc.
+ *
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ * libata documentation is available via 'make {ps|pdf}docs',
+ * as Documentation/DocBook/libata.*
+ *
+ * AHCI hardware documentation:
+ * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
+ * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
+ *
+ */
+
+#ifndef _AHCI_H
+#define _AHCI_H
+
+#include <linux/libata.h>
+
+/* Enclosure Management Control */
+#define EM_CTRL_MSG_TYPE              0x000f0000
+
+/* Enclosure Management LED Message Type */
+#define EM_MSG_LED_HBA_PORT           0x0000000f
+#define EM_MSG_LED_PMP_SLOT           0x0000ff00
+#define EM_MSG_LED_VALUE              0xffff0000
+#define EM_MSG_LED_VALUE_ACTIVITY     0x00070000
+#define EM_MSG_LED_VALUE_OFF          0xfff80000
+#define EM_MSG_LED_VALUE_ON           0x00010000
+
+enum {
+	AHCI_MAX_PORTS		= 32,
+	AHCI_MAX_SG		= 168, /* hardware max is 64K */
+	AHCI_DMA_BOUNDARY	= 0xffffffff,
+	AHCI_MAX_CMDS		= 32,
+	AHCI_CMD_SZ		= 32,
+	AHCI_CMD_SLOT_SZ	= AHCI_MAX_CMDS * AHCI_CMD_SZ,
+	AHCI_RX_FIS_SZ		= 256,
+	AHCI_CMD_TBL_CDB	= 0x40,
+	AHCI_CMD_TBL_HDR_SZ	= 0x80,
+	AHCI_CMD_TBL_SZ		= AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
+	AHCI_CMD_TBL_AR_SZ	= AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
+	AHCI_PORT_PRIV_DMA_SZ	= AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
+				  AHCI_RX_FIS_SZ,
+	AHCI_PORT_PRIV_FBS_DMA_SZ	= AHCI_CMD_SLOT_SZ +
+					  AHCI_CMD_TBL_AR_SZ +
+					  (AHCI_RX_FIS_SZ * 16),
+	AHCI_IRQ_ON_SG		= (1 << 31),
+	AHCI_CMD_ATAPI		= (1 << 5),
+	AHCI_CMD_WRITE		= (1 << 6),
+	AHCI_CMD_PREFETCH	= (1 << 7),
+	AHCI_CMD_RESET		= (1 << 8),
+	AHCI_CMD_CLR_BUSY	= (1 << 10),
+
+	RX_FIS_D2H_REG		= 0x40,	/* offset of D2H Register FIS data */
+	RX_FIS_SDB		= 0x58, /* offset of SDB FIS data */
+	RX_FIS_UNK		= 0x60, /* offset of Unknown FIS data */
+
+	/* global controller registers */
+	HOST_CAP		= 0x00, /* host capabilities */
+	HOST_CTL		= 0x04, /* global host control */
+	HOST_IRQ_STAT		= 0x08, /* interrupt status */
+	HOST_PORTS_IMPL		= 0x0c, /* bitmap of implemented ports */
+	HOST_VERSION		= 0x10, /* AHCI spec. version compliancy */
+	HOST_EM_LOC		= 0x1c, /* Enclosure Management location */
+	HOST_EM_CTL		= 0x20, /* Enclosure Management Control */
+	HOST_CAP2		= 0x24, /* host capabilities, extended */
+
+	/* HOST_CTL bits */
+	HOST_RESET		= (1 << 0),  /* reset controller; self-clear */
+	HOST_IRQ_EN		= (1 << 1),  /* global IRQ enable */
+	HOST_AHCI_EN		= (1 << 31), /* AHCI enabled */
+
+	/* HOST_CAP bits */
+	HOST_CAP_SXS		= (1 << 5),  /* Supports External SATA */
+	HOST_CAP_EMS		= (1 << 6),  /* Enclosure Management support */
+	HOST_CAP_CCC		= (1 << 7),  /* Command Completion Coalescing */
+	HOST_CAP_PART		= (1 << 13), /* Partial state capable */
+	HOST_CAP_SSC		= (1 << 14), /* Slumber state capable */
+	HOST_CAP_PIO_MULTI	= (1 << 15), /* PIO multiple DRQ support */
+	HOST_CAP_FBS		= (1 << 16), /* FIS-based switching support */
+	HOST_CAP_PMP		= (1 << 17), /* Port Multiplier support */
+	HOST_CAP_ONLY		= (1 << 18), /* Supports AHCI mode only */
+	HOST_CAP_CLO		= (1 << 24), /* Command List Override support */
+	HOST_CAP_LED		= (1 << 25), /* Supports activity LED */
+	HOST_CAP_ALPM		= (1 << 26), /* Aggressive Link PM support */
+	HOST_CAP_SSS		= (1 << 27), /* Staggered Spin-up */
+	HOST_CAP_MPS		= (1 << 28), /* Mechanical presence switch */
+	HOST_CAP_SNTF		= (1 << 29), /* SNotification register */
+	HOST_CAP_NCQ		= (1 << 30), /* Native Command Queueing */
+	HOST_CAP_64		= (1 << 31), /* PCI DAC (64-bit DMA) support */
+
+	/* HOST_CAP2 bits */
+	HOST_CAP2_BOH		= (1 << 0),  /* BIOS/OS handoff supported */
+	HOST_CAP2_NVMHCI	= (1 << 1),  /* NVMHCI supported */
+	HOST_CAP2_APST		= (1 << 2),  /* Automatic partial to slumber */
+
+	/* registers for each SATA port */
+	PORT_LST_ADDR		= 0x00, /* command list DMA addr */
+	PORT_LST_ADDR_HI	= 0x04, /* command list DMA addr hi */
+	PORT_FIS_ADDR		= 0x08, /* FIS rx buf addr */
+	PORT_FIS_ADDR_HI	= 0x0c, /* FIS rx buf addr hi */
+	PORT_IRQ_STAT		= 0x10, /* interrupt status */
+	PORT_IRQ_MASK		= 0x14, /* interrupt enable/disable mask */
+	PORT_CMD		= 0x18, /* port command */
+	PORT_TFDATA		= 0x20,	/* taskfile data */
+	PORT_SIG		= 0x24,	/* device TF signature */
+	PORT_CMD_ISSUE		= 0x38, /* command issue */
+	PORT_SCR_STAT		= 0x28, /* SATA phy register: SStatus */
+	PORT_SCR_CTL		= 0x2c, /* SATA phy register: SControl */
+	PORT_SCR_ERR		= 0x30, /* SATA phy register: SError */
+	PORT_SCR_ACT		= 0x34, /* SATA phy register: SActive */
+	PORT_SCR_NTF		= 0x3c, /* SATA phy register: SNotification */
+	PORT_FBS		= 0x40, /* FIS-based Switching */
+
+	/* PORT_IRQ_{STAT,MASK} bits */
+	PORT_IRQ_COLD_PRES	= (1 << 31), /* cold presence detect */
+	PORT_IRQ_TF_ERR		= (1 << 30), /* task file error */
+	PORT_IRQ_HBUS_ERR	= (1 << 29), /* host bus fatal error */
+	PORT_IRQ_HBUS_DATA_ERR	= (1 << 28), /* host bus data error */
+	PORT_IRQ_IF_ERR		= (1 << 27), /* interface fatal error */
+	PORT_IRQ_IF_NONFATAL	= (1 << 26), /* interface non-fatal error */
+	PORT_IRQ_OVERFLOW	= (1 << 24), /* xfer exhausted available S/G */
+	PORT_IRQ_BAD_PMP	= (1 << 23), /* incorrect port multiplier */
+
+	PORT_IRQ_PHYRDY		= (1 << 22), /* PhyRdy changed */
+	PORT_IRQ_DEV_ILCK	= (1 << 7), /* device interlock */
+	PORT_IRQ_CONNECT	= (1 << 6), /* port connect change status */
+	PORT_IRQ_SG_DONE	= (1 << 5), /* descriptor processed */
+	PORT_IRQ_UNK_FIS	= (1 << 4), /* unknown FIS rx'd */
+	PORT_IRQ_SDB_FIS	= (1 << 3), /* Set Device Bits FIS rx'd */
+	PORT_IRQ_DMAS_FIS	= (1 << 2), /* DMA Setup FIS rx'd */
+	PORT_IRQ_PIOS_FIS	= (1 << 1), /* PIO Setup FIS rx'd */
+	PORT_IRQ_D2H_REG_FIS	= (1 << 0), /* D2H Register FIS rx'd */
+
+	PORT_IRQ_FREEZE		= PORT_IRQ_HBUS_ERR |
+				  PORT_IRQ_IF_ERR |
+				  PORT_IRQ_CONNECT |
+				  PORT_IRQ_PHYRDY |
+				  PORT_IRQ_UNK_FIS |
+				  PORT_IRQ_BAD_PMP,
+	PORT_IRQ_ERROR		= PORT_IRQ_FREEZE |
+				  PORT_IRQ_TF_ERR |
+				  PORT_IRQ_HBUS_DATA_ERR,
+	DEF_PORT_IRQ		= PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
+				  PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
+				  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
+
+	/* PORT_CMD bits */
+	PORT_CMD_ASP		= (1 << 27), /* Aggressive Slumber/Partial */
+	PORT_CMD_ALPE		= (1 << 26), /* Aggressive Link PM enable */
+	PORT_CMD_ATAPI		= (1 << 24), /* Device is ATAPI */
+	PORT_CMD_FBSCP		= (1 << 22), /* FBS Capable Port */
+	PORT_CMD_PMP		= (1 << 17), /* PMP attached */
+	PORT_CMD_LIST_ON	= (1 << 15), /* cmd list DMA engine running */
+	PORT_CMD_FIS_ON		= (1 << 14), /* FIS DMA engine running */
+	PORT_CMD_FIS_RX		= (1 << 4), /* Enable FIS receive DMA engine */
+	PORT_CMD_CLO		= (1 << 3), /* Command list override */
+	PORT_CMD_POWER_ON	= (1 << 2), /* Power up device */
+	PORT_CMD_SPIN_UP	= (1 << 1), /* Spin up device */
+	PORT_CMD_START		= (1 << 0), /* Enable port DMA engine */
+
+	PORT_CMD_ICC_MASK	= (0xf << 28), /* i/f ICC state mask */
+	PORT_CMD_ICC_ACTIVE	= (0x1 << 28), /* Put i/f in active state */
+	PORT_CMD_ICC_PARTIAL	= (0x2 << 28), /* Put i/f in partial state */
+	PORT_CMD_ICC_SLUMBER	= (0x6 << 28), /* Put i/f in slumber state */
+
+	PORT_FBS_DWE_OFFSET	= 16, /* FBS device with error offset */
+	PORT_FBS_ADO_OFFSET	= 12, /* FBS active dev optimization offset */
+	PORT_FBS_DEV_OFFSET	= 8,  /* FBS device to issue offset */
+	PORT_FBS_DEV_MASK	= (0xf << PORT_FBS_DEV_OFFSET),  /* FBS.DEV */
+	PORT_FBS_SDE		= (1 << 2), /* FBS single device error */
+	PORT_FBS_DEC		= (1 << 1), /* FBS device error clear */
+	PORT_FBS_EN		= (1 << 0), /* Enable FBS */
+
+	/* hpriv->flags bits */
+	AHCI_HFLAG_NO_NCQ		= (1 << 0),
+	AHCI_HFLAG_IGN_IRQ_IF_ERR	= (1 << 1), /* ignore IRQ_IF_ERR */
+	AHCI_HFLAG_IGN_SERR_INTERNAL	= (1 << 2), /* ignore SERR_INTERNAL */
+	AHCI_HFLAG_32BIT_ONLY		= (1 << 3), /* force 32bit */
+	AHCI_HFLAG_MV_PATA		= (1 << 4), /* PATA port */
+	AHCI_HFLAG_NO_MSI		= (1 << 5), /* no PCI MSI */
+	AHCI_HFLAG_NO_PMP		= (1 << 6), /* no PMP */
+	AHCI_HFLAG_NO_HOTPLUG		= (1 << 7), /* ignore PxSERR.DIAG.N */
+	AHCI_HFLAG_SECT255		= (1 << 8), /* max 255 sectors */
+	AHCI_HFLAG_YES_NCQ		= (1 << 9), /* force NCQ cap on */
+	AHCI_HFLAG_NO_SUSPEND		= (1 << 10), /* don't suspend */
+	AHCI_HFLAG_SRST_TOUT_IS_OFFLINE	= (1 << 11), /* treat SRST timeout as
+							link offline */
+	AHCI_HFLAG_NO_SNTF		= (1 << 12), /* no sntf */
+
+	/* ap->flags bits */
+
+	AHCI_FLAG_COMMON		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
+					  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
+					  ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
+					  ATA_FLAG_IPM,
+
+	ICH_MAP				= 0x90, /* ICH MAP register */
+
+	/* em constants */
+	EM_MAX_SLOTS			= 8,
+	EM_MAX_RETRY			= 5,
+
+	/* em_ctl bits */
+	EM_CTL_RST			= (1 << 9), /* Reset */
+	EM_CTL_TM			= (1 << 8), /* Transmit Message */
+	EM_CTL_ALHD			= (1 << 26), /* Activity LED */
+};
+
+struct ahci_cmd_hdr {
+	__le32			opts;
+	__le32			status;
+	__le32			tbl_addr;
+	__le32			tbl_addr_hi;
+	__le32			reserved[4];
+};
+
+struct ahci_sg {
+	__le32			addr;
+	__le32			addr_hi;
+	__le32			reserved;
+	__le32			flags_size;
+};
+
+struct ahci_em_priv {
+	enum sw_activity blink_policy;
+	struct timer_list timer;
+	unsigned long saved_activity;
+	unsigned long activity;
+	unsigned long led_state;
+};
+
+struct ahci_port_priv {
+	struct ata_link		*active_link;
+	struct ahci_cmd_hdr	*cmd_slot;
+	dma_addr_t		cmd_slot_dma;
+	void			*cmd_tbl;
+	dma_addr_t		cmd_tbl_dma;
+	void			*rx_fis;
+	dma_addr_t		rx_fis_dma;
+	/* for NCQ spurious interrupt analysis */
+	unsigned int		ncq_saw_d2h:1;
+	unsigned int		ncq_saw_dmas:1;
+	unsigned int		ncq_saw_sdb:1;
+	u32 			intr_mask;	/* interrupts to enable */
+	bool			fbs_supported;	/* set iff FBS is supported */
+	bool			fbs_enabled;	/* set iff FBS is enabled */
+	int			fbs_last_dev;	/* save FBS.DEV of last FIS */
+	/* enclosure management info per PM slot */
+	struct ahci_em_priv	em_priv[EM_MAX_SLOTS];
+};
+
+struct ahci_host_priv {
+	void __iomem *		mmio;		/* bus-independant mem map */
+	unsigned int		flags;		/* AHCI_HFLAG_* */
+	u32			cap;		/* cap to use */
+	u32			cap2;		/* cap2 to use */
+	u32			port_map;	/* port map to use */
+	u32			saved_cap;	/* saved initial cap */
+	u32			saved_cap2;	/* saved initial cap2 */
+	u32			saved_port_map;	/* saved initial port_map */
+	u32 			em_loc; /* enclosure management location */
+};
+
+extern int ahci_em_messages;
+extern int ahci_ignore_sss;
+
+extern struct scsi_host_template ahci_sht;
+extern struct ata_port_operations ahci_ops;
+
+void ahci_save_initial_config(struct device *dev,
+			      struct ahci_host_priv *hpriv,
+			      unsigned int force_port_map,
+			      unsigned int mask_port_map);
+void ahci_init_controller(struct ata_host *host);
+int ahci_reset_controller(struct ata_host *host);
+
+int ahci_do_softreset(struct ata_link *link, unsigned int *class,
+		      int pmp, unsigned long deadline,
+		      int (*check_ready)(struct ata_link *link));
+
+int ahci_stop_engine(struct ata_port *ap);
+void ahci_start_engine(struct ata_port *ap);
+int ahci_check_ready(struct ata_link *link);
+int ahci_kick_engine(struct ata_port *ap);
+void ahci_set_em_messages(struct ahci_host_priv *hpriv,
+			  struct ata_port_info *pi);
+int ahci_reset_em(struct ata_host *host);
+irqreturn_t ahci_interrupt(int irq, void *dev_instance);
+void ahci_print_info(struct ata_host *host, const char *scc_s);
+
+static inline void __iomem *__ahci_port_base(struct ata_host *host,
+					     unsigned int port_no)
+{
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+
+	return mmio + 0x100 + (port_no * 0x80);
+}
+
+static inline void __iomem *ahci_port_base(struct ata_port *ap)
+{
+	return __ahci_port_base(ap->host, ap->port_no);
+}
+
+static inline int ahci_nr_ports(u32 cap)
+{
+	return (cap & 0x1f) + 1;
+}
+
+#endif /* _AHCI_H */
diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
new file mode 100644
index 000000000000..42cdd7363fad
--- /dev/null
+++ b/drivers/ata/ahci_platform.c
@@ -0,0 +1,191 @@
+/*
+ * AHCI SATA platform driver
+ *
+ * Copyright 2004-2005  Red Hat, Inc.
+ *   Jeff Garzik <jgarzik@pobox.com>
+ * Copyright 2010  MontaVista Software, LLC.
+ *   Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/libata.h>
+#include <linux/ahci_platform.h>
+#include "ahci.h"
+
+static int __init ahci_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ahci_platform_data *pdata = dev->platform_data;
+	struct ata_port_info pi = {
+		.flags		= AHCI_FLAG_COMMON,
+		.pio_mask	= ATA_PIO4,
+		.udma_mask	= ATA_UDMA6,
+		.port_ops	= &ahci_ops,
+	};
+	const struct ata_port_info *ppi[] = { &pi, NULL };
+	struct ahci_host_priv *hpriv;
+	struct ata_host *host;
+	struct resource *mem;
+	int irq;
+	int n_ports;
+	int i;
+	int rc;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem) {
+		dev_err(dev, "no mmio space\n");
+		return -EINVAL;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq <= 0) {
+		dev_err(dev, "no irq\n");
+		return -EINVAL;
+	}
+
+	if (pdata && pdata->init) {
+		rc = pdata->init(dev);
+		if (rc)
+			return rc;
+	}
+
+	if (pdata && pdata->ata_port_info)
+		pi = *pdata->ata_port_info;
+
+	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
+	if (!hpriv) {
+		rc = -ENOMEM;
+		goto err0;
+	}
+
+	hpriv->flags |= (unsigned long)pi.private_data;
+
+	hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
+	if (!hpriv->mmio) {
+		dev_err(dev, "can't map %pR\n", mem);
+		rc = -ENOMEM;
+		goto err0;
+	}
+
+	ahci_save_initial_config(dev, hpriv,
+		pdata ? pdata->force_port_map : 0,
+		pdata ? pdata->mask_port_map  : 0);
+
+	/* prepare host */
+	if (hpriv->cap & HOST_CAP_NCQ)
+		pi.flags |= ATA_FLAG_NCQ;
+
+	if (hpriv->cap & HOST_CAP_PMP)
+		pi.flags |= ATA_FLAG_PMP;
+
+	ahci_set_em_messages(hpriv, &pi);
+
+	/* CAP.NP sometimes indicate the index of the last enabled
+	 * port, at other times, that of the last possible port, so
+	 * determining the maximum port number requires looking at
+	 * both CAP.NP and port_map.
+	 */
+	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
+
+	host = ata_host_alloc_pinfo(dev, ppi, n_ports);
+	if (!host) {
+		rc = -ENOMEM;
+		goto err0;
+	}
+
+	host->private_data = hpriv;
+
+	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
+		host->flags |= ATA_HOST_PARALLEL_SCAN;
+	else
+		printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
+
+	if (pi.flags & ATA_FLAG_EM)
+		ahci_reset_em(host);
+
+	for (i = 0; i < host->n_ports; i++) {
+		struct ata_port *ap = host->ports[i];
+
+		ata_port_desc(ap, "mmio %pR", mem);
+		ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
+
+		/* set initial link pm policy */
+		ap->pm_policy = NOT_AVAILABLE;
+
+		/* set enclosure management message type */
+		if (ap->flags & ATA_FLAG_EM)
+			ap->em_message_type = ahci_em_messages;
+
+		/* disabled/not-implemented port */
+		if (!(hpriv->port_map & (1 << i)))
+			ap->ops = &ata_dummy_port_ops;
+	}
+
+	rc = ahci_reset_controller(host);
+	if (rc)
+		goto err0;
+
+	ahci_init_controller(host);
+	ahci_print_info(host, "platform");
+
+	rc = ata_host_activate(host, irq, ahci_interrupt, IRQF_SHARED,
+			       &ahci_sht);
+	if (rc)
+		goto err0;
+
+	return 0;
+err0:
+	if (pdata && pdata->exit)
+		pdata->exit(dev);
+	return rc;
+}
+
+static int __devexit ahci_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ahci_platform_data *pdata = dev->platform_data;
+	struct ata_host *host = dev_get_drvdata(dev);
+
+	ata_host_detach(host);
+
+	if (pdata && pdata->exit)
+		pdata->exit(dev);
+
+	return 0;
+}
+
+static struct platform_driver ahci_driver = {
+	.probe = ahci_probe,
+	.remove = __devexit_p(ahci_remove),
+	.driver = {
+		.name = "ahci",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init ahci_init(void)
+{
+	return platform_driver_probe(&ahci_driver, ahci_probe);
+}
+module_init(ahci_init);
+
+static void __exit ahci_exit(void)
+{
+	platform_driver_unregister(&ahci_driver);
+}
+module_exit(ahci_exit);
+
+MODULE_DESCRIPTION("AHCI SATA platform driver");
+MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ahci");
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
new file mode 100644
index 000000000000..38e1b4e9ecf4
--- /dev/null
+++ b/drivers/ata/libahci.c
@@ -0,0 +1,2091 @@
+/*
+ *  libahci.c - Common AHCI SATA low-level routines
+ *
+ *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *    		    Please ALWAYS copy linux-ide@vger.kernel.org
+ *		    on emails.
+ *
+ *  Copyright 2004-2005 Red Hat, Inc.
+ *
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ * libata documentation is available via 'make {ps|pdf}docs',
+ * as Documentation/DocBook/libata.*
+ *
+ * AHCI hardware documentation:
+ * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
+ * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/device.h>
+#include <scsi/scsi_host.h>
+#include <scsi/scsi_cmnd.h>
+#include <linux/libata.h>
+#include "ahci.h"
+
+static int ahci_skip_host_reset;
+int ahci_ignore_sss;
+EXPORT_SYMBOL_GPL(ahci_ignore_sss);
+
+module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
+MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
+
+module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
+MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
+
+static int ahci_enable_alpm(struct ata_port *ap,
+		enum link_pm policy);
+static void ahci_disable_alpm(struct ata_port *ap);
+static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
+static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
+			      size_t size);
+static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
+					ssize_t size);
+
+
+
+static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
+static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
+static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
+static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
+static int ahci_port_start(struct ata_port *ap);
+static void ahci_port_stop(struct ata_port *ap);
+static void ahci_qc_prep(struct ata_queued_cmd *qc);
+static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
+static void ahci_freeze(struct ata_port *ap);
+static void ahci_thaw(struct ata_port *ap);
+static void ahci_enable_fbs(struct ata_port *ap);
+static void ahci_disable_fbs(struct ata_port *ap);
+static void ahci_pmp_attach(struct ata_port *ap);
+static void ahci_pmp_detach(struct ata_port *ap);
+static int ahci_softreset(struct ata_link *link, unsigned int *class,
+			  unsigned long deadline);
+static int ahci_hardreset(struct ata_link *link, unsigned int *class,
+			  unsigned long deadline);
+static void ahci_postreset(struct ata_link *link, unsigned int *class);
+static void ahci_error_handler(struct ata_port *ap);
+static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
+static int ahci_port_resume(struct ata_port *ap);
+static void ahci_dev_config(struct ata_device *dev);
+static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
+			       u32 opts);
+#ifdef CONFIG_PM
+static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
+#endif
+static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
+static ssize_t ahci_activity_store(struct ata_device *dev,
+				   enum sw_activity val);
+static void ahci_init_sw_activity(struct ata_link *link);
+
+static ssize_t ahci_show_host_caps(struct device *dev,
+				   struct device_attribute *attr, char *buf);
+static ssize_t ahci_show_host_cap2(struct device *dev,
+				   struct device_attribute *attr, char *buf);
+static ssize_t ahci_show_host_version(struct device *dev,
+				      struct device_attribute *attr, char *buf);
+static ssize_t ahci_show_port_cmd(struct device *dev,
+				  struct device_attribute *attr, char *buf);
+
+static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
+static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
+static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
+static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
+
+static struct device_attribute *ahci_shost_attrs[] = {
+	&dev_attr_link_power_management_policy,
+	&dev_attr_em_message_type,
+	&dev_attr_em_message,
+	&dev_attr_ahci_host_caps,
+	&dev_attr_ahci_host_cap2,
+	&dev_attr_ahci_host_version,
+	&dev_attr_ahci_port_cmd,
+	NULL
+};
+
+static struct device_attribute *ahci_sdev_attrs[] = {
+	&dev_attr_sw_activity,
+	&dev_attr_unload_heads,
+	NULL
+};
+
+struct scsi_host_template ahci_sht = {
+	ATA_NCQ_SHT("ahci"),
+	.can_queue		= AHCI_MAX_CMDS - 1,
+	.sg_tablesize		= AHCI_MAX_SG,
+	.dma_boundary		= AHCI_DMA_BOUNDARY,
+	.shost_attrs		= ahci_shost_attrs,
+	.sdev_attrs		= ahci_sdev_attrs,
+};
+EXPORT_SYMBOL_GPL(ahci_sht);
+
+struct ata_port_operations ahci_ops = {
+	.inherits		= &sata_pmp_port_ops,
+
+	.qc_defer		= ahci_pmp_qc_defer,
+	.qc_prep		= ahci_qc_prep,
+	.qc_issue		= ahci_qc_issue,
+	.qc_fill_rtf		= ahci_qc_fill_rtf,
+
+	.freeze			= ahci_freeze,
+	.thaw			= ahci_thaw,
+	.softreset		= ahci_softreset,
+	.hardreset		= ahci_hardreset,
+	.postreset		= ahci_postreset,
+	.pmp_softreset		= ahci_softreset,
+	.error_handler		= ahci_error_handler,
+	.post_internal_cmd	= ahci_post_internal_cmd,
+	.dev_config		= ahci_dev_config,
+
+	.scr_read		= ahci_scr_read,
+	.scr_write		= ahci_scr_write,
+	.pmp_attach		= ahci_pmp_attach,
+	.pmp_detach		= ahci_pmp_detach,
+
+	.enable_pm		= ahci_enable_alpm,
+	.disable_pm		= ahci_disable_alpm,
+	.em_show		= ahci_led_show,
+	.em_store		= ahci_led_store,
+	.sw_activity_show	= ahci_activity_show,
+	.sw_activity_store	= ahci_activity_store,
+#ifdef CONFIG_PM
+	.port_suspend		= ahci_port_suspend,
+	.port_resume		= ahci_port_resume,
+#endif
+	.port_start		= ahci_port_start,
+	.port_stop		= ahci_port_stop,
+};
+EXPORT_SYMBOL_GPL(ahci_ops);
+
+int ahci_em_messages = 1;
+EXPORT_SYMBOL_GPL(ahci_em_messages);
+module_param(ahci_em_messages, int, 0444);
+/* add other LED protocol types when they become supported */
+MODULE_PARM_DESC(ahci_em_messages,
+	"Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
+
+static void ahci_enable_ahci(void __iomem *mmio)
+{
+	int i;
+	u32 tmp;
+
+	/* turn on AHCI_EN */
+	tmp = readl(mmio + HOST_CTL);
+	if (tmp & HOST_AHCI_EN)
+		return;
+
+	/* Some controllers need AHCI_EN to be written multiple times.
+	 * Try a few times before giving up.
+	 */
+	for (i = 0; i < 5; i++) {
+		tmp |= HOST_AHCI_EN;
+		writel(tmp, mmio + HOST_CTL);
+		tmp = readl(mmio + HOST_CTL);	/* flush && sanity check */
+		if (tmp & HOST_AHCI_EN)
+			return;
+		msleep(10);
+	}
+
+	WARN_ON(1);
+}
+
+static ssize_t ahci_show_host_caps(struct device *dev,
+				   struct device_attribute *attr, char *buf)
+{
+	struct Scsi_Host *shost = class_to_shost(dev);
+	struct ata_port *ap = ata_shost_to_port(shost);
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+
+	return sprintf(buf, "%x\n", hpriv->cap);
+}
+
+static ssize_t ahci_show_host_cap2(struct device *dev,
+				   struct device_attribute *attr, char *buf)
+{
+	struct Scsi_Host *shost = class_to_shost(dev);
+	struct ata_port *ap = ata_shost_to_port(shost);
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+
+	return sprintf(buf, "%x\n", hpriv->cap2);
+}
+
+static ssize_t ahci_show_host_version(struct device *dev,
+				   struct device_attribute *attr, char *buf)
+{
+	struct Scsi_Host *shost = class_to_shost(dev);
+	struct ata_port *ap = ata_shost_to_port(shost);
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+
+	return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
+}
+
+static ssize_t ahci_show_port_cmd(struct device *dev,
+				  struct device_attribute *attr, char *buf)
+{
+	struct Scsi_Host *shost = class_to_shost(dev);
+	struct ata_port *ap = ata_shost_to_port(shost);
+	void __iomem *port_mmio = ahci_port_base(ap);
+
+	return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
+}
+
+/**
+ *	ahci_save_initial_config - Save and fixup initial config values
+ *	@dev: target AHCI device
+ *	@hpriv: host private area to store config values
+ *	@force_port_map: force port map to a specified value
+ *	@mask_port_map: mask out particular bits from port map
+ *
+ *	Some registers containing configuration info might be setup by
+ *	BIOS and might be cleared on reset.  This function saves the
+ *	initial values of those registers into @hpriv such that they
+ *	can be restored after controller reset.
+ *
+ *	If inconsistent, config values are fixed up by this function.
+ *
+ *	LOCKING:
+ *	None.
+ */
+void ahci_save_initial_config(struct device *dev,
+			      struct ahci_host_priv *hpriv,
+			      unsigned int force_port_map,
+			      unsigned int mask_port_map)
+{
+	void __iomem *mmio = hpriv->mmio;
+	u32 cap, cap2, vers, port_map;
+	int i;
+
+	/* make sure AHCI mode is enabled before accessing CAP */
+	ahci_enable_ahci(mmio);
+
+	/* Values prefixed with saved_ are written back to host after
+	 * reset.  Values without are used for driver operation.
+	 */
+	hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
+	hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
+
+	/* CAP2 register is only defined for AHCI 1.2 and later */
+	vers = readl(mmio + HOST_VERSION);
+	if ((vers >> 16) > 1 ||
+	   ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
+		hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
+	else
+		hpriv->saved_cap2 = cap2 = 0;
+
+	/* some chips have errata preventing 64bit use */
+	if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
+		dev_printk(KERN_INFO, dev,
+			   "controller can't do 64bit DMA, forcing 32bit\n");
+		cap &= ~HOST_CAP_64;
+	}
+
+	if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
+		dev_printk(KERN_INFO, dev,
+			   "controller can't do NCQ, turning off CAP_NCQ\n");
+		cap &= ~HOST_CAP_NCQ;
+	}
+
+	if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
+		dev_printk(KERN_INFO, dev,
+			   "controller can do NCQ, turning on CAP_NCQ\n");
+		cap |= HOST_CAP_NCQ;
+	}
+
+	if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
+		dev_printk(KERN_INFO, dev,
+			   "controller can't do PMP, turning off CAP_PMP\n");
+		cap &= ~HOST_CAP_PMP;
+	}
+
+	if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
+		dev_printk(KERN_INFO, dev,
+			   "controller can't do SNTF, turning off CAP_SNTF\n");
+		cap &= ~HOST_CAP_SNTF;
+	}
+
+	if (force_port_map && port_map != force_port_map) {
+		dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
+			   port_map, force_port_map);
+		port_map = force_port_map;
+	}
+
+	if (mask_port_map) {
+		dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",
+			   port_map,
+			   port_map & mask_port_map);
+		port_map &= mask_port_map;
+	}
+
+	/* cross check port_map and cap.n_ports */
+	if (port_map) {
+		int map_ports = 0;
+
+		for (i = 0; i < AHCI_MAX_PORTS; i++)
+			if (port_map & (1 << i))
+				map_ports++;
+
+		/* If PI has more ports than n_ports, whine, clear
+		 * port_map and let it be generated from n_ports.
+		 */
+		if (map_ports > ahci_nr_ports(cap)) {
+			dev_printk(KERN_WARNING, dev,
+				   "implemented port map (0x%x) contains more "
+				   "ports than nr_ports (%u), using nr_ports\n",
+				   port_map, ahci_nr_ports(cap));
+			port_map = 0;
+		}
+	}
+
+	/* fabricate port_map from cap.nr_ports */
+	if (!port_map) {
+		port_map = (1 << ahci_nr_ports(cap)) - 1;
+		dev_printk(KERN_WARNING, dev,
+			   "forcing PORTS_IMPL to 0x%x\n", port_map);
+
+		/* write the fixed up value to the PI register */
+		hpriv->saved_port_map = port_map;
+	}
+
+	/* record values to use during operation */
+	hpriv->cap = cap;
+	hpriv->cap2 = cap2;
+	hpriv->port_map = port_map;
+}
+EXPORT_SYMBOL_GPL(ahci_save_initial_config);
+
+/**
+ *	ahci_restore_initial_config - Restore initial config
+ *	@host: target ATA host
+ *
+ *	Restore initial config stored by ahci_save_initial_config().
+ *
+ *	LOCKING:
+ *	None.
+ */
+static void ahci_restore_initial_config(struct ata_host *host)
+{
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+
+	writel(hpriv->saved_cap, mmio + HOST_CAP);
+	if (hpriv->saved_cap2)
+		writel(hpriv->saved_cap2, mmio + HOST_CAP2);
+	writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
+	(void) readl(mmio + HOST_PORTS_IMPL);	/* flush */
+}
+
+static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
+{
+	static const int offset[] = {
+		[SCR_STATUS]		= PORT_SCR_STAT,
+		[SCR_CONTROL]		= PORT_SCR_CTL,
+		[SCR_ERROR]		= PORT_SCR_ERR,
+		[SCR_ACTIVE]		= PORT_SCR_ACT,
+		[SCR_NOTIFICATION]	= PORT_SCR_NTF,
+	};
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+
+	if (sc_reg < ARRAY_SIZE(offset) &&
+	    (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
+		return offset[sc_reg];
+	return 0;
+}
+
+static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
+{
+	void __iomem *port_mmio = ahci_port_base(link->ap);
+	int offset = ahci_scr_offset(link->ap, sc_reg);
+
+	if (offset) {
+		*val = readl(port_mmio + offset);
+		return 0;
+	}
+	return -EINVAL;
+}
+
+static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
+{
+	void __iomem *port_mmio = ahci_port_base(link->ap);
+	int offset = ahci_scr_offset(link->ap, sc_reg);
+
+	if (offset) {
+		writel(val, port_mmio + offset);
+		return 0;
+	}
+	return -EINVAL;
+}
+
+void ahci_start_engine(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 tmp;
+
+	/* start DMA */
+	tmp = readl(port_mmio + PORT_CMD);
+	tmp |= PORT_CMD_START;
+	writel(tmp, port_mmio + PORT_CMD);
+	readl(port_mmio + PORT_CMD); /* flush */
+}
+EXPORT_SYMBOL_GPL(ahci_start_engine);
+
+int ahci_stop_engine(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 tmp;
+
+	tmp = readl(port_mmio + PORT_CMD);
+
+	/* check if the HBA is idle */
+	if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
+		return 0;
+
+	/* setting HBA to idle */
+	tmp &= ~PORT_CMD_START;
+	writel(tmp, port_mmio + PORT_CMD);
+
+	/* wait for engine to stop. This could be as long as 500 msec */
+	tmp = ata_wait_register(port_mmio + PORT_CMD,
+				PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
+	if (tmp & PORT_CMD_LIST_ON)
+		return -EIO;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(ahci_stop_engine);
+
+static void ahci_start_fis_rx(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	struct ahci_port_priv *pp = ap->private_data;
+	u32 tmp;
+
+	/* set FIS registers */
+	if (hpriv->cap & HOST_CAP_64)
+		writel((pp->cmd_slot_dma >> 16) >> 16,
+		       port_mmio + PORT_LST_ADDR_HI);
+	writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
+
+	if (hpriv->cap & HOST_CAP_64)
+		writel((pp->rx_fis_dma >> 16) >> 16,
+		       port_mmio + PORT_FIS_ADDR_HI);
+	writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
+
+	/* enable FIS reception */
+	tmp = readl(port_mmio + PORT_CMD);
+	tmp |= PORT_CMD_FIS_RX;
+	writel(tmp, port_mmio + PORT_CMD);
+
+	/* flush */
+	readl(port_mmio + PORT_CMD);
+}
+
+static int ahci_stop_fis_rx(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 tmp;
+
+	/* disable FIS reception */
+	tmp = readl(port_mmio + PORT_CMD);
+	tmp &= ~PORT_CMD_FIS_RX;
+	writel(tmp, port_mmio + PORT_CMD);
+
+	/* wait for completion, spec says 500ms, give it 1000 */
+	tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
+				PORT_CMD_FIS_ON, 10, 1000);
+	if (tmp & PORT_CMD_FIS_ON)
+		return -EBUSY;
+
+	return 0;
+}
+
+static void ahci_power_up(struct ata_port *ap)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 cmd;
+
+	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
+
+	/* spin up device */
+	if (hpriv->cap & HOST_CAP_SSS) {
+		cmd |= PORT_CMD_SPIN_UP;
+		writel(cmd, port_mmio + PORT_CMD);
+	}
+
+	/* wake up link */
+	writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
+}
+
+static void ahci_disable_alpm(struct ata_port *ap)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 cmd;
+	struct ahci_port_priv *pp = ap->private_data;
+
+	/* IPM bits should be disabled by libata-core */
+	/* get the existing command bits */
+	cmd = readl(port_mmio + PORT_CMD);
+
+	/* disable ALPM and ASP */
+	cmd &= ~PORT_CMD_ASP;
+	cmd &= ~PORT_CMD_ALPE;
+
+	/* force the interface back to active */
+	cmd |= PORT_CMD_ICC_ACTIVE;
+
+	/* write out new cmd value */
+	writel(cmd, port_mmio + PORT_CMD);
+	cmd = readl(port_mmio + PORT_CMD);
+
+	/* wait 10ms to be sure we've come out of any low power state */
+	msleep(10);
+
+	/* clear out any PhyRdy stuff from interrupt status */
+	writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
+
+	/* go ahead and clean out PhyRdy Change from Serror too */
+	ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
+
+	/*
+	 * Clear flag to indicate that we should ignore all PhyRdy
+	 * state changes
+	 */
+	hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
+
+	/*
+	 * Enable interrupts on Phy Ready.
+	 */
+	pp->intr_mask |= PORT_IRQ_PHYRDY;
+	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+
+	/*
+	 * don't change the link pm policy - we can be called
+	 * just to turn of link pm temporarily
+	 */
+}
+
+static int ahci_enable_alpm(struct ata_port *ap,
+	enum link_pm policy)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 cmd;
+	struct ahci_port_priv *pp = ap->private_data;
+	u32 asp;
+
+	/* Make sure the host is capable of link power management */
+	if (!(hpriv->cap & HOST_CAP_ALPM))
+		return -EINVAL;
+
+	switch (policy) {
+	case MAX_PERFORMANCE:
+	case NOT_AVAILABLE:
+		/*
+		 * if we came here with NOT_AVAILABLE,
+		 * it just means this is the first time we
+		 * have tried to enable - default to max performance,
+		 * and let the user go to lower power modes on request.
+		 */
+		ahci_disable_alpm(ap);
+		return 0;
+	case MIN_POWER:
+		/* configure HBA to enter SLUMBER */
+		asp = PORT_CMD_ASP;
+		break;
+	case MEDIUM_POWER:
+		/* configure HBA to enter PARTIAL */
+		asp = 0;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/*
+	 * Disable interrupts on Phy Ready. This keeps us from
+	 * getting woken up due to spurious phy ready interrupts
+	 * TBD - Hot plug should be done via polling now, is
+	 * that even supported?
+	 */
+	pp->intr_mask &= ~PORT_IRQ_PHYRDY;
+	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+
+	/*
+	 * Set a flag to indicate that we should ignore all PhyRdy
+	 * state changes since these can happen now whenever we
+	 * change link state
+	 */
+	hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
+
+	/* get the existing command bits */
+	cmd = readl(port_mmio + PORT_CMD);
+
+	/*
+	 * Set ASP based on Policy
+	 */
+	cmd |= asp;
+
+	/*
+	 * Setting this bit will instruct the HBA to aggressively
+	 * enter a lower power link state when it's appropriate and
+	 * based on the value set above for ASP
+	 */
+	cmd |= PORT_CMD_ALPE;
+
+	/* write out new cmd value */
+	writel(cmd, port_mmio + PORT_CMD);
+	cmd = readl(port_mmio + PORT_CMD);
+
+	/* IPM bits should be set by libata-core */
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static void ahci_power_down(struct ata_port *ap)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 cmd, scontrol;
+
+	if (!(hpriv->cap & HOST_CAP_SSS))
+		return;
+
+	/* put device into listen mode, first set PxSCTL.DET to 0 */
+	scontrol = readl(port_mmio + PORT_SCR_CTL);
+	scontrol &= ~0xf;
+	writel(scontrol, port_mmio + PORT_SCR_CTL);
+
+	/* then set PxCMD.SUD to 0 */
+	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
+	cmd &= ~PORT_CMD_SPIN_UP;
+	writel(cmd, port_mmio + PORT_CMD);
+}
+#endif
+
+static void ahci_start_port(struct ata_port *ap)
+{
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ata_link *link;
+	struct ahci_em_priv *emp;
+	ssize_t rc;
+	int i;
+
+	/* enable FIS reception */
+	ahci_start_fis_rx(ap);
+
+	/* enable DMA */
+	ahci_start_engine(ap);
+
+	/* turn on LEDs */
+	if (ap->flags & ATA_FLAG_EM) {
+		ata_for_each_link(link, ap, EDGE) {
+			emp = &pp->em_priv[link->pmp];
+
+			/* EM Transmit bit maybe busy during init */
+			for (i = 0; i < EM_MAX_RETRY; i++) {
+				rc = ahci_transmit_led_message(ap,
+							       emp->led_state,
+							       4);
+				if (rc == -EBUSY)
+					msleep(1);
+				else
+					break;
+			}
+		}
+	}
+
+	if (ap->flags & ATA_FLAG_SW_ACTIVITY)
+		ata_for_each_link(link, ap, EDGE)
+			ahci_init_sw_activity(link);
+
+}
+
+static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
+{
+	int rc;
+
+	/* disable DMA */
+	rc = ahci_stop_engine(ap);
+	if (rc) {
+		*emsg = "failed to stop engine";
+		return rc;
+	}
+
+	/* disable FIS reception */
+	rc = ahci_stop_fis_rx(ap);
+	if (rc) {
+		*emsg = "failed stop FIS RX";
+		return rc;
+	}
+
+	return 0;
+}
+
+int ahci_reset_controller(struct ata_host *host)
+{
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+	u32 tmp;
+
+	/* we must be in AHCI mode, before using anything
+	 * AHCI-specific, such as HOST_RESET.
+	 */
+	ahci_enable_ahci(mmio);
+
+	/* global controller reset */
+	if (!ahci_skip_host_reset) {
+		tmp = readl(mmio + HOST_CTL);
+		if ((tmp & HOST_RESET) == 0) {
+			writel(tmp | HOST_RESET, mmio + HOST_CTL);
+			readl(mmio + HOST_CTL); /* flush */
+		}
+
+		/*
+		 * to perform host reset, OS should set HOST_RESET
+		 * and poll until this bit is read to be "0".
+		 * reset must complete within 1 second, or
+		 * the hardware should be considered fried.
+		 */
+		tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
+					HOST_RESET, 10, 1000);
+
+		if (tmp & HOST_RESET) {
+			dev_printk(KERN_ERR, host->dev,
+				   "controller reset failed (0x%x)\n", tmp);
+			return -EIO;
+		}
+
+		/* turn on AHCI mode */
+		ahci_enable_ahci(mmio);
+
+		/* Some registers might be cleared on reset.  Restore
+		 * initial values.
+		 */
+		ahci_restore_initial_config(host);
+	} else
+		dev_printk(KERN_INFO, host->dev,
+			   "skipping global host reset\n");
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(ahci_reset_controller);
+
+static void ahci_sw_activity(struct ata_link *link)
+{
+	struct ata_port *ap = link->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+
+	if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
+		return;
+
+	emp->activity++;
+	if (!timer_pending(&emp->timer))
+		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
+}
+
+static void ahci_sw_activity_blink(unsigned long arg)
+{
+	struct ata_link *link = (struct ata_link *)arg;
+	struct ata_port *ap = link->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+	unsigned long led_message = emp->led_state;
+	u32 activity_led_state;
+	unsigned long flags;
+
+	led_message &= EM_MSG_LED_VALUE;
+	led_message |= ap->port_no | (link->pmp << 8);
+
+	/* check to see if we've had activity.  If so,
+	 * toggle state of LED and reset timer.  If not,
+	 * turn LED to desired idle state.
+	 */
+	spin_lock_irqsave(ap->lock, flags);
+	if (emp->saved_activity != emp->activity) {
+		emp->saved_activity = emp->activity;
+		/* get the current LED state */
+		activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
+
+		if (activity_led_state)
+			activity_led_state = 0;
+		else
+			activity_led_state = 1;
+
+		/* clear old state */
+		led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
+
+		/* toggle state */
+		led_message |= (activity_led_state << 16);
+		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
+	} else {
+		/* switch to idle */
+		led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
+		if (emp->blink_policy == BLINK_OFF)
+			led_message |= (1 << 16);
+	}
+	spin_unlock_irqrestore(ap->lock, flags);
+	ahci_transmit_led_message(ap, led_message, 4);
+}
+
+static void ahci_init_sw_activity(struct ata_link *link)
+{
+	struct ata_port *ap = link->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+
+	/* init activity stats, setup timer */
+	emp->saved_activity = emp->activity = 0;
+	setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
+
+	/* check our blink policy and set flag for link if it's enabled */
+	if (emp->blink_policy)
+		link->flags |= ATA_LFLAG_SW_ACTIVITY;
+}
+
+int ahci_reset_em(struct ata_host *host)
+{
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+	u32 em_ctl;
+
+	em_ctl = readl(mmio + HOST_EM_CTL);
+	if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
+		return -EINVAL;
+
+	writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(ahci_reset_em);
+
+static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
+					ssize_t size)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	struct ahci_port_priv *pp = ap->private_data;
+	void __iomem *mmio = hpriv->mmio;
+	u32 em_ctl;
+	u32 message[] = {0, 0};
+	unsigned long flags;
+	int pmp;
+	struct ahci_em_priv *emp;
+
+	/* get the slot number from the message */
+	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
+	if (pmp < EM_MAX_SLOTS)
+		emp = &pp->em_priv[pmp];
+	else
+		return -EINVAL;
+
+	spin_lock_irqsave(ap->lock, flags);
+
+	/*
+	 * if we are still busy transmitting a previous message,
+	 * do not allow
+	 */
+	em_ctl = readl(mmio + HOST_EM_CTL);
+	if (em_ctl & EM_CTL_TM) {
+		spin_unlock_irqrestore(ap->lock, flags);
+		return -EBUSY;
+	}
+
+	/*
+	 * create message header - this is all zero except for
+	 * the message size, which is 4 bytes.
+	 */
+	message[0] |= (4 << 8);
+
+	/* ignore 0:4 of byte zero, fill in port info yourself */
+	message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
+
+	/* write message to EM_LOC */
+	writel(message[0], mmio + hpriv->em_loc);
+	writel(message[1], mmio + hpriv->em_loc+4);
+
+	/* save off new led state for port/slot */
+	emp->led_state = state;
+
+	/*
+	 * tell hardware to transmit the message
+	 */
+	writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
+
+	spin_unlock_irqrestore(ap->lock, flags);
+	return size;
+}
+
+static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
+{
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ata_link *link;
+	struct ahci_em_priv *emp;
+	int rc = 0;
+
+	ata_for_each_link(link, ap, EDGE) {
+		emp = &pp->em_priv[link->pmp];
+		rc += sprintf(buf, "%lx\n", emp->led_state);
+	}
+	return rc;
+}
+
+static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
+				size_t size)
+{
+	int state;
+	int pmp;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_em_priv *emp;
+
+	state = simple_strtoul(buf, NULL, 0);
+
+	/* get the slot number from the message */
+	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
+	if (pmp < EM_MAX_SLOTS)
+		emp = &pp->em_priv[pmp];
+	else
+		return -EINVAL;
+
+	/* mask off the activity bits if we are in sw_activity
+	 * mode, user should turn off sw_activity before setting
+	 * activity led through em_message
+	 */
+	if (emp->blink_policy)
+		state &= ~EM_MSG_LED_VALUE_ACTIVITY;
+
+	return ahci_transmit_led_message(ap, state, size);
+}
+
+static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
+{
+	struct ata_link *link = dev->link;
+	struct ata_port *ap = link->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+	u32 port_led_state = emp->led_state;
+
+	/* save the desired Activity LED behavior */
+	if (val == OFF) {
+		/* clear LFLAG */
+		link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
+
+		/* set the LED to OFF */
+		port_led_state &= EM_MSG_LED_VALUE_OFF;
+		port_led_state |= (ap->port_no | (link->pmp << 8));
+		ahci_transmit_led_message(ap, port_led_state, 4);
+	} else {
+		link->flags |= ATA_LFLAG_SW_ACTIVITY;
+		if (val == BLINK_OFF) {
+			/* set LED to ON for idle */
+			port_led_state &= EM_MSG_LED_VALUE_OFF;
+			port_led_state |= (ap->port_no | (link->pmp << 8));
+			port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
+			ahci_transmit_led_message(ap, port_led_state, 4);
+		}
+	}
+	emp->blink_policy = val;
+	return 0;
+}
+
+static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
+{
+	struct ata_link *link = dev->link;
+	struct ata_port *ap = link->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+
+	/* display the saved value of activity behavior for this
+	 * disk.
+	 */
+	return sprintf(buf, "%d\n", emp->blink_policy);
+}
+
+static void ahci_port_init(struct device *dev, struct ata_port *ap,
+			   int port_no, void __iomem *mmio,
+			   void __iomem *port_mmio)
+{
+	const char *emsg = NULL;
+	int rc;
+	u32 tmp;
+
+	/* make sure port is not active */
+	rc = ahci_deinit_port(ap, &emsg);
+	if (rc)
+		dev_warn(dev, "%s (%d)\n", emsg, rc);
+
+	/* clear SError */
+	tmp = readl(port_mmio + PORT_SCR_ERR);
+	VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
+	writel(tmp, port_mmio + PORT_SCR_ERR);
+
+	/* clear port IRQ */
+	tmp = readl(port_mmio + PORT_IRQ_STAT);
+	VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
+	if (tmp)
+		writel(tmp, port_mmio + PORT_IRQ_STAT);
+
+	writel(1 << port_no, mmio + HOST_IRQ_STAT);
+}
+
+void ahci_init_controller(struct ata_host *host)
+{
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+	int i;
+	void __iomem *port_mmio;
+	u32 tmp;
+
+	for (i = 0; i < host->n_ports; i++) {
+		struct ata_port *ap = host->ports[i];
+
+		port_mmio = ahci_port_base(ap);
+		if (ata_port_is_dummy(ap))
+			continue;
+
+		ahci_port_init(host->dev, ap, i, mmio, port_mmio);
+	}
+
+	tmp = readl(mmio + HOST_CTL);
+	VPRINTK("HOST_CTL 0x%x\n", tmp);
+	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
+	tmp = readl(mmio + HOST_CTL);
+	VPRINTK("HOST_CTL 0x%x\n", tmp);
+}
+EXPORT_SYMBOL_GPL(ahci_init_controller);
+
+static void ahci_dev_config(struct ata_device *dev)
+{
+	struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
+
+	if (hpriv->flags & AHCI_HFLAG_SECT255) {
+		dev->max_sectors = 255;
+		ata_dev_printk(dev, KERN_INFO,
+			       "SB600 AHCI: limiting to 255 sectors per cmd\n");
+	}
+}
+
+static unsigned int ahci_dev_classify(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	struct ata_taskfile tf;
+	u32 tmp;
+
+	tmp = readl(port_mmio + PORT_SIG);
+	tf.lbah		= (tmp >> 24)	& 0xff;
+	tf.lbam		= (tmp >> 16)	& 0xff;
+	tf.lbal		= (tmp >> 8)	& 0xff;
+	tf.nsect	= (tmp)		& 0xff;
+
+	return ata_dev_classify(&tf);
+}
+
+static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
+			       u32 opts)
+{
+	dma_addr_t cmd_tbl_dma;
+
+	cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
+
+	pp->cmd_slot[tag].opts = cpu_to_le32(opts);
+	pp->cmd_slot[tag].status = 0;
+	pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
+	pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
+}
+
+int ahci_kick_engine(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
+	u32 tmp;
+	int busy, rc;
+
+	/* stop engine */
+	rc = ahci_stop_engine(ap);
+	if (rc)
+		goto out_restart;
+
+	/* need to do CLO?
+	 * always do CLO if PMP is attached (AHCI-1.3 9.2)
+	 */
+	busy = status & (ATA_BUSY | ATA_DRQ);
+	if (!busy && !sata_pmp_attached(ap)) {
+		rc = 0;
+		goto out_restart;
+	}
+
+	if (!(hpriv->cap & HOST_CAP_CLO)) {
+		rc = -EOPNOTSUPP;
+		goto out_restart;
+	}
+
+	/* perform CLO */
+	tmp = readl(port_mmio + PORT_CMD);
+	tmp |= PORT_CMD_CLO;
+	writel(tmp, port_mmio + PORT_CMD);
+
+	rc = 0;
+	tmp = ata_wait_register(port_mmio + PORT_CMD,
+				PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
+	if (tmp & PORT_CMD_CLO)
+		rc = -EIO;
+
+	/* restart engine */
+ out_restart:
+	ahci_start_engine(ap);
+	return rc;
+}
+EXPORT_SYMBOL_GPL(ahci_kick_engine);
+
+static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
+				struct ata_taskfile *tf, int is_cmd, u16 flags,
+				unsigned long timeout_msec)
+{
+	const u32 cmd_fis_len = 5; /* five dwords */
+	struct ahci_port_priv *pp = ap->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u8 *fis = pp->cmd_tbl;
+	u32 tmp;
+
+	/* prep the command */
+	ata_tf_to_fis(tf, pmp, is_cmd, fis);
+	ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
+
+	/* issue & wait */
+	writel(1, port_mmio + PORT_CMD_ISSUE);
+
+	if (timeout_msec) {
+		tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
+					1, timeout_msec);
+		if (tmp & 0x1) {
+			ahci_kick_engine(ap);
+			return -EBUSY;
+		}
+	} else
+		readl(port_mmio + PORT_CMD_ISSUE);	/* flush */
+
+	return 0;
+}
+
+int ahci_do_softreset(struct ata_link *link, unsigned int *class,
+		      int pmp, unsigned long deadline,
+		      int (*check_ready)(struct ata_link *link))
+{
+	struct ata_port *ap = link->ap;
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	const char *reason = NULL;
+	unsigned long now, msecs;
+	struct ata_taskfile tf;
+	int rc;
+
+	DPRINTK("ENTER\n");
+
+	/* prepare for SRST (AHCI-1.1 10.4.1) */
+	rc = ahci_kick_engine(ap);
+	if (rc && rc != -EOPNOTSUPP)
+		ata_link_printk(link, KERN_WARNING,
+				"failed to reset engine (errno=%d)\n", rc);
+
+	ata_tf_init(link->device, &tf);
+
+	/* issue the first D2H Register FIS */
+	msecs = 0;
+	now = jiffies;
+	if (time_after(now, deadline))
+		msecs = jiffies_to_msecs(deadline - now);
+
+	tf.ctl |= ATA_SRST;
+	if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
+				 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
+		rc = -EIO;
+		reason = "1st FIS failed";
+		goto fail;
+	}
+
+	/* spec says at least 5us, but be generous and sleep for 1ms */
+	msleep(1);
+
+	/* issue the second D2H Register FIS */
+	tf.ctl &= ~ATA_SRST;
+	ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
+
+	/* wait for link to become ready */
+	rc = ata_wait_after_reset(link, deadline, check_ready);
+	if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
+		/*
+		 * Workaround for cases where link online status can't
+		 * be trusted.  Treat device readiness timeout as link
+		 * offline.
+		 */
+		ata_link_printk(link, KERN_INFO,
+				"device not ready, treating as offline\n");
+		*class = ATA_DEV_NONE;
+	} else if (rc) {
+		/* link occupied, -ENODEV too is an error */
+		reason = "device not ready";
+		goto fail;
+	} else
+		*class = ahci_dev_classify(ap);
+
+	DPRINTK("EXIT, class=%u\n", *class);
+	return 0;
+
+ fail:
+	ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
+	return rc;
+}
+
+int ahci_check_ready(struct ata_link *link)
+{
+	void __iomem *port_mmio = ahci_port_base(link->ap);
+	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
+
+	return ata_check_ready(status);
+}
+EXPORT_SYMBOL_GPL(ahci_check_ready);
+
+static int ahci_softreset(struct ata_link *link, unsigned int *class,
+			  unsigned long deadline)
+{
+	int pmp = sata_srst_pmp(link);
+
+	DPRINTK("ENTER\n");
+
+	return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
+}
+EXPORT_SYMBOL_GPL(ahci_do_softreset);
+
+static int ahci_hardreset(struct ata_link *link, unsigned int *class,
+			  unsigned long deadline)
+{
+	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
+	struct ata_port *ap = link->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
+	struct ata_taskfile tf;
+	bool online;
+	int rc;
+
+	DPRINTK("ENTER\n");
+
+	ahci_stop_engine(ap);
+
+	/* clear D2H reception area to properly wait for D2H FIS */
+	ata_tf_init(link->device, &tf);
+	tf.command = 0x80;
+	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
+
+	rc = sata_link_hardreset(link, timing, deadline, &online,
+				 ahci_check_ready);
+
+	ahci_start_engine(ap);
+
+	if (online)
+		*class = ahci_dev_classify(ap);
+
+	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
+	return rc;
+}
+
+static void ahci_postreset(struct ata_link *link, unsigned int *class)
+{
+	struct ata_port *ap = link->ap;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 new_tmp, tmp;
+
+	ata_std_postreset(link, class);
+
+	/* Make sure port's ATAPI bit is set appropriately */
+	new_tmp = tmp = readl(port_mmio + PORT_CMD);
+	if (*class == ATA_DEV_ATAPI)
+		new_tmp |= PORT_CMD_ATAPI;
+	else
+		new_tmp &= ~PORT_CMD_ATAPI;
+	if (new_tmp != tmp) {
+		writel(new_tmp, port_mmio + PORT_CMD);
+		readl(port_mmio + PORT_CMD); /* flush */
+	}
+}
+
+static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
+{
+	struct scatterlist *sg;
+	struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
+	unsigned int si;
+
+	VPRINTK("ENTER\n");
+
+	/*
+	 * Next, the S/G list.
+	 */
+	for_each_sg(qc->sg, sg, qc->n_elem, si) {
+		dma_addr_t addr = sg_dma_address(sg);
+		u32 sg_len = sg_dma_len(sg);
+
+		ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
+		ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
+		ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
+	}
+
+	return si;
+}
+
+static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
+{
+	struct ata_port *ap = qc->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+
+	if (!sata_pmp_attached(ap) || pp->fbs_enabled)
+		return ata_std_qc_defer(qc);
+	else
+		return sata_pmp_qc_defer_cmd_switch(qc);
+}
+
+static void ahci_qc_prep(struct ata_queued_cmd *qc)
+{
+	struct ata_port *ap = qc->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+	int is_atapi = ata_is_atapi(qc->tf.protocol);
+	void *cmd_tbl;
+	u32 opts;
+	const u32 cmd_fis_len = 5; /* five dwords */
+	unsigned int n_elem;
+
+	/*
+	 * Fill in command table information.  First, the header,
+	 * a SATA Register - Host to Device command FIS.
+	 */
+	cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
+
+	ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
+	if (is_atapi) {
+		memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
+		memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
+	}
+
+	n_elem = 0;
+	if (qc->flags & ATA_QCFLAG_DMAMAP)
+		n_elem = ahci_fill_sg(qc, cmd_tbl);
+
+	/*
+	 * Fill in command slot information.
+	 */
+	opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
+	if (qc->tf.flags & ATA_TFLAG_WRITE)
+		opts |= AHCI_CMD_WRITE;
+	if (is_atapi)
+		opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
+
+	ahci_fill_cmd_slot(pp, qc->tag, opts);
+}
+
+static void ahci_fbs_dec_intr(struct ata_port *ap)
+{
+	struct ahci_port_priv *pp = ap->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 fbs = readl(port_mmio + PORT_FBS);
+	int retries = 3;
+
+	DPRINTK("ENTER\n");
+	BUG_ON(!pp->fbs_enabled);
+
+	/* time to wait for DEC is not specified by AHCI spec,
+	 * add a retry loop for safety.
+	 */
+	writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
+	fbs = readl(port_mmio + PORT_FBS);
+	while ((fbs & PORT_FBS_DEC) && retries--) {
+		udelay(1);
+		fbs = readl(port_mmio + PORT_FBS);
+	}
+
+	if (fbs & PORT_FBS_DEC)
+		dev_printk(KERN_ERR, ap->host->dev,
+			   "failed to clear device error\n");
+}
+
+static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ata_eh_info *host_ehi = &ap->link.eh_info;
+	struct ata_link *link = NULL;
+	struct ata_queued_cmd *active_qc;
+	struct ata_eh_info *active_ehi;
+	bool fbs_need_dec = false;
+	u32 serror;
+
+	/* determine active link with error */
+	if (pp->fbs_enabled) {
+		void __iomem *port_mmio = ahci_port_base(ap);
+		u32 fbs = readl(port_mmio + PORT_FBS);
+		int pmp = fbs >> PORT_FBS_DWE_OFFSET;
+
+		if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
+		    ata_link_online(&ap->pmp_link[pmp])) {
+			link = &ap->pmp_link[pmp];
+			fbs_need_dec = true;
+		}
+
+	} else
+		ata_for_each_link(link, ap, EDGE)
+			if (ata_link_active(link))
+				break;
+
+	if (!link)
+		link = &ap->link;
+
+	active_qc = ata_qc_from_tag(ap, link->active_tag);
+	active_ehi = &link->eh_info;
+
+	/* record irq stat */
+	ata_ehi_clear_desc(host_ehi);
+	ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
+
+	/* AHCI needs SError cleared; otherwise, it might lock up */
+	ahci_scr_read(&ap->link, SCR_ERROR, &serror);
+	ahci_scr_write(&ap->link, SCR_ERROR, serror);
+	host_ehi->serror |= serror;
+
+	/* some controllers set IRQ_IF_ERR on device errors, ignore it */
+	if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
+		irq_stat &= ~PORT_IRQ_IF_ERR;
+
+	if (irq_stat & PORT_IRQ_TF_ERR) {
+		/* If qc is active, charge it; otherwise, the active
+		 * link.  There's no active qc on NCQ errors.  It will
+		 * be determined by EH by reading log page 10h.
+		 */
+		if (active_qc)
+			active_qc->err_mask |= AC_ERR_DEV;
+		else
+			active_ehi->err_mask |= AC_ERR_DEV;
+
+		if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
+			host_ehi->serror &= ~SERR_INTERNAL;
+	}
+
+	if (irq_stat & PORT_IRQ_UNK_FIS) {
+		u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
+
+		active_ehi->err_mask |= AC_ERR_HSM;
+		active_ehi->action |= ATA_EH_RESET;
+		ata_ehi_push_desc(active_ehi,
+				  "unknown FIS %08x %08x %08x %08x" ,
+				  unk[0], unk[1], unk[2], unk[3]);
+	}
+
+	if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
+		active_ehi->err_mask |= AC_ERR_HSM;
+		active_ehi->action |= ATA_EH_RESET;
+		ata_ehi_push_desc(active_ehi, "incorrect PMP");
+	}
+
+	if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
+		host_ehi->err_mask |= AC_ERR_HOST_BUS;
+		host_ehi->action |= ATA_EH_RESET;
+		ata_ehi_push_desc(host_ehi, "host bus error");
+	}
+
+	if (irq_stat & PORT_IRQ_IF_ERR) {
+		if (fbs_need_dec)
+			active_ehi->err_mask |= AC_ERR_DEV;
+		else {
+			host_ehi->err_mask |= AC_ERR_ATA_BUS;
+			host_ehi->action |= ATA_EH_RESET;
+		}
+
+		ata_ehi_push_desc(host_ehi, "interface fatal error");
+	}
+
+	if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
+		ata_ehi_hotplugged(host_ehi);
+		ata_ehi_push_desc(host_ehi, "%s",
+			irq_stat & PORT_IRQ_CONNECT ?
+			"connection status changed" : "PHY RDY changed");
+	}
+
+	/* okay, let's hand over to EH */
+
+	if (irq_stat & PORT_IRQ_FREEZE)
+		ata_port_freeze(ap);
+	else if (fbs_need_dec) {
+		ata_link_abort(link);
+		ahci_fbs_dec_intr(ap);
+	} else
+		ata_port_abort(ap);
+}
+
+static void ahci_port_intr(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	struct ata_eh_info *ehi = &ap->link.eh_info;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
+	u32 status, qc_active = 0;
+	int rc;
+
+	status = readl(port_mmio + PORT_IRQ_STAT);
+	writel(status, port_mmio + PORT_IRQ_STAT);
+
+	/* ignore BAD_PMP while resetting */
+	if (unlikely(resetting))
+		status &= ~PORT_IRQ_BAD_PMP;
+
+	/* If we are getting PhyRdy, this is
+	 * just a power state change, we should
+	 * clear out this, plus the PhyRdy/Comm
+	 * Wake bits from Serror
+	 */
+	if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
+		(status & PORT_IRQ_PHYRDY)) {
+		status &= ~PORT_IRQ_PHYRDY;
+		ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
+	}
+
+	if (unlikely(status & PORT_IRQ_ERROR)) {
+		ahci_error_intr(ap, status);
+		return;
+	}
+
+	if (status & PORT_IRQ_SDB_FIS) {
+		/* If SNotification is available, leave notification
+		 * handling to sata_async_notification().  If not,
+		 * emulate it by snooping SDB FIS RX area.
+		 *
+		 * Snooping FIS RX area is probably cheaper than
+		 * poking SNotification but some constrollers which
+		 * implement SNotification, ICH9 for example, don't
+		 * store AN SDB FIS into receive area.
+		 */
+		if (hpriv->cap & HOST_CAP_SNTF)
+			sata_async_notification(ap);
+		else {
+			/* If the 'N' bit in word 0 of the FIS is set,
+			 * we just received asynchronous notification.
+			 * Tell libata about it.
+			 *
+			 * Lack of SNotification should not appear in
+			 * ahci 1.2, so the workaround is unnecessary
+			 * when FBS is enabled.
+			 */
+			if (pp->fbs_enabled)
+				WARN_ON_ONCE(1);
+			else {
+				const __le32 *f = pp->rx_fis + RX_FIS_SDB;
+				u32 f0 = le32_to_cpu(f[0]);
+				if (f0 & (1 << 15))
+					sata_async_notification(ap);
+			}
+		}
+	}
+
+	/* pp->active_link is not reliable once FBS is enabled, both
+	 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
+	 * NCQ and non-NCQ commands may be in flight at the same time.
+	 */
+	if (pp->fbs_enabled) {
+		if (ap->qc_active) {
+			qc_active = readl(port_mmio + PORT_SCR_ACT);
+			qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
+		}
+	} else {
+		/* pp->active_link is valid iff any command is in flight */
+		if (ap->qc_active && pp->active_link->sactive)
+			qc_active = readl(port_mmio + PORT_SCR_ACT);
+		else
+			qc_active = readl(port_mmio + PORT_CMD_ISSUE);
+	}
+
+
+	rc = ata_qc_complete_multiple(ap, qc_active);
+
+	/* while resetting, invalid completions are expected */
+	if (unlikely(rc < 0 && !resetting)) {
+		ehi->err_mask |= AC_ERR_HSM;
+		ehi->action |= ATA_EH_RESET;
+		ata_port_freeze(ap);
+	}
+}
+
+irqreturn_t ahci_interrupt(int irq, void *dev_instance)
+{
+	struct ata_host *host = dev_instance;
+	struct ahci_host_priv *hpriv;
+	unsigned int i, handled = 0;
+	void __iomem *mmio;
+	u32 irq_stat, irq_masked;
+
+	VPRINTK("ENTER\n");
+
+	hpriv = host->private_data;
+	mmio = hpriv->mmio;
+
+	/* sigh.  0xffffffff is a valid return from h/w */
+	irq_stat = readl(mmio + HOST_IRQ_STAT);
+	if (!irq_stat)
+		return IRQ_NONE;
+
+	irq_masked = irq_stat & hpriv->port_map;
+
+	spin_lock(&host->lock);
+
+	for (i = 0; i < host->n_ports; i++) {
+		struct ata_port *ap;
+
+		if (!(irq_masked & (1 << i)))
+			continue;
+
+		ap = host->ports[i];
+		if (ap) {
+			ahci_port_intr(ap);
+			VPRINTK("port %u\n", i);
+		} else {
+			VPRINTK("port %u (no irq)\n", i);
+			if (ata_ratelimit())
+				dev_printk(KERN_WARNING, host->dev,
+					"interrupt on disabled port %u\n", i);
+		}
+
+		handled = 1;
+	}
+
+	/* HOST_IRQ_STAT behaves as level triggered latch meaning that
+	 * it should be cleared after all the port events are cleared;
+	 * otherwise, it will raise a spurious interrupt after each
+	 * valid one.  Please read section 10.6.2 of ahci 1.1 for more
+	 * information.
+	 *
+	 * Also, use the unmasked value to clear interrupt as spurious
+	 * pending event on a dummy port might cause screaming IRQ.
+	 */
+	writel(irq_stat, mmio + HOST_IRQ_STAT);
+
+	spin_unlock(&host->lock);
+
+	VPRINTK("EXIT\n");
+
+	return IRQ_RETVAL(handled);
+}
+EXPORT_SYMBOL_GPL(ahci_interrupt);
+
+static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
+{
+	struct ata_port *ap = qc->ap;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	struct ahci_port_priv *pp = ap->private_data;
+
+	/* Keep track of the currently active link.  It will be used
+	 * in completion path to determine whether NCQ phase is in
+	 * progress.
+	 */
+	pp->active_link = qc->dev->link;
+
+	if (qc->tf.protocol == ATA_PROT_NCQ)
+		writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
+
+	if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
+		u32 fbs = readl(port_mmio + PORT_FBS);
+		fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
+		fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
+		writel(fbs, port_mmio + PORT_FBS);
+		pp->fbs_last_dev = qc->dev->link->pmp;
+	}
+
+	writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
+
+	ahci_sw_activity(qc->dev->link);
+
+	return 0;
+}
+
+static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
+{
+	struct ahci_port_priv *pp = qc->ap->private_data;
+	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
+
+	if (pp->fbs_enabled)
+		d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
+
+	ata_tf_from_fis(d2h_fis, &qc->result_tf);
+	return true;
+}
+
+static void ahci_freeze(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+
+	/* turn IRQ off */
+	writel(0, port_mmio + PORT_IRQ_MASK);
+}
+
+static void ahci_thaw(struct ata_port *ap)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 tmp;
+	struct ahci_port_priv *pp = ap->private_data;
+
+	/* clear IRQ */
+	tmp = readl(port_mmio + PORT_IRQ_STAT);
+	writel(tmp, port_mmio + PORT_IRQ_STAT);
+	writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
+
+	/* turn IRQ back on */
+	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+}
+
+static void ahci_error_handler(struct ata_port *ap)
+{
+	if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
+		/* restart engine */
+		ahci_stop_engine(ap);
+		ahci_start_engine(ap);
+	}
+
+	sata_pmp_error_handler(ap);
+}
+
+static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
+{
+	struct ata_port *ap = qc->ap;
+
+	/* make DMA engine forget about the failed command */
+	if (qc->flags & ATA_QCFLAG_FAILED)
+		ahci_kick_engine(ap);
+}
+
+static void ahci_enable_fbs(struct ata_port *ap)
+{
+	struct ahci_port_priv *pp = ap->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 fbs;
+	int rc;
+
+	if (!pp->fbs_supported)
+		return;
+
+	fbs = readl(port_mmio + PORT_FBS);
+	if (fbs & PORT_FBS_EN) {
+		pp->fbs_enabled = true;
+		pp->fbs_last_dev = -1; /* initialization */
+		return;
+	}
+
+	rc = ahci_stop_engine(ap);
+	if (rc)
+		return;
+
+	writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
+	fbs = readl(port_mmio + PORT_FBS);
+	if (fbs & PORT_FBS_EN) {
+		dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
+		pp->fbs_enabled = true;
+		pp->fbs_last_dev = -1; /* initialization */
+	} else
+		dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
+
+	ahci_start_engine(ap);
+}
+
+static void ahci_disable_fbs(struct ata_port *ap)
+{
+	struct ahci_port_priv *pp = ap->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 fbs;
+	int rc;
+
+	if (!pp->fbs_supported)
+		return;
+
+	fbs = readl(port_mmio + PORT_FBS);
+	if ((fbs & PORT_FBS_EN) == 0) {
+		pp->fbs_enabled = false;
+		return;
+	}
+
+	rc = ahci_stop_engine(ap);
+	if (rc)
+		return;
+
+	writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
+	fbs = readl(port_mmio + PORT_FBS);
+	if (fbs & PORT_FBS_EN)
+		dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
+	else {
+		dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
+		pp->fbs_enabled = false;
+	}
+
+	ahci_start_engine(ap);
+}
+
+static void ahci_pmp_attach(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	struct ahci_port_priv *pp = ap->private_data;
+	u32 cmd;
+
+	cmd = readl(port_mmio + PORT_CMD);
+	cmd |= PORT_CMD_PMP;
+	writel(cmd, port_mmio + PORT_CMD);
+
+	ahci_enable_fbs(ap);
+
+	pp->intr_mask |= PORT_IRQ_BAD_PMP;
+	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+}
+
+static void ahci_pmp_detach(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	struct ahci_port_priv *pp = ap->private_data;
+	u32 cmd;
+
+	ahci_disable_fbs(ap);
+
+	cmd = readl(port_mmio + PORT_CMD);
+	cmd &= ~PORT_CMD_PMP;
+	writel(cmd, port_mmio + PORT_CMD);
+
+	pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
+	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+}
+
+static int ahci_port_resume(struct ata_port *ap)
+{
+	ahci_power_up(ap);
+	ahci_start_port(ap);
+
+	if (sata_pmp_attached(ap))
+		ahci_pmp_attach(ap);
+	else
+		ahci_pmp_detach(ap);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
+{
+	const char *emsg = NULL;
+	int rc;
+
+	rc = ahci_deinit_port(ap, &emsg);
+	if (rc == 0)
+		ahci_power_down(ap);
+	else {
+		ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
+		ahci_start_port(ap);
+	}
+
+	return rc;
+}
+#endif
+
+static int ahci_port_start(struct ata_port *ap)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	struct device *dev = ap->host->dev;
+	struct ahci_port_priv *pp;
+	void *mem;
+	dma_addr_t mem_dma;
+	size_t dma_sz, rx_fis_sz;
+
+	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
+	if (!pp)
+		return -ENOMEM;
+
+	/* check FBS capability */
+	if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
+		void __iomem *port_mmio = ahci_port_base(ap);
+		u32 cmd = readl(port_mmio + PORT_CMD);
+		if (cmd & PORT_CMD_FBSCP)
+			pp->fbs_supported = true;
+		else
+			dev_printk(KERN_WARNING, dev,
+				   "The port is not capable of FBS\n");
+	}
+
+	if (pp->fbs_supported) {
+		dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
+		rx_fis_sz = AHCI_RX_FIS_SZ * 16;
+	} else {
+		dma_sz = AHCI_PORT_PRIV_DMA_SZ;
+		rx_fis_sz = AHCI_RX_FIS_SZ;
+	}
+
+	mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
+	if (!mem)
+		return -ENOMEM;
+	memset(mem, 0, dma_sz);
+
+	/*
+	 * First item in chunk of DMA memory: 32-slot command table,
+	 * 32 bytes each in size
+	 */
+	pp->cmd_slot = mem;
+	pp->cmd_slot_dma = mem_dma;
+
+	mem += AHCI_CMD_SLOT_SZ;
+	mem_dma += AHCI_CMD_SLOT_SZ;
+
+	/*
+	 * Second item: Received-FIS area
+	 */
+	pp->rx_fis = mem;
+	pp->rx_fis_dma = mem_dma;
+
+	mem += rx_fis_sz;
+	mem_dma += rx_fis_sz;
+
+	/*
+	 * Third item: data area for storing a single command
+	 * and its scatter-gather table
+	 */
+	pp->cmd_tbl = mem;
+	pp->cmd_tbl_dma = mem_dma;
+
+	/*
+	 * Save off initial list of interrupts to be enabled.
+	 * This could be changed later
+	 */
+	pp->intr_mask = DEF_PORT_IRQ;
+
+	ap->private_data = pp;
+
+	/* engage engines, captain */
+	return ahci_port_resume(ap);
+}
+
+static void ahci_port_stop(struct ata_port *ap)
+{
+	const char *emsg = NULL;
+	int rc;
+
+	/* de-initialize port */
+	rc = ahci_deinit_port(ap, &emsg);
+	if (rc)
+		ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
+}
+
+void ahci_print_info(struct ata_host *host, const char *scc_s)
+{
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+	u32 vers, cap, cap2, impl, speed;
+	const char *speed_s;
+
+	vers = readl(mmio + HOST_VERSION);
+	cap = hpriv->cap;
+	cap2 = hpriv->cap2;
+	impl = hpriv->port_map;
+
+	speed = (cap >> 20) & 0xf;
+	if (speed == 1)
+		speed_s = "1.5";
+	else if (speed == 2)
+		speed_s = "3";
+	else if (speed == 3)
+		speed_s = "6";
+	else
+		speed_s = "?";
+
+	dev_info(host->dev,
+		"AHCI %02x%02x.%02x%02x "
+		"%u slots %u ports %s Gbps 0x%x impl %s mode\n"
+		,
+
+		(vers >> 24) & 0xff,
+		(vers >> 16) & 0xff,
+		(vers >> 8) & 0xff,
+		vers & 0xff,
+
+		((cap >> 8) & 0x1f) + 1,
+		(cap & 0x1f) + 1,
+		speed_s,
+		impl,
+		scc_s);
+
+	dev_info(host->dev,
+		"flags: "
+		"%s%s%s%s%s%s%s"
+		"%s%s%s%s%s%s%s"
+		"%s%s%s%s%s%s\n"
+		,
+
+		cap & HOST_CAP_64 ? "64bit " : "",
+		cap & HOST_CAP_NCQ ? "ncq " : "",
+		cap & HOST_CAP_SNTF ? "sntf " : "",
+		cap & HOST_CAP_MPS ? "ilck " : "",
+		cap & HOST_CAP_SSS ? "stag " : "",
+		cap & HOST_CAP_ALPM ? "pm " : "",
+		cap & HOST_CAP_LED ? "led " : "",
+		cap & HOST_CAP_CLO ? "clo " : "",
+		cap & HOST_CAP_ONLY ? "only " : "",
+		cap & HOST_CAP_PMP ? "pmp " : "",
+		cap & HOST_CAP_FBS ? "fbs " : "",
+		cap & HOST_CAP_PIO_MULTI ? "pio " : "",
+		cap & HOST_CAP_SSC ? "slum " : "",
+		cap & HOST_CAP_PART ? "part " : "",
+		cap & HOST_CAP_CCC ? "ccc " : "",
+		cap & HOST_CAP_EMS ? "ems " : "",
+		cap & HOST_CAP_SXS ? "sxs " : "",
+		cap2 & HOST_CAP2_APST ? "apst " : "",
+		cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
+		cap2 & HOST_CAP2_BOH ? "boh " : ""
+		);
+}
+EXPORT_SYMBOL_GPL(ahci_print_info);
+
+void ahci_set_em_messages(struct ahci_host_priv *hpriv,
+			  struct ata_port_info *pi)
+{
+	u8 messages;
+	void __iomem *mmio = hpriv->mmio;
+	u32 em_loc = readl(mmio + HOST_EM_LOC);
+	u32 em_ctl = readl(mmio + HOST_EM_CTL);
+
+	if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
+		return;
+
+	messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
+
+	/* we only support LED message type right now */
+	if ((messages & 0x01) && (ahci_em_messages == 1)) {
+		/* store em_loc */
+		hpriv->em_loc = ((em_loc >> 16) * 4);
+		pi->flags |= ATA_FLAG_EM;
+		if (!(em_ctl & EM_CTL_ALHD))
+			pi->flags |= ATA_FLAG_SW_ACTIVITY;
+	}
+}
+EXPORT_SYMBOL_GPL(ahci_set_em_messages);
+
+MODULE_AUTHOR("Jeff Garzik");
+MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
+MODULE_LICENSE("GPL");
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 072ba5ea138f..299d32721a56 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -709,7 +709,13 @@ u64 ata_tf_read_block(struct ata_taskfile *tf, struct ata_device *dev)
 		head = tf->device & 0xf;
 		sect = tf->lbal;
 
-		block = (cyl * dev->heads + head) * dev->sectors + sect;
+		if (!sect) {
+			ata_dev_printk(dev, KERN_WARNING, "device reported "
+				       "invalid CHS sector 0\n");
+			sect = 1; /* oh well */
+		}
+
+		block = (cyl * dev->heads + head) * dev->sectors + sect - 1;
 	}
 
 	return block;
@@ -2299,29 +2305,49 @@ static inline u8 ata_dev_knobble(struct ata_device *dev)
 	return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(dev->id)));
 }
 
-static void ata_dev_config_ncq(struct ata_device *dev,
+static int ata_dev_config_ncq(struct ata_device *dev,
 			       char *desc, size_t desc_sz)
 {
 	struct ata_port *ap = dev->link->ap;
 	int hdepth = 0, ddepth = ata_id_queue_depth(dev->id);
+	unsigned int err_mask;
+	char *aa_desc = "";
 
 	if (!ata_id_has_ncq(dev->id)) {
 		desc[0] = '\0';
-		return;
+		return 0;
 	}
 	if (dev->horkage & ATA_HORKAGE_NONCQ) {
 		snprintf(desc, desc_sz, "NCQ (not used)");
-		return;
+		return 0;
 	}
 	if (ap->flags & ATA_FLAG_NCQ) {
 		hdepth = min(ap->scsi_host->can_queue, ATA_MAX_QUEUE - 1);
 		dev->flags |= ATA_DFLAG_NCQ;
 	}
 
+	if (!(dev->horkage & ATA_HORKAGE_BROKEN_FPDMA_AA) &&
+		(ap->flags & ATA_FLAG_FPDMA_AA) &&
+		ata_id_has_fpdma_aa(dev->id)) {
+		err_mask = ata_dev_set_feature(dev, SETFEATURES_SATA_ENABLE,
+			SATA_FPDMA_AA);
+		if (err_mask) {
+			ata_dev_printk(dev, KERN_ERR, "failed to enable AA"
+				"(error_mask=0x%x)\n", err_mask);
+			if (err_mask != AC_ERR_DEV) {
+				dev->horkage |= ATA_HORKAGE_BROKEN_FPDMA_AA;
+				return -EIO;
+			}
+		} else
+			aa_desc = ", AA";
+	}
+
 	if (hdepth >= ddepth)
-		snprintf(desc, desc_sz, "NCQ (depth %d)", ddepth);
+		snprintf(desc, desc_sz, "NCQ (depth %d)%s", ddepth, aa_desc);
 	else
-		snprintf(desc, desc_sz, "NCQ (depth %d/%d)", hdepth, ddepth);
+		snprintf(desc, desc_sz, "NCQ (depth %d/%d)%s", hdepth,
+			ddepth, aa_desc);
+	return 0;
 }
 
 /**
@@ -2461,7 +2487,7 @@ int ata_dev_configure(struct ata_device *dev)
 
 		if (ata_id_has_lba(id)) {
 			const char *lba_desc;
-			char ncq_desc[20];
+			char ncq_desc[24];
 
 			lba_desc = "LBA";
 			dev->flags |= ATA_DFLAG_LBA;
@@ -2475,7 +2501,9 @@ int ata_dev_configure(struct ata_device *dev)
 			}
 
 			/* config NCQ */
-			ata_dev_config_ncq(dev, ncq_desc, sizeof(ncq_desc));
+			rc = ata_dev_config_ncq(dev, ncq_desc, sizeof(ncq_desc));
+			if (rc)
+				return rc;
 
 			/* print device info to dmesg */
 			if (ata_msg_drv(ap) && print_info) {
@@ -5002,12 +5030,14 @@ void ata_qc_complete(struct ata_queued_cmd *qc)
 			qc->flags |= ATA_QCFLAG_FAILED;
 
 		if (unlikely(qc->flags & ATA_QCFLAG_FAILED)) {
-			if (!ata_tag_internal(qc->tag)) {
-				/* always fill result TF for failed qc */
-				fill_result_tf(qc);
+			/* always fill result TF for failed qc */
+			fill_result_tf(qc);
+
+			if (!ata_tag_internal(qc->tag))
 				ata_qc_schedule_eh(qc);
-				return;
-			}
+			else
+				__ata_qc_complete(qc);
+			return;
 		}
 
 		/* read result TF if requested */
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index 79711b64054b..1652b9190607 100644
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -2541,14 +2541,14 @@ int ata_eh_reset(struct ata_link *link, int classify,
 		dev->pio_mode = XFER_PIO_0;
 		dev->flags &= ~ATA_DFLAG_SLEEPING;
 
-		if (!ata_phys_link_offline(ata_dev_phys_link(dev))) {
-			/* apply class override */
-			if (lflags & ATA_LFLAG_ASSUME_ATA)
-				classes[dev->devno] = ATA_DEV_ATA;
-			else if (lflags & ATA_LFLAG_ASSUME_SEMB)
-				classes[dev->devno] = ATA_DEV_SEMB_UNSUP;
-		} else
-			classes[dev->devno] = ATA_DEV_NONE;
+		if (ata_phys_link_offline(ata_dev_phys_link(dev)))
+			continue;
+
+		/* apply class override */
+		if (lflags & ATA_LFLAG_ASSUME_ATA)
+			classes[dev->devno] = ATA_DEV_ATA;
+		else if (lflags & ATA_LFLAG_ASSUME_SEMB)
+			classes[dev->devno] = ATA_DEV_SEMB_UNSUP;
 	}
 
 	/* record current link speed */
@@ -2581,34 +2581,48 @@ int ata_eh_reset(struct ata_link *link, int classify,
 		slave->eh_info.serror = 0;
 	spin_unlock_irqrestore(link->ap->lock, flags);
 
-	/* Make sure onlineness and classification result correspond.
+	/*
+	 * Make sure onlineness and classification result correspond.
 	 * Hotplug could have happened during reset and some
 	 * controllers fail to wait while a drive is spinning up after
 	 * being hotplugged causing misdetection.  By cross checking
-	 * link onlineness and classification result, those conditions
-	 * can be reliably detected and retried.
+	 * link on/offlineness and classification result, those
+	 * conditions can be reliably detected and retried.
 	 */
 	nr_unknown = 0;
 	ata_for_each_dev(dev, link, ALL) {
-		/* convert all ATA_DEV_UNKNOWN to ATA_DEV_NONE */
-		if (classes[dev->devno] == ATA_DEV_UNKNOWN) {
-			classes[dev->devno] = ATA_DEV_NONE;
-			if (ata_phys_link_online(ata_dev_phys_link(dev)))
+		if (ata_phys_link_online(ata_dev_phys_link(dev))) {
+			if (classes[dev->devno] == ATA_DEV_UNKNOWN) {
+				ata_dev_printk(dev, KERN_DEBUG, "link online "
+					       "but device misclassifed\n");
+				classes[dev->devno] = ATA_DEV_NONE;
 				nr_unknown++;
+			}
+		} else if (ata_phys_link_offline(ata_dev_phys_link(dev))) {
+			if (ata_class_enabled(classes[dev->devno]))
+				ata_dev_printk(dev, KERN_DEBUG, "link offline, "
+					       "clearing class %d to NONE\n",
+					       classes[dev->devno]);
+			classes[dev->devno] = ATA_DEV_NONE;
+		} else if (classes[dev->devno] == ATA_DEV_UNKNOWN) {
+			ata_dev_printk(dev, KERN_DEBUG, "link status unknown, "
+				       "clearing UNKNOWN to NONE\n");
+			classes[dev->devno] = ATA_DEV_NONE;
 		}
 	}
 
 	if (classify && nr_unknown) {
 		if (try < max_tries) {
 			ata_link_printk(link, KERN_WARNING, "link online but "
-				       "device misclassified, retrying\n");
+					"%d devices misclassified, retrying\n",
+					nr_unknown);
 			failed_link = link;
 			rc = -EAGAIN;
 			goto fail;
 		}
 		ata_link_printk(link, KERN_WARNING,
-			       "link online but device misclassified, "
-			       "device detection might fail\n");
+				"link online but %d devices misclassified, "
+				"device detection might fail\n", nr_unknown);
 	}
 
 	/* reset successful, schedule revalidation */
@@ -2835,12 +2849,14 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
 	 * device detection messages backwards.
 	 */
 	ata_for_each_dev(dev, link, ALL) {
-		if (!(new_mask & (1 << dev->devno)) ||
-		    dev->class == ATA_DEV_PMP)
+		if (!(new_mask & (1 << dev->devno)))
 			continue;
 
 		dev->class = ehc->classes[dev->devno];
 
+		if (dev->class == ATA_DEV_PMP)
+			continue;
+
 		ehc->i.flags |= ATA_EHI_PRINTINFO;
 		rc = ata_dev_configure(dev);
 		ehc->i.flags &= ~ATA_EHI_PRINTINFO;
diff --git a/drivers/ata/pata_amd.c b/drivers/ata/pata_amd.c
index 33a74f11171c..567f3f72774e 100644
--- a/drivers/ata/pata_amd.c
+++ b/drivers/ata/pata_amd.c
@@ -307,6 +307,9 @@ static unsigned long nv_mode_filter(struct ata_device *dev,
 		limit |= ATA_MASK_PIO;
 	if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA)))
 		limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA;
+	/* PIO4, MWDMA2, UDMA2 should always be supported regardless of
+	   cable detection result */
+	limit |= ata_pack_xfermask(ATA_PIO4, ATA_MWDMA2, ATA_UDMA2);
 
 	ata_port_printk(ap, KERN_DEBUG, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
 			"BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
diff --git a/drivers/ata/pata_cmd64x.c b/drivers/ata/pata_cmd64x.c
index f98dffedf4bc..f0bad9be0f65 100644
--- a/drivers/ata/pata_cmd64x.c
+++ b/drivers/ata/pata_cmd64x.c
@@ -219,7 +219,7 @@ static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 		regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
 		/* Merge the control bits */
 		regU |= 1 << adev->devno; /* UDMA on */
-		if (adev->dma_mode > 2)	/* 15nS timing */
+		if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
 			regU |= 4 << adev->devno;
 	} else {
 		regU &= ~ (1 << adev->devno);	/* UDMA off */
diff --git a/drivers/ata/pata_fsl.c b/drivers/ata/pata_fsl.c
index c1d05282da03..955095039257 100644
--- a/drivers/ata/pata_fsl.c
+++ b/drivers/ata/pata_fsl.c
@@ -3,7 +3,7 @@
  */
 
 /*
- * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -766,10 +766,11 @@ static int __devinit pata_fsl_probe(struct platform_device *pdev)
 	/*
 	 * Set up resources
 	 */
-	if (unlikely(pdev->num_resources != 3)) {
+	if (unlikely(pdev->num_resources != 2)) {
 		dev_err(&pdev->dev, "invalid number of resources\n");
 		return -EINVAL;
 	}
+
 	/*
 	 * Get an ata_host structure for this device
 	 */
diff --git a/drivers/ata/pata_hpt37x.c b/drivers/ata/pata_hpt37x.c
index 122c786449a9..ca5f8d7f638c 100644
--- a/drivers/ata/pata_hpt37x.c
+++ b/drivers/ata/pata_hpt37x.c
@@ -24,7 +24,7 @@
 #include <linux/libata.h>
 
 #define DRV_NAME	"pata_hpt37x"
-#define DRV_VERSION	"0.6.12"
+#define DRV_VERSION	"0.6.14"
 
 struct hpt_clock {
 	u8	xfer_speed;
@@ -404,9 +404,8 @@ static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
 
 	pci_read_config_dword(pdev, addr1, &reg);
 	mode = hpt37x_find_mode(ap, adev->pio_mode);
-	mode &= ~0x8000000;	/* No FIFO in PIO */
-	mode &= ~0x30070000;	/* Leave config bits alone */
-	reg &= 0x30070000;	/* Strip timing bits */
+	mode &= 0xCFC3FFFF;	/* Leave DMA bits alone */
+	reg &= ~0xCFC3FFFF;	/* Strip timing bits */
 	pci_write_config_dword(pdev, addr1, reg | mode);
 }
 
@@ -423,8 +422,7 @@ static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 {
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	u32 addr1, addr2;
-	u32 reg;
-	u32 mode;
+	u32 reg, mode, mask;
 	u8 fast;
 
 	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
@@ -436,11 +434,12 @@ static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 	fast |= 0x01;
 	pci_write_config_byte(pdev, addr2, fast);
 
+	mask = adev->dma_mode < XFER_UDMA_0 ? 0x31C001FF : 0x303C0000;
+
 	pci_read_config_dword(pdev, addr1, &reg);
 	mode = hpt37x_find_mode(ap, adev->dma_mode);
-	mode |= 0x8000000;	/* FIFO in MWDMA or UDMA */
-	mode &= ~0xC0000000;	/* Leave config bits alone */
-	reg &= 0xC0000000;	/* Strip timing bits */
+	mode &= mask;
+	reg &= ~mask;
 	pci_write_config_dword(pdev, addr1, reg | mode);
 }
 
@@ -508,9 +507,8 @@ static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
 	mode = hpt37x_find_mode(ap, adev->pio_mode);
 
 	printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
-	mode &= ~0x80000000;	/* No FIFO in PIO */
-	mode &= ~0x30070000;	/* Leave config bits alone */
-	reg &= 0x30070000;	/* Strip timing bits */
+	mode &= 0xCFC3FFFF;	/* Leave DMA bits alone */
+	reg &= ~0xCFC3FFFF;	/* Strip timing bits */
 	pci_write_config_dword(pdev, addr1, reg | mode);
 }
 
@@ -527,8 +525,7 @@ static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 {
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	u32 addr1, addr2;
-	u32 reg;
-	u32 mode;
+	u32 reg, mode, mask;
 	u8 fast;
 
 	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
@@ -539,12 +536,13 @@ static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 	fast &= ~0x07;
 	pci_write_config_byte(pdev, addr2, fast);
 
+	mask = adev->dma_mode < XFER_UDMA_0 ? 0x31C001FF : 0x303C0000;
+
 	pci_read_config_dword(pdev, addr1, &reg);
 	mode = hpt37x_find_mode(ap, adev->dma_mode);
 	printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
-	mode &= ~0xC0000000;	/* Leave config bits alone */
-	mode |= 0x80000000;	/* FIFO in MWDMA or UDMA */
-	reg &= 0xC0000000;	/* Strip timing bits */
+	mode &= mask;
+	reg &= ~mask;
 	pci_write_config_dword(pdev, addr1, reg | mode);
 }
 
diff --git a/drivers/ata/pata_hpt3x2n.c b/drivers/ata/pata_hpt3x2n.c
index 3d59fe0a408d..d16e87e29189 100644
--- a/drivers/ata/pata_hpt3x2n.c
+++ b/drivers/ata/pata_hpt3x2n.c
@@ -8,7 +8,7 @@
  * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
  * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
  * Portions Copyright (C) 2003		Red Hat Inc
- * Portions Copyright (C) 2005-2007	MontaVista Software, Inc.
+ * Portions Copyright (C) 2005-2009	MontaVista Software, Inc.
  *
  *
  * TODO
@@ -25,7 +25,7 @@
 #include <linux/libata.h>
 
 #define DRV_NAME	"pata_hpt3x2n"
-#define DRV_VERSION	"0.3.4"
+#define DRV_VERSION	"0.3.8"
 
 enum {
 	HPT_PCI_FAST	=	(1 << 31),
@@ -185,9 +185,8 @@ static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
 
 	pci_read_config_dword(pdev, addr1, &reg);
 	mode = hpt3x2n_find_mode(ap, adev->pio_mode);
-	mode &= ~0x8000000;	/* No FIFO in PIO */
-	mode &= ~0x30070000;	/* Leave config bits alone */
-	reg &= 0x30070000;	/* Strip timing bits */
+	mode &= 0xCFC3FFFF;	/* Leave DMA bits alone */
+	reg &= ~0xCFC3FFFF;	/* Strip timing bits */
 	pci_write_config_dword(pdev, addr1, reg | mode);
 }
 
@@ -204,8 +203,7 @@ static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 {
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	u32 addr1, addr2;
-	u32 reg;
-	u32 mode;
+	u32 reg, mode, mask;
 	u8 fast;
 
 	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
@@ -216,11 +214,12 @@ static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 	fast &= ~0x07;
 	pci_write_config_byte(pdev, addr2, fast);
 
+	mask = adev->dma_mode < XFER_UDMA_0 ? 0x31C001FF : 0x303C0000;
+
 	pci_read_config_dword(pdev, addr1, &reg);
 	mode = hpt3x2n_find_mode(ap, adev->dma_mode);
-	mode |= 0x8000000;	/* FIFO in MWDMA or UDMA */
-	mode &= ~0xC0000000;	/* Leave config bits alone */
-	reg &= 0xC0000000;	/* Strip timing bits */
+	mode &= mask;
+	reg &= ~mask;
 	pci_write_config_dword(pdev, addr1, reg | mode);
 }
 
@@ -263,7 +262,7 @@ static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
 
 static void hpt3x2n_set_clock(struct ata_port *ap, int source)
 {
-	void __iomem *bmdma = ap->ioaddr.bmdma_addr;
+	void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8;
 
 	/* Tristate the bus */
 	iowrite8(0x80, bmdma+0x73);
@@ -273,9 +272,9 @@ static void hpt3x2n_set_clock(struct ata_port *ap, int source)
 	iowrite8(source, bmdma+0x7B);
 	iowrite8(0xC0, bmdma+0x79);
 
-	/* Reset state machines */
-	iowrite8(0x37, bmdma+0x70);
-	iowrite8(0x37, bmdma+0x74);
+	/* Reset state machines, avoid enabling the disabled channels */
+	iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70);
+	iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74);
 
 	/* Complete reset */
 	iowrite8(0x00, bmdma+0x79);
@@ -285,21 +284,10 @@ static void hpt3x2n_set_clock(struct ata_port *ap, int source)
 	iowrite8(0x00, bmdma+0x77);
 }
 
-/* Check if our partner interface is busy */
-
-static int hpt3x2n_pair_idle(struct ata_port *ap)
-{
-	struct ata_host *host = ap->host;
-	struct ata_port *pair = host->ports[ap->port_no ^ 1];
-
-	if (pair->hsm_task_state == HSM_ST_IDLE)
-		return 1;
-	return 0;
-}
-
 static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
 {
 	long flags = (long)ap->host->private_data;
+
 	/* See if we should use the DPLL */
 	if (writing)
 		return USE_DPLL;	/* Needed for write */
@@ -308,20 +296,35 @@ static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
 	return 0;
 }
 
+static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc)
+{
+	struct ata_port *ap = qc->ap;
+	struct ata_port *alt = ap->host->ports[ap->port_no ^ 1];
+	int rc, flags = (long)ap->host->private_data;
+	int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
+
+	/* First apply the usual rules */
+	rc = ata_std_qc_defer(qc);
+	if (rc != 0)
+		return rc;
+
+	if ((flags & USE_DPLL) != dpll && alt->qc_active)
+		return ATA_DEFER_PORT;
+	return 0;
+}
+
 static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
 {
-	struct ata_taskfile *tf = &qc->tf;
 	struct ata_port *ap = qc->ap;
 	int flags = (long)ap->host->private_data;
+	int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
 
-	if (hpt3x2n_pair_idle(ap)) {
-		int dpll = hpt3x2n_use_dpll(ap, (tf->flags & ATA_TFLAG_WRITE));
-		if ((flags & USE_DPLL) != dpll) {
-			if (dpll == 1)
-				hpt3x2n_set_clock(ap, 0x21);
-			else
-				hpt3x2n_set_clock(ap, 0x23);
-		}
+	if ((flags & USE_DPLL) != dpll) {
+		flags &= ~USE_DPLL;
+		flags |= dpll;
+		ap->host->private_data = (void *)(long)flags;
+
+		hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
 	}
 	return ata_sff_qc_issue(qc);
 }
@@ -338,6 +341,8 @@ static struct ata_port_operations hpt3x2n_port_ops = {
 	.inherits	= &ata_bmdma_port_ops,
 
 	.bmdma_stop	= hpt3x2n_bmdma_stop,
+
+	.qc_defer	= hpt3x2n_qc_defer,
 	.qc_issue	= hpt3x2n_qc_issue,
 
 	.cable_detect	= hpt3x2n_cable_detect,
@@ -455,7 +460,7 @@ static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 	unsigned int f_low, f_high;
 	int adjust;
 	unsigned long iobase = pci_resource_start(dev, 4);
-	void *hpriv = NULL;
+	void *hpriv = (void *)USE_DPLL;
 	int rc;
 
 	rc = pcim_enable_device(dev);
@@ -543,7 +548,7 @@ static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 	/* Set our private data up. We only need a few flags so we use
 	   it directly */
 	if (pci_mhz > 60) {
-		hpriv = (void *)PCI66;
+		hpriv = (void *)(PCI66 | USE_DPLL);
 		/*
 		 * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
 		 * the MISC. register to stretch the UltraDMA Tss timing.
diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c
index dc99e26f8e5b..c4647f5b6a22 100644
--- a/drivers/ata/pata_pcmcia.c
+++ b/drivers/ata/pata_pcmcia.c
@@ -136,7 +136,7 @@ static unsigned int ata_data_xfer_8bit(struct ata_device *dev,
  *
  */
  
-void pcmcia_8bit_drain_fifo(struct ata_queued_cmd *qc)
+static void pcmcia_8bit_drain_fifo(struct ata_queued_cmd *qc)
 {
 	int count;
 	struct ata_port *ap;
diff --git a/drivers/ata/pata_sc1200.c b/drivers/ata/pata_sc1200.c
index f49814d6fd2e..3bbed8322ecf 100644
--- a/drivers/ata/pata_sc1200.c
+++ b/drivers/ata/pata_sc1200.c
@@ -235,8 +235,7 @@ static int sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 		.udma_mask = ATA_UDMA2,
 		.port_ops = &sc1200_port_ops
 	};
-	/* Can't enable port 2 yet, see top comments */
-	const struct ata_port_info *ppi[] = { &info, };
+	const struct ata_port_info *ppi[] = { &info, NULL };
 
 	return ata_pci_sff_init_one(dev, ppi, &sc1200_sht, NULL);
 }
diff --git a/drivers/ata/pata_via.c b/drivers/ata/pata_via.c
index 45657cacec43..88984b803d6d 100644
--- a/drivers/ata/pata_via.c
+++ b/drivers/ata/pata_via.c
@@ -111,7 +111,7 @@ static const struct via_isa_bridge {
 	{ "vt8251",	PCI_DEVICE_ID_VIA_8251,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
 	{ "cx700",	PCI_DEVICE_ID_VIA_CX700,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA },
 	{ "vt6410",	PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES },
-	{ "vt6415",	PCI_DEVICE_ID_VIA_6415,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES },
+	{ "vt6415",	PCI_DEVICE_ID_VIA_6415,     0x00, 0xff, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES },
 	{ "vt8237a",	PCI_DEVICE_ID_VIA_8237A,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
 	{ "vt8237",	PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
 	{ "vt8235",	PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c
index 86a40582999c..1eb4e020eb5c 100644
--- a/drivers/ata/sata_nv.c
+++ b/drivers/ata/sata_nv.c
@@ -1594,9 +1594,21 @@ static int nv_hardreset(struct ata_link *link, unsigned int *class,
 	    !ata_dev_enabled(link->device))
 		sata_link_hardreset(link, sata_deb_timing_hotplug, deadline,
 				    NULL, NULL);
-	else if (!(ehc->i.flags & ATA_EHI_QUIET))
-		ata_link_printk(link, KERN_INFO,
-				"nv: skipping hardreset on occupied port\n");
+	else {
+		const unsigned long *timing = sata_ehc_deb_timing(ehc);
+		int rc;
+
+		if (!(ehc->i.flags & ATA_EHI_QUIET))
+			ata_link_printk(link, KERN_INFO, "nv: skipping "
+					"hardreset on occupied port\n");
+
+		/* make sure the link is online */
+		rc = sata_link_resume(link, timing, deadline);
+		/* whine about phy resume failure but proceed */
+		if (rc && rc != -EOPNOTSUPP)
+			ata_link_printk(link, KERN_WARNING, "failed to resume "
+					"link (errno=%d)\n", rc);
+	}
 
 	/* device signature acquisition is unreliable */
 	return -EAGAIN;
diff --git a/drivers/ata/sata_via.c b/drivers/ata/sata_via.c
index bdd43c7f432e..02efd9a83d26 100644
--- a/drivers/ata/sata_via.c
+++ b/drivers/ata/sata_via.c
@@ -93,7 +93,6 @@ static const struct pci_device_id svia_pci_tbl[] = {
 	{ PCI_VDEVICE(VIA, 0x7372), vt6420 },
 	{ PCI_VDEVICE(VIA, 0x5287), vt8251 }, /* 2 sata chnls (Master/Slave) */
 	{ PCI_VDEVICE(VIA, 0x9000), vt8251 },
-	{ PCI_VDEVICE(VIA, 0x9040), vt8251 },
 
 	{ }	/* terminate list */
 };
diff --git a/drivers/base/base.h b/drivers/base/base.h
index b528145a078f..1e52c125f437 100644
--- a/drivers/base/base.h
+++ b/drivers/base/base.h
@@ -104,7 +104,7 @@ extern int system_bus_init(void);
 extern int cpu_dev_init(void);
 
 extern int bus_add_device(struct device *dev);
-extern void bus_attach_device(struct device *dev);
+extern void bus_probe_device(struct device *dev);
 extern void bus_remove_device(struct device *dev);
 
 extern int bus_add_driver(struct device_driver *drv);
diff --git a/drivers/base/bus.c b/drivers/base/bus.c
index 4b04a15146d7..973bf2ad4e0d 100644
--- a/drivers/base/bus.c
+++ b/drivers/base/bus.c
@@ -459,8 +459,9 @@ static inline void remove_deprecated_bus_links(struct device *dev) { }
  * bus_add_device - add device to bus
  * @dev: device being added
  *
+ * - Add device's bus attributes.
+ * - Create links to device's bus.
  * - Add the device to its bus's list of devices.
- * - Create link to device's bus.
  */
 int bus_add_device(struct device *dev)
 {
@@ -483,6 +484,7 @@ int bus_add_device(struct device *dev)
 		error = make_deprecated_bus_links(dev);
 		if (error)
 			goto out_deprecated;
+		klist_add_tail(&dev->p->knode_bus, &bus->p->klist_devices);
 	}
 	return 0;
 
@@ -498,24 +500,19 @@ out_put:
 }
 
 /**
- * bus_attach_device - add device to bus
- * @dev: device tried to attach to a driver
+ * bus_probe_device - probe drivers for a new device
+ * @dev: device to probe
  *
- * - Add device to bus's list of devices.
- * - Try to attach to driver.
+ * - Automatically probe for a driver if the bus allows it.
  */
-void bus_attach_device(struct device *dev)
+void bus_probe_device(struct device *dev)
 {
 	struct bus_type *bus = dev->bus;
-	int ret = 0;
+	int ret;
 
-	if (bus) {
-		if (bus->p->drivers_autoprobe)
-			ret = device_attach(dev);
+	if (bus && bus->p->drivers_autoprobe) {
+		ret = device_attach(dev);
 		WARN_ON(ret < 0);
-		if (ret >= 0)
-			klist_add_tail(&dev->p->knode_bus,
-				       &bus->p->klist_devices);
 	}
 }
 
diff --git a/drivers/base/class.c b/drivers/base/class.c
index eb85e4312301..4317d4ca540a 100644
--- a/drivers/base/class.c
+++ b/drivers/base/class.c
@@ -59,6 +59,8 @@ static void class_release(struct kobject *kobj)
 	else
 		pr_debug("class '%s' does not have a release() function, "
 			 "be careful\n", class->name);
+
+	kfree(cp);
 }
 
 static struct sysfs_ops class_sysfs_ops = {
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 7ecb1938e590..c34774d0b9d3 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -945,7 +945,7 @@ int device_add(struct device *dev)
 					     BUS_NOTIFY_ADD_DEVICE, dev);
 
 	kobject_uevent(&dev->kobj, KOBJ_ADD);
-	bus_attach_device(dev);
+	bus_probe_device(dev);
 	if (parent)
 		klist_add_tail(&dev->p->knode_parent,
 			       &parent->p->klist_children);
diff --git a/drivers/base/driver.c b/drivers/base/driver.c
index 8ae0f63602e0..2b7f5bc8c021 100644
--- a/drivers/base/driver.c
+++ b/drivers/base/driver.c
@@ -236,7 +236,7 @@ int driver_register(struct device_driver *drv)
 		put_driver(other);
 		printk(KERN_ERR "Error: Driver '%s' is already registered, "
 			"aborting...\n", drv->name);
-		return -EEXIST;
+		return -EBUSY;
 	}
 
 	ret = bus_add_driver(drv);
diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c
index a52cc7fe45ea..c18bbbf04e47 100644
--- a/drivers/block/cciss.c
+++ b/drivers/block/cciss.c
@@ -323,6 +323,9 @@ static int cciss_seq_show(struct seq_file *seq, void *v)
 	if (*pos > h->highest_lun)
 		return 0;
 
+	if (drv == NULL) /* it's possible for h->drv[] to have holes. */
+		return 0;
+
 	if (drv->heads == 0)
 		return 0;
 
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 8efaa5ca8a03..00ebf36b0059 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -323,7 +323,7 @@ config SPECIALIX
 
 config SX
 	tristate "Specialix SX (and SI) card support"
-	depends on SERIAL_NONSTANDARD && (PCI || EISA || ISA)
+	depends on SERIAL_NONSTANDARD && (PCI || EISA || ISA) && BROKEN
 	help
 	  This is a driver for the SX and SI multiport serial cards.
 	  Please read the file <file:Documentation/serial/sx.txt> for details.
@@ -334,7 +334,7 @@ config SX
 
 config RIO
 	tristate "Specialix RIO system support"
-	depends on SERIAL_NONSTANDARD
+	depends on SERIAL_NONSTANDARD && BROKEN
 	help
 	  This is a driver for the Specialix RIO, a smart serial card which
 	  drives an outboard box that can support up to 128 ports.  Product
@@ -395,7 +395,7 @@ config NOZOMI
 
 config A2232
 	tristate "Commodore A2232 serial support (EXPERIMENTAL)"
-	depends on EXPERIMENTAL && ZORRO && BROKEN_ON_SMP
+	depends on EXPERIMENTAL && ZORRO && BROKEN
 	---help---
 	  This option supports the 2232 7-port serial card shipped with the
 	  Amiga 2000 and other Zorro-bus machines, dating from 1989.  At
diff --git a/drivers/char/agp/backend.c b/drivers/char/agp/backend.c
index cfa5a649dfe7..19ce9d6c69f1 100644
--- a/drivers/char/agp/backend.c
+++ b/drivers/char/agp/backend.c
@@ -114,9 +114,9 @@ static int agp_find_max(void)
 	long memory, index, result;
 
 #if PAGE_SHIFT < 20
-	memory = num_physpages >> (20 - PAGE_SHIFT);
+	memory = totalram_pages >> (20 - PAGE_SHIFT);
 #else
-	memory = num_physpages << (PAGE_SHIFT - 20);
+	memory = totalram_pages << (PAGE_SHIFT - 20);
 #endif
 	index = 1;
 
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index c58557790585..62711ddeb53a 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -36,6 +36,8 @@
 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
+#define PCI_DEVICE_ID_INTEL_B43_HB          0x2E40
+#define PCI_DEVICE_ID_INTEL_B43_IG          0x2E42
 #define PCI_DEVICE_ID_INTEL_GM45_HB         0x2A40
 #define PCI_DEVICE_ID_INTEL_GM45_IG         0x2A42
 #define PCI_DEVICE_ID_INTEL_IGD_E_HB        0x2E00
@@ -50,6 +52,7 @@
 #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG	    0x0042
 #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB	    0x0044
 #define PCI_DEVICE_ID_INTEL_IGDNG_MA_HB	    0x0062
+#define PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB    0x006a
 #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG	    0x0046
 
 /* cover 915 and 945 variants */
@@ -81,9 +84,11 @@
 		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
 		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
 		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
+		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
 		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
 		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \
-		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB)
+		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB || \
+		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB)
 
 extern int agp_memory_reserved;
 
@@ -679,23 +684,39 @@ static void intel_i830_setup_flush(void)
 	if (!intel_private.i8xx_page)
 		return;
 
-	/* make page uncached */
-	map_page_into_agp(intel_private.i8xx_page);
-
 	intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 	if (!intel_private.i8xx_flush_page)
 		intel_i830_fini_flush();
 }
 
+static void
+do_wbinvd(void *null)
+{
+	wbinvd();
+}
+
+/* The chipset_flush interface needs to get data that has already been
+ * flushed out of the CPU all the way out to main memory, because the GPU
+ * doesn't snoop those buffers.
+ *
+ * The 8xx series doesn't have the same lovely interface for flushing the
+ * chipset write buffers that the later chips do. According to the 865
+ * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
+ * that buffer out, we just fill 1KB and clflush it out, on the assumption
+ * that it'll push whatever was in there out.  It appears to work.
+ */
 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 {
 	unsigned int *pg = intel_private.i8xx_flush_page;
-	int i;
 
-	for (i = 0; i < 256; i += 2)
-		*(pg + i) = i;
+	memset(pg, 0, 1024);
 
-	wmb();
+	if (cpu_has_clflush) {
+		clflush_cache_range(pg, 1024);
+	} else {
+		if (on_each_cpu(do_wbinvd, NULL, 1) != 0)
+			printk(KERN_ERR "Timed out waiting for cache flush.\n");
+	}
 }
 
 /* The intel i830 automatically initializes the agp aperture during POST.
@@ -1216,9 +1237,11 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
 	case PCI_DEVICE_ID_INTEL_Q45_HB:
 	case PCI_DEVICE_ID_INTEL_G45_HB:
 	case PCI_DEVICE_ID_INTEL_G41_HB:
+	case PCI_DEVICE_ID_INTEL_B43_HB:
 	case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
 	case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
 	case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB:
+	case PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB:
 		*gtt_offset = *gtt_size = MB(2);
 		break;
 	default:
@@ -2192,6 +2215,8 @@ static const struct intel_driver_description {
 	    "Q45/Q43", NULL, &intel_i965_driver },
 	{ PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
 	    "G45/G43", NULL, &intel_i965_driver },
+	{ PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0,
+	    "B43", NULL, &intel_i965_driver },
 	{ PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
 	    "G41", NULL, &intel_i965_driver },
 	{ PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
@@ -2200,6 +2225,8 @@ static const struct intel_driver_description {
 	    "IGDNG/M", NULL, &intel_i965_driver },
 	{ PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
 	    "IGDNG/MA", NULL, &intel_i965_driver },
+	{ PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
+	    "IGDNG/MC2", NULL, &intel_i965_driver },
 	{ 0, 0, 0, NULL, NULL, NULL }
 };
 
@@ -2313,15 +2340,6 @@ static int agp_intel_resume(struct pci_dev *pdev)
 	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 	int ret_val;
 
-	pci_restore_state(pdev);
-
-	/* We should restore our graphics device's config space,
-	 * as host bridge (00:00) resumes before graphics device (02:00),
-	 * then our access to its pci space can work right.
-	 */
-	if (intel_private.pcidev)
-		pci_restore_state(intel_private.pcidev);
-
 	if (bridge->driver == &intel_generic_driver)
 		intel_configure();
 	else if (bridge->driver == &intel_850_driver)
@@ -2401,9 +2419,11 @@ static struct pci_device_id agp_intel_pci_table[] = {
 	ID(PCI_DEVICE_ID_INTEL_Q45_HB),
 	ID(PCI_DEVICE_ID_INTEL_G45_HB),
 	ID(PCI_DEVICE_ID_INTEL_G41_HB),
+	ID(PCI_DEVICE_ID_INTEL_B43_HB),
 	ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
 	ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
 	ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB),
+	ID(PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB),
 	{ }
 };
 
diff --git a/drivers/char/hvc_xen.c b/drivers/char/hvc_xen.c
index eba999f8598d..ae453cc25a66 100644
--- a/drivers/char/hvc_xen.c
+++ b/drivers/char/hvc_xen.c
@@ -55,7 +55,7 @@ static inline void notify_daemon(void)
 	notify_remote_via_evtchn(xen_start_info->console.domU.evtchn);
 }
 
-static int write_console(uint32_t vtermno, const char *data, int len)
+static int __write_console(const char *data, int len)
 {
 	struct xencons_interface *intf = xencons_interface();
 	XENCONS_RING_IDX cons, prod;
@@ -76,6 +76,29 @@ static int write_console(uint32_t vtermno, const char *data, int len)
 	return sent;
 }
 
+static int write_console(uint32_t vtermno, const char *data, int len)
+{
+	int ret = len;
+
+	/*
+	 * Make sure the whole buffer is emitted, polling if
+	 * necessary.  We don't ever want to rely on the hvc daemon
+	 * because the most interesting console output is when the
+	 * kernel is crippled.
+	 */
+	while (len) {
+		int sent = __write_console(data, len);
+
+		data += sent;
+		len -= sent;
+
+		if (unlikely(len))
+			HYPERVISOR_sched_op(SCHEDOP_yield, NULL);
+	}
+
+	return ret;
+}
+
 static int read_console(uint32_t vtermno, char *buf, int len)
 {
 	struct xencons_interface *intf = xencons_interface();
diff --git a/drivers/char/keyboard.c b/drivers/char/keyboard.c
index 737be953cc58..950837cf9e9c 100644
--- a/drivers/char/keyboard.c
+++ b/drivers/char/keyboard.c
@@ -1249,7 +1249,7 @@ static void kbd_keycode(unsigned int keycode, int down, int hw_raw)
 
 	if (keycode >= NR_KEYS)
 		if (keycode >= KEY_BRL_DOT1 && keycode <= KEY_BRL_DOT8)
-			keysym = K(KT_BRL, keycode - KEY_BRL_DOT1 + 1);
+			keysym = U(K(KT_BRL, keycode - KEY_BRL_DOT1 + 1));
 		else
 			return;
 	else
diff --git a/drivers/char/nozomi.c b/drivers/char/nozomi.c
index ec58d8c387ff..2171e9dac1ab 100644
--- a/drivers/char/nozomi.c
+++ b/drivers/char/nozomi.c
@@ -1628,10 +1628,10 @@ static void ntty_close(struct tty_struct *tty, struct file *file)
 
 	dc->open_ttys--;
 	port->count--;
-	tty_port_tty_set(port, NULL);
 
 	if (port->count == 0) {
 		DBG1("close: %d", nport->token_dl);
+		tty_port_tty_set(port, NULL);
 		spin_lock_irqsave(&dc->spin_mutex, flags);
 		dc->last_ier &= ~(nport->token_dl);
 		writew(dc->last_ier, dc->reg_ier);
diff --git a/drivers/char/pty.c b/drivers/char/pty.c
index b33d6688e910..53761cefa915 100644
--- a/drivers/char/pty.c
+++ b/drivers/char/pty.c
@@ -120,8 +120,10 @@ static int pty_write(struct tty_struct *tty, const unsigned char *buf, int c)
 		/* Stuff the data into the input queue of the other end */
 		c = tty_insert_flip_string(to, buf, c);
 		/* And shovel */
-		tty_flip_buffer_push(to);
-		tty_wakeup(tty);
+		if (c) {
+			tty_flip_buffer_push(to);
+			tty_wakeup(tty);
+		}
 	}
 	return c;
 }
diff --git a/drivers/char/tpm/tpm.c b/drivers/char/tpm/tpm.c
index b0603b2e5684..47c2d2763456 100644
--- a/drivers/char/tpm/tpm.c
+++ b/drivers/char/tpm/tpm.c
@@ -696,8 +696,7 @@ int __tpm_pcr_read(struct tpm_chip *chip, int pcr_idx, u8 *res_buf)
 
 	cmd.header.in = pcrread_header;
 	cmd.params.pcrread_in.pcr_idx = cpu_to_be32(pcr_idx);
-	BUILD_BUG_ON(cmd.header.in.length > READ_PCR_RESULT_SIZE);
-	rc = transmit_cmd(chip, &cmd, cmd.header.in.length,
+	rc = transmit_cmd(chip, &cmd, READ_PCR_RESULT_SIZE,
 			  "attempting to read a pcr value");
 
 	if (rc == 0)
@@ -742,7 +741,7 @@ EXPORT_SYMBOL_GPL(tpm_pcr_read);
  * the module usage count.
  */
 #define TPM_ORD_PCR_EXTEND cpu_to_be32(20)
-#define EXTEND_PCR_SIZE 34
+#define EXTEND_PCR_RESULT_SIZE 34
 static struct tpm_input_header pcrextend_header = {
 	.tag = TPM_TAG_RQU_COMMAND,
 	.length = cpu_to_be32(34),
@@ -760,10 +759,9 @@ int tpm_pcr_extend(u32 chip_num, int pcr_idx, const u8 *hash)
 		return -ENODEV;
 
 	cmd.header.in = pcrextend_header;
-	BUILD_BUG_ON(be32_to_cpu(cmd.header.in.length) > EXTEND_PCR_SIZE);
 	cmd.params.pcrextend_in.pcr_idx = cpu_to_be32(pcr_idx);
 	memcpy(cmd.params.pcrextend_in.hash, hash, TPM_DIGEST_SIZE);
-	rc = transmit_cmd(chip, &cmd, cmd.header.in.length,
+	rc = transmit_cmd(chip, &cmd, EXTEND_PCR_RESULT_SIZE,
 			  "attempting extend a PCR value");
 
 	module_put(chip->dev->driver->owner);
diff --git a/drivers/char/tpm/tpm_tis.c b/drivers/char/tpm/tpm_tis.c
index aec1931608aa..0b73e4ec1add 100644
--- a/drivers/char/tpm/tpm_tis.c
+++ b/drivers/char/tpm/tpm_tis.c
@@ -450,6 +450,12 @@ static int tpm_tis_init(struct device *dev, resource_size_t start,
 		goto out_err;
 	}
 
+	/* Default timeouts */
+	chip->vendor.timeout_a = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
+	chip->vendor.timeout_b = msecs_to_jiffies(TIS_LONG_TIMEOUT);
+	chip->vendor.timeout_c = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
+	chip->vendor.timeout_d = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
+
 	if (request_locality(chip, 0) != 0) {
 		rc = -ENODEV;
 		goto out_err;
@@ -457,12 +463,6 @@ static int tpm_tis_init(struct device *dev, resource_size_t start,
 
 	vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
 
-	/* Default timeouts */
-	chip->vendor.timeout_a = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
-	chip->vendor.timeout_b = msecs_to_jiffies(TIS_LONG_TIMEOUT);
-	chip->vendor.timeout_c = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
-	chip->vendor.timeout_d = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
-
 	dev_info(dev,
 		 "1.2 TPM (device-id 0x%X, rev-id %d)\n",
 		 vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0)));
diff --git a/drivers/char/tty_buffer.c b/drivers/char/tty_buffer.c
index 3108991c5c8b..0296612cc7df 100644
--- a/drivers/char/tty_buffer.c
+++ b/drivers/char/tty_buffer.c
@@ -402,28 +402,26 @@ static void flush_to_ldisc(struct work_struct *work)
 		container_of(work, struct tty_struct, buf.work.work);
 	unsigned long 	flags;
 	struct tty_ldisc *disc;
-	struct tty_buffer *tbuf, *head;
-	char *char_buf;
-	unsigned char *flag_buf;
 
 	disc = tty_ldisc_ref(tty);
 	if (disc == NULL)	/*  !TTY_LDISC */
 		return;
 
 	spin_lock_irqsave(&tty->buf.lock, flags);
-	/* So we know a flush is running */
-	set_bit(TTY_FLUSHING, &tty->flags);
-	head = tty->buf.head;
-	if (head != NULL) {
-		tty->buf.head = NULL;
-		for (;;) {
-			int count = head->commit - head->read;
+
+	if (!test_and_set_bit(TTY_FLUSHING, &tty->flags)) {
+		struct tty_buffer *head;
+		while ((head = tty->buf.head) != NULL) {
+			int count;
+			char *char_buf;
+			unsigned char *flag_buf;
+
+			count = head->commit - head->read;
 			if (!count) {
 				if (head->next == NULL)
 					break;
-				tbuf = head;
-				head = head->next;
-				tty_buffer_free(tty, tbuf);
+				tty->buf.head = head->next;
+				tty_buffer_free(tty, head);
 				continue;
 			}
 			/* Ldisc or user is trying to flush the buffers
@@ -445,9 +443,9 @@ static void flush_to_ldisc(struct work_struct *work)
 							flag_buf, count);
 			spin_lock_irqsave(&tty->buf.lock, flags);
 		}
-		/* Restore the queue head */
-		tty->buf.head = head;
+		clear_bit(TTY_FLUSHING, &tty->flags);
 	}
+
 	/* We may have a deferred request to flush the input buffer,
 	   if so pull the chain under the lock and empty the queue */
 	if (test_bit(TTY_FLUSHPENDING, &tty->flags)) {
@@ -455,7 +453,6 @@ static void flush_to_ldisc(struct work_struct *work)
 		clear_bit(TTY_FLUSHPENDING, &tty->flags);
 		wake_up(&tty->read_wait);
 	}
-	clear_bit(TTY_FLUSHING, &tty->flags);
 	spin_unlock_irqrestore(&tty->buf.lock, flags);
 
 	tty_ldisc_deref(disc);
diff --git a/drivers/char/tty_io.c b/drivers/char/tty_io.c
index a3afa0c387cd..9531cf8b3482 100644
--- a/drivers/char/tty_io.c
+++ b/drivers/char/tty_io.c
@@ -1184,6 +1184,7 @@ int tty_init_termios(struct tty_struct *tty)
 	tty->termios->c_ospeed = tty_termios_baud_rate(tty->termios);
 	return 0;
 }
+EXPORT_SYMBOL_GPL(tty_init_termios);
 
 /**
  *	tty_driver_install_tty() - install a tty entry in the driver
@@ -1911,8 +1912,10 @@ static int tty_fasync(int fd, struct file *filp, int on)
 			pid = task_pid(current);
 			type = PIDTYPE_PID;
 		}
+		get_pid(pid);
 		spin_unlock_irqrestore(&tty->ctrl_lock, flags);
 		retval = __f_setown(filp, pid, type, 0);
+		put_pid(pid);
 		if (retval)
 			goto out;
 	} else {
diff --git a/drivers/char/tty_ldisc.c b/drivers/char/tty_ldisc.c
index e48af9f79219..414372a442d9 100644
--- a/drivers/char/tty_ldisc.c
+++ b/drivers/char/tty_ldisc.c
@@ -516,7 +516,7 @@ static void tty_ldisc_restore(struct tty_struct *tty, struct tty_ldisc *old)
 static int tty_ldisc_halt(struct tty_struct *tty)
 {
 	clear_bit(TTY_LDISC, &tty->flags);
-	return cancel_delayed_work(&tty->buf.work);
+	return cancel_delayed_work_sync(&tty->buf.work);
 }
 
 /**
@@ -754,12 +754,9 @@ void tty_ldisc_hangup(struct tty_struct *tty)
 	 * N_TTY.
 	 */
 	if (tty->driver->flags & TTY_DRIVER_RESET_TERMIOS) {
-		/* Make sure the old ldisc is quiescent */
-		tty_ldisc_halt(tty);
-		flush_scheduled_work();
-
 		/* Avoid racing set_ldisc or tty_ldisc_release */
 		mutex_lock(&tty->ldisc_mutex);
+		tty_ldisc_halt(tty);
 		if (tty->ldisc) {	/* Not yet closed */
 			/* Switch back to N_TTY */
 			tty_ldisc_reinit(tty);
diff --git a/drivers/char/tty_port.c b/drivers/char/tty_port.c
index 9769b1149f76..c0ff7eeafbb2 100644
--- a/drivers/char/tty_port.c
+++ b/drivers/char/tty_port.c
@@ -96,6 +96,14 @@ void tty_port_tty_set(struct tty_port *port, struct tty_struct *tty)
 }
 EXPORT_SYMBOL(tty_port_tty_set);
 
+static void tty_port_shutdown(struct tty_port *port)
+{
+	if (port->ops->shutdown &&
+		test_and_clear_bit(ASYNCB_INITIALIZED, &port->flags))
+			port->ops->shutdown(port);
+
+}
+
 /**
  *	tty_port_hangup		-	hangup helper
  *	@port: tty port
@@ -116,6 +124,7 @@ void tty_port_hangup(struct tty_port *port)
 	port->tty = NULL;
 	spin_unlock_irqrestore(&port->lock, flags);
 	wake_up_interruptible(&port->open_wait);
+	tty_port_shutdown(port);
 }
 EXPORT_SYMBOL(tty_port_hangup);
 
@@ -208,8 +217,14 @@ int tty_port_block_til_ready(struct tty_port *port,
 
 	/* if non-blocking mode is set we can pass directly to open unless
 	   the port has just hung up or is in another error state */
-	if ((filp->f_flags & O_NONBLOCK) ||
-			(tty->flags & (1 << TTY_IO_ERROR))) {
+	if (tty->flags & (1 << TTY_IO_ERROR)) {
+		port->flags |= ASYNC_NORMAL_ACTIVE;
+		return 0;
+	}
+	if (filp->f_flags & O_NONBLOCK) {
+		/* Indicate we are open */
+		if (tty->termios->c_cflag & CBAUD)
+			tty_port_raise_dtr_rts(port);
 		port->flags |= ASYNC_NORMAL_ACTIVE;
 		return 0;
 	}
@@ -296,15 +311,17 @@ int tty_port_close_start(struct tty_port *port, struct tty_struct *tty, struct f
 
 	if (port->count) {
 		spin_unlock_irqrestore(&port->lock, flags);
+		if (port->ops->drop)
+			port->ops->drop(port);
 		return 0;
 	}
-	port->flags |= ASYNC_CLOSING;
+	set_bit(ASYNCB_CLOSING, &port->flags);
 	tty->closing = 1;
 	spin_unlock_irqrestore(&port->lock, flags);
 	/* Don't block on a stalled port, just pull the chain */
 	if (tty->flow_stopped)
 		tty_driver_flush_buffer(tty);
-	if (port->flags & ASYNC_INITIALIZED &&
+	if (test_bit(ASYNCB_INITIALIZED, &port->flags) &&
 			port->closing_wait != ASYNC_CLOSING_WAIT_NONE)
 		tty_wait_until_sent(tty, port->closing_wait);
 	if (port->drain_delay) {
@@ -318,6 +335,9 @@ int tty_port_close_start(struct tty_port *port, struct tty_struct *tty, struct f
 			timeout = 2 * HZ;
 		schedule_timeout_interruptible(timeout);
 	}
+	/* Don't call port->drop for the last reference. Callers will want
+	   to drop the last active reference in ->shutdown() or the tty
+	   shutdown path */
 	return 1;
 }
 EXPORT_SYMBOL(tty_port_close_start);
@@ -348,3 +368,14 @@ void tty_port_close_end(struct tty_port *port, struct tty_struct *tty)
 	spin_unlock_irqrestore(&port->lock, flags);
 }
 EXPORT_SYMBOL(tty_port_close_end);
+
+void tty_port_close(struct tty_port *port, struct tty_struct *tty,
+							struct file *filp)
+{
+	if (tty_port_close_start(port, tty, filp) == 0)
+		return;
+	tty_port_shutdown(port);
+	tty_port_close_end(port, tty);
+	tty_port_tty_set(port, NULL);
+}
+EXPORT_SYMBOL(tty_port_close);
diff --git a/drivers/char/vt.c b/drivers/char/vt.c
index 404f4c1ee431..6aa88f50b039 100644
--- a/drivers/char/vt.c
+++ b/drivers/char/vt.c
@@ -2948,9 +2948,6 @@ int __init vty_init(const struct file_operations *console_fops)
 		panic("Couldn't register console driver\n");
 	kbd_init();
 	console_map_init();
-#ifdef CONFIG_PROM_CONSOLE
-	prom_con_init();
-#endif
 #ifdef CONFIG_MDA_CONSOLE
 	mda_console_init();
 #endif
diff --git a/drivers/connector/cn_proc.c b/drivers/connector/cn_proc.c
index c5afc98e2675..9ca20d04dd5a 100644
--- a/drivers/connector/cn_proc.c
+++ b/drivers/connector/cn_proc.c
@@ -202,9 +202,8 @@ static void cn_proc_ack(int err, int rcvd_seq, int rcvd_ack)
  * cn_proc_mcast_ctl
  * @data: message sent from userspace via the connector
  */
-static void cn_proc_mcast_ctl(void *data)
+static void cn_proc_mcast_ctl(struct cn_msg *msg, struct netlink_skb_parms *nsp)
 {
-	struct cn_msg *msg = data;
 	enum proc_cn_mcast_op *mc_op = NULL;
 	int err = 0;
 
diff --git a/drivers/connector/cn_queue.c b/drivers/connector/cn_queue.c
index 408c2af25d50..210338ea222f 100644
--- a/drivers/connector/cn_queue.c
+++ b/drivers/connector/cn_queue.c
@@ -78,16 +78,20 @@ void cn_queue_wrapper(struct work_struct *work)
 	struct cn_callback_entry *cbq =
 		container_of(work, struct cn_callback_entry, work);
 	struct cn_callback_data *d = &cbq->data;
+	struct cn_msg *msg = NLMSG_DATA(nlmsg_hdr(d->skb));
+	struct netlink_skb_parms *nsp = &NETLINK_CB(d->skb);
 
-	d->callback(d->callback_priv);
+	d->callback(msg, nsp);
 
-	d->destruct_data(d->ddata);
-	d->ddata = NULL;
+	kfree_skb(d->skb);
+	d->skb = NULL;
 
 	kfree(d->free);
 }
 
-static struct cn_callback_entry *cn_queue_alloc_callback_entry(char *name, struct cb_id *id, void (*callback)(void *))
+static struct cn_callback_entry *
+cn_queue_alloc_callback_entry(char *name, struct cb_id *id,
+			      void (*callback)(struct cn_msg *, struct netlink_skb_parms *))
 {
 	struct cn_callback_entry *cbq;
 
@@ -120,7 +124,8 @@ int cn_cb_equal(struct cb_id *i1, struct cb_id *i2)
 	return ((i1->idx == i2->idx) && (i1->val == i2->val));
 }
 
-int cn_queue_add_callback(struct cn_queue_dev *dev, char *name, struct cb_id *id, void (*callback)(void *))
+int cn_queue_add_callback(struct cn_queue_dev *dev, char *name, struct cb_id *id,
+			  void (*callback)(struct cn_msg *, struct netlink_skb_parms *))
 {
 	struct cn_callback_entry *cbq, *__cbq;
 	int found = 0;
diff --git a/drivers/connector/connector.c b/drivers/connector/connector.c
index 08b2500f21ec..537c29ac4487 100644
--- a/drivers/connector/connector.c
+++ b/drivers/connector/connector.c
@@ -36,17 +36,6 @@ MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Evgeniy Polyakov <zbr@ioremap.net>");
 MODULE_DESCRIPTION("Generic userspace <-> kernelspace connector.");
 
-static u32 cn_idx = CN_IDX_CONNECTOR;
-static u32 cn_val = CN_VAL_CONNECTOR;
-
-module_param(cn_idx, uint, 0);
-module_param(cn_val, uint, 0);
-MODULE_PARM_DESC(cn_idx, "Connector's main device idx.");
-MODULE_PARM_DESC(cn_val, "Connector's main device val.");
-
-static DEFINE_MUTEX(notify_lock);
-static LIST_HEAD(notify_list);
-
 static struct cn_dev cdev;
 
 static int cn_already_initialized;
@@ -129,21 +118,19 @@ EXPORT_SYMBOL_GPL(cn_netlink_send);
 /*
  * Callback helper - queues work and setup destructor for given data.
  */
-static int cn_call_callback(struct cn_msg *msg, void (*destruct_data)(void *), void *data)
+static int cn_call_callback(struct sk_buff *skb)
 {
 	struct cn_callback_entry *__cbq, *__new_cbq;
 	struct cn_dev *dev = &cdev;
+	struct cn_msg *msg = NLMSG_DATA(nlmsg_hdr(skb));
 	int err = -ENODEV;
 
 	spin_lock_bh(&dev->cbdev->queue_lock);
 	list_for_each_entry(__cbq, &dev->cbdev->queue_list, callback_entry) {
 		if (cn_cb_equal(&__cbq->id.id, &msg->id)) {
 			if (likely(!work_pending(&__cbq->work) &&
-					__cbq->data.ddata == NULL)) {
-				__cbq->data.callback_priv = msg;
-
-				__cbq->data.ddata = data;
-				__cbq->data.destruct_data = destruct_data;
+					__cbq->data.skb == NULL)) {
+				__cbq->data.skb = skb;
 
 				if (queue_cn_work(__cbq, &__cbq->work))
 					err = 0;
@@ -156,10 +143,8 @@ static int cn_call_callback(struct cn_msg *msg, void (*destruct_data)(void *), v
 				__new_cbq = kzalloc(sizeof(struct cn_callback_entry), GFP_ATOMIC);
 				if (__new_cbq) {
 					d = &__new_cbq->data;
-					d->callback_priv = msg;
+					d->skb = skb;
 					d->callback = __cbq->data.callback;
-					d->ddata = data;
-					d->destruct_data = destruct_data;
 					d->free = __new_cbq;
 
 					__new_cbq->pdev = __cbq->pdev;
@@ -191,7 +176,6 @@ static int cn_call_callback(struct cn_msg *msg, void (*destruct_data)(void *), v
  */
 static void cn_rx_skb(struct sk_buff *__skb)
 {
-	struct cn_msg *msg;
 	struct nlmsghdr *nlh;
 	int err;
 	struct sk_buff *skb;
@@ -208,68 +192,20 @@ static void cn_rx_skb(struct sk_buff *__skb)
 			return;
 		}
 
-		msg = NLMSG_DATA(nlh);
-		err = cn_call_callback(msg, (void (*)(void *))kfree_skb, skb);
+		err = cn_call_callback(skb);
 		if (err < 0)
 			kfree_skb(skb);
 	}
 }
 
 /*
- * Notification routing.
- *
- * Gets id and checks if there are notification request for it's idx
- * and val.  If there are such requests notify the listeners with the
- * given notify event.
- *
- */
-static void cn_notify(struct cb_id *id, u32 notify_event)
-{
-	struct cn_ctl_entry *ent;
-
-	mutex_lock(&notify_lock);
-	list_for_each_entry(ent, &notify_list, notify_entry) {
-		int i;
-		struct cn_notify_req *req;
-		struct cn_ctl_msg *ctl = ent->msg;
-		int idx_found, val_found;
-
-		idx_found = val_found = 0;
-
-		req = (struct cn_notify_req *)ctl->data;
-		for (i = 0; i < ctl->idx_notify_num; ++i, ++req) {
-			if (id->idx >= req->first &&
-					id->idx < req->first + req->range) {
-				idx_found = 1;
-				break;
-			}
-		}
-
-		for (i = 0; i < ctl->val_notify_num; ++i, ++req) {
-			if (id->val >= req->first &&
-					id->val < req->first + req->range) {
-				val_found = 1;
-				break;
-			}
-		}
-
-		if (idx_found && val_found) {
-			struct cn_msg m = { .ack = notify_event, };
-
-			memcpy(&m.id, id, sizeof(m.id));
-			cn_netlink_send(&m, ctl->group, GFP_KERNEL);
-		}
-	}
-	mutex_unlock(&notify_lock);
-}
-
-/*
  * Callback add routing - adds callback with given ID and name.
  * If there is registered callback with the same ID it will not be added.
  *
  * May sleep.
  */
-int cn_add_callback(struct cb_id *id, char *name, void (*callback)(void *))
+int cn_add_callback(struct cb_id *id, char *name,
+		    void (*callback)(struct cn_msg *, struct netlink_skb_parms *))
 {
 	int err;
 	struct cn_dev *dev = &cdev;
@@ -281,8 +217,6 @@ int cn_add_callback(struct cb_id *id, char *name, void (*callback)(void *))
 	if (err)
 		return err;
 
-	cn_notify(id, 0);
-
 	return 0;
 }
 EXPORT_SYMBOL_GPL(cn_add_callback);
@@ -300,112 +234,9 @@ void cn_del_callback(struct cb_id *id)
 	struct cn_dev *dev = &cdev;
 
 	cn_queue_del_callback(dev->cbdev, id);
-	cn_notify(id, 1);
 }
 EXPORT_SYMBOL_GPL(cn_del_callback);
 
-/*
- * Checks two connector's control messages to be the same.
- * Returns 1 if they are the same or if the first one is corrupted.
- */
-static int cn_ctl_msg_equals(struct cn_ctl_msg *m1, struct cn_ctl_msg *m2)
-{
-	int i;
-	struct cn_notify_req *req1, *req2;
-
-	if (m1->idx_notify_num != m2->idx_notify_num)
-		return 0;
-
-	if (m1->val_notify_num != m2->val_notify_num)
-		return 0;
-
-	if (m1->len != m2->len)
-		return 0;
-
-	if ((m1->idx_notify_num + m1->val_notify_num) * sizeof(*req1) !=
-	    m1->len)
-		return 1;
-
-	req1 = (struct cn_notify_req *)m1->data;
-	req2 = (struct cn_notify_req *)m2->data;
-
-	for (i = 0; i < m1->idx_notify_num; ++i) {
-		if (req1->first != req2->first || req1->range != req2->range)
-			return 0;
-		req1++;
-		req2++;
-	}
-
-	for (i = 0; i < m1->val_notify_num; ++i) {
-		if (req1->first != req2->first || req1->range != req2->range)
-			return 0;
-		req1++;
-		req2++;
-	}
-
-	return 1;
-}
-
-/*
- * Main connector device's callback.
- *
- * Used for notification of a request's processing.
- */
-static void cn_callback(void *data)
-{
-	struct cn_msg *msg = data;
-	struct cn_ctl_msg *ctl;
-	struct cn_ctl_entry *ent;
-	u32 size;
-
-	if (msg->len < sizeof(*ctl))
-		return;
-
-	ctl = (struct cn_ctl_msg *)msg->data;
-
-	size = (sizeof(*ctl) + ((ctl->idx_notify_num +
-				 ctl->val_notify_num) *
-				sizeof(struct cn_notify_req)));
-
-	if (msg->len != size)
-		return;
-
-	if (ctl->len + sizeof(*ctl) != msg->len)
-		return;
-
-	/*
-	 * Remove notification.
-	 */
-	if (ctl->group == 0) {
-		struct cn_ctl_entry *n;
-
-		mutex_lock(&notify_lock);
-		list_for_each_entry_safe(ent, n, &notify_list, notify_entry) {
-			if (cn_ctl_msg_equals(ent->msg, ctl)) {
-				list_del(&ent->notify_entry);
-				kfree(ent);
-			}
-		}
-		mutex_unlock(&notify_lock);
-
-		return;
-	}
-
-	size += sizeof(*ent);
-
-	ent = kzalloc(size, GFP_KERNEL);
-	if (!ent)
-		return;
-
-	ent->msg = (struct cn_ctl_msg *)(ent + 1);
-
-	memcpy(ent->msg, ctl, size - sizeof(*ent));
-
-	mutex_lock(&notify_lock);
-	list_add(&ent->notify_entry, &notify_list);
-	mutex_unlock(&notify_lock);
-}
-
 static int cn_proc_show(struct seq_file *m, void *v)
 {
 	struct cn_queue_dev *dev = cdev.cbdev;
@@ -443,11 +274,8 @@ static const struct file_operations cn_file_ops = {
 static int __devinit cn_init(void)
 {
 	struct cn_dev *dev = &cdev;
-	int err;
 
 	dev->input = cn_rx_skb;
-	dev->id.idx = cn_idx;
-	dev->id.val = cn_val;
 
 	dev->nls = netlink_kernel_create(&init_net, NETLINK_CONNECTOR,
 					 CN_NETLINK_USERS + 0xf,
@@ -463,14 +291,6 @@ static int __devinit cn_init(void)
 
 	cn_already_initialized = 1;
 
-	err = cn_add_callback(&dev->id, "connector", &cn_callback);
-	if (err) {
-		cn_already_initialized = 0;
-		cn_queue_free_dev(dev->cbdev);
-		netlink_kernel_release(dev->nls);
-		return -EINVAL;
-	}
-
 	proc_net_fops_create(&init_net, "connector", S_IRUGO, &cn_file_ops);
 
 	return 0;
@@ -484,7 +304,6 @@ static void __devexit cn_fini(void)
 
 	proc_net_remove(&init_net, "connector");
 
-	cn_del_callback(&dev->id);
 	cn_queue_free_dev(dev->cbdev);
 	netlink_kernel_release(dev->nls);
 }
diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index 8504a2108557..910c49d2641c 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -75,8 +75,11 @@ static void cpuidle_idle_call(void)
 #endif
 	/* ask the governor for the next state */
 	next_state = cpuidle_curr_governor->select(dev);
-	if (need_resched())
+	if (need_resched()) {
+		local_irq_enable();
 		return;
+	}
+
 	target_state = &dev->states[next_state];
 
 	/* enter the state and update stats */
diff --git a/drivers/crypto/dcp.c b/drivers/crypto/dcp.c
index a72d73382778..8b54b127d6d0 100644
--- a/drivers/crypto/dcp.c
+++ b/drivers/crypto/dcp.c
@@ -17,10 +17,16 @@
 
 #include <linux/module.h>
 #include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/sysdev.h>
+#include <linux/bitops.h>
 #include <linux/crypto.h>
 #include <linux/spinlock.h>
+#include <linux/miscdevice.h>
 #include <linux/platform_device.h>
 #include <linux/err.h>
+#include <linux/sysfs.h>
+#include <linux/fs.h>
 #include <crypto/algapi.h>
 #include <crypto/aes.h>
 #include <crypto/sha.h>
@@ -29,6 +35,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/interrupt.h>
 #include <linux/delay.h>
+#include <linux/uaccess.h>
 
 #include <linux/io.h>
 #include <linux/delay.h>
@@ -36,6 +43,13 @@
 #include <asm/cacheflush.h>
 #include <mach/hardware.h>
 #include "dcp.h"
+#include "dcp_bootstream_ioctl.h"
+
+/* Following data only used by DCP bootstream interface */
+struct dcpboot_dma_area {
+	struct dcp_hw_packet hw_packet;
+	uint16_t block[16];
+};
 
 struct dcp {
 	struct device *dev;
@@ -55,6 +69,10 @@ struct dcp {
 	struct dcp_hash_coherent_block *buf1_desc;
 	struct dcp_hash_coherent_block *buf2_desc;
 	struct dcp_hash_coherent_block *user_buf_desc;
+
+	/* Following data only used by DCP bootstream interface */
+	struct dcpboot_dma_area *dcpboot_dma_area;
+	dma_addr_t dcpboot_dma_area_phys;
 };
 
 /* cipher flags */
@@ -1245,6 +1263,106 @@ static irqreturn_t dcp_irq(int irq, void *context)
 	return dcp_common_irq(irq, context);
 }
 
+/* DCP bootstream verification interface: uses OTP key for crypto */
+static int dcp_bootstream_ioctl(struct inode *inode, struct file *file,
+					 unsigned int cmd, unsigned long arg)
+{
+	struct dcp *sdcp = global_sdcp;
+	struct dcpboot_dma_area *da = sdcp->dcpboot_dma_area;
+	void __user *argp = (void __user *)arg;
+	int chan = ROM_DCP_CHAN;
+	unsigned long timeout;
+	struct mutex *mutex;
+	int retVal;
+
+	/* be paranoid */
+	if (sdcp == NULL)
+		return -EBADF;
+
+	if (cmd != DBS_ENC && cmd != DBS_DEC)
+		return -EINVAL;
+
+	/* copy to (aligned) block */
+	if (copy_from_user(da->block, argp, 16))
+		return -EFAULT;
+
+	mutex = &sdcp->op_mutex[chan];
+	mutex_lock(mutex);
+
+	__raw_writel(-1, sdcp->dcp_regs_base +
+		HW_DCP_CHnSTAT_CLR(ROM_DCP_CHAN));
+	__raw_writel(BF(ROM_DCP_CHAN_MASK, DCP_STAT_IRQ),
+		sdcp->dcp_regs_base + HW_DCP_STAT_CLR);
+
+	da->hw_packet.pNext = 0;
+	da->hw_packet.pkt1 = BM_DCP_PACKET1_DECR_SEMAPHORE |
+	    BM_DCP_PACKET1_ENABLE_CIPHER | BM_DCP_PACKET1_OTP_KEY |
+	    BM_DCP_PACKET1_INTERRUPT |
+	    (cmd == DBS_ENC ? BM_DCP_PACKET1_CIPHER_ENCRYPT : 0);
+	da->hw_packet.pkt2 = BF(0, DCP_PACKET2_CIPHER_CFG) |
+	    BF(0, DCP_PACKET2_KEY_SELECT) |
+	    BF(BV_DCP_PACKET2_CIPHER_MODE__ECB, DCP_PACKET2_CIPHER_MODE) |
+	    BF(BV_DCP_PACKET2_CIPHER_SELECT__AES128, DCP_PACKET2_CIPHER_SELECT);
+	da->hw_packet.pSrc = sdcp->dcpboot_dma_area_phys +
+	    offsetof(struct dcpboot_dma_area, block);
+	da->hw_packet.pDst = da->hw_packet.pSrc;	/* in-place */
+	da->hw_packet.size = 16;
+	da->hw_packet.pPayload = 0;
+	da->hw_packet.stat = 0;
+
+	/* Load the work packet pointer and bump the channel semaphore */
+	__raw_writel(sdcp->dcpboot_dma_area_phys +
+		     offsetof(struct dcpboot_dma_area, hw_packet),
+		     sdcp->dcp_regs_base + HW_DCP_CHnCMDPTR(ROM_DCP_CHAN));
+
+	sdcp->wait[chan] = 0;
+	__raw_writel(BF(1, DCP_CHnSEMA_INCREMENT),
+		     sdcp->dcp_regs_base + HW_DCP_CHnSEMA(ROM_DCP_CHAN));
+
+	timeout = jiffies + msecs_to_jiffies(100);
+
+	while (time_before(jiffies, timeout) && sdcp->wait[chan] == 0)
+		cpu_relax();
+
+	if (!time_before(jiffies, timeout)) {
+		dev_err(sdcp->dev,
+			"Timeout while waiting for operation to complete\n");
+		retVal = -ETIMEDOUT;
+		goto exit;
+	}
+
+	if ((__raw_readl(sdcp->dcp_regs_base + HW_DCP_CHnSTAT(ROM_DCP_CHAN))
+			& 0xff) != 0) {
+		dev_err(sdcp->dev, "Channel stat error 0x%02x\n",
+			__raw_readl(sdcp->dcp_regs_base +
+				    HW_DCP_CHnSTAT(ROM_DCP_CHAN)) & 0xff);
+		retVal = -EFAULT;
+		goto exit;
+	}
+
+	if (copy_to_user(argp, da->block, 16)) {
+		retVal =  -EFAULT;
+		goto exit;
+	}
+
+	retVal = 0;
+
+exit:
+	mutex_unlock(mutex);
+	return retVal;
+}
+
+static const struct file_operations dcp_bootstream_fops = {
+	.owner =	THIS_MODULE,
+	.ioctl =	dcp_bootstream_ioctl,
+};
+
+static struct miscdevice dcp_bootstream_misc = {
+	.minor	= MISC_DYNAMIC_MINOR,
+	.name	= "dcpboot",
+	.fops = &dcp_bootstream_fops,
+};
+
 static int dcp_probe(struct platform_device *pdev)
 {
 	struct dcp *sdcp = NULL;
@@ -1439,9 +1557,29 @@ static int dcp_probe(struct platform_device *pdev)
 		}
 	}
 
+	/* register dcpboot interface to allow apps (such as kobs-ng) to
+	 * verify files (such as the bootstream) using the OTP key for crypto */
+	ret = misc_register(&dcp_bootstream_misc);
+	if (ret != 0) {
+		dev_err(&pdev->dev, "Unable to register misc device\n");
+		goto err_unregister_sha1;
+	}
+
+	sdcp->dcpboot_dma_area = dma_alloc_coherent(&pdev->dev,
+		sizeof(*sdcp->dcpboot_dma_area), &sdcp->dcpboot_dma_area_phys,
+		GFP_KERNEL);
+	if (sdcp->dcpboot_dma_area == NULL) {
+		dev_err(&pdev->dev,
+			"Unable to allocate DMAable memory \
+			 for dcpboot interface\n");
+		goto err_dereg;
+	}
+
 	dev_notice(&pdev->dev, "DCP crypto enabled.!\n");
 	return 0;
 
+err_dereg:
+	misc_deregister(&dcp_bootstream_misc);
 err_unregister_sha1:
 	crypto_unregister_shash(&dcp_sha1_alg);
 err_unregister_aes_cbc:
@@ -1487,8 +1625,19 @@ static int dcp_remove(struct platform_device *pdev)
 			sdcp->user_buf_desc, sdcp->user_buf_desc->my_phys);
 	}
 
+	if (sdcp->dcpboot_dma_area) {
+		dma_free_coherent(&pdev->dev, sizeof(*sdcp->dcpboot_dma_area),
+			  sdcp->dcpboot_dma_area, sdcp->dcpboot_dma_area_phys);
+		misc_deregister(&dcp_bootstream_misc);
+	}
+
+
 	crypto_unregister_shash(&dcp_sha1_alg);
-	crypto_unregister_shash(&dcp_sha256_alg);
+
+	if (__raw_readl(sdcp->dcp_regs_base + HW_DCP_CAPABILITY1) &
+		BF_DCP_CAPABILITY1_HASH_ALGORITHMS(
+		BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA256))
+		crypto_unregister_shash(&dcp_sha256_alg);
 
 	crypto_unregister_alg(&dcp_aes_cbc_alg);
 	crypto_unregister_alg(&dcp_aes_ecb_alg);
diff --git a/drivers/crypto/dcp.h b/drivers/crypto/dcp.h
index 00cd27b479c0..a4db91334d06 100644
--- a/drivers/crypto/dcp.h
+++ b/drivers/crypto/dcp.h
@@ -19,7 +19,12 @@
 #define HASH_CHAN	0
 #define HASH_MASK	(1 << HASH_CHAN)
 
-#define ALL_MASK	(CIPHER_MASK | HASH_MASK)
+/* DCP boostream interface uses this channel (same as the ROM) */
+#define ROM_DCP_CHAN 3
+#define ROM_DCP_CHAN_MASK (1 << ROM_DCP_CHAN)
+
+
+#define ALL_MASK	(CIPHER_MASK | HASH_MASK | ROM_DCP_CHAN_MASK)
 
 /* Defines the initialization value for the dcp control register */
 #define DCP_CTRL_INIT \
diff --git a/drivers/crypto/dcp_bootstream_ioctl.h b/drivers/crypto/dcp_bootstream_ioctl.h
new file mode 100644
index 000000000000..7c0c07d5a72d
--- /dev/null
+++ b/drivers/crypto/dcp_bootstream_ioctl.h
@@ -0,0 +1,32 @@
+/*
+ * Freescale DCP driver for bootstream update. Only handles the OTP KEY
+ * case and can only encrypt/decrypt.
+ *
+ * Author: Pantelis Antoniou <pantelis@embeddedalley.com>
+ *
+ * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef DCP_BOOTSTREAM_IOCTL_H
+#define DCP_BOOTSTREAM_IOCTL_H
+
+/* remember to have included the proper _IO definition
+ * file before hand.
+ * For user space it's <sys/ioctl.h>
+ */
+
+#define DBS_IOCTL_BASE   'd'
+
+#define DBS_ENC	_IOW(DBS_IOCTL_BASE, 0x00, uint8_t[16])
+#define DBS_DEC _IOW(DBS_IOCTL_BASE, 0x01, uint8_t[16])
+
+#endif
diff --git a/drivers/crypto/padlock-aes.c b/drivers/crypto/padlock-aes.c
index a9952b1236b0..84c51e177269 100644
--- a/drivers/crypto/padlock-aes.c
+++ b/drivers/crypto/padlock-aes.c
@@ -236,7 +236,7 @@ static inline void ecb_crypt(const u8 *in, u8 *out, u32 *key,
 	/* Padlock in ECB mode fetches at least ecb_fetch_bytes of data.
 	 * We could avoid some copying here but it's probably not worth it.
 	 */
-	if (unlikely(((unsigned long)in & PAGE_SIZE) + ecb_fetch_bytes > PAGE_SIZE)) {
+	if (unlikely(((unsigned long)in & ~PAGE_MASK) + ecb_fetch_bytes > PAGE_SIZE)) {
 		ecb_crypt_copy(in, out, key, cword, count);
 		return;
 	}
@@ -248,7 +248,7 @@ static inline u8 *cbc_crypt(const u8 *in, u8 *out, u32 *key,
 			    u8 *iv, struct cword *cword, int count)
 {
 	/* Padlock in CBC mode fetches at least cbc_fetch_bytes of data. */
-	if (unlikely(((unsigned long)in & PAGE_SIZE) + cbc_fetch_bytes > PAGE_SIZE))
+	if (unlikely(((unsigned long)in & ~PAGE_MASK) + cbc_fetch_bytes > PAGE_SIZE))
 		return cbc_crypt_copy(in, out, key, iv, cword, count);
 
 	return rep_xcrypt_cbc(in, out, key, iv, cword, count);
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 81e1020fb514..27e06ebc2a59 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -89,6 +89,15 @@ config MX3_IPU_IRQS
 	  To avoid bloating the irq_desc[] array we allocate a sufficient
 	  number of IRQ slots and map them dynamically to specific sources.
 
+config MXC_PXP
+    bool "MXC PxP support"
+    select DMA_ENGINE
+
+config MXC_PXP_CLIENT_DEVICE
+    bool "MXC PxP Client Device"
+    default y
+    depends on MXC_PXP
+
 config TXX9_DMAC
 	tristate "Toshiba TXx9 SoC DMA support"
 	depends on MACH_TX49XX || MACH_TX39XX
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 40e1e0083571..72c212ac6b79 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_MV_XOR) += mv_xor.o
 obj-$(CONFIG_DW_DMAC) += dw_dmac.o
 obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
 obj-$(CONFIG_MX3_IPU) += ipu/
+obj-$(CONFIG_MXC_PXP) += pxp/
 obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index 9a1e5fb412ed..73957fb9db5f 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -813,7 +813,7 @@ atc_is_tx_complete(struct dma_chan *chan,
 	dev_vdbg(chan2dev(chan), "is_tx_complete: %d (d%d, u%d)\n",
 			cookie, done ? *done : 0, used ? *used : 0);
 
-	spin_lock_bh(atchan->lock);
+	spin_lock_bh(&atchan->lock);
 
 	last_complete = atchan->completed_cookie;
 	last_used = chan->cookie;
@@ -828,7 +828,7 @@ atc_is_tx_complete(struct dma_chan *chan,
 		ret = dma_async_is_complete(cookie, last_complete, last_used);
 	}
 
-	spin_unlock_bh(atchan->lock);
+	spin_unlock_bh(&atchan->lock);
 
 	if (done)
 		*done = last_complete;
diff --git a/drivers/dma/pxp/Makefile b/drivers/dma/pxp/Makefile
new file mode 100644
index 000000000000..88e51a7fb1e2
--- /dev/null
+++ b/drivers/dma/pxp/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_MXC_PXP) += pxp_dma.o
+obj-$(CONFIG_MXC_PXP_CLIENT_DEVICE) += pxp_device.o
diff --git a/drivers/dma/pxp/pxp_device.c b/drivers/dma/pxp/pxp_device.c
new file mode 100644
index 000000000000..afd08ac6587c
--- /dev/null
+++ b/drivers/dma/pxp/pxp_device.c
@@ -0,0 +1,513 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+#include <linux/interrupt.h>
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/pxp_dma.h>
+
+#include <asm/atomic.h>
+
+static atomic_t open_count = ATOMIC_INIT(0);
+
+static DEFINE_SPINLOCK(pxp_mem_lock);
+static DEFINE_SPINLOCK(pxp_chan_lock);
+static LIST_HEAD(head);
+static LIST_HEAD(list);
+static struct pxp_irq_info irq_info[NR_PXP_VIRT_CHANNEL];
+
+struct pxp_chan_handle {
+	int chan_id;
+	int hist_status;
+};
+
+/* To track the allocated memory buffer */
+struct memalloc_record {
+	struct list_head list;
+	struct pxp_mem_desc mem;
+};
+
+struct pxp_chan_info {
+	int chan_id;
+	struct dma_chan *dma_chan;
+	struct list_head list;
+};
+
+static int pxp_alloc_dma_buffer(struct pxp_mem_desc *mem)
+{
+	mem->cpu_addr = (unsigned long)
+	    dma_alloc_coherent(NULL, PAGE_ALIGN(mem->size),
+			       (dma_addr_t *) (&mem->phys_addr),
+			       GFP_DMA | GFP_KERNEL);
+	pr_debug("[ALLOC] mem alloc phys_addr = 0x%x\n", mem->phys_addr);
+	if ((void *)(mem->cpu_addr) == NULL) {
+		printk(KERN_ERR "Physical memory allocation error!\n");
+		return -1;
+	}
+	return 0;
+}
+
+static void pxp_free_dma_buffer(struct pxp_mem_desc *mem)
+{
+	if (mem->cpu_addr != 0) {
+		dma_free_coherent(0, PAGE_ALIGN(mem->size),
+				  (void *)mem->cpu_addr, mem->phys_addr);
+	}
+}
+
+static int pxp_free_buffers(void)
+{
+	struct memalloc_record *rec, *n;
+	struct pxp_mem_desc mem;
+
+	list_for_each_entry_safe(rec, n, &head, list) {
+		mem = rec->mem;
+		if (mem.cpu_addr != 0) {
+			pxp_free_dma_buffer(&mem);
+			pr_debug("[FREE] freed paddr=0x%08X\n", mem.phys_addr);
+			/* delete from list */
+			list_del(&rec->list);
+			kfree(rec);
+		}
+	}
+
+	return 0;
+}
+
+/* Callback function triggered after PxP receives an EOF interrupt */
+static void pxp_dma_done(void *arg)
+{
+	struct pxp_tx_desc *tx_desc = to_tx_desc(arg);
+	struct dma_chan *chan = tx_desc->txd.chan;
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+	int chan_id = pxp_chan->dma_chan.chan_id;
+
+	pr_debug("DMA Done ISR, chan_id %d\n", chan_id);
+
+	irq_info[chan_id].irq_pending++;
+	irq_info[chan_id].hist_status = tx_desc->hist_status;
+
+	wake_up_interruptible(&(irq_info[chan_id].waitq));
+}
+
+static int pxp_ioc_config_chan(unsigned long arg)
+{
+	struct scatterlist sg[3];
+	struct pxp_tx_desc *desc;
+	struct dma_async_tx_descriptor *txd;
+	struct pxp_chan_info *info;
+	struct pxp_config_data pxp_conf;
+	dma_cookie_t cookie;
+	int chan_id;
+	int i, length, ret;
+
+	ret = copy_from_user(&pxp_conf,
+			     (struct pxp_config_data *)arg,
+			     sizeof(struct pxp_config_data));
+	if (ret)
+		return -EFAULT;
+
+	chan_id = pxp_conf.chan_id;
+	if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL)
+		return -ENODEV;
+
+	init_waitqueue_head(&(irq_info[chan_id].waitq));
+
+	/* Fixme */
+	mdelay(100);
+	/* find the channel */
+	spin_lock(&pxp_chan_lock);
+	list_for_each_entry(info, &list, list) {
+		if (info->dma_chan->chan_id == chan_id)
+			break;
+	}
+	spin_unlock(&pxp_chan_lock);
+
+	sg_init_table(sg, 3);
+
+	txd =
+	    info->dma_chan->device->device_prep_slave_sg(info->dma_chan,
+							 sg, 3,
+							 DMA_TO_DEVICE,
+							 DMA_PREP_INTERRUPT);
+	if (!txd) {
+		pr_err("Error preparing a DMA transaction descriptor.\n");
+		return -EIO;
+	}
+
+	txd->callback_param = txd;
+	txd->callback = pxp_dma_done;
+
+	desc = to_tx_desc(txd);
+
+	length = desc->len;
+	for (i = 0; i < length; i++) {
+		if (i == 0) {	/* S0 */
+			memcpy(&desc->proc_data,
+			       &pxp_conf.proc_data,
+			       sizeof(struct pxp_proc_data));
+			memcpy(&desc->layer_param.s0_param,
+			       &pxp_conf.s0_param,
+			       sizeof(struct pxp_layer_param));
+		} else if (i == 1) {	/* Output */
+			memcpy(&desc->layer_param.out_param,
+			       &pxp_conf.out_param,
+			       sizeof(struct pxp_layer_param));
+		} else {
+			/* OverLay */
+			memcpy(&desc->layer_param.ol_param,
+			       &pxp_conf.ol_param,
+			       sizeof(struct pxp_layer_param));
+		}
+
+		desc = desc->next;
+	}
+
+	cookie = txd->tx_submit(txd);
+	if (cookie < 0) {
+		pr_err("Error tx_submit\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int pxp_device_open(struct inode *inode, struct file *filp)
+{
+	atomic_inc(&open_count);
+
+	return 0;
+}
+
+static int pxp_device_release(struct inode *inode, struct file *filp)
+{
+	if (atomic_dec_and_test(&open_count))
+		pxp_free_buffers();
+
+	return 0;
+}
+
+static int pxp_device_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct memalloc_record *rec, *n;
+	int request_size, found;
+
+	request_size = vma->vm_end - vma->vm_start;
+	found = 0;
+
+	pr_debug("start=0x%x, pgoff=0x%x, size=0x%x\n",
+		 (unsigned int)(vma->vm_start), (unsigned int)(vma->vm_pgoff),
+		 request_size);
+
+	spin_lock(&pxp_mem_lock);
+	list_for_each_entry_safe(rec, n, &head, list) {
+		if (rec->mem.phys_addr == (vma->vm_pgoff << PAGE_SHIFT) &&
+			(rec->mem.size <= request_size)) {
+			found = 1;
+			break;
+		}
+	}
+	spin_unlock(&pxp_mem_lock);
+
+	if (found == 0)
+		return -ENOMEM;
+
+	vma->vm_flags |= VM_IO | VM_RESERVED;
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+			       request_size, vma->vm_page_prot) ? -EAGAIN : 0;
+}
+
+static int pxp_device_ioctl(struct inode *inode, struct file *filp,
+			    unsigned int cmd, unsigned long arg)
+{
+	int ret = 0;
+
+	switch (cmd) {
+	case PXP_IOC_GET_CHAN:
+		{
+			struct pxp_chan_info *info;
+			dma_cap_mask_t mask;
+
+			pr_debug("drv: PXP_IOC_GET_CHAN Line %d\n", __LINE__);
+			info = kzalloc(sizeof(*info), GFP_KERNEL);
+			if (!info) {
+				pr_err("%d: alloc err\n", __LINE__);
+				return -ENOMEM;
+			}
+
+			dma_cap_zero(mask);
+			dma_cap_set(DMA_SLAVE, mask);
+			dma_cap_set(DMA_PRIVATE, mask);
+			info->dma_chan = dma_request_channel(mask, NULL, NULL);
+			if (!info->dma_chan) {
+				pr_err("Unsccessfully received channel!\n");
+				kfree(info);
+				return -EBUSY;
+			}
+			pr_debug("Successfully received channel."
+				 "chan_id %d\n", info->dma_chan->chan_id);
+
+			spin_lock(&pxp_chan_lock);
+			list_add_tail(&info->list, &list);
+			spin_unlock(&pxp_chan_lock);
+
+			if (put_user
+			    (info->dma_chan->chan_id, (u32 __user *) arg))
+				return -EFAULT;
+
+			break;
+		}
+	case PXP_IOC_PUT_CHAN:
+		{
+			int chan_id;
+			struct pxp_chan_info *info;
+
+			if (get_user(chan_id, (u32 __user *) arg))
+				return -EFAULT;
+
+			if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL)
+				return -ENODEV;
+
+			spin_lock(&pxp_chan_lock);
+			list_for_each_entry(info, &list, list) {
+				if (info->dma_chan->chan_id == chan_id)
+					break;
+			}
+			spin_unlock(&pxp_chan_lock);
+
+			pr_debug("%d release chan_id %d\n", __LINE__,
+				 info->dma_chan->chan_id);
+			/* REVISIT */
+			dma_release_channel(info->dma_chan);
+			spin_lock(&pxp_chan_lock);
+			list_del_init(&info->list);
+			spin_unlock(&pxp_chan_lock);
+			kfree(info);
+
+			break;
+		}
+	case PXP_IOC_CONFIG_CHAN:
+		{
+
+			int ret;
+
+			ret = pxp_ioc_config_chan(arg);
+			if (ret)
+				return ret;
+
+			break;
+		}
+	case PXP_IOC_START_CHAN:
+		{
+			struct pxp_chan_info *info;
+			int chan_id;
+
+			if (get_user(chan_id, (u32 __user *) arg))
+				return -EFAULT;
+
+			/* find the channel */
+			spin_lock(&pxp_chan_lock);
+			list_for_each_entry(info, &list, list) {
+				if (info->dma_chan->chan_id == chan_id)
+					break;
+			}
+			spin_unlock(&pxp_chan_lock);
+
+			dma_async_issue_pending(info->dma_chan);
+
+			break;
+		}
+	case PXP_IOC_GET_PHYMEM:
+		{
+			struct memalloc_record *rec;
+
+			rec = kzalloc(sizeof(*rec), GFP_KERNEL);
+			if (!rec)
+				return -ENOMEM;
+
+			ret = copy_from_user(&(rec->mem),
+					     (struct pxp_mem_desc *)arg,
+					     sizeof(struct pxp_mem_desc));
+			if (ret) {
+				kfree(rec);
+				return -EFAULT;
+			}
+
+			pr_debug("[ALLOC] mem alloc size = 0x%x\n",
+				 rec->mem.size);
+
+			ret = pxp_alloc_dma_buffer(&(rec->mem));
+			if (ret == -1) {
+				kfree(rec);
+				printk(KERN_ERR
+				       "Physical memory allocation error!\n");
+				break;
+			}
+			ret = copy_to_user((void __user *)arg, &(rec->mem),
+					   sizeof(struct pxp_mem_desc));
+			if (ret) {
+				kfree(rec);
+				ret = -EFAULT;
+				break;
+			}
+
+			spin_lock(&pxp_mem_lock);
+			list_add(&rec->list, &head);
+			spin_unlock(&pxp_mem_lock);
+
+			break;
+		}
+	case PXP_IOC_PUT_PHYMEM:
+		{
+			struct memalloc_record *rec, *n;
+			struct pxp_mem_desc pxp_mem;
+
+			ret = copy_from_user(&pxp_mem,
+					     (struct pxp_mem_desc *)arg,
+					     sizeof(struct pxp_mem_desc));
+			if (ret)
+				return -EACCES;
+
+			pr_debug("[FREE] mem freed cpu_addr = 0x%x\n",
+				 pxp_mem.cpu_addr);
+			if ((void *)pxp_mem.cpu_addr != NULL)
+				pxp_free_dma_buffer(&pxp_mem);
+
+			spin_lock(&pxp_mem_lock);
+			list_for_each_entry_safe(rec, n, &head, list) {
+				if (rec->mem.cpu_addr == pxp_mem.cpu_addr) {
+					/* delete from list */
+					list_del(&rec->list);
+					kfree(rec);
+					break;
+				}
+			}
+			spin_unlock(&pxp_mem_lock);
+
+			break;
+		}
+	case PXP_IOC_WAIT4CMPLT:
+		{
+			struct pxp_chan_handle chan_handle;
+			int ret, chan_id;
+
+			ret = copy_from_user(&chan_handle,
+					     (struct pxp_chan_handle *)arg,
+					     sizeof(struct pxp_chan_handle));
+			if (ret)
+				return -EFAULT;
+
+			chan_id = chan_handle.chan_id;
+			if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL)
+				return -ENODEV;
+
+			if (!wait_event_interruptible_timeout
+			    (irq_info[chan_id].waitq,
+			     (irq_info[chan_id].irq_pending != 0), 2 * HZ)) {
+				pr_warning("pxp blocking: timeout.\n");
+				return -ETIME;
+			} else if (signal_pending(current)) {
+				printk(KERN_WARNING
+				       "pxp interrupt received.\n");
+				return -ERESTARTSYS;
+			} else
+				irq_info[chan_id].irq_pending--;
+
+			chan_handle.hist_status = irq_info[chan_id].hist_status;
+			ret = copy_to_user((struct pxp_chan_handle *)arg,
+					   &chan_handle,
+					   sizeof(struct pxp_chan_handle));
+			if (ret)
+				return -EFAULT;
+			break;
+		}
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static const struct file_operations pxp_device_fops = {
+	.open = pxp_device_open,
+	.release = pxp_device_release,
+	.ioctl = pxp_device_ioctl,
+	.mmap = pxp_device_mmap,
+};
+
+static struct miscdevice pxp_device_miscdev = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "pxp_device",
+	.fops = &pxp_device_fops,
+};
+
+static int __devinit pxp_device_probe(struct platform_device *pdev)
+{
+	int ret;
+
+	/* PxP DMA interface */
+	dmaengine_get();
+
+	ret = misc_register(&pxp_device_miscdev);
+	if (ret)
+		return ret;
+
+	pr_debug("PxP_Device Probe Successfully\n");
+	return 0;
+}
+
+static int __devexit pxp_device_remove(struct platform_device *pdev)
+{
+	misc_deregister(&pxp_device_miscdev);
+
+	dmaengine_put();
+
+	return 0;
+}
+
+static struct platform_driver pxp_device = {
+	.probe = pxp_device_probe,
+	.remove = __exit_p(pxp_device_remove),
+	.driver = {
+		   .name = "pxp-device",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init pxp_device_init(void)
+{
+	return platform_driver_register(&pxp_device);
+}
+
+static void __exit pxp_device_exit(void)
+{
+	platform_driver_unregister(&pxp_device);
+}
+
+module_init(pxp_device_init);
+module_exit(pxp_device_exit);
+
+MODULE_DESCRIPTION("i.MX PxP client driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/dma/pxp/pxp_dma.c b/drivers/dma/pxp/pxp_dma.c
new file mode 100644
index 000000000000..e418f6c9715e
--- /dev/null
+++ b/drivers/dma/pxp/pxp_dma.c
@@ -0,0 +1,1365 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+/*
+ * Based on STMP378X PxP driver
+ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/vmalloc.h>
+#include <linux/dmaengine.h>
+#include <linux/pxp_dma.h>
+#include <linux/clk.h>
+
+#include "regs-pxp.h"
+
+#define	PXP_DOWNSCALE_THRESHOLD		0x4000
+
+static LIST_HEAD(head);
+
+struct pxp_dma {
+	struct dma_device dma;
+};
+
+struct pxps {
+	struct platform_device *pdev;
+	struct clk *clk;
+	void __iomem *base;
+	int irq;		/* PXP IRQ to the CPU */
+
+	spinlock_t lock;
+	struct mutex mutex;
+
+	struct device *dev;
+	struct pxp_dma pxp_dma;
+	struct pxp_channel channel[NR_PXP_VIRT_CHANNEL];
+	struct work_struct work;
+	struct workqueue_struct *workqueue;
+
+	/* describes most recent processing configuration */
+	struct pxp_config_data pxp_conf_state;
+};
+
+#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma)
+#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd)
+#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan)
+#define to_pxp(id) container_of(id, struct pxps, pxp_dma)
+
+#define PXP_DEF_BUFS	2
+#define PXP_MIN_PIX	8
+
+static uint32_t pxp_s0_formats[] = {
+	PXP_PIX_FMT_RGB24,
+	PXP_PIX_FMT_RGB565,
+	PXP_PIX_FMT_RGB555,
+	PXP_PIX_FMT_YUV420P,
+	PXP_PIX_FMT_YUV422P,
+};
+
+/*
+ * PXP common functions
+ */
+static void dump_pxp_reg(struct pxps *pxp)
+{
+	dev_err(pxp->dev, "PXP_CTRL 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CTRL));
+	dev_err(pxp->dev, "PXP_STAT 0x%x",
+		__raw_readl(pxp->base + HW_PXP_STAT));
+	dev_err(pxp->dev, "PXP_OUTBUF 0x%x",
+		__raw_readl(pxp->base + HW_PXP_OUTBUF));
+	dev_err(pxp->dev, "PXP_OUTBUF2 0x%x",
+		__raw_readl(pxp->base + HW_PXP_OUTBUF2));
+	dev_err(pxp->dev, "PXP_OUTSIZE 0x%x",
+		__raw_readl(pxp->base + HW_PXP_OUTSIZE));
+	dev_err(pxp->dev, "PXP_S0BUF 0x%x",
+		__raw_readl(pxp->base + HW_PXP_S0BUF));
+	dev_err(pxp->dev, "PXP_S0UBUF 0x%x",
+		__raw_readl(pxp->base + HW_PXP_S0UBUF));
+	dev_err(pxp->dev, "PXP_S0VBUF 0x%x",
+		__raw_readl(pxp->base + HW_PXP_S0VBUF));
+	dev_err(pxp->dev, "PXP_S0PARAM 0x%x",
+		__raw_readl(pxp->base + HW_PXP_S0PARAM));
+	dev_err(pxp->dev, "PXP_S0BACKGROUND 0x%x",
+		__raw_readl(pxp->base + HW_PXP_S0BACKGROUND));
+	dev_err(pxp->dev, "PXP_S0CROP 0x%x",
+		__raw_readl(pxp->base + HW_PXP_S0CROP));
+	dev_err(pxp->dev, "PXP_S0SCALE 0x%x",
+		__raw_readl(pxp->base + HW_PXP_S0SCALE));
+	dev_err(pxp->dev, "PXP_OLn 0x%x",
+		__raw_readl(pxp->base + HW_PXP_OLn(0)));
+	dev_err(pxp->dev, "PXP_OLnSIZE 0x%x",
+		__raw_readl(pxp->base + HW_PXP_OLnSIZE(0)));
+	dev_err(pxp->dev, "PXP_OLnPARAM 0x%x",
+		__raw_readl(pxp->base + HW_PXP_OLnPARAM(0)));
+	dev_err(pxp->dev, "PXP_CSCCOEF0 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSCCOEF0));
+	dev_err(pxp->dev, "PXP_CSC2CTRL 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSC2CTRL));
+	dev_err(pxp->dev, "PXP_CSC2COEF0 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSC2COEF0));
+	dev_err(pxp->dev, "PXP_CSC2COEF1 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSC2COEF1));
+	dev_err(pxp->dev, "PXP_CSC2COEF2 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSC2COEF2));
+	dev_err(pxp->dev, "PXP_CSC2COEF3 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSC2COEF3));
+	dev_err(pxp->dev, "PXP_CSC2COEF4 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSC2COEF4));
+	dev_err(pxp->dev, "PXP_CSC2COEF5 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSC2COEF5));
+	dev_err(pxp->dev, "PXP_LUT_CTRL 0x%x",
+		__raw_readl(pxp->base + HW_PXP_LUT_CTRL));
+	dev_err(pxp->dev, "PXP_LUT 0x%x", __raw_readl(pxp->base + HW_PXP_LUT));
+	dev_err(pxp->dev, "PXP_HIST_CTRL 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST_CTRL));
+	dev_err(pxp->dev, "PXP_HIST2_PARAM 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST2_PARAM));
+	dev_err(pxp->dev, "PXP_HIST4_PARAM 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST4_PARAM));
+	dev_err(pxp->dev, "PXP_HIST8_PARAM0 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST8_PARAM0));
+	dev_err(pxp->dev, "PXP_HIST8_PARAM1 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST8_PARAM1));
+	dev_err(pxp->dev, "PXP_HIST16_PARAM0 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST16_PARAM0));
+	dev_err(pxp->dev, "PXP_HIST16_PARAM1 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST16_PARAM1));
+	dev_err(pxp->dev, "PXP_HIST16_PARAM2 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST16_PARAM2));
+	dev_err(pxp->dev, "PXP_HIST16_PARAM3 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST16_PARAM3));
+}
+
+static bool is_yuv(pix_fmt)
+{
+	if ((pix_fmt == PXP_PIX_FMT_YUYV) |
+	    (pix_fmt == PXP_PIX_FMT_UYVY) |
+	    (pix_fmt == PXP_PIX_FMT_Y41P) |
+	    (pix_fmt == PXP_PIX_FMT_YUV444) |
+	    (pix_fmt == PXP_PIX_FMT_NV12) |
+	    (pix_fmt == PXP_PIX_FMT_GREY) |
+	    (pix_fmt == PXP_PIX_FMT_YVU410P) |
+	    (pix_fmt == PXP_PIX_FMT_YUV410P) |
+	    (pix_fmt == PXP_PIX_FMT_YVU420P) |
+	    (pix_fmt == PXP_PIX_FMT_YUV420P) |
+	    (pix_fmt == PXP_PIX_FMT_YUV420P2) |
+	    (pix_fmt == PXP_PIX_FMT_YVU422P) |
+	    (pix_fmt == PXP_PIX_FMT_YUV422P)) {
+		return true;
+	} else {
+		return false;
+	}
+}
+
+static void pxp_set_ctrl(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
+	u32 ctrl;
+	u32 fmt_ctrl;
+
+	/* Configure S0 input format */
+	switch (pxp_conf->s0_param.pixel_fmt) {
+	case PXP_PIX_FMT_RGB24:
+		fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__RGB888;
+		break;
+	case PXP_PIX_FMT_RGB565:
+		fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__RGB565;
+		break;
+	case PXP_PIX_FMT_RGB555:
+		fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__RGB555;
+		break;
+	case PXP_PIX_FMT_YUV420P:
+	case PXP_PIX_FMT_GREY:
+		fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__YUV420;
+		break;
+	case PXP_PIX_FMT_YUV422P:
+		fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__YUV422;
+		break;
+	default:
+		fmt_ctrl = 0;
+	}
+	ctrl = BF_PXP_CTRL_S0_FORMAT(fmt_ctrl);
+
+	/* Configure output format based on out_channel format */
+	switch (pxp_conf->out_param.pixel_fmt) {
+	case PXP_PIX_FMT_RGB24:
+		fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__RGB888;
+		break;
+	case PXP_PIX_FMT_RGB565:
+		fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__RGB565;
+		break;
+	case PXP_PIX_FMT_RGB555:
+		fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__RGB555;
+		break;
+	case PXP_PIX_FMT_YUV420P:
+		fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P420;
+		break;
+	case PXP_PIX_FMT_YUV422P:
+		fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P422;
+		break;
+	case PXP_PIX_FMT_GREY:
+		fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__MONOC8;
+		break;
+	default:
+		fmt_ctrl = 0;
+	}
+	ctrl |= BF_PXP_CTRL_OUTBUF_FORMAT(fmt_ctrl);
+
+	ctrl |= BM_PXP_CTRL_CROP;
+
+	if (proc_data->scaling)
+		ctrl |= BM_PXP_CTRL_SCALE;
+	if (proc_data->vflip)
+		ctrl |= BM_PXP_CTRL_VFLIP;
+	if (proc_data->hflip)
+		ctrl |= BM_PXP_CTRL_HFLIP;
+	if (proc_data->rotate)
+		ctrl |= BF_PXP_CTRL_ROTATE(proc_data->rotate / 90);
+
+	__raw_writel(ctrl, pxp->base + HW_PXP_CTRL);
+}
+
+static int pxp_start(struct pxps *pxp)
+{
+	__raw_writel(BM_PXP_CTRL_IRQ_ENABLE, pxp->base + HW_PXP_CTRL_SET);
+	__raw_writel(BM_PXP_CTRL_ENABLE, pxp->base + HW_PXP_CTRL_SET);
+
+	return 0;
+}
+
+static void pxp_set_outbuf(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *out_params = &pxp_conf->out_param;
+
+	__raw_writel(out_params->paddr, pxp->base + HW_PXP_OUTBUF);
+
+	__raw_writel(BF_PXP_OUTSIZE_WIDTH(out_params->width) |
+		     BF_PXP_OUTSIZE_HEIGHT(out_params->height),
+		     pxp->base + HW_PXP_OUTSIZE);
+}
+
+static void pxp_set_s0colorkey(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
+
+	/* Low and high are set equal. V4L does not allow a chromakey range */
+	if (s0_params->color_key == -1) {
+		/* disable color key */
+		__raw_writel(0xFFFFFF, pxp->base + HW_PXP_S0COLORKEYLOW);
+		__raw_writel(0, pxp->base + HW_PXP_S0COLORKEYHIGH);
+	} else {
+		__raw_writel(s0_params->color_key,
+			     pxp->base + HW_PXP_S0COLORKEYLOW);
+		__raw_writel(s0_params->color_key,
+			     pxp->base + HW_PXP_S0COLORKEYHIGH);
+	}
+}
+
+static void pxp_set_olcolorkey(int layer_no, struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *ol_params = &pxp_conf->ol_param[layer_no];
+
+	/* Low and high are set equal. V4L does not allow a chromakey range */
+	if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) {
+		__raw_writel(ol_params->color_key,
+			     pxp->base + HW_PXP_OLCOLORKEYLOW);
+		__raw_writel(ol_params->color_key,
+			     pxp->base + HW_PXP_OLCOLORKEYHIGH);
+	} else {
+		/* disable color key */
+		__raw_writel(0xFFFFFF, pxp->base + HW_PXP_OLCOLORKEYLOW);
+		__raw_writel(0, pxp->base + HW_PXP_OLCOLORKEYHIGH);
+	}
+}
+
+static void pxp_set_oln(int layer_no, struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no];
+	dma_addr_t phys_addr = olparams_data->paddr;
+	__raw_writel(phys_addr, pxp->base + HW_PXP_OLn(layer_no));
+
+	/* Fixme */
+	__raw_writel(BF_PXP_OLnSIZE_WIDTH(olparams_data->width >> 3) |
+		     BF_PXP_OLnSIZE_HEIGHT(olparams_data->height >> 3),
+		     pxp->base + HW_PXP_OLnSIZE(layer_no));
+}
+
+static void pxp_set_olparam(int layer_no, struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no];
+	u32 olparam;
+
+	olparam = BF_PXP_OLnPARAM_ALPHA(olparams_data->global_alpha);
+	if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB24)
+		olparam |=
+		    BF_PXP_OLnPARAM_FORMAT(BV_PXP_OLnPARAM_FORMAT__RGB888);
+	else
+		olparam |=
+		    BF_PXP_OLnPARAM_FORMAT(BV_PXP_OLnPARAM_FORMAT__RGB565);
+	if (olparams_data->global_alpha)
+		olparam |=
+		    BF_PXP_OLnPARAM_ALPHA_CNTL
+		    (BV_PXP_OLnPARAM_ALPHA_CNTL__Override);
+	if (olparams_data->color_key_enable)
+		olparam |= BM_PXP_OLnPARAM_ENABLE_COLORKEY;
+	if (olparams_data->combine_enable)
+		olparam |= BM_PXP_OLnPARAM_ENABLE;
+	__raw_writel(olparam, pxp->base + HW_PXP_OLnPARAM(layer_no));
+}
+
+static void pxp_set_s0param(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *s0params_data = &pxp_conf->s0_param;
+	struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
+	u32 s0param;
+
+	s0param = BF_PXP_S0PARAM_XBASE(proc_data->drect.left >> 3);
+	s0param |= BF_PXP_S0PARAM_YBASE(proc_data->drect.top >> 3);
+	s0param |= BF_PXP_S0PARAM_WIDTH(s0params_data->width >> 3);
+	s0param |= BF_PXP_S0PARAM_HEIGHT(s0params_data->height >> 3);
+	__raw_writel(s0param, pxp->base + HW_PXP_S0PARAM);
+}
+
+static void pxp_set_s0crop(struct pxps *pxp)
+{
+	u32 s0crop;
+	struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data;
+
+	s0crop = BF_PXP_S0CROP_XBASE(proc_data->srect.left >> 3);
+	s0crop |= BF_PXP_S0CROP_YBASE(proc_data->srect.top >> 3);
+	s0crop |= BF_PXP_S0CROP_WIDTH(proc_data->drect.width >> 3);
+	s0crop |= BF_PXP_S0CROP_HEIGHT(proc_data->drect.height >> 3);
+	__raw_writel(s0crop, pxp->base + HW_PXP_S0CROP);
+}
+
+static int pxp_set_scaling(struct pxps *pxp)
+{
+	int ret = 0;
+	u32 xscale, yscale, s0scale;
+	struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data;
+	struct pxp_layer_param *s0params_data = &pxp->pxp_conf_state.s0_param;
+
+	if ((s0params_data->pixel_fmt != PXP_PIX_FMT_YUV420P) &&
+	    (s0params_data->pixel_fmt != PXP_PIX_FMT_YUV422P)) {
+		proc_data->scaling = 0;
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if ((proc_data->srect.width == proc_data->drect.width) &&
+	    (proc_data->srect.height == proc_data->drect.height)) {
+		proc_data->scaling = 0;
+		__raw_writel(0x10001000, pxp->base + HW_PXP_S0SCALE);
+		goto out;
+	}
+
+	proc_data->scaling = 1;
+	xscale = proc_data->srect.width * 0x1000 / proc_data->drect.width;
+	yscale = proc_data->srect.height * 0x1000 / proc_data->drect.height;
+	if (xscale > PXP_DOWNSCALE_THRESHOLD)
+		xscale = PXP_DOWNSCALE_THRESHOLD;
+	if (yscale > PXP_DOWNSCALE_THRESHOLD)
+		yscale = PXP_DOWNSCALE_THRESHOLD;
+	s0scale = BF_PXP_S0SCALE_YSCALE(yscale) | BF_PXP_S0SCALE_XSCALE(xscale);
+	__raw_writel(s0scale, pxp->base + HW_PXP_S0SCALE);
+
+out:
+	pxp_set_ctrl(pxp);
+
+	return ret;
+}
+
+static void pxp_set_bg(struct pxps *pxp)
+{
+	__raw_writel(pxp->pxp_conf_state.proc_data.bgcolor,
+		     pxp->base + HW_PXP_S0BACKGROUND);
+}
+
+static void pxp_set_lut(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	u32 reg_val;
+	int i;
+
+	if (pxp_conf->proc_data.lut_transform == PXP_LUT_NONE) {
+		__raw_writel(BM_PXP_LUT_CTRL_BYPASS,
+			     pxp->base + HW_PXP_LUT_CTRL);
+	} else if (pxp_conf->proc_data.lut_transform == PXP_LUT_INVERT) {
+		/* Fill out LUT table with 8-bit inverted values */
+
+		/* Initialize LUT address to 0 and clear bypass bit */
+		__raw_writel(0, pxp->base + HW_PXP_LUT_CTRL);
+
+		/* LUT address pointer auto-increments after each data write */
+		for (i = 0; i < 256; i++) {
+			reg_val =
+			    __raw_readl(pxp->base +
+					HW_PXP_LUT_CTRL) & BM_PXP_LUT_CTRL_ADDR;
+			reg_val = ~reg_val & BM_PXP_LUT_DATA;
+			__raw_writel(reg_val, pxp->base + HW_PXP_LUT);
+		}
+	}
+}
+
+static void pxp_set_csc(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
+	struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0];
+	struct pxp_layer_param *out_params = &pxp_conf->out_param;
+
+	bool input_is_YUV = is_yuv(s0_params->pixel_fmt);
+	bool output_is_YUV = is_yuv(out_params->pixel_fmt);
+
+	if (input_is_YUV && output_is_YUV) {
+		/*
+		 * Input = YUV, Output = YUV
+		 * No CSC unless we need to do combining
+		 */
+		if (ol_params->combine_enable) {
+			/* Must convert to RGB for combining with RGB overlay */
+
+			/* CSC1 - YUV->RGB */
+			__raw_writel(0x04030000, pxp->base + HW_PXP_CSCCOEF0);
+			__raw_writel(0x01230208, pxp->base + HW_PXP_CSCCOEF1);
+			__raw_writel(0x076b079c, pxp->base + HW_PXP_CSCCOEF2);
+
+			/* CSC2 - RGB->YUV */
+			__raw_writel(0x4, pxp->base + HW_PXP_CSC2CTRL);
+			__raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2COEF0);
+			__raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2COEF1);
+			__raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2COEF2);
+			__raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2COEF3);
+			__raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2COEF4);
+			__raw_writel(0x00000000, pxp->base + HW_PXP_CSC2COEF5);
+		} else {
+			/* Input & Output both YUV, so bypass both CSCs */
+
+			/* CSC1 - Bypass */
+			__raw_writel(0x40000000, pxp->base + HW_PXP_CSCCOEF0);
+
+			/* CSC2 - Bypass */
+			__raw_writel(0x1, pxp->base + HW_PXP_CSC2CTRL);
+		}
+	} else if (input_is_YUV && !output_is_YUV) {
+		/*
+		 * Input = YUV, Output = RGB
+		 * Use CSC1 to convert to RGB
+		 */
+
+		/* CSC1 - YUV->RGB */
+		__raw_writel(0x04030000, pxp->base + HW_PXP_CSCCOEF0);
+		__raw_writel(0x01230208, pxp->base + HW_PXP_CSCCOEF1);
+		__raw_writel(0x076b079c, pxp->base + HW_PXP_CSCCOEF2);
+
+		/* CSC2 - Bypass */
+		__raw_writel(0x1, pxp->base + HW_PXP_CSC2CTRL);
+	} else if (!input_is_YUV && output_is_YUV) {
+		/*
+		 * Input = RGB, Output = YUV
+		 * Use CSC2 to convert to YUV
+		 */
+
+		/* CSC1 - Bypass */
+		__raw_writel(0x40000000, pxp->base + HW_PXP_CSCCOEF0);
+
+		/* CSC2 - RGB->YUV */
+		__raw_writel(0x4, pxp->base + HW_PXP_CSC2CTRL);
+		__raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2COEF0);
+		__raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2COEF1);
+		__raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2COEF2);
+		__raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2COEF3);
+		__raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2COEF4);
+		__raw_writel(0x00000000, pxp->base + HW_PXP_CSC2COEF5);
+	} else {
+		/*
+		 * Input = RGB, Output = RGB
+		 * Input & Output both RGB, so bypass both CSCs
+		 */
+
+		/* CSC1 - Bypass */
+		__raw_writel(0x40000000, pxp->base + HW_PXP_CSCCOEF0);
+
+		/* CSC2 - Bypass */
+		__raw_writel(0x1, pxp->base + HW_PXP_CSC2CTRL);
+	}
+
+	/* YCrCb colorspace */
+	/* Not sure when we use this...no YCrCb formats are defined for PxP */
+	/*
+	   __raw_writel(0x84ab01f0, HW_PXP_CSCCOEFF0_ADDR);
+	   __raw_writel(0x01230204, HW_PXP_CSCCOEFF1_ADDR);
+	   __raw_writel(0x0730079c, HW_PXP_CSCCOEFF2_ADDR);
+	 */
+
+}
+
+static void pxp_set_s0buf(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
+	dma_addr_t Y, U, V;
+
+	Y = s0_params->paddr;
+	__raw_writel(Y, pxp->base + HW_PXP_S0BUF);
+	if ((s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P) ||
+	    (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) ||
+	    (s0_params->pixel_fmt == PXP_PIX_FMT_GREY)) {
+		/* Set to 1 if YUV format is 4:2:2 rather than 4:2:0 */
+		int s = 2;
+		U = Y + (s0_params->width * s0_params->height);
+		V = U + ((s0_params->width * s0_params->height) >> s);
+		__raw_writel(U, pxp->base + HW_PXP_S0UBUF);
+		__raw_writel(V, pxp->base + HW_PXP_S0VBUF);
+	}
+}
+
+/**
+ * pxp_config() - configure PxP for a processing task
+ * @pxps:	PXP context.
+ * @pxp_chan:	PXP channel.
+ * @return:	0 on success or negative error code on failure.
+ */
+static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan)
+{
+	struct pxp_config_data *pxp_conf_data = &pxp->pxp_conf_state;
+	int ol_nr;
+	int i;
+
+	/* Configure PxP regs */
+	pxp_set_ctrl(pxp);
+	pxp_set_s0param(pxp);
+	pxp_set_s0crop(pxp);
+	pxp_set_scaling(pxp);
+	ol_nr = pxp_conf_data->layer_nr - 2;
+	while (ol_nr > 0) {
+		i = pxp_conf_data->layer_nr - 2 - ol_nr;
+		pxp_set_oln(i, pxp);
+		pxp_set_olparam(i, pxp);
+		/* only the color key in higher overlay will take effect. */
+		pxp_set_olcolorkey(i, pxp);
+		ol_nr--;
+	}
+	pxp_set_s0colorkey(pxp);
+	pxp_set_csc(pxp);
+	pxp_set_bg(pxp);
+	pxp_set_lut(pxp);
+
+	pxp_set_s0buf(pxp);
+	pxp_set_outbuf(pxp);
+
+	return 0;
+}
+
+static struct pxp_tx_desc *pxpdma_first_active(struct pxp_channel *pxp_chan)
+{
+	return list_entry(pxp_chan->active_list.next, struct pxp_tx_desc, list);
+}
+
+static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan)
+{
+	return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list);
+}
+
+/* called with pxp_chan->lock held */
+static void __pxpdma_dostart(struct pxp_channel *pxp_chan)
+{
+	struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device);
+	struct pxps *pxp = to_pxp(pxp_dma);
+	struct pxp_tx_desc *desc;
+	struct pxp_tx_desc *child;
+	int i = 0;
+
+	/* so far we presume only one transaction on active_list */
+	/* S0 */
+	desc = pxpdma_first_active(pxp_chan);
+	memcpy(&pxp->pxp_conf_state.s0_param,
+	       &desc->layer_param.s0_param, sizeof(struct pxp_layer_param));
+	memcpy(&pxp->pxp_conf_state.proc_data,
+	       &desc->proc_data, sizeof(struct pxp_proc_data));
+
+	/* Save PxP configuration */
+	list_for_each_entry(child, &desc->txd.tx_list, list) {
+		if (i == 0) {	/* Output */
+			memcpy(&pxp->pxp_conf_state.out_param,
+			       &child->layer_param.out_param,
+			       sizeof(struct pxp_layer_param));
+		} else {	/* Overlay */
+			memcpy(&pxp->pxp_conf_state.ol_param[i - 1],
+			       &child->layer_param.ol_param,
+			       sizeof(struct pxp_layer_param));
+		}
+
+		i++;
+	}
+	pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__,
+		 pxp->pxp_conf_state.s0_param.width,
+		 pxp->pxp_conf_state.s0_param.height,
+		 pxp->pxp_conf_state.s0_param.paddr);
+	pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__,
+		 pxp->pxp_conf_state.out_param.width,
+		 pxp->pxp_conf_state.out_param.height,
+		 pxp->pxp_conf_state.out_param.paddr);
+}
+
+static void pxpdma_dostart_work(struct work_struct *w)
+{
+	struct pxps *pxp = container_of(w, struct pxps, work);
+	struct pxp_channel *pxp_chan = NULL;
+	unsigned long flags, flags1;
+	int val;
+
+	val = __raw_readl(pxp->base + HW_PXP_CTRL);
+	if (val & BM_PXP_CTRL_ENABLE) {
+		pr_warning("pxp is active, quit.\n");
+		return;
+	}
+
+	spin_lock_irqsave(&pxp->lock, flags);
+	if (list_empty(&head)) {
+		spin_unlock_irqrestore(&pxp->lock, flags);
+		return;
+	}
+
+	pxp_chan = list_entry(head.next, struct pxp_channel, list);
+
+	spin_lock_irqsave(&pxp_chan->lock, flags1);
+	if (!list_empty(&pxp_chan->active_list)) {
+		struct pxp_tx_desc *desc;
+		/* REVISIT */
+		desc = pxpdma_first_active(pxp_chan);
+		__pxpdma_dostart(pxp_chan);
+	}
+	spin_unlock_irqrestore(&pxp_chan->lock, flags1);
+
+	/* Configure PxP */
+	pxp_config(pxp, pxp_chan);
+
+	pxp_start(pxp);
+
+	spin_unlock_irqrestore(&pxp->lock, flags);
+}
+
+static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct list_head *list)
+{
+	struct pxp_tx_desc *desc = NULL;
+	do {
+		desc = pxpdma_first_queued(pxp_chan);
+		list_move_tail(&desc->list, list);
+	} while (!list_empty(&pxp_chan->queue));
+}
+
+static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+	struct pxp_tx_desc *desc = to_tx_desc(tx);
+	struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan);
+	dma_cookie_t cookie;
+	unsigned long flags;
+
+	dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n");
+
+	mutex_lock(&pxp_chan->chan_mutex);
+
+	cookie = pxp_chan->dma_chan.cookie;
+
+	if (++cookie < 0)
+		cookie = 1;
+
+	/* from dmaengine.h: "last cookie value returned to client" */
+	pxp_chan->dma_chan.cookie = cookie;
+	tx->cookie = cookie;
+
+	/* pxp_chan->lock can be taken under ichan->lock, but not v.v. */
+	spin_lock_irqsave(&pxp_chan->lock, flags);
+
+	/* Here we add the tx descriptor to our PxP task queue. */
+	list_add_tail(&desc->list, &pxp_chan->queue);
+
+	spin_unlock_irqrestore(&pxp_chan->lock, flags);
+
+	dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n");
+
+	mutex_unlock(&pxp_chan->chan_mutex);
+	return cookie;
+}
+
+/* Called with pxp_chan->chan_mutex held */
+static int pxp_desc_alloc(struct pxp_channel *pxp_chan, int n)
+{
+	struct pxp_tx_desc *desc = vmalloc(n * sizeof(struct pxp_tx_desc));
+
+	if (!desc)
+		return -ENOMEM;
+
+	pxp_chan->n_tx_desc = n;
+	pxp_chan->desc = desc;
+	INIT_LIST_HEAD(&pxp_chan->active_list);
+	INIT_LIST_HEAD(&pxp_chan->queue);
+	INIT_LIST_HEAD(&pxp_chan->free_list);
+
+	while (n--) {
+		struct dma_async_tx_descriptor *txd = &desc->txd;
+
+		memset(txd, 0, sizeof(*txd));
+		dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan);
+		txd->tx_submit = pxp_tx_submit;
+
+		list_add(&desc->list, &pxp_chan->free_list);
+
+		desc++;
+	}
+
+	return 0;
+}
+
+/**
+ * pxp_init_channel() - initialize a PXP channel.
+ * @pxp_dma:   PXP DMA context.
+ * @pchan:  pointer to the channel object.
+ * @return      0 on success or negative error code on failure.
+ */
+static int pxp_init_channel(struct pxp_dma *pxp_dma,
+			    struct pxp_channel *pxp_chan)
+{
+	unsigned long flags;
+	struct pxps *pxp = to_pxp(pxp_dma);
+	int ret = 0, n_desc = 0;
+
+	/*
+	 * We are using _virtual_ channel here.
+	 * Each channel contains all parameters of corresponding layers
+	 * for one transaction; each layer is represented as one descriptor
+	 * (i.e., pxp_tx_desc) here.
+	 */
+
+	spin_lock_irqsave(&pxp->lock, flags);
+
+	/* max desc nr: S0+OL+OUT = 1+8+1 */
+	n_desc = 10;
+
+	spin_unlock_irqrestore(&pxp->lock, flags);
+
+	if (n_desc && !pxp_chan->desc)
+		ret = pxp_desc_alloc(pxp_chan, n_desc);
+
+	return ret;
+}
+
+/**
+ * pxp_uninit_channel() - uninitialize a PXP channel.
+ * @pxp_dma:   PXP DMA context.
+ * @pchan:  pointer to the channel object.
+ * @return      0 on success or negative error code on failure.
+ */
+static int pxp_uninit_channel(struct pxp_dma *pxp_dma,
+			      struct pxp_channel *pxp_chan)
+{
+	int ret = 0;
+
+	if (pxp_chan->desc)
+		vfree(pxp_chan->desc);
+
+	pxp_chan->desc = NULL;
+
+	return ret;
+}
+
+static irqreturn_t pxp_irq(int irq, void *dev_id)
+{
+	struct pxp_channel *pxp_chan = dev_id;
+	struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device);
+	struct pxps *pxp = to_pxp(pxp_dma);
+	struct pxp_tx_desc *desc;
+	dma_async_tx_callback callback;
+	void *callback_param;
+	unsigned long flags;
+	u32 hist_status;
+
+	hist_status =
+	    __raw_readl(pxp->base + HW_PXP_HIST_CTRL) & BM_PXP_HIST_CTRL_STATUS;
+
+	__raw_writel(BM_PXP_STAT_IRQ, pxp->base + HW_PXP_STAT_CLR);
+
+	spin_lock_irqsave(&pxp->lock, flags);
+
+	if (list_empty(&pxp_chan->active_list)) {
+		pr_debug("PXP_IRQ pxp_chan->active_list empty. chan_id %d\n",
+			 pxp_chan->dma_chan.chan_id);
+		spin_unlock_irqrestore(&pxp->lock, flags);
+		return IRQ_NONE;
+	}
+
+	/* Get descriptor and call callback */
+	desc = pxpdma_first_active(pxp_chan);
+
+	pxp_chan->completed = desc->txd.cookie;
+
+	callback = desc->txd.callback;
+	callback_param = desc->txd.callback_param;
+
+	/* Send histogram status back to caller */
+	desc->hist_status = hist_status;
+
+	if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback)
+		callback(callback_param);
+
+	pxp_chan->status = PXP_CHANNEL_INITIALIZED;
+
+	list_splice_init(&desc->txd.tx_list, &pxp_chan->free_list);
+	list_move(&desc->list, &pxp_chan->free_list);
+
+	list_del(&pxp_chan->list);
+
+	spin_unlock_irqrestore(&pxp->lock, flags);
+
+	queue_work(pxp->workqueue, &pxp->work);
+
+	return IRQ_HANDLED;
+}
+
+static struct pxp_tx_desc *pxp_desc_get(struct pxp_channel *pxp_chan)
+{
+	struct pxp_tx_desc *desc, *_desc;
+	struct pxp_tx_desc *ret = NULL;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pxp_chan->lock, flags);
+	list_for_each_entry_safe(desc, _desc, &pxp_chan->free_list, list) {
+		list_del_init(&desc->list);
+		ret = desc;
+		break;
+	}
+	spin_unlock_irqrestore(&pxp_chan->lock, flags);
+
+	return ret;
+}
+
+static void pxpdma_desc_put(struct pxp_channel *pxp_chan,
+			    struct pxp_tx_desc *desc)
+{
+	if (desc) {
+		struct device *dev = &pxp_chan->dma_chan.dev->device;
+		struct pxp_tx_desc *child;
+		unsigned long flags;
+
+		spin_lock_irqsave(&pxp_chan->lock, flags);
+		list_for_each_entry(child, &desc->txd.tx_list, list)
+		    dev_info(dev, "moving child desc %p to freelist\n", child);
+		list_splice_init(&desc->txd.tx_list, &pxp_chan->free_list);
+		dev_info(dev, "moving desc %p to freelist\n", desc);
+		list_add(&desc->list, &pxp_chan->free_list);
+		spin_unlock_irqrestore(&pxp_chan->lock, flags);
+	}
+}
+
+/* Allocate and initialise a transfer descriptor. */
+static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan,
+							 struct scatterlist
+							 *sgl,
+							 unsigned int sg_len,
+							 enum dma_data_direction
+							 direction,
+							 unsigned long tx_flags)
+{
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+	struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
+	struct pxps *pxp = to_pxp(pxp_dma);
+	struct pxp_tx_desc *desc = NULL;
+	struct pxp_tx_desc *first = NULL, *prev = NULL;
+	struct scatterlist *sg;
+	unsigned long flags;
+	dma_addr_t phys_addr;
+	int i;
+
+	if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) {
+		dev_err(chan->device->dev, "Invalid DMA direction %d!\n",
+			direction);
+		return NULL;
+	}
+
+	if (unlikely(sg_len < 2))
+		return NULL;
+
+	spin_lock_irqsave(&pxp_chan->lock, flags);
+	for_each_sg(sgl, sg, sg_len, i) {
+		desc = pxp_desc_get(pxp_chan);
+		if (!desc) {
+			pxpdma_desc_put(pxp_chan, first);
+			dev_err(chan->device->dev, "Can't get DMA desc.\n");
+			spin_unlock_irqrestore(&pxp_chan->lock, flags);
+			return NULL;
+		}
+
+		phys_addr = sg_dma_address(sg);
+
+		if (!first) {
+			first = desc;
+
+			desc->layer_param.s0_param.paddr = phys_addr;
+		} else {
+			list_add_tail(&desc->list, &first->txd.tx_list);
+			prev->next = desc;
+			desc->next = NULL;
+
+			if (i == 1)
+				desc->layer_param.out_param.paddr = phys_addr;
+			else
+				desc->layer_param.ol_param.paddr = phys_addr;
+		}
+
+		prev = desc;
+	}
+	spin_unlock_irqrestore(&pxp_chan->lock, flags);
+
+	pxp->pxp_conf_state.layer_nr = sg_len;
+	first->txd.flags = tx_flags;
+	first->len = sg_len;
+	pr_debug("%s:%d first %p, first->len %d, flags %08x\n",
+		 __func__, __LINE__, first, first->len, first->txd.flags);
+
+	return &first->txd;
+}
+
+static void pxp_issue_pending(struct dma_chan *chan)
+{
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+	struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
+	struct pxps *pxp = to_pxp(pxp_dma);
+	unsigned long flags0, flags;
+
+	spin_lock_irqsave(&pxp->lock, flags0);
+	spin_lock_irqsave(&pxp_chan->lock, flags);
+	if (!list_empty(&pxp_chan->active_list))
+		queue_work(pxp->workqueue, &pxp->work);
+
+	if (!list_empty(&pxp_chan->queue)) {
+		pxpdma_dequeue(pxp_chan, &pxp_chan->active_list);
+		pxp_chan->status = PXP_CHANNEL_READY;
+		list_add_tail(&pxp_chan->list, &head);
+		queue_work(pxp->workqueue, &pxp->work);
+	}
+	spin_unlock_irqrestore(&pxp_chan->lock, flags);
+	spin_unlock_irqrestore(&pxp->lock, flags0);
+}
+
+static void __pxp_terminate_all(struct dma_chan *chan)
+{
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+	struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
+	unsigned long flags;
+
+	cancel_work_sync(&to_pxp(pxp_dma)->work);
+
+	/* pchan->queue is modified in ISR, have to spinlock */
+	spin_lock_irqsave(&pxp_chan->lock, flags);
+	list_splice_init(&pxp_chan->queue, &pxp_chan->free_list);
+	list_splice_init(&pxp_chan->active_list, &pxp_chan->free_list);
+
+	spin_unlock_irqrestore(&pxp_chan->lock, flags);
+
+	pxp_chan->status = PXP_CHANNEL_INITIALIZED;
+}
+
+static void pxp_terminate_all(struct dma_chan *chan)
+{
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+
+	mutex_lock(&pxp_chan->chan_mutex);
+	__pxp_terminate_all(chan);
+	mutex_unlock(&pxp_chan->chan_mutex);
+}
+
+static int pxp_alloc_chan_resources(struct dma_chan *chan)
+{
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+	struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
+	int ret;
+
+	/* dmaengine.c now guarantees to only offer free channels */
+	BUG_ON(chan->client_count > 1);
+	WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE);
+
+	chan->cookie = 1;
+	pxp_chan->completed = -ENXIO;
+
+	pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id);
+	ret = pxp_init_channel(pxp_dma, pxp_chan);
+	if (ret < 0)
+		goto err_chan;
+
+	ret = request_irq(pxp_chan->eof_irq, pxp_irq, IRQF_SHARED,
+			  "pxp-irq", pxp_chan);
+	if (ret < 0)
+		goto err_irq;
+
+	pxp_chan->status = PXP_CHANNEL_INITIALIZED;
+
+	dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
+		chan->chan_id, pxp_chan->eof_irq);
+
+	return ret;
+
+err_irq:
+	pxp_uninit_channel(pxp_dma, pxp_chan);
+err_chan:
+	return ret;
+}
+
+static void pxp_free_chan_resources(struct dma_chan *chan)
+{
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+	struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
+
+	mutex_lock(&pxp_chan->chan_mutex);
+
+	__pxp_terminate_all(chan);
+
+	pxp_chan->status = PXP_CHANNEL_FREE;
+
+	pxp_uninit_channel(pxp_dma, pxp_chan);
+
+	free_irq(pxp_chan->eof_irq, pxp_chan);
+
+	mutex_unlock(&pxp_chan->chan_mutex);
+}
+
+static enum dma_status pxp_is_tx_complete(struct dma_chan *chan,
+					  dma_cookie_t cookie,
+					  dma_cookie_t *done,
+					  dma_cookie_t *used)
+{
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+
+	if (done)
+		*done = pxp_chan->completed;
+	if (used)
+		*used = chan->cookie;
+	if (cookie != chan->cookie)
+		return DMA_ERROR;
+	return DMA_SUCCESS;
+}
+
+static int pxp_hw_init(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
+	u32 reg_val;
+	int i;
+
+	/* Pull PxP out of reset */
+	__raw_writel(0, pxp->base + HW_PXP_CTRL);
+
+	/* Config defaults */
+
+	/* Initialize non-channel-specific PxP parameters */
+	proc_data->drect.left = proc_data->srect.left = 0;
+	proc_data->drect.top = proc_data->srect.top = 0;
+	proc_data->drect.width = proc_data->srect.width = 0;
+	proc_data->drect.height = proc_data->srect.height = 0;
+	proc_data->scaling = 0;
+	proc_data->hflip = 0;
+	proc_data->vflip = 0;
+	proc_data->rotate = 0;
+	proc_data->bgcolor = 0;
+
+	/* Initialize S0 channel parameters */
+	pxp_conf->s0_param.pixel_fmt = pxp_s0_formats[0];
+	pxp_conf->s0_param.width = 0;
+	pxp_conf->s0_param.height = 0;
+	pxp_conf->s0_param.color_key = -1;
+	pxp_conf->s0_param.color_key_enable = false;
+
+	/* Initialize OL channel parameters */
+	for (i = 0; i < 8; i++) {
+		pxp_conf->ol_param[i].combine_enable = false;
+		pxp_conf->ol_param[i].width = 0;
+		pxp_conf->ol_param[i].height = 0;
+		pxp_conf->ol_param[i].pixel_fmt = PXP_PIX_FMT_RGB565;
+		pxp_conf->ol_param[i].color_key_enable = false;
+		pxp_conf->ol_param[i].color_key = -1;
+		pxp_conf->ol_param[i].global_alpha_enable = false;
+		pxp_conf->ol_param[i].global_alpha = 0;
+		pxp_conf->ol_param[i].local_alpha_enable = false;
+	}
+
+	/* Initialize Output channel parameters */
+	pxp_conf->out_param.width = 0;
+	pxp_conf->out_param.height = 0;
+	pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_RGB565;
+
+	proc_data->overlay_state = 0;
+
+	/* Write default h/w config */
+	pxp_set_ctrl(pxp);
+	pxp_set_s0param(pxp);
+	pxp_set_s0crop(pxp);
+	for (i = 0; i < 8; i++) {
+		pxp_set_oln(i, pxp);
+		pxp_set_olparam(i, pxp);
+		pxp_set_olcolorkey(i, pxp);
+	}
+	pxp_set_s0colorkey(pxp);
+	pxp_set_csc(pxp);
+	pxp_set_bg(pxp);
+	pxp_set_lut(pxp);
+
+	/* One-time histogram configuration */
+	reg_val =
+	    BF_PXP_HIST_CTRL_PANEL_MODE(BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST_CTRL);
+
+	reg_val = BF_PXP_HIST2_PARAM_VALUE0(0x00) |
+	    BF_PXP_HIST2_PARAM_VALUE1(0x00F);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST2_PARAM);
+
+	reg_val = BF_PXP_HIST4_PARAM_VALUE0(0x00) |
+	    BF_PXP_HIST4_PARAM_VALUE1(0x05) |
+	    BF_PXP_HIST4_PARAM_VALUE2(0x0A) | BF_PXP_HIST4_PARAM_VALUE3(0x0F);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST4_PARAM);
+
+	reg_val = BF_PXP_HIST8_PARAM0_VALUE0(0x00) |
+	    BF_PXP_HIST8_PARAM0_VALUE1(0x02) |
+	    BF_PXP_HIST8_PARAM0_VALUE2(0x04) | BF_PXP_HIST8_PARAM0_VALUE3(0x06);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST8_PARAM0);
+	reg_val = BF_PXP_HIST8_PARAM1_VALUE4(0x09) |
+	    BF_PXP_HIST8_PARAM1_VALUE5(0x0B) |
+	    BF_PXP_HIST8_PARAM1_VALUE6(0x0D) | BF_PXP_HIST8_PARAM1_VALUE7(0x0F);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST8_PARAM1);
+
+	reg_val = BF_PXP_HIST16_PARAM0_VALUE0(0x00) |
+	    BF_PXP_HIST16_PARAM0_VALUE1(0x01) |
+	    BF_PXP_HIST16_PARAM0_VALUE2(0x02) |
+	    BF_PXP_HIST16_PARAM0_VALUE3(0x03);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM0);
+	reg_val = BF_PXP_HIST16_PARAM1_VALUE4(0x04) |
+	    BF_PXP_HIST16_PARAM1_VALUE5(0x05) |
+	    BF_PXP_HIST16_PARAM1_VALUE6(0x06) |
+	    BF_PXP_HIST16_PARAM1_VALUE7(0x07);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM1);
+	reg_val = BF_PXP_HIST16_PARAM2_VALUE8(0x08) |
+	    BF_PXP_HIST16_PARAM2_VALUE9(0x09) |
+	    BF_PXP_HIST16_PARAM2_VALUE10(0x0A) |
+	    BF_PXP_HIST16_PARAM2_VALUE11(0x0B);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM2);
+	reg_val = BF_PXP_HIST16_PARAM3_VALUE12(0x0C) |
+	    BF_PXP_HIST16_PARAM3_VALUE13(0x0D) |
+	    BF_PXP_HIST16_PARAM3_VALUE14(0x0E) |
+	    BF_PXP_HIST16_PARAM3_VALUE15(0x0F);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM3);
+
+	return 0;
+}
+
+static int pxp_dma_init(struct pxps *pxp)
+{
+	struct pxp_dma *pxp_dma = &pxp->pxp_dma;
+	struct dma_device *dma = &pxp_dma->dma;
+	int i;
+
+	dma_cap_set(DMA_SLAVE, dma->cap_mask);
+	dma_cap_set(DMA_PRIVATE, dma->cap_mask);
+
+	/* Compulsory common fields */
+	dma->dev = pxp->dev;
+	dma->device_alloc_chan_resources = pxp_alloc_chan_resources;
+	dma->device_free_chan_resources = pxp_free_chan_resources;
+	dma->device_is_tx_complete = pxp_is_tx_complete;
+	dma->device_issue_pending = pxp_issue_pending;
+
+	/* Compulsory for DMA_SLAVE fields */
+	dma->device_prep_slave_sg = pxp_prep_slave_sg;
+	dma->device_terminate_all = pxp_terminate_all;
+
+	/* Initialize PxP Channels */
+	INIT_LIST_HEAD(&dma->channels);
+	for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) {
+		struct pxp_channel *pxp_chan = pxp->channel + i;
+		struct dma_chan *dma_chan = &pxp_chan->dma_chan;
+
+		spin_lock_init(&pxp_chan->lock);
+		mutex_init(&pxp_chan->chan_mutex);
+
+		/* Only one EOF IRQ for PxP, shared by all channels */
+		pxp_chan->eof_irq = pxp->irq;
+		pxp_chan->status = PXP_CHANNEL_FREE;
+		pxp_chan->completed = -ENXIO;
+		snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name),
+			 "PXP EOF %d", i);
+
+		dma_chan->device = &pxp_dma->dma;
+		dma_chan->cookie = 1;
+		dma_chan->chan_id = i;
+		list_add_tail(&dma_chan->device_node, &dma->channels);
+	}
+
+	return dma_async_device_register(&pxp_dma->dma);
+}
+
+static int pxp_probe(struct platform_device *pdev)
+{
+	struct pxps *pxp;
+	struct resource *res;
+	int irq;
+	int err = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	irq = platform_get_irq(pdev, 0);
+	if (!res || irq < 0) {
+		err = -ENODEV;
+		goto exit;
+	}
+
+	pxp = kzalloc(sizeof(*pxp), GFP_KERNEL);
+	if (!pxp) {
+		dev_err(&pdev->dev, "failed to allocate control object\n");
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	pxp->dev = &pdev->dev;
+
+	platform_set_drvdata(pdev, pxp);
+	pxp->irq = irq;
+
+	spin_lock_init(&pxp->lock);
+	mutex_init(&pxp->mutex);
+
+	if (!request_mem_region(res->start, resource_size(res), "pxp-mem")) {
+		err = -EBUSY;
+		goto freepxp;
+	}
+
+	pxp->base = ioremap(res->start, SZ_4K);
+	pxp->pdev = pdev;
+
+	pxp->clk = clk_get(NULL, "pxp_axi");
+	clk_enable(pxp->clk);
+
+	err = pxp_hw_init(pxp);
+	if (err) {
+		dev_err(&pdev->dev, "failed to initialize hardware\n");
+		goto release;
+	}
+
+	/* Initialize DMA engine */
+	err = pxp_dma_init(pxp);
+	if (err < 0)
+		goto err_dma_init;
+
+	INIT_WORK(&pxp->work, pxpdma_dostart_work);
+	pxp->workqueue = create_singlethread_workqueue("pxp_dma");
+exit:
+	return err;
+err_dma_init:
+	free_irq(pxp->irq, pxp);
+	clk_disable(pxp->clk);
+release:
+	release_mem_region(res->start, resource_size(res));
+freepxp:
+	kfree(pxp);
+	dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe function\n");
+	return err;
+}
+
+static int __devexit pxp_remove(struct platform_device *pdev)
+{
+	struct pxps *pxp = platform_get_drvdata(pdev);
+
+	cancel_work_sync(&pxp->work);
+	kfree(pxp);
+
+	free_irq(pxp->irq, pxp);
+	clk_disable(pxp->clk);
+	clk_put(pxp->clk);
+	iounmap(pxp->base);
+
+	kfree(pxp);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int pxp_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct pxps *pxp = platform_get_drvdata(pdev);
+
+	while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE)
+		;
+
+	__raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL);
+	clk_disable(pxp->clk);
+
+	return 0;
+}
+
+static int pxp_resume(struct platform_device *pdev)
+{
+	struct pxps *pxp = platform_get_drvdata(pdev);
+
+	clk_enable(pxp->clk);
+	/* Pull PxP out of reset */
+	__raw_writel(0, pxp->base + HW_PXP_CTRL);
+
+	return 0;
+}
+#else
+#define	pxp_suspend	NULL
+#define	pxp_resume	NULL
+#endif
+
+static struct platform_driver pxp_driver = {
+	.driver = {
+		   .name = "mxc-pxp",
+		   },
+	.probe = pxp_probe,
+	.remove = __exit_p(pxp_remove),
+	.suspend = pxp_suspend,
+	.resume = pxp_resume,
+};
+
+static int __init pxp_init(void)
+{
+	return platform_driver_register(&pxp_driver);
+}
+
+subsys_initcall(pxp_init);
+
+static void __exit pxp_exit(void)
+{
+	platform_driver_unregister(&pxp_driver);
+}
+
+module_exit(pxp_exit);
+
+MODULE_DESCRIPTION("i.MX PxP driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/dma/pxp/regs-pxp.h b/drivers/dma/pxp/regs-pxp.h
new file mode 100644
index 000000000000..b0c1b00fdfa0
--- /dev/null
+++ b/drivers/dma/pxp/regs-pxp.h
@@ -0,0 +1,949 @@
+/*
+ * Freescale PXP Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.6
+ * Template revision: 1.3
+ */
+
+#ifndef __ARCH_ARM___PXP_H
+#define __ARCH_ARM___PXP_H
+
+
+#define HW_PXP_CTRL	(0x00000000)
+#define HW_PXP_CTRL_SET	(0x00000004)
+#define HW_PXP_CTRL_CLR	(0x00000008)
+#define HW_PXP_CTRL_TOG	(0x0000000c)
+
+#define BM_PXP_CTRL_SFTRST 0x80000000
+#define BM_PXP_CTRL_CLKGATE 0x40000000
+#define BM_PXP_CTRL_RSVD 0x20000000
+#define BM_PXP_CTRL_EN_REPEAT 0x10000000
+#define BP_PXP_CTRL_INTERLACED_OUTPUT      26
+#define BM_PXP_CTRL_INTERLACED_OUTPUT 0x0C000000
+#define BF_PXP_CTRL_INTERLACED_OUTPUT(v)  \
+	(((v) << 26) & BM_PXP_CTRL_INTERLACED_OUTPUT)
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0      0x1
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1      0x2
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED  0x3
+#define BP_PXP_CTRL_INTERLACED_INPUT      24
+#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000
+#define BF_PXP_CTRL_INTERLACED_INPUT(v)  \
+	(((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT)
+#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0
+#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0      0x2
+#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1      0x3
+#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000
+#define BV_PXP_CTRL_BLOCK_SIZE__8X8   0x0
+#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1
+#define BM_PXP_CTRL_ALPHA_OUTPUT 0x00400000
+#define BM_PXP_CTRL_IN_PLACE 0x00200000
+#define BM_PXP_CTRL_DELTA 0x00100000
+#define BM_PXP_CTRL_CROP 0x00080000
+#define BM_PXP_CTRL_SCALE 0x00040000
+#define BM_PXP_CTRL_UPSAMPLE 0x00020000
+#define BM_PXP_CTRL_SUBSAMPLE 0x00010000
+#define BP_PXP_CTRL_S0_FORMAT      12
+#define BM_PXP_CTRL_S0_FORMAT 0x0000F000
+#define BF_PXP_CTRL_S0_FORMAT(v)  \
+	(((v) << 12) & BM_PXP_CTRL_S0_FORMAT)
+#define BV_PXP_CTRL_S0_FORMAT__RGB888    0x1
+#define BV_PXP_CTRL_S0_FORMAT__RGB565    0x4
+#define BV_PXP_CTRL_S0_FORMAT__RGB555    0x5
+#define BV_PXP_CTRL_S0_FORMAT__YUV422    0x8
+#define BV_PXP_CTRL_S0_FORMAT__YUV420    0x9
+#define BV_PXP_CTRL_S0_FORMAT__UYVY1P422 0xA
+#define BV_PXP_CTRL_S0_FORMAT__VYUY1P422 0xB
+#define BV_PXP_CTRL_S0_FORMAT__YUV2P422  0xC
+#define BV_PXP_CTRL_S0_FORMAT__YUV2P420  0xD
+#define BV_PXP_CTRL_S0_FORMAT__YVU2P422  0xE
+#define BV_PXP_CTRL_S0_FORMAT__YVU2P420  0xF
+#define BM_PXP_CTRL_VFLIP 0x00000800
+#define BM_PXP_CTRL_HFLIP 0x00000400
+#define BP_PXP_CTRL_ROTATE      8
+#define BM_PXP_CTRL_ROTATE 0x00000300
+#define BF_PXP_CTRL_ROTATE(v)  \
+	(((v) << 8) & BM_PXP_CTRL_ROTATE)
+#define BV_PXP_CTRL_ROTATE__ROT_0   0x0
+#define BV_PXP_CTRL_ROTATE__ROT_90  0x1
+#define BV_PXP_CTRL_ROTATE__ROT_180 0x2
+#define BV_PXP_CTRL_ROTATE__ROT_270 0x3
+#define BP_PXP_CTRL_OUTBUF_FORMAT      4
+#define BM_PXP_CTRL_OUTBUF_FORMAT 0x000000F0
+#define BF_PXP_CTRL_OUTBUF_FORMAT(v)  \
+	(((v) << 4) & BM_PXP_CTRL_OUTBUF_FORMAT)
+#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB8888  0x0
+#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888    0x1
+#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888P   0x2
+#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB1555  0x3
+#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB565    0x4
+#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB555    0x5
+#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV444    0x7
+#define BV_PXP_CTRL_OUTBUF_FORMAT__MONOC8    0x8
+#define BV_PXP_CTRL_OUTBUF_FORMAT__MONOC4    0x9
+#define BV_PXP_CTRL_OUTBUF_FORMAT__UYVY1P422 0xA
+#define BV_PXP_CTRL_OUTBUF_FORMAT__VYUY1P422 0xB
+#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P422  0xC
+#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P420  0xD
+#define BV_PXP_CTRL_OUTBUF_FORMAT__YVU2P422  0xE
+#define BV_PXP_CTRL_OUTBUF_FORMAT__YVU2P420  0xF
+#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000008
+#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004
+#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
+#define BM_PXP_CTRL_ENABLE 0x00000001
+
+#define HW_PXP_STAT	(0x00000010)
+#define HW_PXP_STAT_SET	(0x00000014)
+#define HW_PXP_STAT_CLR	(0x00000018)
+#define HW_PXP_STAT_TOG	(0x0000001c)
+
+#define BP_PXP_STAT_BLOCKX      24
+#define BM_PXP_STAT_BLOCKX 0xFF000000
+#define BF_PXP_STAT_BLOCKX(v) \
+	(((v) << 24) & BM_PXP_STAT_BLOCKX)
+#define BP_PXP_STAT_BLOCKY      16
+#define BM_PXP_STAT_BLOCKY 0x00FF0000
+#define BF_PXP_STAT_BLOCKY(v)  \
+	(((v) << 16) & BM_PXP_STAT_BLOCKY)
+#define BP_PXP_STAT_RSVD2      8
+#define BM_PXP_STAT_RSVD2 0x0000FF00
+#define BF_PXP_STAT_RSVD2(v)  \
+	(((v) << 8) & BM_PXP_STAT_RSVD2)
+#define BP_PXP_STAT_AXI_ERROR_ID      4
+#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0
+#define BF_PXP_STAT_AXI_ERROR_ID(v)  \
+	(((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID)
+#define BM_PXP_STAT_NEXT_IRQ 0x00000008
+#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004
+#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002
+#define BM_PXP_STAT_IRQ 0x00000001
+
+#define HW_PXP_OUTBUF	(0x00000020)
+
+#define BP_PXP_OUTBUF_ADDR      0
+#define BM_PXP_OUTBUF_ADDR 0xFFFFFFFF
+#define BF_PXP_OUTBUF_ADDR(v)   (v)
+
+#define HW_PXP_OUTBUF2	(0x00000030)
+
+#define BP_PXP_OUTBUF2_ADDR      0
+#define BM_PXP_OUTBUF2_ADDR 0xFFFFFFFF
+#define BF_PXP_OUTBUF2_ADDR(v)   (v)
+
+#define HW_PXP_OUTSIZE	(0x00000040)
+
+#define BP_PXP_OUTSIZE_ALPHA      24
+#define BM_PXP_OUTSIZE_ALPHA 0xFF000000
+#define BF_PXP_OUTSIZE_ALPHA(v) \
+	(((v) << 24) & BM_PXP_OUTSIZE_ALPHA)
+#define BP_PXP_OUTSIZE_WIDTH      12
+#define BM_PXP_OUTSIZE_WIDTH 0x00FFF000
+#define BF_PXP_OUTSIZE_WIDTH(v)  \
+	(((v) << 12) & BM_PXP_OUTSIZE_WIDTH)
+#define BP_PXP_OUTSIZE_HEIGHT      0
+#define BM_PXP_OUTSIZE_HEIGHT 0x00000FFF
+#define BF_PXP_OUTSIZE_HEIGHT(v)  \
+	(((v) << 0) & BM_PXP_OUTSIZE_HEIGHT)
+
+#define HW_PXP_S0BUF	(0x00000050)
+
+#define BP_PXP_S0BUF_ADDR      0
+#define BM_PXP_S0BUF_ADDR 0xFFFFFFFF
+#define BF_PXP_S0BUF_ADDR(v)   (v)
+
+#define HW_PXP_S0UBUF	(0x00000060)
+
+#define BP_PXP_S0UBUF_ADDR      0
+#define BM_PXP_S0UBUF_ADDR 0xFFFFFFFF
+#define BF_PXP_S0UBUF_ADDR(v)   (v)
+
+#define HW_PXP_S0VBUF	(0x00000070)
+
+#define BP_PXP_S0VBUF_ADDR      0
+#define BM_PXP_S0VBUF_ADDR 0xFFFFFFFF
+#define BF_PXP_S0VBUF_ADDR(v)   (v)
+
+#define HW_PXP_S0PARAM	(0x00000080)
+
+#define BP_PXP_S0PARAM_XBASE      24
+#define BM_PXP_S0PARAM_XBASE 0xFF000000
+#define BF_PXP_S0PARAM_XBASE(v) \
+	(((v) << 24) & BM_PXP_S0PARAM_XBASE)
+#define BP_PXP_S0PARAM_YBASE      16
+#define BM_PXP_S0PARAM_YBASE 0x00FF0000
+#define BF_PXP_S0PARAM_YBASE(v)  \
+	(((v) << 16) & BM_PXP_S0PARAM_YBASE)
+#define BP_PXP_S0PARAM_WIDTH      8
+#define BM_PXP_S0PARAM_WIDTH 0x0000FF00
+#define BF_PXP_S0PARAM_WIDTH(v)  \
+	(((v) << 8) & BM_PXP_S0PARAM_WIDTH)
+#define BP_PXP_S0PARAM_HEIGHT      0
+#define BM_PXP_S0PARAM_HEIGHT 0x000000FF
+#define BF_PXP_S0PARAM_HEIGHT(v)  \
+	(((v) << 0) & BM_PXP_S0PARAM_HEIGHT)
+
+#define HW_PXP_S0BACKGROUND	(0x00000090)
+
+#define BP_PXP_S0BACKGROUND_COLOR      0
+#define BM_PXP_S0BACKGROUND_COLOR 0xFFFFFFFF
+#define BF_PXP_S0BACKGROUND_COLOR(v)   (v)
+
+#define HW_PXP_S0CROP	(0x000000a0)
+
+#define BP_PXP_S0CROP_XBASE      24
+#define BM_PXP_S0CROP_XBASE 0xFF000000
+#define BF_PXP_S0CROP_XBASE(v) \
+	(((v) << 24) & BM_PXP_S0CROP_XBASE)
+#define BP_PXP_S0CROP_YBASE      16
+#define BM_PXP_S0CROP_YBASE 0x00FF0000
+#define BF_PXP_S0CROP_YBASE(v)  \
+	(((v) << 16) & BM_PXP_S0CROP_YBASE)
+#define BP_PXP_S0CROP_WIDTH      8
+#define BM_PXP_S0CROP_WIDTH 0x0000FF00
+#define BF_PXP_S0CROP_WIDTH(v)  \
+	(((v) << 8) & BM_PXP_S0CROP_WIDTH)
+#define BP_PXP_S0CROP_HEIGHT      0
+#define BM_PXP_S0CROP_HEIGHT 0x000000FF
+#define BF_PXP_S0CROP_HEIGHT(v)  \
+	(((v) << 0) & BM_PXP_S0CROP_HEIGHT)
+
+#define HW_PXP_S0SCALE	(0x000000b0)
+
+#define BM_PXP_S0SCALE_RSVD2 0x80000000
+#define BP_PXP_S0SCALE_YSCALE      16
+#define BM_PXP_S0SCALE_YSCALE 0x7FFF0000
+#define BF_PXP_S0SCALE_YSCALE(v)  \
+	(((v) << 16) & BM_PXP_S0SCALE_YSCALE)
+#define BM_PXP_S0SCALE_RSVD1 0x00008000
+#define BP_PXP_S0SCALE_XSCALE      0
+#define BM_PXP_S0SCALE_XSCALE 0x00007FFF
+#define BF_PXP_S0SCALE_XSCALE(v)  \
+	(((v) << 0) & BM_PXP_S0SCALE_XSCALE)
+
+#define HW_PXP_S0OFFSET	(0x000000c0)
+
+#define BP_PXP_S0OFFSET_RSVD2      28
+#define BM_PXP_S0OFFSET_RSVD2 0xF0000000
+#define BF_PXP_S0OFFSET_RSVD2(v) \
+	(((v) << 28) & BM_PXP_S0OFFSET_RSVD2)
+#define BP_PXP_S0OFFSET_YOFFSET      16
+#define BM_PXP_S0OFFSET_YOFFSET 0x0FFF0000
+#define BF_PXP_S0OFFSET_YOFFSET(v)  \
+	(((v) << 16) & BM_PXP_S0OFFSET_YOFFSET)
+#define BP_PXP_S0OFFSET_RSVD1      12
+#define BM_PXP_S0OFFSET_RSVD1 0x0000F000
+#define BF_PXP_S0OFFSET_RSVD1(v)  \
+	(((v) << 12) & BM_PXP_S0OFFSET_RSVD1)
+#define BP_PXP_S0OFFSET_XOFFSET      0
+#define BM_PXP_S0OFFSET_XOFFSET 0x00000FFF
+#define BF_PXP_S0OFFSET_XOFFSET(v)  \
+	(((v) << 0) & BM_PXP_S0OFFSET_XOFFSET)
+
+#define HW_PXP_CSCCOEF0	(0x000000d0)
+
+#define BM_PXP_CSCCOEF0_YCBCR_MODE 0x80000000
+#define BM_PXP_CSCCOEF0_BYPASS 0x40000000
+#define BM_PXP_CSCCOEF0_RSVD1 0x20000000
+#define BP_PXP_CSCCOEF0_C0      18
+#define BM_PXP_CSCCOEF0_C0 0x1FFC0000
+#define BF_PXP_CSCCOEF0_C0(v)  \
+	(((v) << 18) & BM_PXP_CSCCOEF0_C0)
+#define BP_PXP_CSCCOEF0_UV_OFFSET      9
+#define BM_PXP_CSCCOEF0_UV_OFFSET 0x0003FE00
+#define BF_PXP_CSCCOEF0_UV_OFFSET(v)  \
+	(((v) << 9) & BM_PXP_CSCCOEF0_UV_OFFSET)
+#define BP_PXP_CSCCOEF0_Y_OFFSET      0
+#define BM_PXP_CSCCOEF0_Y_OFFSET 0x000001FF
+#define BF_PXP_CSCCOEF0_Y_OFFSET(v)  \
+	(((v) << 0) & BM_PXP_CSCCOEF0_Y_OFFSET)
+
+#define HW_PXP_CSCCOEF1	(0x000000e0)
+
+#define BP_PXP_CSCCOEF1_RSVD1      27
+#define BM_PXP_CSCCOEF1_RSVD1 0xF8000000
+#define BF_PXP_CSCCOEF1_RSVD1(v) \
+	(((v) << 27) & BM_PXP_CSCCOEF1_RSVD1)
+#define BP_PXP_CSCCOEF1_C1      16
+#define BM_PXP_CSCCOEF1_C1 0x07FF0000
+#define BF_PXP_CSCCOEF1_C1(v)  \
+	(((v) << 16) & BM_PXP_CSCCOEF1_C1)
+#define BP_PXP_CSCCOEF1_RSVD0      11
+#define BM_PXP_CSCCOEF1_RSVD0 0x0000F800
+#define BF_PXP_CSCCOEF1_RSVD0(v)  \
+	(((v) << 11) & BM_PXP_CSCCOEF1_RSVD0)
+#define BP_PXP_CSCCOEF1_C4      0
+#define BM_PXP_CSCCOEF1_C4 0x000007FF
+#define BF_PXP_CSCCOEF1_C4(v)  \
+	(((v) << 0) & BM_PXP_CSCCOEF1_C4)
+
+#define HW_PXP_CSCCOEF2	(0x000000f0)
+
+#define BP_PXP_CSCCOEF2_RSVD1      27
+#define BM_PXP_CSCCOEF2_RSVD1 0xF8000000
+#define BF_PXP_CSCCOEF2_RSVD1(v) \
+	(((v) << 27) & BM_PXP_CSCCOEF2_RSVD1)
+#define BP_PXP_CSCCOEF2_C2      16
+#define BM_PXP_CSCCOEF2_C2 0x07FF0000
+#define BF_PXP_CSCCOEF2_C2(v)  \
+	(((v) << 16) & BM_PXP_CSCCOEF2_C2)
+#define BP_PXP_CSCCOEF2_RSVD0      11
+#define BM_PXP_CSCCOEF2_RSVD0 0x0000F800
+#define BF_PXP_CSCCOEF2_RSVD0(v)  \
+	(((v) << 11) & BM_PXP_CSCCOEF2_RSVD0)
+#define BP_PXP_CSCCOEF2_C3      0
+#define BM_PXP_CSCCOEF2_C3 0x000007FF
+#define BF_PXP_CSCCOEF2_C3(v)  \
+	(((v) << 0) & BM_PXP_CSCCOEF2_C3)
+
+#define HW_PXP_NEXT	(0x00000100)
+#define HW_PXP_NEXT_SET	(0x00000104)
+#define HW_PXP_NEXT_CLR	(0x00000108)
+#define HW_PXP_NEXT_TOG	(0x0000010c)
+
+#define BP_PXP_NEXT_POINTER      2
+#define BM_PXP_NEXT_POINTER 0xFFFFFFFC
+#define BF_PXP_NEXT_POINTER(v) \
+	(((v) << 2) & BM_PXP_NEXT_POINTER)
+#define BM_PXP_NEXT_RSVD 0x00000002
+#define BM_PXP_NEXT_ENABLED 0x00000001
+
+#define HW_PXP_S0COLORKEYLOW	(0x00000180)
+
+#define BP_PXP_S0COLORKEYLOW_RSVD1      24
+#define BM_PXP_S0COLORKEYLOW_RSVD1 0xFF000000
+#define BF_PXP_S0COLORKEYLOW_RSVD1(v) \
+	(((v) << 24) & BM_PXP_S0COLORKEYLOW_RSVD1)
+#define BP_PXP_S0COLORKEYLOW_PIXEL      0
+#define BM_PXP_S0COLORKEYLOW_PIXEL 0x00FFFFFF
+#define BF_PXP_S0COLORKEYLOW_PIXEL(v)  \
+	(((v) << 0) & BM_PXP_S0COLORKEYLOW_PIXEL)
+
+#define HW_PXP_S0COLORKEYHIGH	(0x00000190)
+
+#define BP_PXP_S0COLORKEYHIGH_RSVD1      24
+#define BM_PXP_S0COLORKEYHIGH_RSVD1 0xFF000000
+#define BF_PXP_S0COLORKEYHIGH_RSVD1(v) \
+	(((v) << 24) & BM_PXP_S0COLORKEYHIGH_RSVD1)
+#define BP_PXP_S0COLORKEYHIGH_PIXEL      0
+#define BM_PXP_S0COLORKEYHIGH_PIXEL 0x00FFFFFF
+#define BF_PXP_S0COLORKEYHIGH_PIXEL(v)  \
+	(((v) << 0) & BM_PXP_S0COLORKEYHIGH_PIXEL)
+
+#define HW_PXP_OLCOLORKEYLOW	(0x000001a0)
+
+#define BP_PXP_OLCOLORKEYLOW_RSVD1      24
+#define BM_PXP_OLCOLORKEYLOW_RSVD1 0xFF000000
+#define BF_PXP_OLCOLORKEYLOW_RSVD1(v) \
+	(((v) << 24) & BM_PXP_OLCOLORKEYLOW_RSVD1)
+#define BP_PXP_OLCOLORKEYLOW_PIXEL      0
+#define BM_PXP_OLCOLORKEYLOW_PIXEL 0x00FFFFFF
+#define BF_PXP_OLCOLORKEYLOW_PIXEL(v)  \
+	(((v) << 0) & BM_PXP_OLCOLORKEYLOW_PIXEL)
+
+#define HW_PXP_OLCOLORKEYHIGH	(0x000001b0)
+
+#define BP_PXP_OLCOLORKEYHIGH_RSVD1      24
+#define BM_PXP_OLCOLORKEYHIGH_RSVD1 0xFF000000
+#define BF_PXP_OLCOLORKEYHIGH_RSVD1(v) \
+	(((v) << 24) & BM_PXP_OLCOLORKEYHIGH_RSVD1)
+#define BP_PXP_OLCOLORKEYHIGH_PIXEL      0
+#define BM_PXP_OLCOLORKEYHIGH_PIXEL 0x00FFFFFF
+#define BF_PXP_OLCOLORKEYHIGH_PIXEL(v)  \
+	(((v) << 0) & BM_PXP_OLCOLORKEYHIGH_PIXEL)
+
+#define HW_PXP_DEBUGCTRL	(0x000001d0)
+
+#define BP_PXP_DEBUGCTRL_RSVD      8
+#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFFF00
+#define BF_PXP_DEBUGCTRL_RSVD(v) \
+	(((v) << 8) & BM_PXP_DEBUGCTRL_RSVD)
+#define BP_PXP_DEBUGCTRL_SELECT      0
+#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF
+#define BF_PXP_DEBUGCTRL_SELECT(v)  \
+	(((v) << 0) & BM_PXP_DEBUGCTRL_SELECT)
+#define BV_PXP_DEBUGCTRL_SELECT__NONE     0x0
+#define BV_PXP_DEBUGCTRL_SELECT__CTRL     0x1
+#define BV_PXP_DEBUGCTRL_SELECT__S0REGS   0x2
+#define BV_PXP_DEBUGCTRL_SELECT__S0BAX    0x3
+#define BV_PXP_DEBUGCTRL_SELECT__S0BAY    0x4
+#define BV_PXP_DEBUGCTRL_SELECT__PXBUF    0x5
+#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6
+#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0  0x7
+#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1  0x8
+
+#define HW_PXP_DEBUG	(0x000001e0)
+
+#define BP_PXP_DEBUG_DATA      0
+#define BM_PXP_DEBUG_DATA 0xFFFFFFFF
+#define BF_PXP_DEBUG_DATA(v)   (v)
+
+#define HW_PXP_VERSION	(0x000001f0)
+
+#define BP_PXP_VERSION_MAJOR      24
+#define BM_PXP_VERSION_MAJOR 0xFF000000
+#define BF_PXP_VERSION_MAJOR(v) \
+	(((v) << 24) & BM_PXP_VERSION_MAJOR)
+#define BP_PXP_VERSION_MINOR      16
+#define BM_PXP_VERSION_MINOR 0x00FF0000
+#define BF_PXP_VERSION_MINOR(v)  \
+	(((v) << 16) & BM_PXP_VERSION_MINOR)
+#define BP_PXP_VERSION_STEP      0
+#define BM_PXP_VERSION_STEP 0x0000FFFF
+#define BF_PXP_VERSION_STEP(v)  \
+	(((v) << 0) & BM_PXP_VERSION_STEP)
+
+/*
+ *  multi-register-define name HW_PXP_OLn
+ *              base 0x00000200
+ *              count 8
+ *              offset 0x40
+ */
+#define HW_PXP_OLn(n)	(0x00000200 + (n) * 0x40)
+#define BP_PXP_OLn_ADDR      0
+#define BM_PXP_OLn_ADDR 0xFFFFFFFF
+#define BF_PXP_OLn_ADDR(v)   (v)
+
+/*
+ *  multi-register-define name HW_PXP_OLnSIZE
+ *              base 0x00000210
+ *              count 8
+ *              offset 0x40
+ */
+#define HW_PXP_OLnSIZE(n)	(0x00000210 + (n) * 0x40)
+#define BP_PXP_OLnSIZE_XBASE      24
+#define BM_PXP_OLnSIZE_XBASE 0xFF000000
+#define BF_PXP_OLnSIZE_XBASE(v) \
+	(((v) << 24) & BM_PXP_OLnSIZE_XBASE)
+#define BP_PXP_OLnSIZE_YBASE      16
+#define BM_PXP_OLnSIZE_YBASE 0x00FF0000
+#define BF_PXP_OLnSIZE_YBASE(v)  \
+	(((v) << 16) & BM_PXP_OLnSIZE_YBASE)
+#define BP_PXP_OLnSIZE_WIDTH      8
+#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00
+#define BF_PXP_OLnSIZE_WIDTH(v)  \
+	(((v) << 8) & BM_PXP_OLnSIZE_WIDTH)
+#define BP_PXP_OLnSIZE_HEIGHT      0
+#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF
+#define BF_PXP_OLnSIZE_HEIGHT(v)  \
+	(((v) << 0) & BM_PXP_OLnSIZE_HEIGHT)
+
+/*
+ *  multi-register-define name HW_PXP_OLnPARAM
+ *              base 0x00000220
+ *              count 8
+ *              offset 0x40
+ */
+#define HW_PXP_OLnPARAM(n)	(0x00000220 + (n) * 0x40)
+#define BP_PXP_OLnPARAM_RSVD1      20
+#define BM_PXP_OLnPARAM_RSVD1 0xFFF00000
+#define BF_PXP_OLnPARAM_RSVD1(v) \
+	(((v) << 20) & BM_PXP_OLnPARAM_RSVD1)
+#define BP_PXP_OLnPARAM_ROP      16
+#define BM_PXP_OLnPARAM_ROP 0x000F0000
+#define BF_PXP_OLnPARAM_ROP(v)  \
+	(((v) << 16) & BM_PXP_OLnPARAM_ROP)
+#define BV_PXP_OLnPARAM_ROP__MASKOL     0x0
+#define BV_PXP_OLnPARAM_ROP__MASKNOTOL  0x1
+#define BV_PXP_OLnPARAM_ROP__MASKOLNOT  0x2
+#define BV_PXP_OLnPARAM_ROP__MERGEOL    0x3
+#define BV_PXP_OLnPARAM_ROP__MERGENOTOL 0x4
+#define BV_PXP_OLnPARAM_ROP__MERGEOLNOT 0x5
+#define BV_PXP_OLnPARAM_ROP__NOTCOPYOL  0x6
+#define BV_PXP_OLnPARAM_ROP__NOT        0x7
+#define BV_PXP_OLnPARAM_ROP__NOTMASKOL  0x8
+#define BV_PXP_OLnPARAM_ROP__NOTMERGEOL 0x9
+#define BV_PXP_OLnPARAM_ROP__XOROL      0xA
+#define BV_PXP_OLnPARAM_ROP__NOTXOROL   0xB
+#define BP_PXP_OLnPARAM_ALPHA      8
+#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00
+#define BF_PXP_OLnPARAM_ALPHA(v)  \
+	(((v) << 8) & BM_PXP_OLnPARAM_ALPHA)
+#define BP_PXP_OLnPARAM_FORMAT      4
+#define BM_PXP_OLnPARAM_FORMAT 0x000000F0
+#define BF_PXP_OLnPARAM_FORMAT(v)  \
+	(((v) << 4) & BM_PXP_OLnPARAM_FORMAT)
+#define BV_PXP_OLnPARAM_FORMAT__ARGB8888 0x0
+#define BV_PXP_OLnPARAM_FORMAT__RGB888   0x1
+#define BV_PXP_OLnPARAM_FORMAT__ARGB1555 0x3
+#define BV_PXP_OLnPARAM_FORMAT__RGB565   0x4
+#define BV_PXP_OLnPARAM_FORMAT__RGB555   0x5
+#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008
+#define BP_PXP_OLnPARAM_ALPHA_CNTL      1
+#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006
+#define BF_PXP_OLnPARAM_ALPHA_CNTL(v)  \
+	(((v) << 1) & BM_PXP_OLnPARAM_ALPHA_CNTL)
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded 0x0
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Override 0x1
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply 0x2
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs     0x3
+#define BM_PXP_OLnPARAM_ENABLE 0x00000001
+
+/*
+ *  multi-register-define name HW_PXP_OLnPARAM2
+ *              base 0x00000230
+ *              count 8
+ *              offset 0x40
+ */
+#define HW_PXP_OLnPARAM2(n)	(0x00000230 + (n) * 0x40)
+#define BP_PXP_OLnPARAM2_RSVD      0
+#define BM_PXP_OLnPARAM2_RSVD 0xFFFFFFFF
+#define BF_PXP_OLnPARAM2_RSVD(v)   (v)
+
+#define HW_PXP_CSC2CTRL	(0x00000400)
+
+#define BP_PXP_CSC2CTRL_RSVD      3
+#define BM_PXP_CSC2CTRL_RSVD 0xFFFFFFF8
+#define BF_PXP_CSC2CTRL_RSVD(v) \
+	(((v) << 3) & BM_PXP_CSC2CTRL_RSVD)
+#define BP_PXP_CSC2CTRL_CSC_MODE      1
+#define BM_PXP_CSC2CTRL_CSC_MODE 0x00000006
+#define BF_PXP_CSC2CTRL_CSC_MODE(v)  \
+	(((v) << 1) & BM_PXP_CSC2CTRL_CSC_MODE)
+#define BV_PXP_CSC2CTRL_CSC_MODE__YUV2RGB   0x0
+#define BV_PXP_CSC2CTRL_CSC_MODE__YCbCr2RGB 0x1
+#define BV_PXP_CSC2CTRL_CSC_MODE__RGB2YUV   0x2
+#define BV_PXP_CSC2CTRL_CSC_MODE__RGB2YCbCr 0x3
+#define BM_PXP_CSC2CTRL_BYPASS 0x00000001
+
+#define HW_PXP_CSC2COEF0	(0x00000410)
+
+#define BP_PXP_CSC2COEF0_RSVD1      27
+#define BM_PXP_CSC2COEF0_RSVD1 0xF8000000
+#define BF_PXP_CSC2COEF0_RSVD1(v) \
+	(((v) << 27) & BM_PXP_CSC2COEF0_RSVD1)
+#define BP_PXP_CSC2COEF0_A2      16
+#define BM_PXP_CSC2COEF0_A2 0x07FF0000
+#define BF_PXP_CSC2COEF0_A2(v)  \
+	(((v) << 16) & BM_PXP_CSC2COEF0_A2)
+#define BP_PXP_CSC2COEF0_RSVD0      11
+#define BM_PXP_CSC2COEF0_RSVD0 0x0000F800
+#define BF_PXP_CSC2COEF0_RSVD0(v)  \
+	(((v) << 11) & BM_PXP_CSC2COEF0_RSVD0)
+#define BP_PXP_CSC2COEF0_A1      0
+#define BM_PXP_CSC2COEF0_A1 0x000007FF
+#define BF_PXP_CSC2COEF0_A1(v)  \
+	(((v) << 0) & BM_PXP_CSC2COEF0_A1)
+
+#define HW_PXP_CSC2COEF1	(0x00000420)
+
+#define BP_PXP_CSC2COEF1_RSVD1      27
+#define BM_PXP_CSC2COEF1_RSVD1 0xF8000000
+#define BF_PXP_CSC2COEF1_RSVD1(v) \
+	(((v) << 27) & BM_PXP_CSC2COEF1_RSVD1)
+#define BP_PXP_CSC2COEF1_B1      16
+#define BM_PXP_CSC2COEF1_B1 0x07FF0000
+#define BF_PXP_CSC2COEF1_B1(v)  \
+	(((v) << 16) & BM_PXP_CSC2COEF1_B1)
+#define BP_PXP_CSC2COEF1_RSVD0      11
+#define BM_PXP_CSC2COEF1_RSVD0 0x0000F800
+#define BF_PXP_CSC2COEF1_RSVD0(v)  \
+	(((v) << 11) & BM_PXP_CSC2COEF1_RSVD0)
+#define BP_PXP_CSC2COEF1_A3      0
+#define BM_PXP_CSC2COEF1_A3 0x000007FF
+#define BF_PXP_CSC2COEF1_A3(v)  \
+	(((v) << 0) & BM_PXP_CSC2COEF1_A3)
+
+#define HW_PXP_CSC2COEF2	(0x00000430)
+
+#define BP_PXP_CSC2COEF2_RSVD1      27
+#define BM_PXP_CSC2COEF2_RSVD1 0xF8000000
+#define BF_PXP_CSC2COEF2_RSVD1(v) \
+	(((v) << 27) & BM_PXP_CSC2COEF2_RSVD1)
+#define BP_PXP_CSC2COEF2_B3      16
+#define BM_PXP_CSC2COEF2_B3 0x07FF0000
+#define BF_PXP_CSC2COEF2_B3(v)  \
+	(((v) << 16) & BM_PXP_CSC2COEF2_B3)
+#define BP_PXP_CSC2COEF2_RSVD0      11
+#define BM_PXP_CSC2COEF2_RSVD0 0x0000F800
+#define BF_PXP_CSC2COEF2_RSVD0(v)  \
+	(((v) << 11) & BM_PXP_CSC2COEF2_RSVD0)
+#define BP_PXP_CSC2COEF2_B2      0
+#define BM_PXP_CSC2COEF2_B2 0x000007FF
+#define BF_PXP_CSC2COEF2_B2(v)  \
+	(((v) << 0) & BM_PXP_CSC2COEF2_B2)
+
+#define HW_PXP_CSC2COEF3	(0x00000440)
+
+#define BP_PXP_CSC2COEF3_RSVD1      27
+#define BM_PXP_CSC2COEF3_RSVD1 0xF8000000
+#define BF_PXP_CSC2COEF3_RSVD1(v) \
+	(((v) << 27) & BM_PXP_CSC2COEF3_RSVD1)
+#define BP_PXP_CSC2COEF3_C2      16
+#define BM_PXP_CSC2COEF3_C2 0x07FF0000
+#define BF_PXP_CSC2COEF3_C2(v)  \
+	(((v) << 16) & BM_PXP_CSC2COEF3_C2)
+#define BP_PXP_CSC2COEF3_RSVD0      11
+#define BM_PXP_CSC2COEF3_RSVD0 0x0000F800
+#define BF_PXP_CSC2COEF3_RSVD0(v)  \
+	(((v) << 11) & BM_PXP_CSC2COEF3_RSVD0)
+#define BP_PXP_CSC2COEF3_C1      0
+#define BM_PXP_CSC2COEF3_C1 0x000007FF
+#define BF_PXP_CSC2COEF3_C1(v)  \
+	(((v) << 0) & BM_PXP_CSC2COEF3_C1)
+
+#define HW_PXP_CSC2COEF4	(0x00000450)
+
+#define BP_PXP_CSC2COEF4_RSVD1      25
+#define BM_PXP_CSC2COEF4_RSVD1 0xFE000000
+#define BF_PXP_CSC2COEF4_RSVD1(v) \
+	(((v) << 25) & BM_PXP_CSC2COEF4_RSVD1)
+#define BP_PXP_CSC2COEF4_D1      16
+#define BM_PXP_CSC2COEF4_D1 0x01FF0000
+#define BF_PXP_CSC2COEF4_D1(v)  \
+	(((v) << 16) & BM_PXP_CSC2COEF4_D1)
+#define BP_PXP_CSC2COEF4_RSVD0      11
+#define BM_PXP_CSC2COEF4_RSVD0 0x0000F800
+#define BF_PXP_CSC2COEF4_RSVD0(v)  \
+	(((v) << 11) & BM_PXP_CSC2COEF4_RSVD0)
+#define BP_PXP_CSC2COEF4_C3      0
+#define BM_PXP_CSC2COEF4_C3 0x000007FF
+#define BF_PXP_CSC2COEF4_C3(v)  \
+	(((v) << 0) & BM_PXP_CSC2COEF4_C3)
+
+#define HW_PXP_CSC2COEF5	(0x00000460)
+
+#define BP_PXP_CSC2COEF5_RSVD1      25
+#define BM_PXP_CSC2COEF5_RSVD1 0xFE000000
+#define BF_PXP_CSC2COEF5_RSVD1(v) \
+	(((v) << 25) & BM_PXP_CSC2COEF5_RSVD1)
+#define BP_PXP_CSC2COEF5_D3      16
+#define BM_PXP_CSC2COEF5_D3 0x01FF0000
+#define BF_PXP_CSC2COEF5_D3(v)  \
+	(((v) << 16) & BM_PXP_CSC2COEF5_D3)
+#define BP_PXP_CSC2COEF5_RSVD0      9
+#define BM_PXP_CSC2COEF5_RSVD0 0x0000FE00
+#define BF_PXP_CSC2COEF5_RSVD0(v)  \
+	(((v) << 9) & BM_PXP_CSC2COEF5_RSVD0)
+#define BP_PXP_CSC2COEF5_D2      0
+#define BM_PXP_CSC2COEF5_D2 0x000001FF
+#define BF_PXP_CSC2COEF5_D2(v)  \
+	(((v) << 0) & BM_PXP_CSC2COEF5_D2)
+
+#define HW_PXP_LUT_CTRL	(0x00000470)
+
+#define BM_PXP_LUT_CTRL_BYPASS 0x80000000
+#define BP_PXP_LUT_CTRL_RSVD      8
+#define BM_PXP_LUT_CTRL_RSVD 0x7FFFFF00
+#define BF_PXP_LUT_CTRL_RSVD(v)  \
+	(((v) << 8) & BM_PXP_LUT_CTRL_RSVD)
+#define BP_PXP_LUT_CTRL_ADDR      0
+#define BM_PXP_LUT_CTRL_ADDR 0x000000FF
+#define BF_PXP_LUT_CTRL_ADDR(v)  \
+	(((v) << 0) & BM_PXP_LUT_CTRL_ADDR)
+
+#define HW_PXP_LUT	(0x00000480)
+
+#define BP_PXP_LUT_RSVD      8
+#define BM_PXP_LUT_RSVD 0xFFFFFF00
+#define BF_PXP_LUT_RSVD(v) \
+	(((v) << 8) & BM_PXP_LUT_RSVD)
+#define BP_PXP_LUT_DATA      0
+#define BM_PXP_LUT_DATA 0x000000FF
+#define BF_PXP_LUT_DATA(v)  \
+	(((v) << 0) & BM_PXP_LUT_DATA)
+
+#define HW_PXP_HIST_CTRL	(0x00000490)
+
+#define BP_PXP_HIST_CTRL_RSVD      6
+#define BM_PXP_HIST_CTRL_RSVD 0xFFFFFFC0
+#define BF_PXP_HIST_CTRL_RSVD(v) \
+	(((v) << 6) & BM_PXP_HIST_CTRL_RSVD)
+#define BP_PXP_HIST_CTRL_PANEL_MODE      4
+#define BM_PXP_HIST_CTRL_PANEL_MODE 0x00000030
+#define BF_PXP_HIST_CTRL_PANEL_MODE(v)  \
+	(((v) << 4) & BM_PXP_HIST_CTRL_PANEL_MODE)
+#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY4  0x0
+#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY8  0x1
+#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16 0x2
+#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY32 0x3
+#define BP_PXP_HIST_CTRL_STATUS      0
+#define BM_PXP_HIST_CTRL_STATUS 0x0000000F
+#define BF_PXP_HIST_CTRL_STATUS(v)  \
+	(((v) << 0) & BM_PXP_HIST_CTRL_STATUS)
+
+#define HW_PXP_HIST2_PARAM	(0x000004a0)
+
+#define BP_PXP_HIST2_PARAM_RSVD      16
+#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000
+#define BF_PXP_HIST2_PARAM_RSVD(v) \
+	(((v) << 16) & BM_PXP_HIST2_PARAM_RSVD)
+#define BP_PXP_HIST2_PARAM_RSVD1      13
+#define BM_PXP_HIST2_PARAM_RSVD1 0x0000E000
+#define BF_PXP_HIST2_PARAM_RSVD1(v)  \
+	(((v) << 13) & BM_PXP_HIST2_PARAM_RSVD1)
+#define BP_PXP_HIST2_PARAM_VALUE1      8
+#define BM_PXP_HIST2_PARAM_VALUE1 0x00001F00
+#define BF_PXP_HIST2_PARAM_VALUE1(v)  \
+	(((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1)
+#define BP_PXP_HIST2_PARAM_RSVD0      5
+#define BM_PXP_HIST2_PARAM_RSVD0 0x000000E0
+#define BF_PXP_HIST2_PARAM_RSVD0(v)  \
+	(((v) << 5) & BM_PXP_HIST2_PARAM_RSVD0)
+#define BP_PXP_HIST2_PARAM_VALUE0      0
+#define BM_PXP_HIST2_PARAM_VALUE0 0x0000001F
+#define BF_PXP_HIST2_PARAM_VALUE0(v)  \
+	(((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0)
+
+#define HW_PXP_HIST4_PARAM	(0x000004b0)
+
+#define BP_PXP_HIST4_PARAM_RSVD3      29
+#define BM_PXP_HIST4_PARAM_RSVD3 0xE0000000
+#define BF_PXP_HIST4_PARAM_RSVD3(v) \
+	(((v) << 29) & BM_PXP_HIST4_PARAM_RSVD3)
+#define BP_PXP_HIST4_PARAM_VALUE3      24
+#define BM_PXP_HIST4_PARAM_VALUE3 0x1F000000
+#define BF_PXP_HIST4_PARAM_VALUE3(v)  \
+	(((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3)
+#define BP_PXP_HIST4_PARAM_RSVD2      21
+#define BM_PXP_HIST4_PARAM_RSVD2 0x00E00000
+#define BF_PXP_HIST4_PARAM_RSVD2(v)  \
+	(((v) << 21) & BM_PXP_HIST4_PARAM_RSVD2)
+#define BP_PXP_HIST4_PARAM_VALUE2      16
+#define BM_PXP_HIST4_PARAM_VALUE2 0x001F0000
+#define BF_PXP_HIST4_PARAM_VALUE2(v)  \
+	(((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2)
+#define BP_PXP_HIST4_PARAM_RSVD1      13
+#define BM_PXP_HIST4_PARAM_RSVD1 0x0000E000
+#define BF_PXP_HIST4_PARAM_RSVD1(v)  \
+	(((v) << 13) & BM_PXP_HIST4_PARAM_RSVD1)
+#define BP_PXP_HIST4_PARAM_VALUE1      8
+#define BM_PXP_HIST4_PARAM_VALUE1 0x00001F00
+#define BF_PXP_HIST4_PARAM_VALUE1(v)  \
+	(((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1)
+#define BP_PXP_HIST4_PARAM_RSVD0      5
+#define BM_PXP_HIST4_PARAM_RSVD0 0x000000E0
+#define BF_PXP_HIST4_PARAM_RSVD0(v)  \
+	(((v) << 5) & BM_PXP_HIST4_PARAM_RSVD0)
+#define BP_PXP_HIST4_PARAM_VALUE0      0
+#define BM_PXP_HIST4_PARAM_VALUE0 0x0000001F
+#define BF_PXP_HIST4_PARAM_VALUE0(v)  \
+	(((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0)
+
+#define HW_PXP_HIST8_PARAM0	(0x000004c0)
+
+#define BP_PXP_HIST8_PARAM0_RSVD3      29
+#define BM_PXP_HIST8_PARAM0_RSVD3 0xE0000000
+#define BF_PXP_HIST8_PARAM0_RSVD3(v) \
+	(((v) << 29) & BM_PXP_HIST8_PARAM0_RSVD3)
+#define BP_PXP_HIST8_PARAM0_VALUE3      24
+#define BM_PXP_HIST8_PARAM0_VALUE3 0x1F000000
+#define BF_PXP_HIST8_PARAM0_VALUE3(v)  \
+	(((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3)
+#define BP_PXP_HIST8_PARAM0_RSVD2      21
+#define BM_PXP_HIST8_PARAM0_RSVD2 0x00E00000
+#define BF_PXP_HIST8_PARAM0_RSVD2(v)  \
+	(((v) << 21) & BM_PXP_HIST8_PARAM0_RSVD2)
+#define BP_PXP_HIST8_PARAM0_VALUE2      16
+#define BM_PXP_HIST8_PARAM0_VALUE2 0x001F0000
+#define BF_PXP_HIST8_PARAM0_VALUE2(v)  \
+	(((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2)
+#define BP_PXP_HIST8_PARAM0_RSVD1      13
+#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000E000
+#define BF_PXP_HIST8_PARAM0_RSVD1(v)  \
+	(((v) << 13) & BM_PXP_HIST8_PARAM0_RSVD1)
+#define BP_PXP_HIST8_PARAM0_VALUE1      8
+#define BM_PXP_HIST8_PARAM0_VALUE1 0x00001F00
+#define BF_PXP_HIST8_PARAM0_VALUE1(v)  \
+	(((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1)
+#define BP_PXP_HIST8_PARAM0_RSVD0      5
+#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000E0
+#define BF_PXP_HIST8_PARAM0_RSVD0(v)  \
+	(((v) << 5) & BM_PXP_HIST8_PARAM0_RSVD0)
+#define BP_PXP_HIST8_PARAM0_VALUE0      0
+#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000001F
+#define BF_PXP_HIST8_PARAM0_VALUE0(v)  \
+	(((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0)
+
+#define HW_PXP_HIST8_PARAM1	(0x000004d0)
+
+#define BP_PXP_HIST8_PARAM1_RSVD7      29
+#define BM_PXP_HIST8_PARAM1_RSVD7 0xE0000000
+#define BF_PXP_HIST8_PARAM1_RSVD7(v) \
+	(((v) << 29) & BM_PXP_HIST8_PARAM1_RSVD7)
+#define BP_PXP_HIST8_PARAM1_VALUE7      24
+#define BM_PXP_HIST8_PARAM1_VALUE7 0x1F000000
+#define BF_PXP_HIST8_PARAM1_VALUE7(v)  \
+	(((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7)
+#define BP_PXP_HIST8_PARAM1_RSVD6      21
+#define BM_PXP_HIST8_PARAM1_RSVD6 0x00E00000
+#define BF_PXP_HIST8_PARAM1_RSVD6(v)  \
+	(((v) << 21) & BM_PXP_HIST8_PARAM1_RSVD6)
+#define BP_PXP_HIST8_PARAM1_VALUE6      16
+#define BM_PXP_HIST8_PARAM1_VALUE6 0x001F0000
+#define BF_PXP_HIST8_PARAM1_VALUE6(v)  \
+	(((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6)
+#define BP_PXP_HIST8_PARAM1_RSVD5      13
+#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000E000
+#define BF_PXP_HIST8_PARAM1_RSVD5(v)  \
+	(((v) << 13) & BM_PXP_HIST8_PARAM1_RSVD5)
+#define BP_PXP_HIST8_PARAM1_VALUE5      8
+#define BM_PXP_HIST8_PARAM1_VALUE5 0x00001F00
+#define BF_PXP_HIST8_PARAM1_VALUE5(v)  \
+	(((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5)
+#define BP_PXP_HIST8_PARAM1_RSVD4      5
+#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000E0
+#define BF_PXP_HIST8_PARAM1_RSVD4(v)  \
+	(((v) << 5) & BM_PXP_HIST8_PARAM1_RSVD4)
+#define BP_PXP_HIST8_PARAM1_VALUE4      0
+#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000001F
+#define BF_PXP_HIST8_PARAM1_VALUE4(v)  \
+	(((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4)
+
+#define HW_PXP_HIST16_PARAM0	(0x000004e0)
+
+#define BP_PXP_HIST16_PARAM0_RSVD3      29
+#define BM_PXP_HIST16_PARAM0_RSVD3 0xE0000000
+#define BF_PXP_HIST16_PARAM0_RSVD3(v) \
+	(((v) << 29) & BM_PXP_HIST16_PARAM0_RSVD3)
+#define BP_PXP_HIST16_PARAM0_VALUE3      24
+#define BM_PXP_HIST16_PARAM0_VALUE3 0x1F000000
+#define BF_PXP_HIST16_PARAM0_VALUE3(v)  \
+	(((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3)
+#define BP_PXP_HIST16_PARAM0_RSVD2      21
+#define BM_PXP_HIST16_PARAM0_RSVD2 0x00E00000
+#define BF_PXP_HIST16_PARAM0_RSVD2(v)  \
+	(((v) << 21) & BM_PXP_HIST16_PARAM0_RSVD2)
+#define BP_PXP_HIST16_PARAM0_VALUE2      16
+#define BM_PXP_HIST16_PARAM0_VALUE2 0x001F0000
+#define BF_PXP_HIST16_PARAM0_VALUE2(v)  \
+	(((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2)
+#define BP_PXP_HIST16_PARAM0_RSVD1      13
+#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000E000
+#define BF_PXP_HIST16_PARAM0_RSVD1(v)  \
+	(((v) << 13) & BM_PXP_HIST16_PARAM0_RSVD1)
+#define BP_PXP_HIST16_PARAM0_VALUE1      8
+#define BM_PXP_HIST16_PARAM0_VALUE1 0x00001F00
+#define BF_PXP_HIST16_PARAM0_VALUE1(v)  \
+	(((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1)
+#define BP_PXP_HIST16_PARAM0_RSVD0      5
+#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000E0
+#define BF_PXP_HIST16_PARAM0_RSVD0(v)  \
+	(((v) << 5) & BM_PXP_HIST16_PARAM0_RSVD0)
+#define BP_PXP_HIST16_PARAM0_VALUE0      0
+#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000001F
+#define BF_PXP_HIST16_PARAM0_VALUE0(v)  \
+	(((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0)
+
+#define HW_PXP_HIST16_PARAM1	(0x000004f0)
+
+#define BP_PXP_HIST16_PARAM1_RSVD7      29
+#define BM_PXP_HIST16_PARAM1_RSVD7 0xE0000000
+#define BF_PXP_HIST16_PARAM1_RSVD7(v) \
+	(((v) << 29) & BM_PXP_HIST16_PARAM1_RSVD7)
+#define BP_PXP_HIST16_PARAM1_VALUE7      24
+#define BM_PXP_HIST16_PARAM1_VALUE7 0x1F000000
+#define BF_PXP_HIST16_PARAM1_VALUE7(v)  \
+	(((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7)
+#define BP_PXP_HIST16_PARAM1_RSVD6      21
+#define BM_PXP_HIST16_PARAM1_RSVD6 0x00E00000
+#define BF_PXP_HIST16_PARAM1_RSVD6(v)  \
+	(((v) << 21) & BM_PXP_HIST16_PARAM1_RSVD6)
+#define BP_PXP_HIST16_PARAM1_VALUE6      16
+#define BM_PXP_HIST16_PARAM1_VALUE6 0x001F0000
+#define BF_PXP_HIST16_PARAM1_VALUE6(v)  \
+	(((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6)
+#define BP_PXP_HIST16_PARAM1_RSVD5      13
+#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000E000
+#define BF_PXP_HIST16_PARAM1_RSVD5(v)  \
+	(((v) << 13) & BM_PXP_HIST16_PARAM1_RSVD5)
+#define BP_PXP_HIST16_PARAM1_VALUE5      8
+#define BM_PXP_HIST16_PARAM1_VALUE5 0x00001F00
+#define BF_PXP_HIST16_PARAM1_VALUE5(v)  \
+	(((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5)
+#define BP_PXP_HIST16_PARAM1_RSVD4      5
+#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000E0
+#define BF_PXP_HIST16_PARAM1_RSVD4(v)  \
+	(((v) << 5) & BM_PXP_HIST16_PARAM1_RSVD4)
+#define BP_PXP_HIST16_PARAM1_VALUE4      0
+#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000001F
+#define BF_PXP_HIST16_PARAM1_VALUE4(v)  \
+	(((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4)
+
+#define HW_PXP_HIST16_PARAM2	(0x00000500)
+
+#define BP_PXP_HIST16_PARAM2_RSVD11      29
+#define BM_PXP_HIST16_PARAM2_RSVD11 0xE0000000
+#define BF_PXP_HIST16_PARAM2_RSVD11(v) \
+	(((v) << 29) & BM_PXP_HIST16_PARAM2_RSVD11)
+#define BP_PXP_HIST16_PARAM2_VALUE11      24
+#define BM_PXP_HIST16_PARAM2_VALUE11 0x1F000000
+#define BF_PXP_HIST16_PARAM2_VALUE11(v)  \
+	(((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11)
+#define BP_PXP_HIST16_PARAM2_RSVD10      21
+#define BM_PXP_HIST16_PARAM2_RSVD10 0x00E00000
+#define BF_PXP_HIST16_PARAM2_RSVD10(v)  \
+	(((v) << 21) & BM_PXP_HIST16_PARAM2_RSVD10)
+#define BP_PXP_HIST16_PARAM2_VALUE10      16
+#define BM_PXP_HIST16_PARAM2_VALUE10 0x001F0000
+#define BF_PXP_HIST16_PARAM2_VALUE10(v)  \
+	(((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10)
+#define BP_PXP_HIST16_PARAM2_RSVD9      13
+#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000E000
+#define BF_PXP_HIST16_PARAM2_RSVD9(v)  \
+	(((v) << 13) & BM_PXP_HIST16_PARAM2_RSVD9)
+#define BP_PXP_HIST16_PARAM2_VALUE9      8
+#define BM_PXP_HIST16_PARAM2_VALUE9 0x00001F00
+#define BF_PXP_HIST16_PARAM2_VALUE9(v)  \
+	(((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9)
+#define BP_PXP_HIST16_PARAM2_RSVD8      5
+#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000E0
+#define BF_PXP_HIST16_PARAM2_RSVD8(v)  \
+	(((v) << 5) & BM_PXP_HIST16_PARAM2_RSVD8)
+#define BP_PXP_HIST16_PARAM2_VALUE8      0
+#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000001F
+#define BF_PXP_HIST16_PARAM2_VALUE8(v)  \
+	(((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8)
+
+#define HW_PXP_HIST16_PARAM3	(0x00000510)
+
+#define BP_PXP_HIST16_PARAM3_RSVD15      29
+#define BM_PXP_HIST16_PARAM3_RSVD15 0xE0000000
+#define BF_PXP_HIST16_PARAM3_RSVD15(v) \
+	(((v) << 29) & BM_PXP_HIST16_PARAM3_RSVD15)
+#define BP_PXP_HIST16_PARAM3_VALUE15      24
+#define BM_PXP_HIST16_PARAM3_VALUE15 0x1F000000
+#define BF_PXP_HIST16_PARAM3_VALUE15(v)  \
+	(((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15)
+#define BP_PXP_HIST16_PARAM3_RSVD14      21
+#define BM_PXP_HIST16_PARAM3_RSVD14 0x00E00000
+#define BF_PXP_HIST16_PARAM3_RSVD14(v)  \
+	(((v) << 21) & BM_PXP_HIST16_PARAM3_RSVD14)
+#define BP_PXP_HIST16_PARAM3_VALUE14      16
+#define BM_PXP_HIST16_PARAM3_VALUE14 0x001F0000
+#define BF_PXP_HIST16_PARAM3_VALUE14(v)  \
+	(((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14)
+#define BP_PXP_HIST16_PARAM3_RSVD13      13
+#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000E000
+#define BF_PXP_HIST16_PARAM3_RSVD13(v)  \
+	(((v) << 13) & BM_PXP_HIST16_PARAM3_RSVD13)
+#define BP_PXP_HIST16_PARAM3_VALUE13      8
+#define BM_PXP_HIST16_PARAM3_VALUE13 0x00001F00
+#define BF_PXP_HIST16_PARAM3_VALUE13(v)  \
+	(((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13)
+#define BP_PXP_HIST16_PARAM3_RSVD12      5
+#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000E0
+#define BF_PXP_HIST16_PARAM3_RSVD12(v)  \
+	(((v) << 5) & BM_PXP_HIST16_PARAM3_RSVD12)
+#define BP_PXP_HIST16_PARAM3_VALUE12      0
+#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000001F
+#define BF_PXP_HIST16_PARAM3_VALUE12(v)  \
+	(((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12)
+#endif /* __ARCH_ARM___PXP_H */
diff --git a/drivers/edac/i5000_edac.c b/drivers/edac/i5000_edac.c
index d335086f4a26..0bd85eb99e6e 100644
--- a/drivers/edac/i5000_edac.c
+++ b/drivers/edac/i5000_edac.c
@@ -577,7 +577,13 @@ static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
 		debugf0("\tUncorrected bits= 0x%x\n", ue_errors);
 
 		branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
-		channel = branch;
+
+		/*
+		 * According with i5000 datasheet, bit 28 has no significance
+		 * for errors M4Err-M12Err and M17Err-M21Err, on FERR_NF_FBD
+		 */
+		channel = branch & 2;
+
 		bank = NREC_BANK(info->nrecmema);
 		rank = NREC_RANK(info->nrecmema);
 		rdwr = NREC_RDWR(info->nrecmema);
diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c
index 76b321bb73f9..e5827da92296 100644
--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
@@ -2180,6 +2180,13 @@ static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
 	page     = payload >> PAGE_SHIFT;
 	offset   = payload & ~PAGE_MASK;
 	rest     = p->payload_length;
+	/*
+	 * The controllers I've tested have not worked correctly when
+	 * second_req_count is zero.  Rather than do something we know won't
+	 * work, return an error
+	 */
+	if (rest == 0)
+		return -EINVAL;
 
 	/* FIXME: make packet-per-buffer/dual-buffer a context option */
 	while (rest > 0) {
@@ -2233,7 +2240,7 @@ static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
 					unsigned long payload)
 {
 	struct iso_context *ctx = container_of(base, struct iso_context, base);
-	struct descriptor *d = NULL, *pd = NULL;
+	struct descriptor *d, *pd;
 	struct fw_iso_packet *p = packet;
 	dma_addr_t d_bus, page_bus;
 	u32 z, header_z, rest;
@@ -2271,8 +2278,9 @@ static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
 		d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
 
 		rest = payload_per_buffer;
+		pd = d;
 		for (j = 1; j < z; j++) {
-			pd = d + j;
+			pd++;
 			pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
 						  DESCRIPTOR_INPUT_MORE);
 
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 39b393d38bb3..012cf1f7b8db 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -82,6 +82,7 @@ config DRM_I830
 config DRM_I915
 	tristate "i915 driver"
 	depends on AGP_INTEL
+	select SHMEM
 	select FB_CFB_FILLRECT
 	select FB_CFB_COPYAREA
 	select FB_CFB_IMAGEBLIT
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 7f2728bbc16c..55fb98d179ef 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -333,6 +333,12 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
 	mode->vsync_end = mode->vsync_start + vsync_pulse_width;
 	mode->vtotal = mode->vdisplay + vblank;
 
+	/* Some EDIDs have bogus h/vtotal values */
+	if (mode->hsync_end > mode->htotal)
+		mode->htotal = mode->hsync_end + 1;
+	if (mode->vsync_end > mode->vtotal)
+		mode->vtotal = mode->vsync_end + 1;
+
 	drm_mode_set_name(mode);
 
 	if (pt->misc & DRM_EDID_PT_INTERLACED)
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index f85aaf21e783..f298434e87c7 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -402,15 +402,21 @@ int drm_vblank_get(struct drm_device *dev, int crtc)
 
 	spin_lock_irqsave(&dev->vbl_lock, irqflags);
 	/* Going from 0->1 means we have to enable interrupts again */
-	if (atomic_add_return(1, &dev->vblank_refcount[crtc]) == 1 &&
-	    !dev->vblank_enabled[crtc]) {
-		ret = dev->driver->enable_vblank(dev, crtc);
-		DRM_DEBUG("enabling vblank on crtc %d, ret: %d\n", crtc, ret);
-		if (ret)
+	if (atomic_add_return(1, &dev->vblank_refcount[crtc]) == 1) {
+		if (!dev->vblank_enabled[crtc]) {
+			ret = dev->driver->enable_vblank(dev, crtc);
+			DRM_DEBUG("enabling vblank on crtc %d, ret: %d\n", crtc, ret);
+			if (ret)
+				atomic_dec(&dev->vblank_refcount[crtc]);
+			else {
+				dev->vblank_enabled[crtc] = 1;
+				drm_update_vblank_count(dev, crtc);
+			}
+		}
+	} else {
+		if (!dev->vblank_enabled[crtc]) {
 			atomic_dec(&dev->vblank_refcount[crtc]);
-		else {
-			dev->vblank_enabled[crtc] = 1;
-			drm_update_vblank_count(dev, crtc);
+			ret = -EINVAL;
 		}
 	}
 	spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
@@ -437,6 +443,18 @@ void drm_vblank_put(struct drm_device *dev, int crtc)
 }
 EXPORT_SYMBOL(drm_vblank_put);
 
+void drm_vblank_off(struct drm_device *dev, int crtc)
+{
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&dev->vbl_lock, irqflags);
+	DRM_WAKEUP(&dev->vbl_queue[crtc]);
+	dev->vblank_enabled[crtc] = 0;
+	dev->last_vblank[crtc] = dev->driver->get_vblank_counter(dev, crtc);
+	spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
+}
+EXPORT_SYMBOL(drm_vblank_off);
+
 /**
  * drm_vblank_pre_modeset - account for vblanks across mode sets
  * @dev: DRM device
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fc4b68aa2d05..c078d995aa91 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -94,8 +94,6 @@ static int i915_resume(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret = 0;
 
-	pci_set_power_state(dev->pdev, PCI_D0);
-	pci_restore_state(dev->pdev);
 	if (pci_enable_device(dev->pdev))
 		return -1;
 	pci_set_master(dev->pdev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5b4f87e55621..d3f365d8b6ef 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -264,6 +264,7 @@ typedef struct drm_i915_private {
 	u32 saveDSPASURF;
 	u32 saveDSPATILEOFF;
 	u32 savePFIT_PGM_RATIOS;
+	u32 saveBLC_HIST_CTL;
 	u32 saveBLC_PWM_CTL;
 	u32 saveBLC_PWM_CTL2;
 	u32 saveFPB0;
@@ -837,6 +838,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
+#define IS_I8XX(dev) (IS_I830(dev) || IS_845G(dev) || IS_I85X(dev) || IS_I865G(dev))
 
 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
@@ -854,6 +856,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 		       (dev)->pci_device == 0x2E12 || \
 		       (dev)->pci_device == 0x2E22 || \
 		       (dev)->pci_device == 0x2E32 || \
+		       (dev)->pci_device == 0x2E42 || \
 		       (dev)->pci_device == 0x0042 || \
 		       (dev)->pci_device == 0x0046)
 
@@ -866,6 +869,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 		     (dev)->pci_device == 0x2E12 || \
 		     (dev)->pci_device == 0x2E22 || \
 		     (dev)->pci_device == 0x2E32 || \
+		     (dev)->pci_device == 0x2E42 || \
 		     IS_GM45(dev))
 
 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
@@ -896,9 +900,12 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
  */
 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
 						      IS_I915GM(dev)))
+#define SUPPORTS_DIGITAL_OUTPUTS(dev)	(IS_I9XX(dev) && !IS_IGD(dev))
 #define SUPPORTS_INTEGRATED_HDMI(dev)	(IS_G4X(dev) || IS_IGDNG(dev))
 #define SUPPORTS_INTEGRATED_DP(dev)	(IS_G4X(dev) || IS_IGDNG(dev))
 #define SUPPORTS_EDP(dev)		(IS_IGDNG_M(dev))
+#define SUPPORTS_TV(dev)		(IS_I9XX(dev) && IS_MOBILE(dev) && \
+					!IS_IGDNG(dev) && !IS_IGD(dev))
 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
 /* dsparb controlled by hw only */
 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 80e5ba490dc2..2b7aeeed3990 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1151,27 +1151,21 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 	mutex_lock(&dev->struct_mutex);
 	if (!obj_priv->gtt_space) {
 		ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
-		if (ret) {
-			mutex_unlock(&dev->struct_mutex);
-			return VM_FAULT_SIGBUS;
-		}
-
-		ret = i915_gem_object_set_to_gtt_domain(obj, write);
-		if (ret) {
-			mutex_unlock(&dev->struct_mutex);
-			return VM_FAULT_SIGBUS;
-		}
+		if (ret)
+			goto unlock;
 
 		list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
+
+		ret = i915_gem_object_set_to_gtt_domain(obj, write);
+		if (ret)
+			goto unlock;
 	}
 
 	/* Need a new fence register? */
 	if (obj_priv->tiling_mode != I915_TILING_NONE) {
 		ret = i915_gem_object_get_fence_reg(obj);
-		if (ret) {
-			mutex_unlock(&dev->struct_mutex);
-			return VM_FAULT_SIGBUS;
-		}
+		if (ret)
+			goto unlock;
 	}
 
 	pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
@@ -1179,18 +1173,18 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 
 	/* Finally, remap it using the new GTT offset */
 	ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
-
+unlock:
 	mutex_unlock(&dev->struct_mutex);
 
 	switch (ret) {
+	case 0:
+	case -ERESTARTSYS:
+		return VM_FAULT_NOPAGE;
 	case -ENOMEM:
 	case -EAGAIN:
 		return VM_FAULT_OOM;
-	case -EFAULT:
-	case -EINVAL:
-		return VM_FAULT_SIGBUS;
 	default:
-		return VM_FAULT_NOPAGE;
+		return VM_FAULT_SIGBUS;
 	}
 }
 
@@ -2506,16 +2500,6 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
 	if (obj_priv->pages == NULL)
 		return;
 
-	/* XXX: The 865 in particular appears to be weird in how it handles
-	 * cache flushing.  We haven't figured it out, but the
-	 * clflush+agp_chipset_flush doesn't appear to successfully get the
-	 * data visible to the PGU, while wbinvd + agp_chipset_flush does.
-	 */
-	if (IS_I865G(obj->dev)) {
-		wbinvd();
-		return;
-	}
-
 	drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
 }
 
@@ -3007,6 +2991,16 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
 			return -EINVAL;
 		}
 
+		if (reloc->delta >= target_obj->size) {
+			DRM_ERROR("Relocation beyond target object bounds: "
+				  "obj %p target %d delta %d size %d.\n",
+				  obj, reloc->target_handle,
+				  (int) reloc->delta, (int) target_obj->size);
+			drm_gem_object_unreference(target_obj);
+			i915_gem_object_unpin(obj);
+			return -EINVAL;
+		}
+
 		if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
 		    reloc->read_domains & I915_GEM_DOMAIN_CPU) {
 			DRM_ERROR("reloc with read/write CPU domains: "
@@ -3837,7 +3831,8 @@ void i915_gem_free_object(struct drm_gem_object *obj)
 
 	i915_gem_object_unbind(obj);
 
-	i915_gem_free_mmap_offset(obj);
+	if (obj_priv->mmap_offset)
+		i915_gem_free_mmap_offset(obj);
 
 	kfree(obj_priv->page_cpu_valid);
 	kfree(obj_priv->bit_17);
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index a2d527b22ec4..e774a4a1a503 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -234,7 +234,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 	bool need_disable;
 
-	if (!IS_I9XX(dev)) {
+	if (IS_IGDNG(dev)) {
+		/* On IGDNG whatever DRAM config, GPU always do
+		 * same swizzling setup.
+		 */
+		swizzle_x = I915_BIT_6_SWIZZLE_9_10;
+		swizzle_y = I915_BIT_6_SWIZZLE_9;
+	} else if (!IS_I9XX(dev)) {
 		/* As far as we know, the 865 doesn't have these bit 6
 		 * swizzling issues.
 		 */
@@ -317,13 +323,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 		}
 	}
 
-	/* FIXME: check with memory config on IGDNG */
-	if (IS_IGDNG(dev)) {
-		DRM_ERROR("disable tiling on IGDNG...\n");
-		swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
-		swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
-	}
-
 	dev_priv->mm.bit_6_swizzle_x = swizzle_x;
 	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
 }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7ebc84c2881e..9431a727a985 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -253,10 +253,15 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int ret = IRQ_NONE;
-	u32 de_iir, gt_iir;
+	u32 de_iir, gt_iir, de_ier;
 	u32 new_de_iir, new_gt_iir;
 	struct drm_i915_master_private *master_priv;
 
+	/* disable master interrupt before clearing iir  */
+	de_ier = I915_READ(DEIER);
+	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
+	(void)I915_READ(DEIER);
+
 	de_iir = I915_READ(DEIIR);
 	gt_iir = I915_READ(GTIIR);
 
@@ -287,6 +292,9 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev)
 		gt_iir = new_gt_iir;
 	}
 
+	I915_WRITE(DEIER, de_ier);
+	(void)I915_READ(DEIER);
+
 	return ret;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2955083aa471..9917749afb32 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -915,6 +915,8 @@
 #define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
 #define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
 
+#define BLC_HIST_CTL		0x61260
+
 /* TV port control */
 #define TV_CTL			0x68000
 /** Enables the TV encoder */
@@ -1616,6 +1618,11 @@
 #define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or later */
 #define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
 #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
+#define   PIPE_BPC_MASK 			(7 << 5) /* Ironlake */
+#define   PIPE_8BPC				(0 << 5)
+#define   PIPE_10BPC				(1 << 5)
+#define   PIPE_6BPC				(2 << 5)
+#define   PIPE_12BPC				(3 << 5)
 
 #define DSPARB			0x70030
 #define   DSPARB_CSTART_MASK	(0x7f << 7)
@@ -1733,6 +1740,7 @@
 #define   DISPPLANE_NO_LINE_DOUBLE		0
 #define   DISPPLANE_STEREO_POLARITY_FIRST	0
 #define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
+#define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* IGDNG */
 #define   DISPPLANE_TILED			(1<<10)
 #define DSPAADDR		0x70184
 #define DSPASTRIDE		0x70188
@@ -1865,8 +1873,15 @@
 #define PFA_CTL_1               0x68080
 #define PFB_CTL_1               0x68880
 #define  PF_ENABLE              (1<<31)
+#define  PF_FILTER_MASK		(3<<23)
+#define  PF_FILTER_PROGRAMMED	(0<<23)
+#define  PF_FILTER_MED_3x3	(1<<23)
+#define  PF_FILTER_EDGE_ENHANCE	(2<<23)
+#define  PF_FILTER_EDGE_SOFTEN	(3<<23)
 #define PFA_WIN_SZ		0x68074
 #define PFB_WIN_SZ		0x68874
+#define PFA_WIN_POS		0x68070
+#define PFB_WIN_POS		0x68870
 
 /* legacy palette */
 #define LGC_PALETTE_A           0x4a000
@@ -1913,6 +1928,9 @@
 #define GTIIR   0x44018
 #define GTIER   0x4401c
 
+#define DISP_ARB_CTL	0x45000
+#define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
+
 /* PCH */
 
 /* south display engine interrupt */
@@ -1979,11 +1997,11 @@
 #define  DREF_CPU_SOURCE_OUTPUT_MASK		(3<<13)
 #define  DREF_SSC_SOURCE_DISABLE                (0<<11)
 #define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
-#define  DREF_SSC_SOURCE_MASK			(2<<11)
+#define  DREF_SSC_SOURCE_MASK			(3<<11)
 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
 #define  DREF_NONSPREAD_CK505_ENABLE		(1<<9)
 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
-#define  DREF_NONSPREAD_SOURCE_MASK		(2<<9)
+#define  DREF_NONSPREAD_SOURCE_MASK		(3<<9)
 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
 #define  DREF_SSC4_DOWNSPREAD                   (0<<6)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 1d04e1904ac6..2e4aca658b8b 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -416,6 +416,7 @@ int i915_save_state(struct drm_device *dev)
 	dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
 	dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
 	dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
+	dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
 	if (IS_I965G(dev))
 		dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
 	if (IS_MOBILE(dev) && !IS_I830(dev))
@@ -560,6 +561,7 @@ int i915_restore_state(struct drm_device *dev)
 
 	I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 	I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
+	I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL);
 	I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
 	I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
 	I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index f806fcc54e09..698a0edf0ea9 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -217,6 +217,9 @@ parse_general_features(struct drm_i915_private *dev_priv,
 			if (IS_I85X(dev_priv->dev))
 				dev_priv->lvds_ssc_freq =
 					general->ssc_freq ? 66 : 48;
+			else if (IS_IGDNG(dev_priv->dev))
+				dev_priv->lvds_ssc_freq =
+					general->ssc_freq ? 100 : 120;
 			else
 				dev_priv->lvds_ssc_freq =
 					general->ssc_freq ? 100 : 96;
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 590f81c8f594..046027fa9731 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -151,13 +151,10 @@ static bool intel_igdng_crt_detect_hotplug(struct drm_connector *connector)
 {
 	struct drm_device *dev = connector->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 adpa, temp;
+	u32 adpa;
 	bool ret;
 
-	temp = adpa = I915_READ(PCH_ADPA);
-
-	adpa &= ~ADPA_DAC_ENABLE;
-	I915_WRITE(PCH_ADPA, adpa);
+	adpa = I915_READ(PCH_ADPA);
 
 	adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 
@@ -184,8 +181,6 @@ static bool intel_igdng_crt_detect_hotplug(struct drm_connector *connector)
 	else
 		ret = false;
 
-	/* restore origin register */
-	I915_WRITE(PCH_ADPA, temp);
 	return ret;
 }
 
@@ -239,8 +234,8 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 		} while (time_after(timeout, jiffies));
 	}
 
-	if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) ==
-	    CRT_HOTPLUG_MONITOR_COLOR)
+	if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) !=
+	    CRT_HOTPLUG_MONITOR_NONE)
 		return true;
 
 	return false;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 748ed50c55ca..3ac3b7c49869 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -818,7 +818,7 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 					       refclk, best_clock);
 
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
-		if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
+		if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 		    LVDS_CLKB_POWER_UP)
 			clock.p2 = limit->p2.p2_fast;
 		else
@@ -1008,6 +1008,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 			dspcntr &= ~DISPPLANE_TILED;
 	}
 
+	if (IS_IGDNG(dev))
+		/* must disable */
+		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
+
 	I915_WRITE(dspcntr_reg, dspcntr);
 
 	Start = obj_priv->gtt_offset;
@@ -1154,6 +1158,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 	int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
 	int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
 	int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
+	int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
 	int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
 	int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
 	int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
@@ -1177,6 +1182,15 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 	case DRM_MODE_DPMS_STANDBY:
 	case DRM_MODE_DPMS_SUSPEND:
 		DRM_DEBUG("crtc %d dpms on\n", pipe);
+
+		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+			temp = I915_READ(PCH_LVDS);
+			if ((temp & LVDS_PORT_EN) == 0) {
+				I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
+				POSTING_READ(PCH_LVDS);
+			}
+		}
+
 		if (HAS_eDP) {
 			/* enable eDP PLL */
 			igdng_enable_pll_edp(crtc);
@@ -1205,6 +1219,19 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 			}
 		}
 
+		/* Enable panel fitting for LVDS */
+		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+			temp = I915_READ(pf_ctl_reg);
+			I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
+
+			/* currently full aspect */
+			I915_WRITE(pf_win_pos, 0);
+
+			I915_WRITE(pf_win_size,
+				   (dev_priv->panel_fixed_mode->hdisplay << 16) |
+				   (dev_priv->panel_fixed_mode->vdisplay));
+		}
+
 		/* Enable CPU pipe */
 		temp = I915_READ(pipeconf_reg);
 		if ((temp & PIPEACONF_ENABLE) == 0) {
@@ -1348,8 +1375,6 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 	case DRM_MODE_DPMS_OFF:
 		DRM_DEBUG("crtc %d dpms off\n", pipe);
 
-		i915_disable_vga(dev);
-
 		/* Disable display plane */
 		temp = I915_READ(dspcntr_reg);
 		if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
@@ -1359,6 +1384,8 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 			I915_READ(dspbase_reg);
 		}
 
+		i915_disable_vga(dev);
+
 		/* disable cpu pipe, disable after all planes disabled */
 		temp = I915_READ(pipeconf_reg);
 		if ((temp & PIPEACONF_ENABLE) != 0) {
@@ -1379,9 +1406,15 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 		} else
 			DRM_DEBUG("crtc %d is disabled\n", pipe);
 
-		if (HAS_eDP) {
-			igdng_disable_pll_edp(crtc);
+		udelay(100);
+
+		/* Disable PF */
+		temp = I915_READ(pf_ctl_reg);
+		if ((temp & PF_ENABLE) != 0) {
+			I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
+			I915_READ(pf_ctl_reg);
 		}
+		I915_WRITE(pf_win_size, 0);
 
 		/* disable CPU FDI tx and PCH FDI rx */
 		temp = I915_READ(fdi_tx_reg);
@@ -1407,6 +1440,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 
 		udelay(100);
 
+		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+			temp = I915_READ(PCH_LVDS);
+			I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
+			I915_READ(PCH_LVDS);
+			udelay(100);
+		}
+
 		/* disable PCH transcoder */
 		temp = I915_READ(transconf_reg);
 		if ((temp & TRANS_ENABLE) != 0) {
@@ -1426,6 +1466,8 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 			}
 		}
 
+		udelay(100);
+
 		/* disable PCH DPLL */
 		temp = I915_READ(pch_dpll_reg);
 		if ((temp & DPLL_VCO_ENABLE) != 0) {
@@ -1433,14 +1475,20 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 			I915_READ(pch_dpll_reg);
 		}
 
-		temp = I915_READ(fdi_rx_reg);
-		if ((temp & FDI_RX_PLL_ENABLE) != 0) {
-			temp &= ~FDI_SEL_PCDCLK;
-			temp &= ~FDI_RX_PLL_ENABLE;
-			I915_WRITE(fdi_rx_reg, temp);
-			I915_READ(fdi_rx_reg);
+		if (HAS_eDP) {
+			igdng_disable_pll_edp(crtc);
 		}
 
+		temp = I915_READ(fdi_rx_reg);
+		temp &= ~FDI_SEL_PCDCLK;
+		I915_WRITE(fdi_rx_reg, temp);
+		I915_READ(fdi_rx_reg);
+
+		temp = I915_READ(fdi_rx_reg);
+		temp &= ~FDI_RX_PLL_ENABLE;
+		I915_WRITE(fdi_rx_reg, temp);
+		I915_READ(fdi_rx_reg);
+
 		/* Disable CPU FDI TX PLL */
 		temp = I915_READ(fdi_tx_reg);
 		if ((temp & FDI_TX_PLL_ENABLE) != 0) {
@@ -1449,16 +1497,8 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 			udelay(100);
 		}
 
-		/* Disable PF */
-		temp = I915_READ(pf_ctl_reg);
-		if ((temp & PF_ENABLE) != 0) {
-			I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
-			I915_READ(pf_ctl_reg);
-		}
-		I915_WRITE(pf_win_size, 0);
-
 		/* Wait for the clocks to turn off. */
-		udelay(150);
+		udelay(100);
 		break;
 	}
 }
@@ -1522,6 +1562,7 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
 		intel_update_watermarks(dev);
 		/* Give the overlay scaler a chance to disable if it's on this pipe */
 		//intel_crtc_dpms_video(crtc, FALSE); TODO
+		drm_vblank_off(dev, pipe);
 
 		/* Disable the VGA plane that we never use */
 		i915_disable_vga(dev);
@@ -1746,7 +1787,7 @@ fdi_reduce_ratio(u32 *num, u32 *den)
 #define LINK_N 0x80000
 
 static void
-igdng_compute_m_n(int bytes_per_pixel, int nlanes,
+igdng_compute_m_n(int bits_per_pixel, int nlanes,
 		int pixel_clock, int link_clock,
 		struct fdi_m_n *m_n)
 {
@@ -1756,7 +1797,8 @@ igdng_compute_m_n(int bytes_per_pixel, int nlanes,
 
 	temp = (u64) DATA_N * pixel_clock;
 	temp = div_u64(temp, link_clock);
-	m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
+	m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
+	m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
 	m_n->gmch_n = DATA_N;
 	fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 
@@ -1858,7 +1900,14 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 {
 	long entries_required, wm_size;
 
-	entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
+	/*
+	 * Note: we need to make sure we don't overflow for various clock &
+	 * latency values.
+	 * clocks go from a few thousand to several hundred thousand.
+	 * latency is usually a few thousand
+	 */
+	entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
+		1000;
 	entries_required /= wm->cacheline_size;
 
 	DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
@@ -2371,7 +2420,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 
 	/* FDI link */
 	if (IS_IGDNG(dev)) {
-		int lane, link_bw;
+		int lane, link_bw, bpp;
 		/* eDP doesn't require FDI link, so just set DP M/N
 		   according to current link config */
 		if (is_edp) {
@@ -2390,10 +2439,72 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 			lane = 4;
 			link_bw = 270000;
 		}
-		igdng_compute_m_n(3, lane, target_clock,
+
+		/* determine panel color depth */
+		temp = I915_READ(pipeconf_reg);
+
+		switch (temp & PIPE_BPC_MASK) {
+		case PIPE_8BPC:
+			bpp = 24;
+			break;
+		case PIPE_10BPC:
+			bpp = 30;
+			break;
+		case PIPE_6BPC:
+			bpp = 18;
+			break;
+		case PIPE_12BPC:
+			bpp = 36;
+			break;
+		default:
+			DRM_ERROR("unknown pipe bpc value\n");
+			bpp = 24;
+		}
+
+		igdng_compute_m_n(bpp, lane, target_clock,
 				  link_bw, &m_n);
 	}
 
+	/* Ironlake: try to setup display ref clock before DPLL
+	 * enabling. This is only under driver's control after
+	 * PCH B stepping, previous chipset stepping should be
+	 * ignoring this setting.
+	 */
+	if (IS_IGDNG(dev)) {
+		temp = I915_READ(PCH_DREF_CONTROL);
+		/* Always enable nonspread source */
+		temp &= ~DREF_NONSPREAD_SOURCE_MASK;
+		temp |= DREF_NONSPREAD_SOURCE_ENABLE;
+		I915_WRITE(PCH_DREF_CONTROL, temp);
+		POSTING_READ(PCH_DREF_CONTROL);
+
+		temp &= ~DREF_SSC_SOURCE_MASK;
+		temp |= DREF_SSC_SOURCE_ENABLE;
+		I915_WRITE(PCH_DREF_CONTROL, temp);
+		POSTING_READ(PCH_DREF_CONTROL);
+
+		udelay(200);
+
+		if (is_edp) {
+			if (dev_priv->lvds_use_ssc) {
+				temp |= DREF_SSC1_ENABLE;
+				I915_WRITE(PCH_DREF_CONTROL, temp);
+				POSTING_READ(PCH_DREF_CONTROL);
+
+				udelay(200);
+
+				temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+				temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+				I915_WRITE(PCH_DREF_CONTROL, temp);
+				POSTING_READ(PCH_DREF_CONTROL);
+			} else {
+				temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+				I915_WRITE(PCH_DREF_CONTROL, temp);
+				POSTING_READ(PCH_DREF_CONTROL);
+			}
+		}
+	}
+
 	if (IS_IGD(dev))
 		fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
 	else
@@ -2616,6 +2727,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 
 	intel_wait_for_vblank(dev);
 
+	if (IS_IGDNG(dev)) {
+		/* enable address swizzle for tiling buffer */
+		temp = I915_READ(DISP_ARB_CTL);
+		I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
+	}
+
 	I915_WRITE(dspcntr_reg, dspcntr);
 
 	/* Flush the plane changes */
@@ -3231,7 +3348,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 		if (I915_READ(PCH_DP_D) & DP_DETECTED)
 			intel_dp_init(dev, PCH_DP_D);
 
-	} else if (IS_I9XX(dev)) {
+	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
 		bool found = false;
 
 		if (I915_READ(SDVOB) & SDVO_DETECTED) {
@@ -3258,10 +3375,10 @@ static void intel_setup_outputs(struct drm_device *dev)
 
 		if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
 			intel_dp_init(dev, DP_D);
-	} else
+	} else if (IS_I8XX(dev))
 		intel_dvo_init(dev);
 
-	if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
+	if (SUPPORTS_TV(dev))
 		intel_tv_init(dev);
 
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 1d30802e773e..75a9b83fd7d3 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -114,7 +114,7 @@ static int intelfb_check_var(struct fb_var_screeninfo *var,
 	struct drm_framebuffer *fb = &intel_fb->base;
 	int depth;
 
-	if (var->pixclock == -1 || !var->pixclock)
+	if (var->pixclock != 0)
 		return -EINVAL;
 
 	/* Need to resize the fb object !!! */
@@ -205,7 +205,7 @@ static int intelfb_set_par(struct fb_info *info)
 
 	DRM_DEBUG("%d %d\n", var->xres, var->pixclock);
 
-	if (var->pixclock != -1) {
+	if (var->pixclock != 0) {
 
 		DRM_ERROR("PIXEL CLOCK SET\n");
 		return -EINVAL;
@@ -692,7 +692,7 @@ static int intelfb_multi_fb_probe_crtc(struct drm_device *dev, struct drm_crtc *
 	par->crtc_count = 1;
 
 	if (new_fb) {
-		info->var.pixclock = -1;
+		info->var.pixclock = 0;
 		if (register_framebuffer(info) < 0)
 			return -EINVAL;
 	} else
@@ -846,7 +846,7 @@ static int intelfb_single_fb_probe(struct drm_device *dev)
 	par->crtc_count = crtc_count;
 
 	if (new_fb) {
-		info->var.pixclock = -1;
+		info->var.pixclock = 0;
 		if (register_framebuffer(info) < 0)
 			return -EINVAL;
 	} else
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 8df02ef89261..b7d091ba8c5c 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -305,6 +305,10 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
 		goto out;
 	}
 
+	/* full screen scale for now */
+	if (IS_IGDNG(dev))
+		goto out;
+
 	/* 965+ wants fuzzy fitting */
 	if (IS_I965G(dev))
 		pfit_control |= (intel_crtc->pipe << PFIT_PIPE_SHIFT) |
@@ -332,8 +336,10 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
 	 * to register description and PRM.
 	 * Change the value here to see the borders for debugging
 	 */
-	I915_WRITE(BCLRPAT_A, 0);
-	I915_WRITE(BCLRPAT_B, 0);
+	if (!IS_IGDNG(dev)) {
+		I915_WRITE(BCLRPAT_A, 0);
+		I915_WRITE(BCLRPAT_B, 0);
+	}
 
 	switch (lvds_priv->fitting_mode) {
 	case DRM_MODE_SCALE_NO_SCALE:
@@ -582,7 +588,6 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
 	 * settings.
 	 */
 
-	/* No panel fitting yet, fixme */
 	if (IS_IGDNG(dev))
 		return;
 
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index d3b74ba62b4a..66dc1a54cbf6 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -114,6 +114,9 @@ struct intel_sdvo_priv {
 	/* DDC bus used by this SDVO output */
 	uint8_t ddc_bus;
 
+	/* Mac mini hack -- use the same DDC as the analog connector */
+	struct i2c_adapter *analog_ddc_bus;
+
 	int save_sdvo_mult;
 	u16 save_active_outputs;
 	struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
@@ -1478,6 +1481,36 @@ intel_sdvo_multifunc_encoder(struct intel_output *intel_output)
 	return (caps > 1);
 }
 
+static struct drm_connector *
+intel_find_analog_connector(struct drm_device *dev)
+{
+	struct drm_connector *connector;
+	struct intel_output *intel_output;
+
+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+		intel_output = to_intel_output(connector);
+		if (intel_output->type == INTEL_OUTPUT_ANALOG)
+			return connector;
+	}
+	return NULL;
+}
+
+static int
+intel_analog_is_connected(struct drm_device *dev)
+{
+	struct drm_connector *analog_connector;
+	analog_connector = intel_find_analog_connector(dev);
+
+	if (!analog_connector)
+		return false;
+
+	if (analog_connector->funcs->detect(analog_connector) ==
+			connector_status_disconnected)
+		return false;
+
+	return true;
+}
+
 enum drm_connector_status
 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
 {
@@ -1488,6 +1521,15 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
 
 	edid = drm_get_edid(&intel_output->base,
 			    intel_output->ddc_bus);
+
+	/* when there is no edid and no monitor is connected with VGA
+	 * port, try to use the CRT ddc to read the EDID for DVI-connector
+	 */
+	if (edid == NULL &&
+	    sdvo_priv->analog_ddc_bus &&
+	    !intel_analog_is_connected(intel_output->base.dev))
+		edid = drm_get_edid(&intel_output->base,
+				    sdvo_priv->analog_ddc_bus);
 	if (edid != NULL) {
 		/* Don't report the output as connected if it's a DVI-I
 		 * connector with a non-digital EDID coming out.
@@ -1540,31 +1582,32 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect
 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
 {
 	struct intel_output *intel_output = to_intel_output(connector);
+	struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
+	int num_modes;
 
 	/* set the bus switch and get the modes */
-	intel_ddc_get_modes(intel_output);
+	num_modes = intel_ddc_get_modes(intel_output);
 
-#if 0
-	struct drm_device *dev = encoder->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	/* Mac mini hack.  On this device, I get DDC through the analog, which
-	 * load-detects as disconnected.  I fail to DDC through the SDVO DDC,
-	 * but it does load-detect as connected.  So, just steal the DDC bits
-	 * from analog when we fail at finding it the right way.
+	/*
+	 * Mac mini hack.  On this device, the DVI-I connector shares one DDC
+	 * link between analog and digital outputs. So, if the regular SDVO
+	 * DDC fails, check to see if the analog output is disconnected, in
+	 * which case we'll look there for the digital DDC data.
 	 */
-	crt = xf86_config->output[0];
-	intel_output = crt->driver_private;
-	if (intel_output->type == I830_OUTPUT_ANALOG &&
-	    crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
-		I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
-		edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
-		xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true);
-	}
-	if (edid_mon) {
-		xf86OutputSetEDID(output, edid_mon);
-		modes = xf86OutputGetEDIDModes(output);
+	if (num_modes == 0 &&
+	    sdvo_priv->analog_ddc_bus &&
+	    !intel_analog_is_connected(intel_output->base.dev)) {
+		struct i2c_adapter *digital_ddc_bus;
+
+		/* Switch to the analog ddc bus and try that
+		 */
+		digital_ddc_bus = intel_output->ddc_bus;
+		intel_output->ddc_bus = sdvo_priv->analog_ddc_bus;
+
+		(void) intel_ddc_get_modes(intel_output);
+
+		intel_output->ddc_bus = digital_ddc_bus;
 	}
-#endif
 }
 
 /**
@@ -1748,6 +1791,8 @@ static void intel_sdvo_destroy(struct drm_connector *connector)
 		intel_i2c_destroy(intel_output->i2c_bus);
 	if (intel_output->ddc_bus)
 		intel_i2c_destroy(intel_output->ddc_bus);
+	if (sdvo_priv->analog_ddc_bus)
+		intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
 
 	if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
 		drm_mode_destroy(connector->dev,
@@ -2074,10 +2119,15 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
 	}
 
 	/* setup the DDC bus. */
-	if (output_device == SDVOB)
+	if (output_device == SDVOB) {
 		intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
-	else
+		sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
+						"SDVOB/VGA DDC BUS");
+	} else {
 		intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
+		sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
+						"SDVOC/VGA DDC BUS");
+	}
 
 	if (intel_output->ddc_bus == NULL)
 		goto err_i2c;
@@ -2143,6 +2193,8 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
 	return true;
 
 err_i2c:
+	if (sdvo_priv->analog_ddc_bus != NULL)
+		intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
 	if (intel_output->ddc_bus != NULL)
 		intel_i2c_destroy(intel_output->ddc_bus);
 	if (intel_output->i2c_bus != NULL)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 5b1c9e9fdba0..05f6fe40f2e3 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1212,20 +1212,17 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 		tv_ctl |= TV_TRILEVEL_SYNC;
 	if (tv_mode->pal_burst)
 		tv_ctl |= TV_PAL_BURST;
+
 	scctl1 = 0;
-	/* dda1 implies valid video levels */
-	if (tv_mode->dda1_inc) {
+	if (tv_mode->dda1_inc)
 		scctl1 |= TV_SC_DDA1_EN;
-	}
-
 	if (tv_mode->dda2_inc)
 		scctl1 |= TV_SC_DDA2_EN;
-
 	if (tv_mode->dda3_inc)
 		scctl1 |= TV_SC_DDA3_EN;
-
 	scctl1 |= tv_mode->sc_reset;
-	scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
+	if (video_levels)
+		scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
 	scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;
 
 	scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
diff --git a/drivers/gpu/drm/r128/r128_cce.c b/drivers/gpu/drm/r128/r128_cce.c
index c75fd3564040..ebf9f63e5d49 100644
--- a/drivers/gpu/drm/r128/r128_cce.c
+++ b/drivers/gpu/drm/r128/r128_cce.c
@@ -353,6 +353,11 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init)
 
 	DRM_DEBUG("\n");
 
+	if (dev->dev_private) {
+		DRM_DEBUG("called when already initialized\n");
+		return -EINVAL;
+	}
+
 	dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL);
 	if (dev_priv == NULL)
 		return -ENOMEM;
@@ -649,6 +654,8 @@ int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_pri
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
 		DRM_DEBUG("while CCE running\n");
 		return 0;
@@ -671,6 +678,8 @@ int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	/* Flush any pending CCE commands.  This ensures any outstanding
 	 * commands are exectuted by the engine before we turn it off.
 	 */
@@ -708,10 +717,7 @@ int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_pri
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	if (!dev_priv) {
-		DRM_DEBUG("called before init done\n");
-		return -EINVAL;
-	}
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
 
 	r128_do_cce_reset(dev_priv);
 
@@ -728,6 +734,8 @@ int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	if (dev_priv->cce_running) {
 		r128_do_cce_flush(dev_priv);
 	}
@@ -741,6 +749,8 @@ int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev->dev_private);
+
 	return r128_do_engine_reset(dev);
 }
 
diff --git a/drivers/gpu/drm/r128/r128_drv.h b/drivers/gpu/drm/r128/r128_drv.h
index 797a26c42dab..3c60829d82e9 100644
--- a/drivers/gpu/drm/r128/r128_drv.h
+++ b/drivers/gpu/drm/r128/r128_drv.h
@@ -422,6 +422,14 @@ static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv)
  * Misc helper macros
  */
 
+#define DEV_INIT_TEST_WITH_RETURN(_dev_priv)				\
+do {									\
+	if (!_dev_priv) {						\
+		DRM_ERROR("called with no initialization\n");		\
+		return -EINVAL;						\
+	}								\
+} while (0)
+
 #define RING_SPACE_TEST_WITH_RETURN( dev_priv )				\
 do {									\
 	drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i;		\
diff --git a/drivers/gpu/drm/r128/r128_state.c b/drivers/gpu/drm/r128/r128_state.c
index 026a48c95c8f..af2665cf4718 100644
--- a/drivers/gpu/drm/r128/r128_state.c
+++ b/drivers/gpu/drm/r128/r128_state.c
@@ -1244,14 +1244,18 @@ static void r128_cce_dispatch_stipple(struct drm_device * dev, u32 * stipple)
 static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_r128_sarea_t *sarea_priv;
 	drm_r128_clear_t *clear = data;
 	DRM_DEBUG("\n");
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
+	sarea_priv = dev_priv->sarea_priv;
+
 	if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
 		sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
 
@@ -1312,6 +1316,8 @@ static int r128_cce_flip(struct drm_device *dev, void *data, struct drm_file *fi
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
 	if (!dev_priv->page_flipping)
@@ -1331,6 +1337,8 @@ static int r128_cce_swap(struct drm_device *dev, void *data, struct drm_file *fi
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
 	if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
@@ -1354,10 +1362,7 @@ static int r128_cce_vertex(struct drm_device *dev, void *data, struct drm_file *
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
 
 	DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
 		  DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
@@ -1410,10 +1415,7 @@ static int r128_cce_indices(struct drm_device *dev, void *data, struct drm_file
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
 
 	DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
 		  elts->idx, elts->start, elts->end, elts->discard);
@@ -1476,6 +1478,8 @@ static int r128_cce_blit(struct drm_device *dev, void *data, struct drm_file *fi
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx);
 
 	if (blit->idx < 0 || blit->idx >= dma->buf_count) {
@@ -1501,6 +1505,8 @@ static int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *f
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
 	ret = -EINVAL;
@@ -1531,6 +1537,8 @@ static int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32)))
 		return -EFAULT;
 
@@ -1555,10 +1563,7 @@ static int r128_cce_indirect(struct drm_device *dev, void *data, struct drm_file
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
 
 	DRM_DEBUG("idx=%d s=%d e=%d d=%d\n",
 		  indirect->idx, indirect->start, indirect->end,
@@ -1620,10 +1625,7 @@ static int r128_getparam(struct drm_device *dev, void *data, struct drm_file *fi
 	drm_r128_getparam_t *param = data;
 	int value;
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
 
 	DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
 
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index fcfe5c02d744..7bae834df0ca 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -134,6 +134,14 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
 		}
 	}
 
+	/* HIS X1300 is DVI+VGA, not DVI+DVI */
+	if ((dev->pdev->device == 0x7146) &&
+	    (dev->pdev->subsystem_vendor == 0x17af) &&
+	    (dev->pdev->subsystem_device == 0x2058)) {
+		if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
+			return false;
+	}
+
 	/* Funky macbooks */
 	if ((dev->pdev->device == 0x71C5) &&
 	    (dev->pdev->subsystem_vendor == 0x106b) &&
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index ec383edf5f38..f1d6d3d4519f 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -120,7 +120,7 @@ static int radeonfb_check_var(struct fb_var_screeninfo *var,
 	struct drm_framebuffer *fb = &rfb->base;
 	int depth;
 
-	if (var->pixclock == -1 || !var->pixclock) {
+	if (var->pixclock != 0) {
 		return -EINVAL;
 	}
 	/* Need to resize the fb object !!! */
@@ -234,7 +234,7 @@ static int radeonfb_set_par(struct fb_info *info)
 	int ret;
 	int i;
 
-	if (var->pixclock != -1) {
+	if (var->pixclock != 0) {
 		DRM_ERROR("PIXEL CLCOK SET\n");
 		return -EINVAL;
 	}
@@ -828,7 +828,7 @@ static int radeonfb_single_fb_probe(struct radeon_device *rdev)
 	rfbdev->crtc_count = crtc_count;
 
 	if (new_fb) {
-		info->var.pixclock = -1;
+		info->var.pixclock = 0;
 		if (register_framebuffer(info) < 0)
 			return -EINVAL;
 	} else {
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 0da72f18fd3a..ff9c18d07925 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -291,8 +291,7 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 	uint32_t mask;
 
 	if (radeon_crtc->crtc_id)
-		mask = (RADEON_CRTC2_EN |
-			RADEON_CRTC2_DISP_DIS |
+		mask = (RADEON_CRTC2_DISP_DIS |
 			RADEON_CRTC2_VSYNC_DIS |
 			RADEON_CRTC2_HSYNC_DIS |
 			RADEON_CRTC2_DISP_REQ_EN_B);
@@ -304,7 +303,7 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 	switch (mode) {
 	case DRM_MODE_DPMS_ON:
 		if (radeon_crtc->crtc_id)
-			WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask);
+			WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
 		else {
 			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
 									 RADEON_CRTC_DISP_REQ_EN_B));
@@ -318,7 +317,7 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 	case DRM_MODE_DPMS_OFF:
 		drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 		if (radeon_crtc->crtc_id)
-			WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
+			WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
 		else {
 			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
 										    RADEON_CRTC_DISP_REQ_EN_B));
diff --git a/drivers/hid/hid-apple.c b/drivers/hid/hid-apple.c
index 303ccce05bb3..637867e94c9c 100644
--- a/drivers/hid/hid-apple.c
+++ b/drivers/hid/hid-apple.c
@@ -431,6 +431,13 @@ static const struct hid_device_id apple_devices[] = {
 		.driver_data = APPLE_HAS_FN | APPLE_ISO_KEYBOARD },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING3_JIS),
 		.driver_data = APPLE_HAS_FN | APPLE_RDESC_JIS },
+	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_ANSI),
+		.driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN },
+	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_ISO),
+		.driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN |
+			APPLE_ISO_KEYBOARD },
+	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_JIS),
+		.driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY),
 		.driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY),
diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c
index 5eb10c2ce665..c0537218d9c1 100644
--- a/drivers/hid/hid-core.c
+++ b/drivers/hid/hid-core.c
@@ -1259,6 +1259,9 @@ static const struct hid_device_id hid_blacklist[] = {
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING3_ANSI) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING3_ISO) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING3_JIS) },
+	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_ANSI) },
+	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_ISO) },
+	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_JIS) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_BELKIN, USB_DEVICE_ID_FLIP_KVM) },
@@ -1319,7 +1322,6 @@ static const struct hid_device_id hid_blacklist[] = {
 	{ HID_USB_DEVICE(USB_VENDOR_ID_ZEROPLUS, 0x0005) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_ZEROPLUS, 0x0030) },
 
-	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, 0x030c) },
 	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_PRESENTER_8K_BT) },
 	{ }
 };
diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
index 630101037921..bee718f8714e 100644
--- a/drivers/hid/hid-ids.h
+++ b/drivers/hid/hid-ids.h
@@ -88,6 +88,9 @@
 #define USB_DEVICE_ID_APPLE_WELLSPRING3_ANSI	0x0236
 #define USB_DEVICE_ID_APPLE_WELLSPRING3_ISO	0x0237
 #define USB_DEVICE_ID_APPLE_WELLSPRING3_JIS	0x0238
+#define USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_ANSI  0x0239
+#define USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_ISO   0x023a
+#define USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_JIS   0x023b
 #define USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY	0x030a
 #define USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY	0x030b
 #define USB_DEVICE_ID_APPLE_ATV_IRCONTROL	0x8241
diff --git a/drivers/hwmon/adt7462.c b/drivers/hwmon/adt7462.c
index 1852f27bac51..14f910d3dd9b 100644
--- a/drivers/hwmon/adt7462.c
+++ b/drivers/hwmon/adt7462.c
@@ -97,7 +97,7 @@ I2C_CLIENT_INSMOD_1(adt7462);
 #define		ADT7462_PIN24_SHIFT		6
 #define		ADT7462_PIN26_VOLT_INPUT	0x08
 #define		ADT7462_PIN25_VOLT_INPUT	0x20
-#define		ADT7462_PIN28_SHIFT		6	/* cfg3 */
+#define		ADT7462_PIN28_SHIFT		4	/* cfg3 */
 #define		ADT7462_PIN28_VOLT		0x5
 
 #define ADT7462_REG_ALARM1			0xB8
@@ -182,7 +182,7 @@ I2C_CLIENT_INSMOD_1(adt7462);
  *
  * Some, but not all, of these voltages have low/high limits.
  */
-#define ADT7462_VOLT_COUNT	12
+#define ADT7462_VOLT_COUNT	13
 
 #define ADT7462_VENDOR		0x41
 #define ADT7462_DEVICE		0x62
diff --git a/drivers/hwmon/adt7475.c b/drivers/hwmon/adt7475.c
index d39877a7da63..20579fad4a24 100644
--- a/drivers/hwmon/adt7475.c
+++ b/drivers/hwmon/adt7475.c
@@ -350,8 +350,7 @@ static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
 
 	case FAULT:
 		/* Note - only for remote1 and remote2 */
-		out = data->alarms & (sattr->index ? 0x8000 : 0x4000);
-		out = out ? 0 : 1;
+		out = !!(data->alarms & (sattr->index ? 0x8000 : 0x4000));
 		break;
 
 	default:
@@ -1152,7 +1151,7 @@ static struct adt7475_data *adt7475_update_device(struct device *dev)
 	}
 
 	/* Limits and settings, should never change update every 60 seconds */
-	if (time_after(jiffies, data->limits_updated + HZ * 2) ||
+	if (time_after(jiffies, data->limits_updated + HZ * 60) ||
 	    !data->valid) {
 		data->config5 = adt7475_read(REG_CONFIG5);
 
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index 93c17223b527..2b8f439794b9 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -191,7 +191,7 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
 		if (err) {
 			dev_warn(dev,
 				 "Unable to access MSR 0xEE, for Tjmax, left"
-				 " at default");
+				 " at default\n");
 		} else if (eax & 0x40000000) {
 			tjmax = 85000;
 		}
diff --git a/drivers/hwmon/fschmd.c b/drivers/hwmon/fschmd.c
index ea955edde87e..3e51d54b60f4 100644
--- a/drivers/hwmon/fschmd.c
+++ b/drivers/hwmon/fschmd.c
@@ -767,6 +767,7 @@ leave:
 static int watchdog_open(struct inode *inode, struct file *filp)
 {
 	struct fschmd_data *pos, *data = NULL;
+	int watchdog_is_open;
 
 	/* We get called from drivers/char/misc.c with misc_mtx hold, and we
 	   call misc_register() from fschmd_probe() with watchdog_data_mutex
@@ -781,10 +782,12 @@ static int watchdog_open(struct inode *inode, struct file *filp)
 		}
 	}
 	/* Note we can never not have found data, so we don't check for this */
-	kref_get(&data->kref);
+	watchdog_is_open = test_and_set_bit(0, &data->watchdog_is_open);
+	if (!watchdog_is_open)
+		kref_get(&data->kref);
 	mutex_unlock(&watchdog_data_mutex);
 
-	if (test_and_set_bit(0, &data->watchdog_is_open))
+	if (watchdog_is_open)
 		return -EBUSY;
 
 	/* Start the watchdog */
@@ -819,7 +822,7 @@ static int watchdog_release(struct inode *inode, struct file *filp)
 static ssize_t watchdog_write(struct file *filp, const char __user *buf,
 	size_t count, loff_t *offset)
 {
-	size_t ret;
+	int ret;
 	struct fschmd_data *data = filp->private_data;
 
 	if (count) {
diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c
index 9157247fed8e..231a6a5d6d70 100644
--- a/drivers/hwmon/it87.c
+++ b/drivers/hwmon/it87.c
@@ -1028,12 +1028,11 @@ static int __init it87_find(unsigned short *address,
 		chip_type, *address, sio_data->revision);
 
 	/* Read GPIO config and VID value from LDN 7 (GPIO) */
-	if (chip_type != IT8705F_DEVID) {
+	if (sio_data->type != it87) {
 		int reg;
 
 		superio_select(GPIO);
-		if ((chip_type == it8718) ||
-		    (chip_type == it8720))
+		if (sio_data->type == it8718 || sio_data->type == it8720)
 			sio_data->vid_value = superio_inb(IT87_SIO_VID_REG);
 
 		reg = superio_inb(IT87_SIO_PINX2_REG);
diff --git a/drivers/hwmon/lm78.c b/drivers/hwmon/lm78.c
index a1787fdf5b9f..2348622b533c 100644
--- a/drivers/hwmon/lm78.c
+++ b/drivers/hwmon/lm78.c
@@ -870,17 +870,16 @@ static struct lm78_data *lm78_update_device(struct device *dev)
 static int __init lm78_isa_found(unsigned short address)
 {
 	int val, save, found = 0;
-
-	/* We have to request the region in two parts because some
-	   boards declare base+4 to base+7 as a PNP device */
-	if (!request_region(address, 4, "lm78")) {
-		pr_debug("lm78: Failed to request low part of region\n");
-		return 0;
-	}
-	if (!request_region(address + 4, 4, "lm78")) {
-		pr_debug("lm78: Failed to request high part of region\n");
-		release_region(address, 4);
-		return 0;
+	int port;
+
+	/* Some boards declare base+0 to base+7 as a PNP device, some base+4
+	 * to base+7 and some base+5 to base+6. So we better request each port
+	 * individually for the probing phase. */
+	for (port = address; port < address + LM78_EXTENT; port++) {
+		if (!request_region(port, 1, "lm78")) {
+			pr_debug("lm78: Failed to request port 0x%x\n", port);
+			goto release;
+		}
 	}
 
 #define REALLY_SLOW_IO
@@ -944,8 +943,8 @@ static int __init lm78_isa_found(unsigned short address)
 			val & 0x80 ? "LM79" : "LM78", (int)address);
 
  release:
-	release_region(address + 4, 4);
-	release_region(address, 4);
+	for (port--; port >= address; port--)
+		release_region(port, 1);
 	return found;
 }
 
diff --git a/drivers/hwmon/sht15.c b/drivers/hwmon/sht15.c
index 6290a259456e..e828d17e9318 100644
--- a/drivers/hwmon/sht15.c
+++ b/drivers/hwmon/sht15.c
@@ -304,7 +304,7 @@ static inline int sht15_calc_temp(struct sht15_data *data)
 	int d1 = 0;
 	int i;
 
-	for (i = 1; i < ARRAY_SIZE(temppoints) - 1; i++)
+	for (i = 1; i < ARRAY_SIZE(temppoints); i++)
 		/* Find pointer to interpolate */
 		if (data->supply_uV > temppoints[i - 1].vdd) {
 			d1 = (data->supply_uV/1000 - temppoints[i - 1].vdd)
@@ -331,12 +331,12 @@ static inline int sht15_calc_humid(struct sht15_data *data)
 
 	const int c1 = -4;
 	const int c2 = 40500; /* x 10 ^ -6 */
-	const int c3 = 2800; /* x10 ^ -9 */
+	const int c3 = -2800; /* x10 ^ -9 */
 
 	RHlinear = c1*1000
 		+ c2 * data->val_humid/1000
 		+ (data->val_humid * data->val_humid * c3)/1000000;
-	return (temp - 25000) * (10000 + 800 * data->val_humid)
+	return (temp - 25000) * (10000 + 80 * data->val_humid)
 		/ 1000000 + RHlinear;
 }
 
diff --git a/drivers/hwmon/w83781d.c b/drivers/hwmon/w83781d.c
index 0bdab959b736..3c237004b1ca 100644
--- a/drivers/hwmon/w83781d.c
+++ b/drivers/hwmon/w83781d.c
@@ -1818,17 +1818,17 @@ static int __init
 w83781d_isa_found(unsigned short address)
 {
 	int val, save, found = 0;
-
-	/* We have to request the region in two parts because some
-	   boards declare base+4 to base+7 as a PNP device */
-	if (!request_region(address, 4, "w83781d")) {
-		pr_debug("w83781d: Failed to request low part of region\n");
-		return 0;
-	}
-	if (!request_region(address + 4, 4, "w83781d")) {
-		pr_debug("w83781d: Failed to request high part of region\n");
-		release_region(address, 4);
-		return 0;
+	int port;
+
+	/* Some boards declare base+0 to base+7 as a PNP device, some base+4
+	 * to base+7 and some base+5 to base+6. So we better request each port
+	 * individually for the probing phase. */
+	for (port = address; port < address + W83781D_EXTENT; port++) {
+		if (!request_region(port, 1, "w83781d")) {
+			pr_debug("w83781d: Failed to request port 0x%x\n",
+				 port);
+			goto release;
+		}
 	}
 
 #define REALLY_SLOW_IO
@@ -1902,8 +1902,8 @@ w83781d_isa_found(unsigned short address)
 			val == 0x30 ? "W83782D" : "W83781D", (int)address);
 
  release:
-	release_region(address + 4, 4);
-	release_region(address, 4);
+	for (port--; port >= address; port--)
+		release_region(port, 1);
 	return found;
 }
 
diff --git a/drivers/i2c/busses/i2c-amd756.c b/drivers/i2c/busses/i2c-amd756.c
index f7d6fe9c49ba..8f0b90ef8c76 100644
--- a/drivers/i2c/busses/i2c-amd756.c
+++ b/drivers/i2c/busses/i2c-amd756.c
@@ -364,7 +364,7 @@ static int __devinit amd756_probe(struct pci_dev *pdev,
 	error = acpi_check_region(amd756_ioport, SMB_IOSIZE,
 				  amd756_driver.name);
 	if (error)
-		return error;
+		return -ENODEV;
 
 	if (!request_region(amd756_ioport, SMB_IOSIZE, amd756_driver.name)) {
 		dev_err(&pdev->dev, "SMB region 0x%x already in use!\n",
diff --git a/drivers/i2c/busses/i2c-amd8111.c b/drivers/i2c/busses/i2c-amd8111.c
index a7c59908c457..5b4ad86ca166 100644
--- a/drivers/i2c/busses/i2c-amd8111.c
+++ b/drivers/i2c/busses/i2c-amd8111.c
@@ -376,8 +376,10 @@ static int __devinit amd8111_probe(struct pci_dev *dev,
 	smbus->size = pci_resource_len(dev, 0);
 
 	error = acpi_check_resource_conflict(&dev->resource[0]);
-	if (error)
+	if (error) {
+		error = -ENODEV;
 		goto out_kfree;
+	}
 
 	if (!request_region(smbus->base, smbus->size, amd8111_driver.name)) {
 		error = -EBUSY;
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 9d2c5adf5d4f..55edcfe5b851 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -732,8 +732,10 @@ static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id
 	}
 
 	err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
-	if (err)
+	if (err) {
+		err = -ENODEV;
 		goto exit;
+	}
 
 	err = pci_request_region(dev, SMBBAR, i801_driver.name);
 	if (err) {
diff --git a/drivers/i2c/busses/i2c-isch.c b/drivers/i2c/busses/i2c-isch.c
index 9f6b8e0f8632..dba6eb053e2f 100644
--- a/drivers/i2c/busses/i2c-isch.c
+++ b/drivers/i2c/busses/i2c-isch.c
@@ -281,7 +281,7 @@ static int __devinit sch_probe(struct pci_dev *dev,
 		return -ENODEV;
 	}
 	if (acpi_check_region(sch_smba, SMBIOSIZE, sch_driver.name))
-		return -EBUSY;
+		return -ENODEV;
 	if (!request_region(sch_smba, SMBIOSIZE, sch_driver.name)) {
 		dev_err(&dev->dev, "SMBus region 0x%x already in use!\n",
 			sch_smba);
diff --git a/drivers/i2c/busses/i2c-pca-isa.c b/drivers/i2c/busses/i2c-pca-isa.c
index 0ed68e2ccd22..f7346a9bd95f 100644
--- a/drivers/i2c/busses/i2c-pca-isa.c
+++ b/drivers/i2c/busses/i2c-pca-isa.c
@@ -75,7 +75,7 @@ static int pca_isa_waitforcompletion(void *pd)
 	unsigned long timeout;
 
 	if (irq > -1) {
-		ret = wait_event_interruptible_timeout(pca_wait,
+		ret = wait_event_timeout(pca_wait,
 				pca_isa_readbyte(pd, I2C_PCA_CON)
 				& I2C_PCA_CON_SI, pca_isa_ops.timeout);
 	} else {
@@ -96,7 +96,7 @@ static void pca_isa_resetchip(void *pd)
 }
 
 static irqreturn_t pca_handler(int this_irq, void *dev_id) {
-	wake_up_interruptible(&pca_wait);
+	wake_up(&pca_wait);
 	return IRQ_HANDLED;
 }
 
diff --git a/drivers/i2c/busses/i2c-pca-platform.c b/drivers/i2c/busses/i2c-pca-platform.c
index c4df9d411cd5..5b2213df5ed0 100644
--- a/drivers/i2c/busses/i2c-pca-platform.c
+++ b/drivers/i2c/busses/i2c-pca-platform.c
@@ -84,7 +84,7 @@ static int i2c_pca_pf_waitforcompletion(void *pd)
 	unsigned long timeout;
 
 	if (i2c->irq) {
-		ret = wait_event_interruptible_timeout(i2c->wait,
+		ret = wait_event_timeout(i2c->wait,
 			i2c->algo_data.read_byte(i2c, I2C_PCA_CON)
 			& I2C_PCA_CON_SI, i2c->adap.timeout);
 	} else {
@@ -122,7 +122,7 @@ static irqreturn_t i2c_pca_pf_handler(int this_irq, void *dev_id)
 	if ((i2c->algo_data.read_byte(i2c, I2C_PCA_CON) & I2C_PCA_CON_SI) == 0)
 		return IRQ_NONE;
 
-	wake_up_interruptible(&i2c->wait);
+	wake_up(&i2c->wait);
 
 	return IRQ_HANDLED;
 }
diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c
index 0249a7d762b9..808e49e6ad4e 100644
--- a/drivers/i2c/busses/i2c-piix4.c
+++ b/drivers/i2c/busses/i2c-piix4.c
@@ -168,7 +168,7 @@ static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
 	}
 
 	if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
-		return -EBUSY;
+		return -ENODEV;
 
 	if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 		dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
@@ -259,7 +259,7 @@ static int __devinit piix4_setup_sb800(struct pci_dev *PIIX4_dev,
 
 	piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
 	if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
-		return -EBUSY;
+		return -ENODEV;
 
 	if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 		dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
diff --git a/drivers/i2c/busses/i2c-sis96x.c b/drivers/i2c/busses/i2c-sis96x.c
index 8295885b2fdb..1649963b00dc 100644
--- a/drivers/i2c/busses/i2c-sis96x.c
+++ b/drivers/i2c/busses/i2c-sis96x.c
@@ -280,7 +280,7 @@ static int __devinit sis96x_probe(struct pci_dev *dev,
 
 	retval = acpi_check_resource_conflict(&dev->resource[SIS96x_BAR]);
 	if (retval)
-		return retval;
+		return -ENODEV;
 
 	/* Everything is happy, let's grab the memory and set things up. */
 	if (!request_region(sis96x_smbus_base, SMB_IOSIZE,
diff --git a/drivers/i2c/busses/i2c-tiny-usb.c b/drivers/i2c/busses/i2c-tiny-usb.c
index b1c050ff311d..e29b6d5ba8ef 100644
--- a/drivers/i2c/busses/i2c-tiny-usb.c
+++ b/drivers/i2c/busses/i2c-tiny-usb.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/module.h>
+#include <linux/types.h>
 
 /* include interfaces to usb layer */
 #include <linux/usb.h>
@@ -31,8 +32,8 @@
 #define CMD_I2C_IO_END		(1<<1)
 
 /* i2c bit delay, default is 10us -> 100kHz */
-static int delay = 10;
-module_param(delay, int, 0);
+static unsigned short delay = 10;
+module_param(delay, ushort, 0);
 MODULE_PARM_DESC(delay, "bit delay in microseconds, "
 		 "e.g. 10 for 100kHz (default is 100kHz)");
 
@@ -109,7 +110,7 @@ static int usb_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
 
 static u32 usb_func(struct i2c_adapter *adapter)
 {
-	u32 func;
+	__le32 func;
 
 	/* get functionality from adapter */
 	if (usb_read(adapter, CMD_GET_FUNC, 0, 0, &func, sizeof(func)) !=
@@ -118,7 +119,7 @@ static u32 usb_func(struct i2c_adapter *adapter)
 		return 0;
 	}
 
-	return func;
+	return le32_to_cpu(func);
 }
 
 /* This is the actual algorithm we define */
@@ -216,8 +217,7 @@ static int i2c_tiny_usb_probe(struct usb_interface *interface,
 		 "i2c-tiny-usb at bus %03d device %03d",
 		 dev->usb_dev->bus->busnum, dev->usb_dev->devnum);
 
-	if (usb_write(&dev->adapter, CMD_SET_DELAY,
-		      cpu_to_le16(delay), 0, NULL, 0) != 0) {
+	if (usb_write(&dev->adapter, CMD_SET_DELAY, delay, 0, NULL, 0) != 0) {
 		dev_err(&dev->adapter.dev,
 			"failure setting delay to %dus\n", delay);
 		retval = -EIO;
diff --git a/drivers/i2c/busses/i2c-viapro.c b/drivers/i2c/busses/i2c-viapro.c
index 54d810a4d00f..e4b1543015af 100644
--- a/drivers/i2c/busses/i2c-viapro.c
+++ b/drivers/i2c/busses/i2c-viapro.c
@@ -365,7 +365,7 @@ static int __devinit vt596_probe(struct pci_dev *pdev,
 found:
 	error = acpi_check_region(vt596_smba, 8, vt596_driver.name);
 	if (error)
-		return error;
+		return -ENODEV;
 
 	if (!request_region(vt596_smba, 8, vt596_driver.name)) {
 		dev_err(&pdev->dev, "SMBus region 0x%x already in use!\n",
diff --git a/drivers/i2c/chips/tsl2550.c b/drivers/i2c/chips/tsl2550.c
index b96f3025e588..ec0a7cab6c8b 100644
--- a/drivers/i2c/chips/tsl2550.c
+++ b/drivers/i2c/chips/tsl2550.c
@@ -277,6 +277,7 @@ static DEVICE_ATTR(operating_mode, S_IWUSR | S_IRUGO,
 
 static ssize_t __tsl2550_show_lux(struct i2c_client *client, char *buf)
 {
+	struct tsl2550_data *data = i2c_get_clientdata(client);
 	u8 ch0, ch1;
 	int ret;
 
@@ -296,6 +297,8 @@ static ssize_t __tsl2550_show_lux(struct i2c_client *client, char *buf)
 	ret = tsl2550_calculate_lux(ch0, ch1);
 	if (ret < 0)
 		return ret;
+	if (data->operating_mode == 1)
+		ret *= 5;
 
 	return sprintf(buf, "%d\n", ret);
 }
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 0e45c296d3d2..b67c32c3fa13 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -718,6 +718,7 @@ int i2c_del_adapter(struct i2c_adapter *adap)
 {
 	int res = 0;
 	struct i2c_adapter *found;
+	struct i2c_client *client, *next;
 
 	/* First make sure that this adapter was ever added */
 	mutex_lock(&core_lock);
@@ -737,10 +738,23 @@ int i2c_del_adapter(struct i2c_adapter *adap)
 	if (res)
 		return res;
 
+	/* Remove devices instantiated from sysfs */
+	list_for_each_entry_safe(client, next, &userspace_devices, detected) {
+		if (client->adapter == adap) {
+			dev_dbg(&adap->dev, "Removing %s at 0x%x\n",
+				client->name, client->addr);
+			list_del(&client->detected);
+			i2c_unregister_device(client);
+		}
+	}
+
 	/* Detach any active clients. This can't fail, thus we do not
 	   checking the returned value. */
 	res = device_for_each_child(&adap->dev, NULL, __unregister_client);
 
+	/* device name is gone after device_unregister */
+	dev_dbg(&adap->dev, "adapter [%s] unregistered\n", adap->name);
+
 	/* clean up the sysfs representation */
 	init_completion(&adap->dev_released);
 	device_unregister(&adap->dev);
@@ -753,8 +767,6 @@ int i2c_del_adapter(struct i2c_adapter *adap)
 	idr_remove(&i2c_adapter_idr, adap->nr);
 	mutex_unlock(&core_lock);
 
-	dev_dbg(&adap->dev, "adapter [%s] unregistered\n", adap->name);
-
 	/* Clear the device structure in case this adapter is ever going to be
 	   added again */
 	memset(&adap->dev, 0, sizeof(adap->dev));
diff --git a/drivers/ide/cmd64x.c b/drivers/ide/cmd64x.c
index 680e5975217f..ca0c46f6580a 100644
--- a/drivers/ide/cmd64x.c
+++ b/drivers/ide/cmd64x.c
@@ -379,7 +379,8 @@ static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
 		.enablebits	= {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
 		.port_ops	= &cmd64x_port_ops,
 		.host_flags	= IDE_HFLAG_CLEAR_SIMPLEX |
-				  IDE_HFLAG_ABUSE_PREFETCH,
+				  IDE_HFLAG_ABUSE_PREFETCH |
+				  IDE_HFLAG_SERIALIZE,
 		.pio_mask	= ATA_PIO5,
 		.mwdma_mask	= ATA_MWDMA2,
 		.udma_mask	= 0x00, /* no udma */
@@ -389,7 +390,8 @@ static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
 		.init_chipset	= init_chipset_cmd64x,
 		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 		.port_ops	= &cmd648_port_ops,
-		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH,
+		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH |
+				  IDE_HFLAG_SERIALIZE,
 		.pio_mask	= ATA_PIO5,
 		.mwdma_mask	= ATA_MWDMA2,
 		.udma_mask	= ATA_UDMA2,
diff --git a/drivers/ide/ide-ioctls.c b/drivers/ide/ide-ioctls.c
index e246d3d3fbcc..b05ee089841a 100644
--- a/drivers/ide/ide-ioctls.c
+++ b/drivers/ide/ide-ioctls.c
@@ -162,7 +162,7 @@ static int ide_cmd_ioctl(ide_drive_t *drive, unsigned long arg)
 	if (tf->command == ATA_CMD_SET_FEATURES &&
 	    tf->feature == SETFEATURES_XFER &&
 	    tf->nsect >= XFER_SW_DMA_0) {
-		xfer_rate = ide_find_dma_mode(drive, XFER_UDMA_6);
+		xfer_rate = ide_find_dma_mode(drive, tf->nsect);
 		if (xfer_rate != tf->nsect) {
 			err = -EINVAL;
 			goto abort;
diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c
index 1bb106f6221a..ad33db2eacf1 100644
--- a/drivers/ide/ide-probe.c
+++ b/drivers/ide/ide-probe.c
@@ -1035,15 +1035,6 @@ static void ide_port_init_devices(ide_hwif_t *hwif)
 		if (port_ops && port_ops->init_dev)
 			port_ops->init_dev(drive);
 	}
-
-	ide_port_for_each_dev(i, drive, hwif) {
-		/*
-		 * default to PIO Mode 0 before we figure out
-		 * the most suited mode for the attached device
-		 */
-		if (port_ops && port_ops->set_pio_mode)
-			port_ops->set_pio_mode(drive, 0);
-	}
 }
 
 static void ide_init_port(ide_hwif_t *hwif, unsigned int port,
diff --git a/drivers/ide/sis5513.c b/drivers/ide/sis5513.c
index afca22beaadf..3b88eba04c9c 100644
--- a/drivers/ide/sis5513.c
+++ b/drivers/ide/sis5513.c
@@ -2,7 +2,7 @@
  * Copyright (C) 1999-2000	Andre Hedrick <andre@linux-ide.org>
  * Copyright (C) 2002		Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
  * Copyright (C) 2003		Vojtech Pavlik <vojtech@suse.cz>
- * Copyright (C) 2007		Bartlomiej Zolnierkiewicz
+ * Copyright (C) 2007-2009	Bartlomiej Zolnierkiewicz
  *
  * May be copied or modified under the terms of the GNU General Public License
  *
@@ -281,11 +281,13 @@ static void config_drive_art_rwp(ide_drive_t *drive)
 
 	pci_read_config_byte(dev, 0x4b, &reg4bh);
 
+	rw_prefetch = reg4bh & ~(0x11 << drive->dn);
+
 	if (drive->media == ide_disk)
-		rw_prefetch = 0x11 << drive->dn;
+		rw_prefetch |= 0x11 << drive->dn;
 
-	if ((reg4bh & (0x11 << drive->dn)) != rw_prefetch)
-		pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
+	if (reg4bh != rw_prefetch)
+		pci_write_config_byte(dev, 0x4b, rw_prefetch);
 }
 
 static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
diff --git a/drivers/ide/slc90e66.c b/drivers/ide/slc90e66.c
index 9aec78d3bcff..1ccfb40e7215 100644
--- a/drivers/ide/slc90e66.c
+++ b/drivers/ide/slc90e66.c
@@ -91,8 +91,7 @@ static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
 
 		if (!(reg48 & u_flag))
 			pci_write_config_word(dev, 0x48, reg48|u_flag);
-		/* FIXME: (reg4a & a_speed) ? */
-		if ((reg4a & u_speed) != u_speed) {
+		if ((reg4a & a_speed) != u_speed) {
 			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 			pci_read_config_word(dev, 0x4a, &reg4a);
 			pci_write_config_word(dev, 0x4a, reg4a|u_speed);
diff --git a/drivers/input/keyboard/atkbd.c b/drivers/input/keyboard/atkbd.c
index 6c6a09b1c0fe..abc314f93ff3 100644
--- a/drivers/input/keyboard/atkbd.c
+++ b/drivers/input/keyboard/atkbd.c
@@ -1608,6 +1608,15 @@ static struct dmi_system_id atkbd_dmi_quirk_table[] __initdata = {
 		.driver_data = atkbd_samsung_forced_release_keys,
 	},
 	{
+		.ident = "Samsung R59P/R60P/R61P",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
+			DMI_MATCH(DMI_PRODUCT_NAME, "R59P/R60P/R61P"),
+		},
+		.callback = atkbd_setup_forced_release,
+		.driver_data = atkbd_samsung_forced_release_keys,
+	},
+	{
 		.ident = "Fujitsu Amilo PA 1510",
 		.matches = {
 			DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"),
diff --git a/drivers/input/keyboard/mxc_keyb.c b/drivers/input/keyboard/mxc_keyb.c
index 99dd7cf51cb5..033713cbdfdf 100644
--- a/drivers/input/keyboard/mxc_keyb.c
+++ b/drivers/input/keyboard/mxc_keyb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -58,12 +58,168 @@
 #include <linux/clk.h>
 #include <asm/mach/keypad.h>
 
+/*!
+ * Keypad Module Name
+ */
+#define MOD_NAME  "mxckpd"
+
+/*!
+ * XLATE mode selection
+ */
+#define KEYPAD_XLATE        0
+
+/*!
+ * RAW mode selection
+ */
+#define KEYPAD_RAW          1
+
+/*!
+ * Maximum number of keys.
+ */
+#define MAXROW			8
+#define MAXCOL			8
+#define MXC_MAXKEY		(MAXROW * MAXCOL)
+
+/*!
+ * This define indicates break scancode for every key release. A constant
+ * of 128 is added to the key press scancode.
+ */
+#define  MXC_KEYRELEASE   128
+
+/*
+ * _reg_KPP_KPCR   _reg_KPP_KPSR _reg_KPP_KDDR _reg_KPP_KPDR
+ *  The offset of Keypad Control Register Address
+ */
+#define KPCR    0x00
+
+/*
+ * The offset of Keypad Status Register Address
+ */
+#define KPSR    0x02
+
+/*
+ * The offset of Keypad Data Direction Address
+ */
+#define KDDR   0x04
+
+/*
+ * The offset of Keypad Data Register
+ */
+#define KPDR    0x06
+
+/*
+ * Key Press Interrupt Status bit
+ */
+#define KBD_STAT_KPKD        0x01
+
+/*
+ * Key Release Interrupt Status bit
+ */
+#define KBD_STAT_KPKR        0x02
+
+/*
+ * Key Depress Synchronizer Chain Status bit
+ */
+#define KBD_STAT_KDSC        0x04
+
+/*
+ * Key Release Synchronizer Status bit
+ */
+#define KBD_STAT_KRSS        0x08
+
+/*
+ * Key Depress Interrupt Enable Status bit
+ */
+#define KBD_STAT_KDIE        0x100
+
 /*
- * Module header file
+ * Key Release Interrupt Enable
  */
-#include "mxc_keyb.h"
+#define KBD_STAT_KRIE        0x200
+
+/*
+ * Keypad Clock Enable
+ */
+#define KBD_STAT_KPPEN       0x400
+
+/*!
+ * Buffer size of keypad queue. Should be a power of 2.
+ */
+#define KPP_BUF_SIZE    128
+
+/*!
+ * Test whether bit is set for integer c
+ */
+#define TEST_BIT(c, n) ((c) & (0x1 << (n)))
+
+/*!
+ * Set nth bit in the integer c
+ */
+#define BITSET(c, n)   ((c) | (1 << (n)))
+
+/*!
+ * Reset nth bit in the integer c
+ */
+#define BITRESET(c, n) ((c) & ~(1 << (n)))
+
+/*!
+ * This enum represents the keypad state machine to maintain debounce logic
+ * for key press/release.
+ */
+enum KeyState {
+
+	/*!
+	 * Key press state.
+	 */
+	KStateUp,
+
+	/*!
+	 * Key press debounce state.
+	 */
+	KStateFirstDown,
+
+	/*!
+	 * Key release state.
+	 */
+	KStateDown,
+
+	/*!
+	 * Key release debounce state.
+	 */
+	KStateFirstUp
+};
 
 /*!
+ * Keypad Private Data Structure
+ */
+struct keypad_priv {
+
+	/*!
+	 * Keypad state machine.
+	 */
+	enum KeyState iKeyState;
+
+	/*!
+	 * Number of rows configured in the keypad matrix
+	 */
+	unsigned long kpp_rows;
+
+	/*!
+	 * Number of Columns configured in the keypad matrix
+	 */
+	unsigned long kpp_cols;
+
+	/*!
+	 * Timer used for Keypad polling.
+	 */
+	struct timer_list poll_timer;
+
+	/*!
+	 * The base address
+	 */
+	void __iomem *base;
+};
+/*!
  * This structure holds the keypad private data structure.
  */
 static struct keypad_priv kpp_dev;
@@ -269,26 +425,26 @@ static int mxc_kpp_scan_matrix(void)
 
 	for (col = 0; col < kpp_dev.kpp_cols; col++) {	/* Col */
 		/* 2. Write 1.s to KPDR[15:8] setting column data to 1.s */
-		reg_val = __raw_readw(KPDR);
+		reg_val = __raw_readw(kpp_dev.base + KPDR);
 		reg_val |= 0xff00;
-		__raw_writew(reg_val, KPDR);
+		__raw_writew(reg_val, kpp_dev.base + KPDR);
 
 		/*
 		 * 3. Configure columns as totem pole outputs(for quick
 		 * discharging of keypad capacitance)
 		 */
-		reg_val = __raw_readw(KPCR);
+		reg_val = __raw_readw(kpp_dev.base + KPCR);
 		reg_val &= 0x00ff;
-		__raw_writew(reg_val, KPCR);
+		__raw_writew(reg_val, kpp_dev.base + KPCR);
 
 		udelay(2);
 
 		/*
 		 * 4. Configure columns as open-drain
 		 */
-		reg_val = __raw_readw(KPCR);
+		reg_val = __raw_readw(kpp_dev.base + KPCR);
 		reg_val |= ((1 << kpp_dev.kpp_cols) - 1) << 8;
-		__raw_writew(reg_val, KPCR);
+		__raw_writew(reg_val, kpp_dev.base + KPCR);
 
 		/*
 		 * 5. Write a single column to 0, others to 1.
@@ -298,9 +454,9 @@ static int mxc_kpp_scan_matrix(void)
 		 */
 
 		/* Col bit starts at 8th bit in KPDR */
-		reg_val = __raw_readw(KPDR);
+		reg_val = __raw_readw(kpp_dev.base + KPDR);
 		reg_val &= ~(1 << (8 + col));
-		__raw_writew(reg_val, KPDR);
+		__raw_writew(reg_val, kpp_dev.base + KPDR);
 
 		/* Delay added to avoid propagating the 0 from column to row
 		 * when scanning. */
@@ -308,7 +464,7 @@ static int mxc_kpp_scan_matrix(void)
 		udelay(5);
 
 		/* Read row input */
-		reg_val = __raw_readw(KPDR);
+		reg_val = __raw_readw(kpp_dev.base + KPDR);
 		for (row = 0; row < kpp_dev.kpp_rows; row++) {	/* sample row */
 			if (TEST_BIT(reg_val, row) == 0) {
 				cur_rcmap[row] = BITSET(cur_rcmap[row], col);
@@ -324,12 +480,12 @@ static int mxc_kpp_scan_matrix(void)
 	 * clear the KPKD synchronizer chain by writing "1" to KDSC register
 	 */
 	reg_val = 0x00;
-	__raw_writew(reg_val, KPDR);
-	reg_val = __raw_readw(KPDR);
-	reg_val = __raw_readw(KPSR);
+	__raw_writew(reg_val, kpp_dev.base + KPDR);
+	reg_val = __raw_readw(kpp_dev.base + KPDR);
+	reg_val = __raw_readw(kpp_dev.base + KPSR);
 	reg_val |= KBD_STAT_KPKD | KBD_STAT_KPKR | KBD_STAT_KRSS |
 	    KBD_STAT_KDSC;
-	__raw_writew(reg_val, KPSR);
+	__raw_writew(reg_val, kpp_dev.base + KPSR);
 
 	/* Check key press status change */
 
@@ -558,14 +714,14 @@ static void mxc_kpp_handle_timer(unsigned long data)
 		 * Stop scanning and wait for interrupt.
 		 * Enable press interrupt and disable release interrupt.
 		 */
-		__raw_writew(0x00FF, KPDR);
-		reg_val = __raw_readw(KPSR);
+		__raw_writew(0x00FF, kpp_dev.base + KPDR);
+		reg_val = __raw_readw(kpp_dev.base + KPSR);
 		reg_val |= (KBD_STAT_KPKR | KBD_STAT_KPKD);
 		reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC;
-		__raw_writew(reg_val, KPSR);
+		__raw_writew(reg_val, kpp_dev.base + KPSR);
 		reg_val |= KBD_STAT_KDIE;
 		reg_val &= ~KBD_STAT_KRIE;
-		__raw_writew(reg_val, KPSR);
+		__raw_writew(reg_val, kpp_dev.base + KPSR);
 
 		/*
 		 * No more keys pressed... make sure unwanted key codes are
@@ -613,7 +769,7 @@ static irqreturn_t mxc_kpp_interrupt(int irq, void *dev_id)
 
 	/* Delete the polling timer */
 	del_timer(&kpp_dev.poll_timer);
-	reg_val = __raw_readw(KPSR);
+	reg_val = __raw_readw(kpp_dev.base + KPSR);
 
 	/* Check if it is key press interrupt */
 	if (reg_val & KBD_STAT_KPKD) {
@@ -621,7 +777,7 @@ static irqreturn_t mxc_kpp_interrupt(int irq, void *dev_id)
 		 * Disable key press(KDIE status bit) interrupt
 		 */
 		reg_val &= ~KBD_STAT_KDIE;
-		__raw_writew(reg_val, KPSR);
+		__raw_writew(reg_val, kpp_dev.base + KPSR);
 	} else {
 		/* spurious interrupt */
 		return IRQ_RETVAL(0);
@@ -767,6 +923,7 @@ static int mxc_kpp_probe(struct platform_device *pdev)
 	int i, irq;
 	int retval;
 	unsigned int reg_val;
+	struct resource *res;
 
 	keypad = (struct keypad_data *)pdev->dev.platform_data;
 
@@ -774,6 +931,14 @@ static int mxc_kpp_probe(struct platform_device *pdev)
 	kpp_dev.kpp_rows = keypad->rowmax;
 	key_pad_enabled = 0;
 
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	kpp_dev.base = ioremap(res->start, res->end - res->start + 1);
+	if (!kpp_dev.base)
+		return -ENOMEM;
+
 	irq = platform_get_irq(pdev, 0);
 	keypad->irq = irq;
 
@@ -793,30 +958,30 @@ static int mxc_kpp_probe(struct platform_device *pdev)
 	 * LSB nibble in KPP is for 8 rows
 	 * MSB nibble in KPP is for 8 cols
 	 */
-	reg_val = __raw_readw(KPCR);
+	reg_val = __raw_readw(kpp_dev.base + KPCR);
 	reg_val |= (1 << keypad->rowmax) - 1;	/* LSB */
 	reg_val |= ((1 << keypad->colmax) - 1) << 8;	/* MSB */
-	__raw_writew(reg_val, KPCR);
+	__raw_writew(reg_val, kpp_dev.base + KPCR);
 
 	/* Write 0's to KPDR[15:8] */
-	reg_val = __raw_readw(KPDR);
+	reg_val = __raw_readw(kpp_dev.base + KPDR);
 	reg_val &= 0x00ff;
-	__raw_writew(reg_val, KPDR);
+	__raw_writew(reg_val, kpp_dev.base + KPDR);
 
 	/* Configure columns as output, rows as input (KDDR[15:0]) */
-	reg_val = __raw_readw(KDDR);
+	reg_val = __raw_readw(kpp_dev.base + KDDR);
 	reg_val |= 0xff00;
 	reg_val &= 0xff00;
-	__raw_writew(reg_val, KDDR);
+	__raw_writew(reg_val, kpp_dev.base + KDDR);
 
-	reg_val = __raw_readw(KPSR);
+	reg_val = __raw_readw(kpp_dev.base + KPSR);
 	reg_val &= ~(KBD_STAT_KPKR | KBD_STAT_KPKD);
 	reg_val |= KBD_STAT_KPKD;
 	reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC;
-	__raw_writew(reg_val, KPSR);
+	__raw_writew(reg_val, kpp_dev.base + KPSR);
 	reg_val |= KBD_STAT_KDIE;
 	reg_val &= ~KBD_STAT_KRIE;
-	__raw_writew(reg_val, KPSR);
+	__raw_writew(reg_val, kpp_dev.base + KPSR);
 
 	has_leaning_key = keypad->learning;
 	mxckpd_keycodes = keypad->matrix;
@@ -950,16 +1115,16 @@ static int mxc_kpp_remove(struct platform_device *pdev)
 	 * Set KDIE control bit, clear KRIE control bit (avoid false release
 	 * events. Disable the keypad GPIO pins.
 	 */
-	__raw_writew(0x00, KPCR);
-	__raw_writew(0x00, KPDR);
-	__raw_writew(0x00, KDDR);
+	__raw_writew(0x00, kpp_dev.base + KPCR);
+	__raw_writew(0x00, kpp_dev.base + KPDR);
+	__raw_writew(0x00, kpp_dev.base + KDDR);
 
-	reg_val = __raw_readw(KPSR);
+	reg_val = __raw_readw(kpp_dev.base + KPSR);
 	reg_val |= KBD_STAT_KPKD;
 	reg_val &= ~KBD_STAT_KRSS;
 	reg_val |= KBD_STAT_KDIE;
 	reg_val &= ~KBD_STAT_KRIE;
-	__raw_writew(reg_val, KPSR);
+	__raw_writew(reg_val, kpp_dev.base + KPSR);
 
 	gpio_keypad_inactive();
 	clk_disable(kpp_clk);
diff --git a/drivers/input/misc/mma7455l.c b/drivers/input/misc/mma7455l.c
index 1cee2d1add04..48dca60d2cfe 100644
--- a/drivers/input/misc/mma7455l.c
+++ b/drivers/input/misc/mma7455l.c
@@ -583,6 +583,8 @@ static int __devexit mma7455l_remove(struct i2c_client *client)
 {
 	struct mma7455l_info *mma = dev_get_drvdata(&client->dev);
 
+	free_irq(client->irq, mma);
+
 	sysfs_remove_group(&client->dev.kobj, &mma7455l_attr_group);
 	input_unregister_device(mma->input_dev);
 	dev_set_drvdata(&client->dev, NULL);
diff --git a/drivers/input/mouse/alps.c b/drivers/input/mouse/alps.c
index 5547e2429fbe..b172bef75910 100644
--- a/drivers/input/mouse/alps.c
+++ b/drivers/input/mouse/alps.c
@@ -5,6 +5,7 @@
  * Copyright (c) 2003-2005 Peter Osterlund <petero2@telia.com>
  * Copyright (c) 2004 Dmitry Torokhov <dtor@mail.ru>
  * Copyright (c) 2005 Vojtech Pavlik <vojtech@suse.cz>
+ * Copyright (c) 2009 Sebastian Kapfer <sebastian_kapfer@gmx.net>
  *
  * ALPS detection, tap switching and status querying info is taken from
  * tpconfig utility (by C. Scott Ananian and Bruce Kall).
@@ -35,6 +36,8 @@
 #define ALPS_OLDPROTO	0x10
 #define ALPS_PASS	0x20
 #define ALPS_FW_BK_2	0x40
+#define ALPS_PS2_INTERLEAVED	0x80	/* 3-byte PS/2 packet interleaved with
+					   6-byte ALPS packet */
 
 static const struct alps_model_info alps_model_data[] = {
 	{ { 0x32, 0x02, 0x14 },	0xf8, 0xf8, ALPS_PASS | ALPS_DUALPOINT }, /* Toshiba Salellite Pro M10 */
@@ -55,7 +58,9 @@ static const struct alps_model_info alps_model_data[] = {
 	{ { 0x20, 0x02, 0x0e },	0xf8, 0xf8, ALPS_PASS | ALPS_DUALPOINT }, /* XXX */
 	{ { 0x22, 0x02, 0x0a },	0xf8, 0xf8, ALPS_PASS | ALPS_DUALPOINT },
 	{ { 0x22, 0x02, 0x14 }, 0xff, 0xff, ALPS_PASS | ALPS_DUALPOINT }, /* Dell Latitude D600 */
-	{ { 0x62, 0x02, 0x14 }, 0xcf, 0xcf, ALPS_PASS | ALPS_DUALPOINT }, /* Dell Latitude E6500 */
+	/* Dell Latitude E5500, E6400, E6500, Precision M4400 */
+	{ { 0x62, 0x02, 0x14 }, 0xcf, 0xcf,
+		ALPS_PASS | ALPS_DUALPOINT | ALPS_PS2_INTERLEAVED },
 	{ { 0x73, 0x02, 0x50 }, 0xcf, 0xcf, ALPS_FW_BK_1 },		  /* Dell Vostro 1400 */
 };
 
@@ -66,20 +71,88 @@ static const struct alps_model_info alps_model_data[] = {
  */
 
 /*
- * ALPS abolute Mode - new format
+ * PS/2 packet format
+ *
+ * byte 0:  0    0 YSGN XSGN    1    M    R    L
+ * byte 1: X7   X6   X5   X4   X3   X2   X1   X0
+ * byte 2: Y7   Y6   Y5   Y4   Y3   Y2   Y1   Y0
+ *
+ * Note that the device never signals overflow condition.
+ *
+ * ALPS absolute Mode - new format
  *
  * byte 0:  1    ?    ?    ?    1    ?    ?    ?
  * byte 1:  0   x6   x5   x4   x3   x2   x1   x0
- * byte 2:  0   x10  x9   x8   x7    ?  fin  ges
+ * byte 2:  0  x10   x9   x8   x7    ?  fin  ges
  * byte 3:  0   y9   y8   y7    1    M    R    L
  * byte 4:  0   y6   y5   y4   y3   y2   y1   y0
  * byte 5:  0   z6   z5   z4   z3   z2   z1   z0
  *
+ * Dualpoint device -- interleaved packet format
+ *
+ * byte 0:    1    1    0    0    1    1    1    1
+ * byte 1:    0   x6   x5   x4   x3   x2   x1   x0
+ * byte 2:    0  x10   x9   x8   x7    0  fin  ges
+ * byte 3:    0    0 YSGN XSGN    1    1    1    1
+ * byte 4:   X7   X6   X5   X4   X3   X2   X1   X0
+ * byte 5:   Y7   Y6   Y5   Y4   Y3   Y2   Y1   Y0
+ * byte 6:    0   y9   y8   y7    1    m    r    l
+ * byte 7:    0   y6   y5   y4   y3   y2   y1   y0
+ * byte 8:    0   z6   z5   z4   z3   z2   z1   z0
+ *
+ * CAPITALS = stick, miniscules = touchpad
+ *
  * ?'s can have different meanings on different models,
  * such as wheel rotation, extra buttons, stick buttons
  * on a dualpoint, etc.
  */
 
+static bool alps_is_valid_first_byte(const struct alps_model_info *model,
+				     unsigned char data)
+{
+	return (data & model->mask0) == model->byte0;
+}
+
+static void alps_report_buttons(struct psmouse *psmouse,
+				struct input_dev *dev1, struct input_dev *dev2,
+				int left, int right, int middle)
+{
+	struct alps_data *priv = psmouse->private;
+	const struct alps_model_info *model = priv->i;
+
+	if (model->flags & ALPS_PS2_INTERLEAVED) {
+		struct input_dev *dev;
+
+		/*
+		 * If shared button has already been reported on the
+		 * other device (dev2) then this event should be also
+		 * sent through that device.
+		 */
+		dev = test_bit(BTN_LEFT, dev2->key) ? dev2 : dev1;
+		input_report_key(dev, BTN_LEFT, left);
+
+		dev = test_bit(BTN_RIGHT, dev2->key) ? dev2 : dev1;
+		input_report_key(dev, BTN_RIGHT, right);
+
+		dev = test_bit(BTN_MIDDLE, dev2->key) ? dev2 : dev1;
+		input_report_key(dev, BTN_MIDDLE, middle);
+
+		/*
+		 * Sync the _other_ device now, we'll do the first
+		 * device later once we report the rest of the events.
+		 */
+		input_sync(dev2);
+	} else {
+		/*
+		 * For devices with non-interleaved packets we know what
+		 * device buttons belong to so we can simply report them.
+		 */
+		input_report_key(dev1, BTN_LEFT, left);
+		input_report_key(dev1, BTN_RIGHT, right);
+		input_report_key(dev1, BTN_MIDDLE, middle);
+	}
+}
+
 static void alps_process_packet(struct psmouse *psmouse)
 {
 	struct alps_data *priv = psmouse->private;
@@ -89,18 +162,6 @@ static void alps_process_packet(struct psmouse *psmouse)
 	int x, y, z, ges, fin, left, right, middle;
 	int back = 0, forward = 0;
 
-	if ((packet[0] & 0xc8) == 0x08) {   /* 3-byte PS/2 packet */
-		input_report_key(dev2, BTN_LEFT,   packet[0] & 1);
-		input_report_key(dev2, BTN_RIGHT,  packet[0] & 2);
-		input_report_key(dev2, BTN_MIDDLE, packet[0] & 4);
-		input_report_rel(dev2, REL_X,
-			packet[1] ? packet[1] - ((packet[0] << 4) & 0x100) : 0);
-		input_report_rel(dev2, REL_Y,
-			packet[2] ? ((packet[0] << 3) & 0x100) - packet[2] : 0);
-		input_sync(dev2);
-		return;
-	}
-
 	if (priv->i->flags & ALPS_OLDPROTO) {
 		left = packet[2] & 0x10;
 		right = packet[2] & 0x08;
@@ -136,18 +197,13 @@ static void alps_process_packet(struct psmouse *psmouse)
 		input_report_rel(dev2, REL_X,  (x > 383 ? (x - 768) : x));
 		input_report_rel(dev2, REL_Y, -(y > 255 ? (y - 512) : y));
 
-		input_report_key(dev2, BTN_LEFT, left);
-		input_report_key(dev2, BTN_RIGHT, right);
-		input_report_key(dev2, BTN_MIDDLE, middle);
+		alps_report_buttons(psmouse, dev2, dev, left, right, middle);
 
-		input_sync(dev);
 		input_sync(dev2);
 		return;
 	}
 
-	input_report_key(dev, BTN_LEFT, left);
-	input_report_key(dev, BTN_RIGHT, right);
-	input_report_key(dev, BTN_MIDDLE, middle);
+	alps_report_buttons(psmouse, dev, dev2, left, right, middle);
 
 	/* Convert hardware tap to a reasonable Z value */
 	if (ges && !fin) z = 40;
@@ -188,25 +244,168 @@ static void alps_process_packet(struct psmouse *psmouse)
 	input_sync(dev);
 }
 
+static void alps_report_bare_ps2_packet(struct psmouse *psmouse,
+					unsigned char packet[],
+					bool report_buttons)
+{
+	struct alps_data *priv = psmouse->private;
+	struct input_dev *dev2 = priv->dev2;
+
+	if (report_buttons)
+		alps_report_buttons(psmouse, dev2, psmouse->dev,
+				packet[0] & 1, packet[0] & 2, packet[0] & 4);
+
+	input_report_rel(dev2, REL_X,
+		packet[1] ? packet[1] - ((packet[0] << 4) & 0x100) : 0);
+	input_report_rel(dev2, REL_Y,
+		packet[2] ? ((packet[0] << 3) & 0x100) - packet[2] : 0);
+
+	input_sync(dev2);
+}
+
+static psmouse_ret_t alps_handle_interleaved_ps2(struct psmouse *psmouse)
+{
+	struct alps_data *priv = psmouse->private;
+
+	if (psmouse->pktcnt < 6)
+		return PSMOUSE_GOOD_DATA;
+
+	if (psmouse->pktcnt == 6) {
+		/*
+		 * Start a timer to flush the packet if it ends up last
+		 * 6-byte packet in the stream. Timer needs to fire
+		 * psmouse core times out itself. 20 ms should be enough
+		 * to decide if we are getting more data or not.
+		 */
+		mod_timer(&priv->timer, jiffies + msecs_to_jiffies(20));
+		return PSMOUSE_GOOD_DATA;
+	}
+
+	del_timer(&priv->timer);
+
+	if (psmouse->packet[6] & 0x80) {
+
+		/*
+		 * Highest bit is set - that means we either had
+		 * complete ALPS packet and this is start of the
+		 * next packet or we got garbage.
+		 */
+
+		if (((psmouse->packet[3] |
+		      psmouse->packet[4] |
+		      psmouse->packet[5]) & 0x80) ||
+		    (!alps_is_valid_first_byte(priv->i, psmouse->packet[6]))) {
+			dbg("refusing packet %x %x %x %x "
+			    "(suspected interleaved ps/2)\n",
+			    psmouse->packet[3], psmouse->packet[4],
+			    psmouse->packet[5], psmouse->packet[6]);
+			return PSMOUSE_BAD_DATA;
+		}
+
+		alps_process_packet(psmouse);
+
+		/* Continue with the next packet */
+		psmouse->packet[0] = psmouse->packet[6];
+		psmouse->pktcnt = 1;
+
+	} else {
+
+		/*
+		 * High bit is 0 - that means that we indeed got a PS/2
+		 * packet in the middle of ALPS packet.
+		 *
+		 * There is also possibility that we got 6-byte ALPS
+		 * packet followed  by 3-byte packet from trackpoint. We
+		 * can not distinguish between these 2 scenarios but
+		 * becase the latter is unlikely to happen in course of
+		 * normal operation (user would need to press all
+		 * buttons on the pad and start moving trackpoint
+		 * without touching the pad surface) we assume former.
+		 * Even if we are wrong the wost thing that would happen
+		 * the cursor would jump but we should not get protocol
+		 * desynchronization.
+		 */
+
+		alps_report_bare_ps2_packet(psmouse, &psmouse->packet[3],
+					    false);
+
+		/*
+		 * Continue with the standard ALPS protocol handling,
+		 * but make sure we won't process it as an interleaved
+		 * packet again, which may happen if all buttons are
+		 * pressed. To avoid this let's reset the 4th bit which
+		 * is normally 1.
+		 */
+		psmouse->packet[3] = psmouse->packet[6] & 0xf7;
+		psmouse->pktcnt = 4;
+	}
+
+	return PSMOUSE_GOOD_DATA;
+}
+
+static void alps_flush_packet(unsigned long data)
+{
+	struct psmouse *psmouse = (struct psmouse *)data;
+
+	serio_pause_rx(psmouse->ps2dev.serio);
+
+	if (psmouse->pktcnt == 6) {
+
+		/*
+		 * We did not any more data in reasonable amount of time.
+		 * Validate the last 3 bytes and process as a standard
+		 * ALPS packet.
+		 */
+		if ((psmouse->packet[3] |
+		     psmouse->packet[4] |
+		     psmouse->packet[5]) & 0x80) {
+			dbg("refusing packet %x %x %x "
+			    "(suspected interleaved ps/2)\n",
+			    psmouse->packet[3], psmouse->packet[4],
+			    psmouse->packet[5]);
+		} else {
+			alps_process_packet(psmouse);
+		}
+		psmouse->pktcnt = 0;
+	}
+
+	serio_continue_rx(psmouse->ps2dev.serio);
+}
+
 static psmouse_ret_t alps_process_byte(struct psmouse *psmouse)
 {
 	struct alps_data *priv = psmouse->private;
+	const struct alps_model_info *model = priv->i;
 
 	if ((psmouse->packet[0] & 0xc8) == 0x08) { /* PS/2 packet */
 		if (psmouse->pktcnt == 3) {
-			alps_process_packet(psmouse);
+			alps_report_bare_ps2_packet(psmouse, psmouse->packet,
+						    true);
 			return PSMOUSE_FULL_PACKET;
 		}
 		return PSMOUSE_GOOD_DATA;
 	}
 
-	if ((psmouse->packet[0] & priv->i->mask0) != priv->i->byte0)
+	/* Check for PS/2 packet stuffed in the middle of ALPS packet. */
+
+	if ((model->flags & ALPS_PS2_INTERLEAVED) &&
+	    psmouse->pktcnt >= 4 && (psmouse->packet[3] & 0x0f) == 0x0f) {
+		return alps_handle_interleaved_ps2(psmouse);
+	}
+
+	if (!alps_is_valid_first_byte(model, psmouse->packet[0])) {
+		dbg("refusing packet[0] = %x (mask0 = %x, byte0 = %x)\n",
+		    psmouse->packet[0], model->mask0, model->byte0);
 		return PSMOUSE_BAD_DATA;
+	}
 
 	/* Bytes 2 - 6 should have 0 in the highest bit */
 	if (psmouse->pktcnt >= 2 && psmouse->pktcnt <= 6 &&
-	    (psmouse->packet[psmouse->pktcnt - 1] & 0x80))
+	    (psmouse->packet[psmouse->pktcnt - 1] & 0x80)) {
+		dbg("refusing packet[%i] = %x\n",
+		    psmouse->pktcnt - 1, psmouse->packet[psmouse->pktcnt - 1]);
 		return PSMOUSE_BAD_DATA;
+	}
 
 	if (psmouse->pktcnt == 6) {
 		alps_process_packet(psmouse);
@@ -441,6 +640,7 @@ static void alps_disconnect(struct psmouse *psmouse)
 	struct alps_data *priv = psmouse->private;
 
 	psmouse_reset(psmouse);
+	del_timer_sync(&priv->timer);
 	input_unregister_device(priv->dev2);
 	kfree(priv);
 }
@@ -457,6 +657,8 @@ int alps_init(struct psmouse *psmouse)
 		goto init_fail;
 
 	priv->dev2 = dev2;
+	setup_timer(&priv->timer, alps_flush_packet, (unsigned long)psmouse);
+
 	psmouse->private = priv;
 
 	if (alps_hw_init(psmouse, &version))
diff --git a/drivers/input/mouse/alps.h b/drivers/input/mouse/alps.h
index 4bbddc99962b..4b6024163d3c 100644
--- a/drivers/input/mouse/alps.h
+++ b/drivers/input/mouse/alps.h
@@ -23,6 +23,7 @@ struct alps_data {
 	char phys[32];			/* Phys */
 	const struct alps_model_info *i;/* Info */
 	int prev_fin;			/* Finger bit from previous packet */
+	struct timer_list timer;
 };
 
 #ifdef CONFIG_MOUSE_PS2_ALPS
diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c
index 19984bf06cad..c65e24510494 100644
--- a/drivers/input/mouse/synaptics.c
+++ b/drivers/input/mouse/synaptics.c
@@ -652,6 +652,16 @@ static const struct dmi_system_id toshiba_dmi_table[] = {
 			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 			DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M300"),
 		},
+
+	},
+	{
+		.ident = "Toshiba Portege M300",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "Portable PC"),
+			DMI_MATCH(DMI_PRODUCT_VERSION, "Version 1.0"),
+		},
+
 	},
 	{ }
 };
diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c
index ba9d38c3f412..0f74aeee2aea 100644
--- a/drivers/input/touchscreen/ads7846.c
+++ b/drivers/input/touchscreen/ads7846.c
@@ -17,14 +17,11 @@
  *  it under the terms of the GNU General Public License version 2 as
  *  published by the Free Software Foundation.
  */
-#include <linux/hwmon.h>
+#include <linux/device.h>
 #include <linux/init.h>
-#include <linux/err.h>
 #include <linux/delay.h>
 #include <linux/input.h>
 #include <linux/interrupt.h>
-#include <linux/slab.h>
-#include <linux/gpio.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <asm/irq.h>
@@ -33,9 +30,7 @@
 /*
  * This code has been heavily tested on a Nokia 770, and lightly
  * tested on other ads7846 devices (OSK/Mistral, Lubbock).
- * TSC2046 is just newer ads7846 silicon.
- * Support for ads7843 tested on Atmel at91sam926x-EK.
- * Support for ads7845 has only been stubbed in.
+ * Support for ads7843 and ads7845 has only been stubbed in.
  *
  * IRQ handling needs a workaround because of a shortcoming in handling
  * edge triggered IRQs on some platforms like the OMAP1/2. These
@@ -51,8 +46,7 @@
  * files.
  */
 
-#define TS_POLL_DELAY	(1 * 1000000)	/* ns delay before the first sample */
-#define TS_POLL_PERIOD	(5 * 1000000)	/* ns delay between samples */
+#define	TS_POLL_PERIOD	msecs_to_jiffies(10)
 
 /* this driver doesn't aim at the peak continuous sample rate */
 #define	SAMPLE_BITS	(8 /*cmd*/ + 16 /*sample*/ + 2 /* before, after */)
@@ -61,77 +55,57 @@ struct ts_event {
 	/* For portability, we can't read 12 bit values using SPI (which
 	 * would make the controller deliver them as native byteorder u16
 	 * with msbs zeroed).  Instead, we read them as two 8-bit values,
-	 * *** WHICH NEED BYTESWAPPING *** and range adjustment.
+	 * which need byteswapping then range adjustment.
 	 */
-	u16	x;
-	u16	y;
-	u16	z1, z2;
-	int	ignore;
-};
-
-/*
- * We allocate this separately to avoid cache line sharing issues when
- * driver is used with DMA-based SPI controllers (like atmel_spi) on
- * systems where main memory is not DMA-coherent (most non-x86 boards).
- */
-struct ads7846_packet {
-	u8			read_x, read_y, read_z1, read_z2, pwrdown;
-	u16			dummy;		/* for the pwrdown read */
-	struct ts_event		tc;
+	__be16 x;
+	__be16 y;
+	__be16 z1, z2;
+	int    ignore;
 };
 
 struct ads7846 {
 	struct input_dev	*input;
 	char			phys[32];
-	char			name[32];
 
-	struct spi_device	*spi;
-
-#if defined(CONFIG_HWMON) || defined(CONFIG_HWMON_MODULE)
-	struct attribute_group	*attr_group;
-	struct device		*hwmon;
-#endif
+	u32			*txbuf;
+	u32			*rxbuf;
+	u8			buflen;
+	u8			skip_samples;
+	u16			rotate;
 
+	struct spi_device	*spi;
 	u16			model;
-	u16			vref_mv;
 	u16			vref_delay_usecs;
 	u16			x_plate_ohms;
 	u16			pressure_max;
 
-	bool			swap_xy;
-
-	struct ads7846_packet	*packet;
+	u8			read_x, read_y, read_z1, read_z2, pwrdown;
+	u16                     zerro;          /* to send zerros while receiving */
+	u16			dummy;		/* for the pwrdown read */
+	struct ts_event		tc;
 
-	struct spi_transfer	xfer[18];
+	struct spi_transfer	xfer[10];
 	struct spi_message	msg[5];
 	struct spi_message	*last_msg;
 	int			msg_idx;
 	int			read_cnt;
 	int			read_rep;
 	int			last_read;
+	int			skip_this_sample;
 
 	u16			debounce_max;
 	u16			debounce_tol;
 	u16			debounce_rep;
 
-	u16			penirq_recheck_delay_usecs;
-
 	spinlock_t		lock;
-	struct hrtimer		timer;
+	struct timer_list	timer;		/* P: lock */
 	unsigned		pendown:1;	/* P: lock */
 	unsigned		pending:1;	/* P: lock */
 // FIXME remove "irq_disabled"
 	unsigned		irq_disabled:1;	/* P: lock */
 	unsigned		disabled:1;
-	unsigned		is_suspended:1;
 
-	int			(*filter)(void *data, int data_idx, int *val);
-	void			*filter_data;
-	void			(*filter_cleanup)(void *data);
 	int			(*get_pendown_state)(void);
-	int			gpio_pendown;
-
-	void			(*wait_for_sync)(void);
 };
 
 /* leave chip selected when we're done, for quicker re-select? */
@@ -141,6 +115,7 @@ struct ads7846 {
 #define	CS_CHANGE(xfer)	((xfer).cs_change = 0)
 #endif
 
+
 /*--------------------------------------------------------------------------*/
 
 /* The ADS7846 has touchscreen and other sensors.
@@ -167,16 +142,19 @@ struct ads7846 {
 #define	MAX_12BIT	((1<<12)-1)
 
 /* leave ADC powered up (disables penirq) between differential samples */
-#define	READ_12BIT_DFR(x, adc, vref) (ADS_START | ADS_A2A1A0_d_ ## x \
-	| ADS_12_BIT | ADS_DFR | \
-	(adc ? ADS_PD10_ADC_ON : 0) | (vref ? ADS_PD10_REF_ON : 0))
+#define	READ_12BIT_DFR(x) (ADS_START | ADS_A2A1A0_d_ ## x \
+	| ADS_12_BIT | ADS_DFR)
+
+#define	READ_Y	(READ_12BIT_DFR(y)  | ADS_PD10_ADC_ON)
+#define	READ_Z1	(READ_12BIT_DFR(z1) | ADS_PD10_ADC_ON)
+#define	READ_Z2	(READ_12BIT_DFR(z2) | ADS_PD10_ADC_ON)
 
-#define	READ_Y(vref)	(READ_12BIT_DFR(y,  1, vref))
-#define	READ_Z1(vref)	(READ_12BIT_DFR(z1, 1, vref))
-#define	READ_Z2(vref)	(READ_12BIT_DFR(z2, 1, vref))
+#define	READ_X	(READ_12BIT_DFR(x)  | ADS_PD10_ADC_ON)
+#define	PWRDOWN	(READ_12BIT_DFR(y)  | ADS_PD10_PDOWN)	/* LAST */
 
-#define	READ_X(vref)	(READ_12BIT_DFR(x,  1, vref))
-#define	PWRDOWN		(READ_12BIT_DFR(y,  0, 0))	/* LAST */
+/* alternate ads7843 commands */
+#define	ALT_READ_Y      (READ_12BIT_DFR(y)  | ADS_PD10_ALL_ON)
+#define	ALT_READ_X      (READ_12BIT_DFR(x)  | ADS_PD10_ALL_ON)
 
 /* single-ended samples need to first power up reference voltage;
  * we leave both ADC and VREF powered
@@ -184,15 +162,21 @@ struct ads7846 {
 #define	READ_12BIT_SER(x) (ADS_START | ADS_A2A1A0_ ## x \
 	| ADS_12_BIT | ADS_SER)
 
-#define	REF_ON	(READ_12BIT_DFR(x, 1, 1))
-#define	REF_OFF	(READ_12BIT_DFR(y, 0, 0))
+#define	REF_ON	(READ_12BIT_DFR(x) | ADS_PD10_ALL_ON)
+#define	REF_OFF	(READ_12BIT_DFR(y) | ADS_PD10_PDOWN)
+
+#define	MAX_BUF_SAMPLE_LEN	(20)
+/* Following configuration should be done in the platform configuration */
+#define	SCREEN_LANDSCAPE	1
+#undef	SCREEN_PORTRAIT
+#define MAX_DIFF_BETWEEN_SAMPLES_X	100
+#define MAX_DIFF_BETWEEN_SAMPLES_Y	100
+
 
 /*--------------------------------------------------------------------------*/
 
 /*
  * Non-touchscreen sensors only use single-ended conversions.
- * The range is GND..vREF. The ads7843 and ads7835 must use external vREF;
- * ads7846 lets that pin be unconnected, to use internal vREF.
  */
 
 struct ser_req {
@@ -200,6 +184,7 @@ struct ser_req {
 	u8			command;
 	u8			ref_off;
 	u16			scratch;
+	u16                     zerro;
 	__be16			sample;
 	struct spi_message	msg;
 	struct spi_transfer	xfer[6];
@@ -211,247 +196,132 @@ static void ads7846_disable(struct ads7846 *ts);
 static int device_suspended(struct device *dev)
 {
 	struct ads7846 *ts = dev_get_drvdata(dev);
-	return ts->is_suspended || ts->disabled;
+	return dev->power.power_state.event != PM_EVENT_ON || ts->disabled;
 }
 
+static int ads7843_setup_buffers(struct device *dev)
+{
+	struct ads7846		*ts = dev_get_drvdata(dev);
+	int i;
+
+	ts->txbuf = kzalloc(sizeof(u32) * ts->buflen * 3, GFP_KERNEL);
+	if (!ts->txbuf)
+		return -ENOMEM;
+
+	ts->rxbuf = kzalloc(sizeof(u32) * ts->buflen * 3, GFP_KERNEL);
+	if (!ts->rxbuf) {
+		kfree(ts->txbuf);
+		return -ENOMEM;
+	}
+	for (i = 0; i < ((ts->buflen * 3) / 2); i++)
+#if defined( SCREEN_LANDSCAPE )
+		ts->txbuf[i] = (READ_12BIT_DFR(x) | ADS_PD10_PDOWN) << 8;
+#else
+		ts->txbuf[i] = (READ_12BIT_DFR(y) | ADS_PD10_PDOWN) << 8;
+#endif
+	for (; i < ts->buflen * 3; i++)
+#if defined( SCREEN_LANDSCAPE )
+		ts->txbuf[i] = (READ_12BIT_DFR(y) | ADS_PD10_PDOWN) << 8;
+#else
+		ts->txbuf[i] = (READ_12BIT_DFR(x) | ADS_PD10_PDOWN) << 8;
+#endif
+	return 0;
+}
+
+
 static int ads7846_read12_ser(struct device *dev, unsigned command)
 {
 	struct spi_device	*spi = to_spi_device(dev);
 	struct ads7846		*ts = dev_get_drvdata(dev);
 	struct ser_req		*req = kzalloc(sizeof *req, GFP_KERNEL);
 	int			status;
-	int			use_internal;
+	int			sample;
+	int			i;
 
 	if (!req)
 		return -ENOMEM;
 
 	spi_message_init(&req->msg);
 
-	/* FIXME boards with ads7846 might use external vref instead ... */
-	use_internal = (ts->model == 7846);
-
-	/* maybe turn on internal vREF, and let it settle */
-	if (use_internal) {
-		req->ref_on = REF_ON;
-		req->xfer[0].tx_buf = &req->ref_on;
-		req->xfer[0].len = 1;
-		spi_message_add_tail(&req->xfer[0], &req->msg);
-
-		req->xfer[1].rx_buf = &req->scratch;
-		req->xfer[1].len = 2;
-
-		/* for 1uF, settle for 800 usec; no cap, 100 usec.  */
-		req->xfer[1].delay_usecs = ts->vref_delay_usecs;
-		spi_message_add_tail(&req->xfer[1], &req->msg);
-	}
+	/* activate reference, so it has time to settle; */
+	req->ref_on = REF_ON;
+	req->xfer[0].tx_buf = &req->ref_on;
+	req->xfer[0].len = 1;
+	req->xfer[1].tx_buf = &req->zerro;
+	req->xfer[1].rx_buf = &req->scratch;
+	req->xfer[1].len = 2;
+
+	/*
+	 * for external VREF, 0 usec (and assume it's always on);
+	 * for 1uF, use 800 usec;
+	 * no cap, 100 usec.
+	 */
+	req->xfer[1].delay_usecs = ts->vref_delay_usecs;
 
 	/* take sample */
 	req->command = (u8) command;
 	req->xfer[2].tx_buf = &req->command;
 	req->xfer[2].len = 1;
-	spi_message_add_tail(&req->xfer[2], &req->msg);
-
+	req->xfer[3].tx_buf = &req->zerro;
 	req->xfer[3].rx_buf = &req->sample;
 	req->xfer[3].len = 2;
-	spi_message_add_tail(&req->xfer[3], &req->msg);
 
 	/* REVISIT:  take a few more samples, and compare ... */
 
-	/* converter in low power mode & enable PENIRQ */
-	req->ref_off = PWRDOWN;
+	/* turn off reference */
+	req->ref_off = REF_OFF;
 	req->xfer[4].tx_buf = &req->ref_off;
 	req->xfer[4].len = 1;
-	spi_message_add_tail(&req->xfer[4], &req->msg);
-
+	// TODO req->xfer[3].tx_buf = &req->zerro;
+	req->xfer[5].tx_buf = &req->zerro;
 	req->xfer[5].rx_buf = &req->scratch;
 	req->xfer[5].len = 2;
+
 	CS_CHANGE(req->xfer[5]);
-	spi_message_add_tail(&req->xfer[5], &req->msg);
+
+	/* group all the transfers together, so we can't interfere with
+	 * reading touchscreen state; disable penirq while sampling
+	 */
+	for (i = 0; i < 6; i++)
+		spi_message_add_tail(&req->xfer[i], &req->msg);
 
 	ts->irq_disabled = 1;
-	disable_irq(spi->irq);
+	disable_irq_nosync(spi->irq);
 	status = spi_sync(spi, &req->msg);
 	ts->irq_disabled = 0;
 	enable_irq(spi->irq);
 
-	if (status == 0) {
-		/* on-wire is a must-ignore bit, a BE12 value, then padding */
-		status = be16_to_cpu(req->sample);
-		status = status >> 3;
-		status &= 0x0fff;
-	}
+	if (req->msg.status)
+		status = req->msg.status;
+
+	/* on-wire is a must-ignore bit, a BE12 value, then padding */
+	sample = be16_to_cpu(req->sample);
+	sample = sample >> 3;
+	sample &= 0x0fff;
 
 	kfree(req);
-	return status;
+	return status ? status : sample;
 }
 
-#if defined(CONFIG_HWMON) || defined(CONFIG_HWMON_MODULE)
-
-#define SHOW(name, var, adjust) static ssize_t \
+#define SHOW(name) static ssize_t \
 name ## _show(struct device *dev, struct device_attribute *attr, char *buf) \
 { \
-	struct ads7846 *ts = dev_get_drvdata(dev); \
 	ssize_t v = ads7846_read12_ser(dev, \
-			READ_12BIT_SER(var) | ADS_PD10_ALL_ON); \
+			READ_12BIT_SER(name) | ADS_PD10_ALL_ON); \
 	if (v < 0) \
 		return v; \
-	return sprintf(buf, "%u\n", adjust(ts, v)); \
+	return sprintf(buf, "%u\n", (unsigned) v); \
 } \
 static DEVICE_ATTR(name, S_IRUGO, name ## _show, NULL);
 
-
-/* Sysfs conventions report temperatures in millidegrees Celsius.
- * ADS7846 could use the low-accuracy two-sample scheme, but can't do the high
- * accuracy scheme without calibration data.  For now we won't try either;
- * userspace sees raw sensor values, and must scale/calibrate appropriately.
- */
-static inline unsigned null_adjust(struct ads7846 *ts, ssize_t v)
-{
-	return v;
-}
-
-SHOW(temp0, temp0, null_adjust)		/* temp1_input */
-SHOW(temp1, temp1, null_adjust)		/* temp2_input */
-
-
-/* sysfs conventions report voltages in millivolts.  We can convert voltages
- * if we know vREF.  userspace may need to scale vAUX to match the board's
- * external resistors; we assume that vBATT only uses the internal ones.
- */
-static inline unsigned vaux_adjust(struct ads7846 *ts, ssize_t v)
-{
-	unsigned retval = v;
-
-	/* external resistors may scale vAUX into 0..vREF */
-	retval *= ts->vref_mv;
-	retval = retval >> 12;
-	return retval;
-}
-
-static inline unsigned vbatt_adjust(struct ads7846 *ts, ssize_t v)
-{
-	unsigned retval = vaux_adjust(ts, v);
-
-	/* ads7846 has a resistor ladder to scale this signal down */
-	if (ts->model == 7846)
-		retval *= 4;
-	return retval;
-}
-
-SHOW(in0_input, vaux, vaux_adjust)
-SHOW(in1_input, vbatt, vbatt_adjust)
-
-
-static struct attribute *ads7846_attributes[] = {
-	&dev_attr_temp0.attr,
-	&dev_attr_temp1.attr,
-	&dev_attr_in0_input.attr,
-	&dev_attr_in1_input.attr,
-	NULL,
-};
-
-static struct attribute_group ads7846_attr_group = {
-	.attrs = ads7846_attributes,
-};
-
-static struct attribute *ads7843_attributes[] = {
-	&dev_attr_in0_input.attr,
-	&dev_attr_in1_input.attr,
-	NULL,
-};
-
-static struct attribute_group ads7843_attr_group = {
-	.attrs = ads7843_attributes,
-};
-
-static struct attribute *ads7845_attributes[] = {
-	&dev_attr_in0_input.attr,
-	NULL,
-};
-
-static struct attribute_group ads7845_attr_group = {
-	.attrs = ads7845_attributes,
-};
-
-static int ads784x_hwmon_register(struct spi_device *spi, struct ads7846 *ts)
-{
-	struct device *hwmon;
-	int err;
-
-	/* hwmon sensors need a reference voltage */
-	switch (ts->model) {
-	case 7846:
-		if (!ts->vref_mv) {
-			dev_dbg(&spi->dev, "assuming 2.5V internal vREF\n");
-			ts->vref_mv = 2500;
-		}
-		break;
-	case 7845:
-	case 7843:
-		if (!ts->vref_mv) {
-			dev_warn(&spi->dev,
-				"external vREF for ADS%d not specified\n",
-				ts->model);
-			return 0;
-		}
-		break;
-	}
-
-	/* different chips have different sensor groups */
-	switch (ts->model) {
-	case 7846:
-		ts->attr_group = &ads7846_attr_group;
-		break;
-	case 7845:
-		ts->attr_group = &ads7845_attr_group;
-		break;
-	case 7843:
-		ts->attr_group = &ads7843_attr_group;
-		break;
-	default:
-		dev_dbg(&spi->dev, "ADS%d not recognized\n", ts->model);
-		return 0;
-	}
-
-	err = sysfs_create_group(&spi->dev.kobj, ts->attr_group);
-	if (err)
-		return err;
-
-	hwmon = hwmon_device_register(&spi->dev);
-	if (IS_ERR(hwmon)) {
-		sysfs_remove_group(&spi->dev.kobj, ts->attr_group);
-		return PTR_ERR(hwmon);
-	}
-
-	ts->hwmon = hwmon;
-	return 0;
-}
-
-static void ads784x_hwmon_unregister(struct spi_device *spi,
-				     struct ads7846 *ts)
-{
-	if (ts->hwmon) {
-		sysfs_remove_group(&spi->dev.kobj, ts->attr_group);
-		hwmon_device_unregister(ts->hwmon);
-	}
-}
-
-#else
-static inline int ads784x_hwmon_register(struct spi_device *spi,
-					 struct ads7846 *ts)
-{
-	return 0;
-}
-
-static inline void ads784x_hwmon_unregister(struct spi_device *spi,
-					    struct ads7846 *ts)
-{
-}
-#endif
+SHOW(temp0)
+SHOW(temp1)
+SHOW(vaux)
+SHOW(vbatt)
 
 static int is_pen_down(struct device *dev)
 {
-	struct ads7846	*ts = dev_get_drvdata(dev);
+	struct ads7846		*ts = dev_get_drvdata(dev);
 
 	return ts->pendown;
 }
@@ -477,11 +347,10 @@ static ssize_t ads7846_disable_store(struct device *dev,
 				     const char *buf, size_t count)
 {
 	struct ads7846 *ts = dev_get_drvdata(dev);
-	unsigned long i;
-
-	if (strict_strtoul(buf, 10, &i))
-		return -EINVAL;
+	char *endp;
+	int i;
 
+	i = simple_strtoul(buf, &endp, 10);
 	spin_lock_irq(&ts->lock);
 
 	if (i)
@@ -496,30 +365,8 @@ static ssize_t ads7846_disable_store(struct device *dev,
 
 static DEVICE_ATTR(disable, 0664, ads7846_disable_show, ads7846_disable_store);
 
-static struct attribute *ads784x_attributes[] = {
-	&dev_attr_pen_down.attr,
-	&dev_attr_disable.attr,
-	NULL,
-};
-
-static struct attribute_group ads784x_attr_group = {
-	.attrs = ads784x_attributes,
-};
-
 /*--------------------------------------------------------------------------*/
 
-static int get_pendown_state(struct ads7846 *ts)
-{
-	if (ts->get_pendown_state)
-		return ts->get_pendown_state();
-
-	return !gpio_get_value(ts->gpio_pendown);
-}
-
-static void null_wait_for_sync(void)
-{
-}
-
 /*
  * PENIRQ only kicks the timer.  The timer only reissues the SPI transfer,
  * to retrieve touchscreen status.
@@ -531,25 +378,25 @@ static void null_wait_for_sync(void)
 static void ads7846_rx(void *ads)
 {
 	struct ads7846		*ts = ads;
-	struct ads7846_packet	*packet = ts->packet;
+	struct input_dev	*input_dev = ts->input;
 	unsigned		Rt;
+	unsigned		sync = 0;
 	u16			x, y, z1, z2;
+	unsigned long		flags;
 
-	/* ads7846_rx_val() did in-place conversion (including byteswap) from
-	 * on-the-wire format as part of debouncing to get stable readings.
+	/* adjust:  on-wire is a must-ignore bit, a BE12 value, then padding;
+	 * built from two 8 bit values written msb-first.
 	 */
-	x = packet->tc.x;
-	y = packet->tc.y;
-	z1 = packet->tc.z1;
-	z2 = packet->tc.z2;
+	x = (be16_to_cpu(ts->tc.x) >> 3) & 0x0fff;
+	y = (be16_to_cpu(ts->tc.y) >> 3) & 0x0fff;
+	z1 = (be16_to_cpu(ts->tc.z1) >> 3) & 0x0fff;
+	z2 = (be16_to_cpu(ts->tc.z2) >> 3) & 0x0fff;
 
 	/* range filtering */
 	if (x == MAX_12BIT)
 		x = 0;
 
-	if (ts->model == 7843) {
-		Rt = ts->pressure_max / 2;
-	} else if (likely(x && z1)) {
+	if (likely(x && z1 && !device_suspended(&ts->spi->dev))) {
 		/* compute touch pressure resistance using equation #2 */
 		Rt = z2;
 		Rt -= z1;
@@ -557,194 +404,281 @@ static void ads7846_rx(void *ads)
 		Rt *= ts->x_plate_ohms;
 		Rt /= z1;
 		Rt = (Rt + 2047) >> 12;
-	} else {
+	} else
 		Rt = 0;
-	}
 
 	/* Sample found inconsistent by debouncing or pressure is beyond
-	 * the maximum. Don't report it to user space, repeat at least
-	 * once more the measurement
-	 */
-	if (packet->tc.ignore || Rt > ts->pressure_max) {
-#ifdef VERBOSE
-		pr_debug("%s: ignored %d pressure %d\n",
-			dev_name(&ts->spi->dev), packet->tc.ignore, Rt);
-#endif
-		hrtimer_start(&ts->timer, ktime_set(0, TS_POLL_PERIOD),
-			      HRTIMER_MODE_REL);
+	* the maximum. Don't report it to user space, repeat at least
+	* once more the measurement */
+	if (ts->tc.ignore || Rt > ts->pressure_max) {
+		mod_timer(&ts->timer, jiffies + TS_POLL_PERIOD);
 		return;
 	}
 
-	/* Maybe check the pendown state before reporting. This discards
-	 * false readings when the pen is lifted.
+	/* NOTE:  "pendown" is inferred from pressure; we don't rely on
+	 * being able to check nPENIRQ status, or "friendly" trigger modes
+	 * (both-edges is much better than just-falling or low-level).
+	 *
+	 * REVISIT:  some boards may require reading nPENIRQ; it's
+	 * needed on 7843.  and 7845 reads pressure differently...
+	 *
+	 * REVISIT:  the touchscreen might not be connected; this code
+	 * won't notice that, even if nPENIRQ never fires ...
 	 */
-	if (ts->penirq_recheck_delay_usecs) {
-		udelay(ts->penirq_recheck_delay_usecs);
-		if (!get_pendown_state(ts))
-			Rt = 0;
+	if (!ts->pendown && Rt != 0) {
+		input_report_key(input_dev, BTN_TOUCH, 1);
+		sync = 1;
+	} else if (ts->pendown && Rt == 0) {
+		input_report_key(input_dev, BTN_TOUCH, 0);
+		sync = 1;
 	}
 
-	/* NOTE: We can't rely on the pressure to determine the pen down
-	 * state, even this controller has a pressure sensor.  The pressure
-	 * value can fluctuate for quite a while after lifting the pen and
-	 * in some cases may not even settle at the expected value.
-	 *
-	 * The only safe way to check for the pen up condition is in the
-	 * timer by reading the pen signal state (it's a GPIO _and_ IRQ).
-	 */
 	if (Rt) {
-		struct input_dev *input = ts->input;
+		input_report_abs(input_dev, ABS_X, x);
+		input_report_abs(input_dev, ABS_Y, y);
+		sync = 1;
+	}
 
-		if (!ts->pendown) {
-			input_report_key(input, BTN_TOUCH, 1);
-			ts->pendown = 1;
-#ifdef VERBOSE
-			dev_dbg(&ts->spi->dev, "DOWN\n");
+	if (sync) {
+		input_report_abs(input_dev, ABS_PRESSURE, Rt);
+		input_sync(input_dev);
+	}
+
+#ifdef	VERBOSE
+	if (Rt || ts->pendown)
+		pr_debug("%s: %d/%d/%d%s\n", dev_name(&ts->spi->dev),
+			x, y, Rt, Rt ? "" : " UP");
 #endif
+
+	spin_lock_irqsave(&ts->lock, flags);
+
+	ts->pendown = (Rt != 0);
+	mod_timer(&ts->timer, jiffies + TS_POLL_PERIOD);
+
+	spin_unlock_irqrestore(&ts->lock, flags);
+}
+
+static inline u16 ad7843_get_sample_val(u32 sample)
+{
+	return (((((sample & 0x00ff0000) >> 8) | (sample >> 24)) >> 3) & 0x0fff);
+}
+
+static u32 ad7843_get_better_values(struct ads7846 *ts, int index, int skiplimit)
+{
+	u32 diff12, diff23, diff31;
+	u32 vals[3];
+	int i;
+
+	for (i = 0; i < 3; i++) {
+		vals[i] = ad7843_get_sample_val(ts->rxbuf[index+i]);
+		if (vals[i] == 0x0fff || vals[i] == 0) {
+			ts->skip_this_sample = 1;
+			return 0;
 		}
+	}
 
-		if (ts->swap_xy)
-			swap(x, y);
+	diff12 = (vals[0] > vals[1]) ? vals[0] - vals[1] : vals[1] - vals[0];
+	if (diff12 > skiplimit) {
+		ts->skip_this_sample = 1;
+		return 0;
+	}
 
-		input_report_abs(input, ABS_X, x);
-		input_report_abs(input, ABS_Y, y);
-		input_report_abs(input, ABS_PRESSURE, Rt);
+	diff23 = (vals[1] > vals[2]) ? vals[1] - vals[2] : vals[2] - vals[1];
+	if (diff23 > skiplimit) {
+		ts->skip_this_sample = 1;
+		return 0;
+	}
 
-		input_sync(input);
-#ifdef VERBOSE
-		dev_dbg(&ts->spi->dev, "%4d/%4d/%4d\n", x, y, Rt);
-#endif
+	diff31 = (vals[2] > vals[0]) ? vals[2] - vals[0] : vals[0] - vals[2];
+	if (diff31 > skiplimit) {
+		ts->skip_this_sample = 1;
+		return 0;
 	}
 
-	hrtimer_start(&ts->timer, ktime_set(0, TS_POLL_PERIOD),
-			HRTIMER_MODE_REL);
+	if (diff12 < diff23 && diff12 < diff31)
+		return (vals[0] + vals[1]) / 2;
+	if (diff23 < diff12 && diff23 < diff31)
+		return (vals[1] + vals[2]) / 2;
+
+	return (vals[0] + vals[2]) / 2;
 }
 
-static int ads7846_debounce(void *ads, int data_idx, int *val)
+static void ads7843_rx_average(void *ads)
+{
+	struct ads7846          *ts = ads;
+	struct input_dev        *input_dev = ts->input;
+	u16                     x, y, temp;
+	unsigned long           flags;
+	int i, sample_count;
+
+	dev_dbg(&ts->spi->dev, "%s\n", __FUNCTION__);
+
+	for (i = 0, y = 0, x = 0, sample_count = 0; i < (ts->buflen * 3 / 2); i+=3) {
+		if (i >= ts->skip_samples*3) {
+			temp = ad7843_get_better_values(ts, i, MAX_DIFF_BETWEEN_SAMPLES_Y);
+			if (!ts->skip_this_sample) {
+				if (ts->rotate == 180) {
+					y += MAX_12BIT - temp;
+				} else if (ts->rotate == 0) {
+					y += temp;
+				} else {
+					dev_info(&ts->spi->dev,
+						 "Rotate mode %d, not implemented yet\n",
+						 ts->rotate);
+				}
+				sample_count++;
+			}
+		}
+		ts->skip_this_sample = 0;
+	}
+
+	if (!sample_count)
+		goto sample_taken;
+
+	y /= sample_count;
+
+	for (sample_count = 0; i < (ts->buflen * 3); i+=3) {
+		if (i >= (ts->skip_samples + ts->buflen / 2)*3) {
+			temp = ad7843_get_better_values(ts, i, MAX_DIFF_BETWEEN_SAMPLES_X);
+			if (!ts->skip_this_sample) {
+				if (ts->rotate == 180) {
+					x += MAX_12BIT - temp;
+				} else if (ts->rotate == 0) {
+					x += temp;
+				} else {
+					dev_info(&ts->spi->dev,
+						 "Rotate mode %d, not implemented yet\n",
+						 ts->rotate);
+				}
+				sample_count++;
+			}
+		}
+		ts->skip_this_sample = 0;
+	}
+
+	if (!sample_count)
+		goto sample_taken;
+
+	x /= sample_count;
+
+       if (ts->pendown) {
+
+               input_report_key(input_dev, BTN_TOUCH, 1);
+               input_report_abs(input_dev, ABS_PRESSURE, ts->pressure_max / 2);
+               input_report_abs(input_dev, ABS_X, x);
+               input_report_abs(input_dev, ABS_Y, y);
+       } else {
+               input_report_key(input_dev, BTN_TOUCH, 0);
+               input_report_abs(input_dev, ABS_PRESSURE, 0);
+       }
+
+       input_sync(input_dev);
+       dev_dbg(&ts->spi->dev, "%d/%d %s\n", x, y, ts->pendown ? "" : " UP");
+
+sample_taken:
+       if (ts->pendown) {
+               spin_lock_irqsave(&ts->lock, flags);
+               mod_timer(&ts->timer, jiffies + TS_POLL_PERIOD);
+               spin_unlock_irqrestore(&ts->lock, flags);
+       }
+}
+
+static void ads7846_debounce(void *ads)
 {
 	struct ads7846		*ts = ads;
+	struct spi_message	*m;
+	struct spi_transfer	*t;
+	int			val;
+	int			status;
 
-	if (!ts->read_cnt || (abs(ts->last_read - *val) > ts->debounce_tol)) {
-		/* Start over collecting consistent readings. */
-		ts->read_rep = 0;
+	m = &ts->msg[ts->msg_idx];
+	t = list_entry(m->transfers.prev, struct spi_transfer, transfer_list);
+	val = (be16_to_cpu(*(__be16 *)t->rx_buf) >> 3) & 0x0fff;
+	if (!ts->read_cnt || (abs(ts->last_read - val) > ts->debounce_tol)) {
 		/* Repeat it, if this was the first read or the read
 		 * wasn't consistent enough. */
 		if (ts->read_cnt < ts->debounce_max) {
-			ts->last_read = *val;
+			ts->last_read = val;
 			ts->read_cnt++;
-			return ADS7846_FILTER_REPEAT;
 		} else {
 			/* Maximum number of debouncing reached and still
 			 * not enough number of consistent readings. Abort
 			 * the whole sample, repeat it in the next sampling
 			 * period.
 			 */
+			ts->tc.ignore = 1;
 			ts->read_cnt = 0;
-			return ADS7846_FILTER_IGNORE;
+			/* Last message will contain ads7846_rx() as the
+			 * completion function.
+			 */
+			m = ts->last_msg;
 		}
+		/* Start over collecting consistent readings. */
+		ts->read_rep = 0;
 	} else {
 		if (++ts->read_rep > ts->debounce_rep) {
 			/* Got a good reading for this coordinate,
 			 * go for the next one. */
+			ts->tc.ignore = 0;
+			ts->msg_idx++;
 			ts->read_cnt = 0;
 			ts->read_rep = 0;
-			return ADS7846_FILTER_OK;
-		} else {
+			m++;
+		} else
 			/* Read more values that are consistent. */
 			ts->read_cnt++;
-			return ADS7846_FILTER_REPEAT;
-		}
 	}
-}
-
-static int ads7846_no_filter(void *ads, int data_idx, int *val)
-{
-	return ADS7846_FILTER_OK;
-}
-
-static void ads7846_rx_val(void *ads)
-{
-	struct ads7846 *ts = ads;
-	struct ads7846_packet *packet = ts->packet;
-	struct spi_message *m;
-	struct spi_transfer *t;
-	int val;
-	int action;
-	int status;
-
-	m = &ts->msg[ts->msg_idx];
-	t = list_entry(m->transfers.prev, struct spi_transfer, transfer_list);
-
-	/* adjust:  on-wire is a must-ignore bit, a BE12 value, then padding;
-	 * built from two 8 bit values written msb-first.
-	 */
-	val = be16_to_cpup((__be16 *)t->rx_buf) >> 3;
-
-	action = ts->filter(ts->filter_data, ts->msg_idx, &val);
-	switch (action) {
-	case ADS7846_FILTER_REPEAT:
-		break;
-	case ADS7846_FILTER_IGNORE:
-		packet->tc.ignore = 1;
-		/* Last message will contain ads7846_rx() as the
-		 * completion function.
-		 */
-		m = ts->last_msg;
-		break;
-	case ADS7846_FILTER_OK:
-		*(u16 *)t->rx_buf = val;
-		packet->tc.ignore = 0;
-		m = &ts->msg[++ts->msg_idx];
-		break;
-	default:
-		BUG();
-	}
-	ts->wait_for_sync();
 	status = spi_async(ts->spi, m);
 	if (status)
 		dev_err(&ts->spi->dev, "spi_async --> %d\n",
 				status);
 }
 
-static enum hrtimer_restart ads7846_timer(struct hrtimer *handle)
+static void ads7846_timer(unsigned long handle)
 {
-	struct ads7846	*ts = container_of(handle, struct ads7846, timer);
-	int		status = 0;
+	struct ads7846		*ts = (void *)handle;
+	struct input_dev        *input_dev = ts->input;
+	int			status = 0;
 
-	spin_lock(&ts->lock);
-
-	if (unlikely(!get_pendown_state(ts) ||
-		     device_suspended(&ts->spi->dev))) {
-		if (ts->pendown) {
-			struct input_dev *input = ts->input;
-
-			input_report_key(input, BTN_TOUCH, 0);
-			input_report_abs(input, ABS_PRESSURE, 0);
-			input_sync(input);
+	/* get sample */
+	ts->pendown = ts->get_pendown_state();
+	spin_lock_irq(&ts->lock);
+	if (ts->model == 7843) {
+		ts->pending = 0;
+		if (unlikely(!ts->pendown)) {
 
-			ts->pendown = 0;
-#ifdef VERBOSE
-			dev_dbg(&ts->spi->dev, "UP\n");
-#endif
-		}
+			input_report_key(input_dev, BTN_TOUCH, 0);
+			input_report_abs(input_dev, ABS_PRESSURE, 0);
+			input_sync(input_dev);
 
-		/* measurement cycle ended */
-		if (!device_suspended(&ts->spi->dev)) {
-			ts->irq_disabled = 0;
-			enable_irq(ts->spi->irq);
+			if (!device_suspended(&ts->spi->dev)) {
+				ts->irq_disabled = 0;
+				enable_irq(ts->spi->irq);
+			}
+		} else {
+			/* pen is still down, continue with the measurement */
+			status = spi_async(ts->spi, &ts->msg[0]);
+			if (status)
+				dev_err(&ts->spi->dev, "spi_async --> %d\n", status);
 		}
-		ts->pending = 0;
 	} else {
-		/* pen is still down, continue with the measurement */
-		ts->msg_idx = 0;
-		ts->wait_for_sync();
-		status = spi_async(ts->spi, &ts->msg[0]);
-		if (status)
-			dev_err(&ts->spi->dev, "spi_async --> %d\n", status);
+		if (unlikely(ts->msg_idx && !ts->pendown)) {
+			/* measurement cycle ended */
+			if (!device_suspended(&ts->spi->dev)) {
+				ts->irq_disabled = 0;
+				enable_irq(ts->spi->irq);
+			}
+			ts->pending = 0;
+			ts->msg_idx = 0;
+		} else {
+			/* pen is still down, continue with the measurement */
+			ts->msg_idx = 0;
+			status = spi_async(ts->spi, &ts->msg[0]);
+			if (status)
+				dev_err(&ts->spi->dev, "spi_async --> %d\n", status);
+		}
 	}
-
-	spin_unlock(&ts->lock);
-	return HRTIMER_NORESTART;
+	spin_unlock_irq(&ts->lock);
 }
 
 static irqreturn_t ads7846_irq(int irq, void *handle)
@@ -753,7 +687,8 @@ static irqreturn_t ads7846_irq(int irq, void *handle)
 	unsigned long flags;
 
 	spin_lock_irqsave(&ts->lock, flags);
-	if (likely(get_pendown_state(ts))) {
+
+	if (likely(ts->get_pendown_state())) {
 		if (!ts->irq_disabled) {
 			/* The ARM do_simple_IRQ() dispatcher doesn't act
 			 * like the other dispatchers:  it will report IRQs
@@ -763,8 +698,7 @@ static irqreturn_t ads7846_irq(int irq, void *handle)
 			ts->irq_disabled = 1;
 			disable_irq_nosync(ts->spi->irq);
 			ts->pending = 1;
-			hrtimer_start(&ts->timer, ktime_set(0, TS_POLL_DELAY),
-					HRTIMER_MODE_REL);
+			mod_timer(&ts->timer, jiffies);
 		}
 	}
 	spin_unlock_irqrestore(&ts->lock, flags);
@@ -785,7 +719,7 @@ static void ads7846_disable(struct ads7846 *ts)
 	/* are we waiting for IRQ, or polling? */
 	if (!ts->pending) {
 		ts->irq_disabled = 1;
-		disable_irq(ts->spi->irq);
+		disable_irq_nosync(ts->spi->irq);
 	} else {
 		/* the timer will run at least once more, and
 		 * leave everything in a clean state, IRQ disabled
@@ -800,6 +734,7 @@ static void ads7846_disable(struct ads7846 *ts)
 	/* we know the chip's in lowpower mode since we always
 	 * leave it that way after every request
 	 */
+
 }
 
 /* Must be called with ts->lock held */
@@ -819,7 +754,7 @@ static int ads7846_suspend(struct spi_device *spi, pm_message_t message)
 
 	spin_lock_irq(&ts->lock);
 
-	ts->is_suspended = 1;
+	spi->dev.power.power_state = message;
 	ads7846_disable(ts);
 
 	spin_unlock_irq(&ts->lock);
@@ -834,7 +769,7 @@ static int ads7846_resume(struct spi_device *spi)
 
 	spin_lock_irq(&ts->lock);
 
-	ts->is_suspended = 0;
+	spi->dev.power.power_state = PMSG_ON;
 	ads7846_enable(ts);
 
 	spin_unlock_irq(&ts->lock);
@@ -842,45 +777,13 @@ static int ads7846_resume(struct spi_device *spi)
 	return 0;
 }
 
-static int __devinit setup_pendown(struct spi_device *spi, struct ads7846 *ts)
-{
-	struct ads7846_platform_data *pdata = spi->dev.platform_data;
-	int err;
-
-	/* REVISIT when the irq can be triggered active-low, or if for some
-	 * reason the touchscreen isn't hooked up, we don't need to access
-	 * the pendown state.
-	 */
-	if (!pdata->get_pendown_state && !gpio_is_valid(pdata->gpio_pendown)) {
-		dev_err(&spi->dev, "no get_pendown_state nor gpio_pendown?\n");
-		return -EINVAL;
-	}
-
-	if (pdata->get_pendown_state) {
-		ts->get_pendown_state = pdata->get_pendown_state;
-		return 0;
-	}
-
-	err = gpio_request(pdata->gpio_pendown, "ads7846_pendown");
-	if (err) {
-		dev_err(&spi->dev, "failed to request pendown GPIO%d\n",
-				pdata->gpio_pendown);
-		return err;
-	}
-
-	ts->gpio_pendown = pdata->gpio_pendown;
-	return 0;
-}
-
 static int __devinit ads7846_probe(struct spi_device *spi)
 {
 	struct ads7846			*ts;
-	struct ads7846_packet		*packet;
 	struct input_dev		*input_dev;
 	struct ads7846_platform_data	*pdata = spi->dev.platform_data;
 	struct spi_message		*m;
 	struct spi_transfer		*x;
-	int				vref;
 	int				err;
 
 	if (!spi->irq) {
@@ -900,33 +803,46 @@ static int __devinit ads7846_probe(struct spi_device *spi)
 		return -EINVAL;
 	}
 
+	/* REVISIT when the irq can be triggered active-low, or if for some
+	 * reason the touchscreen isn't hooked up, we don't need to access
+	 * the pendown state.
+	 */
+	if (pdata->get_pendown_state == NULL) {
+		dev_dbg(&spi->dev, "no get_pendown_state function?\n");
+		return -EINVAL;
+	}
+
 	/* We'd set TX wordsize 8 bits and RX wordsize to 13 bits ... except
 	 * that even if the hardware can do that, the SPI controller driver
 	 * may not.  So we stick to very-portable 8 bit words, both RX and TX.
 	 */
 	spi->bits_per_word = 8;
-	spi->mode = SPI_MODE_0;
-	err = spi_setup(spi);
-	if (err < 0)
-		return err;
 
 	ts = kzalloc(sizeof(struct ads7846), GFP_KERNEL);
-	packet = kzalloc(sizeof(struct ads7846_packet), GFP_KERNEL);
 	input_dev = input_allocate_device();
-	if (!ts || !packet || !input_dev) {
+	if (!ts || !input_dev) {
 		err = -ENOMEM;
 		goto err_free_mem;
 	}
 
 	dev_set_drvdata(&spi->dev, ts);
 
-	ts->packet = packet;
+	spi->dev.power.power_state = PMSG_ON;
+
 	ts->spi = spi;
 	ts->input = input_dev;
-	ts->vref_mv = pdata->vref_mv;
-	ts->swap_xy = pdata->swap_xy;
 
-	hrtimer_init(&ts->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+	ts->buflen = pdata->buflen ? : MAX_BUF_SAMPLE_LEN;
+	ts->buflen = ts->buflen & ~0x1;	/* must be even */
+
+	if (ads7843_setup_buffers(&spi->dev)) {
+		dev_dbg(&spi->dev, "error allocating memory for sample buffers\n");
+		err = -ENOMEM;
+		goto err_free_mem;
+	}
+
+	init_timer(&ts->timer);
+	ts->timer.data = (unsigned long) ts;
 	ts->timer.function = ads7846_timer;
 
 	spin_lock_init(&ts->lock);
@@ -935,40 +851,22 @@ static int __devinit ads7846_probe(struct spi_device *spi)
 	ts->vref_delay_usecs = pdata->vref_delay_usecs ? : 100;
 	ts->x_plate_ohms = pdata->x_plate_ohms ? : 400;
 	ts->pressure_max = pdata->pressure_max ? : ~0;
+	ts->skip_samples = pdata->skip_samples ? : 0;
+	ts->rotate = pdata->rotate ? : 0;
 
-	if (pdata->filter != NULL) {
-		if (pdata->filter_init != NULL) {
-			err = pdata->filter_init(pdata, &ts->filter_data);
-			if (err < 0)
-				goto err_free_mem;
-		}
-		ts->filter = pdata->filter;
-		ts->filter_cleanup = pdata->filter_cleanup;
-	} else if (pdata->debounce_max) {
+	if (pdata->debounce_max) {
 		ts->debounce_max = pdata->debounce_max;
-		if (ts->debounce_max < 2)
-			ts->debounce_max = 2;
 		ts->debounce_tol = pdata->debounce_tol;
 		ts->debounce_rep = pdata->debounce_rep;
-		ts->filter = ads7846_debounce;
-		ts->filter_data = ts;
+		if (ts->debounce_rep > ts->debounce_max + 1)
+			ts->debounce_rep = ts->debounce_max - 1;
 	} else
-		ts->filter = ads7846_no_filter;
-
-	err = setup_pendown(spi, ts);
-	if (err)
-		goto err_cleanup_filter;
-
-	if (pdata->penirq_recheck_delay_usecs)
-		ts->penirq_recheck_delay_usecs =
-				pdata->penirq_recheck_delay_usecs;
-
-	ts->wait_for_sync = pdata->wait_for_sync ? : null_wait_for_sync;
+		ts->debounce_tol = ~0;
+	ts->get_pendown_state = pdata->get_pendown_state;
 
 	snprintf(ts->phys, sizeof(ts->phys), "%s/input0", dev_name(&spi->dev));
-	snprintf(ts->name, sizeof(ts->name), "ADS%d Touchscreen", ts->model);
 
-	input_dev->name = ts->name;
+	input_dev->name = "ADS784x Touchscreen";
 	input_dev->phys = ts->phys;
 	input_dev->dev.parent = &spi->dev;
 
@@ -983,9 +881,8 @@ static int __devinit ads7846_probe(struct spi_device *spi)
 			pdata->y_max ? : MAX_12BIT,
 			0, 0);
 	input_set_abs_params(input_dev, ABS_PRESSURE,
-			pdata->pressure_min, pdata->pressure_max, 0, 0);
-
-	vref = pdata->keep_vref_on;
+			pdata->pressure_min ? : 0,
+			pdata->pressure_max ? : 1, 0, 0);
 
 	/* set up the transfers to read touchscreen state; this assumes we
 	 * use formula #2 for pressure, not #3.
@@ -995,209 +892,176 @@ static int __devinit ads7846_probe(struct spi_device *spi)
 
 	spi_message_init(m);
 
-	/* y- still on; turn on only y+ (and ADC) */
-	packet->read_y = READ_Y(vref);
-	x->tx_buf = &packet->read_y;
-	x->len = 1;
-	spi_message_add_tail(x, m);
-
-	x++;
-	x->rx_buf = &packet->tc.y;
-	x->len = 2;
-	spi_message_add_tail(x, m);
-
-	/* the first sample after switching drivers can be low quality;
-	 * optionally discard it, using a second one after the signals
-	 * have had enough time to stabilize.
-	 */
-	if (pdata->settle_delay_usecs) {
-		x->delay_usecs = pdata->settle_delay_usecs;
-
-		x++;
-		x->tx_buf = &packet->read_y;
-		x->len = 1;
+	if (ts->model == 7843) {
+		x->tx_buf = ts->txbuf;
+		x->rx_buf = ts->rxbuf;
+		x->len = ts->buflen * sizeof(u32) * 3; /* For every sample we take 3 samples and choose the better 2 */
 		spi_message_add_tail(x, m);
 
-		x++;
-		x->rx_buf = &packet->tc.y;
-		x->len = 2;
-		spi_message_add_tail(x, m);
-	}
-
-	m->complete = ads7846_rx_val;
-	m->context = ts;
-
-	m++;
-	spi_message_init(m);
-
-	/* turn y- off, x+ on, then leave in lowpower */
-	x++;
-	packet->read_x = READ_X(vref);
-	x->tx_buf = &packet->read_x;
-	x->len = 1;
-	spi_message_add_tail(x, m);
-
-	x++;
-	x->rx_buf = &packet->tc.x;
-	x->len = 2;
-	spi_message_add_tail(x, m);
-
-	/* ... maybe discard first sample ... */
-	if (pdata->settle_delay_usecs) {
-		x->delay_usecs = pdata->settle_delay_usecs;
+		m->complete = ads7843_rx_average;
+		m->context = ts;
 
-		x++;
-		x->tx_buf = &packet->read_x;
+		ts->last_msg = m;
+	} else {
+		/* y- still on; turn on only y+ (and ADC) */
+		ts->read_y = READ_Y;
+		x->tx_buf = &ts->read_y;
 		x->len = 1;
 		spi_message_add_tail(x, m);
 
 		x++;
-		x->rx_buf = &packet->tc.x;
+		x->rx_buf = &ts->tc.y;
 		x->len = 2;
 		spi_message_add_tail(x, m);
-	}
 
-	m->complete = ads7846_rx_val;
-	m->context = ts;
+		m->complete = ads7846_debounce;
+		m->context = ts;
 
-	/* turn y+ off, x- on; we'll use formula #2 */
-	if (ts->model == 7846) {
 		m++;
 		spi_message_init(m);
 
+		/* turn y- off, x+ on, then leave in lowpower */
 		x++;
-		packet->read_z1 = READ_Z1(vref);
-		x->tx_buf = &packet->read_z1;
+		ts->read_x = READ_X;
+		x->tx_buf = &ts->read_x;
 		x->len = 1;
 		spi_message_add_tail(x, m);
 
 		x++;
-		x->rx_buf = &packet->tc.z1;
+		x->rx_buf = &ts->tc.x;
 		x->len = 2;
 		spi_message_add_tail(x, m);
 
-		/* ... maybe discard first sample ... */
-		if (pdata->settle_delay_usecs) {
-			x->delay_usecs = pdata->settle_delay_usecs;
+		m->complete = ads7846_debounce;
+		m->context = ts;
+
+		/* turn y+ off, x- on; we'll use formula #2 */
+		if (ts->model == 7846) {
+			m++;
+			spi_message_init(m);
 
 			x++;
-			x->tx_buf = &packet->read_z1;
+			ts->read_z1 = READ_Z1;
+			x->tx_buf = &ts->read_z1;
 			x->len = 1;
 			spi_message_add_tail(x, m);
 
 			x++;
-			x->rx_buf = &packet->tc.z1;
+			x->rx_buf = &ts->tc.z1;
 			x->len = 2;
 			spi_message_add_tail(x, m);
-		}
-
-		m->complete = ads7846_rx_val;
-		m->context = ts;
-
-		m++;
-		spi_message_init(m);
 
-		x++;
-		packet->read_z2 = READ_Z2(vref);
-		x->tx_buf = &packet->read_z2;
-		x->len = 1;
-		spi_message_add_tail(x, m);
-
-		x++;
-		x->rx_buf = &packet->tc.z2;
-		x->len = 2;
-		spi_message_add_tail(x, m);
+			m->complete = ads7846_debounce;
+			m->context = ts;
 
-		/* ... maybe discard first sample ... */
-		if (pdata->settle_delay_usecs) {
-			x->delay_usecs = pdata->settle_delay_usecs;
+			m++;
+			spi_message_init(m);
 
 			x++;
-			x->tx_buf = &packet->read_z2;
+			ts->read_z2 = READ_Z2;
+			x->tx_buf = &ts->read_z2;
 			x->len = 1;
 			spi_message_add_tail(x, m);
 
 			x++;
-			x->rx_buf = &packet->tc.z2;
+			x->rx_buf = &ts->tc.z2;
 			x->len = 2;
 			spi_message_add_tail(x, m);
-		}
 
-		m->complete = ads7846_rx_val;
-		m->context = ts;
-	}
+			m->complete = ads7846_debounce;
+			m->context = ts;
+		}
 
-	/* power down */
-	m++;
-	spi_message_init(m);
+		/* power down */
+		m++;
+		spi_message_init(m);
 
-	x++;
-	packet->pwrdown = PWRDOWN;
-	x->tx_buf = &packet->pwrdown;
-	x->len = 1;
-	spi_message_add_tail(x, m);
+		x++;
+		ts->pwrdown = PWRDOWN;
+		x->tx_buf = &ts->pwrdown;
+		x->len = 1;
+		spi_message_add_tail(x, m);
 
-	x++;
-	x->rx_buf = &packet->dummy;
-	x->len = 2;
-	CS_CHANGE(*x);
-	spi_message_add_tail(x, m);
+		x++;
+		x->rx_buf = &ts->dummy;
+		x->len = 2;
+		CS_CHANGE(*x);
+		spi_message_add_tail(x, m);
 
-	m->complete = ads7846_rx;
-	m->context = ts;
+		m->complete = ads7846_rx;
+		m->context = ts;
 
-	ts->last_msg = m;
+		ts->last_msg = m;
+	}
 
 	if (request_irq(spi->irq, ads7846_irq, IRQF_TRIGGER_FALLING,
 			spi->dev.driver->name, ts)) {
-		dev_info(&spi->dev,
-			"trying pin change workaround on irq %d\n", spi->irq);
-		err = request_irq(spi->irq, ads7846_irq,
-				  IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
-				  spi->dev.driver->name, ts);
-		if (err) {
-			dev_dbg(&spi->dev, "irq %d busy?\n", spi->irq);
-			goto err_free_gpio;
-		}
+		dev_dbg(&spi->dev, "irq %d busy?\n", spi->irq);
+		err = -EBUSY;
+		goto err_free_buf;
 	}
 
-	err = ads784x_hwmon_register(spi, ts);
-	if (err)
-		goto err_free_irq;
-
 	dev_info(&spi->dev, "touchscreen, irq %d\n", spi->irq);
 
-	/* take a first sample, leaving nPENIRQ active and vREF off; avoid
+	/* take a first sample, leaving nPENIRQ active; avoid
 	 * the touchscreen, in case it's not connected.
 	 */
-	(void) ads7846_read12_ser(&spi->dev,
-			  READ_12BIT_SER(vaux) | ADS_PD10_ALL_ON);
+	if (ts->model != 7843) {
+		/* take a first sample, leaving nPENIRQ active; avoid
+		 * the touchscreen, in case it's not connected.
+		 */
+		(void) ads7846_read12_ser(&spi->dev,
+				READ_12BIT_SER(vaux) | ADS_PD10_ALL_ON);
+	}
 
-	err = sysfs_create_group(&spi->dev.kobj, &ads784x_attr_group);
-	if (err)
-		goto err_remove_hwmon;
+	/* ads7843/7845 don't have temperature sensors, and
+	 * use the other sensors a bit differently too
+	 */
+	if (ts->model == 7846) {
+		device_create_file(&spi->dev, &dev_attr_temp0);
+		device_create_file(&spi->dev, &dev_attr_temp1);
+	}
+
+	if (ts->model != 7845 && ts->model != 7843)
+		device_create_file(&spi->dev, &dev_attr_vbatt);
+
+	if (ts->model != 7843) {
+		device_create_file(&spi->dev, &dev_attr_vaux);
+	}
+
+	device_create_file(&spi->dev, &dev_attr_pen_down);
+	device_create_file(&spi->dev, &dev_attr_disable);
 
 	err = input_register_device(input_dev);
 	if (err)
-		goto err_remove_attr_group;
+		goto err_remove_attr;
 
 	return 0;
 
- err_remove_attr_group:
-	sysfs_remove_group(&spi->dev.kobj, &ads784x_attr_group);
- err_remove_hwmon:
-	ads784x_hwmon_unregister(spi, ts);
- err_free_irq:
+ err_remove_attr:
+	device_remove_file(&spi->dev, &dev_attr_disable);
+	device_remove_file(&spi->dev, &dev_attr_pen_down);
+	if (ts->model == 7846) {
+		device_remove_file(&spi->dev, &dev_attr_temp1);
+		device_remove_file(&spi->dev, &dev_attr_temp0);
+	}
+
+	if (ts->model != 7845 && ts->model != 7843)
+		device_remove_file(&spi->dev, &dev_attr_vbatt);
+
+	if (ts->model != 7843) {
+		device_remove_file(&spi->dev, &dev_attr_vaux);
+	}
+
 	free_irq(spi->irq, ts);
- err_free_gpio:
-	if (ts->gpio_pendown != -1)
-		gpio_free(ts->gpio_pendown);
- err_cleanup_filter:
-	if (ts->filter_cleanup)
-		ts->filter_cleanup(ts->filter_data);
+
+ err_free_buf:
+	if (ts->txbuf)
+		kfree(ts->txbuf);
+	if (ts->rxbuf)
+		kfree(ts->rxbuf);
  err_free_mem:
 	input_free_device(input_dev);
-	kfree(packet);
 	kfree(ts);
 	return err;
 }
@@ -1206,24 +1070,33 @@ static int __devexit ads7846_remove(struct spi_device *spi)
 {
 	struct ads7846		*ts = dev_get_drvdata(&spi->dev);
 
-	ads784x_hwmon_unregister(spi, ts);
 	input_unregister_device(ts->input);
 
 	ads7846_suspend(spi, PMSG_SUSPEND);
 
-	sysfs_remove_group(&spi->dev.kobj, &ads784x_attr_group);
+	if (ts->txbuf)
+		kfree(ts->txbuf);
+	if (ts->rxbuf)
+		kfree(ts->rxbuf);
 
-	free_irq(ts->spi->irq, ts);
-	/* suspend left the IRQ disabled */
-	enable_irq(ts->spi->irq);
+	device_remove_file(&spi->dev, &dev_attr_disable);
+	device_remove_file(&spi->dev, &dev_attr_pen_down);
+	if (ts->model == 7846) {
+		device_remove_file(&spi->dev, &dev_attr_temp1);
+		device_remove_file(&spi->dev, &dev_attr_temp0);
+	}
+
+	if (ts->model != 7845 && ts->model != 7843)
+		device_remove_file(&spi->dev, &dev_attr_vbatt);
 
-	if (ts->gpio_pendown != -1)
-		gpio_free(ts->gpio_pendown);
+	if (ts->model != 7843) {
+		device_remove_file(&spi->dev, &dev_attr_vaux);
+	}
 
-	if (ts->filter_cleanup)
-		ts->filter_cleanup(ts->filter_data);
+	free_irq(ts->spi->irq, ts);
+	/* suspend left the IRQ disabled */
+	disable_irq_nosync(ts->spi->irq);
 
-	kfree(ts->packet);
 	kfree(ts);
 
 	dev_dbg(&spi->dev, "unregistered touchscreen\n");
diff --git a/drivers/input/touchscreen/mxc_ts.c b/drivers/input/touchscreen/mxc_ts.c
index 610f31e65778..6146b27f01da 100644
--- a/drivers/input/touchscreen/mxc_ts.c
+++ b/drivers/input/touchscreen/mxc_ts.c
@@ -76,8 +76,7 @@ static int ts_thread(void *arg)
 			msleep(20);
 			continue;
 		}
-		if (!(ts_sample.contact_resistance || wait))
-		{
+		if (!(ts_sample.contact_resistance || wait)) {
 			msleep(20);
 			continue;
 		}
diff --git a/drivers/isdn/gigaset/interface.c b/drivers/isdn/gigaset/interface.c
index 8ff7e35c7069..f33ac27de643 100644
--- a/drivers/isdn/gigaset/interface.c
+++ b/drivers/isdn/gigaset/interface.c
@@ -408,33 +408,28 @@ static int if_write_room(struct tty_struct *tty)
 	return retval;
 }
 
-/* FIXME: This function does not have error returns */
-
 static int if_chars_in_buffer(struct tty_struct *tty)
 {
 	struct cardstate *cs;
-	int retval = -ENODEV;
+	int retval = 0;
 
 	cs = (struct cardstate *) tty->driver_data;
 	if (!cs) {
 		pr_err("%s: no cardstate\n", __func__);
-		return -ENODEV;
+		return 0;
 	}
 
 	gig_dbg(DEBUG_IF, "%u: %s()", cs->minor_index, __func__);
 
-	if (mutex_lock_interruptible(&cs->mutex))
-		return -ERESTARTSYS; // FIXME -EINTR?
+	mutex_lock(&cs->mutex);
 
-	if (!cs->connected) {
+	if (!cs->connected)
 		gig_dbg(DEBUG_IF, "not connected");
-		retval = -ENODEV;
-	} else if (!cs->open_count)
+	else if (!cs->open_count)
 		dev_warn(cs->dev, "%s: device not opened\n", __func__);
-	else if (cs->mstate != MS_LOCKED) {
+	else if (cs->mstate != MS_LOCKED)
 		dev_warn(cs->dev, "can't write to unlocked device\n");
-		retval = -EBUSY;
-	} else
+	else
 		retval = cs->ops->chars_in_buffer(cs);
 
 	mutex_unlock(&cs->mutex);
diff --git a/drivers/isdn/hisax/hfc_usb.c b/drivers/isdn/hisax/hfc_usb.c
index 9de54202c90c..a420b64472e3 100644
--- a/drivers/isdn/hisax/hfc_usb.c
+++ b/drivers/isdn/hisax/hfc_usb.c
@@ -817,8 +817,8 @@ collect_rx_frame(usb_fifo * fifo, __u8 * data, int len, int finish)
 	}
 	/* we have a complete hdlc packet */
 	if (finish) {
-		if ((!fifo->skbuff->data[fifo->skbuff->len - 1])
-		    && (fifo->skbuff->len > 3)) {
+		if (fifo->skbuff->len > 3 &&
+				!fifo->skbuff->data[fifo->skbuff->len - 1]) {
 
 			if (fifon == HFCUSB_D_RX) {
 				DBG(HFCUSB_DBG_DCHANNEL,
diff --git a/drivers/isdn/i4l/isdn_ppp.c b/drivers/isdn/i4l/isdn_ppp.c
index aa30b5cb3513..9a9dc3be1c49 100644
--- a/drivers/isdn/i4l/isdn_ppp.c
+++ b/drivers/isdn/i4l/isdn_ppp.c
@@ -1535,10 +1535,8 @@ static int isdn_ppp_mp_bundle_array_init(void)
 	int sz = ISDN_MAX_CHANNELS*sizeof(ippp_bundle);
 	if( (isdn_ppp_bundle_arr = kzalloc(sz, GFP_KERNEL)) == NULL )
 		return -ENOMEM;
-	for (i = 0; i < ISDN_MAX_CHANNELS; i++) {
+	for( i = 0; i < ISDN_MAX_CHANNELS; i++ )
 		spin_lock_init(&isdn_ppp_bundle_arr[i].lock);
-		skb_queue_head_init(&isdn_ppp_bundle_arr[i].frags);
-	}
 	return 0;
 }
 
@@ -1571,7 +1569,7 @@ static int isdn_ppp_mp_init( isdn_net_local * lp, ippp_bundle * add_to )
 		if ((lp->netdev->pb = isdn_ppp_mp_bundle_alloc()) == NULL)
 			return -ENOMEM;
 		lp->next = lp->last = lp;	/* nobody else in a queue */
-		skb_queue_head_init(&lp->netdev->pb->frags);
+		lp->netdev->pb->frags = NULL;
 		lp->netdev->pb->frames = 0;
 		lp->netdev->pb->seq = UINT_MAX;
 	}
@@ -1583,29 +1581,28 @@ static int isdn_ppp_mp_init( isdn_net_local * lp, ippp_bundle * add_to )
 
 static u32 isdn_ppp_mp_get_seq( int short_seq, 
 					struct sk_buff * skb, u32 last_seq );
-static void isdn_ppp_mp_discard(ippp_bundle *mp, struct sk_buff *from,
-				struct sk_buff *to);
-static void isdn_ppp_mp_reassembly(isdn_net_dev *net_dev, isdn_net_local *lp,
-				   struct sk_buff *from, struct sk_buff *to,
-				   u32 lastseq);
-static void isdn_ppp_mp_free_skb(ippp_bundle *mp, struct sk_buff *skb);
+static struct sk_buff * isdn_ppp_mp_discard( ippp_bundle * mp,
+			struct sk_buff * from, struct sk_buff * to );
+static void isdn_ppp_mp_reassembly( isdn_net_dev * net_dev, isdn_net_local * lp,
+				struct sk_buff * from, struct sk_buff * to );
+static void isdn_ppp_mp_free_skb( ippp_bundle * mp, struct sk_buff * skb );
 static void isdn_ppp_mp_print_recv_pkt( int slot, struct sk_buff * skb );
 
 static void isdn_ppp_mp_receive(isdn_net_dev * net_dev, isdn_net_local * lp, 
-				struct sk_buff *skb)
+							struct sk_buff *skb)
 {
-	struct sk_buff *newfrag, *frag, *start, *nextf;
-	u32 newseq, minseq, thisseq;
-	isdn_mppp_stats *stats;
 	struct ippp_struct *is;
+	isdn_net_local * lpq;
+	ippp_bundle * mp;
+	isdn_mppp_stats * stats;
+	struct sk_buff * newfrag, * frag, * start, *nextf;
+	u32 newseq, minseq, thisseq;
 	unsigned long flags;
-	isdn_net_local *lpq;
-	ippp_bundle *mp;
 	int slot;
 
 	spin_lock_irqsave(&net_dev->pb->lock, flags);
-	mp = net_dev->pb;
-	stats = &mp->stats;
+    	mp = net_dev->pb;
+        stats = &mp->stats;
 	slot = lp->ppp_slot;
 	if (slot < 0 || slot >= ISDN_MAX_CHANNELS) {
 		printk(KERN_ERR "%s: lp->ppp_slot(%d)\n",
@@ -1616,19 +1613,20 @@ static void isdn_ppp_mp_receive(isdn_net_dev * net_dev, isdn_net_local * lp,
 		return;
 	}
 	is = ippp_table[slot];
-	if (++mp->frames > stats->max_queue_len)
+    	if( ++mp->frames > stats->max_queue_len )
 		stats->max_queue_len = mp->frames;
 
 	if (is->debug & 0x8)
 		isdn_ppp_mp_print_recv_pkt(lp->ppp_slot, skb);
 
 	newseq = isdn_ppp_mp_get_seq(is->mpppcfg & SC_IN_SHORT_SEQ,
-				     skb, is->last_link_seqno);
+						skb, is->last_link_seqno);
+
 
 	/* if this packet seq # is less than last already processed one,
 	 * toss it right away, but check for sequence start case first 
 	 */
-	if (mp->seq > MP_LONGSEQ_MAX && (newseq & MP_LONGSEQ_MAXBIT)) {
+	if( mp->seq > MP_LONGSEQ_MAX && (newseq & MP_LONGSEQ_MAXBIT) ) {
 		mp->seq = newseq;	/* the first packet: required for
 					 * rfc1990 non-compliant clients --
 					 * prevents constant packet toss */
@@ -1659,31 +1657,22 @@ static void isdn_ppp_mp_receive(isdn_net_dev * net_dev, isdn_net_local * lp,
 					 * packets */
 	newfrag = skb;
 
-	/* Insert new fragment into the proper sequence slot.  */
-	skb_queue_walk(&mp->frags, frag) {
-		if (MP_SEQ(frag) == newseq) {
-			isdn_ppp_mp_free_skb(mp, newfrag);
-			newfrag = NULL;
-			break;
-		}
-		if (MP_LT(newseq, MP_SEQ(frag))) {
-			__skb_queue_before(&mp->frags, frag, newfrag);
-			newfrag = NULL;
-			break;
-		}
-	}
-	if (newfrag)
-		__skb_queue_tail(&mp->frags, newfrag);
+  	/* if this new fragment is before the first one, then enqueue it now. */
+  	if ((frag = mp->frags) == NULL || MP_LT(newseq, MP_SEQ(frag))) {
+		newfrag->next = frag;
+    		mp->frags = frag = newfrag;
+    		newfrag = NULL;
+  	}
 
-	frag = skb_peek(&mp->frags);
-	start = ((MP_FLAGS(frag) & MP_BEGIN_FRAG) &&
-		 (MP_SEQ(frag) == mp->seq)) ? frag : NULL;
-	if (!start)
-		goto check_overflow;
+  	start = MP_FLAGS(frag) & MP_BEGIN_FRAG &&
+				MP_SEQ(frag) == mp->seq ? frag : NULL;
 
-	/* main fragment traversing loop
+	/*
+	 * main fragment traversing loop
 	 *
 	 * try to accomplish several tasks:
+	 * - insert new fragment into the proper sequence slot (once that's done
+	 *   newfrag will be set to NULL)
 	 * - reassemble any complete fragment sequence (non-null 'start'
 	 *   indicates there is a continguous sequence present)
 	 * - discard any incomplete sequences that are below minseq -- due
@@ -1692,46 +1681,71 @@ static void isdn_ppp_mp_receive(isdn_net_dev * net_dev, isdn_net_local * lp,
 	 *   come to complete such sequence and it should be discarded
 	 *
 	 * loop completes when we accomplished the following tasks:
+	 * - new fragment is inserted in the proper sequence ('newfrag' is
+	 *   set to NULL)
 	 * - we hit a gap in the sequence, so no reassembly/processing is 
 	 *   possible ('start' would be set to NULL)
 	 *
 	 * algorithm for this code is derived from code in the book
 	 * 'PPP Design And Debugging' by James Carlson (Addison-Wesley)
 	 */
-	skb_queue_walk_safe(&mp->frags, frag, nextf) {
-		thisseq = MP_SEQ(frag);
-
-		/* check for misplaced start */
-		if (start != frag && (MP_FLAGS(frag) & MP_BEGIN_FRAG)) {
-			printk(KERN_WARNING"isdn_mppp(seq %d): new "
-			       "BEGIN flag with no prior END", thisseq);
-			stats->seqerrs++;
-			stats->frame_drops++;
-			isdn_ppp_mp_discard(mp, start, frag);
-			start = frag;
-		} else if (MP_LE(thisseq, minseq)) {		
-			if (MP_FLAGS(frag) & MP_BEGIN_FRAG)
+  	while (start != NULL || newfrag != NULL) {
+
+    		thisseq = MP_SEQ(frag);
+    		nextf = frag->next;
+
+    		/* drop any duplicate fragments */
+    		if (newfrag != NULL && thisseq == newseq) {
+      			isdn_ppp_mp_free_skb(mp, newfrag);
+      			newfrag = NULL;
+    		}
+
+    		/* insert new fragment before next element if possible. */
+    		if (newfrag != NULL && (nextf == NULL ||
+						MP_LT(newseq, MP_SEQ(nextf)))) {
+      			newfrag->next = nextf;
+      			frag->next = nextf = newfrag;
+      			newfrag = NULL;
+    		}
+
+    		if (start != NULL) {
+	    		/* check for misplaced start */
+      			if (start != frag && (MP_FLAGS(frag) & MP_BEGIN_FRAG)) {
+				printk(KERN_WARNING"isdn_mppp(seq %d): new "
+				      "BEGIN flag with no prior END", thisseq);
+				stats->seqerrs++;
+				stats->frame_drops++;
+				start = isdn_ppp_mp_discard(mp, start,frag);
+				nextf = frag->next;
+      			}
+    		} else if (MP_LE(thisseq, minseq)) {
+      			if (MP_FLAGS(frag) & MP_BEGIN_FRAG)
 				start = frag;
-			else {
+      			else {
 				if (MP_FLAGS(frag) & MP_END_FRAG)
-					stats->frame_drops++;
-				__skb_unlink(skb, &mp->frags);
+	  				stats->frame_drops++;
+				if( mp->frags == frag )
+					mp->frags = nextf;
 				isdn_ppp_mp_free_skb(mp, frag);
+				frag = nextf;
 				continue;
-			}
+      			}
 		}
 
-		/* if we have end fragment, then we have full reassembly
-		 * sequence -- reassemble and process packet now
+		/* if start is non-null and we have end fragment, then
+		 * we have full reassembly sequence -- reassemble
+		 * and process packet now
 		 */
-		if (MP_FLAGS(frag) & MP_END_FRAG) {
-			minseq = mp->seq = (thisseq+1) & MP_LONGSEQ_MASK;
-			/* Reassemble the packet then dispatch it */
-			isdn_ppp_mp_reassembly(net_dev, lp, start, frag, thisseq);
+    		if (start != NULL && (MP_FLAGS(frag) & MP_END_FRAG)) {
+      			minseq = mp->seq = (thisseq+1) & MP_LONGSEQ_MASK;
+      			/* Reassemble the packet then dispatch it */
+			isdn_ppp_mp_reassembly(net_dev, lp, start, nextf);
 
-			start = NULL;
-			frag = NULL;
-		}
+      			start = NULL;
+      			frag = NULL;
+
+      			mp->frags = nextf;
+    		}
 
 		/* check if need to update start pointer: if we just
 		 * reassembled the packet and sequence is contiguous
@@ -1742,25 +1756,26 @@ static void isdn_ppp_mp_receive(isdn_net_dev * net_dev, isdn_net_local * lp,
 		 * below low watermark and set start to the next frag or
 		 * clear start ptr.
 		 */ 
-		if (nextf != (struct sk_buff *)&mp->frags && 
+    		if (nextf != NULL &&
 		    ((thisseq+1) & MP_LONGSEQ_MASK) == MP_SEQ(nextf)) {
-			/* if we just reassembled and the next one is here, 
-			 * then start another reassembly.
-			 */
-			if (frag == NULL) {
+      			/* if we just reassembled and the next one is here,
+			 * then start another reassembly. */
+
+      			if (frag == NULL) {
 				if (MP_FLAGS(nextf) & MP_BEGIN_FRAG)
-					start = nextf;
-				else {
-					printk(KERN_WARNING"isdn_mppp(seq %d):"
-					       " END flag with no following "
-					       "BEGIN", thisseq);
+	  				start = nextf;
+				else
+				{
+	  				printk(KERN_WARNING"isdn_mppp(seq %d):"
+						" END flag with no following "
+						"BEGIN", thisseq);
 					stats->seqerrs++;
 				}
 			}
-		} else {
-			if (nextf != (struct sk_buff *)&mp->frags &&
-			    frag != NULL &&
-			    MP_LT(thisseq, minseq)) {
+
+    		} else {
+			if ( nextf != NULL && frag != NULL &&
+						MP_LT(thisseq, minseq)) {
 				/* we've got a break in the sequence
 				 * and we not at the end yet
 				 * and we did not just reassembled
@@ -1769,39 +1784,41 @@ static void isdn_ppp_mp_receive(isdn_net_dev * net_dev, isdn_net_local * lp,
 			 	 * discard all the frames below low watermark 
 				 * and start over */
 				stats->frame_drops++;
-				isdn_ppp_mp_discard(mp, start, nextf);
+				mp->frags = isdn_ppp_mp_discard(mp,start,nextf);
 			}
 			/* break in the sequence, no reassembly */
-			start = NULL;
-		}
-		if (!start)
-			break;
-	}
+      			start = NULL;
+    		}
+
+    		frag = nextf;
+  	}	/* while -- main loop */
+
+  	if (mp->frags == NULL)
+    		mp->frags = frag;
 
-check_overflow:
 	/* rather straighforward way to deal with (not very) possible 
-	 * queue overflow
-	 */
+	 * queue overflow */
 	if (mp->frames > MP_MAX_QUEUE_LEN) {
 		stats->overflows++;
-		skb_queue_walk_safe(&mp->frags, frag, nextf) {
-			if (mp->frames <= MP_MAX_QUEUE_LEN)
-				break;
-			__skb_unlink(frag, &mp->frags);
-			isdn_ppp_mp_free_skb(mp, frag);
+		while (mp->frames > MP_MAX_QUEUE_LEN) {
+			frag = mp->frags->next;
+			isdn_ppp_mp_free_skb(mp, mp->frags);
+			mp->frags = frag;
 		}
 	}
 	spin_unlock_irqrestore(&mp->lock, flags);
 }
 
-static void isdn_ppp_mp_cleanup(isdn_net_local *lp)
+static void isdn_ppp_mp_cleanup( isdn_net_local * lp )
 {
-	struct sk_buff *skb, *tmp;
-
-	skb_queue_walk_safe(&lp->netdev->pb->frags, skb, tmp) {
-		__skb_unlink(skb, &lp->netdev->pb->frags);
-		isdn_ppp_mp_free_skb(lp->netdev->pb, skb);
-	}
+	struct sk_buff * frag = lp->netdev->pb->frags;
+	struct sk_buff * nextfrag;
+    	while( frag ) {
+		nextfrag = frag->next;
+		isdn_ppp_mp_free_skb(lp->netdev->pb, frag);
+		frag = nextfrag;
+	}
+	lp->netdev->pb->frags = NULL;
 }
 
 static u32 isdn_ppp_mp_get_seq( int short_seq, 
@@ -1838,115 +1855,72 @@ static u32 isdn_ppp_mp_get_seq( int short_seq,
 	return seq;
 }
 
-static void isdn_ppp_mp_discard(ippp_bundle *mp, struct sk_buff *from,
-				struct sk_buff *to)
+struct sk_buff * isdn_ppp_mp_discard( ippp_bundle * mp,
+			struct sk_buff * from, struct sk_buff * to )
 {
-	if (from) {
-		struct sk_buff *skb, *tmp;
-		int freeing = 0;
-
-		skb_queue_walk_safe(&mp->frags, skb, tmp) {
-			if (skb == to)
-				break;
-			if (skb == from)
-				freeing = 1;
-			if (!freeing)
-				continue;
-			__skb_unlink(skb, &mp->frags);
-			isdn_ppp_mp_free_skb(mp, skb);
+	if( from )
+		while (from != to) {
+	  		struct sk_buff * next = from->next;
+			isdn_ppp_mp_free_skb(mp, from);
+	  		from = next;
 		}
-	}
+	return from;
 }
 
-static unsigned int calc_tot_len(struct sk_buff_head *queue,
-				 struct sk_buff *from, struct sk_buff *to)
+void isdn_ppp_mp_reassembly( isdn_net_dev * net_dev, isdn_net_local * lp,
+				struct sk_buff * from, struct sk_buff * to )
 {
-	unsigned int tot_len = 0;
-	struct sk_buff *skb;
-	int found_start = 0;
-
-	skb_queue_walk(queue, skb) {
-		if (skb == from)
-			found_start = 1;
-		if (!found_start)
-			continue;
-		tot_len += skb->len - MP_HEADER_LEN;
-		if (skb == to)
-			break;
-	}
-	return tot_len;
-}
-
-/* Reassemble packet using fragments in the reassembly queue from
- * 'from' until 'to', inclusive.
- */
-static void isdn_ppp_mp_reassembly(isdn_net_dev *net_dev, isdn_net_local *lp,
-				   struct sk_buff *from, struct sk_buff *to,
-				   u32 lastseq)
-{
-	ippp_bundle *mp = net_dev->pb;
-	unsigned int tot_len;
-	struct sk_buff *skb;
+	ippp_bundle * mp = net_dev->pb;
 	int proto;
+	struct sk_buff * skb;
+	unsigned int tot_len;
 
 	if (lp->ppp_slot < 0 || lp->ppp_slot >= ISDN_MAX_CHANNELS) {
 		printk(KERN_ERR "%s: lp->ppp_slot(%d) out of range\n",
 			__func__, lp->ppp_slot);
 		return;
 	}
-
-	tot_len = calc_tot_len(&mp->frags, from, to);
-
-	if (MP_FLAGS(from) == (MP_BEGIN_FRAG | MP_END_FRAG)) {
-		if (ippp_table[lp->ppp_slot]->debug & 0x40)
+	if( MP_FLAGS(from) == (MP_BEGIN_FRAG | MP_END_FRAG) ) {
+		if( ippp_table[lp->ppp_slot]->debug & 0x40 )
 			printk(KERN_DEBUG "isdn_mppp: reassembly: frame %d, "
-			       "len %d\n", MP_SEQ(from), from->len);
+					"len %d\n", MP_SEQ(from), from->len );
 		skb = from;
 		skb_pull(skb, MP_HEADER_LEN);
-		__skb_unlink(skb, &mp->frags);
 		mp->frames--;	
 	} else {
-		struct sk_buff *walk, *tmp;
-		int found_start = 0;
+		struct sk_buff * frag;
+		int n;
 
-		if (ippp_table[lp->ppp_slot]->debug & 0x40)
-			printk(KERN_DEBUG"isdn_mppp: reassembling frames %d "
-			       "to %d, len %d\n", MP_SEQ(from), lastseq,
-			       tot_len);
+		for(tot_len=n=0, frag=from; frag != to; frag=frag->next, n++)
+			tot_len += frag->len - MP_HEADER_LEN;
 
-		skb = dev_alloc_skb(tot_len);
-		if (!skb)
+		if( ippp_table[lp->ppp_slot]->debug & 0x40 )
+			printk(KERN_DEBUG"isdn_mppp: reassembling frames %d "
+				"to %d, len %d\n", MP_SEQ(from),
+				(MP_SEQ(from)+n-1) & MP_LONGSEQ_MASK, tot_len );
+		if( (skb = dev_alloc_skb(tot_len)) == NULL ) {
 			printk(KERN_ERR "isdn_mppp: cannot allocate sk buff "
-			       "of size %d\n", tot_len);
-
-		found_start = 0;
-		skb_queue_walk_safe(&mp->frags, walk, tmp) {
-			if (walk == from)
-				found_start = 1;
-			if (!found_start)
-				continue;
+					"of size %d\n", tot_len);
+			isdn_ppp_mp_discard(mp, from, to);
+			return;
+		}
 
-			if (skb) {
-				unsigned int len = walk->len - MP_HEADER_LEN;
-				skb_copy_from_linear_data_offset(walk, MP_HEADER_LEN,
-								 skb_put(skb, len),
-								 len);
-			}
-			__skb_unlink(walk, &mp->frags);
-			isdn_ppp_mp_free_skb(mp, walk);
+		while( from != to ) {
+			unsigned int len = from->len - MP_HEADER_LEN;
 
-			if (walk == to)
-				break;
+			skb_copy_from_linear_data_offset(from, MP_HEADER_LEN,
+							 skb_put(skb,len),
+							 len);
+			frag = from->next;
+			isdn_ppp_mp_free_skb(mp, from);
+			from = frag;
 		}
 	}
-	if (!skb)
-		return;
-
    	proto = isdn_ppp_strip_proto(skb);
 	isdn_ppp_push_higher(net_dev, lp, skb, proto);
 }
 
-static void isdn_ppp_mp_free_skb(ippp_bundle *mp, struct sk_buff *skb)
+static void isdn_ppp_mp_free_skb(ippp_bundle * mp, struct sk_buff * skb)
 {
 	dev_kfree_skb(skb);
 	mp->frames--;
diff --git a/drivers/macintosh/therm_adt746x.c b/drivers/macintosh/therm_adt746x.c
index fde377c60cca..386a7972111d 100644
--- a/drivers/macintosh/therm_adt746x.c
+++ b/drivers/macintosh/therm_adt746x.c
@@ -79,6 +79,7 @@ struct thermostat {
 	u8			limits[3];
 	int			last_speed[2];
 	int			last_var[2];
+	int			pwm_inv[2];
 };
 
 static enum {ADT7460, ADT7467} therm_type;
@@ -124,6 +125,8 @@ read_reg(struct thermostat* th, int reg)
 	return data;
 }
 
+static struct i2c_driver thermostat_driver;
+
 static int
 attach_thermostat(struct i2c_adapter *adapter)
 {
@@ -148,7 +151,7 @@ attach_thermostat(struct i2c_adapter *adapter)
 	 * Let i2c-core delete that device on driver removal.
 	 * This is safe because i2c-core holds the core_lock mutex for us.
 	 */
-	list_add_tail(&client->detected, &client->driver->clients);
+	list_add_tail(&client->detected, &thermostat_driver.clients);
 	return 0;
 }
 
@@ -227,19 +230,23 @@ static void write_fan_speed(struct thermostat *th, int speed, int fan)
 	
 	if (speed >= 0) {
 		manual = read_reg(th, MANUAL_MODE[fan]);
+		manual &= ~INVERT_MASK;
 		write_reg(th, MANUAL_MODE[fan],
-			(manual|MANUAL_MASK) & (~INVERT_MASK));
+			manual | MANUAL_MASK | th->pwm_inv[fan]);
 		write_reg(th, FAN_SPD_SET[fan], speed);
 	} else {
 		/* back to automatic */
 		if(therm_type == ADT7460) {
 			manual = read_reg(th,
 				MANUAL_MODE[fan]) & (~MANUAL_MASK);
-
+			manual &= ~INVERT_MASK;
+			manual |= th->pwm_inv[fan];
 			write_reg(th,
 				MANUAL_MODE[fan], manual|REM_CONTROL[fan]);
 		} else {
 			manual = read_reg(th, MANUAL_MODE[fan]);
+			manual &= ~INVERT_MASK;
+			manual |= th->pwm_inv[fan];
 			write_reg(th, MANUAL_MODE[fan], manual&(~AUTO_MASK));
 		}
 	}
@@ -416,6 +423,10 @@ static int probe_thermostat(struct i2c_client *client,
 
 	thermostat = th;
 
+	/* record invert bit status because fw can corrupt it after suspend */
+	th->pwm_inv[0] = read_reg(th, MANUAL_MODE[0]) & INVERT_MASK;
+	th->pwm_inv[1] = read_reg(th, MANUAL_MODE[1]) & INVERT_MASK;
+
 	/* be sure to really write fan speed the first time */
 	th->last_speed[0] = -2;
 	th->last_speed[1] = -2;
diff --git a/drivers/macintosh/therm_pm72.c b/drivers/macintosh/therm_pm72.c
index a028598af2d3..ea32c7e5a9af 100644
--- a/drivers/macintosh/therm_pm72.c
+++ b/drivers/macintosh/therm_pm72.c
@@ -286,6 +286,8 @@ struct fcu_fan_table	fcu_fans[] = {
 	},
 };
 
+static struct i2c_driver therm_pm72_driver;
+
 /*
  * Utility function to create an i2c_client structure and
  * attach it to one of u3 adapters
@@ -318,7 +320,7 @@ static struct i2c_client *attach_i2c_chip(int id, const char *name)
 	 * Let i2c-core delete that device on driver removal.
 	 * This is safe because i2c-core holds the core_lock mutex for us.
 	 */
-	list_add_tail(&clt->detected, &clt->driver->clients);
+	list_add_tail(&clt->detected, &therm_pm72_driver.clients);
 	return clt;
 }
 
diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c
index b40fb9b6c862..6f308a4757ee 100644
--- a/drivers/macintosh/via-pmu.c
+++ b/drivers/macintosh/via-pmu.c
@@ -405,7 +405,11 @@ static int __init via_pmu_start(void)
 		printk(KERN_ERR "via-pmu: can't map interrupt\n");
 		return -ENODEV;
 	}
-	if (request_irq(irq, via_pmu_interrupt, 0, "VIA-PMU", (void *)0)) {
+	/* We set IRQF_TIMER because we don't want the interrupt to be disabled
+	 * between the 2 passes of driver suspend, we control our own disabling
+	 * for that one
+	 */
+	if (request_irq(irq, via_pmu_interrupt, IRQF_TIMER, "VIA-PMU", (void *)0)) {
 		printk(KERN_ERR "via-pmu: can't request irq %d\n", irq);
 		return -ENODEV;
 	}
@@ -419,7 +423,7 @@ static int __init via_pmu_start(void)
 			gpio_irq = irq_of_parse_and_map(gpio_node, 0);
 
 		if (gpio_irq != NO_IRQ) {
-			if (request_irq(gpio_irq, gpio1_interrupt, 0,
+			if (request_irq(gpio_irq, gpio1_interrupt, IRQF_TIMER,
 					"GPIO1 ADB", (void *)0))
 				printk(KERN_ERR "pmu: can't get irq %d"
 				       " (GPIO1)\n", gpio_irq);
@@ -925,8 +929,7 @@ proc_write_options(struct file *file, const char __user *buffer,
 
 #ifdef CONFIG_ADB
 /* Send an ADB command */
-static int
-pmu_send_request(struct adb_request *req, int sync)
+static int pmu_send_request(struct adb_request *req, int sync)
 {
 	int i, ret;
 
@@ -1005,16 +1008,11 @@ pmu_send_request(struct adb_request *req, int sync)
 }
 
 /* Enable/disable autopolling */
-static int
-pmu_adb_autopoll(int devs)
+static int __pmu_adb_autopoll(int devs)
 {
 	struct adb_request req;
 
-	if ((vias == NULL) || (!pmu_fully_inited) || !pmu_has_adb)
-		return -ENXIO;
-
 	if (devs) {
-		adb_dev_map = devs;
 		pmu_request(&req, NULL, 5, PMU_ADB_CMD, 0, 0x86,
 			    adb_dev_map >> 8, adb_dev_map);
 		pmu_adb_flags = 2;
@@ -1027,9 +1025,17 @@ pmu_adb_autopoll(int devs)
 	return 0;
 }
 
+static int pmu_adb_autopoll(int devs)
+{
+	if ((vias == NULL) || (!pmu_fully_inited) || !pmu_has_adb)
+		return -ENXIO;
+
+	adb_dev_map = devs;
+	return __pmu_adb_autopoll(devs);
+}
+
 /* Reset the ADB bus */
-static int
-pmu_adb_reset_bus(void)
+static int pmu_adb_reset_bus(void)
 {
 	struct adb_request req;
 	int save_autopoll = adb_dev_map;
@@ -1038,13 +1044,13 @@ pmu_adb_reset_bus(void)
 		return -ENXIO;
 
 	/* anyone got a better idea?? */
-	pmu_adb_autopoll(0);
+	__pmu_adb_autopoll(0);
 
-	req.nbytes = 5;
+	req.nbytes = 4;
 	req.done = NULL;
 	req.data[0] = PMU_ADB_CMD;
-	req.data[1] = 0;
-	req.data[2] = ADB_BUSRESET;
+	req.data[1] = ADB_BUSRESET;
+	req.data[2] = 0;
 	req.data[3] = 0;
 	req.data[4] = 0;
 	req.reply_len = 0;
@@ -1056,7 +1062,7 @@ pmu_adb_reset_bus(void)
 	pmu_wait_complete(&req);
 
 	if (save_autopoll != 0)
-		pmu_adb_autopoll(save_autopoll);
+		__pmu_adb_autopoll(save_autopoll);
 
 	return 0;
 }
diff --git a/drivers/macintosh/windfarm_lm75_sensor.c b/drivers/macintosh/windfarm_lm75_sensor.c
index 529886c7a826..ed6426a10773 100644
--- a/drivers/macintosh/windfarm_lm75_sensor.c
+++ b/drivers/macintosh/windfarm_lm75_sensor.c
@@ -115,6 +115,8 @@ static int wf_lm75_probe(struct i2c_client *client,
 	return rc;
 }
 
+static struct i2c_driver wf_lm75_driver;
+
 static struct i2c_client *wf_lm75_create(struct i2c_adapter *adapter,
 					     u8 addr, int ds1775,
 					     const char *loc)
@@ -157,7 +159,7 @@ static struct i2c_client *wf_lm75_create(struct i2c_adapter *adapter,
 	 * Let i2c-core delete that device on driver removal.
 	 * This is safe because i2c-core holds the core_lock mutex for us.
 	 */
-	list_add_tail(&client->detected, &client->driver->clients);
+	list_add_tail(&client->detected, &wf_lm75_driver.clients);
 	return client;
  fail:
 	return NULL;
diff --git a/drivers/macintosh/windfarm_max6690_sensor.c b/drivers/macintosh/windfarm_max6690_sensor.c
index e2a55ecda2b2..a67b349319e9 100644
--- a/drivers/macintosh/windfarm_max6690_sensor.c
+++ b/drivers/macintosh/windfarm_max6690_sensor.c
@@ -88,6 +88,8 @@ static int wf_max6690_probe(struct i2c_client *client,
 	return rc;
 }
 
+static struct i2c_driver wf_max6690_driver;
+
 static struct i2c_client *wf_max6690_create(struct i2c_adapter *adapter,
 					    u8 addr, const char *loc)
 {
@@ -119,7 +121,7 @@ static struct i2c_client *wf_max6690_create(struct i2c_adapter *adapter,
 	 * Let i2c-core delete that device on driver removal.
 	 * This is safe because i2c-core holds the core_lock mutex for us.
 	 */
-	list_add_tail(&client->detected, &client->driver->clients);
+	list_add_tail(&client->detected, &wf_max6690_driver.clients);
 	return client;
 
  fail:
diff --git a/drivers/macintosh/windfarm_smu_sat.c b/drivers/macintosh/windfarm_smu_sat.c
index 5da729e58f99..e20330a28959 100644
--- a/drivers/macintosh/windfarm_smu_sat.c
+++ b/drivers/macintosh/windfarm_smu_sat.c
@@ -194,6 +194,8 @@ static struct wf_sensor_ops wf_sat_ops = {
 	.owner		= THIS_MODULE,
 };
 
+static struct i2c_driver wf_sat_driver;
+
 static void wf_sat_create(struct i2c_adapter *adapter, struct device_node *dev)
 {
 	struct i2c_board_info info;
@@ -222,7 +224,7 @@ static void wf_sat_create(struct i2c_adapter *adapter, struct device_node *dev)
 	 * Let i2c-core delete that device on driver removal.
 	 * This is safe because i2c-core holds the core_lock mutex for us.
 	 */
-	list_add_tail(&client->detected, &client->driver->clients);
+	list_add_tail(&client->detected, &wf_sat_driver.clients);
 }
 
 static int wf_sat_probe(struct i2c_client *client,
diff --git a/drivers/md/bitmap.c b/drivers/md/bitmap.c
index 3319c2fec28e..0aee97a30b80 100644
--- a/drivers/md/bitmap.c
+++ b/drivers/md/bitmap.c
@@ -1077,23 +1077,31 @@ static bitmap_counter_t *bitmap_get_counter(struct bitmap *bitmap,
  *			out to disk
  */
 
-void bitmap_daemon_work(struct bitmap *bitmap)
+void bitmap_daemon_work(mddev_t *mddev)
 {
+	struct bitmap *bitmap;
 	unsigned long j;
 	unsigned long flags;
 	struct page *page = NULL, *lastpage = NULL;
 	int blocks;
 	void *paddr;
 
-	if (bitmap == NULL)
+	/* Use a mutex to guard daemon_work against
+	 * bitmap_destroy.
+	 */
+	mutex_lock(&mddev->bitmap_mutex);
+	bitmap = mddev->bitmap;
+	if (bitmap == NULL) {
+		mutex_unlock(&mddev->bitmap_mutex);
 		return;
+	}
 	if (time_before(jiffies, bitmap->daemon_lastrun + bitmap->daemon_sleep*HZ))
 		goto done;
 
 	bitmap->daemon_lastrun = jiffies;
 	if (bitmap->allclean) {
 		bitmap->mddev->thread->timeout = MAX_SCHEDULE_TIMEOUT;
-		return;
+		goto done;
 	}
 	bitmap->allclean = 1;
 
@@ -1202,6 +1210,7 @@ void bitmap_daemon_work(struct bitmap *bitmap)
  done:
 	if (bitmap->allclean == 0)
 		bitmap->mddev->thread->timeout = bitmap->daemon_sleep * HZ;
+	mutex_unlock(&mddev->bitmap_mutex);
 }
 
 static bitmap_counter_t *bitmap_get_counter(struct bitmap *bitmap,
@@ -1538,9 +1547,9 @@ void bitmap_flush(mddev_t *mddev)
 	 */
 	sleep = bitmap->daemon_sleep;
 	bitmap->daemon_sleep = 0;
-	bitmap_daemon_work(bitmap);
-	bitmap_daemon_work(bitmap);
-	bitmap_daemon_work(bitmap);
+	bitmap_daemon_work(mddev);
+	bitmap_daemon_work(mddev);
+	bitmap_daemon_work(mddev);
 	bitmap->daemon_sleep = sleep;
 	bitmap_update_sb(bitmap);
 }
@@ -1571,6 +1580,7 @@ static void bitmap_free(struct bitmap *bitmap)
 	kfree(bp);
 	kfree(bitmap);
 }
+
 void bitmap_destroy(mddev_t *mddev)
 {
 	struct bitmap *bitmap = mddev->bitmap;
@@ -1578,7 +1588,9 @@ void bitmap_destroy(mddev_t *mddev)
 	if (!bitmap) /* there was no bitmap */
 		return;
 
+	mutex_lock(&mddev->bitmap_mutex);
 	mddev->bitmap = NULL; /* disconnect from the md device */
+	mutex_unlock(&mddev->bitmap_mutex);
 	if (mddev->thread)
 		mddev->thread->timeout = MAX_SCHEDULE_TIMEOUT;
 
diff --git a/drivers/md/bitmap.h b/drivers/md/bitmap.h
index e98900671ca9..7e38d13ddcac 100644
--- a/drivers/md/bitmap.h
+++ b/drivers/md/bitmap.h
@@ -282,7 +282,7 @@ void bitmap_close_sync(struct bitmap *bitmap);
 void bitmap_cond_end_sync(struct bitmap *bitmap, sector_t sector);
 
 void bitmap_unplug(struct bitmap *bitmap);
-void bitmap_daemon_work(struct bitmap *bitmap);
+void bitmap_daemon_work(mddev_t *mddev);
 #endif
 
 #endif
diff --git a/drivers/md/dm-exception-store.c b/drivers/md/dm-exception-store.c
index 556acff3952f..932d1b123143 100644
--- a/drivers/md/dm-exception-store.c
+++ b/drivers/md/dm-exception-store.c
@@ -155,7 +155,8 @@ static int set_chunk_size(struct dm_exception_store *store,
 	char *value;
 
 	chunk_size_ulong = simple_strtoul(chunk_size_arg, &value, 10);
-	if (*chunk_size_arg == '\0' || *value != '\0') {
+	if (*chunk_size_arg == '\0' || *value != '\0' ||
+	    chunk_size_ulong > UINT_MAX) {
 		*error = "Invalid chunk size";
 		return -EINVAL;
 	}
@@ -171,34 +172,35 @@ static int set_chunk_size(struct dm_exception_store *store,
 	 */
 	chunk_size_ulong = round_up(chunk_size_ulong, PAGE_SIZE >> 9);
 
-	return dm_exception_store_set_chunk_size(store, chunk_size_ulong,
+	return dm_exception_store_set_chunk_size(store,
+						 (unsigned) chunk_size_ulong,
 						 error);
 }
 
 int dm_exception_store_set_chunk_size(struct dm_exception_store *store,
-				      unsigned long chunk_size_ulong,
+				      unsigned chunk_size,
 				      char **error)
 {
 	/* Check chunk_size is a power of 2 */
-	if (!is_power_of_2(chunk_size_ulong)) {
+	if (!is_power_of_2(chunk_size)) {
 		*error = "Chunk size is not a power of 2";
 		return -EINVAL;
 	}
 
 	/* Validate the chunk size against the device block size */
-	if (chunk_size_ulong % (bdev_logical_block_size(store->cow->bdev) >> 9)) {
+	if (chunk_size % (bdev_logical_block_size(store->cow->bdev) >> 9)) {
 		*error = "Chunk size is not a multiple of device blocksize";
 		return -EINVAL;
 	}
 
-	if (chunk_size_ulong > INT_MAX >> SECTOR_SHIFT) {
+	if (chunk_size > INT_MAX >> SECTOR_SHIFT) {
 		*error = "Chunk size is too high";
 		return -EINVAL;
 	}
 
-	store->chunk_size = chunk_size_ulong;
-	store->chunk_mask = chunk_size_ulong - 1;
-	store->chunk_shift = ffs(chunk_size_ulong) - 1;
+	store->chunk_size = chunk_size;
+	store->chunk_mask = chunk_size - 1;
+	store->chunk_shift = ffs(chunk_size) - 1;
 
 	return 0;
 }
@@ -251,7 +253,7 @@ int dm_exception_store_create(struct dm_target *ti, int argc, char **argv,
 
 	r = set_chunk_size(tmp_store, argv[2], &ti->error);
 	if (r)
-		goto bad_cow;
+		goto bad_ctr;
 
 	r = type->ctr(tmp_store, 0, NULL);
 	if (r) {
diff --git a/drivers/md/dm-exception-store.h b/drivers/md/dm-exception-store.h
index 812c71872ba0..8a223a48802c 100644
--- a/drivers/md/dm-exception-store.h
+++ b/drivers/md/dm-exception-store.h
@@ -101,9 +101,9 @@ struct dm_exception_store {
 	struct dm_dev *cow;
 
 	/* Size of data blocks saved - must be a power of 2 */
-	chunk_t chunk_size;
-	chunk_t chunk_mask;
-	chunk_t chunk_shift;
+	unsigned chunk_size;
+	unsigned chunk_mask;
+	unsigned chunk_shift;
 
 	void *context;
 };
@@ -169,7 +169,7 @@ int dm_exception_store_type_register(struct dm_exception_store_type *type);
 int dm_exception_store_type_unregister(struct dm_exception_store_type *type);
 
 int dm_exception_store_set_chunk_size(struct dm_exception_store *store,
-				      unsigned long chunk_size_ulong,
+				      unsigned chunk_size,
 				      char **error);
 
 int dm_exception_store_create(struct dm_target *ti, int argc, char **argv,
diff --git a/drivers/md/dm-log-userspace-base.c b/drivers/md/dm-log-userspace-base.c
index 6e186b1a062d..7ac2c1450d10 100644
--- a/drivers/md/dm-log-userspace-base.c
+++ b/drivers/md/dm-log-userspace-base.c
@@ -156,7 +156,7 @@ static int userspace_ctr(struct dm_dirty_log *log, struct dm_target *ti,
 	}
 
 	/* The ptr value is sufficient for local unique id */
-	lc->luid = (uint64_t)lc;
+	lc->luid = (unsigned long)lc;
 
 	lc->ti = ti;
 
@@ -582,7 +582,7 @@ static int userspace_status(struct dm_dirty_log *log, status_type_t status_type,
 		break;
 	case STATUSTYPE_TABLE:
 		sz = 0;
-		table_args = strstr(lc->usr_argv_str, " ");
+		table_args = strchr(lc->usr_argv_str, ' ');
 		BUG_ON(!table_args); /* There will always be a ' ' */
 		table_args++;
 
diff --git a/drivers/md/dm-log-userspace-transfer.c b/drivers/md/dm-log-userspace-transfer.c
index ba0edad2d048..54abf9e303b7 100644
--- a/drivers/md/dm-log-userspace-transfer.c
+++ b/drivers/md/dm-log-userspace-transfer.c
@@ -129,11 +129,13 @@ static int fill_pkg(struct cn_msg *msg, struct dm_ulog_request *tfr)
  * This is the connector callback that delivers data
  * that was sent from userspace.
  */
-static void cn_ulog_callback(void *data)
+static void cn_ulog_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp)
 {
-	struct cn_msg *msg = (struct cn_msg *)data;
 	struct dm_ulog_request *tfr = (struct dm_ulog_request *)(msg + 1);
 
+	if (!cap_raised(nsp->eff_cap, CAP_SYS_ADMIN))
+		return;
+
 	spin_lock(&receiving_list_lock);
 	if (msg->len == 0)
 		fill_pkg(msg, NULL);
diff --git a/drivers/md/dm-snap-persistent.c b/drivers/md/dm-snap-persistent.c
index d5b2e08750d5..0c746420c008 100644
--- a/drivers/md/dm-snap-persistent.c
+++ b/drivers/md/dm-snap-persistent.c
@@ -284,12 +284,13 @@ static int read_header(struct pstore *ps, int *new_snapshot)
 {
 	int r;
 	struct disk_header *dh;
-	chunk_t chunk_size;
+	unsigned chunk_size;
 	int chunk_size_supplied = 1;
 	char *chunk_err;
 
 	/*
-	 * Use default chunk size (or hardsect_size, if larger) if none supplied
+	 * Use default chunk size (or logical_block_size, if larger)
+	 * if none supplied
 	 */
 	if (!ps->store->chunk_size) {
 		ps->store->chunk_size = max(DM_CHUNK_SIZE_DEFAULT_SECTORS,
@@ -334,10 +335,9 @@ static int read_header(struct pstore *ps, int *new_snapshot)
 		return 0;
 
 	if (chunk_size_supplied)
-		DMWARN("chunk size %llu in device metadata overrides "
-		       "table chunk size of %llu.",
-		       (unsigned long long)chunk_size,
-		       (unsigned long long)ps->store->chunk_size);
+		DMWARN("chunk size %u in device metadata overrides "
+		       "table chunk size of %u.",
+		       chunk_size, ps->store->chunk_size);
 
 	/* We had a bogus chunk_size. Fix stuff up. */
 	free_area(ps);
@@ -345,8 +345,8 @@ static int read_header(struct pstore *ps, int *new_snapshot)
 	r = dm_exception_store_set_chunk_size(ps->store, chunk_size,
 					      &chunk_err);
 	if (r) {
-		DMERR("invalid on-disk chunk size %llu: %s.",
-		      (unsigned long long)chunk_size, chunk_err);
+		DMERR("invalid on-disk chunk size %u: %s.",
+		      chunk_size, chunk_err);
 		return r;
 	}
 
diff --git a/drivers/md/dm-snap.c b/drivers/md/dm-snap.c
index 57f1bf7f3b7a..3a3ba46e6d4b 100644
--- a/drivers/md/dm-snap.c
+++ b/drivers/md/dm-snap.c
@@ -296,6 +296,7 @@ static void __insert_origin(struct origin *o)
  */
 static int register_snapshot(struct dm_snapshot *snap)
 {
+	struct dm_snapshot *l;
 	struct origin *o, *new_o;
 	struct block_device *bdev = snap->origin->bdev;
 
@@ -319,7 +320,11 @@ static int register_snapshot(struct dm_snapshot *snap)
 		__insert_origin(o);
 	}
 
-	list_add_tail(&snap->list, &o->snapshots);
+	/* Sort the list according to chunk size, largest-first smallest-last */
+	list_for_each_entry(l, &o->snapshots, list)
+		if (l->store->chunk_size < snap->store->chunk_size)
+			break;
+	list_add_tail(&snap->list, &l->list);
 
 	up_write(&_origins_lock);
 	return 0;
@@ -668,6 +673,11 @@ static int snapshot_ctr(struct dm_target *ti, unsigned int argc, char **argv)
 	bio_list_init(&s->queued_bios);
 	INIT_WORK(&s->queued_bios_work, flush_queued_bios);
 
+	if (!s->store->chunk_size) {
+		ti->error = "Chunk size not set";
+		goto bad_load_and_register;
+	}
+
 	/* Add snapshot to the list of snapshots for this origin */
 	/* Exceptions aren't triggered till snapshot_resume() is called */
 	if (register_snapshot(s)) {
@@ -951,7 +961,7 @@ static void start_copy(struct dm_snap_pending_exception *pe)
 
 	src.bdev = bdev;
 	src.sector = chunk_to_sector(s->store, pe->e.old_chunk);
-	src.count = min(s->store->chunk_size, dev_size - src.sector);
+	src.count = min((sector_t)s->store->chunk_size, dev_size - src.sector);
 
 	dest.bdev = s->store->cow->bdev;
 	dest.sector = chunk_to_sector(s->store, pe->e.new_chunk);
@@ -1142,6 +1152,8 @@ static int snapshot_status(struct dm_target *ti, status_type_t type,
 	unsigned sz = 0;
 	struct dm_snapshot *snap = ti->private;
 
+	down_write(&snap->lock);
+
 	switch (type) {
 	case STATUSTYPE_INFO:
 		if (!snap->valid)
@@ -1173,6 +1185,8 @@ static int snapshot_status(struct dm_target *ti, status_type_t type,
 		break;
 	}
 
+	up_write(&snap->lock);
+
 	return 0;
 }
 
@@ -1388,7 +1402,7 @@ static void origin_resume(struct dm_target *ti)
 	struct dm_dev *dev = ti->private;
 	struct dm_snapshot *snap;
 	struct origin *o;
-	chunk_t chunk_size = 0;
+	unsigned chunk_size = 0;
 
 	down_read(&_origins_lock);
 	o = __lookup_origin(dev->bdev);
@@ -1465,7 +1479,7 @@ static int __init dm_snapshot_init(void)
 	r = dm_register_target(&snapshot_target);
 	if (r) {
 		DMERR("snapshot target register failed %d", r);
-		return r;
+		goto bad_register_snapshot_target;
 	}
 
 	r = dm_register_target(&origin_target);
@@ -1522,6 +1536,9 @@ bad2:
 	dm_unregister_target(&origin_target);
 bad1:
 	dm_unregister_target(&snapshot_target);
+
+bad_register_snapshot_target:
+	dm_exception_store_exit();
 	return r;
 }
 
diff --git a/drivers/md/dm.c b/drivers/md/dm.c
index b4845b14740d..ae087b0c49f9 100644
--- a/drivers/md/dm.c
+++ b/drivers/md/dm.c
@@ -47,6 +47,7 @@ struct dm_io {
 	atomic_t io_count;
 	struct bio *bio;
 	unsigned long start_time;
+	spinlock_t endio_lock;
 };
 
 /*
@@ -576,8 +577,12 @@ static void dec_pending(struct dm_io *io, int error)
 	struct mapped_device *md = io->md;
 
 	/* Push-back supersedes any I/O errors */
-	if (error && !(io->error > 0 && __noflush_suspending(md)))
-		io->error = error;
+	if (unlikely(error)) {
+		spin_lock_irqsave(&io->endio_lock, flags);
+		if (!(io->error > 0 && __noflush_suspending(md)))
+			io->error = error;
+		spin_unlock_irqrestore(&io->endio_lock, flags);
+	}
 
 	if (atomic_dec_and_test(&io->io_count)) {
 		if (io->error == DM_ENDIO_REQUEUE) {
@@ -1224,6 +1229,7 @@ static void __split_and_process_bio(struct mapped_device *md, struct bio *bio)
 	atomic_set(&ci.io->io_count, 1);
 	ci.io->bio = bio;
 	ci.io->md = md;
+	spin_lock_init(&ci.io->endio_lock);
 	ci.sector = bio->bi_sector;
 	ci.sector_count = bio_sectors(bio);
 	if (unlikely(bio_empty_barrier(bio)))
@@ -1819,6 +1825,7 @@ static struct mapped_device *alloc_dev(int minor)
 bad_bdev:
 	destroy_workqueue(md->wq);
 bad_thread:
+	del_gendisk(md->disk);
 	put_disk(md->disk);
 bad_disk:
 	blk_cleanup_queue(md->queue);
diff --git a/drivers/md/md.c b/drivers/md/md.c
index 9dd872000cec..2938e9ca711e 100644
--- a/drivers/md/md.c
+++ b/drivers/md/md.c
@@ -276,7 +276,9 @@ static void mddev_put(mddev_t *mddev)
 	if (!atomic_dec_and_lock(&mddev->active, &all_mddevs_lock))
 		return;
 	if (!mddev->raid_disks && list_empty(&mddev->disks) &&
-	    !mddev->hold_active) {
+	    mddev->ctime == 0 && !mddev->hold_active) {
+		/* Array is not configured at all, and not held active,
+		 * so destroy it */
 		list_del(&mddev->all_mddevs);
 		if (mddev->gendisk) {
 			/* we did a probe so need to clean up.
@@ -361,6 +363,7 @@ static mddev_t * mddev_find(dev_t unit)
 
 	mutex_init(&new->open_mutex);
 	mutex_init(&new->reconfig_mutex);
+	mutex_init(&new->bitmap_mutex);
 	INIT_LIST_HEAD(&new->disks);
 	INIT_LIST_HEAD(&new->all_mddevs);
 	init_timer(&new->safemode_timer);
@@ -5039,6 +5042,10 @@ static int set_array_info(mddev_t * mddev, mdu_array_info_t *info)
 		mddev->minor_version = info->minor_version;
 		mddev->patch_version = info->patch_version;
 		mddev->persistent = !info->not_persistent;
+		/* ensure mddev_put doesn't delete this now that there
+		 * is some minimal configuration.
+		 */
+		mddev->ctime         = get_seconds();
 		return 0;
 	}
 	mddev->major_version = MD_MAJOR_VERSION;
@@ -6495,8 +6502,9 @@ void md_do_sync(mddev_t *mddev)
  skip:
 	mddev->curr_resync = 0;
 	mddev->curr_resync_completed = 0;
-	mddev->resync_min = 0;
-	mddev->resync_max = MaxSector;
+	if (!test_bit(MD_RECOVERY_INTR, &mddev->recovery))
+		/* We completed so max setting can be forgotten. */
+		mddev->resync_max = MaxSector;
 	sysfs_notify(&mddev->kobj, NULL, "sync_completed");
 	wake_up(&resync_wait);
 	set_bit(MD_RECOVERY_DONE, &mddev->recovery);
@@ -6594,7 +6602,7 @@ void md_check_recovery(mddev_t *mddev)
 
 
 	if (mddev->bitmap)
-		bitmap_daemon_work(mddev->bitmap);
+		bitmap_daemon_work(mddev);
 
 	if (mddev->ro)
 		return;
diff --git a/drivers/md/md.h b/drivers/md/md.h
index f8fc188bc762..d7aad830018e 100644
--- a/drivers/md/md.h
+++ b/drivers/md/md.h
@@ -289,6 +289,7 @@ struct mddev_s
 								* hot-adding a bitmap.  It should
 								* eventually be settable by sysfs.
 								*/
+	struct mutex			bitmap_mutex;
 
 	struct list_head		all_mddevs;
 };
diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c
index 8726fd7ebce5..d3e492e8781c 100644
--- a/drivers/md/raid1.c
+++ b/drivers/md/raid1.c
@@ -1643,11 +1643,12 @@ static void raid1d(mddev_t *mddev)
 					       r1_bio->sector,
 					       r1_bio->sectors);
 				unfreeze_array(conf);
-			}
+			} else
+				md_error(mddev,
+					 conf->mirrors[r1_bio->read_disk].rdev);
 
 			bio = r1_bio->bios[r1_bio->read_disk];
-			if ((disk=read_balance(conf, r1_bio)) == -1 ||
-			    disk == r1_bio->read_disk) {
+			if ((disk=read_balance(conf, r1_bio)) == -1) {
 				printk(KERN_ALERT "raid1: %s: unrecoverable I/O"
 				       " read error for block %llu\n",
 				       bdevname(bio->bi_bdev,b),
@@ -1676,6 +1677,7 @@ static void raid1d(mddev_t *mddev)
 				generic_make_request(bio);
 			}
 		}
+		cond_resched();
 	}
 	if (unplug)
 		unplug_slaves(mddev);
diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c
index 3d9020cf6f6e..6a5a5fb18b30 100644
--- a/drivers/md/raid10.c
+++ b/drivers/md/raid10.c
@@ -1630,6 +1630,7 @@ static void raid10d(mddev_t *mddev)
 				generic_make_request(bio);
 			}
 		}
+		cond_resched();
 	}
 	if (unplug)
 		unplug_slaves(mddev);
diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
index b8a2c5dc67ba..c339c8fdcbd5 100644
--- a/drivers/md/raid5.c
+++ b/drivers/md/raid5.c
@@ -3790,6 +3790,8 @@ static sector_t reshape_request(mddev_t *mddev, sector_t sector_nr, int *skipped
 			sector_nr = conf->reshape_progress;
 		sector_div(sector_nr, new_data_disks);
 		if (sector_nr) {
+			mddev->curr_resync_completed = sector_nr;
+			sysfs_notify(&mddev->kobj, NULL, "sync_completed");
 			*skipped = 1;
 			return sector_nr;
 		}
diff --git a/drivers/media/common/tuners/mxl5007t.c b/drivers/media/common/tuners/mxl5007t.c
index 2d02698d4f4f..7eb1bf75cd07 100644
--- a/drivers/media/common/tuners/mxl5007t.c
+++ b/drivers/media/common/tuners/mxl5007t.c
@@ -196,7 +196,7 @@ static void copy_reg_bits(struct reg_pair_t *reg_pair1,
 	i = j = 0;
 
 	while (reg_pair1[i].reg || reg_pair1[i].val) {
-		while (reg_pair2[j].reg || reg_pair2[j].reg) {
+		while (reg_pair2[j].reg || reg_pair2[j].val) {
 			if (reg_pair1[i].reg != reg_pair2[j].reg) {
 				j++;
 				continue;
diff --git a/drivers/media/common/tuners/tda18271-fe.c b/drivers/media/common/tuners/tda18271-fe.c
index b10935630154..f446f9a18ef1 100644
--- a/drivers/media/common/tuners/tda18271-fe.c
+++ b/drivers/media/common/tuners/tda18271-fe.c
@@ -595,13 +595,13 @@ static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq)
 		case RF2:
 			map[i].rf_a1 = (prog_cal[RF2] - prog_tab[RF2] -
 					prog_cal[RF1] + prog_tab[RF1]) /
-				((rf_freq[RF2] - rf_freq[RF1]) / 1000);
+				(s32)((rf_freq[RF2] - rf_freq[RF1]) / 1000);
 			map[i].rf2   = rf_freq[RF2] / 1000;
 			break;
 		case RF3:
 			map[i].rf_a2 = (prog_cal[RF3] - prog_tab[RF3] -
 					prog_cal[RF2] + prog_tab[RF2]) /
-				((rf_freq[RF3] - rf_freq[RF2]) / 1000);
+				(s32)((rf_freq[RF3] - rf_freq[RF2]) / 1000);
 			map[i].rf_b2 = prog_cal[RF2] - prog_tab[RF2];
 			map[i].rf3   = rf_freq[RF3] / 1000;
 			break;
@@ -963,12 +963,12 @@ static int tda18271_set_analog_params(struct dvb_frontend *fe,
 	struct tda18271_std_map_item *map;
 	char *mode;
 	int ret;
-	u32 freq = params->frequency * 62500;
+	u32 freq = params->frequency * 125 *
+		((params->mode == V4L2_TUNER_RADIO) ? 1 : 1000) / 2;
 
 	priv->mode = TDA18271_ANALOG;
 
 	if (params->mode == V4L2_TUNER_RADIO) {
-		freq = freq / 1000;
 		map = &std_map->fm_radio;
 		mode = "fm";
 	} else if (params->std & V4L2_STD_MN) {
diff --git a/drivers/media/dvb/dvb-usb/af9015.c b/drivers/media/dvb/dvb-usb/af9015.c
index 26690dfb3260..4d0c8d56047c 100644
--- a/drivers/media/dvb/dvb-usb/af9015.c
+++ b/drivers/media/dvb/dvb-usb/af9015.c
@@ -1266,6 +1266,7 @@ static struct usb_device_id af9015_usb_table[] = {
 	{USB_DEVICE(USB_VID_KWORLD_2,  USB_PID_CONCEPTRONIC_CTVDIGRCU)},
 	{USB_DEVICE(USB_VID_KWORLD_2,  USB_PID_KWORLD_MC810)},
 	{USB_DEVICE(USB_VID_KYE,       USB_PID_GENIUS_TVGO_DVB_T03)},
+/* 25 */{USB_DEVICE(USB_VID_KWORLD_2,  USB_PID_KWORLD_399U_2)},
 	{0},
 };
 MODULE_DEVICE_TABLE(usb, af9015_usb_table);
@@ -1346,7 +1347,8 @@ static struct dvb_usb_device_properties af9015_properties[] = {
 			{
 				.name = "KWorld PlusTV Dual DVB-T Stick " \
 					"(DVB-T 399U)",
-				.cold_ids = {&af9015_usb_table[4], NULL},
+				.cold_ids = {&af9015_usb_table[4],
+					     &af9015_usb_table[25], NULL},
 				.warm_ids = {NULL},
 			},
 			{
diff --git a/drivers/media/dvb/dvb-usb/cxusb.c b/drivers/media/dvb/dvb-usb/cxusb.c
index 406d7fba369d..f32b332ba76d 100644
--- a/drivers/media/dvb/dvb-usb/cxusb.c
+++ b/drivers/media/dvb/dvb-usb/cxusb.c
@@ -663,6 +663,14 @@ static struct zl10353_config cxusb_zl10353_xc3028_config = {
 	.parallel_ts = 1,
 };
 
+static struct zl10353_config cxusb_zl10353_xc3028_config_no_i2c_gate = {
+	.demod_address = 0x0f,
+	.if2 = 45600,
+	.no_tuner = 1,
+	.parallel_ts = 1,
+	.disable_i2c_gate_ctrl = 1,
+};
+
 static struct mt352_config cxusb_mt352_xc3028_config = {
 	.demod_address = 0x0f,
 	.if2 = 4560,
@@ -894,7 +902,7 @@ static int cxusb_dualdig4_frontend_attach(struct dvb_usb_adapter *adap)
 	cxusb_bluebird_gpio_pulse(adap->dev, 0x02, 1);
 
 	if ((adap->fe = dvb_attach(zl10353_attach,
-				   &cxusb_zl10353_xc3028_config,
+				   &cxusb_zl10353_xc3028_config_no_i2c_gate,
 				   &adap->dev->i2c_adap)) == NULL)
 		return -EIO;
 
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
index 9593b7289994..5ace1312c34c 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
+++ b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
@@ -103,6 +103,7 @@
 #define USB_PID_GRANDTEC_DVBT_USB_WARM			0x0fa1
 #define USB_PID_INTEL_CE9500				0x9500
 #define USB_PID_KWORLD_399U				0xe399
+#define USB_PID_KWORLD_399U_2				0xe400
 #define USB_PID_KWORLD_395U				0xe396
 #define USB_PID_KWORLD_395U_2				0xe39b
 #define USB_PID_KWORLD_395U_3				0xe395
diff --git a/drivers/media/dvb/frontends/dib7000p.c b/drivers/media/dvb/frontends/dib7000p.c
index 8217e5b38f47..ac10fff61f3c 100644
--- a/drivers/media/dvb/frontends/dib7000p.c
+++ b/drivers/media/dvb/frontends/dib7000p.c
@@ -1344,6 +1344,11 @@ struct dvb_frontend * dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr,
 	if (dib7000p_identify(st) != 0)
 		goto error;
 
+	/* FIXME: make sure the dev.parent field is initialized, or else
+	request_firmware() will hit an OOPS (this should be moved somewhere
+	more common) */
+	st->i2c_master.gated_tuner_i2c_adap.dev.parent = i2c_adap->dev.parent;
+
 	dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr);
 
 	dib7000p_demod_reset(st);
diff --git a/drivers/media/dvb/siano/smsusb.c b/drivers/media/dvb/siano/smsusb.c
index cb8a358b7310..8f88a586b0dd 100644
--- a/drivers/media/dvb/siano/smsusb.c
+++ b/drivers/media/dvb/siano/smsusb.c
@@ -529,6 +529,12 @@ struct usb_device_id smsusb_id_table[] = {
 		.driver_info = SMS1XXX_BOARD_SIANO_NICE },
 	{ USB_DEVICE(0x187f, 0x0301),
 		.driver_info = SMS1XXX_BOARD_SIANO_VENICE },
+	{ USB_DEVICE(0x2040, 0xb900),
+		.driver_info = SMS1XXX_BOARD_HAUPPAUGE_WINDHAM },
+	{ USB_DEVICE(0x2040, 0xb910),
+		.driver_info = SMS1XXX_BOARD_HAUPPAUGE_WINDHAM },
+	{ USB_DEVICE(0x2040, 0xc000),
+		.driver_info = SMS1XXX_BOARD_HAUPPAUGE_WINDHAM },
 	{ } /* Terminating entry */
 	};
 
diff --git a/drivers/media/radio/radio-gemtek-pci.c b/drivers/media/radio/radio-gemtek-pci.c
index c3f579de6e71..c6cf11661868 100644
--- a/drivers/media/radio/radio-gemtek-pci.c
+++ b/drivers/media/radio/radio-gemtek-pci.c
@@ -181,12 +181,10 @@ static void gemtek_pci_mute(struct gemtek_pci *card)
 
 static void gemtek_pci_unmute(struct gemtek_pci *card)
 {
-	mutex_lock(&card->lock);
 	if (card->mute) {
 		gemtek_pci_setfrequency(card, card->current_frequency);
 		card->mute = false;
 	}
-	mutex_unlock(&card->lock);
 }
 
 static int gemtek_pci_getsignal(struct gemtek_pci *card)
diff --git a/drivers/media/video/bt8xx/bttv-driver.c b/drivers/media/video/bt8xx/bttv-driver.c
index 8cc6dd28d6a7..b8e276c88353 100644
--- a/drivers/media/video/bt8xx/bttv-driver.c
+++ b/drivers/media/video/bt8xx/bttv-driver.c
@@ -1299,7 +1299,7 @@ set_tvnorm(struct bttv *btv, unsigned int norm)
 
 	tvnorm = &bttv_tvnorms[norm];
 
-	if (!memcmp(&bttv_tvnorms[btv->tvnorm].cropcap, &tvnorm->cropcap,
+	if (memcmp(&bttv_tvnorms[btv->tvnorm].cropcap, &tvnorm->cropcap,
 		    sizeof (tvnorm->cropcap))) {
 		bttv_crop_reset(&btv->crop[0], norm);
 		btv->crop[1] = btv->crop[0]; /* current = default */
@@ -3798,11 +3798,34 @@ bttv_irq_next_video(struct bttv *btv, struct bttv_buffer_set *set)
 		if (!V4L2_FIELD_HAS_BOTH(item->vb.field) &&
 		    (item->vb.queue.next != &btv->capture)) {
 			item = list_entry(item->vb.queue.next, struct bttv_buffer, vb.queue);
+			/* Mike Isely <isely@pobox.com> - Only check
+			 * and set up the bottom field in the logic
+			 * below.  Don't ever do the top field.  This
+			 * of course means that if we set up the
+			 * bottom field in the above code that we'll
+			 * actually skip a field.  But that's OK.
+			 * Having processed only a single buffer this
+			 * time, then the next time around the first
+			 * available buffer should be for a top field.
+			 * That will then cause us here to set up a
+			 * top then a bottom field in the normal way.
+			 * The alternative to this understanding is
+			 * that we set up the second available buffer
+			 * as a top field, but that's out of order
+			 * since this driver always processes the top
+			 * field first - the effect will be the two
+			 * buffers being returned in the wrong order,
+			 * with the second buffer also being delayed
+			 * by one field time (owing to the fifo nature
+			 * of videobuf).  Worse still, we'll be stuck
+			 * doing fields out of order now every time
+			 * until something else causes a field to be
+			 * dropped.  By effectively forcing a field to
+			 * drop this way then we always get back into
+			 * sync within a single frame time.  (Out of
+			 * order fields can screw up deinterlacing
+			 * algorithms.) */
 			if (!V4L2_FIELD_HAS_BOTH(item->vb.field)) {
-				if (NULL == set->top &&
-				    V4L2_FIELD_TOP == item->vb.field) {
-					set->top = item;
-				}
 				if (NULL == set->bottom &&
 				    V4L2_FIELD_BOTTOM == item->vb.field) {
 					set->bottom = item;
diff --git a/drivers/media/video/em28xx/em28xx-audio.c b/drivers/media/video/em28xx/em28xx-audio.c
index 7bd8a70f0a0b..ac947aecb9c3 100644
--- a/drivers/media/video/em28xx/em28xx-audio.c
+++ b/drivers/media/video/em28xx/em28xx-audio.c
@@ -383,6 +383,11 @@ static int snd_em28xx_hw_capture_free(struct snd_pcm_substream *substream)
 
 static int snd_em28xx_prepare(struct snd_pcm_substream *substream)
 {
+	struct em28xx *dev = snd_pcm_substream_chip(substream);
+
+	dev->adev.hwptr_done_capture = 0;
+	dev->adev.capture_transfer_done = 0;
+
 	return 0;
 }
 
diff --git a/drivers/media/video/em28xx/em28xx-cards.c b/drivers/media/video/em28xx/em28xx-cards.c
index 1c2e544eda73..ffe9306f5bb9 100644
--- a/drivers/media/video/em28xx/em28xx-cards.c
+++ b/drivers/media/video/em28xx/em28xx-cards.c
@@ -2170,8 +2170,6 @@ static int em28xx_hint_board(struct em28xx *dev)
 /* ----------------------------------------------------------------------- */
 void em28xx_register_i2c_ir(struct em28xx *dev)
 {
-	struct i2c_board_info info;
-	struct IR_i2c_init_data init_data;
 	const unsigned short addr_list[] = {
 		 0x30, 0x47, I2C_CLIENT_END
 	};
@@ -2179,9 +2177,9 @@ void em28xx_register_i2c_ir(struct em28xx *dev)
 	if (disable_ir)
 		return;
 
-	memset(&info, 0, sizeof(struct i2c_board_info));
-	memset(&init_data, 0, sizeof(struct IR_i2c_init_data));
-	strlcpy(info.type, "ir_video", I2C_NAME_SIZE);
+	memset(&dev->info, 0, sizeof(&dev->info));
+	memset(&dev->init_data, 0, sizeof(dev->init_data));
+	strlcpy(dev->info.type, "ir_video", I2C_NAME_SIZE);
 
 	/* detect & configure */
 	switch (dev->model) {
@@ -2191,19 +2189,19 @@ void em28xx_register_i2c_ir(struct em28xx *dev)
 		break;
 	case (EM2800_BOARD_TERRATEC_CINERGY_200):
 	case (EM2820_BOARD_TERRATEC_CINERGY_250):
-		init_data.ir_codes = ir_codes_em_terratec;
-		init_data.get_key = em28xx_get_key_terratec;
-		init_data.name = "i2c IR (EM28XX Terratec)";
+		dev->init_data.ir_codes = ir_codes_em_terratec;
+		dev->init_data.get_key = em28xx_get_key_terratec;
+		dev->init_data.name = "i2c IR (EM28XX Terratec)";
 		break;
 	case (EM2820_BOARD_PINNACLE_USB_2):
-		init_data.ir_codes = ir_codes_pinnacle_grey;
-		init_data.get_key = em28xx_get_key_pinnacle_usb_grey;
-		init_data.name = "i2c IR (EM28XX Pinnacle PCTV)";
+		dev->init_data.ir_codes = ir_codes_pinnacle_grey;
+		dev->init_data.get_key = em28xx_get_key_pinnacle_usb_grey;
+		dev->init_data.name = "i2c IR (EM28XX Pinnacle PCTV)";
 		break;
 	case (EM2820_BOARD_HAUPPAUGE_WINTV_USB_2):
-		init_data.ir_codes = ir_codes_hauppauge_new;
-		init_data.get_key = em28xx_get_key_em_haup;
-		init_data.name = "i2c IR (EM2840 Hauppauge)";
+		dev->init_data.ir_codes = ir_codes_hauppauge_new;
+		dev->init_data.get_key = em28xx_get_key_em_haup;
+		dev->init_data.name = "i2c IR (EM2840 Hauppauge)";
 		break;
 	case (EM2820_BOARD_MSI_VOX_USB_2):
 		break;
@@ -2215,9 +2213,9 @@ void em28xx_register_i2c_ir(struct em28xx *dev)
 		break;
 	}
 
-	if (init_data.name)
-		info.platform_data = &init_data;
-	i2c_new_probed_device(&dev->i2c_adap, &info, addr_list);
+	if (dev->init_data.name)
+		dev->info.platform_data = &dev->init_data;
+	i2c_new_probed_device(&dev->i2c_adap, &dev->info, addr_list);
 }
 
 void em28xx_card_setup(struct em28xx *dev)
diff --git a/drivers/media/video/em28xx/em28xx-dvb.c b/drivers/media/video/em28xx/em28xx-dvb.c
index d603575431b4..ec1d212f7e3a 100644
--- a/drivers/media/video/em28xx/em28xx-dvb.c
+++ b/drivers/media/video/em28xx/em28xx-dvb.c
@@ -591,6 +591,7 @@ static int dvb_fini(struct em28xx *dev)
 
 	if (dev->dvb) {
 		unregister_dvb(dev->dvb);
+		kfree(dev->dvb);
 		dev->dvb = NULL;
 	}
 
diff --git a/drivers/media/video/em28xx/em28xx.h b/drivers/media/video/em28xx/em28xx.h
index a2add61f7d59..cb2a70a59a0f 100644
--- a/drivers/media/video/em28xx/em28xx.h
+++ b/drivers/media/video/em28xx/em28xx.h
@@ -595,6 +595,10 @@ struct em28xx {
 	struct delayed_work sbutton_query_work;
 
 	struct em28xx_dvb *dvb;
+
+	/* I2C keyboard data */
+	struct i2c_board_info info;
+	struct IR_i2c_init_data init_data;
 };
 
 struct em28xx_ops {
diff --git a/drivers/media/video/gspca/m5602/m5602_s5k4aa.c b/drivers/media/video/gspca/m5602/m5602_s5k4aa.c
index 0163903d1c0f..3b159e4e69b1 100644
--- a/drivers/media/video/gspca/m5602/m5602_s5k4aa.c
+++ b/drivers/media/video/gspca/m5602/m5602_s5k4aa.c
@@ -35,12 +35,25 @@ static
     const
 	struct dmi_system_id s5k4aa_vflip_dmi_table[] = {
 	{
+		.ident = "BRUNEINIT",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "BRUNENIT"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "BRUNENIT"),
+			DMI_MATCH(DMI_BOARD_VERSION, "00030D0000000001")
+		}
+	}, {
 		.ident = "Fujitsu-Siemens Amilo Xa 2528",
 		.matches = {
 			DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"),
 			DMI_MATCH(DMI_PRODUCT_NAME, "AMILO Xa 2528")
 		}
 	}, {
+		.ident = "Fujitsu-Siemens Amilo Xi 2528",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "AMILO Xi 2528")
+		}
+	}, {
 		.ident = "Fujitsu-Siemens Amilo Xi 2550",
 		.matches = {
 			DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"),
@@ -51,6 +64,13 @@ static
 		.matches = {
 			DMI_MATCH(DMI_SYS_VENDOR, "Micro-Star International"),
 			DMI_MATCH(DMI_PRODUCT_NAME, "GX700"),
+			DMI_MATCH(DMI_BIOS_DATE, "12/02/2008")
+		}
+	}, {
+		.ident = "MSI GX700",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Micro-Star International"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "GX700"),
 			DMI_MATCH(DMI_BIOS_DATE, "07/26/2007")
 		}
 	}, {
diff --git a/drivers/media/video/gspca/ov519.c b/drivers/media/video/gspca/ov519.c
index 2f6e135d94bc..557886522211 100644
--- a/drivers/media/video/gspca/ov519.c
+++ b/drivers/media/video/gspca/ov519.c
@@ -3364,6 +3364,7 @@ static const __devinitdata struct usb_device_id device_table[] = {
 	{USB_DEVICE(0x041e, 0x4061), .driver_info = BRIDGE_OV519 },
 	{USB_DEVICE(0x041e, 0x4064),
 	 .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
+	{USB_DEVICE(0x041e, 0x4067), .driver_info = BRIDGE_OV519 },
 	{USB_DEVICE(0x041e, 0x4068),
 	 .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
 	{USB_DEVICE(0x045e, 0x028c), .driver_info = BRIDGE_OV519 },
diff --git a/drivers/media/video/gspca/sonixj.c b/drivers/media/video/gspca/sonixj.c
index d6332ab80669..33f4d0a1f6fd 100644
--- a/drivers/media/video/gspca/sonixj.c
+++ b/drivers/media/video/gspca/sonixj.c
@@ -727,7 +727,7 @@ static const u8 ov7660_sensor_init[][8] = {
 	{0xa1, 0x21, 0x12, 0x05, 0x00, 0x00, 0x00, 0x10},
 						/* Outformat = rawRGB */
 	{0xa1, 0x21, 0x13, 0xb8, 0x00, 0x00, 0x00, 0x10}, /* init COM8 */
-	{0xd1, 0x21, 0x00, 0x01, 0x74, 0x74, 0x00, 0x10},
+	{0xd1, 0x21, 0x00, 0x01, 0x74, 0x92, 0x00, 0x10},
 						/* GAIN BLUE RED VREF */
 	{0xd1, 0x21, 0x04, 0x00, 0x7d, 0x62, 0x00, 0x10},
 						/* COM 1 BAVE GEAVE AECHH */
@@ -783,7 +783,7 @@ static const u8 ov7660_sensor_init[][8] = {
 	{0xc1, 0x21, 0x88, 0xaf, 0xc7, 0xdf, 0x00, 0x10}, /* gamma curve */
 	{0xc1, 0x21, 0x8b, 0x99, 0x99, 0xcf, 0x00, 0x10}, /* reserved */
 	{0xb1, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x10}, /* DM_LNL/H */
-	{0xb1, 0x21, 0xa1, 0x00, 0x00, 0x00, 0x00, 0x10},
+	{0xa1, 0x21, 0xa1, 0x00, 0x00, 0x00, 0x00, 0x10},
 /****** (some exchanges in the win trace) ******/
 	{0xa1, 0x21, 0x1e, 0x01, 0x00, 0x00, 0x00, 0x10}, /* MVFP */
 						/* bits[3..0]reserved */
@@ -1145,17 +1145,12 @@ static int configure_gpio(struct gspca_dev *gspca_dev,
 		reg_w1(gspca_dev, 0x01, 0x42);
 		break;
 	case SENSOR_OV7660:
-		reg_w1(gspca_dev, 0x01, 0x61);
-		reg_w1(gspca_dev, 0x17, 0x20);
-		reg_w1(gspca_dev, 0x01, 0x60);
-		reg_w1(gspca_dev, 0x01, 0x40);
-		break;
 	case SENSOR_SP80708:
 		reg_w1(gspca_dev, 0x01, 0x63);
 		reg_w1(gspca_dev, 0x17, 0x20);
 		reg_w1(gspca_dev, 0x01, 0x62);
 		reg_w1(gspca_dev, 0x01, 0x42);
-		mdelay(100);
+		msleep(100);
 		reg_w1(gspca_dev, 0x02, 0x62);
 		break;
 /*	case SENSOR_HV7131R: */
@@ -1624,6 +1619,8 @@ static void setvflip(struct sd *sd)
 
 static void setinfrared(struct sd *sd)
 {
+	if (sd->gspca_dev.ctrl_dis & (1 << INFRARED_IDX))
+		return;
 /*fixme: different sequence for StarCam Clip and StarCam 370i */
 /* Clip */
 	i2c_w1(&sd->gspca_dev, 0x02,			/* gpio */
@@ -1637,16 +1634,19 @@ static void setfreq(struct gspca_dev *gspca_dev)
 	if (gspca_dev->ctrl_dis & (1 << FREQ_IDX))
 		return;
 	if (sd->sensor == SENSOR_OV7660) {
+		u8 com8;
+
+		com8 = 0xdf;		/* auto gain/wb/expo */
 		switch (sd->freq) {
 		case 0: /* Banding filter disabled */
-			i2c_w1(gspca_dev, 0x13, 0xdf);
+			i2c_w1(gspca_dev, 0x13, com8 | 0x20);
 			break;
 		case 1: /* 50 hz */
-			i2c_w1(gspca_dev, 0x13, 0xff);
+			i2c_w1(gspca_dev, 0x13, com8);
 			i2c_w1(gspca_dev, 0x3b, 0x0a);
 			break;
 		case 2: /* 60 hz */
-			i2c_w1(gspca_dev, 0x13, 0xff);
+			i2c_w1(gspca_dev, 0x13, com8);
 			i2c_w1(gspca_dev, 0x3b, 0x02);
 			break;
 		}
@@ -1796,12 +1796,6 @@ static int sd_start(struct gspca_dev *gspca_dev)
 		reg_w1(gspca_dev, 0x99, 0x60);
 		break;
 	case SENSOR_OV7660:
-		reg_w1(gspca_dev, 0x9a, 0x05);
-		if (sd->bridge == BRIDGE_SN9C105)
-			reg_w1(gspca_dev, 0x99, 0xff);
-		else
-			reg_w1(gspca_dev, 0x99, 0x5b);
-		break;
 	case SENSOR_SP80708:
 		reg_w1(gspca_dev, 0x9a, 0x05);
 		reg_w1(gspca_dev, 0x99, 0x59);
@@ -2325,18 +2319,19 @@ static const __devinitdata struct usb_device_id device_table[] = {
 	{USB_DEVICE(0x0c45, 0x607c), BSI(SN9C102P, HV7131R, 0x11)},
 /*	{USB_DEVICE(0x0c45, 0x607e), BSI(SN9C102P, OV7630, 0x??)}, */
 	{USB_DEVICE(0x0c45, 0x60c0), BSI(SN9C105, MI0360, 0x5d)},
-/*	{USB_DEVICE(0x0c45, 0x60c8), BSI(SN9C105, OM6801, 0x??)}, */
+/*	{USB_DEVICE(0x0c45, 0x60c8), BSI(SN9C105, OM6802, 0x??)}, */
 /*	{USB_DEVICE(0x0c45, 0x60cc), BSI(SN9C105, HV7131GP, 0x??)}, */
 	{USB_DEVICE(0x0c45, 0x60ec), BSI(SN9C105, MO4000, 0x21)},
 /*	{USB_DEVICE(0x0c45, 0x60ef), BSI(SN9C105, ICM105C, 0x??)}, */
 /*	{USB_DEVICE(0x0c45, 0x60fa), BSI(SN9C105, OV7648, 0x??)}, */
 	{USB_DEVICE(0x0c45, 0x60fb), BSI(SN9C105, OV7660, 0x21)},
-	{USB_DEVICE(0x0c45, 0x60fc), BSI(SN9C105, HV7131R, 0x11)},
 #if !defined CONFIG_USB_SN9C102 && !defined CONFIG_USB_SN9C102_MODULE
+	{USB_DEVICE(0x0c45, 0x60fc), BSI(SN9C105, HV7131R, 0x11)},
 	{USB_DEVICE(0x0c45, 0x60fe), BSI(SN9C105, OV7630, 0x21)},
 #endif
 	{USB_DEVICE(0x0c45, 0x6100), BSI(SN9C120, MI0360, 0x5d)}, /*sn9c128*/
-/*	{USB_DEVICE(0x0c45, 0x6108), BSI(SN9C120, OM6801, 0x??)}, */
+/*	{USB_DEVICE(0x0c45, 0x6102), BSI(SN9C120, PO2030N, ??)}, */
+/*	{USB_DEVICE(0x0c45, 0x6108), BSI(SN9C120, OM6802, 0x21)}, */
 	{USB_DEVICE(0x0c45, 0x610a), BSI(SN9C120, OV7648, 0x21)}, /*sn9c128*/
 	{USB_DEVICE(0x0c45, 0x610b), BSI(SN9C120, OV7660, 0x21)}, /*sn9c128*/
 	{USB_DEVICE(0x0c45, 0x610c), BSI(SN9C120, HV7131R, 0x11)}, /*sn9c128*/
@@ -2352,6 +2347,7 @@ static const __devinitdata struct usb_device_id device_table[] = {
 #if !defined CONFIG_USB_SN9C102 && !defined CONFIG_USB_SN9C102_MODULE
 	{USB_DEVICE(0x0c45, 0x6130), BSI(SN9C120, MI0360, 0x5d)},
 #endif
+/*	{USB_DEVICE(0x0c45, 0x6132), BSI(SN9C120, OV7670, 0x21)}, */
 	{USB_DEVICE(0x0c45, 0x6138), BSI(SN9C120, MO4000, 0x21)},
 	{USB_DEVICE(0x0c45, 0x613a), BSI(SN9C120, OV7648, 0x21)},
 #if !defined CONFIG_USB_SN9C102 && !defined CONFIG_USB_SN9C102_MODULE
@@ -2359,7 +2355,9 @@ static const __devinitdata struct usb_device_id device_table[] = {
 #endif
 	{USB_DEVICE(0x0c45, 0x613c), BSI(SN9C120, HV7131R, 0x11)},
 	{USB_DEVICE(0x0c45, 0x613e), BSI(SN9C120, OV7630, 0x21)},
-	{USB_DEVICE(0x0c45, 0x6143), BSI(SN9C120, SP80708, 0x18)},
+/*	{USB_DEVICE(0x0c45, 0x6142), BSI(SN9C120, PO2030N, ??)}, *sn9c120b*/
+	{USB_DEVICE(0x0c45, 0x6143), BSI(SN9C120, SP80708, 0x18)}, /*sn9c120b*/
+	{USB_DEVICE(0x0c45, 0x6148), BSI(SN9C120, OM6802, 0x21)}, /*sn9c120b*/
 	{}
 };
 MODULE_DEVICE_TABLE(usb, device_table);
diff --git a/drivers/media/video/mxc/capture/Kconfig b/drivers/media/video/mxc/capture/Kconfig
index adab0a886f36..276dfa424feb 100644
--- a/drivers/media/video/mxc/capture/Kconfig
+++ b/drivers/media/video/mxc/capture/Kconfig
@@ -58,6 +58,22 @@ config MXC_CAMERA_MICRON111
 	---help---
 	  If you plan to use the mt9v111 Camera with your MXC system, say Y here.
 
+config MXC_CAMERA_MICRON111_1
+    tristate "Micron mt9v111 camera 1 support"
+    select I2C_MXC
+    depends on ! VIDEO_MXC_EMMA_CAMERA
+    depends on MXC_CAMERA_MICRON111
+    ---help---
+      If you plan to use the mt9v111 Camera 1 with your MXC system, say Y here.
+
+config MXC_CAMERA_MICRON111_2
+    tristate "Micron mt9v111 camera 2 support"
+    select I2C_MXC
+    depends on ! VIDEO_MXC_EMMA_CAMERA
+    depends on MXC_CAMERA_MICRON111
+    ---help---
+      If you plan to use the mt9v111 Camera 2 with your MXC system, say Y here.
+
 config MXC_CAMERA_OV2640
 	tristate "OmniVision ov2640 camera support"
 	depends on !VIDEO_MXC_EMMA_CAMERA
@@ -72,7 +88,7 @@ config MXC_CAMERA_OV3640
 
 config MXC_TVIN_ADV7180
 	tristate "Analog Device adv7180 TV Decoder Input support"
-	depends on MACH_MX35_3DS
+	depends on (MACH_MX35_3DS || MACH_MX51_3DS)
 	---help---
 	  If you plan to use the adv7180 video decoder with your MXC system, say Y here.
 
diff --git a/drivers/media/video/mxc/capture/Makefile b/drivers/media/video/mxc/capture/Makefile
index 112923c8fc8f..03ff094171bf 100644
--- a/drivers/media/video/mxc/capture/Makefile
+++ b/drivers/media/video/mxc/capture/Makefile
@@ -35,5 +35,5 @@ obj-$(CONFIG_MXC_CAMERA_OV2640) += ov2640_camera.o
 ov3640_camera-objs := ov3640.o sensor_clock.o
 obj-$(CONFIG_MXC_CAMERA_OV3640) += ov3640_camera.o
 
-adv7180_tvin-objs := adv7180.o sensor_clock.o
+adv7180_tvin-objs := adv7180.o
 obj-$(CONFIG_MXC_TVIN_ADV7180) += adv7180_tvin.o
diff --git a/drivers/media/video/mxc/capture/adv7180.c b/drivers/media/video/mxc/capture/adv7180.c
index 1edee763bebc..527a0d1ad9fa 100644
--- a/drivers/media/video/mxc/capture/adv7180.c
+++ b/drivers/media/video/mxc/capture/adv7180.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -39,6 +39,7 @@ static struct regulator *dvddio_regulator;
 static struct regulator *dvdd_regulator;
 static struct regulator *avdd_regulator;
 static struct regulator *pvdd_regulator;
+static struct mxc_tvin_platform_data *tvin_plat;
 
 extern void gpio_sensor_active(void);
 extern void gpio_sensor_inactive(void);
@@ -118,26 +119,26 @@ static video_fmt_t video_fmts[] = {
 	{			/*! NTSC */
 	 .v4l2_id = V4L2_STD_NTSC,
 	 .name = "NTSC",
-	 .raw_width = 720 - 1,	/* SENS_FRM_WIDTH */
-	 .raw_height = 288 - 1,	/* SENS_FRM_HEIGHT */
+	 .raw_width = 720,	/* SENS_FRM_WIDTH */
+	 .raw_height = 525,	/* SENS_FRM_HEIGHT */
 	 .active_width = 720,	/* ACT_FRM_WIDTH plus 1 */
-	 .active_height = (480 / 2),	/* ACT_FRM_WIDTH plus 1 */
+	 .active_height = 480,	/* ACT_FRM_WIDTH plus 1 */
 	 },
 	{			/*! (B, G, H, I, N) PAL */
 	 .v4l2_id = V4L2_STD_PAL,
 	 .name = "PAL",
-	 .raw_width = 720 - 1,
-	 .raw_height = (576 / 2) + 24 * 2 - 1,
+	 .raw_width = 720,
+	 .raw_height = 625,
 	 .active_width = 720,
-	 .active_height = (576 / 2),
+	 .active_height = 576,
 	 },
 	{			/*! Unlocked standard */
 	 .v4l2_id = V4L2_STD_ALL,
 	 .name = "Autodetect",
-	 .raw_width = 720 - 1,
-	 .raw_height = (576 / 2) + 24 * 2 - 1,
+	 .raw_width = 720,
+	 .raw_height = 625,
 	 .active_width = 720,
-	 .active_height = (576 / 2),
+	 .active_height = 576,
 	 },
 };
 
@@ -246,6 +247,10 @@ static void adv7180_get_std(v4l2_std_id *std)
 
 	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180_get_std\n");
 
+	/* Make sure power on */
+	if (tvin_plat->pwdn)
+		tvin_plat->pwdn(0);
+
 	/* Read the AD_RESULT to get the detect output video standard */
 	tmp = adv7180_read(ADV7180_STATUS_1) & 0x70;
 
@@ -335,6 +340,11 @@ static int ioctl_s_power(struct v4l2_int_device *s, int on)
 
 	if (on && !sensor->on) {
 		gpio_sensor_active();
+
+		/* Make sure pwoer on */
+		if (tvin_plat->pwdn)
+			tvin_plat->pwdn(0);
+
 		if (adv7180_write_reg(ADV7180_PWR_MNG, 0) != 0)
 			return -EIO;
 	} else if (!on && sensor->on) {
@@ -500,6 +510,10 @@ static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
 
 	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_g_ctrl\n");
 
+	/* Make sure power on */
+	if (tvin_plat->pwdn)
+		tvin_plat->pwdn(0);
+
 	switch (vc->id) {
 	case V4L2_CID_BRIGHTNESS:
 		dev_dbg(&adv7180_data.i2c_client->dev,
@@ -593,6 +607,10 @@ static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
 
 	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_s_ctrl\n");
 
+	/* Make sure power on */
+	if (tvin_plat->pwdn)
+		tvin_plat->pwdn(0);
+
 	switch (vc->id) {
 	case V4L2_CID_BRIGHTNESS:
 		dev_dbg(&adv7180_data.i2c_client->dev,
@@ -803,13 +821,13 @@ static int adv7180_probe(struct i2c_client *client,
 {
 	int rev_id;
 	int ret = 0;
-	struct mxc_tvin_platform_data *plat_data = client->dev.platform_data;
+	tvin_plat = client->dev.platform_data;
 
 	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180_probe\n");
 
-	if (plat_data->dvddio_reg) {
+	if (tvin_plat->dvddio_reg) {
 		dvddio_regulator =
-		    regulator_get(&client->dev, plat_data->dvddio_reg);
+		    regulator_get(&client->dev, tvin_plat->dvddio_reg);
 		if (!IS_ERR_VALUE((unsigned long)dvddio_regulator)) {
 			regulator_set_voltage(dvddio_regulator, 3300000, 3300000);
 			if (regulator_enable(dvddio_regulator) != 0)
@@ -817,9 +835,9 @@ static int adv7180_probe(struct i2c_client *client,
 		}
 	}
 
-	if (plat_data->dvdd_reg) {
+	if (tvin_plat->dvdd_reg) {
 		dvdd_regulator =
-		    regulator_get(&client->dev, plat_data->dvdd_reg);
+		    regulator_get(&client->dev, tvin_plat->dvdd_reg);
 		if (!IS_ERR_VALUE((unsigned long)dvdd_regulator)) {
 			regulator_set_voltage(dvdd_regulator, 1800000, 1800000);
 			if (regulator_enable(dvdd_regulator) != 0)
@@ -827,9 +845,9 @@ static int adv7180_probe(struct i2c_client *client,
 		}
 	}
 
-	if (plat_data->avdd_reg) {
+	if (tvin_plat->avdd_reg) {
 		avdd_regulator =
-		    regulator_get(&client->dev, plat_data->avdd_reg);
+		    regulator_get(&client->dev, tvin_plat->avdd_reg);
 		if (!IS_ERR_VALUE((unsigned long)avdd_regulator)) {
 			regulator_set_voltage(avdd_regulator, 1800000, 1800000);
 			if (regulator_enable(avdd_regulator) != 0)
@@ -837,9 +855,9 @@ static int adv7180_probe(struct i2c_client *client,
 		}
 	}
 
-	if (plat_data->pvdd_reg) {
+	if (tvin_plat->pvdd_reg) {
 		pvdd_regulator =
-		    regulator_get(&client->dev, plat_data->pvdd_reg);
+		    regulator_get(&client->dev, tvin_plat->pvdd_reg);
 		if (!IS_ERR_VALUE((unsigned long)pvdd_regulator)) {
 			regulator_set_voltage(pvdd_regulator, 1800000, 1800000);
 			if (regulator_enable(pvdd_regulator) != 0)
@@ -847,11 +865,12 @@ static int adv7180_probe(struct i2c_client *client,
 		}
 	}
 
-	if (plat_data->reset)
-		plat_data->reset();
 
-	if (plat_data->pwdn)
-		plat_data->pwdn(1);
+	if (tvin_plat->reset)
+		tvin_plat->reset();
+
+	if (tvin_plat->pwdn)
+		tvin_plat->pwdn(0);
 
 	msleep(1);
 
@@ -913,7 +932,7 @@ static int adv7180_detach(struct i2c_client *client)
 		__func__, IF_NAME, client->addr << 1, client->adapter->name);
 
 	if (plat_data->pwdn)
-		plat_data->pwdn(0);
+		plat_data->pwdn(1);
 
 	if (dvddio_regulator) {
 		regulator_disable(dvddio_regulator);
diff --git a/drivers/media/video/mxc/capture/csi_v4l2_capture.c b/drivers/media/video/mxc/capture/csi_v4l2_capture.c
index 9bddc3692996..cf224e0673f0 100644
--- a/drivers/media/video/mxc/capture/csi_v4l2_capture.c
+++ b/drivers/media/video/mxc/capture/csi_v4l2_capture.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -789,15 +789,15 @@ static ssize_t csi_v4l_read(struct file *file, char *buf, size_t count,
 							  (cam->v2f.fmt.
 							   pix.sizeimage),
 							  &cam->
-							  still_buf,
+							  still_buf[0],
 							  GFP_DMA | GFP_KERNEL);
 		if (cam->still_buf_vaddr == NULL) {
 			pr_err("alloc dma memory failed\n");
 			return -ENOMEM;
 		}
 		cam->still_counter = 0;
-		__raw_writel(cam->still_buf, CSI_CSIDMASA_FB2);
-		__raw_writel(cam->still_buf, CSI_CSIDMASA_FB1);
+		__raw_writel(cam->still_buf[0], CSI_CSIDMASA_FB2);
+		__raw_writel(cam->still_buf[0], CSI_CSIDMASA_FB1);
 		__raw_writel(__raw_readl(CSI_CSICR3) | BIT_DMA_REFLASH_RFF,
 			     CSI_CSICR3);
 		__raw_writel(__raw_readl(CSI_CSISR), CSI_CSISR);
@@ -813,8 +813,8 @@ static ssize_t csi_v4l_read(struct file *file, char *buf, size_t count,
 
 	if (cam->still_buf_vaddr != NULL) {
 		dma_free_coherent(0, PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
-				  cam->still_buf_vaddr, cam->still_buf);
-		cam->still_buf = 0;
+				  cam->still_buf_vaddr, cam->still_buf[0]);
+		cam->still_buf[0] = 0;
 		cam->still_buf_vaddr = NULL;
 	}
 
diff --git a/drivers/media/video/mxc/capture/emma_v4l2_capture.c b/drivers/media/video/mxc/capture/emma_v4l2_capture.c
index 9cb08b26f1cd..170807716ec6 100644
--- a/drivers/media/video/mxc/capture/emma_v4l2_capture.c
+++ b/drivers/media/video/mxc/capture/emma_v4l2_capture.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -858,7 +858,7 @@ static void mxc_csi_dma_chaining(void *data)
 
 		/* Config DMA */
 		memset(&dma_request, 0, sizeof(mxc_dma_requestbuf_t));
-		dma_request.dst_addr = cam->still_buf
+		dma_request.dst_addr = cam->still_buf[0]
 		    + (chained % max_dma) * CSI_DMA_LENGTH;
 		dma_request.src_addr = (dma_addr_t) CSI_CSIRXFIFO_PHYADDR;
 		dma_request.num_of_bytes = count;
@@ -1040,7 +1040,7 @@ mxc_v4l_read(struct file *file, char *buf, size_t count, loff_t *ppos)
 
 	cam->still_buf_vaddr = dma_alloc_coherent(0,
 						  PAGE_ALIGN(CSI_MEM_SIZE),
-						  &cam->still_buf,
+						  &cam->still_buf[0],
 						  GFP_DMA | GFP_KERNEL);
 
 	if (!cam->still_buf_vaddr) {
@@ -1120,8 +1120,8 @@ mxc_v4l_read(struct file *file, char *buf, size_t count, loff_t *ppos)
 
       exit1:
 	dma_free_coherent(0, PAGE_ALIGN(CSI_MEM_SIZE),
-			  cam->still_buf_vaddr, cam->still_buf);
-	cam->still_buf = 0;
+			  cam->still_buf_vaddr, cam->still_buf[0]);
+	cam->still_buf[0] = 0;
 
       exit0:
 	up(&cam->busy_lock);
@@ -1160,7 +1160,8 @@ mxc_v4l_read(struct file *file, char *buf, size_t count, loff_t *ppos)
 
 	v_address = dma_alloc_coherent(0,
 				       PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
-				       &cam->still_buf, GFP_DMA | GFP_KERNEL);
+				       &cam->still_buf[0],
+				       GFP_DMA | GFP_KERNEL);
 
 	if (!v_address) {
 		pr_info("mxc_v4l_read failed at allocate still_buf\n");
@@ -1194,8 +1195,8 @@ mxc_v4l_read(struct file *file, char *buf, size_t count, loff_t *ppos)
 
       exit1:
 	dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address,
-			  cam->still_buf);
-	cam->still_buf = 0;
+			  cam->still_buf[0]);
+	cam->still_buf[0] = 0;
 
       exit0:
 	up(&cam->busy_lock);
diff --git a/drivers/media/video/mxc/capture/ipu_csi_enc.c b/drivers/media/video/mxc/capture/ipu_csi_enc.c
index fd3f0c132c14..0b87282551ff 100644
--- a/drivers/media/video/mxc/capture/ipu_csi_enc.c
+++ b/drivers/media/video/mxc/capture/ipu_csi_enc.c
@@ -25,6 +25,7 @@
 #include "ipu_prp_sw.h"
 
 #ifdef CAMERA_DBG
+	extern void ipu_dump_registers(void);
 	#define CAMERA_TRACE(x) (printk)x
 #else
 	#define CAMERA_TRACE(x)
@@ -66,6 +67,7 @@ static int csi_enc_setup(cam_data *cam)
 	u32 pixel_fmt;
 	int err = 0;
 	dma_addr_t dummy = cam->dummy_frame.buffer.m.offset;
+	ipu_channel_t channel;
 
 	CAMERA_TRACE("In csi_enc_setup\n");
 	if (!cam) {
@@ -101,13 +103,18 @@ static int csi_enc_setup(cam_data *cam)
 
 	ipu_csi_enable_mclk_if(CSI_MCLK_ENC, cam->csi, true, true);
 
-	err = ipu_init_channel(CSI_MEM, &params);
+	if (cam->csi == 0)
+		channel = CSI_MEM0;
+	else
+		channel = CSI_MEM1;
+
+	err = ipu_init_channel(channel, &params);
 	if (err != 0) {
 		printk(KERN_ERR "ipu_init_channel %d\n", err);
 		return err;
 	}
 
-	err = ipu_init_channel_buffer(CSI_MEM, IPU_OUTPUT_BUFFER,
+	err = ipu_init_channel_buffer(channel, IPU_OUTPUT_BUFFER,
 				      pixel_fmt, cam->v2f.fmt.pix.width,
 				      cam->v2f.fmt.pix.height,
 				      cam->v2f.fmt.pix.width, IPU_ROTATE_NONE,
@@ -115,12 +122,12 @@ static int csi_enc_setup(cam_data *cam)
 				      cam->offset.u_offset,
 				      cam->offset.v_offset);
 	if (err != 0) {
-		printk(KERN_ERR "CSI_MEM output buffer\n");
+		printk(KERN_ERR "CSI_MEM%d output buffer\n",cam->csi);
 		return err;
 	}
-	err = ipu_enable_channel(CSI_MEM);
+	err = ipu_enable_channel(channel);
 	if (err < 0) {
-		printk(KERN_ERR "ipu_enable_channel CSI_MEM\n");
+		printk(KERN_ERR "ipu_enable_channel CSI_MEM%d\n",cam->csi);
 		return err;
 	}
 
@@ -135,24 +142,34 @@ static int csi_enc_setup(cam_data *cam)
  *
  * @return  status
  */
-static int csi_enc_eba_update(dma_addr_t eba, int *buffer_num)
+static int csi_enc_eba_update(int csi, dma_addr_t eba, int *buffer_num)
 {
 	int err = 0;
+	ipu_channel_t channel;
+
+	if (csi == 0)
+		channel = CSI_MEM0;
+	else
+		channel = CSI_MEM1;
 
-	pr_debug("eba %x\n", eba);
-	err = ipu_update_channel_buffer(CSI_MEM, IPU_OUTPUT_BUFFER,
+	err = ipu_update_channel_buffer(channel, IPU_OUTPUT_BUFFER,
 					*buffer_num, eba);
+
 	if (err != 0) {
-		ipu_clear_buffer_ready(CSI_MEM, IPU_OUTPUT_BUFFER,
+		ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER,
 				       *buffer_num);
 		printk(KERN_ERR "err %d buffer_num %d\n", err, *buffer_num);
 		return err;
 	}
 
-	ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, *buffer_num);
+	ipu_select_buffer(channel, IPU_OUTPUT_BUFFER, *buffer_num);
 
 	*buffer_num = (*buffer_num == 0) ? 1 : 0;
 
+#ifdef CAMERA_DBG
+	ipu_dump_registers ();
+#endif
+
 	return 0;
 }
 
@@ -166,6 +183,7 @@ static int csi_enc_enabling_tasks(void *private)
 {
 	cam_data *cam = (cam_data *) private;
 	int err = 0;
+	int ipu_irq_csi_out_eof;
 	CAMERA_TRACE("IPU:In csi_enc_enabling_tasks\n");
 
 	cam->dummy_frame.vaddress = dma_alloc_coherent(0,
@@ -182,11 +200,16 @@ static int csi_enc_enabling_tasks(void *private)
 	    PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
 	cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress;
 
-	ipu_clear_irq(IPU_IRQ_CSI0_OUT_EOF);
-	err = ipu_request_irq(IPU_IRQ_CSI0_OUT_EOF,
-			      csi_enc_callback, 0, "Mxc Camera", cam);
+	if (cam->csi == 0)
+		ipu_irq_csi_out_eof = IPU_IRQ_CSI0_OUT_EOF;
+	else
+		ipu_irq_csi_out_eof = IPU_IRQ_CSI1_OUT_EOF;
+	ipu_clear_irq(ipu_irq_csi_out_eof);
+	err = ipu_request_irq(ipu_irq_csi_out_eof,
+				csi_enc_callback, 0, "Mxc Camera", cam);
+
 	if (err != 0) {
-		printk(KERN_ERR "Error registering rot irq\n");
+		printk(KERN_ERR "Error registering eot irq for csi %d\n",cam->csi);
 		return err;
 	}
 
@@ -209,12 +232,24 @@ static int csi_enc_disabling_tasks(void *private)
 {
 	cam_data *cam = (cam_data *) private;
 	int err = 0;
+	ipu_channel_t channel;
+	int ipu_irq_csi_out_eof;
 
-	ipu_free_irq(IPU_IRQ_CSI0_OUT_EOF, cam);
+	if (cam->csi == 0)
+	{
+		channel = CSI_MEM0;
+		ipu_irq_csi_out_eof = IPU_IRQ_CSI0_OUT_EOF;
+	}
+	else
+	{
+		channel = CSI_MEM1;
+		ipu_irq_csi_out_eof = IPU_IRQ_CSI1_OUT_EOF;
+	}
 
-	err = ipu_disable_channel(CSI_MEM, true);
+	ipu_free_irq(ipu_irq_csi_out_eof, cam);
+	err = ipu_disable_channel(channel, true);
 
-	ipu_uninit_channel(CSI_MEM);
+	ipu_uninit_channel(channel);
 
 	if (cam->dummy_frame.vaddress != 0) {
 		dma_free_coherent(0, cam->dummy_frame.buffer.length,
diff --git a/drivers/media/video/mxc/capture/ipu_prp_enc.c b/drivers/media/video/mxc/capture/ipu_prp_enc.c
index 4b5426cb887d..0df8050ad7de 100644
--- a/drivers/media/video/mxc/capture/ipu_prp_enc.c
+++ b/drivers/media/video/mxc/capture/ipu_prp_enc.c
@@ -19,12 +19,14 @@
  * @ingroup IPU
  */
 
+#include <linux/types.h>
 #include <linux/dma-mapping.h>
 #include <linux/ipu.h>
 #include "mxc_v4l2_capture.h"
 #include "ipu_prp_sw.h"
 
 #ifdef CAMERA_DBG
+	extern void ipu_dump_registers(void);
 	#define CAMERA_TRACE(x) (printk)x
 #else
 	#define CAMERA_TRACE(x)
@@ -266,11 +268,10 @@ static int prp_enc_setup(cam_data * cam)
  *
  * @return  status
  */
-static int prp_enc_eba_update(dma_addr_t eba, int *buffer_num)
+static int prp_enc_eba_update(int csi, dma_addr_t eba, int *buffer_num)
 {
 	int err = 0;
 
-	pr_debug("eba %x\n", eba);
 	if (grotation >= IPU_ROTATE_90_RIGHT) {
 		err = ipu_update_channel_buffer(MEM_ROT_ENC_MEM,
 						IPU_OUTPUT_BUFFER, *buffer_num,
@@ -294,6 +295,11 @@ static int prp_enc_eba_update(dma_addr_t eba, int *buffer_num)
 	}
 
 	*buffer_num = (*buffer_num == 0) ? 1 : 0;
+
+#ifdef CAMERA_DBG
+	ipu_dump_registers ();
+#endif
+
 	return 0;
 }
 
@@ -350,7 +356,6 @@ static int prp_enc_disabling_tasks(void *private)
 	if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
 		ipu_unlink_channels(CSI_PRP_ENC_MEM, MEM_ROT_ENC_MEM);
 	}
-
 	err = ipu_disable_channel(CSI_PRP_ENC_MEM, true);
 	if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
 		err |= ipu_disable_channel(MEM_ROT_ENC_MEM, true);
diff --git a/drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c b/drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c
index 7f0984c42950..9f8078d558b0 100644
--- a/drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c
+++ b/drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c
@@ -182,6 +182,7 @@ static int prpvf_start(void *private)
 		printk(KERN_ERR "Error initializing CSI_PRP_VF_MEM\n");
 		goto out_3;
 	}
+
 	err = ipu_init_channel(MEM_ROT_VF_MEM, NULL);
 	if (err != 0) {
 		printk(KERN_ERR "Error MEM_ROT_VF_MEM channel\n");
@@ -200,6 +201,7 @@ static int prpvf_start(void *private)
 	}
 
 	if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) {
+
 		err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER,
 					      format,
 					      vf.csi_prp_vf_mem.out_height,
diff --git a/drivers/media/video/mxc/capture/ipu_still.c b/drivers/media/video/mxc/capture/ipu_still.c
index 348bf2b9b564..22cf3f51e1cb 100644
--- a/drivers/media/video/mxc/capture/ipu_still.c
+++ b/drivers/media/video/mxc/capture/ipu_still.c
@@ -26,6 +26,9 @@
 #include "ipu_prp_sw.h"
 
 static int callback_eof_flag;
+#ifndef CONFIG_MXC_IPU_V1
+static int buffer_num;
+#endif
 
 #ifdef CONFIG_MXC_IPU_V1
 static int callback_flag;
@@ -42,10 +45,10 @@ static int callback_flag;
  */
 static irqreturn_t prp_csi_eof_callback(int irq, void *dev_id)
 {
-	if (callback_flag == 2) {
-		ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, 0);
+	ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER,
+			  callback_flag%2 ? 1 : 0);
+	if (callback_flag == 0)
 		ipu_enable_channel(CSI_MEM);
-	}
 
 	callback_flag++;
 	return IRQ_HANDLED;
@@ -65,9 +68,12 @@ static irqreturn_t prp_still_callback(int irq, void *dev_id)
 	cam_data *cam = (cam_data *) dev_id;
 
 	callback_eof_flag++;
-	if (callback_eof_flag < 5)
-		ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, 0);
-	else {
+	if (callback_eof_flag < 5) {
+#ifndef CONFIG_MXC_IPU_V1
+		buffer_num = (buffer_num == 0) ? 1 : 0;
+		ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, buffer_num);
+#endif
+	} else {
 		cam->still_counter++;
 		wake_up_interruptible(&cam->still_queue);
 	}
@@ -87,6 +93,8 @@ static int prp_still_start(void *private)
 	u32 pixel_fmt;
 	int err;
 	ipu_channel_params_t params;
+	ipu_channel_t channel;
+	int ipu_irq_csi_out_eof;
 
 	if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
 		pixel_fmt = IPU_PIX_FMT_YUV420P;
@@ -113,20 +121,32 @@ static int prp_still_start(void *private)
 
 	ipu_csi_enable_mclk_if(CSI_MCLK_RAW, cam->csi, true, true);
 
+	if (cam->csi == 0) {
+		channel = CSI_MEM0;
+		ipu_irq_csi_out_eof = IPU_IRQ_CSI0_OUT_EOF;
+	}
+	else {
+		channel = CSI_MEM1;
+		ipu_irq_csi_out_eof = IPU_IRQ_CSI1_OUT_EOF;
+	}
+
 	memset(&params, 0, sizeof(params));
-	err = ipu_init_channel(CSI_MEM, &params);
+	params.csi_mem.csi = cam->csi;
+	err = ipu_init_channel(channel, &params);
 	if (err != 0)
 		return err;
 
-	err = ipu_init_channel_buffer(CSI_MEM, IPU_OUTPUT_BUFFER,
+	err = ipu_init_channel_buffer(channel, IPU_OUTPUT_BUFFER,
 				      pixel_fmt, cam->v2f.fmt.pix.width,
 				      cam->v2f.fmt.pix.height,
 				      cam->v2f.fmt.pix.width, IPU_ROTATE_NONE,
-				      cam->still_buf, 0, 0, 0);
+				      cam->still_buf[0], cam->still_buf[1],
+				      0, 0);
 	if (err != 0)
 		return err;
 
 #ifdef CONFIG_MXC_IPU_V1
+	ipu_clear_irq(IPU_IRQ_SENSOR_OUT_EOF);
 	err = ipu_request_irq(IPU_IRQ_SENSOR_OUT_EOF, prp_still_callback,
 			      0, "Mxc Camera", cam);
 	if (err != 0) {
@@ -135,6 +155,7 @@ static int prp_still_start(void *private)
 	}
 	callback_flag = 0;
 	callback_eof_flag = 0;
+	ipu_clear_irq(IPU_IRQ_SENSOR_EOF);
 	err = ipu_request_irq(IPU_IRQ_SENSOR_EOF, prp_csi_eof_callback,
 			      0, "Mxc Camera", NULL);
 	if (err != 0) {
@@ -142,8 +163,9 @@ static int prp_still_start(void *private)
 		return err;
 	}
 #else
-	ipu_clear_irq(IPU_IRQ_CSI0_OUT_EOF);
-	err = ipu_request_irq(IPU_IRQ_CSI0_OUT_EOF, prp_still_callback,
+
+	ipu_clear_irq(ipu_irq_csi_out_eof);
+	err = ipu_request_irq(ipu_irq_csi_out_eof, prp_still_callback,
 			      0, "Mxc Camera", cam);
 	if (err != 0) {
 		printk(KERN_ERR "Error registering irq.\n");
@@ -151,9 +173,9 @@ static int prp_still_start(void *private)
 	}
 
 	callback_eof_flag = 0;
+	ipu_select_buffer(channel, IPU_OUTPUT_BUFFER, 0);
+	ipu_enable_channel(channel);
 
-	ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, 0);
-	ipu_enable_channel(CSI_MEM);
 	ipu_enable_csi(cam->csi);
 #endif
 
@@ -170,17 +192,28 @@ static int prp_still_stop(void *private)
 {
 	cam_data *cam = (cam_data *) private;
 	int err = 0;
+	ipu_channel_t channel;
+	int ipu_irq_csi_out_eof;
+
+	if (cam->csi == 0) {
+		channel = CSI_MEM0;
+		ipu_irq_csi_out_eof = IPU_IRQ_CSI0_OUT_EOF;
+	}
+	else {
+		channel = CSI_MEM1;
+		ipu_irq_csi_out_eof = IPU_IRQ_CSI1_OUT_EOF;
+	}
 
 #ifdef CONFIG_MXC_IPU_V1
 	ipu_free_irq(IPU_IRQ_SENSOR_EOF, NULL);
 	ipu_free_irq(IPU_IRQ_SENSOR_OUT_EOF, cam);
 #else
-	ipu_free_irq(IPU_IRQ_CSI0_OUT_EOF, cam);
+	ipu_free_irq(ipu_irq_csi_out_eof, cam);
 #endif
 
 	ipu_disable_csi(cam->csi);
-	ipu_disable_channel(CSI_MEM, true);
-	ipu_uninit_channel(CSI_MEM);
+	ipu_disable_channel(channel, true);
+	ipu_uninit_channel(channel);
 	ipu_csi_enable_mclk_if(CSI_MCLK_RAW, cam->csi, false, false);
 
 	return err;
diff --git a/drivers/media/video/mxc/capture/mt9v111.c b/drivers/media/video/mxc/capture/mt9v111.c
index c95a20683924..dfdd455db3dd 100644
--- a/drivers/media/video/mxc/capture/mt9v111.c
+++ b/drivers/media/video/mxc/capture/mt9v111.c
@@ -18,6 +18,9 @@
  *
  * @ingroup Camera
  */
+
+//#define MT9V111_DEBUG
+
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/slab.h>
@@ -40,7 +43,6 @@ static mt9v111_conf mt9v111_device;
 /*!
  * Holds the current frame rate.
  */
-static int reset_frame_rate = MT9V111_FRAME_RATE;
 
 struct sensor {
 	const struct mt9v111_platform_data *platform_data;
@@ -49,33 +51,45 @@ struct sensor {
 	struct v4l2_pix_format pix;
 	struct v4l2_captureparm streamcap;
 	bool on;
+	bool used;
 
 	/* control settings */
 	int brightness;
-	int hue;
-	int contrast;
 	int saturation;
-	int red;
-	int green;
-	int blue;
+	int sharpness;
+	int gain;
 	int ae_mode;
 
-} mt9v111_data;
-
-extern void gpio_sensor_active(void);
-extern void gpio_sensor_inactive(void);
+};
 
 static int mt9v111_probe(struct i2c_client *client,
 			 const struct i2c_device_id *id);
 static int mt9v111_remove(struct i2c_client *client);
 
 static const struct i2c_device_id mt9v111_id[] = {
-	{"mt9v111", 0},
+	{"mt9v111_1", 2},
+	{"mt9v111_2", 3},
 	{},
 };
 
+struct sensor mt9v111_data[ARRAY_SIZE(mt9v111_id)-1];
+
 MODULE_DEVICE_TABLE(i2c, mt9v111_id);
 
+static int mt9v111_suspend(struct i2c_client *client, pm_message_t mesg)
+{
+	pr_debug("In mt9v111_suspend\n");
+
+	return 0;
+}
+
+static int mt9v111_resume(struct i2c_client *client)
+{
+	pr_debug("In mt9v111_resume\n");
+
+	return 0;
+}
+
 static struct i2c_driver mt9v111_i2c_driver = {
 	.driver = {
 		   .owner = THIS_MODULE,
@@ -84,37 +98,52 @@ static struct i2c_driver mt9v111_i2c_driver = {
 	.probe = mt9v111_probe,
 	.remove = mt9v111_remove,
 	.id_table = mt9v111_id,
-/* To add power management add .suspend and .resume functions */
+	.suspend = mt9v111_suspend,
+	.resume = mt9v111_resume,
 };
 
 /*
  * Function definitions
  */
 
-#ifdef MT9V111_DEBUG
-static inline int mt9v111_read_reg(u8 reg)
+static int mt9v111_id_from_name ( const char * name )
+{
+	int id = -1;
+
+	if( name == NULL || ( strlen(name) < strlen("mt9v111_n") ) )
+		return -1;
+
+	id = (int)simple_strtol(name+strlen("mt9v111_"),NULL,0) - 1;
+	if( id >= ARRAY_SIZE(mt9v111_id) ) {
+		printk("Invalid sensor index %d for %s\n",id,name);
+		return -1;
+	}
+
+	return id;
+}
+
+static inline int mt9v111_read_reg(int sensorid , u8 reg)
 {
-	int val = i2c_smbus_read_word_data(mt9v111_data.i2c_client, reg);
+	int val = i2c_smbus_read_word_data(mt9v111_data[sensorid].i2c_client, reg);
 	if (val != -1)
 		val = cpu_to_be16(val);
 	return val;
 }
-#endif
 
 /*!
  * Writes to the register via I2C.
  */
-static inline int mt9v111_write_reg(u8 reg, u16 val)
+static inline int mt9v111_write_reg(int sensorid , u8 reg, u16 val)
 {
-	pr_debug("In mt9v111_write_reg (0x%x, 0x%x)\n", reg, val);
+	pr_debug("[%d] In mt9v111_write_reg (0x%x, 0x%x)\n", sensorid , reg, val);
 	pr_debug("   write reg %x val %x.\n", reg, val);
 
-	return i2c_smbus_write_word_data(mt9v111_data.i2c_client,
+	return i2c_smbus_write_word_data(mt9v111_data[sensorid].i2c_client,
 					 reg, cpu_to_be16(val));
 }
 
 /*!
- * Initialize mt9v111_sensor_lib
+ * Initialize mt9v111_sensor_lib_datasheet
  * Libarary for Sensor configuration through I2C
  *
  * @param       coreReg       Core Registers
@@ -122,7 +151,7 @@ static inline int mt9v111_write_reg(u8 reg, u16 val)
  *
  * @return status
  */
-static u8 mt9v111_sensor_lib(mt9v111_coreReg * coreReg, mt9v111_IFPReg * ifpReg)
+static u8 mt9v111_sensor_lib_datasheet(int sensorid , mt9v111_coreReg * coreReg, mt9v111_IFPReg * ifpReg)
 {
 	u8 reg;
 	u16 data;
@@ -130,200 +159,103 @@ static u8 mt9v111_sensor_lib(mt9v111_coreReg * coreReg, mt9v111_IFPReg * ifpReg)
 
 	pr_debug("In mt9v111_sensor_lib\n");
 
+	/* IFP R51(0x33)=5137,R57(0x39)=290,R59(0x3B)=1068,R62(0x3E)=4095,R89(0x59)=504,R90(0x5A)=605,R92(0x5C)=8222,R93(0x5D)=10021,R100(0x64)=4477 */
+
 	/*
 	 * setup to IFP registers
 	 */
 	reg = MT9V111I_ADDR_SPACE_SEL;
 	data = ifpReg->addrSpaceSel;
-	mt9v111_write_reg(reg, data);
-
-	/* Operation Mode Control */
-	reg = MT9V111I_MODE_CONTROL;
-	data = ifpReg->modeControl;
-	mt9v111_write_reg(reg, data);
-
-	/* Output format */
-	reg = MT9V111I_FORMAT_CONTROL;
-	data = ifpReg->formatControl;	/* Set bit 12 */
-	mt9v111_write_reg(reg, data);
-
-	/* AE limit 4 */
-	reg = MT9V111I_SHUTTER_WIDTH_LIMIT_AE;
-	data = ifpReg->gainLimitAE;
-	mt9v111_write_reg(reg, data);
-
-	reg = MT9V111I_OUTPUT_FORMAT_CTRL2;
-	data = ifpReg->outputFormatCtrl2;
-	mt9v111_write_reg(reg, data);
-
-	reg = MT9V111I_AE_SPEED;
-	data = ifpReg->AESpeed;
-	mt9v111_write_reg(reg, data);
-
-	/* output image size */
-	reg = MT9V111i_H_PAN;
-	data = 0x8000 | ifpReg->HPan;
-	mt9v111_write_reg(reg, data);
-
-	reg = MT9V111i_H_ZOOM;
-	data = 0x8000 | ifpReg->HZoom;
-	mt9v111_write_reg(reg, data);
-
-	reg = MT9V111i_H_SIZE;
-	data = 0x8000 | ifpReg->HSize;
-	mt9v111_write_reg(reg, data);
-
-	reg = MT9V111i_V_PAN;
-	data = 0x8000 | ifpReg->VPan;
-	mt9v111_write_reg(reg, data);
+	mt9v111_write_reg(sensorid,reg, data);
 
-	reg = MT9V111i_V_ZOOM;
-	data = 0x8000 | ifpReg->VZoom;
-	mt9v111_write_reg(reg, data);
+	reg = MT9V111I_LIMIT_SHARP_SATU_CTRL;
+	data = ifpReg->limitSharpSatuCtrl;
+	mt9v111_write_reg(sensorid,reg, data);
 
-	reg = MT9V111i_V_SIZE;
-	data = 0x8000 | ifpReg->VSize;
-	mt9v111_write_reg(reg, data);
-
-	reg = MT9V111i_H_PAN;
-	data = ~0x8000 & ifpReg->HPan;
-	mt9v111_write_reg(reg, data);
-#if 0
 	reg = MT9V111I_UPPER_SHUTTER_DELAY_LIM;
 	data = ifpReg->upperShutterDelayLi;
-	mt9v111_write_reg(reg, data);
+	mt9v111_write_reg(sensorid,reg, data);
+
+	reg = MT9V111I_IPF_BLACK_LEVEL_SUB;
+	data = ifpReg->ipfBlackLevelSub;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	reg = MT9V111I_GAIN_THRE_CCAM_ADJ;
+	data = ifpReg->agimnThreCamAdj;
+	mt9v111_write_reg(sensorid,reg, data);
 
 	reg = MT9V111I_SHUTTER_60;
 	data = ifpReg->shutter_width_60;
-	mt9v111_write_reg(reg, data);
+	mt9v111_write_reg(sensorid,reg, data);
+
+	reg = MT9V111I_AUTO_EXPOSURE_17;
+	data = ifpReg->auto_exposure_17;
+	mt9v111_write_reg(sensorid,reg, data);
 
 	reg = MT9V111I_SEARCH_FLICK_60;
 	data = ifpReg->search_flicker_60;
-	mt9v111_write_reg(reg, data);
-#endif
+	mt9v111_write_reg(sensorid,reg, data);
+
+	reg = MT9V111I_RESERVED93;
+	data = ifpReg->reserved93;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	reg = MT9V111I_RESERVED100;
+	data = ifpReg->reserved100;
+	mt9v111_write_reg(sensorid,reg, data);
 
 	/*
 	 * setup to sensor core registers
 	 */
 	reg = MT9V111I_ADDR_SPACE_SEL;
 	data = coreReg->addressSelect;
-	mt9v111_write_reg(reg, data);
-
-	/* enable changes and put the Sync bit on */
-	reg = MT9V111S_OUTPUT_CTRL;
-	data = MT9V111S_OUTCTRL_SYNC | MT9V111S_OUTCTRL_CHIP_ENABLE | 0x3000;
-	mt9v111_write_reg(reg, data);
+	mt9v111_write_reg(sensorid,reg, data);
 
-	/* min PIXCLK - Default */
-	reg = MT9V111S_PIXEL_CLOCK_SPEED;
-	data = coreReg->pixelClockSpeed;
-	mt9v111_write_reg(reg, data);
+	/* Core R5=46, R7[4]=0 (DEFAULT) ,R33=58369*/
 
-	/* Setup image flipping / Dark rows / row/column skip */
-	reg = MT9V111S_READ_MODE;
-	data = coreReg->readMode;
-	mt9v111_write_reg(reg, data);
-
-	/* zoom 0 */
-	reg = MT9V111S_DIGITAL_ZOOM;
-	data = coreReg->digitalZoom;
-	mt9v111_write_reg(reg, data);
-
-	/* min H-blank */
 	reg = MT9V111S_HOR_BLANKING;
 	data = coreReg->horizontalBlanking;
-	mt9v111_write_reg(reg, data);
-
-	/* min V-blank */
-	reg = MT9V111S_VER_BLANKING;
-	data = coreReg->verticalBlanking;
-	mt9v111_write_reg(reg, data);
-
-	reg = MT9V111S_SHUTTER_WIDTH;
-	data = coreReg->shutterWidth;
-	mt9v111_write_reg(reg, data);
+	mt9v111_write_reg(sensorid,reg, data);
 
-	reg = MT9V111S_SHUTTER_DELAY;
-	data = ifpReg->upperShutterDelayLi;
-	mt9v111_write_reg(reg, data);
-
-	/* changes become effective */
-	reg = MT9V111S_OUTPUT_CTRL;
-	data = MT9V111S_OUTCTRL_CHIP_ENABLE | 0x3000;
-	mt9v111_write_reg(reg, data);
+	reg = MT9V111S_RESERVED33;
+	data = coreReg->reserved33;
+	mt9v111_write_reg(sensorid,reg, data);
 
 	return error;
 }
 
-/*!
- * MT9V111 frame rate calculate
- *
- * @param frame_rate       int *
- * @param mclk             int
- * @return  None
- */
-static void mt9v111_rate_cal(int *frame_rate, int mclk)
+void mt9v111_config_datasheet(void)
 {
-	int num_clock_per_row;
-	int max_rate = 0;
+	pr_debug("In mt9v111_config_datasheet\n");
 
-	pr_debug("In mt9v111_rate_cal\n");
+	mt9v111_device.coreReg->addressSelect = MT9V111I_SEL_SCA;
 
-	num_clock_per_row = (MT9V111_MAX_WIDTH + 114 + MT9V111_HORZBLANK_MIN)
-			* 2;
-	max_rate = mclk / (num_clock_per_row *
-			   (MT9V111_MAX_HEIGHT + MT9V111_VERTBLANK_DEFAULT));
+	/* MT9V111I_ADDR_SPACE_SEL */
+	mt9v111_device.ifpReg->addrSpaceSel = MT9V111I_SEL_IFP;
 
-	if ((*frame_rate > max_rate) || (*frame_rate == 0)) {
-		*frame_rate = max_rate;
-	}
+	/* Recommended values for 30fps @ 27MHz from datasheet*/
 
-	mt9v111_device.coreReg->verticalBlanking
-	    = mclk / (*frame_rate * num_clock_per_row) - MT9V111_MAX_HEIGHT;
+	/* Core R5=132, R6=10 , R7[4]=0 (DEFAULT) ,R33=58369*/
 
-	reset_frame_rate = *frame_rate;
-}
+	mt9v111_device.coreReg->horizontalBlanking = 132;
+	mt9v111_device.coreReg->verticalBlanking = 10;
+	mt9v111_device.coreReg->reserved33 = 58369;
 
-/*!
- * MT9V111 sensor configuration
- */
-void mt9v111_config(void)
-{
-	pr_debug("In mt9v111_config\n");
+	/* IFP R51(0x33)=5137,R57(0x39)=290,R59(0x3B)=1068,R62(0x3E)=4095,R89(0x59)=504,R90(0x5A)=605,R92(0x5C)=8222,R93(0x5D)=10021,R100(0x64)=4477 */
 
-	mt9v111_device.coreReg->addressSelect = MT9V111I_SEL_SCA;
-	mt9v111_device.ifpReg->addrSpaceSel = MT9V111I_SEL_IFP;
+	mt9v111_device.ifpReg->limitSharpSatuCtrl = 5137;
+	mt9v111_device.ifpReg->upperShutterDelayLi = 290;
+	mt9v111_device.ifpReg->ipfBlackLevelSub = 1068;
+	mt9v111_device.ifpReg->agimnThreCamAdj = 4095;
 
-	mt9v111_device.coreReg->windowHeight = MT9V111_WINHEIGHT;
-	mt9v111_device.coreReg->windowWidth = MT9V111_WINWIDTH;
-	mt9v111_device.coreReg->zoomColStart = 0;
-	mt9v111_device.coreReg->zomRowStart = 0;
-	mt9v111_device.coreReg->digitalZoom = 0x0;
-
-	mt9v111_device.coreReg->verticalBlanking = MT9V111_VERTBLANK_DEFAULT;
-	mt9v111_device.coreReg->horizontalBlanking = MT9V111_HORZBLANK_MIN;
-	mt9v111_device.coreReg->pixelClockSpeed = 0;
-	mt9v111_device.coreReg->readMode = 0xd0a1;
-
-	mt9v111_device.ifpReg->outputFormatCtrl2 = 0;
-	mt9v111_device.ifpReg->gainLimitAE = 0x300;
-	mt9v111_device.ifpReg->AESpeed = 0x80;
-
-	/* here is the default value */
-	mt9v111_device.ifpReg->formatControl = 0xc800;
-	mt9v111_device.ifpReg->modeControl = 0x708e;
-	mt9v111_device.ifpReg->awbSpeed = 0x4514;
-	mt9v111_device.coreReg->shutterWidth = 0xf8;
-
-	/* output size */
-	mt9v111_device.ifpReg->HPan = 0;
-	mt9v111_device.ifpReg->HZoom = MT9V111_MAX_WIDTH;
-	mt9v111_device.ifpReg->HSize = MT9V111_MAX_WIDTH;
-	mt9v111_device.ifpReg->VPan = 0;
-	mt9v111_device.ifpReg->VZoom = MT9V111_MAX_HEIGHT;
-	mt9v111_device.ifpReg->VSize = MT9V111_MAX_HEIGHT;
+	mt9v111_device.ifpReg->shutter_width_60 = 504;
+	mt9v111_device.ifpReg->auto_exposure_17 = 605;
+	mt9v111_device.ifpReg->search_flicker_60 = 8222;
+	mt9v111_device.ifpReg->reserved93 = 10021;
+	mt9v111_device.ifpReg->reserved100 = 4477;
 }
 
+
 /*!
  * mt9v111 sensor set saturtionn
  *
@@ -331,7 +263,7 @@ void mt9v111_config(void)
 
  * @return  Error code of 0.
  */
-static int mt9v111_set_saturation(int saturation)
+static int mt9v111_set_saturation(int sensorid , int saturation)
 {
 	u8 reg;
 	u16 data;
@@ -357,6 +289,9 @@ static int mt9v111_set_saturation(int saturation)
 	case 25:
 		mt9v111_device.ifpReg->awbSpeed = 0x6514;
 		break;
+	case 0:
+		mt9v111_device.ifpReg->awbSpeed = 0x7514;
+		break;
 	default:
 		mt9v111_device.ifpReg->awbSpeed = 0x4514;
 		break;
@@ -364,12 +299,348 @@ static int mt9v111_set_saturation(int saturation)
 
 	reg = MT9V111I_ADDR_SPACE_SEL;
 	data = mt9v111_device.ifpReg->addrSpaceSel;
-	mt9v111_write_reg(reg, data);
+	mt9v111_write_reg(sensorid,reg, data);
 
 	/* Operation Mode Control */
 	reg = MT9V111I_AWB_SPEED;
 	data = mt9v111_device.ifpReg->awbSpeed;
-	mt9v111_write_reg(reg, data);
+	mt9v111_write_reg(sensorid,reg, data);
+
+	return 0;
+}
+
+#if 0
+/*!
+ * mt9v111 sensor set digital zoom
+ *
+ * @param on/off   int
+
+ * @return  0 on success, -1 on error.
+ */
+static int mt9v111_set_digitalzoom(int sensorid , unsigned int on)
+{
+	u8 reg;
+	u16 data;
+	pr_debug("In mt9v111_set_digitalzoom(%d)\n",on);
+
+	if( on > 1 )
+	    return -1;
+
+	mt9v111_device.coreReg->digitalZoom = on;
+
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = mt9v111_device.coreReg->addressSelect;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	/* Operation Mode Control */
+	reg = MT9V111S_DIGITAL_ZOOM;
+	data = mt9v111_device.coreReg->digitalZoom;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	return 0;
+}
+
+/*!
+ * mt9v111 sensor set digital pan
+ *
+ * @param pan_level   int
+
+ * @return  0 on success, -1 on error.
+ */
+static int mt9v111_set_digitalpan (int sensorid , int pan_level)
+{
+	u8 reg;
+	u16 data;
+	pr_debug("In mt9v111_set_digitalpan(%d)\n",
+		pan_level);
+
+	mt9v111_device.ifpReg->HPan = 8;
+	if (pan_level & 0xFFFF0000) {
+		pan_level = (0xFFFFFFFF - pan_level);
+		pan_level = pan_level / 0x14;
+		mt9v111_device.ifpReg->HPan =
+			mt9v111_device.ifpReg->HPan - (pan_level & 0x3FF);
+	} else {
+		pan_level = pan_level / 0x14;
+		mt9v111_device.ifpReg->HPan =
+			mt9v111_device.ifpReg->HPan + (pan_level - 1);
+	}
+
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = mt9v111_device.ifpReg->addrSpaceSel;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	/* Operation Mode Control */
+	reg = MT9V111i_H_PAN;
+	data = mt9v111_device.ifpReg->HPan;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	return 0;
+}
+
+/*!
+ * mt9v111 sensor set digital tilt
+ *
+ * @param tilt_level   int
+
+ * @return  0 on success, -1 on error.
+ */
+static int mt9v111_set_digitaltilt (int sensorid , int tilt_level)
+{
+	u8 reg;
+	u16 data;
+	pr_debug("In mt9v111_set_digitaltilt(%d)\n",
+		tilt_level);
+
+	mt9v111_device.ifpReg->VPan = 8;
+        if( tilt_level & 0xFFFF0000 ) {
+				tilt_level = (0xFFFFFFFF - tilt_level);
+				tilt_level = tilt_level / 0x14;
+                mt9v111_device.ifpReg->VPan = mt9v111_device.ifpReg->VPan - (tilt_level & 0x3FF);
+        }
+        else {
+				tilt_level = tilt_level / 0x14;
+                mt9v111_device.ifpReg->VPan = mt9v111_device.ifpReg->VPan + (tilt_level - 1);
+        }
+
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = mt9v111_device.ifpReg->addrSpaceSel;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	/* Operation Mode Control */
+	reg = MT9V111i_V_PAN;
+	data = mt9v111_device.ifpReg->VPan;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	return 0;
+}
+
+/*!
+ * mt9v111 sensor set output resolution
+ *
+ * @param resolution   res
+
+ * @return  0 on success, -1 on error.
+ */
+static int mt9v111_set_outputresolution(int sensorid , MT9V111_OutputResolution res)
+{
+	u8 reg;
+	u16 data;
+	int zoom = 0;
+
+	pr_debug("In mt9v111_set_outputresolution(%d)\n",res);
+
+	switch (res) {
+	    case MT9V111_OutputResolution_VGA:
+			/* 640x480 */
+			mt9v111_device.ifpReg->HSize = 0x0280;
+			mt9v111_device.ifpReg->VSize = 0x01E0;
+			break;
+
+	    case MT9V111_OutputResolution_QVGA:
+			/* 320x240 */
+			mt9v111_device.ifpReg->HSize = 0x0140;
+			mt9v111_device.ifpReg->VSize = 0x00F0;
+			break;
+
+	    case MT9V111_OutputResolution_CIF:
+			/* 352x288 */
+			mt9v111_device.ifpReg->HSize = 0x0160;
+			mt9v111_device.ifpReg->VSize = 0x0120;
+			mt9v111_device.ifpReg->HZoom = 0x0160;
+			mt9v111_device.ifpReg->VZoom = 0x0120;
+			zoom = 1;
+			break;
+
+	    case MT9V111_OutputResolution_QCIF:
+			/* 176X220 */
+			mt9v111_device.ifpReg->HSize = 0x00B0;
+			mt9v111_device.ifpReg->VSize = 0x0090;
+			mt9v111_device.ifpReg->HZoom = 0x00B0;
+			mt9v111_device.ifpReg->VZoom = 0x0090;
+			zoom = 1;
+			break;
+
+	    case MT9V111_OutputResolution_QQVGA:
+			/* 2048*1536 */
+			mt9v111_device.ifpReg->HSize = 0x00A0;
+			mt9v111_device.ifpReg->VSize = 0x0078;
+			mt9v111_device.ifpReg->HZoom = 0x00A0;
+			mt9v111_device.ifpReg->VZoom = 0x0078;
+			zoom = 1;
+			break;
+
+	    case MT9V111_OutputResolution_SXGA:
+		/* 1280x1024 */
+			break;
+
+		default:
+			break;
+	}
+
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = mt9v111_device.ifpReg->addrSpaceSel;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	reg = MT9V111i_V_SIZE;
+	data = mt9v111_device.ifpReg->VSize;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	reg = MT9V111i_H_SIZE;
+	data = mt9v111_device.ifpReg->HSize;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	if ( zoom ) {
+	    reg = MT9V111i_V_ZOOM;
+	    data = mt9v111_device.ifpReg->VZoom;
+	    mt9v111_write_reg(sensorid,reg, data);
+
+	    reg = MT9V111i_H_ZOOM;
+	    data = mt9v111_device.ifpReg->HZoom;
+	    mt9v111_write_reg(sensorid,reg, data);
+	}
+
+	return 0;
+}
+
+/*!
+ * mt9v111 sensor set digital flash
+ *
+ * @param flash_level   int
+
+ * @return  0 on success, -1 on error.
+ */
+static int mt9v111_set_digitalflash (int sensorid , int flash_level)
+{
+	u8 reg;
+	u16 data = mt9v111_read_reg(sensorid,MT9V111i_FLASH_CTRL);
+	pr_debug("In mt9v111_set_digitalflash(%d)\n",
+			flash_level);
+
+	if(flash_level) {
+	    data &= (0xFF00);
+	    data |= ((flash_level & 0x00FF) | (1<<13));
+	}
+	else {
+	    data &= ~(1<<13);
+	}
+
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = mt9v111_device.ifpReg->addrSpaceSel;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	/* Operation Mode Control */
+	reg = MT9V111i_FLASH_CTRL;
+	mt9v111_device.ifpReg->flashCtrl = data;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	return 0;
+}
+
+/*!
+ * mt9v111 sensor set digital monochrome
+ *
+ * @param on   int
+
+ * @return  0 on success, -1 on error.
+ */
+static int mt9v111_set_digitalmonochrome (int sensorid , int on)
+{
+	u8 reg;
+	u16 data = mt9v111_read_reg(sensorid,MT9V111I_FORMAT_CONTROL);
+	pr_debug("In mt9v111_set_digitalmonochrome(%d)\n",
+			on);
+
+        /* clear the monochrome bit field */
+        data &= ~(1<<5);
+
+         /* enable or disable monochrome mode */
+         if( on )
+                 data |= (0<<5);
+         else
+                 data |= (1<<5);
+
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = mt9v111_device.ifpReg->addrSpaceSel;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	/* Operation Mode Control */
+	reg = MT9V111I_FORMAT_CONTROL;
+	mt9v111_device.ifpReg->formatControl = data;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	return 0;
+}
+#endif
+
+/*!
+ * mt9v111 sensor set digital sharpness
+ *
+ * @param value   int
+
+ * @return  0 on success, -1 on error.
+ */
+static int mt9v111_set_digitalsharpness (int sensorid , int value)
+{
+	u8 reg;
+	u16 data ;
+
+	pr_debug("In mt9v111_set_digitalsharpness(%d)\n",value);
+
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = mt9v111_device.ifpReg->addrSpaceSel;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	data = mt9v111_read_reg(sensorid,MT9V111I_APERTURE_GAIN);
+
+	/* erase current and remove auto reduce sharpness in low light */
+	 data &= ~(0x000F);
+	 data |= (value & (0x000F));
+	 if( data > (0x000F) )
+			 return -1;
+
+	/* Operation Mode Control */
+	reg = MT9V111I_APERTURE_GAIN;
+	mt9v111_device.ifpReg->apertureGain = data;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	return 0;
+}
+
+/*!
+ * mt9v111 sensor set digital brightness
+ *
+ * @param value   int
+
+ * @return  0 on success, -1 on error.
+ */
+static int mt9v111_set_digitalbrightness (int sensorid , int value)
+{
+	u8 reg;
+	u16 data;
+	u32 max_brightness, min_brightness;
+
+	data = mt9v111_read_reg(sensorid,MT9V111I_CLIP_LIMIT_OUTPUT_LUMI);
+	max_brightness = data >> 8;
+	min_brightness = (u8)data;
+
+	if( value > max_brightness )
+		value = max_brightness;
+	else if( value < min_brightness )
+		value = min_brightness;
+
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = mt9v111_device.ifpReg->addrSpaceSel;
+	mt9v111_write_reg(sensorid,reg, data);
+
+	data = mt9v111_read_reg(sensorid,MT9V111I_AE_PRECISION_TARGET);
+	data &= 0xFF00; /* Clear target luminance */
+	data |= ((u8)value );
+
+	/* Operation Mode Control */
+	reg = MT9V111I_AE_PRECISION_TARGET;
+	mt9v111_device.ifpReg->AEPrecisionTarget = data;
+	mt9v111_write_reg(sensorid,reg, data);
 
 	return 0;
 }
@@ -380,7 +651,7 @@ static int mt9v111_set_saturation(int saturation)
  * @param ae_mode      int
  * @return  Error code of 0 (no Error)
  */
-static int mt9v111_set_ae_mode(int ae_mode)
+static int mt9v111_set_ae_mode(int sensorid , int ae_mode)
 {
 	u8 reg;
 	u16 data;
@@ -408,19 +679,20 @@ static int mt9v111_set_ae_mode(int ae_mode)
 	/* V4L2_EXPOSURE_MANUAL = 1 needs register setting of 0x308E */
 	mt9v111_device.ifpReg->modeControl &= 0x3fff;
 	mt9v111_device.ifpReg->modeControl |= (ae_mode & 0x03) << 14;
-	mt9v111_data.ae_mode = ae_mode;
+	mt9v111_data[sensorid].ae_mode = ae_mode;
 
 	reg = MT9V111I_ADDR_SPACE_SEL;
 	data = mt9v111_device.ifpReg->addrSpaceSel;
-	mt9v111_write_reg(reg, data);
+	mt9v111_write_reg(sensorid,reg, data);
 
 	reg = MT9V111I_MODE_CONTROL;
 	data = mt9v111_device.ifpReg->modeControl;
-	mt9v111_write_reg(reg, data);
+	mt9v111_write_reg(sensorid,reg, data);
 
 	return 0;
 }
 
+#if 0
 /*!
  * mt9v111 sensor get AE measurement window mode configuration
  *
@@ -435,6 +707,7 @@ static void mt9v111_get_ae_mode(int *ae_mode)
 		*ae_mode = (mt9v111_device.ifpReg->modeControl & 0xc) >> 2;
 	}
 }
+#endif
 
 #ifdef MT9V111_DEBUG
 /*!
@@ -442,33 +715,33 @@ static void mt9v111_get_ae_mode(int *ae_mode)
  *
  * @return none
  */
-static void mt9v111_test_pattern(bool flag)
+static void mt9v111_test_pattern(int sensorid , bool flag)
 {
 	u16 data;
 
 	/* switch to sensor registers */
-	mt9v111_write_reg(MT9V111I_ADDR_SPACE_SEL, MT9V111I_SEL_SCA);
+	mt9v111_write_reg(sensorid,MT9V111I_ADDR_SPACE_SEL, MT9V111I_SEL_SCA);
 
 	if (flag == true) {
 		testpattern = MT9V111S_OUTCTRL_TEST_MODE;
 
-		data = mt9v111_read_reg(MT9V111S_ROW_NOISE_CTRL) & 0xBF;
-		mt9v111_write_reg(MT9V111S_ROW_NOISE_CTRL, data);
+		data = mt9v111_read_reg(sensorid,MT9V111S_ROW_NOISE_CTRL) & 0xBF;
+		mt9v111_write_reg(sensorid,MT9V111S_ROW_NOISE_CTRL, data);
 
-		mt9v111_write_reg(MT9V111S_TEST_DATA, 0);
+		mt9v111_write_reg(sensorid,MT9V111S_TEST_DATA, 0);
 
 		/* changes take effect */
 		data = MT9V111S_OUTCTRL_CHIP_ENABLE | testpattern | 0x3000;
-		mt9v111_write_reg(MT9V111S_OUTPUT_CTRL, data);
+		mt9v111_write_reg(sensorid,MT9V111S_OUTPUT_CTRL, data);
 	} else {
 		testpattern = 0;
 
-		data = mt9v111_read_reg(MT9V111S_ROW_NOISE_CTRL) | 0x40;
+		data = mt9v111_read_reg(sensorid,MT9V111S_ROW_NOISE_CTRL) | 0x40;
 		mt9v111_write_reg(MT9V111S_ROW_NOISE_CTRL, data);
 
 		/* changes take effect */
 		data = MT9V111S_OUTCTRL_CHIP_ENABLE | testpattern | 0x3000;
-		mt9v111_write_reg(MT9V111S_OUTPUT_CTRL, data);
+		mt9v111_write_reg(sensorid,MT9V111S_OUTPUT_CTRL, data);
 	}
 }
 #endif
@@ -507,6 +780,7 @@ static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
 	p->u.bt656.clock_curr = MT9V111_MCLK;
 	p->if_type = V4L2_IF_TYPE_BT656;
 	p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+	p->u.bt656.bt_sync_correct = 1;	// translates to CSI ext vsync
 	p->u.bt656.clock_min = MT9V111_CLK_MIN;
 	p->u.bt656.clock_max = MT9V111_CLK_MAX;
 
@@ -534,10 +808,12 @@ static int ioctl_s_power(struct v4l2_int_device *s, int on)
 
 	sensor->on = on;
 
-	if (on)
-		gpio_sensor_active();
-	else
-		gpio_sensor_inactive();
+	if(on) {
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, 0 /* cam->csi */, true, true);
+	}
+	else {
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, 0 /* cam->csi */, false, false);
+	}
 
 	return 0;
 }
@@ -554,19 +830,23 @@ static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
 	int ret = 0;
 	struct v4l2_captureparm *cparm = &a->parm.capture;
 	/* s->priv points to mt9v111_data */
+	int sensorid = mt9v111_id_from_name(((struct sensor *)s->priv)->v4l2_int_device->name);
 
 	pr_debug("In mt9v111:ioctl_g_parm\n");
 
+	if( sensorid < 0 )
+		return ret;
+
 	switch (a->type) {
 	/* This is the only case currently handled. */
 	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
 		pr_debug("   type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
 		memset(a, 0, sizeof(*a));
 		a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-		cparm->capability = mt9v111_data.streamcap.capability;
+		cparm->capability = mt9v111_data[sensorid].streamcap.capability;
 		cparm->timeperframe =
-				mt9v111_data.streamcap.timeperframe;
-		cparm->capturemode = mt9v111_data.streamcap.capturemode;
+				mt9v111_data[sensorid].streamcap.timeperframe;
+		cparm->capturemode = mt9v111_data[sensorid].streamcap.capturemode;
 		ret = 0;
 		break;
 
@@ -605,9 +885,13 @@ static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
 	int ret = 0;
 	struct v4l2_captureparm *cparm = &a->parm.capture;
 	/* s->priv points to mt9v111_data */
+	int sensorid = mt9v111_id_from_name(((struct sensor *)s->priv)->v4l2_int_device->name);
 
 	pr_debug("In mt9v111:ioctl_s_parm\n");
 
+	if( sensorid < 0 )
+		return ret;
+
 	switch (a->type) {
 	/* This is the only case currently handled. */
 	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
@@ -617,13 +901,13 @@ static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
 		 * Changing the frame rate is not allowed on this
 		 *camera. */
 		if (cparm->timeperframe.denominator !=
-		    mt9v111_data.streamcap.timeperframe.denominator) {
+		    mt9v111_data[sensorid].streamcap.timeperframe.denominator) {
 			pr_err("ERROR: mt9v111: ioctl_s_parm: " \
 			       "This camera does not allow frame rate "
 			       "changes.\n");
 			ret = -EINVAL;
 		} else {
-			mt9v111_data.streamcap.timeperframe =
+			mt9v111_data[sensorid].streamcap.timeperframe =
 						cparm->timeperframe;
 		      /* Call any camera functions to match settings. */
 		}
@@ -635,7 +919,7 @@ static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
 				"unsupported capture mode\n");
 			ret  = -EINVAL;
 		} else {
-			mt9v111_data.streamcap.capturemode =
+			mt9v111_data[sensorid].streamcap.capturemode =
 						cparm->capturemode;
 		      /* Call any camera functions to match settings. */
 		      /* Right now this camera only supports 1 mode. */
@@ -685,6 +969,7 @@ static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
 	return 0;
 }
 
+#if 0
 /*!
  * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl
  * @s: pointer to standard V4L2 device structure
@@ -700,6 +985,7 @@ static int ioctl_queryctrl(struct v4l2_int_device *s, struct v4l2_queryctrl *qc)
 
 	return 0;
 }
+#endif
 
 /*!
  * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
@@ -712,66 +998,29 @@ static int ioctl_queryctrl(struct v4l2_int_device *s, struct v4l2_queryctrl *qc)
  */
 static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
 {
+	int sensorid = mt9v111_id_from_name(((struct sensor *)s->priv)->v4l2_int_device->name);
+
 	pr_debug("In mt9v111:ioctl_g_ctrl\n");
 
+	if( sensorid < 0 )
+		return 0;
+
 	switch (vc->id) {
 	case V4L2_CID_BRIGHTNESS:
 		pr_debug("   V4L2_CID_BRIGHTNESS\n");
-		vc->value = mt9v111_data.brightness;
-		break;
-	case V4L2_CID_CONTRAST:
-		pr_debug("   V4L2_CID_CONTRAST\n");
-		vc->value = mt9v111_data.contrast;
+		vc->value = mt9v111_data[sensorid].brightness;
 		break;
 	case V4L2_CID_SATURATION:
 		pr_debug("   V4L2_CID_SATURATION\n");
-		vc->value = mt9v111_data.saturation;
-		break;
-	case V4L2_CID_HUE:
-		pr_debug("   V4L2_CID_HUE\n");
-		vc->value = mt9v111_data.hue;
-		break;
-	case V4L2_CID_AUTO_WHITE_BALANCE:
-		pr_debug(
-			"   V4L2_CID_AUTO_WHITE_BALANCE\n");
-		vc->value = 0;
-		break;
-	case V4L2_CID_DO_WHITE_BALANCE:
-		pr_debug(
-			"   V4L2_CID_DO_WHITE_BALANCE\n");
-		vc->value = 0;
-		break;
-	case V4L2_CID_RED_BALANCE:
-		pr_debug("   V4L2_CID_RED_BALANCE\n");
-		vc->value = mt9v111_data.red;
-		break;
-	case V4L2_CID_BLUE_BALANCE:
-		pr_debug("   V4L2_CID_BLUE_BALANCE\n");
-		vc->value = mt9v111_data.blue;
-		break;
-	case V4L2_CID_GAMMA:
-		pr_debug("   V4L2_CID_GAMMA\n");
-		vc->value = 0;
+		vc->value = mt9v111_data[sensorid].saturation;
 		break;
 	case V4L2_CID_EXPOSURE:
 		pr_debug("   V4L2_CID_EXPOSURE\n");
-		vc->value = mt9v111_data.ae_mode;
-		break;
-	case V4L2_CID_AUTOGAIN:
-		pr_debug("   V4L2_CID_AUTOGAIN\n");
-		vc->value = 0;
+		vc->value = mt9v111_data[sensorid].ae_mode;
 		break;
 	case V4L2_CID_GAIN:
 		pr_debug("   V4L2_CID_GAIN\n");
-		vc->value = 0;
-		break;
-	case V4L2_CID_HFLIP:
-		pr_debug("   V4L2_CID_HFLIP\n");
-		vc->value = 0;
-		break;
-	case V4L2_CID_VFLIP:
-		pr_debug("   V4L2_CID_VFLIP\n");
-		vc->value = 0;
+		vc->value = mt9v111_data[sensorid].gain;
 		break;
 	default:
 		pr_debug("   Default case\n");
@@ -794,56 +1043,34 @@ static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
 static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
 {
 	int retval = 0;
+	int sensorid = mt9v111_id_from_name(((struct sensor *)s->priv)->v4l2_int_device->name);
 
 	pr_debug("In mt9v111:ioctl_s_ctrl %d\n",
 		vc->id);
 
+	if( sensorid < 0 )
+		return retval;
+
 	switch (vc->id) {
 	case V4L2_CID_BRIGHTNESS:
 		pr_debug("   V4L2_CID_BRIGHTNESS\n");
-		break;
-	case V4L2_CID_CONTRAST:
-		pr_debug("   V4L2_CID_CONTRAST\n");
+		mt9v111_set_digitalbrightness(sensorid,vc->value);
+		mt9v111_data[sensorid].brightness = vc->value;
 		break;
 	case V4L2_CID_SATURATION:
 		pr_debug("   V4L2_CID_SATURATION\n");
-		retval = mt9v111_set_saturation(vc->value);
-		break;
-	case V4L2_CID_HUE:
-		pr_debug("   V4L2_CID_HUE\n");
-		break;
-	case V4L2_CID_AUTO_WHITE_BALANCE:
-		pr_debug(
-			"   V4L2_CID_AUTO_WHITE_BALANCE\n");
-		break;
-	case V4L2_CID_DO_WHITE_BALANCE:
-		pr_debug(
-			"   V4L2_CID_DO_WHITE_BALANCE\n");
-		break;
-	case V4L2_CID_RED_BALANCE:
-		pr_debug("   V4L2_CID_RED_BALANCE\n");
-		break;
-	case V4L2_CID_BLUE_BALANCE:
-		pr_debug("   V4L2_CID_BLUE_BALANCE\n");
-		break;
-	case V4L2_CID_GAMMA:
-		pr_debug("   V4L2_CID_GAMMA\n");
+		retval = mt9v111_set_saturation(sensorid,vc->value);
+		mt9v111_data[sensorid].saturation = vc->value;
 		break;
 	case V4L2_CID_EXPOSURE:
 		pr_debug("   V4L2_CID_EXPOSURE\n");
-		retval = mt9v111_set_ae_mode(vc->value);
-		break;
-	case V4L2_CID_AUTOGAIN:
-		pr_debug("   V4L2_CID_AUTOGAIN\n");
+		retval = mt9v111_set_ae_mode(sensorid,vc->value);
+		mt9v111_data[sensorid].ae_mode = vc->value;
 		break;
 	case V4L2_CID_GAIN:
 		pr_debug("   V4L2_CID_GAIN\n");
-		break;
-	case V4L2_CID_HFLIP:
-		pr_debug("   V4L2_CID_HFLIP\n");
-		break;
-	case V4L2_CID_VFLIP:
-		pr_debug("   V4L2_CID_VFLIP\n");
+		mt9v111_set_digitalsharpness(sensorid,vc->value);
+		mt9v111_data[sensorid].gain = vc->value;
 		break;
 	default:
 		pr_debug("   Default case\n");
@@ -854,13 +1081,41 @@ static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
 	return retval;
 }
 
+static void mt9v111_ifp_reset ( int sensorid )
+{
+	mt9v111_write_reg(sensorid,MT9V111S_ADDR_SPACE_SEL, 0x0001);
+	mt9v111_write_reg(sensorid,MT9V111I_SOFT_RESET, 0x0001);
+	msleep(100);
+	mt9v111_write_reg(sensorid,MT9V111I_SOFT_RESET, 0x0000);
+	msleep(100);
+}
+
+static void mt9v111_sensor_reset ( int sensorid )
+{
+	mt9v111_write_reg(sensorid,MT9V111S_ADDR_SPACE_SEL, 0x0004);
+	mt9v111_write_reg(sensorid,MT9V111S_RESET, 0x0001);
+	msleep(100);
+	mt9v111_write_reg(sensorid,MT9V111S_RESET, 0x0000);
+	msleep(100);
+}
+
 /*!
  * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
  * @s: pointer to standard V4L2 device structure
  */
 static int ioctl_init(struct v4l2_int_device *s)
 {
-	pr_debug("In mt9v111:ioctl_init\n");
+	int sensorid = 0;
+
+	sensorid = mt9v111_id_from_name(((struct sensor *)s->priv)->v4l2_int_device->name);
+	if( sensorid < 0 )
+		return 0;
+
+	pr_debug("In mt9v111:ioctl_init for sensor %d\n",sensorid);
+
+	mt9v111_sensor_reset(sensorid);
+	mt9v111_ifp_reset(sensorid);
+	mt9v111_sensor_lib_datasheet(sensorid,mt9v111_device.coreReg, mt9v111_device.ifpReg);
 
 	return 0;
 }
@@ -873,19 +1128,146 @@ static int ioctl_init(struct v4l2_int_device *s)
  */
 static int ioctl_dev_init(struct v4l2_int_device *s)
 {
+	int sensorid = 0;
 	uint32_t clock_rate = MT9V111_MCLK;
 
+	sensorid = mt9v111_id_from_name(((struct sensor *)s->priv)->v4l2_int_device->name);
+	if( sensorid < 0 )
+		return 0;
+
 	pr_debug("In mt9v111:ioctl_dev_init\n");
 
-	gpio_sensor_active();
+	set_mclk_rate(&clock_rate, 0);	// Both sensors use mclk0 on Digi ccwmx51
+
+	mt9v111_sensor_reset(sensorid);
+	mt9v111_ifp_reset(sensorid);
+	mt9v111_sensor_lib_datasheet(sensorid,mt9v111_device.coreReg, mt9v111_device.ifpReg);
 
-	set_mclk_rate(&clock_rate);
-	mt9v111_rate_cal(&reset_frame_rate, clock_rate);
-	mt9v111_sensor_lib(mt9v111_device.coreReg, mt9v111_device.ifpReg);
+	return 0;
+}
+
+/* list of image formats supported by sensor */
+static const struct v4l2_fmtdesc mt9v111_formats[] = {
+	{
+		.description = "RGB565",
+		.pixelformat = V4L2_PIX_FMT_RGB565,
+	},
+	{
+		.description = "YUV422 UYVY",
+		.pixelformat = V4L2_PIX_FMT_UYVY,
+	},
+};
+
+#define MT9V111_NUM_CAPTURE_FORMATS	ARRAY_SIZE(mt9v111_formats)
+
+static int ioctl_enum_fmt_cap(struct v4l2_int_device *s,
+				   struct v4l2_fmtdesc *fmt)
+{
+	int index = fmt->index;
+
+	switch (fmt->type) {
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		if (index >= MT9V111_NUM_CAPTURE_FORMATS)
+			return -EINVAL;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	fmt->flags = mt9v111_formats[index].flags;
+	strlcpy(fmt->description, mt9v111_formats[index].description,
+		sizeof(fmt->description));
+	fmt->pixelformat = mt9v111_formats[index].pixelformat;
 
 	return 0;
 }
 
+static int ioctl_s_fmt_cap(struct v4l2_int_device *s,
+			struct v4l2_format *f)
+{
+	unsigned short reg;
+	int sensorid = mt9v111_id_from_name(((struct sensor *)s->priv)->v4l2_int_device->name);
+	struct sensor *sensor = s->priv;
+	/* s->priv points to mt9v111_data */
+
+	if( sensorid < 0 )
+		return -ENODEV;
+
+	/* Select IFP registers */
+	mt9v111_write_reg (sensorid,MT9V111S_ADDR_SPACE_SEL, 0x0001);
+
+	switch (f->fmt.pix.pixelformat) {
+		case V4L2_PIX_FMT_RGB565:
+			/*MT9V111I_OUTPUT_FORMAT_CTRL2*/
+			reg = mt9v111_read_reg (sensorid,MT9V111I_OUTPUT_FORMAT_CTRL2);
+			reg &= ~(0x3 << 6);
+			mt9v111_write_reg (sensorid,MT9V111I_OUTPUT_FORMAT_CTRL2, reg);
+
+			/* MT9V111I_FORMAT_CONTROL */
+			reg = mt9v111_read_reg(sensorid,MT9V111I_FORMAT_CONTROL);
+			reg |= 1 << 12;
+			mt9v111_write_reg(sensorid,MT9V111I_FORMAT_CONTROL, reg);
+			break;
+
+		case V4L2_PIX_FMT_YUV444:
+		case V4L2_PIX_FMT_UYVY:
+		case V4L2_PIX_FMT_YVU420:
+		case V4L2_PIX_FMT_YUYV:
+			/* MT9V111I_FORMAT_CONTROL */
+			reg = mt9v111_read_reg(sensorid,MT9V111I_FORMAT_CONTROL);
+			reg &= ~(1 << 12);
+			mt9v111_write_reg(sensorid,MT9V111I_FORMAT_CONTROL, reg);
+			break;
+
+		default:
+			return -EINVAL;
+	}
+
+	sensor->pix.width = f->fmt.pix.width;
+	sensor->pix.height = f->fmt.pix.height;
+	sensor->pix.sizeimage = f->fmt.pix.sizeimage;
+	sensor->pix.pixelformat = f->fmt.pix.pixelformat;
+	return 0;
+}
+
+static int ioctl_try_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
+{
+	int i;
+
+	if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+		return -EINVAL;
+
+	for( i=0 ; i < MT9V111_NUM_CAPTURE_FORMATS ; i++) {
+		if( f->fmt.pix.pixelformat == mt9v111_formats[i].pixelformat )
+			return 0;
+	}
+
+	return -EINVAL;
+}
+
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+static int ioctl_get_register(struct v4l2_int_device *s,struct v4l2_dbg_register * dreg)
+{
+	int sensorid = mt9v111_id_from_name(((struct sensor *)s->priv)->v4l2_int_device->name);
+
+	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, 0 /* cam->csi */ , true, true);
+	dreg->val = mt9v111_read_reg (sensorid,dreg->reg);
+	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, 0 /* cam->csi */ , false, false);
+	return 0;
+}
+
+static int ioctl_set_register(struct v4l2_int_device *s,struct v4l2_dbg_register * dreg)
+{
+	int sensorid = mt9v111_id_from_name(((struct sensor *)s->priv)->v4l2_int_device->name);
+
+	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, 0 /* cam->csi */ , true, true);
+	mt9v111_write_reg (sensorid,dreg->reg, dreg->val);
+	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, 0 /* cam->csi */ , false, false);
+	return 0;
+}
+#endif
+
 /*!
  * This structure defines all the ioctls for this module and links them to the
  * enumeration.
@@ -910,16 +1292,23 @@ static struct v4l2_int_ioctl_desc mt9v111_ioctl_desc[] = {
 	/*!
 	 * VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type.
 	 */
-/*	{vidioc_int_enum_fmt_cap_num,
-				(v4l2_int_ioctl_func *) ioctl_enum_fmt_cap}, */
+	{vidioc_int_enum_fmt_cap_num,
+				(v4l2_int_ioctl_func *) ioctl_enum_fmt_cap},
+
 
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+	{vidioc_int_g_register_num,
+				(v4l2_int_ioctl_func *) ioctl_get_register},
+	{vidioc_int_s_register_num,
+				(v4l2_int_ioctl_func *) ioctl_set_register},
+#endif
 	/*!
 	 * VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type.
 	 * This ioctl is used to negotiate the image capture size and
 	 * pixel format without actually making it take effect.
 	 */
-/*	{vidioc_int_try_fmt_cap_num,
-				(v4l2_int_ioctl_func *) ioctl_try_fmt_cap}, */
+	{vidioc_int_try_fmt_cap_num,
+				(v4l2_int_ioctl_func *) ioctl_try_fmt_cap},
 
 	{vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_g_fmt_cap},
 
@@ -928,7 +1317,7 @@ static struct v4l2_int_ioctl_desc mt9v111_ioctl_desc[] = {
 	 * format, returns error code if format not supported or HW can't be
 	 * correctly configured.
 	 */
-/*	{vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */
+	{vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap},
 
 	{vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm},
 	{vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm},
@@ -937,20 +1326,56 @@ static struct v4l2_int_ioctl_desc mt9v111_ioctl_desc[] = {
 	{vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl},
 };
 
-static struct v4l2_int_slave mt9v111_slave = {
-	.ioctls = mt9v111_ioctl_desc,
-	.num_ioctls = ARRAY_SIZE(mt9v111_ioctl_desc),
+static struct v4l2_int_slave mt9v111_slave[] = {
+	{
+		.ioctls = mt9v111_ioctl_desc,
+		.num_ioctls = ARRAY_SIZE(mt9v111_ioctl_desc),
+		.attach_to = "mxc_v4l2_cap_1",
+	},
+	{
+		.ioctls = mt9v111_ioctl_desc,
+		.num_ioctls = ARRAY_SIZE(mt9v111_ioctl_desc),
+		.attach_to = "mxc_v4l2_cap_2",
+	},
 };
 
-static struct v4l2_int_device mt9v111_int_device = {
-	.module = THIS_MODULE,
-	.name = "mt9v111",
-	.type = v4l2_int_type_slave,
-	.u = {
-		.slave = &mt9v111_slave,
+static struct v4l2_int_device mt9v111_int_device [] = {
+		{
+			.module = THIS_MODULE,
+			.type = v4l2_int_type_slave,
+			.u = {
+				.slave = &mt9v111_slave[0],
+				},
+		},
+		{
+			.module = THIS_MODULE,
+			.type = v4l2_int_type_slave,
+			.u = {
+				.slave = &mt9v111_slave[1],
+				},
 		},
 };
 
+static int mt9v111_read_id( int sensoridx )
+{
+	int sensorid = 0;
+	int ret = 0;
+
+	mt9v111_write_reg (sensoridx,MT9V111S_ADDR_SPACE_SEL, 0x0004);
+
+	sensorid = mt9v111_read_reg (sensoridx,MT9V111S_CHIP_VERSION);
+	if( sensorid == 0x823a )
+	{
+		printk(KERN_INFO" MT9V111 ID %x\n",sensorid);
+	}
+	else
+	{
+		printk(KERN_ERR" MT9V111 Could not detect sensor (read %x)\n",sensorid);
+		ret = -ENODEV;
+	}
+	return ret;
+}
+
 /*!
  * mt9v111 I2C probe function
  * Function set in i2c_driver struct.
@@ -962,32 +1387,56 @@ static int mt9v111_probe(struct i2c_client *client,
 			 const struct i2c_device_id *id)
 {
 	int retval;
+	int sensorid;
 
 	pr_debug("In mt9v111_probe  device id is %s\n", id->name);
 
+	sensorid = mt9v111_id_from_name(id->name);
+
+	if( sensorid < 0 )
+		return -ENODEV;
+
 	/* Set initial values for the sensor struct. */
-	memset(&mt9v111_data, 0, sizeof(mt9v111_data));
-	mt9v111_data.i2c_client = client;
+	memset(&mt9v111_data[sensorid], 0, sizeof(struct sensor));
+	mt9v111_data[sensorid].i2c_client = client;
 	pr_debug("   client name is %s\n", client->name);
-	mt9v111_data.pix.pixelformat = V4L2_PIX_FMT_UYVY;
-	mt9v111_data.pix.width = MT9V111_MAX_WIDTH;
-	mt9v111_data.pix.height = MT9V111_MAX_HEIGHT;
-	mt9v111_data.streamcap.capability = 0; /* No higher resolution or frame
-						* frame rate changes supported.
-						*/
-	mt9v111_data.streamcap.timeperframe.denominator = MT9V111_FRAME_RATE;
-	mt9v111_data.streamcap.timeperframe.numerator = 1;
+	mt9v111_data[sensorid].pix.pixelformat = V4L2_PIX_FMT_UYVY;
+	mt9v111_data[sensorid].pix.width = MT9V111_MAX_WIDTH;
+	mt9v111_data[sensorid].pix.height = MT9V111_MAX_HEIGHT;
+	mt9v111_data[sensorid].streamcap.capability = 0; /* No higher resolution or frame
+						* frame rate changes supported.*/
+	mt9v111_data[sensorid].streamcap.timeperframe.denominator = MT9V111_FRAME_RATE;
+	mt9v111_data[sensorid].streamcap.timeperframe.numerator = 1;
+
+	strcpy(mt9v111_int_device[sensorid].name,id->name);
+	pr_debug("   video device name is %s\n", mt9v111_data[sensorid].v4l2_int_device->name);
+	mt9v111_data[sensorid].v4l2_int_device = &mt9v111_int_device[sensorid];
+	mt9v111_int_device[sensorid].priv = &mt9v111_data[sensorid];
+
+	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, sensorid , true, true);
+
+	if( mt9v111_read_id(sensorid) != 0) {
+		printk(KERN_ERR"mt9v111_probe: No sensor found\n");
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, sensorid , false, false);
+		return -ENXIO;
+	}
 
-	mt9v111_int_device.priv = &mt9v111_data;
+#ifdef MT9V111_DEBUG
+	mt9v111_test_pattern(1);
+#endif
+
+	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, sensorid , false, false);
 
 	pr_debug("   type is %d (expect %d)\n",
-		mt9v111_int_device.type, v4l2_int_type_slave);
+		mt9v111_int_device[sensorid].type, v4l2_int_type_slave);
 	pr_debug("   num ioctls is %d\n",
-		mt9v111_int_device.u.slave->num_ioctls);
+		mt9v111_int_device[sensorid].u.slave->num_ioctls);
 
 	/* This function attaches this structure to the /dev/video0 device.
 	 * The pointer in priv points to the mt9v111_data structure here.*/
-	retval = v4l2_int_device_register(&mt9v111_int_device);
+	retval = v4l2_int_device_register(&mt9v111_int_device[sensorid]);
+	if( retval == 0 )
+		mt9v111_data[sensorid].used = 1;
 
 	return retval;
 }
@@ -998,9 +1447,14 @@ static int mt9v111_probe(struct i2c_client *client,
  */
 static int mt9v111_remove(struct i2c_client *client)
 {
+	int i;
+
 	pr_debug("In mt9v111_remove\n");
 
-	v4l2_int_device_unregister(&mt9v111_int_device);
+	for ( i=0 ; i < ARRAY_SIZE(mt9v111_int_device) ; i++ ) {
+		if( mt9v111_data[i].used )
+			v4l2_int_device_unregister(&mt9v111_int_device[i]);
+	}
 	return 0;
 }
 
@@ -1033,13 +1487,13 @@ static __init int mt9v111_init(void)
 	memset(mt9v111_device.ifpReg, 0, sizeof(mt9v111_IFPReg));
 
 	/* Set contents of the just created structures. */
-	mt9v111_config();
+	mt9v111_config_datasheet();
 
 	/* Tells the i2c driver what functions to call for this driver. */
 	err = i2c_add_driver(&mt9v111_i2c_driver);
 	if (err != 0)
 		pr_err("%s:driver registration failed, error=%d \n",
-		       __func__, err);
+			   __func__, err);
 
 	return err;
 }
@@ -1055,7 +1509,6 @@ static void __exit mt9v111_clean(void)
 	pr_debug("In mt9v111_clean()\n");
 
 	i2c_del_driver(&mt9v111_i2c_driver);
-	gpio_sensor_inactive();
 
 	if (mt9v111_device.coreReg) {
 		kfree(mt9v111_device.coreReg);
diff --git a/drivers/media/video/mxc/capture/mt9v111.h b/drivers/media/video/mxc/capture/mt9v111.h
index cf38cec4757c..ba91a722a076 100644
--- a/drivers/media/video/mxc/capture/mt9v111.h
+++ b/drivers/media/video/mxc/capture/mt9v111.h
@@ -111,11 +111,14 @@
 #define MT9V111I_GAMMA_KNEE_Y90           0x57
 #define MT9V111I_GAMMA_VALUE_Y0           0x58
 #define MT9V111I_SHUTTER_60               0x59
+#define MT9V111I_AUTO_EXPOSURE_17         0x5A
 #define MT9V111I_SEARCH_FLICK_60          0x5c
+#define MT9V111I_RESERVED93	    	      0x5d
 #define MT9V111I_RATIO_IMAGE_GAIN_BASE    0x5e
 #define MT9V111I_RATIO_IMAGE_GAIN_DELTA   0x5f
 #define MT9V111I_SIGN_VALUE_REG5F         0x60
 #define MT9V111I_AE_GAIN                  0x62
+#define MT9V111I_RESERVED100              0x64
 #define MT9V111I_MAX_GAIN_AE              0x67
 #define MT9V111I_LENS_CORRECT_CTRL        0x80
 #define MT9V111I_SHADING_PARAMETER1       0x81
@@ -173,6 +176,7 @@
 #define MT9V111S_ROW_START_IN_ZOOM        0x13
 #define MT9V111S_DIGITAL_ZOOM             0x1e
 #define MT9V111S_READ_MODE                0x20
+#define MT9V111S_RESERVED33               0x21
 #define MT9V111S_DAC_CTRL                 0x27
 #define MT9V111S_GREEN1_GAIN              0x2b
 #define MT9V111S_BLUE_GAIN                0x2c
@@ -278,6 +282,7 @@ typedef struct {
 	u32 rowNoiseControl;
 	u32 darkTargetwNC;
 	u32 testData;		/*!< test mode */
+	u32 reserved33;
 	u32 globalGain;
 	u32 chipVersion;
 	u32 darkTargetwoNC;
@@ -375,11 +380,14 @@ typedef struct {
 	u32 gammaKneeY90;	/*!< Gamma knee points Y9 and Y10 */
 	u32 gammaKneeY0;	/*!< Gamma knee point Y0 */
 	u32 shutter_width_60;
+	u32 auto_exposure_17;
 	u32 search_flicker_60;
+	u32 reserved93;
 	u32 ratioImageGainBase;
 	u32 ratioImageGainDelta;
 	u32 signValueReg5F;
 	u32 aeGain;
+	u32 reserved100;
 	u32 maxGainAE;
 	u32 lensCorrectCtrl;
 	u32 shadingParameter1;	/*!< Shade Parameters */
diff --git a/drivers/media/video/mxc/capture/mx27_prpsw.c b/drivers/media/video/mxc/capture/mx27_prpsw.c
index ce7db16913ec..eca200a580f2 100644
--- a/drivers/media/video/mxc/capture/mx27_prpsw.c
+++ b/drivers/media/video/mxc/capture/mx27_prpsw.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -702,7 +702,7 @@ static int prp_still_start(void *private)
 	cam_data *cam = (cam_data *) private;
 
 	g_still_on = 1;
-	g_prp_cfg.ch2_ptr = (unsigned int)cam->still_buf;
+	g_prp_cfg.ch2_ptr = (unsigned int)cam->still_buf[0];
 	g_prp_cfg.ch2_ptr2 = 0;
 
 	if (prp_v4l2_cfg(&g_prp_cfg, cam))
diff --git a/drivers/media/video/mxc/capture/mxc_v4l2_capture.c b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c
index 30ad533b0ebd..0ab131d605a4 100644
--- a/drivers/media/video/mxc/capture/mxc_v4l2_capture.c
+++ b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c
@@ -18,6 +18,8 @@
  *
  * @ingroup MXC_V4L2_CAPTURE
  */
+
+
 #include <linux/version.h>
 #include <linux/module.h>
 #include <linux/init.h>
@@ -37,9 +39,9 @@
 #include <media/v4l2-int-device.h>
 #include "mxc_v4l2_capture.h"
 #include "ipu_prp_sw.h"
+#include "asm/delay.h"
 
 static int video_nr = -1;
-static cam_data *g_cam;
 
 /*! This data is used for the output to the display. */
 #define MXC_V4L2_CAPTURE_NUM_OUTPUTS	3
@@ -74,21 +76,23 @@ static struct v4l2_output mxc_capture_outputs[MXC_V4L2_CAPTURE_NUM_OUTPUTS] = {
 static struct v4l2_input mxc_capture_inputs[MXC_V4L2_CAPTURE_NUM_INPUTS] = {
 	{
 	 .index = 0,
-	 .name = "CSI IC MEM",
+	 .name = "CSI MEM",
 	 .type = V4L2_INPUT_TYPE_CAMERA,
 	 .audioset = 0,
 	 .tuner = 0,
 	 .std = V4L2_STD_UNKNOWN,
-	 .status = 0,
+	 .status = V4L2_IN_ST_NO_POWER,
 	 },
 	{
 	 .index = 1,
+// AG: CSI IC MEM works but has problems
+//	 .name = "CSI IC MEM",
 	 .name = "CSI MEM",
 	 .type = V4L2_INPUT_TYPE_CAMERA,
 	 .audioset = 0,
 	 .tuner = 0,
 	 .std = V4L2_STD_UNKNOWN,
-	 .status = V4L2_IN_ST_NO_POWER,
+	 .status = 0,
 	 },
 };
 
@@ -118,6 +122,7 @@ typedef struct {
 	u16 active_left;	/*!< Active left. */
 } video_fmt_t;
 
+#if 0
 /*!
  * Description of video formats supported.
  *
@@ -128,37 +133,39 @@ static video_fmt_t video_fmts[] = {
 	{			/*! NTSC */
 	 .v4l2_id = V4L2_STD_NTSC,
 	 .name = "NTSC",
-	 .raw_width = 720 - 1,		/* SENS_FRM_WIDTH */
-	 .raw_height = 288 - 1,		/* SENS_FRM_HEIGHT */
-	 .active_width = 720,		/* ACT_FRM_WIDTH plus 1 */
-	 .active_height = (480 / 2),	/* ACT_FRM_HEIGHT plus 1 */
-	 .active_top = 12,
+	 .raw_width = 720,		/* SENS_FRM_WIDTH */
+	 .raw_height = 525,		/* SENS_FRM_HEIGHT */
+	 .active_width = 720,		/* ACT_FRM_WIDTH */
+	 .active_height = 240,		/* ACT_FRM_HEIGHT */
+	 .active_top = 0,
 	 .active_left = 0,
 	 },
 	{			/*! (B, G, H, I, N) PAL */
 	 .v4l2_id = V4L2_STD_PAL,
 	 .name = "PAL",
-	 .raw_width = 720 - 1,
-	 .raw_height = (576 / 2) + 24 * 2 - 1,
+	 .raw_width = 720,
+	 .raw_height = 625,
 	 .active_width = 720,
-	 .active_height = (576 / 2),
+	 .active_height = 288,
 	 .active_top = 0,
 	 .active_left = 0,
 	 },
 	{			/*! Unlocked standard */
 	 .v4l2_id = V4L2_STD_ALL,
 	 .name = "Autodetect",
-	 .raw_width = 720 - 1,
-	 .raw_height = (576 / 2) + 24 * 2 - 1,
+	 .raw_width = 720,
+	 .raw_height = 625,
 	 .active_width = 720,
-	 .active_height = (576 / 2),
+	 .active_height = 288,
 	 .active_top = 0,
 	 .active_left = 0,
 	 },
 };
 
+
 /*!* Standard index of TV. */
 static video_fmt_idx video_index = TV_NOT_LOCKED;
+#endif
 
 static int mxc_v4l2_master_attach(struct v4l2_int_device *slave);
 static void mxc_v4l2_master_detach(struct v4l2_int_device *slave);
@@ -172,15 +179,27 @@ static struct v4l2_int_master mxc_v4l2_master = {
 	.detach = mxc_v4l2_master_detach,
 };
 
-static struct v4l2_int_device mxc_v4l2_int_device = {
+static struct v4l2_int_device mxc_v4l2_int_device [] = {
+	{
+	.module = THIS_MODULE,
+	.name = "mxc_v4l2_cap_1",
+	.type = v4l2_int_type_master,
+	.u = {
+		.master = &mxc_v4l2_master,
+		},
+	},
+	{
 	.module = THIS_MODULE,
-	.name = "mxc_v4l2_cap",
+	.name = "mxc_v4l2_cap_2",
 	.type = v4l2_int_type_master,
 	.u = {
 		.master = &mxc_v4l2_master,
 		},
+	},
 };
 
+static cam_data *g_cam[ARRAY_SIZE(mxc_v4l2_int_device)];
+
 /***************************************************************************
  * Functions for handling Frame buffers.
  **************************************************************************/
@@ -260,6 +279,7 @@ static int mxc_allocate_frame_buf(cam_data *cam, int count)
 static void mxc_free_frames(cam_data *cam)
 {
 	int i;
+	unsigned long lock_flags;
 
 	pr_debug("In MVC:mxc_free_frames\n");
 
@@ -269,9 +289,11 @@ static void mxc_free_frames(cam_data *cam)
 
 	cam->enc_counter = 0;
 	cam->skip_frame = 0;
+	spin_lock_irqsave(&cam->dqueue_int_lock, lock_flags);
 	INIT_LIST_HEAD(&cam->ready_q);
 	INIT_LIST_HEAD(&cam->working_q);
 	INIT_LIST_HEAD(&cam->done_q);
+	spin_unlock_irqrestore(&cam->dqueue_int_lock, lock_flags);
 }
 
 /*!
@@ -331,8 +353,7 @@ static int mxc_streamon(cam_data *cam)
 {
 	struct mxc_v4l_frame *frame;
 	int err = 0;
-
-	pr_debug("In MVC:mxc_streamon\n");
+	unsigned long lock_flags;
 
 	if (NULL == cam) {
 		pr_err("ERROR! cam parameter is NULL\n");
@@ -363,23 +384,27 @@ static int mxc_streamon(cam_data *cam)
 		}
 	}
 
+	spin_lock_irqsave(&cam->queue_int_lock, lock_flags);
 	cam->ping_pong_csi = 0;
 	if (cam->enc_update_eba) {
-		frame =
-		    list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
-		list_del(cam->ready_q.next);
-		list_add_tail(&frame->queue, &cam->working_q);
-		err = cam->enc_update_eba(frame->buffer.m.offset,
-					  &cam->ping_pong_csi);
 
 		frame =
 		    list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
 		list_del(cam->ready_q.next);
 		list_add_tail(&frame->queue, &cam->working_q);
-		err |= cam->enc_update_eba(frame->buffer.m.offset,
-					   &cam->ping_pong_csi);
+		err = cam->enc_update_eba(cam->csi,frame->buffer.m.offset,
+					  &cam->ping_pong_csi);
+		if (!list_empty(&cam->ready_q)) {
+			frame =
+				list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
+			list_del(cam->ready_q.next);
+			list_add_tail(&frame->queue, &cam->working_q);
+			err |= cam->enc_update_eba(cam->csi,frame->buffer.m.offset,
+						   &cam->ping_pong_csi);
+		}
+		cam->capture_on = true;
 	} else {
-		return -EINVAL;
+		err = -EINVAL;
 	}
 
 	if (cam->overlay_on == true)
@@ -387,11 +412,9 @@ static int mxc_streamon(cam_data *cam)
 
 	if (cam->enc_enable_csi) {
 		err = cam->enc_enable_csi(cam);
-		if (err != 0)
-			return err;
 	}
 
-	cam->capture_on = true;
+	spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags);
 
 	return err;
 }
@@ -543,8 +566,6 @@ static int start_preview(cam_data *cam)
 {
 	int err = 0;
 
-	pr_debug("MVC: start_preview\n");
-
 #if defined(CONFIG_MXC_IPU_PRP_VF_SDC) || defined(CONFIG_MXC_IPU_PRP_VF_SDC_MODULE)
 	pr_debug("   This is an SDC display\n");
 	if (cam->output == 0 || cam->output == 2) {
@@ -602,8 +623,6 @@ static int stop_preview(cam_data *cam)
 {
 	int err = 0;
 
-	pr_debug("MVC: stop preview\n");
-
 #if defined(CONFIG_MXC_IPU_PRP_VF_ADC) || defined(CONFIG_MXC_IPU_PRP_VF_ADC_MODULE)
 	if (cam->output == 1) {
 		err = prp_vf_adc_deselect(cam);
@@ -674,6 +693,29 @@ static int mxc_v4l2_g_fmt(cam_data *cam, struct v4l2_format *f)
 		 __func__,
 		 cam->crop_current.width, cam->crop_current.height);
 
+	retval = vidioc_int_g_fmt_cap(cam->sensor,f);
+	return retval;
+}
+
+/*!
+ * V4L2 - mxc_v4l2_enum_fmt function
+ *
+ * @param cam         structure cam_data *
+ *
+ * @param f           structure v4l2_fmtdesc *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2_enum_fmt(cam_data *cam, struct v4l2_fmtdesc *f)
+{
+	int retval = 0;
+
+	pr_debug("In MVC: mxc_v4l2_enum_fmt\n");
+
+	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
+	retval = vidioc_int_enum_fmt_cap(cam->sensor,f);
+	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
+
 	return retval;
 }
 
@@ -709,10 +751,14 @@ static int mxc_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f)
 		 * for CSI MEM input mode.
 		 */
 		if (strcmp(mxc_capture_inputs[cam->current_input].name,
-			   "CSI MEM") == 0) {
+			   "CSI MEM") == 0 || strcmp(mxc_capture_inputs[cam->current_input].name,
+					   "CSI IC MEM") == 0) {
 			f->fmt.pix.width = cam->crop_current.width;
 			f->fmt.pix.height = cam->crop_current.height;
 		}
+		else {
+			printk("Error no match %s\n",mxc_capture_inputs[cam->current_input].name);
+		}
 
 		if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
 			height = &f->fmt.pix.width;
@@ -811,6 +857,13 @@ static int mxc_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f)
 				break;
 			}
 		}
+
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi,
+				       true, true);
+		vidioc_int_s_fmt_cap(cam->sensor, f);
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi,
+				       false, false);
+
 		break;
 	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
 		pr_debug("   type=V4L2_BUF_TYPE_VIDEO_OVERLAY\n");
@@ -1057,63 +1110,10 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
 	return ret;
 }
 
-/*!
- * V4L2 - mxc_v4l2_s_param function
- * Allows setting of capturemode and frame rate.
- *
- * @param cam         structure cam_data *
- * @param parm        structure v4l2_streamparm *
- *
- * @return  status    0 success, EINVAL failed
- */
-static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm)
-{
-	struct v4l2_ifparm ifparm;
+static int 	mxc_v4l2_init_csi( cam_data *cam ) {
 	struct v4l2_format cam_fmt;
-	struct v4l2_streamparm currentparm;
 	ipu_csi_signal_cfg_t csi_param;
-	int err = 0;
-
-	pr_debug("In mxc_v4l2_s_param\n");
-
-	if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
-		pr_err(KERN_ERR "mxc_v4l2_s_param invalid type\n");
-		return -EINVAL;
-	}
-
-	/* Stop the viewfinder */
-	if (cam->overlay_on == true) {
-		stop_preview(cam);
-	}
-
-	currentparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-
-	/* First check that this device can support the changes requested. */
-	err = vidioc_int_g_parm(cam->sensor, &currentparm);
-	if (err) {
-		pr_err("%s: vidioc_int_g_parm returned an error %d\n",
-			__func__, err);
-		goto exit;
-	}
-
-	pr_debug("   Current capabilities are %x\n",
-			currentparm.parm.capture.capability);
-	pr_debug("   Current capturemode is %d  change to %d\n",
-			currentparm.parm.capture.capturemode,
-			parm->parm.capture.capturemode);
-	pr_debug("   Current framerate is %d  change to %d\n",
-			currentparm.parm.capture.timeperframe.denominator,
-			parm->parm.capture.timeperframe.denominator);
-
-	/* This will change any camera settings needed. */
-	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
-	err = vidioc_int_s_parm(cam->sensor, parm);
-	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
-	if (err) {
-		pr_err("%s: vidioc_int_s_parm returned an error %d\n",
-			__func__, err);
-		goto exit;
-	}
+	struct v4l2_ifparm ifparm;
 
 	/* If resolution changed, need to re-program the CSI */
 	/* Get new values. */
@@ -1131,13 +1131,13 @@ static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm)
 	csi_param.force_eof = 0;
 	csi_param.data_en_pol = 0;
 	csi_param.data_fmt = 0;
-	csi_param.csi = 0;
+	csi_param.csi = cam->csi;
 	csi_param.mclk = 0;
 
 	/* This may not work on other platforms. Check when adding a new one.*/
 	pr_debug("   clock_curr=mclk=%d\n", ifparm.u.bt656.clock_curr);
 	if (ifparm.u.bt656.clock_curr == 0) {
-		csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
+		csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
 	} else {
 		csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
 	}
@@ -1189,7 +1189,63 @@ static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm)
 	ipu_csi_init_interface(cam->crop_bounds.width,
 			       cam->crop_bounds.height,
 			       cam_fmt.fmt.pix.pixelformat, csi_param);
+	return 0;
+}
 
+/*!
+ * V4L2 - mxc_v4l2_s_param function
+ * Allows setting of capturemode and frame rate.
+ *
+ * @param cam         structure cam_data *
+ * @param parm        structure v4l2_streamparm *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm)
+{
+	struct v4l2_streamparm currentparm;
+	int err = 0;
+
+	if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		pr_err(KERN_ERR "mxc_v4l2_s_param invalid type\n");
+		return -EINVAL;
+	}
+
+	/* Stop the viewfinder */
+	if (cam->overlay_on == true) {
+		stop_preview(cam);
+	}
+
+	currentparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+
+	/* First check that this device can support the changes requested. */
+	err = vidioc_int_g_parm(cam->sensor, &currentparm);
+	if (err) {
+		pr_err("%s: vidioc_int_g_parm returned an error %d\n",
+			__func__, err);
+		goto exit;
+	}
+
+	pr_debug("   Current capabilities are %x\n",
+			currentparm.parm.capture.capability);
+	pr_debug("   Current capturemode is %d  change to %d\n",
+			currentparm.parm.capture.capturemode,
+			parm->parm.capture.capturemode);
+	pr_debug("   Current framerate is %d  change to %d\n",
+			currentparm.parm.capture.timeperframe.denominator,
+			parm->parm.capture.timeperframe.denominator);
+
+	/* This will change any camera settings needed. */
+	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
+	err = vidioc_int_s_parm(cam->sensor, parm);
+	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
+	if (err) {
+		pr_err("%s: vidioc_int_s_parm returned an error %d\n",
+			__func__, err);
+		goto exit;
+	}
+
+	err = mxc_v4l2_init_csi(cam);
 
 exit:
 	if (cam->overlay_on == true)
@@ -1198,6 +1254,7 @@ exit:
 	return err;
 }
 
+#if 0
 /*!
  * V4L2 - mxc_v4l2_s_std function
  *
@@ -1287,6 +1344,7 @@ static int mxc_v4l2_g_std(cam_data *cam, v4l2_std_id *e)
 
 	return 0;
 }
+#endif
 
 /*!
  * Dequeue one V4L capture buffer
@@ -1372,6 +1430,11 @@ static int mxc_v4l_open(struct file *file)
 		return -EBADF;
 	}
 
+	if(!cam->sensor) {
+		pr_err("ERROR: v4l2 capture: Unattached sensor!\n");
+		return -EBADF;
+	}
+
 	down(&cam->busy_lock);
 	err = 0;
 	if (signal_pending(current))
@@ -1411,12 +1474,9 @@ static int mxc_v4l_open(struct file *file)
 		csi_param.force_eof = 0;
 		csi_param.data_en_pol = 0;
 		csi_param.mclk = ifparm.u.bt656.clock_curr;
-
+		csi_param.ext_vsync = ifparm.u.bt656.bt_sync_correct;
 		csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv;
 
-		/* Once we handle multiple inputs this will need to change. */
-		csi_param.csi = 0;
-
 		if (ifparm.u.bt656.mode
 				== V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT)
 			csi_param.data_width = IPU_CSI_DATA_WIDTH_8;
@@ -1464,11 +1524,13 @@ static int mxc_v4l_open(struct file *file)
 			__func__,
 			cam->crop_current.width, cam->crop_current.height);
 
+		udelay(100);
+
 		csi_param.data_fmt = cam_fmt.fmt.pix.pixelformat;
 		pr_debug("On Open: Input to ipu size is %d x %d\n",
 				cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height);
 		ipu_csi_set_window_size(cam->crop_current.width,
-					cam->crop_current.width,
+					cam->crop_current.height,
 					cam->csi);
 		ipu_csi_set_window_pos(cam->crop_current.left,
 					cam->crop_current.top,
@@ -1478,12 +1540,16 @@ static int mxc_v4l_open(struct file *file)
 					cam_fmt.fmt.pix.pixelformat,
 					csi_param);
 
+		udelay(100);
+
 		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi,
 				       true, true);
 		vidioc_int_init(cam->sensor);
 
 		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi,
 				       false, false);
+
+		udelay(100);
 }
 
 	file->private_data = dev;
@@ -1519,7 +1585,7 @@ static int mxc_v4l_close(struct file *file)
 		err = stop_preview(cam);
 		cam->overlay_on = false;
 	}
-	if (cam->capture_pid == current->pid) {
+	if (cam->capture_pid == current->tgid) {
 		err |= mxc_streamoff(cam);
 		wake_up_interruptible(&cam->enc_queue);
 	}
@@ -1570,7 +1636,7 @@ static ssize_t mxc_v4l_read(struct file *file, char *buf, size_t count,
 			    loff_t *ppos)
 {
 	int err = 0;
-	u8 *v_address;
+	u8 *v_address[2];
 	struct video_device *dev = video_devdata(file);
 	cam_data *cam = video_get_drvdata(dev);
 
@@ -1581,11 +1647,17 @@ static ssize_t mxc_v4l_read(struct file *file, char *buf, size_t count,
 	if (cam->overlay_on == true)
 		stop_preview(cam);
 
-	v_address = dma_alloc_coherent(0,
+	v_address[0] = dma_alloc_coherent(0,
 				       PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
-				       &cam->still_buf, GFP_DMA | GFP_KERNEL);
+				       &cam->still_buf[0],
+				       GFP_DMA | GFP_KERNEL);
+
+	v_address[1] = dma_alloc_coherent(0,
+				       PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
+				       &cam->still_buf[1],
+				       GFP_DMA | GFP_KERNEL);
 
-	if (!v_address) {
+	if (!v_address[0] || !v_address[1]) {
 		err = -ENOBUFS;
 		goto exit0;
 	}
@@ -1593,14 +1665,14 @@ static ssize_t mxc_v4l_read(struct file *file, char *buf, size_t count,
 	err = prp_still_select(cam);
 	if (err != 0) {
 		err = -EIO;
-		goto exit1;
+		goto exit0;
 	}
 
 	cam->still_counter = 0;
 	err = cam->csi_start(cam);
 	if (err != 0) {
 		err = -EIO;
-		goto exit2;
+		goto exit1;
 	}
 
 	if (!wait_event_interruptible_timeout(cam->still_queue,
@@ -1609,19 +1681,23 @@ static ssize_t mxc_v4l_read(struct file *file, char *buf, size_t count,
 		pr_err("ERROR: v4l2 capture: mxc_v4l_read timeout counter %x\n",
 		       cam->still_counter);
 		err = -ETIME;
-		goto exit2;
+		goto exit1;
 	}
-	err = copy_to_user(buf, v_address, cam->v2f.fmt.pix.sizeimage);
-
-      exit2:
-	prp_still_deselect(cam);
+	err = copy_to_user(buf, v_address[1], cam->v2f.fmt.pix.sizeimage);
 
       exit1:
-	dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address,
-			  cam->still_buf);
-	cam->still_buf = 0;
+	prp_still_deselect(cam);
 
       exit0:
+	if (v_address[0] != 0)
+		dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address[0],
+				  cam->still_buf[0]);
+	if (v_address[1] != 0)
+		dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address[1],
+				  cam->still_buf[1]);
+
+	cam->still_buf[0] = cam->still_buf[1] = 0;
+
 	if (cam->overlay_on == true) {
 		start_preview(cam);
 	}
@@ -1661,6 +1737,21 @@ static long mxc_v4l_do_ioctl(struct file *file,
 		return -EBUSY;
 
 	switch (ioctlnr) {
+
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+	case VIDIOC_DBG_S_REGISTER: {
+		struct v4l2_dbg_register * dreg = arg;
+		vidioc_int_s_register(cam->sensor,dreg);
+		break;
+	}
+
+	case VIDIOC_DBG_G_REGISTER: {
+		struct v4l2_dbg_register * dreg = arg;
+		vidioc_int_g_register(cam->sensor,dreg);
+		break;
+	}
+#endif
+
 	/*!
 	 * V4l2 VIDIOC_QUERYCAP ioctl
 	 */
@@ -1695,6 +1786,14 @@ static long mxc_v4l_do_ioctl(struct file *file,
 		struct v4l2_format *sf = arg;
 		pr_debug("   case VIDIOC_S_FMT\n");
 		retval = mxc_v4l2_s_fmt(cam, sf);
+		mxc_v4l2_init_csi(cam);
+		break;
+	}
+
+	case VIDIOC_ENUM_FMT: {
+		struct v4l2_fmtdesc *fd = arg;
+		pr_debug("   case VIDIOC_ENUM_FMT\n");
+		retval = mxc_v4l2_enum_fmt(cam, fd);
 		break;
 	}
 
@@ -1775,9 +1874,8 @@ static long mxc_v4l_do_ioctl(struct file *file,
 				if (cam->skip_frame > 0) {
 					list_add_tail(&cam->frame[index].queue,
 						      &cam->working_q);
-
 					retval =
-					   cam->enc_update_eba(cam->
+					   cam->enc_update_eba(cam->csi,cam->
 							       frame[index].
 							       buffer.m.offset,
 							       &cam->
@@ -1999,28 +2097,6 @@ static long mxc_v4l_do_ioctl(struct file *file,
 		break;
 	}
 
-	/* linux v4l2 bug, kernel c0485619 user c0405619 */
-	case VIDIOC_ENUMSTD: {
-		struct v4l2_standard *e = arg;
-		pr_debug("   case VIDIOC_ENUMSTD\n");
-		*e = cam->standard;
-		break;
-	}
-
-	case VIDIOC_G_STD: {
-		v4l2_std_id *e = arg;
-		pr_debug("   case VIDIOC_G_STD\n");
-		retval = mxc_v4l2_g_std(cam, e);
-		break;
-	}
-
-	case VIDIOC_S_STD: {
-		v4l2_std_id *e = arg;
-		pr_debug("   case VIDIOC_S_STD\n");
-		retval = mxc_v4l2_s_std(cam, *e);
-
-		break;
-	}
 
 	case VIDIOC_ENUMOUTPUT: {
 		struct v4l2_output *output = arg;
@@ -2109,8 +2185,13 @@ static long mxc_v4l_do_ioctl(struct file *file,
 		break;
 	}
 
-	case VIDIOC_ENUM_FMT:
-	case VIDIOC_TRY_FMT:
+	case VIDIOC_TRY_FMT: {
+		struct v4l2_format * f = arg;
+		pr_debug("   case VIDIOC_TRY_FMT\n");
+		retval = vidioc_int_try_fmt_cap(cam->sensor,f);
+		break;
+	}
+
 	case VIDIOC_QUERYCTRL:
 	case VIDIOC_G_TUNER:
 	case VIDIOC_S_TUNER:
@@ -2236,12 +2317,21 @@ static void camera_platform_release(struct device *device)
 }
 
 /*! Device Definition for Mt9v111 devices */
-static struct platform_device mxc_v4l2_devices = {
-	.name = "mxc_v4l2",
-	.dev = {
-		.release = camera_platform_release,
-		},
-	.id = 0,
+static struct platform_device mxc_v4l2_devices[] = {
+	{
+		.name = "mxc_v4l2_1",
+		.dev = {
+			.release = camera_platform_release,
+			},
+		.id = 0,
+	},
+	{
+		.name = "mxc_v4l2_2",
+		.dev = {
+			.release = camera_platform_release,
+			},
+		.id = 1,
+	}
 };
 
 /*!
@@ -2302,7 +2392,7 @@ static void camera_callback(u32 mask, void *dev)
 							 struct mxc_v4l_frame,
 							 queue);
 
-				if (cam->enc_update_eba(
+				if (cam->enc_update_eba(cam->csi,
 						ready_frame->buffer.m.offset,
 						&cam->ping_pong_csi) == 0) {
 					list_del(cam->ready_q.next);
@@ -2354,7 +2444,7 @@ static void camera_callback(u32 mask, void *dev)
 			ready_frame = list_entry(cam->ready_q.next,
 						 struct mxc_v4l_frame,
 						 queue);
-			if (cam->enc_update_eba(ready_frame->buffer.m.offset,
+			if (cam->enc_update_eba(cam->csi,ready_frame->buffer.m.offset,
 						&cam->ping_pong_csi) == 0) {
 				list_del(cam->ready_q.next);
 				list_add_tail(&ready_frame->queue,
@@ -2362,7 +2452,7 @@ static void camera_callback(u32 mask, void *dev)
 			} else
 				return;
 		} else {
-			if (cam->enc_update_eba(
+			if (cam->enc_update_eba(cam->csi,
 				cam->dummy_frame.buffer.m.offset,
 				&cam->ping_pong_csi) == -EACCES)
 				return;
@@ -2379,13 +2469,15 @@ static void camera_callback(u32 mask, void *dev)
  *
  * @return status  0 Success
  */
-static void init_camera_struct(cam_data *cam)
+static void init_camera_struct(cam_data *cam,unsigned int csi)
 {
-	pr_debug("In MVC: init_camera_struct\n");
+	pr_debug("In MVC: init_camera_struct for csi %d\n",csi);
 
 	/* Default everything to 0 */
 	memset(cam, 0, sizeof(cam_data));
 
+	cam->csi = csi;
+
 	init_MUTEX(&cam->param_lock);
 	init_MUTEX(&cam->busy_lock);
 
@@ -2396,7 +2488,7 @@ static void init_camera_struct(cam_data *cam)
 	*(cam->video_dev) = mxc_v4l_template;
 
 	video_set_drvdata(cam->video_dev, cam);
-	dev_set_drvdata(&mxc_v4l2_devices.dev, (void *)cam);
+	dev_set_drvdata(&mxc_v4l2_devices[csi].dev, (void *)cam);
 	cam->video_dev->minor = -1;
 
 	init_waitqueue_head(&cam->enc_queue);
@@ -2428,6 +2520,8 @@ static void init_camera_struct(cam_data *cam)
 	cam->skip_frame = 0;
 	cam->v4l2_fb.flags = V4L2_FBUF_FLAG_OVERLAY;
 
+	cam->current_input = cam->csi;
+
 	cam->v2f.fmt.pix.sizeimage = 352 * 288 * 3 / 2;
 	cam->v2f.fmt.pix.bytesperline = 288 * 3 / 2;
 	cam->v2f.fmt.pix.width = 288;
@@ -2438,9 +2532,6 @@ static void init_camera_struct(cam_data *cam)
 	cam->win.w.left = 0;
 	cam->win.w.top = 0;
 
-	cam->csi = 0;  /* Need to determine how to set this correctly with
-			* multiple video input devices. */
-
 	cam->enc_callback = camera_callback;
 	init_waitqueue_head(&cam->power_queue);
 	spin_lock_init(&cam->queue_int_lock);
@@ -2460,11 +2551,12 @@ static u8 camera_power(cam_data *cam, bool cameraOn)
 {
 	pr_debug("In MVC:camera_power on=%d\n", cameraOn);
 
+	if( !cam->open_count )
+		return 0;
+
 	if (cameraOn == true) {
-		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
 		vidioc_int_s_power(cam->sensor, 1);
 	} else {
-		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
 		vidioc_int_s_power(cam->sensor, 0);
 	}
 	return 0;
@@ -2491,15 +2583,15 @@ static int mxc_v4l2_suspend(struct platform_device *pdev, pm_message_t state)
 		return -1;
 	}
 
+	if (!cam->open_count) {
+		return 0;
+	}
+
 	cam->low_power = true;
 
 	if (cam->overlay_on == true)
 		stop_preview(cam);
-	if ((cam->capture_on == true) && cam->enc_disable) {
-		cam->enc_disable(cam);
-	}
 	camera_power(cam, false);
-
 	return 0;
 }
 
@@ -2522,14 +2614,19 @@ static int mxc_v4l2_resume(struct platform_device *pdev)
 		return -1;
 	}
 
+	if( !cam->open_count )
+		return 0;
+
 	cam->low_power = false;
 	wake_up_interruptible(&cam->power_queue);
+
 	camera_power(cam, true);
 
 	if (cam->overlay_on == true)
 		start_preview(cam);
+
 	if (cam->capture_on == true)
-		mxc_streamon(cam);
+	    mxc_streamon(cam);
 
 	return 0;
 }
@@ -2537,15 +2634,27 @@ static int mxc_v4l2_resume(struct platform_device *pdev)
 /*!
  * This structure contains pointers to the power management callback functions.
  */
-static struct platform_driver mxc_v4l2_driver = {
-	.driver = {
-		   .name = "mxc_v4l2",
-		   },
-	.probe = NULL,
-	.remove = NULL,
-	.suspend = mxc_v4l2_suspend,
-	.resume = mxc_v4l2_resume,
-	.shutdown = NULL,
+static struct platform_driver mxc_v4l2_driver[] = {
+	{
+		.driver = {
+			   .name = "mxc_v4l2_1",
+			   },
+		.probe = NULL,
+		.remove = NULL,
+		.suspend = mxc_v4l2_suspend,
+		.resume = mxc_v4l2_resume,
+		.shutdown = NULL,
+	},
+	{
+		.driver = {
+			   .name = "mxc_v4l2_2",
+			   },
+		.probe = NULL,
+		.remove = NULL,
+		.suspend = mxc_v4l2_suspend,
+		.resume = mxc_v4l2_resume,
+		.shutdown = NULL,
+	},
 };
 
 /*!
@@ -2567,6 +2676,7 @@ static int mxc_v4l2_master_attach(struct v4l2_int_device *slave)
 	}
 
 	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
+	vidioc_int_s_power(cam->sensor, 1);
 	vidioc_int_dev_init(slave);
 	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
 	cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
@@ -2623,53 +2733,55 @@ static void mxc_v4l2_master_detach(struct v4l2_int_device *slave)
 static __init int camera_init(void)
 {
 	u8 err = 0;
+	int i;
 
 	pr_debug("In MVC:camera_init\n");
 
-	/* Register the device driver structure. */
-	err = platform_driver_register(&mxc_v4l2_driver);
-	if (err != 0) {
-		pr_err("ERROR: v4l2 capture:camera_init: "
-			"platform_driver_register failed.\n");
-		return err;
-	}
+	for (i = 0; i < ARRAY_SIZE(mxc_v4l2_int_device); i++) {
+		/* Register the device driver structure. */
+		err = platform_driver_register(&mxc_v4l2_driver[i]);
+		if (err != 0) {
+			pr_err("ERROR: v4l2 capture:camera_init: "
+				"platform_driver_register failed.\n");
+			return err;
+		}
 
-	/* Create g_cam and initialize it. */
-	if ((g_cam = kmalloc(sizeof(cam_data), GFP_KERNEL)) == NULL) {
-		pr_err("ERROR: v4l2 capture: failed to register camera\n");
-		platform_driver_unregister(&mxc_v4l2_driver);
-		return -1;
-	}
-	init_camera_struct(g_cam);
+		/* Create g_cam and initialize it. */
+		if ((g_cam [i] = kmalloc(sizeof(cam_data), GFP_KERNEL)) == NULL) {
+			pr_err("ERROR: v4l2 capture: failed to register camera\n");
+			platform_driver_unregister(&mxc_v4l2_driver[i]);
+			return -1;
+		}
+		init_camera_struct(g_cam [i], i);
 
-	/* Set up the v4l2 device and register it*/
-	mxc_v4l2_int_device.priv = g_cam;
-	/* This function contains a bug that won't let this be rmmod'd. */
-	v4l2_int_device_register(&mxc_v4l2_int_device);
+		/* Set up the v4l2 device and register it*/
+		mxc_v4l2_int_device[i].priv = g_cam [i];
+		/* This function contains a bug that won't let this be rmmod'd. */
+		v4l2_int_device_register(&mxc_v4l2_int_device[i]);
 
-	/* Register the I2C device */
-	err = platform_device_register(&mxc_v4l2_devices);
-	if (err != 0) {
-		pr_err("ERROR: v4l2 capture: camera_init: "
-		       "platform_device_register failed.\n");
-		platform_driver_unregister(&mxc_v4l2_driver);
-		kfree(g_cam);
-		g_cam = NULL;
-		return err;
-	}
+		/* Register the I2C device */
+		err = platform_device_register(&mxc_v4l2_devices[i]);
+		if (err != 0) {
+			pr_err("ERROR: v4l2 capture: camera_init: "
+				   "platform_device_register failed.\n");
+					platform_driver_unregister(&mxc_v4l2_driver[i]);
+					kfree(g_cam [i]);
+					g_cam [i] = NULL;
+			return err;
+		}
 
-	/* register v4l video device */
-	if (video_register_device(g_cam->video_dev, VFL_TYPE_GRABBER, video_nr)
-	    == -1) {
-		platform_device_unregister(&mxc_v4l2_devices);
-		platform_driver_unregister(&mxc_v4l2_driver);
-		kfree(g_cam);
-		g_cam = NULL;
-		pr_err("ERROR: v4l2 capture: video_register_device failed\n");
-		return -1;
+		/* register v4l video device */
+		if (video_register_device(g_cam[i]->video_dev, VFL_TYPE_GRABBER, video_nr)== -1) {
+			platform_device_unregister(&mxc_v4l2_devices[i]);
+			platform_driver_unregister(&mxc_v4l2_driver[i]);
+			kfree(g_cam[i]);
+			g_cam [i] = NULL;
+			pr_err("ERROR: v4l2 capture: video_register_device failed\n");
+			return -1;
+		}
+		pr_debug("   Video device registered: %s #%d\n",
+			g_cam[i]->video_dev->name, g_cam[i]->video_dev->minor);
 	}
-	pr_debug("   Video device registered: %s #%d\n",
-		 g_cam->video_dev->name, g_cam->video_dev->minor);
 
 	return err;
 }
@@ -2683,19 +2795,34 @@ static void __exit camera_exit(void)
 
 	pr_info("V4L2 unregistering video\n");
 
-	if (g_cam->open_count) {
+	if (g_cam[0]->open_count) {
+		pr_err("ERROR: v4l2 capture:camera open "
+			"-- setting ops to NULL\n");
+	} else {
+		pr_info("V4L2 freeing image input device\n");
+		v4l2_int_device_unregister(&mxc_v4l2_int_device[0]);
+		video_unregister_device(g_cam[0]->video_dev);
+		platform_driver_unregister(&mxc_v4l2_driver[0]);
+		platform_device_unregister(&mxc_v4l2_devices[0]);
+
+		mxc_free_frame_buf(g_cam[0]);
+		kfree(g_cam[0]);
+		g_cam[0] = NULL;
+	}
+
+	if (g_cam[1]->open_count) {
 		pr_err("ERROR: v4l2 capture:camera open "
 			"-- setting ops to NULL\n");
 	} else {
 		pr_info("V4L2 freeing image input device\n");
-		v4l2_int_device_unregister(&mxc_v4l2_int_device);
-		video_unregister_device(g_cam->video_dev);
-		platform_driver_unregister(&mxc_v4l2_driver);
-		platform_device_unregister(&mxc_v4l2_devices);
-
-		mxc_free_frame_buf(g_cam);
-		kfree(g_cam);
-		g_cam = NULL;
+		v4l2_int_device_unregister(&mxc_v4l2_int_device[1]);
+		video_unregister_device(g_cam[1]->video_dev);
+		platform_driver_unregister(&mxc_v4l2_driver[1]);
+		platform_device_unregister(&mxc_v4l2_devices[1]);
+
+		mxc_free_frame_buf(g_cam[1]);
+		kfree(g_cam[1]);
+		g_cam[1] = NULL;
 	}
 }
 
diff --git a/drivers/media/video/mxc/capture/mxc_v4l2_capture.h b/drivers/media/video/mxc/capture/mxc_v4l2_capture.h
index 45a211a80a38..abaaaea48447 100644
--- a/drivers/media/video/mxc/capture/mxc_v4l2_capture.h
+++ b/drivers/media/video/mxc/capture/mxc_v4l2_capture.h
@@ -36,6 +36,7 @@
 #include <media/v4l2-dev.h>
 
 #define FRAME_NUM 3
+//#define FRAME_NUM 4
 
 /*!
  * v4l2 frame structure.
@@ -123,7 +124,7 @@ typedef struct _cam_data {
 	/* still image capture */
 	wait_queue_head_t still_queue;
 	int still_counter;
-	dma_addr_t still_buf;
+	dma_addr_t still_buf[2];
 	void *still_buf_vaddr;
 
 	/* overlay */
@@ -166,7 +167,7 @@ typedef struct _cam_data {
 	struct v4l2_rect crop_defrect;
 	struct v4l2_rect crop_current;
 
-	int (*enc_update_eba) (dma_addr_t eba, int *bufferNum);
+	int (*enc_update_eba) (int csi,dma_addr_t eba, int *bufferNum);
 	int (*enc_enable) (void *private);
 	int (*enc_disable) (void *private);
 	int (*enc_enable_csi) (void *private);
@@ -194,6 +195,7 @@ typedef struct _cam_data {
 	/* camera sensor interface */
 	struct camera_sensor *cam_sensor; 	/* old version */
 	struct v4l2_int_device *sensor;
+	struct timeval tv_wakeup; // TODO - for testing. Remove later
 } cam_data;
 
 #if defined(CONFIG_MXC_IPU_V1) || defined(CONFIG_VIDEO_MXC_EMMA_CAMERA) \
diff --git a/drivers/media/video/mxc/capture/ov3640.c b/drivers/media/video/mxc/capture/ov3640.c
index 29e61234e7f8..0169e0553ada 100644
--- a/drivers/media/video/mxc/capture/ov3640.c
+++ b/drivers/media/video/mxc/capture/ov3640.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -40,8 +40,8 @@ enum ov3640_mode {
 	ov3640_mode_MIN = 0,
 	ov3640_mode_VGA_640_480 = 0,
 	ov3640_mode_QVGA_320_240 = 1,
-	ov3640_mode_QXGA_2048_1536 = 2,
-	ov3640_mode_XGA_1024_768 = 3,
+	ov3640_mode_XGA_1024_768 = 2,
+	ov3640_mode_QXGA_2048_1536 = 3,
 	ov3640_mode_NTSC_720_480 = 4,
 	ov3640_mode_PAL_720_576 = 5,
 	ov3640_mode_MAX = 5
@@ -93,6 +93,44 @@ struct sensor {
 } ov3640_data;
 
 static struct reg_value ov3640_setting_15fps_QXGA_2048_1536[] = {
+#if 0
+	/* The true 15fps QXGA setting. */
+	{0x3012, 0x80, 0, 0}, {0x304d, 0x41, 0, 0}, {0x3087, 0x16, 0, 0},
+	{0x30aa, 0x45, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0},
+	{0x30b2, 0x13, 0, 0}, {0x30d7, 0x10, 0, 0}, {0x309e, 0x00, 0, 0},
+	{0x3602, 0x26, 0, 0}, {0x3603, 0x4D, 0, 0}, {0x364c, 0x04, 0, 0},
+	{0x360c, 0x12, 0, 0}, {0x361e, 0x00, 0, 0}, {0x361f, 0x11, 0, 0},
+	{0x3633, 0x03, 0, 0}, {0x3629, 0x3c, 0, 0}, {0x300e, 0x33, 0, 0},
+	{0x300f, 0x21, 0, 0}, {0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0},
+	{0x304c, 0x81, 0, 0}, {0x3029, 0x47, 0, 0}, {0x3070, 0x00, 0, 0},
+	{0x3071, 0xEC, 0, 0}, {0x301C, 0x06, 0, 0}, {0x3072, 0x00, 0, 0},
+	{0x3073, 0xC5, 0, 0}, {0x301D, 0x07, 0, 0}, {0x3018, 0x38, 0, 0},
+	{0x3019, 0x30, 0, 0}, {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0},
+	{0x3087, 0x02, 0, 0}, {0x3082, 0x20, 0, 0}, {0x303c, 0x08, 0, 0},
+	{0x303d, 0x18, 0, 0}, {0x303e, 0x06, 0, 0}, {0x303F, 0x0c, 0, 0},
+	{0x3030, 0x62, 0, 0}, {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0},
+	{0x3033, 0x6e, 0, 0}, {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0},
+	{0x3036, 0xa6, 0, 0}, {0x3037, 0x6a, 0, 0}, {0x3015, 0x12, 0, 0},
+	{0x3014, 0x04, 0, 0}, {0x3013, 0xf7, 0, 0}, {0x3104, 0x02, 0, 0},
+	{0x3105, 0xfd, 0, 0}, {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0},
+	{0x3308, 0xa5, 0, 0}, {0x3316, 0xff, 0, 0}, {0x3317, 0x00, 0, 0},
+	{0x3087, 0x02, 0, 0}, {0x3082, 0x20, 0, 0}, {0x3300, 0x13, 0, 0},
+	{0x3301, 0xd6, 0, 0}, {0x3302, 0xef, 0, 0}, {0x30b8, 0x20, 0, 0},
+	{0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0},
+	{0x3100, 0x02, 0, 0}, {0x3304, 0x00, 0, 0}, {0x3400, 0x00, 0, 0},
+	{0x3404, 0x02, 0, 0}, {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0},
+	{0x3022, 0x00, 0, 0}, {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0},
+	{0x3025, 0x18, 0, 0}, {0x3026, 0x06, 0, 0}, {0x3027, 0x0c, 0, 0},
+	{0x335f, 0x68, 0, 0}, {0x3360, 0x18, 0, 0}, {0x3361, 0x0c, 0, 0},
+	{0x3362, 0x68, 0, 0}, {0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0},
+	{0x3403, 0x42, 0, 0}, {0x3088, 0x08, 0, 0}, {0x3089, 0x00, 0, 0},
+	{0x308a, 0x06, 0, 0}, {0x308b, 0x00, 0, 0}, {0x3507, 0x06, 0, 0},
+	{0x350a, 0x4f, 0, 0}, {0x3600, 0xc4, 0, 0},
+#endif
+	/*
+	 * Only support 7.5fps for QXGA to workaround screen tearing issue
+	 * for 15fps when capturing still image.
+	 */
 	{0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0},
 	{0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0},
 	{0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0},
@@ -118,25 +156,9 @@ static struct reg_value ov3640_setting_15fps_QXGA_2048_1536[] = {
 	{0x30bb, 0x08, 0, 0}, {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0},
 	{0x3100, 0x02, 0, 0}, {0x3301, 0xde, 0, 0}, {0x3304, 0x00, 0, 0},
 	{0x3400, 0x00, 0, 0}, {0x3404, 0x02, 0, 0}, {0x3600, 0xc4, 0, 0},
-	{0x3302, 0xef, 0, 0}, {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0},
-	{0x3022, 0x00, 0, 0}, {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0},
-	{0x3025, 0x00, 0, 0}, {0x3026, 0x06, 0, 0}, {0x3027, 0x00, 0, 0},
-	{0x335f, 0x68, 0, 0}, {0x3360, 0x00, 0, 0}, {0x3361, 0x00, 0, 0},
-	{0x3362, 0x68, 0, 0}, {0x3363, 0x00, 0, 0}, {0x3364, 0x00, 0, 0},
-	{0x3403, 0x00, 0, 0}, {0x3088, 0x08, 0, 0}, {0x3089, 0x00, 0, 0},
-	{0x308a, 0x06, 0, 0}, {0x308b, 0x00, 0, 0}, {0x307c, 0x10, 0, 0},
-	{0x3090, 0xc0, 0, 0}, {0x304c, 0x84, 0, 0}, {0x308d, 0x04, 0, 0},
-	{0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3012, 0x00, 0, 0},
-	{0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0}, {0x3022, 0x00, 0, 0},
-	{0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0}, {0x3025, 0x18, 0, 0},
-	{0x3026, 0x06, 0, 0}, {0x3027, 0x0c, 0, 0}, {0x302a, 0x06, 0, 0},
-	{0x302b, 0x20, 0, 0}, {0x3075, 0x44, 0, 0}, {0x300d, 0x00, 0, 0},
-	{0x30d7, 0x00, 0, 0}, {0x3069, 0x40, 0, 0}, {0x303e, 0x01, 0, 0},
-	{0x303f, 0x80, 0, 0}, {0x3302, 0x20, 0, 0}, {0x335f, 0x68, 0, 0},
-	{0x3360, 0x18, 0, 0}, {0x3361, 0x0c, 0, 0}, {0x3362, 0x68, 0, 0},
-	{0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0}, {0x3403, 0x42, 0, 0},
 	{0x3088, 0x08, 0, 0}, {0x3089, 0x00, 0, 0}, {0x308a, 0x06, 0, 0},
-	{0x308b, 0x00, 0, 0},
+	{0x308b, 0x00, 0, 0}, {0x308d, 0x04, 0, 0}, {0x3086, 0x03, 0, 0},
+	{0x3086, 0x00, 0, 0}, {0x3011, 0x01, 0, 0},
 };
 
 static struct reg_value ov3640_setting_15fps_XGA_1024_768[] = {
@@ -674,6 +696,7 @@ static struct regulator *io_regulator;
 static struct regulator *core_regulator;
 static struct regulator *analog_regulator;
 static struct regulator *gpo_regulator;
+static struct mxc_camera_platform_data *camera_plat;
 
 static int ov3640_probe(struct i2c_client *adapter,
 				const struct i2c_device_id *device_id);
@@ -843,6 +866,10 @@ static int ioctl_s_power(struct v4l2_int_device *s, int on)
 		if (analog_regulator)
 			if (regulator_enable(analog_regulator) != 0)
 				return -EIO;
+		/* Make sure power on */
+		if (camera_plat->pwdn)
+			camera_plat->pwdn(0);
+
 	} else if (!on && sensor->on) {
 		if (analog_regulator)
 			regulator_disable(analog_regulator);
@@ -920,6 +947,10 @@ static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
 	enum ov3640_frame_rate frame_rate;
 	int ret = 0;
 
+	/* Make sure power on */
+	if (camera_plat->pwdn)
+		camera_plat->pwdn(0);
+
 	switch (a->type) {
 	/* This is the only case currently handled. */
 	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
@@ -1297,6 +1328,11 @@ static int ov3640_probe(struct i2c_client *client,
 			gpo_regulator = NULL;
 	}
 
+	if (plat_data->pwdn)
+		plat_data->pwdn(0);
+
+	camera_plat = plat_data;
+
 	ov3640_int_device.priv = &ov3640_data;
 	retval = v4l2_int_device_register(&ov3640_int_device);
 
diff --git a/drivers/media/video/mxc/output/mxc_v4l2_output.c b/drivers/media/video/mxc/output/mxc_v4l2_output.c
index 408f9b7871a8..0567298dcb7e 100644
--- a/drivers/media/video/mxc/output/mxc_v4l2_output.c
+++ b/drivers/media/video/mxc/output/mxc_v4l2_output.c
@@ -44,9 +44,7 @@ vout_data *g_vout;
 #define LOAD_3FIELDS(vout) ((INTERLACED_CONTENT(vout)) && \
 			    ((vout)->motion_sel != HIGH_MOTION))
 
-#define SDC_FG_FB_FORMAT        IPU_PIX_FMT_RGB565
-
-struct v4l2_output mxc_outputs[2] = {
+struct v4l2_output mxc_outputs[1] = {
 	{
 	 .index = MXC_V4L2_OUT_2_SDC,
 	 .name = "DISP3 Video Out",
@@ -54,23 +52,14 @@ struct v4l2_output mxc_outputs[2] = {
 						   but no other choice */
 	 .audioset = 0,
 	 .modulator = 0,
-	 .std = V4L2_STD_UNKNOWN},
-	{
-	 .index = MXC_V4L2_OUT_2_ADC,
-	 .name = "DISPx Video Out",
-	 .type = V4L2_OUTPUT_TYPE_ANALOG,	/* not really correct,
-						   but no other choice */
-	 .audioset = 0,
-	 .modulator = 0,
 	 .std = V4L2_STD_UNKNOWN}
 };
 
 static int video_nr = 16;
 static spinlock_t g_lock = SPIN_LOCK_UNLOCKED;
 static int last_index_n;
-static int last_index_c;
 static unsigned int ipu_ic_out_max_width_size;
-
+static unsigned int ipu_ic_out_max_height_size;
 /* debug counters */
 uint32_t g_irq_cnt;
 uint32_t g_buf_output_cnt;
@@ -260,6 +249,9 @@ static int select_display_buffer(vout_data *vout, int next_buf)
 			!= next_buf)
 		ret = ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER,
 				next_buf);
+	else
+		dev_dbg(&vout->video_dev->dev,
+			"display buffer not ready for select\n");
 	return ret;
 }
 
@@ -290,21 +282,55 @@ static void setup_next_buf_timer(vout_data *vout, int index)
 			"timer handler next schedule: %lu\n", timeout);
 }
 
-static int wait_for_disp_vsync(vout_data *vout)
+static int finish_previous_frame(vout_data *vout)
 {
 	struct fb_info *fbi =
 		registered_fb[vout->output_fb_num[vout->cur_disp_output]];
 	mm_segment_t old_fs;
 	int ret = 0;
 
-	/* wait for display frame finish */
-	if (fbi->fbops->fb_ioctl) {
-		old_fs = get_fs();
-		set_fs(KERNEL_DS);
-		ret = fbi->fbops->fb_ioctl(fbi, MXCFB_WAIT_FOR_VSYNC,
-			(unsigned int)NULL);
-		set_fs(old_fs);
+	/* make sure buf[next_done_ipu_buf] showed */
+	while (ipu_check_buffer_busy(vout->display_ch,
+			IPU_INPUT_BUFFER, vout->next_done_ipu_buf)) {
+		/* wait for display frame finish */
+		if (fbi->fbops->fb_ioctl) {
+			old_fs = get_fs();
+			set_fs(KERNEL_DS);
+			ret = fbi->fbops->fb_ioctl(fbi, MXCFB_WAIT_FOR_VSYNC,
+					(unsigned int)NULL);
+			set_fs(old_fs);
+
+			if (ret < 0) {
+				/* ic_bypass need clear display buffer ready for next update*/
+				ipu_clear_buffer_ready(vout->display_ch, IPU_INPUT_BUFFER,
+						vout->next_done_ipu_buf);
+			}
+		}
 	}
+
+	return ret;
+}
+
+static int show_current_frame(vout_data *vout)
+{
+	struct fb_info *fbi =
+		registered_fb[vout->output_fb_num[vout->cur_disp_output]];
+	mm_segment_t old_fs;
+	int ret = 0;
+
+	/* make sure buf[next_rdy_ipu_buf] begin to show */
+	if (ipu_get_cur_buffer_idx(vout->display_ch, IPU_INPUT_BUFFER)
+		!= vout->next_rdy_ipu_buf) {
+		/* wait for display frame finish */
+		if (fbi->fbops->fb_ioctl) {
+			old_fs = get_fs();
+			set_fs(KERNEL_DS);
+			ret = fbi->fbops->fb_ioctl(fbi, MXCFB_WAIT_FOR_VSYNC,
+					(unsigned int)NULL);
+			set_fs(old_fs);
+		}
+	}
+
 	return ret;
 }
 
@@ -316,84 +342,65 @@ static void timer_work_func(struct work_struct *work)
 	int last_buf;
 	unsigned long lock_flags = 0;
 
-	/* wait 2 first frame finish for ic bypass mode*/
-	if ((g_buf_output_cnt == 0) && vout->ic_bypass) {
-		wait_for_disp_vsync(vout);
-		wait_for_disp_vsync(vout);
-		spin_lock_irqsave(&g_lock, lock_flags);
-		last_buf = vout->ipu_buf[0];
-		vout->v4l2_bufs[last_buf].flags = V4L2_BUF_FLAG_DONE;
-		queue_buf(&vout->done_q, last_buf);
-		vout->ipu_buf[0] = -1;
-		last_buf = vout->ipu_buf[1];
-		vout->v4l2_bufs[last_buf].flags = V4L2_BUF_FLAG_DONE;
-		queue_buf(&vout->done_q, last_buf);
-		vout->ipu_buf[1] = -1;
-		g_buf_output_cnt = 2;
-		wake_up_interruptible(&vout->v4l_bufq);
-		if (vout->state == STATE_STREAM_PAUSED) {
-			index = peek_next_buf(&vout->ready_q);
-			if (index != -1) {
-				/* Setup timer for next buffer, when stream has been paused */
-				pr_debug("next index %d\n", index);
-				setup_next_buf_timer(vout, index);
-				vout->state = STATE_STREAM_ON;
-			}
-		}
-		spin_unlock_irqrestore(&g_lock, lock_flags);
-		return;
-	}
-
-	if (wait_for_disp_vsync(vout) < 0) {
-		/* ic_bypass need clear display buffer ready for next update*/
-		ipu_clear_buffer_ready(vout->display_ch, IPU_INPUT_BUFFER,
-			!vout->next_done_ipu_buf);
-	}
+	finish_previous_frame(vout);
 
 	spin_lock_irqsave(&g_lock, lock_flags);
 
-	if (vout->ic_bypass) {
-		last_buf = vout->ipu_buf[vout->next_done_ipu_buf];
-		if (last_buf != -1) {
-			g_buf_output_cnt++;
-			vout->v4l2_bufs[last_buf].flags = V4L2_BUF_FLAG_DONE;
-			queue_buf(&vout->done_q, last_buf);
-			wake_up_interruptible(&vout->v4l_bufq);
-			vout->ipu_buf[vout->next_done_ipu_buf] = -1;
-			vout->next_done_ipu_buf = !vout->next_done_ipu_buf;
+	if (g_buf_output_cnt == 0) {
+		ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 1);
+	} else {
+		index = dequeue_buf(&vout->ready_q);
+		if (index == -1) {	/* no buffers ready, should never occur */
+			dev_err(&vout->video_dev->dev,
+					"mxc_v4l2out: timer - no queued buffers ready\n");
+			goto exit;
 		}
-	}
-
-	if (vout->ic_bypass)
-		ret = select_display_buffer(vout, vout->next_rdy_ipu_buf);
-	else if (LOAD_3FIELDS(vout))
-		ret = ipu_select_multi_vdi_buffer(vout->next_rdy_ipu_buf);
-	else
-		ret = ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER,
-				vout->next_rdy_ipu_buf);
-	if (ret < 0) {
-		dev_err(&vout->video_dev->dev,
-				"unable to set IPU buffer ready\n");
-	}
+		g_buf_dq_cnt++;
+		vout->frame_count++;
 
-	/* Non IC split action */
-	if (!vout->pp_split)
+		vout->ipu_buf[vout->next_rdy_ipu_buf] = index;
+		ret = ipu_update_channel_buffer(vout->display_ch, IPU_INPUT_BUFFER,
+				vout->next_rdy_ipu_buf,
+				vout->v4l2_bufs[index].m.offset);
+		ret += select_display_buffer(vout, vout->next_rdy_ipu_buf);
+		if (ret < 0) {
+			dev_err(&vout->video_dev->dev,
+					"unable to update buffer %d address rc=%d\n",
+					vout->next_rdy_ipu_buf, ret);
+			goto exit;
+		}
+		spin_unlock_irqrestore(&g_lock, lock_flags);
+		show_current_frame(vout);
+		spin_lock_irqsave(&g_lock, lock_flags);
 		vout->next_rdy_ipu_buf = !vout->next_rdy_ipu_buf;
+	}
 
-	/* Setup timer for next buffer */
-	index = peek_next_buf(&vout->ready_q);
-	if (index != -1)
-		setup_next_buf_timer(vout, index);
-	else
-		vout->state = STATE_STREAM_PAUSED;
+	last_buf = vout->ipu_buf[vout->next_done_ipu_buf];
+	if (last_buf != -1) {
+		g_buf_output_cnt++;
+		vout->v4l2_bufs[last_buf].flags = V4L2_BUF_FLAG_DONE;
+		queue_buf(&vout->done_q, last_buf);
+		wake_up_interruptible(&vout->v4l_bufq);
+		vout->ipu_buf[vout->next_done_ipu_buf] = -1;
+		vout->next_done_ipu_buf = !vout->next_done_ipu_buf;
+	}
 
-	spin_unlock_irqrestore(&g_lock, lock_flags);
+	if (g_buf_output_cnt > 0) {
+		/* Setup timer for next buffer */
+		index = peek_next_buf(&vout->ready_q);
+		if (index != -1)
+			setup_next_buf_timer(vout, index);
+		else
+			vout->state = STATE_STREAM_PAUSED;
 
-	if (vout->state == STATE_STREAM_STOPPING) {
-		if ((vout->ipu_buf[0] == -1) && (vout->ipu_buf[1] == -1)) {
-			vout->state = STATE_STREAM_OFF;
+		if (vout->state == STATE_STREAM_STOPPING) {
+			if ((vout->ipu_buf[0] == -1) && (vout->ipu_buf[1] == -1)) {
+				vout->state = STATE_STREAM_OFF;
+			}
 		}
 	}
+exit:
+	spin_unlock_irqrestore(&g_lock, lock_flags);
 }
 
 static void mxc_v4l2out_timer_handler(unsigned long arg)
@@ -401,13 +408,13 @@ static void mxc_v4l2out_timer_handler(unsigned long arg)
 	int index, ret;
 	unsigned long lock_flags = 0;
 	vout_data *vout = (vout_data *) arg;
-	unsigned int aid_field_offset = 0, current_field_offset = 0;
 
 	spin_lock_irqsave(&g_lock, lock_flags);
 
 	if ((vout->state == STATE_STREAM_STOPPING)
 	    || (vout->state == STATE_STREAM_OFF))
 		goto exit0;
+
 	/*
 	 * If timer occurs before IPU h/w is ready, then set the state to
 	 * paused and the timer will be set again when next buffer is queued
@@ -419,98 +426,82 @@ static void mxc_v4l2out_timer_handler(unsigned long arg)
 		goto exit0;
 	}
 
-	/* Dequeue buffer and pass to IPU */
-	if (INTERLACED_CONTENT(vout)) {
-		if (((LOAD_3FIELDS(vout)) && (vout->next_rdy_ipu_buf)) ||
-		    ((!LOAD_3FIELDS(vout)) && !(vout->next_rdy_ipu_buf))) {
-			aid_field_offset = vout->bytesperline;
-			current_field_offset = 0;
-			index = last_index_n;
-		} else {
-			aid_field_offset = 0;
-			current_field_offset = vout->bytesperline;
-			index = dequeue_buf(&vout->ready_q);
-			if (index == -1) {	/* no buffers ready, should never occur */
-				dev_err(&vout->video_dev->dev,
-					"mxc_v4l2out: timer - no queued buffers ready\n");
-				goto exit0;
-			}
-			g_buf_dq_cnt++;
-			vout->frame_count++;
-			last_index_n = index;
-		}
-	} else {
-		current_field_offset = 0;
-		index = dequeue_buf(&vout->ready_q);
-		if (index == -1) {	/* no buffers ready, should never occur */
-			dev_err(&vout->video_dev->dev,
-				"mxc_v4l2out: timer - no queued buffers ready\n");
-			goto exit0;
+	/* VDI need both buffer done before update buffer? */
+	if (INTERLACED_CONTENT(vout) &&
+		(vout->ipu_buf[!vout->next_rdy_ipu_buf] != -1)) {
+		dev_dbg(&vout->video_dev->dev, "IPU buffer busy\n");
+		vout->state = STATE_STREAM_PAUSED;
+		goto exit0;
+	}
+
+	/* Handle ic bypass mode in work queue */
+	if (vout->ic_bypass) {
+		if (queue_work(vout->v4l_wq, &vout->timer_work) == 0) {
+			dev_err(&vout->video_dev->dev, "work was in queue already!\n ");
+			vout->state = STATE_STREAM_PAUSED;
 		}
-		g_buf_dq_cnt++;
-		vout->frame_count++;
+		goto exit0;
 	}
 
+	/* Dequeue buffer and pass to IPU */
+	index = dequeue_buf(&vout->ready_q);
+	if (index == -1) {	/* no buffers ready, should never occur */
+		dev_err(&vout->video_dev->dev,
+			"mxc_v4l2out: timer - no queued buffers ready\n");
+		goto exit0;
+	}
+	g_buf_dq_cnt++;
+	vout->frame_count++;
+
 	/* update next buffer */
-	if (vout->ic_bypass) {
+	if (LOAD_3FIELDS(vout)) {
+		int index_n = index;
+		int index_p = last_index_n;
+		vout->ipu_buf_p[vout->next_rdy_ipu_buf] = last_index_n;
 		vout->ipu_buf[vout->next_rdy_ipu_buf] = index;
-		ret = ipu_update_channel_buffer(vout->display_ch, IPU_INPUT_BUFFER,
-				      vout->next_rdy_ipu_buf,
-				      vout->v4l2_bufs[index].m.offset);
+		vout->ipu_buf_n[vout->next_rdy_ipu_buf] = index;
+		ret = ipu_update_channel_buffer(vout->post_proc_ch,
+				IPU_INPUT_BUFFER,
+				vout->next_rdy_ipu_buf,
+				vout->v4l2_bufs[index].m.offset);
+		ret += ipu_update_channel_buffer(MEM_VDI_PRP_VF_MEM_P,
+				IPU_INPUT_BUFFER,
+				vout->next_rdy_ipu_buf,
+				vout->v4l2_bufs[index_p].m.offset + vout->bytesperline);
+		ret += ipu_update_channel_buffer(MEM_VDI_PRP_VF_MEM_N,
+				IPU_INPUT_BUFFER,
+				vout->next_rdy_ipu_buf,
+				vout->v4l2_bufs[index_n].m.offset) + vout->bytesperline;
+		last_index_n = index;
 	} else {
-		if (LOAD_3FIELDS(vout)) {
-			int index_n = index;
-			int index_p = last_index_c;
-			index = last_index_n;
-			vout->ipu_buf_p[vout->next_rdy_ipu_buf] = index_p;
-			vout->ipu_buf[vout->next_rdy_ipu_buf] = last_index_c = index;
-			vout->ipu_buf_n[vout->next_rdy_ipu_buf] = last_index_n = index_n;
-			last_index_n = vout->ipu_buf_n[vout->next_rdy_ipu_buf];
-			last_index_c = vout->ipu_buf[vout->next_rdy_ipu_buf];
+		vout->ipu_buf[vout->next_rdy_ipu_buf] = index;
+		if (vout->pp_split) {
+			vout->ipu_buf[!vout->next_rdy_ipu_buf] = index;
+			/* always left stripe */
 			ret = ipu_update_channel_buffer(vout->post_proc_ch,
-							IPU_INPUT_BUFFER,
-							vout->next_rdy_ipu_buf,
-							vout->v4l2_bufs[index].m.offset+current_field_offset);
-			ret += ipu_update_channel_buffer(MEM_VDI_PRP_VF_MEM_P,
-							 IPU_INPUT_BUFFER,
-							 vout->next_rdy_ipu_buf,
-							 vout->v4l2_bufs[index_p].m.offset+aid_field_offset);
-			ret += ipu_update_channel_buffer(MEM_VDI_PRP_VF_MEM_N,
-							 IPU_INPUT_BUFFER,
-							 vout->next_rdy_ipu_buf,
-							 vout->v4l2_bufs[index_n].m.offset+aid_field_offset);
-		} else {
-			vout->ipu_buf[vout->next_rdy_ipu_buf] = index;
-			if (vout->pp_split) {
-				vout->ipu_buf[!vout->next_rdy_ipu_buf] = index;
-				/* always left stripe */
-				ret = ipu_update_channel_buffer(vout->post_proc_ch,
-									IPU_INPUT_BUFFER,
-									0,/* vout->next_rdy_ipu_buf,*/
-									(vout->v4l2_bufs[index].m.offset) +
-									vout->pp_left_stripe.input_column +
-									current_field_offset);
-
-				/* the U/V offset has to be updated inside of IDMAC */
-				/* according to stripe offset */
-				ret += ipu_update_channel_offset(vout->post_proc_ch,
-									IPU_INPUT_BUFFER,
-									vout->v2f.fmt.pix.pixelformat,
-									vout->v2f.fmt.pix.width,
-									vout->v2f.fmt.pix.height,
-									vout->bytesperline,
-									vout->offset.u_offset,
-									vout->offset.v_offset,
-									0,
-									vout->pp_left_stripe.input_column + current_field_offset);
-
-			} else
-				ret = ipu_update_channel_buffer(vout->post_proc_ch,
-									IPU_INPUT_BUFFER,
-									vout->next_rdy_ipu_buf,
-									vout->v4l2_bufs[index].m.offset +
-									current_field_offset);
-		}
+					IPU_INPUT_BUFFER,
+					0,/* vout->next_rdy_ipu_buf,*/
+					(vout->v4l2_bufs[index].m.offset) +
+					vout->pp_left_stripe.input_column +
+					vout->pp_up_stripe.input_column * vout->bytesperline);
+
+			/* the U/V offset has to be updated inside of IDMAC */
+			/* according to stripe offset */
+			ret += ipu_update_channel_offset(vout->post_proc_ch,
+					IPU_INPUT_BUFFER,
+					vout->v2f.fmt.pix.pixelformat,
+					vout->v2f.fmt.pix.width,
+					vout->v2f.fmt.pix.height,
+					vout->bytesperline,
+					vout->offset.u_offset,
+					vout->offset.v_offset,
+					vout->pp_up_stripe.input_column,
+					vout->pp_left_stripe.input_column);
+		} else
+			ret = ipu_update_channel_buffer(vout->post_proc_ch,
+					IPU_INPUT_BUFFER,
+					vout->next_rdy_ipu_buf,
+					vout->v4l2_bufs[index].m.offset);
 	}
 
 	if (ret < 0) {
@@ -521,9 +512,32 @@ static void mxc_v4l2out_timer_handler(unsigned long arg)
 	}
 
 	/* set next buffer ready */
-	if (queue_work(vout->v4l_wq, &vout->timer_work) == 0) {
-		dev_err(&vout->video_dev->dev, "work was in queue already!\n ");
+	if (LOAD_3FIELDS(vout))
+		ret = ipu_select_multi_vdi_buffer(vout->next_rdy_ipu_buf);
+	else
+		ret = ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER,
+				vout->next_rdy_ipu_buf);
+	if (ret < 0) {
+		dev_err(&vout->video_dev->dev,
+				"unable to set IPU buffer ready\n");
+		goto exit0;
+	}
+
+	/* Non IC split action */
+	if (!vout->pp_split)
+		vout->next_rdy_ipu_buf = !vout->next_rdy_ipu_buf;
+
+	/* Setup timer for next buffer */
+	index = peek_next_buf(&vout->ready_q);
+	if (index != -1)
+		setup_next_buf_timer(vout, index);
+	else
 		vout->state = STATE_STREAM_PAUSED;
+
+	if (vout->state == STATE_STREAM_STOPPING) {
+		if ((vout->ipu_buf[0] == -1) && (vout->ipu_buf[1] == -1)) {
+			vout->state = STATE_STREAM_OFF;
+		}
 	}
 
 	spin_unlock_irqrestore(&g_lock, lock_flags);
@@ -540,12 +554,15 @@ static irqreturn_t mxc_v4l2out_work_irq_handler(int irq, void *dev_id)
 	int index;
 	unsigned long lock_flags = 0;
 	vout_data *vout = dev_id;
-	int pp_out_buf_num = 0;
+	int pp_out_buf_left_right = 0;
 	int disp_buf_num = 0;
 	int disp_buf_num_next = 1;
+	int local_buffer = 0;
 	int pp_out_buf_offset = 0;
+	int pp_out_buf_up_down = 0;
 	int release_buffer = 0;
-	u32 eba_offset;
+	u32 eba_offset = 0;
+	u32 vertical_offset = 0;
 	u16 x_pos;
 	u16 y_pos;
 	int ret = -1;
@@ -563,17 +580,37 @@ static irqreturn_t mxc_v4l2out_work_irq_handler(int irq, void *dev_id)
 	if (last_buf != -1) {
 		/* If IC split mode on, update output buffer number */
 		if (vout->pp_split) {
-			pp_out_buf_num = vout->pp_split_buf_num & 1;/* left/right stripe */
-			disp_buf_num = vout->pp_split_buf_num >> 1;
-			disp_buf_num_next = ((vout->pp_split_buf_num+2) & 3) >> 1;
-			if (!pp_out_buf_num) {/* next buffer is right stripe*/
-				eba_offset = vout->pp_right_stripe.input_column;/*always right stripe*/
+			pp_out_buf_up_down = vout->pp_split_buf_num & 1;/* left/right stripe */
+			pp_out_buf_left_right = (vout->pp_split_buf_num >> 1) & 1; /* up/down */
+			local_buffer = (vout->pp_split == 1) ? pp_out_buf_up_down :
+					pp_out_buf_left_right;
+			disp_buf_num = vout->pp_split_buf_num >> 2;
+			disp_buf_num_next =
+					((vout->pp_split_buf_num + (vout->pp_split << 0x1)) & 7) >> 2;
+			if ((!pp_out_buf_left_right) ||
+				((!pp_out_buf_up_down) && (vout->pp_split == 1))) {
+				if (vout->pp_split == 1) {
+						eba_offset = ((pp_out_buf_left_right + pp_out_buf_up_down) & 1) ?
+									vout->pp_right_stripe.input_column :
+									vout->pp_left_stripe.input_column;
+						vertical_offset = pp_out_buf_up_down ?
+									vout->pp_up_stripe.input_column :
+									vout->pp_down_stripe.input_column;
+
+				} else {
+						eba_offset = pp_out_buf_left_right ?
+									vout->pp_left_stripe.input_column :
+									vout->pp_right_stripe.input_column;
+						vertical_offset = pp_out_buf_left_right ?
+									vout->pp_up_stripe.input_column :
+									vout->pp_down_stripe.input_column;
+				}
+
 				ret = ipu_update_channel_buffer(vout->post_proc_ch,
 						IPU_INPUT_BUFFER,
-						1, /* right stripe */
+						(1 - local_buffer),
 						(vout->v4l2_bufs[vout->ipu_buf[disp_buf_num]].m.offset)
-						+ eba_offset);
-
+						+ eba_offset + vertical_offset * vout->bytesperline);
 				ret += ipu_update_channel_offset(vout->post_proc_ch,
 								IPU_INPUT_BUFFER,
 								vout->v2f.fmt.pix.pixelformat,
@@ -582,46 +619,65 @@ static irqreturn_t mxc_v4l2out_work_irq_handler(int irq, void *dev_id)
 								vout->bytesperline,
 								vout->offset.u_offset,
 								vout->offset.v_offset,
-								0,
-								vout->pp_right_stripe.input_column);
+								vertical_offset,
+								eba_offset);
 
 				/* select right stripe */
-				ret += ipu_select_buffer(vout->post_proc_ch,
-												IPU_INPUT_BUFFER, 1);
+				ret += ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER,
+							(1 - local_buffer));
 				if (ret < 0)
 					dev_err(&vout->video_dev->dev,
 					"unable to set IPU buffer ready\n");
+					vout->next_rdy_ipu_buf = !vout->next_rdy_ipu_buf;
 
+			} else {/* last stripe is done, run display refresh */
+				select_display_buffer(vout, disp_buf_num);
 				vout->ipu_buf[vout->next_done_ipu_buf] = -1;
 				vout->next_done_ipu_buf = !vout->next_done_ipu_buf;
-
-			} else /* right stripe is done, run display refresh */
-				select_display_buffer(vout, disp_buf_num);
-
-			vout->next_rdy_ipu_buf = !vout->next_rdy_ipu_buf;
+				vout->next_rdy_ipu_buf = !vout->next_rdy_ipu_buf;
+			}
 
 			/* offset for next buffer's EBA */
-			pp_out_buf_offset = pp_out_buf_num ? vout->pp_right_stripe.output_column :
-				vout->pp_left_stripe.output_column;
 			eba_offset = 0;
+			if (vout->pp_split == 1) {
+				pp_out_buf_offset = ((vout->pp_split_buf_num >> 1) & 1) ?
+								vout->pp_left_stripe.output_column :
+								vout->pp_right_stripe.output_column;
+
+				eba_offset = ((vout->pp_split_buf_num & 1) ?
+								vout->pp_down_stripe.output_column :
+								vout->pp_up_stripe.output_column);
+
+			} else {
+				pp_out_buf_offset = ((vout->pp_split_buf_num >> 1) & 1) ?
+									vout->pp_right_stripe.output_column :
+									vout->pp_left_stripe.output_column;
+				eba_offset = ((vout->pp_split_buf_num >> 1) & 1) ?
+									vout->pp_down_stripe.output_column :
+									vout->pp_up_stripe.output_column;
+			}
+
 			if (vout->cur_disp_output == 5) {
 				x_pos = (vout->crop_current.left / 8) * 8;
 				y_pos = vout->crop_current.top;
-				eba_offset = (vout->xres * y_pos + x_pos) * vout->bpp / 8;
+				eba_offset += (vout->xres * y_pos + x_pos) * vout->bpp / 8;
 			}
 
+
 			/* next buffer update */
 			eba_offset = vout->display_bufs[disp_buf_num_next] +
-								pp_out_buf_offset + eba_offset;
+						pp_out_buf_offset + eba_offset;
 
 			ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER,
-												pp_out_buf_num, eba_offset);
+						local_buffer, eba_offset);
 
 			/* next buffer ready */
-			ret = ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, pp_out_buf_num);
+			ret = ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, local_buffer);
+
+			/* next stripe_buffer index 0..7 */
+			vout->pp_split_buf_num = (vout->pp_split_buf_num + vout->pp_split) & 0x7;
+
 
-			/* next stripe_buffer index 0..3 */
-			vout->pp_split_buf_num = (vout->pp_split_buf_num + 1) & 3;
 		} else {
 			/* show to display */
 			select_display_buffer(vout, vout->next_done_ipu_buf);
@@ -630,14 +686,12 @@ static irqreturn_t mxc_v4l2out_work_irq_handler(int irq, void *dev_id)
 		}
 
 		/* release buffer. For split mode: if second stripe is done */
-		release_buffer = vout->pp_split ? pp_out_buf_num : 1;
+		release_buffer = vout->pp_split ? (!(vout->pp_split_buf_num & 0x3)) : 1;
 		if (release_buffer) {
-			if ((!INTERLACED_CONTENT(vout)) || (vout->next_done_ipu_buf)) {
-				g_buf_output_cnt++;
-				vout->v4l2_bufs[last_buf].flags = V4L2_BUF_FLAG_DONE;
-				queue_buf(&vout->done_q, last_buf);
-				wake_up_interruptible(&vout->v4l_bufq);
-			}
+			g_buf_output_cnt++;
+			vout->v4l2_bufs[last_buf].flags = V4L2_BUF_FLAG_DONE;
+			queue_buf(&vout->done_q, last_buf);
+			wake_up_interruptible(&vout->v4l_bufq);
 			vout->ipu_buf[vout->next_done_ipu_buf] = -1;
 			if (LOAD_3FIELDS(vout)) {
 				vout->ipu_buf_p[vout->next_done_ipu_buf] = -1;
@@ -702,7 +756,6 @@ static int init_VDI_channel(vout_data *vout, ipu_channel_params_t params)
 static int init_VDI_in_channel_buffer(vout_data *vout, uint32_t in_pixel_fmt,
 				   uint16_t in_width, uint16_t in_height,
 				   uint32_t stride,
-				   dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
 				   uint32_t u_offset, uint32_t v_offset)
 {
 	struct device *dev = &vout->video_dev->dev;
@@ -710,7 +763,7 @@ static int init_VDI_in_channel_buffer(vout_data *vout, uint32_t in_pixel_fmt,
 	if (ipu_init_channel_buffer(MEM_VDI_PRP_VF_MEM, IPU_INPUT_BUFFER,
 				    in_pixel_fmt, in_width, in_height, stride,
 				    IPU_ROTATE_NONE,
-				    vout->v4l2_bufs[vout->ipu_buf[0]].m.offset+vout->bytesperline,
+				    vout->v4l2_bufs[vout->ipu_buf[0]].m.offset,
 				    vout->v4l2_bufs[vout->ipu_buf[0]].m.offset,
 				    u_offset, v_offset) != 0) {
 		dev_err(dev, "Error initializing VDI current input buffer\n");
@@ -721,7 +774,7 @@ static int init_VDI_in_channel_buffer(vout_data *vout, uint32_t in_pixel_fmt,
 					    IPU_INPUT_BUFFER,
 					    in_pixel_fmt, in_width, in_height,
 					    stride, IPU_ROTATE_NONE,
-					    vout->v4l2_bufs[vout->ipu_buf_p[0]].m.offset,
+					    vout->v4l2_bufs[vout->ipu_buf_p[0]].m.offset+vout->bytesperline,
 					    vout->v4l2_bufs[vout->ipu_buf_p[0]].m.offset+vout->bytesperline,
 					    u_offset, v_offset) != 0) {
 			dev_err(dev, "Error initializing VDI previous input buffer\n");
@@ -731,7 +784,7 @@ static int init_VDI_in_channel_buffer(vout_data *vout, uint32_t in_pixel_fmt,
 					    IPU_INPUT_BUFFER,
 					    in_pixel_fmt, in_width, in_height,
 					    stride, IPU_ROTATE_NONE,
-					    vout->v4l2_bufs[vout->ipu_buf_n[0]].m.offset,
+					    vout->v4l2_bufs[vout->ipu_buf_n[0]].m.offset+vout->bytesperline,
 					    vout->v4l2_bufs[vout->ipu_buf_n[0]].m.offset+vout->bytesperline,
 					    u_offset, v_offset) != 0) {
 			dev_err(dev, "Error initializing VDI next input buffer\n");
@@ -759,10 +812,7 @@ static int init_VDI(ipu_channel_params_t params, vout_data *vout,
 	params.mem_prp_vf_mem.in_pixel_fmt = vout->v2f.fmt.pix.pixelformat;
 	params.mem_prp_vf_mem.out_width = out_width;
 	params.mem_prp_vf_mem.out_height = out_height;
-	if (vout->display_ch == ADC_SYS2)
-		params.mem_prp_vf_mem.out_pixel_fmt = SDC_FG_FB_FORMAT;
-	else
-		params.mem_prp_vf_mem.out_pixel_fmt = bpp_to_fmt(fbi);
+	params.mem_prp_vf_mem.out_pixel_fmt = bpp_to_fmt(fbi);
 
 	if (init_VDI_channel(vout, params) != 0) {
 		dev_err(dev, "Error init_VDI_channel channel\n");
@@ -775,8 +825,6 @@ static int init_VDI(ipu_channel_params_t params, vout_data *vout,
 				       params.mem_prp_vf_mem.in_height,
 				       bytes_per_pixel(params.mem_prp_vf_mem.
 						       in_pixel_fmt),
-				       vout->v4l2_bufs[vout->ipu_buf[0]].m.offset,
-				       vout->v4l2_bufs[vout->ipu_buf[1]].m.offset,
 				       vout->offset.u_offset,
 				       vout->offset.v_offset) != 0) {
 		return -EINVAL;
@@ -805,7 +853,6 @@ static int init_VDI(ipu_channel_params_t params, vout_data *vout,
 			dev_err(dev, "Error initializing PRP output buffer\n");
 			return -EINVAL;
 		}
-
 		if (ipu_init_channel(MEM_ROT_VF_MEM, NULL) != 0) {
 			dev_err(dev, "Error initializing PP ROT channel\n");
 			return -EINVAL;
@@ -887,10 +934,7 @@ static int init_PP(ipu_channel_params_t *params, vout_data *vout,
 	x_pos = 0;
 	y_pos = 0;
 
-	if (vout->display_ch == ADC_SYS2)
-		params->mem_pp_mem.out_pixel_fmt = SDC_FG_FB_FORMAT;
-	else
-		params->mem_pp_mem.out_pixel_fmt = bpp_to_fmt(fbi);
+	params->mem_pp_mem.out_pixel_fmt = bpp_to_fmt(fbi);
 
 	if (vout->cur_disp_output == 5) {
 		x_pos = (vout->crop_current.left / 8) * 8;
@@ -907,37 +951,66 @@ static int init_PP(ipu_channel_params_t *params, vout_data *vout,
 	params->mem_pp_mem.in_pixel_fmt = vout->v2f.fmt.pix.pixelformat;
 	params->mem_pp_mem.out_width = out_width;
 	params->mem_pp_mem.out_height = out_height;
-	params->mem_pp_mem.out_resize_ratio = 0; /* 0 means unused */
-
+	params->mem_pp_mem.outh_resize_ratio = 0; /* 0 means unused */
+	params->mem_pp_mem.outv_resize_ratio = 0; /* 0 means unused */
 	/* split IC by two stripes, the by pass is impossible*/
 	if (vout->pp_split) {
-		ipu_calc_stripes_sizes(
-					params->mem_pp_mem.in_width, /* input frame width;>1 */
-					params->mem_pp_mem.out_width, /* output frame width; >1 */
-					ipu_ic_out_max_width_size,
-					(((unsigned long long)1) << 32), /* 32bit for fractional*/
-					1,	/* equal stripes */
-					params->mem_pp_mem.in_pixel_fmt,
-					params->mem_pp_mem.out_pixel_fmt,
-					&(vout->pp_left_stripe),
-					&(vout->pp_right_stripe));
-
-		vout->pp_left_stripe.input_column = vout->pp_left_stripe.input_column *
+		vout->pp_left_stripe.input_column = 0;
+		vout->pp_left_stripe.output_column = 0;
+		vout->pp_right_stripe.input_column = 0;
+		vout->pp_right_stripe.output_column = 0;
+		vout->pp_up_stripe.input_column = 0;
+		vout->pp_up_stripe.output_column = 0;
+		vout->pp_down_stripe.input_column = 0;
+		vout->pp_down_stripe.output_column = 0;
+		if (vout->pp_split != 3) {
+			ipu_calc_stripes_sizes(
+				params->mem_pp_mem.in_width, /* input frame width;>1 */
+				params->mem_pp_mem.out_width, /* output frame width; >1 */
+				ipu_ic_out_max_width_size,
+				(((unsigned long long)1) << 32), /* 32bit for fractional*/
+				1,	/* equal stripes */
+				params->mem_pp_mem.in_pixel_fmt,
+				params->mem_pp_mem.out_pixel_fmt,
+				&(vout->pp_left_stripe),
+				&(vout->pp_right_stripe));
+
+			vout->pp_left_stripe.input_column = vout->pp_left_stripe.input_column *
 								fmt_to_bpp(vout->v2f.fmt.pix.pixelformat) / 8;
-		vout->pp_left_stripe.output_column = vout->pp_left_stripe.output_column *
+			vout->pp_left_stripe.output_column = vout->pp_left_stripe.output_column *
 								fmt_to_bpp(params->mem_pp_mem.out_pixel_fmt) / 8;
-		vout->pp_right_stripe.input_column = vout->pp_right_stripe.input_column *
+			vout->pp_right_stripe.input_column = vout->pp_right_stripe.input_column *
 								fmt_to_bpp(vout->v2f.fmt.pix.pixelformat) / 8;
-		vout->pp_right_stripe.output_column = vout->pp_right_stripe.output_column *
+			vout->pp_right_stripe.output_column = vout->pp_right_stripe.output_column *
 								fmt_to_bpp(params->mem_pp_mem.out_pixel_fmt) / 8;
 
+
 		/* updare parameters */
 		params->mem_pp_mem.in_width = vout->pp_left_stripe.input_width;
 		params->mem_pp_mem.out_width = vout->pp_left_stripe.output_width;
 		out_width = vout->pp_left_stripe.output_width;
 		/* for using in ic_init*/
-		params->mem_pp_mem.out_resize_ratio = vout->pp_left_stripe.irr;
-
+		params->mem_pp_mem.outh_resize_ratio = vout->pp_left_stripe.irr;
+		}
+		if (vout->pp_split != 2) {
+			ipu_calc_stripes_sizes(
+				params->mem_pp_mem.in_height, /* input frame width;>1 */
+				params->mem_pp_mem.out_height, /* output frame width; >1 */
+				ipu_ic_out_max_height_size,
+				(((unsigned long long)1) << 32),/* 32bit for fractional */
+				1,	/* equal stripes */
+				params->mem_pp_mem.in_pixel_fmt,
+				params->mem_pp_mem.out_pixel_fmt,
+				&(vout->pp_up_stripe),
+				&(vout->pp_down_stripe));
+			vout->pp_down_stripe.output_column = vout->pp_down_stripe.output_column * out_stride;
+			vout->pp_up_stripe.output_column = vout->pp_up_stripe.output_column * out_stride;
+			params->mem_pp_mem.outv_resize_ratio = vout->pp_up_stripe.irr;
+			params->mem_pp_mem.in_height = vout->pp_up_stripe.input_width;/*height*/
+			out_height = vout->pp_up_stripe.output_width;/*height*/
+			if (vout->pp_split == 3)
+				vout->pp_split = 2;/*2 vertical stripe as two horizontal stripes */
+		}
 		vout->pp_split_buf_num = 0;
 	}
 
@@ -1048,20 +1121,27 @@ static int init_PP(ipu_channel_params_t *params, vout_data *vout,
 		ipu_update_channel_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER,
 									0,
 									vout->v4l2_bufs[vout->ipu_buf[0]].m.offset +
-									vout->pp_left_stripe.input_column);
+									vout->pp_left_stripe.input_column +
+									vout->pp_up_stripe.input_column * vout->bytesperline);
+
+
 		ipu_update_channel_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER,
 									1,
 									vout->v4l2_bufs[vout->ipu_buf[0]].m.offset +
-									vout->pp_right_stripe.input_column);
+									vout->pp_right_stripe.input_column +
+									vout->pp_up_stripe.input_column * vout->bytesperline);
+
 		ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER,
 									0,
 									vout->display_bufs[0] + eba_offset +
-									vout->pp_left_stripe.output_column);
+									vout->pp_left_stripe.output_column +
+									vout->pp_up_stripe.output_column);
 
 		ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER,
 									1,
 									vout->display_bufs[0] + eba_offset +
-									vout->pp_right_stripe.output_column);
+									vout->pp_right_stripe.output_column +
+									vout->pp_up_stripe.output_column);
 	}
 
 	return 0;
@@ -1084,8 +1164,8 @@ static int mxc_v4l2out_streamon(vout_data * vout)
 	    registered_fb[vout->output_fb_num[vout->cur_disp_output]];
 	u16 out_width;
 	u16 out_height;
-	bool use_direct_adc = false;
 	mm_segment_t old_fs;
+	unsigned int ipu_ch = CHAN_NONE;
 	int rc = 0;
 
 	dev_dbg(dev, "mxc_v4l2out_streamon: field format=%d\n",
@@ -1107,28 +1187,44 @@ static int mxc_v4l2out_streamon(vout_data * vout)
 		return -EINVAL;
 	}
 
+	/*
+	 * params init, check whether operation exceed the IC limitation:
+	 * whether split mode used ( ipu version >= ipuv3 only)
+	 */
 	g_irq_cnt = g_buf_output_cnt = g_buf_q_cnt = g_buf_dq_cnt = 0;
 	out_width = vout->crop_current.width;
 	out_height = vout->crop_current.height;
 	vout->next_done_ipu_buf = 0;
 	vout->next_rdy_ipu_buf = 1;
 	vout->pp_split = 0;
-
-	if (!INTERLACED_CONTENT(vout)) {
-		vout->next_done_ipu_buf = vout->next_rdy_ipu_buf = 0;
-		vout->ipu_buf[0] = dequeue_buf(&vout->ready_q);
+	ipu_ic_out_max_height_size = 1024;
 #ifdef CONFIG_MXC_IPU_V1
+	if (cpu_is_mx35())
 		ipu_ic_out_max_width_size = 800;
+	else
+		ipu_ic_out_max_width_size = 720;
 #else
-		ipu_ic_out_max_width_size = 1024;
+	ipu_ic_out_max_width_size = 1024;
 #endif
+	if ((out_width > ipu_ic_out_max_width_size) ||
+		(out_height > ipu_ic_out_max_height_size))
+		vout->pp_split = 4;
+	if (!INTERLACED_CONTENT(vout)) {
+		vout->next_done_ipu_buf = vout->next_rdy_ipu_buf = 0;
+		vout->ipu_buf[0] = dequeue_buf(&vout->ready_q);
 		/* split IC by two stripes, the by pass is impossible*/
 		if ((out_width != vout->v2f.fmt.pix.width ||
 			out_height != vout->v2f.fmt.pix.height) &&
-			out_width > ipu_ic_out_max_width_size) {
-			vout->pp_split = 1;
+			vout->pp_split) {
 			vout->ipu_buf[1] = vout->ipu_buf[0];
 			vout->frame_count = 1;
+			if ((out_width > ipu_ic_out_max_width_size) &&
+				(out_height > ipu_ic_out_max_height_size))
+				vout->pp_split = 1; /*4 stripes*/
+			else if (!(out_height > ipu_ic_out_max_height_size))
+				vout->pp_split = 2; /*two horizontal stripes */
+			else
+				vout->pp_split = 3; /*2 vertical stripes*/
 		} else {
 			vout->ipu_buf[1] = dequeue_buf(&vout->ready_q);
 			vout->frame_count = 2;
@@ -1137,211 +1233,84 @@ static int mxc_v4l2out_streamon(vout_data * vout)
 		vout->ipu_buf[0] = dequeue_buf(&vout->ready_q);
 		vout->ipu_buf[1] = -1;
 		vout->frame_count = 1;
-		last_index_n = vout->ipu_buf[0];
 	} else {
 		vout->ipu_buf_p[0] = dequeue_buf(&vout->ready_q);
-		vout->ipu_buf[0] = vout->ipu_buf_p[0];
-		vout->ipu_buf_n[0] = dequeue_buf(&vout->ready_q);
+		vout->ipu_buf[0] = dequeue_buf(&vout->ready_q);
+		vout->ipu_buf_n[0] = vout->ipu_buf[0];
 		vout->ipu_buf_p[1] = -1;
 		vout->ipu_buf[1] = -1;
 		vout->ipu_buf_n[1] = -1;
-		last_index_c = vout->ipu_buf[0];
 		last_index_n = vout->ipu_buf_n[0];
 		vout->frame_count = 2;
 	}
 
-	/* Init Display Channel */
-#ifdef CONFIG_FB_MXC_ASYNC_PANEL
-	if (vout->cur_disp_output < DISP3) {
-		vout->work_irq = IPU_IRQ_PP_IN_EOF;
-		ipu_clear_irq(vout->work_irq);
-		ipu_request_irq(vout->work_irq,
-				mxc_v4l2out_work_irq_handler,
-				0, vout->video_dev->name, vout);
-		mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_OFF, 0);
-		fbi = NULL;
-		if (ipu_can_rotate_in_place(vout->rotate)) {
-			dev_dbg(dev, "Using PP direct to ADC channel\n");
-			use_direct_adc = true;
-			vout->display_ch = MEM_PP_ADC;
-			vout->post_proc_ch = MEM_PP_ADC;
-
-			memset(&params, 0, sizeof(params));
-			params.mem_pp_adc.in_width = vout->v2f.fmt.pix.width;
-			params.mem_pp_adc.in_height = vout->v2f.fmt.pix.height;
-			params.mem_pp_adc.in_pixel_fmt =
-			    vout->v2f.fmt.pix.pixelformat;
-			params.mem_pp_adc.out_width = out_width;
-			params.mem_pp_adc.out_height = out_height;
-			params.mem_pp_adc.out_pixel_fmt = SDC_FG_FB_FORMAT;
-#ifdef CONFIG_FB_MXC_EPSON_PANEL
-			params.mem_pp_adc.out_left =
-			    2 + vout->crop_current.left;
-#else
-			params.mem_pp_adc.out_left =
-			    12 + vout->crop_current.left;
-#endif
-			params.mem_pp_adc.out_top = vout->crop_current.top;
-			if (ipu_init_channel(vout->post_proc_ch, &params) != 0) {
-				dev_err(dev, "Error initializing PP chan\n");
-				return -EINVAL;
-			}
-			if (ipu_init_channel_buffer(vout->post_proc_ch,
-						    IPU_INPUT_BUFFER,
-						    params.mem_pp_adc.
-						    in_pixel_fmt,
-						    params.mem_pp_adc.in_width,
-						    params.mem_pp_adc.in_height,
-						    vout->v2f.fmt.pix.
-						    bytesperline /
-						    bytes_per_pixel(params.
-								    mem_pp_adc.
-								    in_pixel_fmt),
-						    vout->rotate,
-						    vout->v4l2_bufs[vout->ipu_buf[0]].m.offset,
-						    vout->v4l2_bufs[vout->ipu_buf[1]].m.offset,
-						    vout->offset.u_offset,
-						    vout->offset.v_offset) !=
-			    0) {
-				dev_err(dev, "Error initializing PP in buf\n");
-				return -EINVAL;
-			}
-
-			if (ipu_init_channel_buffer(vout->post_proc_ch,
-						    IPU_OUTPUT_BUFFER,
-						    params.mem_pp_adc.
-						    out_pixel_fmt, out_width,
-						    out_height, out_width,
-						    vout->rotate, 0, 0, 0,
-						    0) != 0) {
-				dev_err(dev,
-					"Error initializing PP output buffer\n");
-				return -EINVAL;
-			}
-
-		} else {
-			dev_dbg(dev, "Using ADC SYS2 channel\n");
-			vout->display_ch = ADC_SYS2;
-			vout->post_proc_ch = MEM_PP_MEM;
-
-			if (vout->display_bufs[0]) {
-				mxc_free_buffers(vout->display_bufs,
-						 vout->display_bufs_vaddr,
-						 2, vout->display_buf_size);
-			}
-
-			vout->display_buf_size = vout->crop_current.width *
-			    vout->crop_current.height *
-			    fmt_to_bpp(SDC_FG_FB_FORMAT) / 8;
-			mxc_allocate_buffers(vout->display_bufs,
-					     vout->display_bufs_vaddr,
-					     2, vout->display_buf_size);
-
-			memset(&params, 0, sizeof(params));
-			params.adc_sys2.disp = vout->cur_disp_output;
-			params.adc_sys2.ch_mode = WriteTemplateNonSeq;
-#ifdef CONFIG_FB_MXC_EPSON_PANEL
-			params.adc_sys2.out_left = 2 + vout->crop_current.left;
-#else
-			params.adc_sys2.out_left = 12 + vout->crop_current.left;
-#endif
-			params.adc_sys2.out_top = vout->crop_current.top;
-			if (ipu_init_channel(ADC_SYS2, &params) < 0)
-				return -EINVAL;
-
-			if (ipu_init_channel_buffer(vout->display_ch,
-						    IPU_INPUT_BUFFER,
-						    SDC_FG_FB_FORMAT,
-						    out_width, out_height,
-						    out_width, IPU_ROTATE_NONE,
-						    vout->display_bufs[0],
-						    vout->display_bufs[1], 0,
-						    0) != 0) {
-				dev_err(dev,
-					"Error initializing SDC FG buffer\n");
-				return -EINVAL;
-			}
-		}
-	} else
-#endif
-	{			/* Use SDC */
-		unsigned int ipu_ch = CHAN_NONE;
-
-		dev_dbg(dev, "Using SDC channel\n");
-
-		if (INTERLACED_CONTENT(vout))
-			vout->work_irq = IPU_IRQ_PRP_VF_OUT_EOF;
-		else
-			vout->work_irq = IPU_IRQ_PP_IN_EOF;
-
-		/*
-		 * Bypass IC if resizing and rotation are not needed
-		 * Meanwhile, apply IC bypass to SDC only
-		 */
-		fbvar = fbi->var;
-		vout->xres = fbvar.xres;
-		vout->yres = fbvar.yres;
-
-		if (vout->cur_disp_output == 3 || vout->cur_disp_output == 5) {
-			fbvar.bits_per_pixel = 16;
+	/*
+	 * Bypass IC if resizing and rotation are not needed
+	 * Meanwhile, apply IC bypass to SDC only
+	 */
+	fbvar = fbi->var;
+	vout->xres = fbvar.xres;
+	vout->yres = fbvar.yres;
+
+	if (vout->cur_disp_output == 3 || vout->cur_disp_output == 5) {
+		fbvar.bits_per_pixel = 16;
+		if (vout->cur_disp_output == 3) {
+			/* Only set YUV for the first display. The second display can
+			 * only work in RGB */
 			if (format_is_yuv(vout->v2f.fmt.pix.pixelformat))
 				fbvar.nonstd = IPU_PIX_FMT_UYVY;
 			else
 				fbvar.nonstd = 0;
-			if (vout->cur_disp_output == 3) {
-				fbvar.xres = out_width;
-				fbvar.yres = out_height;
-				vout->xres = fbvar.xres;
-				vout->yres = fbvar.yres;
-			}
 
-			fbvar.xres_virtual = fbvar.xres;
-			fbvar.yres_virtual = fbvar.yres * 2;
+			fbvar.xres = out_width;
+			fbvar.yres = out_height;
+			vout->xres = fbvar.xres;
+			vout->yres = fbvar.yres;
 		}
 
-		if (out_width == vout->v2f.fmt.pix.width &&
-			out_height == vout->v2f.fmt.pix.height &&
-			vout->xres == out_width &&
-			vout->yres == out_height &&
-			ipu_can_rotate_in_place(vout->rotate)) {
-			vout->ic_bypass = 1;
-		} else {
-			vout->ic_bypass = 0;
-		}
+		fbvar.xres_virtual = fbvar.xres;
+		fbvar.yres_virtual = fbvar.yres * 2;
+	}
+
+	if (out_width == vout->v2f.fmt.pix.width &&
+	    out_height == vout->v2f.fmt.pix.height &&
+	    vout->xres == out_width &&
+	    vout->yres == out_height &&
+	    ipu_can_rotate_in_place(vout->rotate) &&
+	    (vout->bytesperline ==
+	     bytes_per_pixel(vout->v2f.fmt.pix.pixelformat) * out_width) &&
+	    !INTERLACED_CONTENT(vout)) {
+		vout->ic_bypass = 1;
+	} else {
+		vout->ic_bypass = 0;
+	}
 
 #ifdef CONFIG_MXC_IPU_V1
-		/* IPUv1 needs IC to do CSC */
-		if (format_is_yuv(vout->v2f.fmt.pix.pixelformat) !=
-		    format_is_yuv(bpp_to_fmt(fbi)))
-			vout->ic_bypass = 0;
+	/* IPUv1 needs IC to do CSC */
+	if (format_is_yuv(vout->v2f.fmt.pix.pixelformat) !=
+	    format_is_yuv(bpp_to_fmt(fbi)))
+		vout->ic_bypass = 0;
 #endif
 
-		/* We are using IC to do input cropping */
-		if (vout->queue_buf_paddr[vout->ipu_buf[0]] !=
-		    vout->v4l2_bufs[vout->ipu_buf[0]].m.offset ||
-		    vout->queue_buf_paddr[vout->ipu_buf[1]] !=
-		    vout->v4l2_bufs[vout->ipu_buf[1]].m.offset)
-			vout->ic_bypass = 0;
-
-		if (fbi->fbops->fb_ioctl) {
-			old_fs = get_fs();
-			set_fs(KERNEL_DS);
-			fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_IPU_CHAN,
-					(unsigned long)&ipu_ch);
-			set_fs(old_fs);
-		}
+	if (fbi->fbops->fb_ioctl) {
+		old_fs = get_fs();
+		set_fs(KERNEL_DS);
+		fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_IPU_CHAN,
+				(unsigned long)&ipu_ch);
+		set_fs(old_fs);
+	}
 
-		if (ipu_ch == CHAN_NONE) {
-			dev_err(dev, "Can not get display ipu channel\n");
-			return -EINVAL;
-		}
+	if (ipu_ch == CHAN_NONE) {
+		dev_err(dev, "Can not get display ipu channel\n");
+		return -EINVAL;
+	}
 
-		vout->display_ch = ipu_ch;
+	vout->display_ch = ipu_ch;
 
-		if (vout->ic_bypass) {
-			pr_debug("Bypassing IC\n");
-			vout->work_irq = -1;
-			switch (vout->v2f.fmt.pix.pixelformat) {
+	if (vout->ic_bypass) {
+		pr_debug("Bypassing IC\n");
+		vout->pp_split = 0;
+		switch (vout->v2f.fmt.pix.pixelformat) {
 			case V4L2_PIX_FMT_YUV420:
 			case V4L2_PIX_FMT_YVU420:
 			case V4L2_PIX_FMT_NV12:
@@ -1353,87 +1322,80 @@ static int mxc_v4l2out_streamon(vout_data * vout)
 			default:
 				fbvar.bits_per_pixel = 8*
 					bytes_per_pixel(vout->v2f.fmt.pix.pixelformat);
-			}
-			fbvar.nonstd = vout->v2f.fmt.pix.pixelformat;
 		}
+		fbvar.nonstd = vout->v2f.fmt.pix.pixelformat;
+	}
 
-		fbvar.activate |= FB_ACTIVATE_FORCE;
-		fb_set_var(fbi, &fbvar);
+	/* Init display channel through fb API */
+	fbvar.activate |= FB_ACTIVATE_FORCE;
+	fb_set_var(fbi, &fbvar);
 
-		if (fbi->fbops->fb_ioctl && vout->display_ch == MEM_FG_SYNC) {
-			fb_pos.x = vout->crop_current.left;
-			fb_pos.y = vout->crop_current.top;
-			old_fs = get_fs();
-			set_fs(KERNEL_DS);
-			fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS,
-					     (unsigned long)&fb_pos);
-			set_fs(old_fs);
-		}
+	if (fbi->fbops->fb_ioctl && vout->display_ch == MEM_FG_SYNC) {
+		fb_pos.x = vout->crop_current.left;
+		fb_pos.y = vout->crop_current.top;
+		old_fs = get_fs();
+		set_fs(KERNEL_DS);
+		fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS,
+				(unsigned long)&fb_pos);
+		set_fs(old_fs);
+	}
 
-		vout->display_bufs[1] = fbi->fix.smem_start;
-		vout->display_bufs[0] = fbi->fix.smem_start +
-			(fbi->fix.line_length * vout->yres);
-		vout->display_buf_size = vout->xres *
-			vout->yres * fbi->var.bits_per_pixel / 8;
-
-		/* fill black color for init fb, we assume fb has double buffer*/
-		if (format_is_yuv(vout->v2f.fmt.pix.pixelformat)) {
-			int i;
-
-			if ((vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) ||
-				(vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) ||
-				(!vout->ic_bypass)) {
-				short * tmp = (short *) fbi->screen_base;
-				short color;
-				if (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
-					color = 0x8000;
-				else
-					color = 0x80;
-				for (i = 0; i < (fbi->fix.line_length * fbi->var.yres_virtual)/2;
+	vout->display_bufs[1] = fbi->fix.smem_start;
+	vout->display_bufs[0] = fbi->fix.smem_start +
+		(fbi->fix.line_length * vout->yres);
+	vout->display_buf_size = vout->xres *
+		vout->yres * fbi->var.bits_per_pixel / 8;
+
+	/* fill black color for init fb, we assume fb has double buffer*/
+	if (format_is_yuv(vout->v2f.fmt.pix.pixelformat)) {
+		int i;
+
+		if ((vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) ||
+			(vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) ||
+			(!vout->ic_bypass)) {
+			short * tmp = (short *) fbi->screen_base;
+			short color;
+			if (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
+				color = 0x8000;
+			else
+				color = 0x80;
+			for (i = 0; i < (fbi->fix.line_length * fbi->var.yres_virtual)/2;
 					i++, tmp++)
-					*tmp = color;
-			} else if ((vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) ||
+				*tmp = color;
+		} else if ((vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) ||
 				(vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YVU420) ||
 				(vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12)) {
-				char * base = (char *)fbi->screen_base;
-				int j, screen_size = fbi->var.xres * fbi->var.yres;
-
-				for (j = 0; j < 2; j++) {
-					memset(base, 0, screen_size);
-					base += screen_size;
-					for (i = 0; i < screen_size/2; i++, base++)
-						*base = 0x80;
-				}
-			} else if (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) {
-				char * base = (char *)fbi->screen_base;
-				int j, screen_size = fbi->var.xres * fbi->var.yres;
-
-				for (j = 0; j < 2; j++) {
-					memset(base, 0, screen_size);
-					base += screen_size;
-					for (i = 0; i < screen_size; i++, base++)
-						*base = 0x80;
-				}
+			char * base = (char *)fbi->screen_base;
+			int j, screen_size = fbi->var.xres * fbi->var.yres;
+
+			for (j = 0; j < 2; j++) {
+				memset(base, 0, screen_size);
+				base += screen_size;
+				for (i = 0; i < screen_size/2; i++, base++)
+					*base = 0x80;
+			}
+		} else if (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) {
+			char * base = (char *)fbi->screen_base;
+			int j, screen_size = fbi->var.xres * fbi->var.yres;
+
+			for (j = 0; j < 2; j++) {
+				memset(base, 0, screen_size);
+				base += screen_size;
+				for (i = 0; i < screen_size; i++, base++)
+					*base = 0x80;
 			}
-		} else
-			memset(fbi->screen_base, 0x0,
-					fbi->fix.line_length * fbi->var.yres_virtual);
-
-		if (INTERLACED_CONTENT(vout))
-			vout->post_proc_ch = MEM_VDI_PRP_VF_MEM;
-		else
-			vout->post_proc_ch = MEM_PP_MEM;
-
-		if (!vout->ic_bypass) {
-			ipu_clear_irq(vout->work_irq);
-			ipu_request_irq(vout->work_irq,
-					mxc_v4l2out_work_irq_handler,
-					0, vout->video_dev->name, vout);
 		}
-	}
+	} else
+		memset(fbi->screen_base, 0x0,
+				fbi->fix.line_length * fbi->var.yres_virtual);
 
-	/* Init PP */
-	if (use_direct_adc == false && !vout->ic_bypass) {
+	if (INTERLACED_CONTENT(vout))
+		vout->post_proc_ch = MEM_VDI_PRP_VF_MEM;
+	else if (!vout->ic_bypass)
+		vout->post_proc_ch = MEM_PP_MEM;
+
+	/* Init IC channel */
+	if (!vout->ic_bypass) {
 		if (vout->rotate >= IPU_ROTATE_90_RIGHT) {
 			out_width = vout->crop_current.height;
 			out_height = vout->crop_current.width;
@@ -1441,7 +1403,11 @@ static int mxc_v4l2out_streamon(vout_data * vout)
 		vout->display_input_ch = vout->post_proc_ch;
 		memset(&params, 0, sizeof(params));
 		if (INTERLACED_CONTENT(vout)) {
-			rc = init_VDI(params, vout, dev, fbi, out_width, out_height);
+			if (vout->pp_split) {
+				dev_err(&vout->video_dev->dev, "VDI split has not supported yet.\n");
+				return -1;
+			} else
+				rc = init_VDI(params, vout, dev, fbi, out_width, out_height);
 		} else {
 			rc = init_PP(&params, vout, dev, fbi, out_width, out_height);
 		}
@@ -1449,52 +1415,87 @@ static int mxc_v4l2out_streamon(vout_data * vout)
 			return rc;
 	}
 
+	if (!vout->ic_bypass) {
+		switch (vout->display_input_ch) {
+		case MEM_PP_MEM:
+			vout->work_irq = IPU_IRQ_PP_OUT_EOF;
+			break;
+		case MEM_VDI_PRP_VF_MEM:
+			vout->work_irq = IPU_IRQ_PRP_VF_OUT_EOF;
+			break;
+		case MEM_ROT_VF_MEM:
+			vout->work_irq = IPU_IRQ_PRP_VF_ROT_OUT_EOF;
+			break;
+		case MEM_ROT_PP_MEM:
+			vout->work_irq = IPU_IRQ_PP_ROT_OUT_EOF;
+			break;
+		default:
+			dev_err(&vout->video_dev->dev,
+				"not support channel, should not be here\n");
+		}
+	} else
+		vout->work_irq = -1;
+
+	if (!vout->ic_bypass && (vout->work_irq > 0)) {
+		ipu_clear_irq(vout->work_irq);
+		ipu_request_irq(vout->work_irq,
+				mxc_v4l2out_work_irq_handler,
+				0, vout->video_dev->name, vout);
+	}
+
 	vout->state = STATE_STREAM_PAUSED;
 
-	if (use_direct_adc == false) {
-		if (fbi) {
-			acquire_console_sem();
-			fb_blank(fbi, FB_BLANK_UNBLANK);
-			release_console_sem();
-		} else {
-			ipu_enable_channel(vout->display_ch);
-		}
-		if (!vout->ic_bypass) {
+	/* Enable display and IC channels */
+	if (fbi) {
+		acquire_console_sem();
+		fb_blank(fbi, FB_BLANK_UNBLANK);
+		release_console_sem();
+	} else {
+		ipu_enable_channel(vout->display_ch);
+	}
+	if (!vout->ic_bypass) {
 #ifndef CONFIG_MXC_IPU_V1
-			ipu_enable_channel(vout->post_proc_ch);
+		ipu_enable_channel(vout->post_proc_ch);
 #endif
-			if (LOAD_3FIELDS(vout)) {
-				ipu_enable_channel(MEM_VDI_PRP_VF_MEM_P);
-				ipu_enable_channel(MEM_VDI_PRP_VF_MEM_N);
-				ipu_select_multi_vdi_buffer(0);
-			} else if (INTERLACED_CONTENT(vout)) {
-				ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0);
-			} else {
-				ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0);
-				if (!vout->pp_split)
-					ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 1);
-			}
-			ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 0);
-			ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 1);
+		if (LOAD_3FIELDS(vout)) {
+			ipu_enable_channel(MEM_VDI_PRP_VF_MEM_P);
+			ipu_enable_channel(MEM_VDI_PRP_VF_MEM_N);
+			ipu_select_multi_vdi_buffer(0);
+		} else if (INTERLACED_CONTENT(vout)) {
+			ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0);
+		} else {
+			ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0);
+			if (!vout->pp_split)
+				ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 1);
+		}
+		ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 0);
+		ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 1);
 #ifdef CONFIG_MXC_IPU_V1
-			ipu_enable_channel(vout->post_proc_ch);
+		ipu_enable_channel(vout->post_proc_ch);
 #endif
-		} else {
-			ipu_update_channel_buffer(vout->display_ch,
+	} else {
+		ipu_update_channel_buffer(vout->display_ch,
 				IPU_INPUT_BUFFER,
 				0, vout->v4l2_bufs[vout->ipu_buf[0]].m.offset);
-			ipu_update_channel_buffer(vout->display_ch,
+		ipu_update_channel_buffer(vout->display_ch,
 				IPU_INPUT_BUFFER,
 				1, vout->v4l2_bufs[vout->ipu_buf[1]].m.offset);
-			ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 0);
-			ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 1);
-			queue_work(vout->v4l_wq, &vout->timer_work);
-		}
-	} else {
-		ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0);
-		ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 1);
-		ipu_enable_channel(vout->post_proc_ch);
+		if (vout->offset.u_offset || vout->offset.v_offset)
+			/* only update u/v offset */
+			ipu_update_channel_offset(vout->display_ch,
+					IPU_INPUT_BUFFER,
+					vout->v2f.fmt.pix.pixelformat,
+					vout->v2f.fmt.pix.width,
+					vout->v2f.fmt.pix.height,
+					vout->bytesperline,
+					vout->offset.u_offset,
+					vout->offset.v_offset,
+					0,
+					0);
+		ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 0);
+		queue_work(vout->v4l_wq, &vout->timer_work);
 	}
+
 	vout->start_jiffies = jiffies;
 
 	msleep(1);
@@ -1529,7 +1530,8 @@ static int mxc_v4l2out_streamoff(vout_data * vout)
 	if (!vout->ic_bypass)
 		ipu_free_irq(vout->work_irq, vout);
 
-	cancel_work_sync(&vout->timer_work);
+	if (vout->ic_bypass)
+		cancel_work_sync(&vout->timer_work);
 
 	spin_lock_irqsave(&g_lock, lockflag);
 
@@ -1556,9 +1558,21 @@ static int mxc_v4l2out_streamoff(vout_data * vout)
 		}
 	}
 
-	if (vout->post_proc_ch == MEM_PP_MEM ||
+	if (vout->ic_bypass) {
+		fbi->var.activate |= FB_ACTIVATE_FORCE;
+		fb_set_var(fbi, &fbi->var);
+
+		if (vout->display_ch == MEM_FG_SYNC) {
+			acquire_console_sem();
+			fb_blank(fbi, FB_BLANK_POWERDOWN);
+			release_console_sem();
+		}
+
+		vout->display_bufs[0] = 0;
+		vout->display_bufs[1] = 0;
+	} else if (vout->post_proc_ch == MEM_PP_MEM ||
 	    vout->post_proc_ch == MEM_PRP_VF_MEM) {
-		/* SDC or ADC with Rotation */
+		/* SDC with Rotation */
 		if (!ipu_can_rotate_in_place(vout->rotate)) {
 			ipu_unlink_channels(MEM_PP_MEM, MEM_ROT_PP_MEM);
 			ipu_disable_channel(MEM_ROT_PP_MEM, true);
@@ -1571,28 +1585,23 @@ static int mxc_v4l2out_streamoff(vout_data * vout)
 		}
 		ipu_disable_channel(MEM_PP_MEM, true);
 
-		if (vout->display_ch == ADC_SYS2 ||
-			vout->display_ch == MEM_FG_SYNC) {
-			ipu_disable_channel(vout->display_ch, true);
-			ipu_uninit_channel(vout->display_ch);
-		} else {
-			fbi->var.activate |= FB_ACTIVATE_FORCE;
-			fb_set_var(fbi, &fbi->var);
-
-			if (vout->display_ch == MEM_FG_SYNC) {
-				acquire_console_sem();
-				fb_blank(fbi, FB_BLANK_POWERDOWN);
-				release_console_sem();
-			}
+		fbi->var.activate |= FB_ACTIVATE_FORCE;
+		fb_set_var(fbi, &fbi->var);
 
-			vout->display_bufs[0] = 0;
-			vout->display_bufs[1] = 0;
+		if (vout->display_ch == MEM_FG_SYNC) {
+			acquire_console_sem();
+			fb_blank(fbi, FB_BLANK_POWERDOWN);
+			release_console_sem();
 		}
 
+		vout->display_bufs[0] = 0;
+		vout->display_bufs[1] = 0;
+
 		ipu_uninit_channel(MEM_PP_MEM);
 		if (!ipu_can_rotate_in_place(vout->rotate))
 			ipu_uninit_channel(MEM_ROT_PP_MEM);
-	} else if (INTERLACED_CONTENT(vout) && (vout->post_proc_ch == MEM_VDI_PRP_VF_MEM)) {
+	} else if (INTERLACED_CONTENT(vout) &&
+		(vout->post_proc_ch == MEM_VDI_PRP_VF_MEM)) {
 		if (!ipu_can_rotate_in_place(vout->rotate)) {
 			ipu_unlink_channels(MEM_VDI_PRP_VF_MEM,
 					    MEM_ROT_VF_MEM);
@@ -1606,32 +1615,32 @@ static int mxc_v4l2out_streamoff(vout_data * vout)
 		}
 
 		ipu_disable_channel(MEM_VDI_PRP_VF_MEM, true);
+		if (LOAD_3FIELDS(vout)) {
+			ipu_disable_channel(MEM_VDI_PRP_VF_MEM_P, true);
+			ipu_disable_channel(MEM_VDI_PRP_VF_MEM_N, true);
+		}
 
-		if (vout->display_ch == ADC_SYS2 ||
-			vout->display_ch == MEM_FG_SYNC) {
-			ipu_disable_channel(vout->display_ch, true);
-			ipu_uninit_channel(vout->display_ch);
-		} else {
-			fbi->var.activate |= FB_ACTIVATE_FORCE;
-			fb_set_var(fbi, &fbi->var);
-
-			if (vout->display_ch == MEM_FG_SYNC) {
-				acquire_console_sem();
-				fb_blank(fbi, FB_BLANK_POWERDOWN);
-				release_console_sem();
-			}
+		fbi->var.activate |= FB_ACTIVATE_FORCE;
+		fb_set_var(fbi, &fbi->var);
 
-			vout->display_bufs[0] = 0;
-			vout->display_bufs[1] = 0;
+		if (vout->display_ch == MEM_FG_SYNC) {
+			acquire_console_sem();
+			fb_blank(fbi, FB_BLANK_POWERDOWN);
+			release_console_sem();
 		}
 
+		vout->display_bufs[0] = 0;
+		vout->display_bufs[1] = 0;
+
 		ipu_uninit_channel(MEM_VDI_PRP_VF_MEM);
+		if (LOAD_3FIELDS(vout)) {
+			ipu_uninit_channel(MEM_VDI_PRP_VF_MEM_P);
+			ipu_uninit_channel(MEM_VDI_PRP_VF_MEM_N);
+		}
 		if (!ipu_can_rotate_in_place(vout->rotate))
 			ipu_uninit_channel(MEM_ROT_VF_MEM);
-	} else {		/* ADC Direct */
-		ipu_disable_channel(MEM_PP_ADC, true);
-		ipu_uninit_channel(MEM_PP_ADC);
 	}
+
 	vout->ready_q.head = vout->ready_q.tail = 0;
 	vout->done_q.head = vout->done_q.tail = 0;
 	for (i = 0; i < vout->buffer_cnt; i++) {
@@ -1640,23 +1649,9 @@ static int mxc_v4l2out_streamoff(vout_data * vout)
 		vout->v4l2_bufs[i].timestamp.tv_usec = 0;
 	}
 
+	vout->post_proc_ch = CHAN_NONE;
 	vout->state = STATE_STREAM_OFF;
 
-#ifdef CONFIG_FB_MXC_ASYNC_PANEL
-	if (vout->cur_disp_output < DISP3) {
-		if (vout->display_bufs[0] != 0) {
-			mxc_free_buffers(vout->display_bufs,
-					 vout->display_bufs_vaddr, 2,
-					 vout->display_buf_size);
-		}
-
-		mxcfb_set_refresh_mode(registered_fb
-				       [vout->
-					output_fb_num[vout->cur_disp_output]],
-				       MXCFB_REFRESH_PARTIAL, 0);
-	}
-#endif
-
 	return retval;
 }
 
@@ -1751,7 +1746,6 @@ static int mxc_v4l2out_s_fmt(vout_data * vout, struct v4l2_format *f)
 		dev_err(&vout->video_dev->dev,
 			"De-interlacing not supported in this device!\n");
 		vout->field_fmt = V4L2_FIELD_NONE;
-		break;
 	case V4L2_FIELD_INTERLACED_BT:
 		dev_err(&vout->video_dev->dev,
 			"V4L2_FIELD_INTERLACED_BT field format not supported yet!\n");
@@ -2284,12 +2278,8 @@ mxc_v4l2out_do_ioctl(struct file *file,
 				break;
 			}
 
-			if (output->index < 3) {
-				*output = mxc_outputs[MXC_V4L2_OUT_2_ADC];
-				output->name[4] = '0' + output->index;
-			} else {
+			if (output->index >= 3)
 				*output = mxc_outputs[MXC_V4L2_OUT_2_SDC];
-			}
 			break;
 		}
 	case VIDIOC_G_OUTPUT:
diff --git a/drivers/media/video/mxc/output/mxc_v4l2_output.h b/drivers/media/video/mxc/output/mxc_v4l2_output.h
index 0dd8eb0076a9..096dc3b17a06 100644
--- a/drivers/media/video/mxc/output/mxc_v4l2_output.h
+++ b/drivers/media/video/mxc/output/mxc_v4l2_output.h
@@ -39,7 +39,6 @@
 
 #define MXC_V4L2_OUT_NUM_OUTPUTS        6
 #define MXC_V4L2_OUT_2_SDC              0
-#define MXC_V4L2_OUT_2_ADC              1
 
 
 typedef struct {
@@ -141,8 +140,10 @@ typedef struct _vout_data {
 	int pp_split; /* 0,1 */
 	struct stripe_param pp_left_stripe;
 	struct stripe_param pp_right_stripe; /* struct for split parameters */
-	/* IC ouput buffer number. Counting from 0 to 3 */
-	int pp_split_buf_num; /*  0..3 */
+	struct stripe_param pp_up_stripe;
+	struct stripe_param pp_down_stripe;
+	/* IC ouput buffer number. Counting from 0 to 7 */
+	int pp_split_buf_num; /*  0..7 */
 	u16 bpp ; /* bit per pixel */
 	u16 xres; /* width of physical frame (BGs) */
 	u16 yres; /* heigth of physical frame (BGs)*/
diff --git a/drivers/media/video/mxs_pxp.c b/drivers/media/video/mxs_pxp.c
index 83c9c52c3b0c..017d22458a22 100644
--- a/drivers/media/video/mxs_pxp.c
+++ b/drivers/media/video/mxs_pxp.c
@@ -31,6 +31,7 @@
 #include <linux/platform_device.h>
 #include <linux/vmalloc.h>
 #include <linux/videodev2.h>
+#include <linux/delay.h>
 
 #include <media/videobuf-dma-contig.h>
 #include <media/v4l2-common.h>
@@ -671,6 +672,7 @@ static int pxp_streamon(struct file *file, void *priv, enum v4l2_buf_type t)
 
 	pxp_set_outbuf(pxp);
 	ret = videobuf_streamon(&pxp->s0_vbq);
+	msleep(20);
 
 	if (!ret && (pxp->output == 0))
 		mxsfb_cfg_pxp(1, pxp->outb_phys);
@@ -686,7 +688,9 @@ static int pxp_streamoff(struct file *file, void *priv, enum v4l2_buf_type t)
 	if ((t != V4L2_BUF_TYPE_VIDEO_OUTPUT))
 		return -EINVAL;
 
+	cancel_work_sync(&pxp->work);
 	ret = videobuf_streamoff(&pxp->s0_vbq);
+	msleep(20);
 
 	if (!ret)
 		mxsfb_cfg_pxp(0, 0);
@@ -1101,8 +1105,10 @@ static int pxp_close(struct file *file)
 {
 	struct pxps *pxp = video_get_drvdata(video_devdata(file));
 
-	if (pxp->workqueue)
+	if (pxp->workqueue) {
+		flush_workqueue(pxp->workqueue);
 		destroy_workqueue(pxp->workqueue);
+	}
 
 	videobuf_stop(&pxp->s0_vbq);
 	videobuf_mmap_free(&pxp->s0_vbq);
diff --git a/drivers/media/video/ov511.c b/drivers/media/video/ov511.c
index 0bc2cf573c76..2bed9e22968b 100644
--- a/drivers/media/video/ov511.c
+++ b/drivers/media/video/ov511.c
@@ -5878,7 +5878,7 @@ ov51x_probe(struct usb_interface *intf, const struct usb_device_id *id)
 		goto error;
 	}
 
-	mutex_lock(&ov->lock);
+	mutex_unlock(&ov->lock);
 
 	return 0;
 
diff --git a/drivers/media/video/pwc/pwc-ctrl.c b/drivers/media/video/pwc/pwc-ctrl.c
index 50b415e07eda..f7f7e04cf485 100644
--- a/drivers/media/video/pwc/pwc-ctrl.c
+++ b/drivers/media/video/pwc/pwc-ctrl.c
@@ -753,7 +753,7 @@ int pwc_set_shutter_speed(struct pwc_device *pdev, int mode, int value)
 		buf[0] = 0xff; /* fixed */
 
 	ret = send_control_msg(pdev,
-		SET_LUM_CTL, SHUTTER_MODE_FORMATTER, &buf, sizeof(buf));
+		SET_LUM_CTL, SHUTTER_MODE_FORMATTER, &buf, 1);
 
 	if (!mode && ret >= 0) {
 		if (value < 0)
diff --git a/drivers/media/video/s2255drv.c b/drivers/media/video/s2255drv.c
index 9e3262c0ba37..2c0bb06cab3b 100644
--- a/drivers/media/video/s2255drv.c
+++ b/drivers/media/video/s2255drv.c
@@ -598,11 +598,6 @@ static int s2255_got_frame(struct s2255_dev *dev, int chn, int jpgsize)
 	buf = list_entry(dma_q->active.next,
 			 struct s2255_buffer, vb.queue);
 
-	if (!waitqueue_active(&buf->vb.done)) {
-		/* no one active */
-		rc = -1;
-		goto unlock;
-	}
 	list_del(&buf->vb.queue);
 	do_gettimeofday(&buf->vb.ts);
 	dprintk(100, "[%p/%d] wakeup\n", buf, buf->vb.i);
diff --git a/drivers/media/video/saa7134/saa7134-cards.c b/drivers/media/video/saa7134/saa7134-cards.c
index 6eebe3ef97d3..52a79b3f8a4a 100644
--- a/drivers/media/video/saa7134/saa7134-cards.c
+++ b/drivers/media/video/saa7134/saa7134-cards.c
@@ -3373,6 +3373,7 @@ struct saa7134_board saa7134_boards[] = {
 		.tuner_config   = 3,
 		.mpeg           = SAA7134_MPEG_DVB,
 		.ts_type	= SAA7134_MPEG_TS_SERIAL,
+		.ts_force_val   = 1,
 		.gpiomask       = 0x0800100, /* GPIO 21 is an INPUT */
 		.inputs         = {{
 			.name = name_tv,
diff --git a/drivers/media/video/saa7134/saa7134-input.c b/drivers/media/video/saa7134/saa7134-input.c
index 6e219c2db841..69e48ceee27f 100644
--- a/drivers/media/video/saa7134/saa7134-input.c
+++ b/drivers/media/video/saa7134/saa7134-input.c
@@ -684,8 +684,6 @@ void saa7134_input_fini(struct saa7134_dev *dev)
 
 void saa7134_probe_i2c_ir(struct saa7134_dev *dev)
 {
-	struct i2c_board_info info;
-	struct IR_i2c_init_data init_data;
 	const unsigned short addr_list[] = {
 		0x7a, 0x47, 0x71, 0x2d,
 		I2C_CLIENT_END
@@ -705,32 +703,32 @@ void saa7134_probe_i2c_ir(struct saa7134_dev *dev)
 		return;
 	}
 
-	memset(&info, 0, sizeof(struct i2c_board_info));
-	memset(&init_data, 0, sizeof(struct IR_i2c_init_data));
-	strlcpy(info.type, "ir_video", I2C_NAME_SIZE);
+	memset(&dev->info, 0, sizeof(dev->info));
+	memset(&dev->init_data, 0, sizeof(dev->init_data));
+	strlcpy(dev->info.type, "ir_video", I2C_NAME_SIZE);
 
 	switch (dev->board) {
 	case SAA7134_BOARD_PINNACLE_PCTV_110i:
 	case SAA7134_BOARD_PINNACLE_PCTV_310i:
-		init_data.name = "Pinnacle PCTV";
+		dev->init_data.name = "Pinnacle PCTV";
 		if (pinnacle_remote == 0) {
-			init_data.get_key = get_key_pinnacle_color;
-			init_data.ir_codes = ir_codes_pinnacle_color;
+			dev->init_data.get_key = get_key_pinnacle_color;
+			dev->init_data.ir_codes = ir_codes_pinnacle_color;
 		} else {
-			init_data.get_key = get_key_pinnacle_grey;
-			init_data.ir_codes = ir_codes_pinnacle_grey;
+			dev->init_data.get_key = get_key_pinnacle_grey;
+			dev->init_data.ir_codes = ir_codes_pinnacle_grey;
 		}
 		break;
 	case SAA7134_BOARD_UPMOST_PURPLE_TV:
-		init_data.name = "Purple TV";
-		init_data.get_key = get_key_purpletv;
-		init_data.ir_codes = ir_codes_purpletv;
+		dev->init_data.name = "Purple TV";
+		dev->init_data.get_key = get_key_purpletv;
+		dev->init_data.ir_codes = ir_codes_purpletv;
 		break;
 	case SAA7134_BOARD_MSI_TVATANYWHERE_PLUS:
-		init_data.name = "MSI TV@nywhere Plus";
-		init_data.get_key = get_key_msi_tvanywhere_plus;
-		init_data.ir_codes = ir_codes_msi_tvanywhere_plus;
-		info.addr = 0x30;
+		dev->init_data.name = "MSI TV@nywhere Plus";
+		dev->init_data.get_key = get_key_msi_tvanywhere_plus;
+		dev->init_data.ir_codes = ir_codes_msi_tvanywhere_plus;
+		dev->info.addr = 0x30;
 		/* MSI TV@nywhere Plus controller doesn't seem to
 		   respond to probes unless we read something from
 		   an existing device. Weird...
@@ -741,9 +739,9 @@ void saa7134_probe_i2c_ir(struct saa7134_dev *dev)
 			(1 == rc) ? "yes" : "no");
 		break;
 	case SAA7134_BOARD_HAUPPAUGE_HVR1110:
-		init_data.name = "HVR 1110";
-		init_data.get_key = get_key_hvr1110;
-		init_data.ir_codes = ir_codes_hauppauge_new;
+		dev->init_data.name = "HVR 1110";
+		dev->init_data.get_key = get_key_hvr1110;
+		dev->init_data.ir_codes = ir_codes_hauppauge_new;
 		break;
 	case SAA7134_BOARD_BEHOLD_607FM_MK3:
 	case SAA7134_BOARD_BEHOLD_607FM_MK5:
@@ -757,26 +755,26 @@ void saa7134_probe_i2c_ir(struct saa7134_dev *dev)
 	case SAA7134_BOARD_BEHOLD_M63:
 	case SAA7134_BOARD_BEHOLD_M6_EXTRA:
 	case SAA7134_BOARD_BEHOLD_H6:
-		init_data.name = "BeholdTV";
-		init_data.get_key = get_key_beholdm6xx;
-		init_data.ir_codes = ir_codes_behold;
+		dev->init_data.name = "BeholdTV";
+		dev->init_data.get_key = get_key_beholdm6xx;
+		dev->init_data.ir_codes = ir_codes_behold;
 		break;
 	case SAA7134_BOARD_AVERMEDIA_CARDBUS_501:
 	case SAA7134_BOARD_AVERMEDIA_CARDBUS_506:
-		info.addr = 0x40;
+		dev->info.addr = 0x40;
 		break;
 	}
 
-	if (init_data.name)
-		info.platform_data = &init_data;
+	if (dev->init_data.name)
+		dev->info.platform_data = &dev->init_data;
 	/* No need to probe if address is known */
-	if (info.addr) {
-		i2c_new_device(&dev->i2c_adap, &info);
+	if (dev->info.addr) {
+		i2c_new_device(&dev->i2c_adap, &dev->info);
 		return;
 	}
 
 	/* Address not known, fallback to probing */
-	i2c_new_probed_device(&dev->i2c_adap, &info, addr_list);
+	i2c_new_probed_device(&dev->i2c_adap, &dev->info, addr_list);
 }
 
 static int saa7134_rc5_irq(struct saa7134_dev *dev)
diff --git a/drivers/media/video/saa7134/saa7134-ts.c b/drivers/media/video/saa7134/saa7134-ts.c
index 3fa652279ac0..03488ba4c99c 100644
--- a/drivers/media/video/saa7134/saa7134-ts.c
+++ b/drivers/media/video/saa7134/saa7134-ts.c
@@ -262,11 +262,13 @@ int saa7134_ts_start(struct saa7134_dev *dev)
 	switch (saa7134_boards[dev->board].ts_type) {
 	case SAA7134_MPEG_TS_PARALLEL:
 		saa_writeb(SAA7134_TS_SERIAL0, 0x40);
-		saa_writeb(SAA7134_TS_PARALLEL, 0xec);
+		saa_writeb(SAA7134_TS_PARALLEL, 0xec |
+			(saa7134_boards[dev->board].ts_force_val << 4));
 		break;
 	case SAA7134_MPEG_TS_SERIAL:
 		saa_writeb(SAA7134_TS_SERIAL0, 0xd8);
-		saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
+		saa_writeb(SAA7134_TS_PARALLEL, 0x6c |
+			(saa7134_boards[dev->board].ts_force_val << 4));
 		saa_writeb(SAA7134_TS_PARALLEL_SERIAL, 0xbc);
 		saa_writeb(SAA7134_TS_SERIAL1, 0x02);
 		break;
diff --git a/drivers/media/video/saa7134/saa7134.h b/drivers/media/video/saa7134/saa7134.h
index fb564f14887c..f50734f39466 100644
--- a/drivers/media/video/saa7134/saa7134.h
+++ b/drivers/media/video/saa7134/saa7134.h
@@ -355,6 +355,7 @@ struct saa7134_board {
 	enum saa7134_mpeg_type  mpeg;
 	enum saa7134_mpeg_ts_type ts_type;
 	unsigned int            vid_port_opts;
+	unsigned int            ts_force_val:1;
 };
 
 #define card_has_radio(dev)   (NULL != saa7134_boards[dev->board].radio.name)
@@ -584,6 +585,10 @@ struct saa7134_dev {
 	int                        nosignal;
 	unsigned int               insuspend;
 
+	/* I2C keyboard data */
+	struct i2c_board_info      info;
+	struct IR_i2c_init_data    init_data;
+
 	/* SAA7134_MPEG_* */
 	struct saa7134_ts          ts;
 	struct saa7134_dmaqueue    ts_q;
diff --git a/drivers/media/video/sn9c102/sn9c102_devtable.h b/drivers/media/video/sn9c102/sn9c102_devtable.h
index 38a716020d7f..36ee43a9ee95 100644
--- a/drivers/media/video/sn9c102/sn9c102_devtable.h
+++ b/drivers/media/video/sn9c102/sn9c102_devtable.h
@@ -123,8 +123,8 @@ static const struct usb_device_id sn9c102_id_table[] = {
 	{ SN9C102_USB_DEVICE(0x0c45, 0x613b, BRIDGE_SN9C120), },
 #if !defined CONFIG_USB_GSPCA && !defined CONFIG_USB_GSPCA_MODULE
 	{ SN9C102_USB_DEVICE(0x0c45, 0x613c, BRIDGE_SN9C120), },
-#endif
 	{ SN9C102_USB_DEVICE(0x0c45, 0x613e, BRIDGE_SN9C120), },
+#endif
 	{ }
 };
 
diff --git a/drivers/media/video/uvc/uvc_driver.c b/drivers/media/video/uvc/uvc_driver.c
index 04b47832fa0a..5a8a8d1cc9c0 100644
--- a/drivers/media/video/uvc/uvc_driver.c
+++ b/drivers/media/video/uvc/uvc_driver.c
@@ -46,6 +46,7 @@
 unsigned int uvc_no_drop_param;
 static unsigned int uvc_quirks_param;
 unsigned int uvc_trace_param;
+unsigned int uvc_timeout_param = UVC_CTRL_STREAMING_TIMEOUT;
 
 /* ------------------------------------------------------------------------
  * Video formats
@@ -2034,6 +2035,8 @@ module_param_named(quirks, uvc_quirks_param, uint, S_IRUGO|S_IWUSR);
 MODULE_PARM_DESC(quirks, "Forced device quirks");
 module_param_named(trace, uvc_trace_param, uint, S_IRUGO|S_IWUSR);
 MODULE_PARM_DESC(trace, "Trace level bitmask");
+module_param_named(timeout, uvc_timeout_param, uint, S_IRUGO|S_IWUSR);
+MODULE_PARM_DESC(timeout, "Streaming control requests timeout");
 
 MODULE_AUTHOR(DRIVER_AUTHOR);
 MODULE_DESCRIPTION(DRIVER_DESC);
diff --git a/drivers/media/video/uvc/uvc_video.c b/drivers/media/video/uvc/uvc_video.c
index 01b633c73480..f2480c35c265 100644
--- a/drivers/media/video/uvc/uvc_video.c
+++ b/drivers/media/video/uvc/uvc_video.c
@@ -130,7 +130,7 @@ static int uvc_get_video_ctrl(struct uvc_video_device *video,
 
 	ret = __uvc_query_ctrl(video->dev, query, 0, video->streaming->intfnum,
 		probe ? VS_PROBE_CONTROL : VS_COMMIT_CONTROL, data, size,
-		UVC_CTRL_STREAMING_TIMEOUT);
+		uvc_timeout_param);
 
 	if ((query == GET_MIN || query == GET_MAX) && ret == 2) {
 		/* Some cameras, mostly based on Bison Electronics chipsets,
@@ -235,7 +235,7 @@ static int uvc_set_video_ctrl(struct uvc_video_device *video,
 	ret = __uvc_query_ctrl(video->dev, SET_CUR, 0,
 		video->streaming->intfnum,
 		probe ? VS_PROBE_CONTROL : VS_COMMIT_CONTROL, data, size,
-		UVC_CTRL_STREAMING_TIMEOUT);
+		uvc_timeout_param);
 	if (ret != size) {
 		uvc_printk(KERN_ERR, "Failed to set UVC %s control : "
 			"%d (exp. %u).\n", probe ? "probe" : "commit",
diff --git a/drivers/media/video/uvc/uvcvideo.h b/drivers/media/video/uvc/uvcvideo.h
index 3c78d3c1e4c0..3265fbf3fc96 100644
--- a/drivers/media/video/uvc/uvcvideo.h
+++ b/drivers/media/video/uvc/uvcvideo.h
@@ -304,7 +304,7 @@ struct uvc_xu_control {
 #define UVC_MAX_STATUS_SIZE	16
 
 #define UVC_CTRL_CONTROL_TIMEOUT	300
-#define UVC_CTRL_STREAMING_TIMEOUT	1000
+#define UVC_CTRL_STREAMING_TIMEOUT	3000
 
 /* Devices quirks */
 #define UVC_QUIRK_STATUS_INTERVAL	0x00000001
@@ -695,6 +695,7 @@ struct uvc_driver {
 
 extern unsigned int uvc_no_drop_param;
 extern unsigned int uvc_trace_param;
+extern unsigned int uvc_timeout_param;
 
 #define uvc_trace(flag, msg...) \
 	do { \
diff --git a/drivers/media/video/v4l1-compat.c b/drivers/media/video/v4l1-compat.c
index 02f2a6d18b45..ec766937aff6 100644
--- a/drivers/media/video/v4l1-compat.c
+++ b/drivers/media/video/v4l1-compat.c
@@ -565,10 +565,9 @@ static noinline long v4l1_compat_get_input_info(
 		break;
 	}
 	chan->norm = 0;
-	err = drv(file, VIDIOC_G_STD, &sid);
-	if (err < 0)
-		dprintk("VIDIOCGCHAN / VIDIOC_G_STD: %ld\n", err);
-	if (err == 0) {
+	/* Note: G_STD might not be present for radio receivers,
+	 * so we should ignore any errors. */
+	if (drv(file, VIDIOC_G_STD, &sid) == 0) {
 		if (sid & V4L2_STD_PAL)
 			chan->norm = VIDEO_MODE_PAL;
 		if (sid & V4L2_STD_NTSC)
@@ -777,10 +776,9 @@ static noinline long v4l1_compat_get_tuner(
 			tun->flags |= VIDEO_TUNER_SECAM;
 	}
 
-	err = drv(file, VIDIOC_G_STD, &sid);
-	if (err < 0)
-		dprintk("VIDIOCGTUNER / VIDIOC_G_STD: %ld\n", err);
-	if (err == 0) {
+	/* Note: G_STD might not be present for radio receivers,
+	 * so we should ignore any errors. */
+	if (drv(file, VIDIOC_G_STD, &sid) == 0) {
 		if (sid & V4L2_STD_PAL)
 			tun->mode = VIDEO_MODE_PAL;
 		if (sid & V4L2_STD_NTSC)
diff --git a/drivers/message/fusion/mptbase.c b/drivers/message/fusion/mptbase.c
index 5d0ba4f5924c..9ad7bb4e721f 100644
--- a/drivers/message/fusion/mptbase.c
+++ b/drivers/message/fusion/mptbase.c
@@ -1015,9 +1015,9 @@ mpt_add_sge_64bit(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
 {
 	SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
 	pSge->Address.Low = cpu_to_le32
-			(lower_32_bits((unsigned long)(dma_addr)));
+			(lower_32_bits(dma_addr));
 	pSge->Address.High = cpu_to_le32
-			(upper_32_bits((unsigned long)dma_addr));
+			(upper_32_bits(dma_addr));
 	pSge->FlagsLength = cpu_to_le32
 			((flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
 }
@@ -1038,8 +1038,8 @@ mpt_add_sge_64bit_1078(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
 	u32 tmp;
 
 	pSge->Address.Low = cpu_to_le32
-			(lower_32_bits((unsigned long)(dma_addr)));
-	tmp = (u32)(upper_32_bits((unsigned long)dma_addr));
+			(lower_32_bits(dma_addr));
+	tmp = (u32)(upper_32_bits(dma_addr));
 
 	/*
 	 * 1078 errata workaround for the 36GB limitation
@@ -1101,7 +1101,7 @@ mpt_add_chain_64bit(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
 		pChain->NextChainOffset = next;
 
 		pChain->Address.Low = cpu_to_le32(tmp);
-		tmp = (u32)(upper_32_bits((unsigned long)dma_addr));
+		tmp = (u32)(upper_32_bits(dma_addr));
 		pChain->Address.High = cpu_to_le32(tmp);
 }
 
diff --git a/drivers/mfd/ab3100-core.c b/drivers/mfd/ab3100-core.c
index 13e7d7bfe85f..dd8b6b3ff1ea 100644
--- a/drivers/mfd/ab3100-core.c
+++ b/drivers/mfd/ab3100-core.c
@@ -643,7 +643,7 @@ struct ab3100_init_setting {
 	u8 setting;
 };
 
-static const struct ab3100_init_setting __initdata
+static const struct ab3100_init_setting __initconst
 ab3100_init_settings[] = {
 	{
 		.abreg = AB3100_MCA,
diff --git a/drivers/misc/enclosure.c b/drivers/misc/enclosure.c
index 348443bdb23b..8393376b1080 100644
--- a/drivers/misc/enclosure.c
+++ b/drivers/misc/enclosure.c
@@ -362,6 +362,7 @@ static const char *const enclosure_status [] = {
 	[ENCLOSURE_STATUS_NOT_INSTALLED] = "not installed",
 	[ENCLOSURE_STATUS_UNKNOWN] = "unknown",
 	[ENCLOSURE_STATUS_UNAVAILABLE] = "unavailable",
+	[ENCLOSURE_STATUS_MAX] = NULL,
 };
 
 static const char *const enclosure_type [] = {
diff --git a/drivers/misc/sgi-gru/gruprocfs.c b/drivers/misc/sgi-gru/gruprocfs.c
index 9cbf95bedce6..de530d9942d2 100644
--- a/drivers/misc/sgi-gru/gruprocfs.c
+++ b/drivers/misc/sgi-gru/gruprocfs.c
@@ -161,14 +161,15 @@ static int options_show(struct seq_file *s, void *p)
 static ssize_t options_write(struct file *file, const char __user *userbuf,
 			     size_t count, loff_t *data)
 {
-	unsigned long val;
-	char buf[80];
+	char buf[20];
 
-	if (strncpy_from_user(buf, userbuf, sizeof(buf) - 1) < 0)
+	if (count >= sizeof(buf))
+		return -EINVAL;
+	if (copy_from_user(buf, userbuf, count))
 		return -EFAULT;
-	buf[count - 1] = '\0';
-	if (!strict_strtoul(buf, 10, &val))
-		gru_options = val;
+	buf[count] = '\0';
+	if (strict_strtoul(buf, 0, &gru_options))
+		return -EINVAL;
 
 	return count;
 }
diff --git a/drivers/mmc/core/Kconfig b/drivers/mmc/core/Kconfig
index ab37a6d9d32a..bb22ffd76ef8 100644
--- a/drivers/mmc/core/Kconfig
+++ b/drivers/mmc/core/Kconfig
@@ -3,7 +3,7 @@
 #
 
 config MMC_UNSAFE_RESUME
-	bool "Allow unsafe resume (DANGEROUS)"
+	bool "Assume MMC/SD cards are non-removable (DANGEROUS)"
 	help
 	  If you say Y here, the MMC layer will assume that all cards
 	  stayed in their respective slots during the suspend. The
@@ -14,3 +14,5 @@ config MMC_UNSAFE_RESUME
 	  This option is usually just for embedded systems which use
 	  a MMC/SD card for rootfs. Most people should say N here.
 
+	  This option sets a default which can be overridden by the
+	  module parameter "removable=0" or "removable=1".
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 50b208253440..91ba2f812d73 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -48,6 +48,22 @@ int use_spi_crc = 1;
 module_param(use_spi_crc, bool, 0);
 
 /*
+ * We normally treat cards as removed during suspend if they are not
+ * known to be on a non-removable bus, to avoid the risk of writing
+ * back data to a different card after resume.  Allow this to be
+ * overridden if necessary.
+ */
+#ifdef CONFIG_MMC_UNSAFE_RESUME
+int mmc_assume_removable;
+#else
+int mmc_assume_removable = 1;
+#endif
+module_param_named(removable, mmc_assume_removable, bool, 0644);
+MODULE_PARM_DESC(
+	removable,
+	"MMC/SD cards are removable and may be removed during suspend");
+
+/*
  * Internal function. Schedule delayed work in the MMC work queue.
  */
 static int mmc_schedule_delayed_work(struct delayed_work *work,
@@ -344,6 +360,101 @@ unsigned int mmc_align_data_size(struct mmc_card *card, unsigned int sz)
 EXPORT_SYMBOL(mmc_align_data_size);
 
 /**
+ *	mmc_host_enable - enable a host.
+ *	@host: mmc host to enable
+ *
+ *	Hosts that support power saving can use the 'enable' and 'disable'
+ *	methods to exit and enter power saving states. For more information
+ *	see comments for struct mmc_host_ops.
+ */
+int mmc_host_enable(struct mmc_host *host)
+{
+	if (!(host->caps & MMC_CAP_DISABLE))
+		return 0;
+
+	if (host->en_dis_recurs)
+		return 0;
+
+	if (host->nesting_cnt++)
+		return 0;
+
+	cancel_delayed_work_sync(&host->disable);
+
+	if (host->enabled)
+		return 0;
+
+	if (host->ops->enable) {
+		int err;
+
+		host->en_dis_recurs = 1;
+		err = host->ops->enable(host);
+		host->en_dis_recurs = 0;
+
+		if (err) {
+			pr_debug("%s: enable error %d\n",
+				 mmc_hostname(host), err);
+			return err;
+		}
+	}
+	host->enabled = 1;
+	return 0;
+}
+EXPORT_SYMBOL(mmc_host_enable);
+
+static int mmc_host_do_disable(struct mmc_host *host, int lazy)
+{
+	if (host->ops->disable) {
+		int err;
+
+		host->en_dis_recurs = 1;
+		err = host->ops->disable(host, lazy);
+		host->en_dis_recurs = 0;
+
+		if (err < 0) {
+			pr_debug("%s: disable error %d\n",
+				 mmc_hostname(host), err);
+			return err;
+		}
+		if (err > 0) {
+			unsigned long delay = msecs_to_jiffies(err);
+
+			mmc_schedule_delayed_work(&host->disable, delay);
+		}
+	}
+	host->enabled = 0;
+	return 0;
+}
+
+/**
+ *	mmc_host_disable - disable a host.
+ *	@host: mmc host to disable
+ *
+ *	Hosts that support power saving can use the 'enable' and 'disable'
+ *	methods to exit and enter power saving states. For more information
+ *	see comments for struct mmc_host_ops.
+ */
+int mmc_host_disable(struct mmc_host *host)
+{
+	int err;
+
+	if (!(host->caps & MMC_CAP_DISABLE))
+		return 0;
+
+	if (host->en_dis_recurs)
+		return 0;
+
+	if (--host->nesting_cnt)
+		return 0;
+
+	if (!host->enabled)
+		return 0;
+
+	err = mmc_host_do_disable(host, 0);
+	return err;
+}
+EXPORT_SYMBOL(mmc_host_disable);
+
+/**
  *	__mmc_claim_host - exclusively claim a host
  *	@host: mmc host to claim
  *	@abort: whether or not the operation should be aborted
@@ -366,25 +477,111 @@ int __mmc_claim_host(struct mmc_host *host, atomic_t *abort)
 	while (1) {
 		set_current_state(TASK_UNINTERRUPTIBLE);
 		stop = abort ? atomic_read(abort) : 0;
-		if (stop || !host->claimed)
+		if (stop || !host->claimed || host->claimer == current)
 			break;
 		spin_unlock_irqrestore(&host->lock, flags);
 		schedule();
 		spin_lock_irqsave(&host->lock, flags);
 	}
 	set_current_state(TASK_RUNNING);
-	if (!stop)
+	if (!stop) {
 		host->claimed = 1;
-	else
+		host->claimer = current;
+		host->claim_cnt += 1;
+	} else
 		wake_up(&host->wq);
 	spin_unlock_irqrestore(&host->lock, flags);
 	remove_wait_queue(&host->wq, &wait);
+	if (!stop)
+		mmc_host_enable(host);
 	return stop;
 }
 
 EXPORT_SYMBOL(__mmc_claim_host);
 
 /**
+ *	mmc_try_claim_host - try exclusively to claim a host
+ *	@host: mmc host to claim
+ *
+ *	Returns %1 if the host is claimed, %0 otherwise.
+ */
+int mmc_try_claim_host(struct mmc_host *host)
+{
+	int claimed_host = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&host->lock, flags);
+	if (!host->claimed || host->claimer == current) {
+		host->claimed = 1;
+		host->claimer = current;
+		host->claim_cnt += 1;
+		claimed_host = 1;
+	}
+	spin_unlock_irqrestore(&host->lock, flags);
+	return claimed_host;
+}
+EXPORT_SYMBOL(mmc_try_claim_host);
+
+static void mmc_do_release_host(struct mmc_host *host)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&host->lock, flags);
+	if (--host->claim_cnt) {
+		/* Release for nested claim */
+		spin_unlock_irqrestore(&host->lock, flags);
+	} else {
+		host->claimed = 0;
+		host->claimer = NULL;
+		spin_unlock_irqrestore(&host->lock, flags);
+		wake_up(&host->wq);
+	}
+}
+
+void mmc_host_deeper_disable(struct work_struct *work)
+{
+	struct mmc_host *host =
+		container_of(work, struct mmc_host, disable.work);
+
+	/* If the host is claimed then we do not want to disable it anymore */
+	if (!mmc_try_claim_host(host))
+		return;
+	mmc_host_do_disable(host, 1);
+	mmc_do_release_host(host);
+}
+
+/**
+ *	mmc_host_lazy_disable - lazily disable a host.
+ *	@host: mmc host to disable
+ *
+ *	Hosts that support power saving can use the 'enable' and 'disable'
+ *	methods to exit and enter power saving states. For more information
+ *	see comments for struct mmc_host_ops.
+ */
+int mmc_host_lazy_disable(struct mmc_host *host)
+{
+	if (!(host->caps & MMC_CAP_DISABLE))
+		return 0;
+
+	if (host->en_dis_recurs)
+		return 0;
+
+	if (--host->nesting_cnt)
+		return 0;
+
+	if (!host->enabled)
+		return 0;
+
+	if (host->disable_delay) {
+		mmc_schedule_delayed_work(&host->disable,
+				msecs_to_jiffies(host->disable_delay));
+		return 0;
+	} else
+		return mmc_host_do_disable(host, 1);
+}
+EXPORT_SYMBOL(mmc_host_lazy_disable);
+
+/**
  *	mmc_release_host - release a host
  *	@host: mmc host to release
  *
@@ -393,15 +590,11 @@ EXPORT_SYMBOL(__mmc_claim_host);
  */
 void mmc_release_host(struct mmc_host *host)
 {
-	unsigned long flags;
-
 	WARN_ON(!host->claimed);
 
-	spin_lock_irqsave(&host->lock, flags);
-	host->claimed = 0;
-	spin_unlock_irqrestore(&host->lock, flags);
+	mmc_host_lazy_disable(host);
 
-	wake_up(&host->wq);
+	mmc_do_release_host(host);
 }
 
 EXPORT_SYMBOL(mmc_release_host);
@@ -687,7 +880,13 @@ void mmc_set_timing(struct mmc_host *host, unsigned int timing)
  */
 static void mmc_power_up(struct mmc_host *host)
 {
-	int bit = fls(host->ocr_avail) - 1;
+	int bit;
+
+	/* If ocr is set, we use it */
+	if (host->ocr)
+		bit = ffs(host->ocr) - 1;
+	else
+		bit = fls(host->ocr_avail) - 1;
 
 	host->ios.vdd = bit;
 	if (mmc_host_is_spi(host)) {
@@ -858,6 +1057,17 @@ void mmc_rescan(struct work_struct *work)
 		container_of(work, struct mmc_host, detect.work);
 	u32 ocr;
 	int err;
+	unsigned long flags;
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	if (host->rescan_disable) {
+		spin_unlock_irqrestore(&host->lock, flags);
+		return;
+	}
+
+	spin_unlock_irqrestore(&host->lock, flags);
+
 
 	mmc_bus_get(host);
 
@@ -890,8 +1100,7 @@ void mmc_rescan(struct work_struct *work)
 	mmc_claim_host(host);
 
 	mmc_power_up(host);
-	sdio_go_idle(host);
-
+	sdio_reset(host);
 	mmc_go_idle(host);
 
 	mmc_send_if_cond(host, host->ocr_avail);
@@ -949,9 +1158,14 @@ void mmc_stop_host(struct mmc_host *host)
 	spin_unlock_irqrestore(&host->lock, flags);
 #endif
 
+	if (host->caps & MMC_CAP_DISABLE)
+		cancel_delayed_work(&host->disable);
 	cancel_delayed_work(&host->detect);
 	mmc_flush_scheduled_work();
 
+	/* clear pm flags now and let card drivers set them as needed */
+	host->pm_flags = 0;
+
 	mmc_bus_get(host);
 	if (host->bus_ops && !host->bus_dead) {
 		if (host->bus_ops->remove)
@@ -960,6 +1174,8 @@ void mmc_stop_host(struct mmc_host *host)
 		mmc_claim_host(host);
 		mmc_detach_bus(host);
 		mmc_release_host(host);
+		mmc_bus_put(host);
+		return;
 	}
 	mmc_bus_put(host);
 
@@ -968,6 +1184,80 @@ void mmc_stop_host(struct mmc_host *host)
 	mmc_power_off(host);
 }
 
+void mmc_power_save_host(struct mmc_host *host)
+{
+	mmc_bus_get(host);
+
+	if (!host->bus_ops || host->bus_dead || !host->bus_ops->power_restore) {
+		mmc_bus_put(host);
+		return;
+	}
+
+	if (host->bus_ops->power_save)
+		host->bus_ops->power_save(host);
+
+	mmc_bus_put(host);
+
+	mmc_power_off(host);
+}
+EXPORT_SYMBOL(mmc_power_save_host);
+
+void mmc_power_restore_host(struct mmc_host *host)
+{
+	mmc_bus_get(host);
+
+	if (!host->bus_ops || host->bus_dead || !host->bus_ops->power_restore) {
+		mmc_bus_put(host);
+		return;
+	}
+
+	mmc_power_up(host);
+	host->bus_ops->power_restore(host);
+
+	mmc_bus_put(host);
+}
+EXPORT_SYMBOL(mmc_power_restore_host);
+
+int mmc_card_awake(struct mmc_host *host)
+{
+	int err = -ENOSYS;
+
+	mmc_bus_get(host);
+
+	if (host->bus_ops && !host->bus_dead && host->bus_ops->awake)
+		err = host->bus_ops->awake(host);
+
+	mmc_bus_put(host);
+
+	return err;
+}
+EXPORT_SYMBOL(mmc_card_awake);
+
+int mmc_card_sleep(struct mmc_host *host)
+{
+	int err = -ENOSYS;
+
+	mmc_bus_get(host);
+
+	if (host->bus_ops && !host->bus_dead && host->bus_ops->awake)
+		err = host->bus_ops->sleep(host);
+
+	mmc_bus_put(host);
+
+	return err;
+}
+EXPORT_SYMBOL(mmc_card_sleep);
+
+int mmc_card_can_sleep(struct mmc_host *host)
+{
+	struct mmc_card *card = host->card;
+
+	if (card && mmc_card_mmc(card) && card->ext_csd.rev >= 3)
+		return 1;
+	return 0;
+}
+EXPORT_SYMBOL(mmc_card_can_sleep);
+
 #ifdef CONFIG_PM
 
 /**
@@ -977,27 +1267,37 @@ void mmc_stop_host(struct mmc_host *host)
  */
 int mmc_suspend_host(struct mmc_host *host, pm_message_t state)
 {
+	int err = 0;
+
+	if (host->caps & MMC_CAP_DISABLE)
+		cancel_delayed_work(&host->disable);
 	cancel_delayed_work(&host->detect);
 	mmc_flush_scheduled_work();
 
 	mmc_bus_get(host);
 	if (host->bus_ops && !host->bus_dead) {
 		if (host->bus_ops->suspend)
-			host->bus_ops->suspend(host);
-		if (!host->bus_ops->resume) {
+			err = host->bus_ops->suspend(host);
+		if (err == -ENOSYS || !host->bus_ops->resume) {
+			/*
+			 * We simply "remove" the card in this case.
+			 * It will be redetected on resume.
+			 */
 			if (host->bus_ops->remove)
 				host->bus_ops->remove(host);
-
 			mmc_claim_host(host);
 			mmc_detach_bus(host);
 			mmc_release_host(host);
+			host->pm_flags = 0;
+			err = 0;
 		}
 	}
 	mmc_bus_put(host);
 
-	mmc_power_off(host);
+	if (!err && !(host->pm_flags & MMC_PM_KEEP_POWER))
+		mmc_power_off(host);
 
-	return 0;
+	return err;
 }
 
 EXPORT_SYMBOL(mmc_suspend_host);
@@ -1008,26 +1308,75 @@ EXPORT_SYMBOL(mmc_suspend_host);
  */
 int mmc_resume_host(struct mmc_host *host)
 {
+	int err = 0;
+
 	mmc_bus_get(host);
 	if (host->bus_ops && !host->bus_dead) {
-		mmc_power_up(host);
-		mmc_select_voltage(host, host->ocr);
+		if (!(host->pm_flags & MMC_PM_KEEP_POWER)) {
+			mmc_power_up(host);
+			mmc_select_voltage(host, host->ocr);
+		}
 		BUG_ON(!host->bus_ops->resume);
-		host->bus_ops->resume(host);
+		err = host->bus_ops->resume(host);
+		if (err) {
+			printk(KERN_WARNING "%s: error %d during resume "
+					    "(card was removed?)\n",
+					    mmc_hostname(host), err);
+			err = 0;
+		}
 	}
 	mmc_bus_put(host);
 
-	/*
-	 * We add a slight delay here so that resume can progress
-	 * in parallel.
-	 */
-	mmc_detect_change(host, 1);
-
-	return 0;
+	return err;
 }
-
 EXPORT_SYMBOL(mmc_resume_host);
 
+/* Do the card removal on suspend if card is assumed removeable
+ * Do that in pm notifier while userspace isn't yet frozen, so we will be able
+   to sync the card.
+*/
+int mmc_pm_notify(struct notifier_block *notify_block,
+					unsigned long mode, void *unused)
+{
+	struct mmc_host *host = container_of(
+		notify_block, struct mmc_host, pm_notify);
+	unsigned long flags;
+
+
+	switch (mode) {
+	case PM_HIBERNATION_PREPARE:
+	case PM_SUSPEND_PREPARE:
+
+		spin_lock_irqsave(&host->lock, flags);
+		host->rescan_disable = 1;
+		spin_unlock_irqrestore(&host->lock, flags);
+		cancel_delayed_work_sync(&host->detect);
+
+		if (!host->bus_ops || host->bus_ops->suspend)
+			break;
+
+		mmc_claim_host(host);
+
+		if (host->bus_ops->remove)
+			host->bus_ops->remove(host);
+
+		mmc_detach_bus(host);
+		mmc_release_host(host);
+		host->pm_flags = 0;
+		break;
+
+	case PM_POST_SUSPEND:
+	case PM_POST_HIBERNATION:
+
+		spin_lock_irqsave(&host->lock, flags);
+		host->rescan_disable = 0;
+		spin_unlock_irqrestore(&host->lock, flags);
+		mmc_detect_change(host, 0);
+
+	}
+
+	return 0;
+}
 #endif
 
 static int __init mmc_init(void)
diff --git a/drivers/mmc/core/core.h b/drivers/mmc/core/core.h
index c819effa1032..a811c52a1659 100644
--- a/drivers/mmc/core/core.h
+++ b/drivers/mmc/core/core.h
@@ -16,10 +16,14 @@
 #define MMC_CMD_RETRIES        3
 
 struct mmc_bus_ops {
+	int (*awake)(struct mmc_host *);
+	int (*sleep)(struct mmc_host *);
 	void (*remove)(struct mmc_host *);
 	void (*detect)(struct mmc_host *);
-	void (*suspend)(struct mmc_host *);
-	void (*resume)(struct mmc_host *);
+	int (*suspend)(struct mmc_host *);
+	int (*resume)(struct mmc_host *);
+	void (*power_save)(struct mmc_host *);
+	void (*power_restore)(struct mmc_host *);
 };
 
 void mmc_attach_bus(struct mmc_host *host, const struct mmc_bus_ops *ops);
@@ -50,7 +54,9 @@ int mmc_attach_mmc(struct mmc_host *host, u32 ocr);
 int mmc_attach_sd(struct mmc_host *host, u32 ocr);
 int mmc_attach_sdio(struct mmc_host *host, u32 ocr);
 
+/* Module parameters */
 extern int use_spi_crc;
+extern int mmc_assume_removable;
 
 /* Debugfs information for hosts and cards */
 void mmc_add_host_debugfs(struct mmc_host *host);
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 5e945e64ead7..0efe631e50ca 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -16,6 +16,8 @@
 #include <linux/idr.h>
 #include <linux/pagemap.h>
 #include <linux/leds.h>
+#include <linux/slab.h>
+#include <linux/suspend.h>
 
 #include <linux/mmc/host.h>
 
@@ -83,6 +85,8 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *dev)
 	spin_lock_init(&host->lock);
 	init_waitqueue_head(&host->wq);
 	INIT_DELAYED_WORK(&host->detect, mmc_rescan);
+	INIT_DELAYED_WORK_DEFERRABLE(&host->disable, mmc_host_deeper_disable);
+	host->pm_notify.notifier_call = mmc_pm_notify;
 
 	/*
 	 * By default, hosts do not support SGIO or large requests.
@@ -131,6 +135,7 @@ int mmc_add_host(struct mmc_host *host)
 #endif
 
 	mmc_start_host(host);
+	register_pm_notifier(&host->pm_notify);
 
 	return 0;
 }
@@ -147,6 +152,7 @@ EXPORT_SYMBOL(mmc_add_host);
  */
 void mmc_remove_host(struct mmc_host *host)
 {
+	unregister_pm_notifier(&host->pm_notify);
 	mmc_stop_host(host);
 
 #ifdef CONFIG_DEBUG_FS
diff --git a/drivers/mmc/core/host.h b/drivers/mmc/core/host.h
index c2dc3d2d9f9a..8c87e1109a34 100644
--- a/drivers/mmc/core/host.h
+++ b/drivers/mmc/core/host.h
@@ -14,5 +14,7 @@
 int mmc_register_host_class(void);
 void mmc_unregister_host_class(void);
 
+void mmc_host_deeper_disable(struct work_struct *work);
+
 #endif
 
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index e207dcf9e754..abcd4392a8e9 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -160,7 +160,6 @@ static int mmc_read_ext_csd(struct mmc_card *card)
 {
 	int err;
 	u8 *ext_csd;
-	unsigned int ext_csd_struct;
 
 	BUG_ON(!card);
 
@@ -180,11 +179,11 @@ static int mmc_read_ext_csd(struct mmc_card *card)
 
 	err = mmc_send_ext_csd(card, ext_csd);
 	if (err) {
-		/*
-		 * We all hosts that cannot perform the command
-		 * to fail more gracefully
-		 */
-		if (err != -EINVAL)
+		/* If the host or the card can't do the switch,
+		 * fail more gracefully. */
+		if ((err != -EINVAL)
+		 && (err != -ENOSYS)
+		 && (err != -EFAULT))
 			goto out;
 
 		/*
@@ -207,16 +206,16 @@ static int mmc_read_ext_csd(struct mmc_card *card)
 		goto out;
 	}
 
-	ext_csd_struct = ext_csd[EXT_CSD_REV];
-	if (ext_csd_struct > 5) {
+	card->ext_csd.rev = ext_csd[EXT_CSD_REV];
+	if (card->ext_csd.rev > 3) {
 		printk(KERN_ERR "%s: unrecognised EXT_CSD structure "
 			"version %d\n", mmc_hostname(card->host),
-			ext_csd_struct);
+			card->ext_csd.rev);
 		err = -EINVAL;
 		goto out;
 	}
 
-	if (ext_csd_struct >= 2) {
+	if (card->ext_csd.rev >= 2) {
 		card->ext_csd.sectors =
 			ext_csd[EXT_CSD_SEC_CNT + 0] << 0 |
 			ext_csd[EXT_CSD_SEC_CNT + 1] << 8 |
@@ -226,7 +225,13 @@ static int mmc_read_ext_csd(struct mmc_card *card)
 			mmc_card_set_blockaddr(card);
 	}
 
+	card->ext_csd.card_type = ext_csd[EXT_CSD_CARD_TYPE];
+
 	switch (ext_csd[EXT_CSD_CARD_TYPE]) {
+	case EXT_CSD_CARD_TYPE_DDR_52 | EXT_CSD_CARD_TYPE_52
+		| EXT_CSD_CARD_TYPE_26:
+		card->ext_csd.hs_max_dtr = 52000000;
+		break;
 	case EXT_CSD_CARD_TYPE_52 | EXT_CSD_CARD_TYPE_26:
 		card->ext_csd.hs_max_dtr = 52000000;
 		break;
@@ -238,9 +243,20 @@ static int mmc_read_ext_csd(struct mmc_card *card)
 		printk(KERN_WARNING "%s: card is mmc v4 but doesn't "
 			"support any high-speed modes.\n",
 			mmc_hostname(card->host));
+		printk(KERN_WARNING "%s: card type is 0x%x\n",
+			mmc_hostname(card->host), ext_csd[EXT_CSD_CARD_TYPE]);
 		goto out;
 	}
 
+	if (card->ext_csd.rev >= 3) {
+		u8 sa_shift = ext_csd[EXT_CSD_S_A_TIMEOUT];
+
+		/* Sleep / awake timeout in 100ns units */
+		if (sa_shift > 0 && sa_shift <= 0x17)
+			card->ext_csd.sa_timeout =
+					1 << ext_csd[EXT_CSD_S_A_TIMEOUT];
+	}
+
 out:
 	kfree(ext_csd);
 
@@ -434,10 +450,21 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
 	 * Activate wide bus (if supported).
 	 */
 	if ((card->csd.mmca_vsn >= CSD_SPEC_VER_4) &&
-	    (host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA))) {
+		(host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA
+			       | MMC_CAP_DATA_DDR))) {
 		unsigned ext_csd_bit, bus_width;
 
-		if (host->caps & MMC_CAP_8_BIT_DATA) {
+		if ((host->caps & MMC_CAP_8_BIT_DATA) &&
+				(host->caps & MMC_CAP_DATA_DDR) &&
+				(card->ext_csd.card_type & MMC_DDR_MODE_MASK)) {
+			ext_csd_bit = EXT_CSD_BUS_WIDTH_8_DDR;
+			bus_width = MMC_BUS_WIDTH_8 | MMC_BUS_WIDTH_DDR;
+		} else if ((host->caps & MMC_CAP_4_BIT_DATA) &&
+				(host->caps & MMC_CAP_DATA_DDR) &&
+				(card->ext_csd.card_type & MMC_DDR_MODE_MASK)) {
+			ext_csd_bit = EXT_CSD_BUS_WIDTH_4_DDR;
+			bus_width = MMC_BUS_WIDTH_4 | MMC_BUS_WIDTH_DDR;
+		} else if (host->caps & MMC_CAP_8_BIT_DATA) {
 			ext_csd_bit = EXT_CSD_BUS_WIDTH_8;
 			bus_width = MMC_BUS_WIDTH_8;
 		} else {
@@ -507,12 +534,10 @@ static void mmc_detect(struct mmc_host *host)
 	}
 }
 
-#ifdef CONFIG_MMC_UNSAFE_RESUME
-
 /*
  * Suspend callback from host.
  */
-static void mmc_suspend(struct mmc_host *host)
+static int mmc_suspend(struct mmc_host *host)
 {
 	BUG_ON(!host);
 	BUG_ON(!host->card);
@@ -522,6 +547,8 @@ static void mmc_suspend(struct mmc_host *host)
 		mmc_deselect_cards(host);
 	host->card->state &= ~MMC_STATE_HIGHSPEED;
 	mmc_release_host(host);
+
+	return 0;
 }
 
 /*
@@ -530,7 +557,7 @@ static void mmc_suspend(struct mmc_host *host)
  * This function tries to determine if the same card is still present
  * and, if so, restore all state to it.
  */
-static void mmc_resume(struct mmc_host *host)
+static int mmc_resume(struct mmc_host *host)
 {
 	int err;
 
@@ -541,30 +568,78 @@ static void mmc_resume(struct mmc_host *host)
 	err = mmc_init_card(host, host->ocr, host->card);
 	mmc_release_host(host);
 
-	if (err) {
-		mmc_remove(host);
+	return err;
+}
 
-		mmc_claim_host(host);
-		mmc_detach_bus(host);
-		mmc_release_host(host);
+static void mmc_power_restore(struct mmc_host *host)
+{
+	host->card->state &= ~MMC_STATE_HIGHSPEED;
+	mmc_claim_host(host);
+	mmc_init_card(host, host->ocr, host->card);
+	mmc_release_host(host);
+}
+
+static int mmc_sleep(struct mmc_host *host)
+{
+	struct mmc_card *card = host->card;
+	int err = -ENOSYS;
+
+	if (card && card->ext_csd.rev >= 3) {
+		err = mmc_card_sleepawake(host, 1);
+		if (err < 0)
+			pr_debug("%s: Error %d while putting card into sleep",
+				 mmc_hostname(host), err);
 	}
 
+	return err;
 }
 
-#else
-
-#define mmc_suspend NULL
-#define mmc_resume NULL
+static int mmc_awake(struct mmc_host *host)
+{
+	struct mmc_card *card = host->card;
+	int err = -ENOSYS;
+
+	if (card && card->ext_csd.rev >= 3) {
+		err = mmc_card_sleepawake(host, 0);
+		if (err < 0)
+			pr_debug("%s: Error %d while awaking sleeping card",
+				 mmc_hostname(host), err);
+	}
 
-#endif
+	return err;
+}
 
 static const struct mmc_bus_ops mmc_ops = {
+	.awake = mmc_awake,
+	.sleep = mmc_sleep,
+	.remove = mmc_remove,
+	.detect = mmc_detect,
+	.suspend = NULL,
+	.resume = NULL,
+	.power_restore = mmc_power_restore,
+};
+
+static const struct mmc_bus_ops mmc_ops_unsafe = {
+	.awake = mmc_awake,
+	.sleep = mmc_sleep,
 	.remove = mmc_remove,
 	.detect = mmc_detect,
 	.suspend = mmc_suspend,
 	.resume = mmc_resume,
+	.power_restore = mmc_power_restore,
 };
 
+static void mmc_attach_bus_ops(struct mmc_host *host)
+{
+	const struct mmc_bus_ops *bus_ops;
+
+	if (host->caps & MMC_CAP_NONREMOVABLE || !mmc_assume_removable)
+		bus_ops = &mmc_ops_unsafe;
+	else
+		bus_ops = &mmc_ops;
+	mmc_attach_bus(host, bus_ops);
+}
+
 /*
  * Starting point for MMC card init.
  */
@@ -575,7 +650,7 @@ int mmc_attach_mmc(struct mmc_host *host, u32 ocr)
 	BUG_ON(!host);
 	WARN_ON(!host->claimed);
 
-	mmc_attach_bus(host, &mmc_ops);
+	mmc_attach_bus_ops(host);
 
 	/*
 	 * We need to get OCR a different way for SPI.
diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c
index 34ce2703d29a..355c6042cf65 100644
--- a/drivers/mmc/core/mmc_ops.c
+++ b/drivers/mmc/core/mmc_ops.c
@@ -57,6 +57,42 @@ int mmc_deselect_cards(struct mmc_host *host)
 	return _mmc_select_card(host, NULL);
 }
 
+int mmc_card_sleepawake(struct mmc_host *host, int sleep)
+{
+	struct mmc_command cmd;
+	struct mmc_card *card = host->card;
+	int err;
+
+	if (sleep)
+		mmc_deselect_cards(host);
+
+	memset(&cmd, 0, sizeof(struct mmc_command));
+
+	cmd.opcode = MMC_SLEEP_AWAKE;
+	cmd.arg = card->rca << 16;
+	if (sleep)
+		cmd.arg |= 1 << 15;
+
+	cmd.flags = MMC_RSP_R1B | MMC_CMD_AC;
+	err = mmc_wait_for_cmd(host, &cmd, 0);
+	if (err)
+		return err;
+
+	/*
+	 * If the host does not wait while the card signals busy, then we will
+	 * will have to wait the sleep/awake timeout.  Note, we cannot use the
+	 * SEND_STATUS command to poll the status because that command (and most
+	 * others) is invalid while the card sleeps.
+	 */
+	if (!(host->caps & MMC_CAP_WAIT_WHILE_BUSY))
+		mmc_delay(DIV_ROUND_UP(card->ext_csd.sa_timeout, 10000));
+
+	if (!sleep)
+		err = mmc_select_card(card);
+
+	return err;
+}
+
 int mmc_go_idle(struct mmc_host *host)
 {
 	int err;
diff --git a/drivers/mmc/core/mmc_ops.h b/drivers/mmc/core/mmc_ops.h
index 17854bf7cf0d..653eb8e84178 100644
--- a/drivers/mmc/core/mmc_ops.h
+++ b/drivers/mmc/core/mmc_ops.h
@@ -25,6 +25,7 @@ int mmc_send_status(struct mmc_card *card, u32 *status);
 int mmc_send_cid(struct mmc_host *host, u32 *cid);
 int mmc_spi_read_ocr(struct mmc_host *host, int highcap, u32 *ocrp);
 int mmc_spi_set_crc(struct mmc_host *host, int use_crc);
+int mmc_card_sleepawake(struct mmc_host *host, int sleep);
 
 #endif
 
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
index cd81c395e164..c2a8cafd8276 100644
--- a/drivers/mmc/core/sd.c
+++ b/drivers/mmc/core/sd.c
@@ -210,11 +210,11 @@ static int mmc_read_switch(struct mmc_card *card)
 
 	err = mmc_sd_switch(card, 0, 0, 1, status);
 	if (err) {
-		/*
-		 * We all hosts that cannot perform the command
-		 * to fail more gracefully
-		 */
-		if (err != -EINVAL)
+		/* If the host or the card can't do the switch,
+		 * fail more gracefully. */
+		if ((err != -EINVAL)
+		 && (err != -ENOSYS)
+		 && (err != -EFAULT))
 			goto out;
 
 		printk(KERN_WARNING "%s: problem reading switch "
@@ -561,12 +561,10 @@ static void mmc_sd_detect(struct mmc_host *host)
 	}
 }
 
-#ifdef CONFIG_MMC_UNSAFE_RESUME
-
 /*
  * Suspend callback from host.
  */
-static void mmc_sd_suspend(struct mmc_host *host)
+static int mmc_sd_suspend(struct mmc_host *host)
 {
 	BUG_ON(!host);
 	BUG_ON(!host->card);
@@ -576,6 +574,8 @@ static void mmc_sd_suspend(struct mmc_host *host)
 		mmc_deselect_cards(host);
 	host->card->state &= ~MMC_STATE_HIGHSPEED;
 	mmc_release_host(host);
+
+	return 0;
 }
 
 /*
@@ -584,7 +584,7 @@ static void mmc_sd_suspend(struct mmc_host *host)
  * This function tries to determine if the same card is still present
  * and, if so, restore all state to it.
  */
-static void mmc_sd_resume(struct mmc_host *host)
+static int mmc_sd_resume(struct mmc_host *host)
 {
 	int err;
 
@@ -595,30 +595,44 @@ static void mmc_sd_resume(struct mmc_host *host)
 	err = mmc_sd_init_card(host, host->ocr, host->card);
 	mmc_release_host(host);
 
-	if (err) {
-		mmc_sd_remove(host);
-
-		mmc_claim_host(host);
-		mmc_detach_bus(host);
-		mmc_release_host(host);
-	}
-
+	return err;
 }
 
-#else
-
-#define mmc_sd_suspend NULL
-#define mmc_sd_resume NULL
-
-#endif
+static void mmc_sd_power_restore(struct mmc_host *host)
+{
+	host->card->state &= ~MMC_STATE_HIGHSPEED;
+	mmc_claim_host(host);
+	mmc_sd_init_card(host, host->ocr, host->card);
+	mmc_release_host(host);
+}
 
 static const struct mmc_bus_ops mmc_sd_ops = {
 	.remove = mmc_sd_remove,
 	.detect = mmc_sd_detect,
+	.suspend = NULL,
+	.resume = NULL,
+	.power_restore = mmc_sd_power_restore,
+};
+
+static const struct mmc_bus_ops mmc_sd_ops_unsafe = {
+	.remove = mmc_sd_remove,
+	.detect = mmc_sd_detect,
 	.suspend = mmc_sd_suspend,
 	.resume = mmc_sd_resume,
+	.power_restore = mmc_sd_power_restore,
 };
 
+static void mmc_sd_attach_bus_ops(struct mmc_host *host)
+{
+	const struct mmc_bus_ops *bus_ops;
+
+	if (host->caps & MMC_CAP_NONREMOVABLE || !mmc_assume_removable)
+		bus_ops = &mmc_sd_ops_unsafe;
+	else
+		bus_ops = &mmc_sd_ops;
+	mmc_attach_bus(host, bus_ops);
+}
+
 /*
  * Starting point for SD card init.
  */
@@ -629,7 +643,7 @@ int mmc_attach_sd(struct mmc_host *host, u32 ocr)
 	BUG_ON(!host);
 	WARN_ON(!host->claimed);
 
-	mmc_attach_bus(host, &mmc_sd_ops);
+	mmc_sd_attach_bus_ops(host);
 
 	/*
 	 * We need to get OCR a different way for SPI.
diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c
index fb99ccff9080..7f3093dd2b49 100644
--- a/drivers/mmc/core/sdio.c
+++ b/drivers/mmc/core/sdio.c
@@ -195,6 +195,135 @@ static int sdio_enable_hs(struct mmc_card *card)
 }
 
 /*
+ * Handle the detection and initialisation of a card.
+ *
+ * In the case of a resume, "oldcard" will contain the card
+ * we're trying to reinitialise.
+ */
+static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr,
+			      struct mmc_card *oldcard)
+{
+	struct mmc_card *card;
+	int err;
+
+	BUG_ON(!host);
+	WARN_ON(!host->claimed);
+
+	/*
+	 * Inform the card of the voltage
+	 */
+	err = mmc_send_io_op_cond(host, host->ocr, &ocr);
+	if (err)
+		goto err;
+
+	/*
+	 * For SPI, enable CRC as appropriate.
+	 */
+	if (mmc_host_is_spi(host)) {
+		err = mmc_spi_set_crc(host, use_spi_crc);
+		if (err)
+			goto err;
+	}
+
+	/*
+	 * Allocate card structure.
+	 */
+	card = mmc_alloc_card(host, NULL);
+	if (IS_ERR(card)) {
+		err = PTR_ERR(card);
+		goto err;
+	}
+
+	card->type = MMC_TYPE_SDIO;
+
+	/*
+	 * For native busses:  set card RCA and quit open drain mode.
+	 */
+	if (!mmc_host_is_spi(host)) {
+		err = mmc_send_relative_addr(host, &card->rca);
+		if (err)
+			goto remove;
+
+		mmc_set_bus_mode(host, MMC_BUSMODE_PUSHPULL);
+	}
+
+	/*
+	 * Select card, as all following commands rely on that.
+	 */
+	if (!mmc_host_is_spi(host)) {
+		err = mmc_select_card(card);
+		if (err)
+			goto remove;
+	}
+
+	/*
+	 * Read the common registers.
+	 */
+	err = sdio_read_cccr(card);
+	if (err)
+		goto remove;
+
+	/*
+	 * Read the common CIS tuples.
+	 */
+	err = sdio_read_common_cis(card);
+	if (err)
+		goto remove;
+
+	if (oldcard) {
+		int same = (card->cis.vendor == oldcard->cis.vendor &&
+			    card->cis.device == oldcard->cis.device);
+		mmc_remove_card(card);
+		if (!same) {
+			err = -ENOENT;
+			goto err;
+		}
+		card = oldcard;
+		return 0;
+	}
+
+	/*
+	 * Switch to high-speed (if supported).
+	 */
+	err = sdio_enable_hs(card);
+	if (err)
+		goto remove;
+
+	/*
+	 * Change to the card's maximum speed.
+	 */
+	if (mmc_card_highspeed(card)) {
+		/*
+		 * The SDIO specification doesn't mention how
+		 * the CIS transfer speed register relates to
+		 * high-speed, but it seems that 50 MHz is
+		 * mandatory.
+		 */
+		mmc_set_clock(host, 50000000);
+	} else {
+		mmc_set_clock(host, card->cis.max_dtr);
+	}
+
+	/*
+	 * Switch to wider bus (if supported).
+	 */
+	err = sdio_enable_wide(card);
+	if (err)
+		goto remove;
+
+	if (!oldcard)
+		host->card = card;
+	return 0;
+
+remove:
+	if (!oldcard)
+		mmc_remove_card(card);
+
+err:
+	return err;
+}
+
+/*
  * Host is being removed. Free up the current card.
  */
 static void mmc_sdio_remove(struct mmc_host *host)
@@ -243,10 +372,77 @@ static void mmc_sdio_detect(struct mmc_host *host)
 	}
 }
 
+/*
+ * SDIO suspend.  We need to suspend all functions separately.
+ * Therefore all registered functions must have drivers with suspend
+ * and resume methods.  Failing that we simply remove the whole card.
+ */
+static int mmc_sdio_suspend(struct mmc_host *host)
+{
+	int i, err = 0;
+
+	for (i = 0; i < host->card->sdio_funcs; i++) {
+		struct sdio_func *func = host->card->sdio_func[i];
+		if (func && sdio_func_present(func) && func->dev.driver) {
+			const struct dev_pm_ops *pmops = func->dev.driver->pm;
+			if (!pmops || !pmops->suspend || !pmops->resume) {
+				/* force removal of entire card in that case */
+				err = -ENOSYS;
+			} else
+				err = pmops->suspend(&func->dev);
+			if (err)
+				break;
+		}
+	}
+	while (err && --i >= 0) {
+		struct sdio_func *func = host->card->sdio_func[i];
+		if (func && sdio_func_present(func) && func->dev.driver) {
+			const struct dev_pm_ops *pmops = func->dev.driver->pm;
+			pmops->resume(&func->dev);
+		}
+	}
+
+	return err;
+}
+
+static int mmc_sdio_resume(struct mmc_host *host)
+{
+	int i, err;
+
+	BUG_ON(!host);
+	BUG_ON(!host->card);
+
+	/* Basic card reinitialization. */
+	mmc_claim_host(host);
+	err = mmc_sdio_init_card(host, host->ocr, host->card);
+	mmc_release_host(host);
+
+	/*
+	 * If the card looked to be the same as before suspending, then
+	 * we proceed to resume all card functions.  If one of them returns
+	 * an error then we simply return that error to the core and the
+	 * card will be redetected as new.  It is the responsibility of
+	 * the function driver to perform further tests with the extra
+	 * knowledge it has of the card to confirm the card is indeed the
+	 * same as before suspending (same MAC address for network cards,
+	 * etc.) and return an error otherwise.
+	 */
+	for (i = 0; !err && i < host->card->sdio_funcs; i++) {
+		struct sdio_func *func = host->card->sdio_func[i];
+		if (func && sdio_func_present(func) && func->dev.driver) {
+			const struct dev_pm_ops *pmops = func->dev.driver->pm;
+			err = pmops->resume(&func->dev);
+		}
+	}
+
+	return err;
+}
 
 static const struct mmc_bus_ops mmc_sdio_ops = {
 	.remove = mmc_sdio_remove,
 	.detect = mmc_sdio_detect,
+	.suspend = mmc_sdio_suspend,
+	.resume = mmc_sdio_resume,
 };
 
 
diff --git a/drivers/mmc/core/sdio_io.c b/drivers/mmc/core/sdio_io.c
index f61fc2d4cd0a..ff69a2feecd5 100644
--- a/drivers/mmc/core/sdio_io.c
+++ b/drivers/mmc/core/sdio_io.c
@@ -635,3 +635,52 @@ void sdio_f0_writeb(struct sdio_func *func, unsigned char b, unsigned int addr,
 		*err_ret = ret;
 }
 EXPORT_SYMBOL_GPL(sdio_f0_writeb);
+
+/**
+ *	sdio_get_host_pm_caps - get host power management capabilities
+ *	@func: SDIO function attached to host
+ *
+ *	Returns a capability bitmask corresponding to power management
+ *	features supported by the host controller that the card function
+ *	might rely upon during a system suspend.  The host doesn't need
+ *	to be claimed, nor the function active, for this information to be
+ *	obtained.
+ */
+mmc_pm_flag_t sdio_get_host_pm_caps(struct sdio_func *func)
+{
+	BUG_ON(!func);
+	BUG_ON(!func->card);
+
+	return func->card->host->pm_caps;
+}
+EXPORT_SYMBOL_GPL(sdio_get_host_pm_caps);
+
+/**
+ *	sdio_set_host_pm_flags - set wanted host power management capabilities
+ *	@func: SDIO function attached to host
+ *
+ *	Set a capability bitmask corresponding to wanted host controller
+ *	power management features for the upcoming suspend state.
+ *	This must be called, if needed, each time the suspend method of
+ *	the function driver is called, and must contain only bits that
+ *	were returned by sdio_get_host_pm_caps().
+ *	The host doesn't need to be claimed, nor the function active,
+ *	for this information to be set.
+ */
+int sdio_set_host_pm_flags(struct sdio_func *func, mmc_pm_flag_t flags)
+{
+	struct mmc_host *host;
+
+	BUG_ON(!func);
+	BUG_ON(!func->card);
+
+	host = func->card->host;
+
+	if (flags & ~host->pm_caps)
+		return -EINVAL;
+
+	/* function suspend methods are serialized, hence no lock needed */
+	host->pm_flags |= flags;
+	return 0;
+}
+EXPORT_SYMBOL_GPL(sdio_set_host_pm_flags);
diff --git a/drivers/mmc/core/sdio_ops.c b/drivers/mmc/core/sdio_ops.c
index 208beeb23ed6..b6304fb8bf90 100644
--- a/drivers/mmc/core/sdio_ops.c
+++ b/drivers/mmc/core/sdio_ops.c
@@ -67,6 +67,61 @@ int mmc_send_io_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr)
 	return err;
 }
 
+static int mmc_io_rw_direct_host(struct mmc_host *host, int write, unsigned fn,
+	unsigned addr, u8 in, u8 *out)
+{
+	struct mmc_command cmd;
+	int err;
+
+	BUG_ON(!host);
+	BUG_ON(fn > 7);
+
+	/* sanity check */
+	if (addr & ~0x1FFFF)
+		return -EINVAL;
+
+	memset(&cmd, 0, sizeof(struct mmc_command));
+
+	cmd.opcode = SD_IO_RW_DIRECT;
+	cmd.arg = write ? 0x80000000 : 0x00000000;
+	cmd.arg |= fn << 28;
+	cmd.arg |= (write && out) ? 0x08000000 : 0x00000000;
+	cmd.arg |= addr << 9;
+	cmd.arg |= in;
+	cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
+
+	err = mmc_wait_for_cmd(host, &cmd, 0);
+	if (err)
+		return err;
+
+	if (mmc_host_is_spi(host)) {
+		/* host driver already reported errors */
+	} else {
+		if (cmd.resp[0] & R5_ERROR)
+			return -EIO;
+		if (cmd.resp[0] & R5_FUNCTION_NUMBER)
+			return -EINVAL;
+		if (cmd.resp[0] & R5_OUT_OF_RANGE)
+			return -ERANGE;
+	}
+
+	if (out) {
+		if (mmc_host_is_spi(host))
+			*out = (cmd.resp[0] >> 8) & 0xFF;
+		else
+			*out = cmd.resp[0] & 0xFF;
+	}
+
+	return 0;
+}
+
+int mmc_io_rw_direct(struct mmc_card *card, int write, unsigned fn,
+	unsigned addr, u8 in, u8 *out)
+{
+	BUG_ON(!card);
+	return mmc_io_rw_direct_host(card->host, write, fn, addr, in, out);
+}
+
 int mmc_io_rw_extended(struct mmc_card *card, int write, unsigned fn,
 	unsigned addr, int incr_addr, u8 *buf, unsigned blocks, unsigned blksz)
 {
@@ -134,62 +189,7 @@ int mmc_io_rw_extended(struct mmc_card *card, int write, unsigned fn,
 	return 0;
 }
 
-static int mmc_io_rw_direct_host(struct mmc_host *host, int write, unsigned fn,
-	unsigned addr, u8 in, u8 *out)
-{
-	struct mmc_command cmd;
-	int err;
-
-	BUG_ON(!host);
-	BUG_ON(fn > 7);
-
-	/* sanity check */
-	if (addr & ~0x1FFFF)
-		return -EINVAL;
-
-	memset(&cmd, 0, sizeof(struct mmc_command));
-
-	cmd.opcode = SD_IO_RW_DIRECT;
-	cmd.arg = write ? 0x80000000 : 0x00000000;
-	cmd.arg |= fn << 28;
-	cmd.arg |= (write && out) ? 0x08000000 : 0x00000000;
-	cmd.arg |= addr << 9;
-	cmd.arg |= in;
-	cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
-
-	err = mmc_wait_for_cmd(host, &cmd, 0);
-	if (err)
-		return err;
-
-	if (mmc_host_is_spi(host)) {
-		/* host driver already reported errors */
-	} else {
-		if (cmd.resp[0] & R5_ERROR)
-			return -EIO;
-		if (cmd.resp[0] & R5_FUNCTION_NUMBER)
-			return -EINVAL;
-		if (cmd.resp[0] & R5_OUT_OF_RANGE)
-			return -ERANGE;
-	}
-
-	if (out) {
-		if (mmc_host_is_spi(host))
-			*out = (cmd.resp[0] >> 8) & 0xFF;
-		else
-			*out = cmd.resp[0] & 0xFF;
-	}
-
-	return 0;
-}
-
-int mmc_io_rw_direct(struct mmc_card *card, int write, unsigned fn,
-	unsigned addr, u8 in, u8 *out)
-{
-	BUG_ON(!card);
-	return mmc_io_rw_direct_host(card->host, write, fn, addr, in, out);
-}
-
-int sdio_go_idle(struct mmc_host *host)
+int sdio_reset(struct mmc_host *host)
 {
 	int ret;
 	u8 abort;
diff --git a/drivers/mmc/core/sdio_ops.h b/drivers/mmc/core/sdio_ops.h
index 9b546c71eb5e..85c7ecf809f4 100644
--- a/drivers/mmc/core/sdio_ops.h
+++ b/drivers/mmc/core/sdio_ops.h
@@ -18,6 +18,7 @@ int mmc_io_rw_direct(struct mmc_card *card, int write, unsigned fn,
 int mmc_io_rw_extended(struct mmc_card *card, int write, unsigned fn,
 	unsigned addr, int incr_addr, u8 *buf, unsigned blocks, unsigned blksz);
 int sdio_go_idle(struct mmc_host *host);
+int sdio_reset(struct mmc_host *host);
 
 #endif
 
diff --git a/drivers/mmc/host/mx_sdhci.c b/drivers/mmc/host/mx_sdhci.c
index 5a68a8e02fe2..0557d4d337c1 100644
--- a/drivers/mmc/host/mx_sdhci.c
+++ b/drivers/mmc/host/mx_sdhci.c
@@ -142,32 +142,32 @@ EXPORT_SYMBOL(mxc_mmc_force_detect);
 
 static void sdhci_dumpregs(struct sdhci_host *host)
 {
-	printk(KERN_DEBUG DRIVER_NAME
+	printk(KERN_INFO DRIVER_NAME
 	       ": ============== REGISTER DUMP ==============\n");
 
-	printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
+	printk(KERN_INFO DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
 	       readl(host->ioaddr + SDHCI_DMA_ADDRESS),
 	       readl(host->ioaddr + SDHCI_HOST_VERSION));
-	printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
+	printk(KERN_INFO DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
 	       (readl(host->ioaddr + SDHCI_BLOCK_SIZE) & 0xFFFF),
 	       (readl(host->ioaddr + SDHCI_BLOCK_COUNT) >> 16));
-	printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
+	printk(KERN_INFO DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
 	       readl(host->ioaddr + SDHCI_ARGUMENT),
 	       readl(host->ioaddr + SDHCI_TRANSFER_MODE));
-	printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
+	printk(KERN_INFO DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
 	       readl(host->ioaddr + SDHCI_PRESENT_STATE),
 	       readl(host->ioaddr + SDHCI_HOST_CONTROL));
-	printk(KERN_DEBUG DRIVER_NAME ": Clock:    0x%08x\n",
+	printk(KERN_INFO DRIVER_NAME ": Clock:    0x%08x\n",
 	       readl(host->ioaddr + SDHCI_CLOCK_CONTROL));
-	printk(KERN_DEBUG DRIVER_NAME ": Int stat: 0x%08x\n",
+	printk(KERN_INFO DRIVER_NAME ": Int stat: 0x%08x\n",
 	       readl(host->ioaddr + SDHCI_INT_STATUS));
-	printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
+	printk(KERN_INFO DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 	       readl(host->ioaddr + SDHCI_INT_ENABLE),
 	       readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
-	printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x\n",
+	printk(KERN_INFO DRIVER_NAME ": Caps:     0x%08x\n",
 	       readl(host->ioaddr + SDHCI_CAPABILITIES));
 
-	printk(KERN_DEBUG DRIVER_NAME
+	printk(KERN_INFO DRIVER_NAME
 	       ": ===========================================\n");
 }
 
@@ -506,6 +506,30 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 		host->flags &= ~SDHCI_REQ_USE_DMA;
 	}
 
+	if (cpu_is_mx25() && (data->blksz * data->blocks < 0x10)) {
+		host->flags &= ~SDHCI_REQ_USE_DMA;
+		DBG("Reverting to PIO in small data transfer.\n");
+		writel(readl(host->ioaddr + SDHCI_INT_ENABLE)
+				| SDHCI_INT_DATA_AVAIL
+				| SDHCI_INT_SPACE_AVAIL,
+				host->ioaddr + SDHCI_INT_ENABLE);
+		writel(readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)
+				| SDHCI_INT_DATA_AVAIL
+				| SDHCI_INT_SPACE_AVAIL,
+				host->ioaddr + SDHCI_SIGNAL_ENABLE);
+	} else if (cpu_is_mx25() && (host->flags & SDHCI_USE_DMA)) {
+		host->flags |= SDHCI_REQ_USE_DMA;
+		DBG("Reverting to DMA in large data transfer.\n");
+		writel(readl(host->ioaddr + SDHCI_INT_ENABLE)
+				& ~(SDHCI_INT_DATA_AVAIL
+				| SDHCI_INT_SPACE_AVAIL),
+				host->ioaddr + SDHCI_INT_ENABLE);
+		writel(readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)
+				& ~(SDHCI_INT_DATA_AVAIL
+				| SDHCI_INT_SPACE_AVAIL),
+				host->ioaddr + SDHCI_SIGNAL_ENABLE);
+	}
+
 	if (host->flags & SDHCI_REQ_USE_DMA) {
 		int i;
 		struct scatterlist *tsg;
@@ -644,7 +668,7 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 	WARN_ON(host->cmd);
 
 	/* Wait max 10 ms */
-	timeout = 5000;
+	timeout = 500;
 
 	mask = SDHCI_CMD_INHIBIT;
 	if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
@@ -695,7 +719,7 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 			mode |= SDHCI_TRNS_READ;
 		else
 			mode &= ~SDHCI_TRNS_READ;
-		if (host->flags & SDHCI_USE_DMA)
+		if (host->flags & SDHCI_REQ_USE_DMA)
 			mode |= SDHCI_TRNS_DMA;
 		if (host->flags & SDHCI_USE_EXTERNAL_DMA)
 			DBG("Prepare data completely in %s transfer mode.\n",
@@ -727,6 +751,11 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 		flags |= SDHCI_CMD_DATA;
 
 	mode |= SDHCI_MAKE_CMD(cmd->opcode, flags);
+	if (host->mmc->ios.bus_width & MMC_BUS_WIDTH_DDR) {
+		/* Eanble the DDR mode */
+		mode |= SDHCI_TRNS_DDR_EN;
+	} else
+		mode &= ~SDHCI_TRNS_DDR_EN;
 	DBG("Complete sending cmd, transfer mode would be 0x%x.\n", mode);
 	writel(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
 }
@@ -775,6 +804,7 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 	int clk_rate = 0;
 	u32 clk;
 	unsigned long timeout;
+	struct mmc_ios ios = host->mmc->ios;
 
 	if (clock == 0) {
 		goto out;
@@ -784,17 +814,20 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 			host->plat_data->clk_flg = 1;
 		}
 	}
-	if (clock == host->clock)
+	if (clock == host->clock && !(ios.bus_width & MMC_BUS_WIDTH_DDR))
 		return;
 
 	clk_rate = clk_get_rate(host->clk);
 	clk = readl(host->ioaddr + SDHCI_CLOCK_CONTROL) & ~SDHCI_CLOCK_MASK;
-	if (!cpu_is_mx53())
+	if (cpu_is_mx53() || cpu_is_mx50())
+		writel(clk | SDHCI_CLOCK_SDCLKFS1,
+				host->ioaddr + SDHCI_CLOCK_CONTROL);
+	else
 		writel(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 
 	if (clock == host->min_clk)
 		prescaler = 16;
-	else if (cpu_is_mx53())
+	else if (cpu_is_mx53() || cpu_is_mx50())
 		prescaler = 1;
 	else
 		prescaler = 0;
@@ -820,6 +853,86 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 	DBG("prescaler = 0x%x, divider = 0x%x\n", prescaler, div);
 	clk |= (prescaler << 8) | (div << 4);
 
+	/* Configure the DLL when DDR mode is enabled */
+	if (ios.bus_width & MMC_BUS_WIDTH_DDR) {
+		/* Make sure that the PER, HLK, IPG are all enabled */
+		writel(readl(host->ioaddr + SDHCI_CLOCK_CONTROL)
+				| SDHCI_CLOCK_IPG_EN
+				| SDHCI_CLOCK_HLK_EN
+				| SDHCI_CLOCK_PER_EN,
+				host->ioaddr + SDHCI_CLOCK_CONTROL);
+
+		/* Enable the DLL and delay chain */
+		writel(readl(host->ioaddr + SDHCI_DLL_CONTROL)
+				| DLL_CTRL_ENABLE,
+				host->ioaddr + SDHCI_DLL_CONTROL);
+
+		timeout = 1000000;
+		while (timeout > 0) {
+			timeout--;
+			if (readl(host->ioaddr + SDHCI_DLL_STATUS)
+					& DLL_STS_REF_LOCK)
+				break;
+			else if (timeout == 0)
+				printk(KERN_ERR "DLL REF LOCK Timeout!\n");
+		};
+		DBG("dll stat: 0x%x\n", readl(host->ioaddr + SDHCI_DLL_STATUS));
+
+		writel(readl(host->ioaddr + SDHCI_DLL_CONTROL)
+				| DLL_CTRL_SLV_UP_INT | DLL_CTRL_REF_UP_INT
+				| DLL_CTRL_SLV_DLY_TAR,
+				host->ioaddr + SDHCI_DLL_CONTROL);
+
+		timeout = 1000000;
+		while (timeout > 0) {
+			timeout--;
+			if (readl(host->ioaddr + SDHCI_DLL_STATUS)
+					& DLL_STS_SLV_LOCK)
+				break;
+			else if (timeout == 0)
+				printk(KERN_ERR "DLL SLV LOCK Timeout!\n");
+		};
+
+		writel(readl(host->ioaddr + SDHCI_DLL_CONTROL)
+				| DLL_CTRL_SLV_FORCE_UPD,
+				host->ioaddr + SDHCI_DLL_CONTROL);
+
+		writel(readl(host->ioaddr + SDHCI_DLL_CONTROL)
+				& (~DLL_CTRL_SLV_FORCE_UPD),
+				host->ioaddr + SDHCI_DLL_CONTROL);
+
+		timeout = 1000000;
+		while (timeout > 0) {
+			timeout--;
+			if (readl(host->ioaddr + SDHCI_DLL_STATUS)
+					& DLL_STS_REF_LOCK)
+				break;
+			else if (timeout == 0)
+				printk(KERN_ERR "DLL REF LOCK Timeout!\n");
+		};
+		timeout = 1000000;
+		while (timeout > 0) {
+			timeout--;
+			if (readl(host->ioaddr + SDHCI_DLL_STATUS)
+					& DLL_STS_SLV_LOCK)
+				break;
+			else if (timeout == 0)
+				printk(KERN_ERR "DLL SLV LOCK Timeout!\n");
+		};
+		DBG("dll stat: 0x%x\n", readl(host->ioaddr + SDHCI_DLL_STATUS));
+
+		/* Let the PER, HLK, IPG to be auto-gate */
+		writel(readl(host->ioaddr + SDHCI_CLOCK_CONTROL)
+				& ~(SDHCI_CLOCK_IPG_EN | SDHCI_CLOCK_HLK_EN
+					| SDHCI_CLOCK_PER_EN),
+				host->ioaddr + SDHCI_CLOCK_CONTROL);
+
+	} else if (readl(host->ioaddr + SDHCI_DLL_STATUS) & DLL_STS_SLV_LOCK) {
+		/* reset DLL CTRL */
+		writel(readl(host->ioaddr + SDHCI_DLL_CONTROL) | DLL_CTRL_RESET,
+				host->ioaddr + SDHCI_DLL_CONTROL);
+	}
+
 	/* Configure the clock control register */
 	clk |=
 	    (readl(host->ioaddr + SDHCI_CLOCK_CONTROL) & (~SDHCI_CLOCK_MASK));
@@ -830,7 +943,7 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 		       host->ioaddr + SDHCI_CLOCK_CONTROL);
 
 	/* Wait max 10 ms */
-	timeout = 5000;
+	timeout = 500;
 	while (timeout > 0) {
 		timeout--;
 		udelay(20);
@@ -933,8 +1046,8 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	u32 tmp;
 	mxc_dma_device_t dev_id = 0;
 
-	DBG("%s: clock %u, bus %lu, power %u, vdd %u\n", DRIVER_NAME,
-	    ios->clock, 1UL << ios->bus_width, ios->power_mode, ios->vdd);
+	DBG("%s: clock %u, bus %u, power %u, vdd %u\n", DRIVER_NAME,
+	    ios->clock, ios->bus_width, ios->power_mode, ios->vdd);
 
 	host = mmc_priv(mmc);
 
@@ -1000,10 +1113,10 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
 	tmp = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 
-	if (ios->bus_width == MMC_BUS_WIDTH_4) {
+	if ((ios->bus_width & ~MMC_BUS_WIDTH_DDR) == MMC_BUS_WIDTH_4) {
 		tmp &= ~SDHCI_CTRL_8BITBUS;
 		tmp |= SDHCI_CTRL_4BITBUS;
-	} else if (ios->bus_width == MMC_BUS_WIDTH_8) {
+	} else if ((ios->bus_width & ~MMC_BUS_WIDTH_DDR) == MMC_BUS_WIDTH_8) {
 		tmp &= ~SDHCI_CTRL_4BITBUS;
 		tmp |= SDHCI_CTRL_8BITBUS;
 	} else if (ios->bus_width == MMC_BUS_WIDTH_1) {
diff --git a/drivers/mmc/host/mx_sdhci.h b/drivers/mmc/host/mx_sdhci.h
index 0bd79934952e..fa36dff0fd9a 100644
--- a/drivers/mmc/host/mx_sdhci.h
+++ b/drivers/mmc/host/mx_sdhci.h
@@ -2,7 +2,6 @@
  *  linux/drivers/mmc/host/mx_sdhci.h - Secure Digital Host
  *  Controller Interface driver
  *
- *  Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
  *  Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -28,6 +27,7 @@
 #define  SDHCI_TRNS_DMA		0x00000001
 #define  SDHCI_TRNS_BLK_CNT_EN	0x00000002
 #define  SDHCI_TRNS_ACMD12	0x00000004
+#define  SDHCI_TRNS_DDR_EN 	0x00000008
 #define  SDHCI_TRNS_READ	0x00000010
 #define  SDHCI_TRNS_MULTI	0x00000020
 #define  SDHCI_TRNS_DPSEL	0x00200000
@@ -95,6 +95,7 @@
 #define  SDHCI_CLOCK_PER_EN	0x00000004
 #define  SDHCI_CLOCK_HLK_EN	0x00000002
 #define  SDHCI_CLOCK_IPG_EN	0x00000001
+#define  SDHCI_CLOCK_SDCLKFS1 	0x00000100
 #define  SDHCI_CLOCK_MASK 	0x0000FFFF
 
 #define SDHCI_TIMEOUT_CONTROL	0x2E
@@ -188,6 +189,17 @@
 #define SDHCI_ADMA_ADDRESS	0x58
 
 /* 60-FB reserved */
+#define SDHCI_DLL_CONTROL 	0x60
+#define DLL_CTRL_ENABLE 	0x00000001
+#define DLL_CTRL_RESET 		0x00000002
+#define DLL_CTRL_SLV_FORCE_UPD 	0x00000004
+#define DLL_CTRL_SLV_DLY_TAR 	0x00000000
+#define DLL_CTRL_SLV_UP_INT 	0x00200000
+#define DLL_CTRL_REF_UP_INT 	0x20000000
+
+#define SDHCI_DLL_STATUS 	0x64
+#define DLL_STS_SLV_LOCK 	0x00000001
+#define DLL_STS_REF_LOCK 	0x00000002
 
 /* ADMA Addr Descriptor Attribute Filed */
 enum {
diff --git a/drivers/mmc/host/mxc_mmc.c b/drivers/mmc/host/mxc_mmc.c
index 980dc98c9b5f..9cb492f40145 100644
--- a/drivers/mmc/host/mxc_mmc.c
+++ b/drivers/mmc/host/mxc_mmc.c
@@ -13,7 +13,7 @@
  */
 
 /*
- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -1232,7 +1232,7 @@ static int mxcmci_probe(struct platform_device *pdev)
 	mmc->f_max = mmc_plat->max_clk;
 	mmc->max_req_size = 32 * 1024;
 	mmc->max_seg_size = mmc->max_req_size;
-	mmc->max_blk_count = 65536;
+	mmc->max_blk_count = 32;
 
 	spin_lock_init(&host->lock);
 	host->mmc = mmc;
diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
index c60352247c49..b849e873613b 100644
--- a/drivers/mmc/host/mxs-mmc.c
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -183,6 +183,12 @@ static void mxs_mmc_detect_poll(unsigned long arg)
 				BM_SSP_CTRL1_RECV_TIMEOUT_IRQ   | \
 				BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
 
+#define MXS_MMC_ERR_BITS (BM_SSP_CTRL1_RESP_ERR_IRQ       | \
+				BM_SSP_CTRL1_RESP_TIMEOUT_IRQ   | \
+				BM_SSP_CTRL1_DATA_TIMEOUT_IRQ   | \
+				BM_SSP_CTRL1_DATA_CRC_IRQ       | \
+				BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)
+
 /* SSP DMA interrupt handler */
 static irqreturn_t mmc_irq_handler(int irq, void *dev_id)
 {
@@ -198,19 +204,17 @@ static irqreturn_t mmc_irq_handler(int irq, void *dev_id)
 		/* STOP the dma transfer here. */
 		mxs_dma_cooked(host->dmach, NULL);
 	}
-	host->status =
-	    __raw_readl(host->ssp_base + HW_SSP_STATUS);
 
-	if (host->cmd)		/* else it is a bogus interrupt */
-		complete(&host->dma_done);
+	if ((irq == host->dmairq) || (c1 & MXS_MMC_ERR_BITS))
+		if (host->cmd) {
+			host->status =
+				__raw_readl(host->ssp_base + HW_SSP_STATUS);
+			complete(&host->dma_done);
+		}
 
-	if ((c1 & BM_SSP_CTRL1_SDIO_IRQ) && (c1 & BM_SSP_CTRL1_SDIO_IRQ_EN)) {
-		__raw_writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, host->ssp_base + \
-			HW_SSP_CTRL0_CLR);
-		__raw_writel(BM_SSP_CTRL1_SDIO_IRQ_EN, host->ssp_base + \
-			HW_SSP_CTRL1_CLR);
+	if ((c1 & BM_SSP_CTRL1_SDIO_IRQ) && (c1 & BM_SSP_CTRL1_SDIO_IRQ_EN))
 		mmc_signal_sdio_irq(host->mmc);
-	}
+
 	return IRQ_HANDLED;
 }
 
@@ -239,6 +243,7 @@ static void mxs_mmc_bc(struct mxs_mmc_host *host)
 {
 	struct mmc_command *cmd = host->cmd;
 	struct mxs_dma_desc *dma_desc = host->dma_desc;
+	unsigned long flags;
 
 	dma_desc->cmd.cmd.bits.command = NO_DMA_XFER;
 	dma_desc->cmd.cmd.bits.irq = 1;
@@ -255,7 +260,8 @@ static void mxs_mmc_bc(struct mxs_mmc_host *host)
 
 	if (host->sdio_irq_en) {
 		dma_desc->cmd.pio_words[0] |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
-		dma_desc->cmd.pio_words[1] |= BM_SSP_CMD0_CONT_CLKING_EN;
+		dma_desc->cmd.pio_words[1] |= BM_SSP_CMD0_CONT_CLKING_EN \
+			| BM_SSP_CMD0_SLOW_CLKING_EN;
 	}
 
 	init_completion(&host->dma_done);
@@ -265,6 +271,7 @@ static void mxs_mmc_bc(struct mxs_mmc_host *host)
 	dev_dbg(host->dev, "%s start DMA.\n", __func__);
 	if (mxs_dma_enable(host->dmach) < 0)
 		dev_err(host->dev, "mmc_dma_enable failed\n");
+
 	wait_for_completion(&host->dma_done);
 
 	cmd->error = mxs_mmc_cmd_error(host->status);
@@ -273,6 +280,7 @@ static void mxs_mmc_bc(struct mxs_mmc_host *host)
 		dev_dbg(host->dev, "Command error 0x%x\n", cmd->error);
 		mxs_dma_reset(host->dmach);
 	}
+	mxs_dma_disable(host->dmach);
 }
 
 /* Send the ac command to the device */
@@ -284,6 +292,7 @@ static void mxs_mmc_ac(struct mxs_mmc_host *host)
 	u32 ssp_ctrl0;
 	u32 ssp_cmd0;
 	u32 ssp_cmd1;
+	unsigned long flags;
 
 	ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
 	    0 : BM_SSP_CTRL0_IGNORE_CRC;
@@ -305,7 +314,8 @@ static void mxs_mmc_ac(struct mxs_mmc_host *host)
 
 	if (host->sdio_irq_en) {
 		ssp_ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
-		ssp_cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN;
+		ssp_cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN \
+			| BM_SSP_CMD0_SLOW_CLKING_EN;
 	}
 
 	dma_desc->cmd.pio_words[0] = ssp_ctrl0;
@@ -356,6 +366,7 @@ static void mxs_mmc_ac(struct mxs_mmc_host *host)
 		dev_dbg(host->dev, "Command error 0x%x\n", cmd->error);
 		mxs_dma_reset(host->dmach);
 	}
+	mxs_dma_disable(host->dmach);
 }
 
 /* Copy data between sg list and dma buffer */
@@ -451,6 +462,7 @@ static void mxs_mmc_adtc(struct mxs_mmc_host *host)
 
 	u32 data_size = cmd->data->blksz * cmd->data->blocks;
 	u32 log2_block_size;
+	unsigned long flags;
 
 	ignore_crc = mmc_resp_type(cmd) & MMC_RSP_CRC ? 0 : 1;
 	resp = mmc_resp_type(cmd) & MMC_RSP_PRESENT ? 1 : 0;
@@ -551,17 +563,25 @@ static void mxs_mmc_adtc(struct mxs_mmc_host *host)
 		}
 		/* Configure the CMD0 */
 		ssp_cmd0 = BF(cmd->opcode, SSP_CMD0_CMD);
-	} else
-		ssp_cmd0 =
-		    BF(log2_block_size, SSP_BLOCK_SIZE_BLOCK_SIZE) |
-		    BF(cmd->opcode, SSP_CMD0_CMD) |
-		    BF(cmd->data->blocks - 1, SSP_BLOCK_SIZE_BLOCK_COUNT);
-
+	} else {
+		if ((1<<log2_block_size) != cmd->data->blksz) {
+			BUG_ON(cmd->data->blocks > 1);
+			ssp_cmd0 =
+				BF(0, SSP_BLOCK_SIZE_BLOCK_SIZE) |
+				BF(cmd->opcode, SSP_CMD0_CMD) |
+				BF(0, SSP_BLOCK_SIZE_BLOCK_COUNT);
+		} else
+			ssp_cmd0 =
+			BF(log2_block_size, SSP_BLOCK_SIZE_BLOCK_SIZE) |
+			BF(cmd->opcode, SSP_CMD0_CMD) |
+			BF(cmd->data->blocks - 1, SSP_BLOCK_SIZE_BLOCK_COUNT);
+	}
 	if (host->sdio_irq_en) {
 		ssp_ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
-		ssp_cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN;
+		ssp_cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN \
+			| BM_SSP_CMD0_SLOW_CLKING_EN;
 	}
-	if (cmd->opcode == 12)
+	if ((cmd->opcode == 12) || (cmd->opcode == 53))
 		ssp_cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
 
 	ssp_cmd1 = BF(cmd->arg, SSP_CMD1_CMD_ARG);
@@ -628,6 +648,7 @@ static void mxs_mmc_adtc(struct mxs_mmc_host *host)
 		dev_dbg(host->dev, "Transferred %u bytes\n",
 			cmd->data->bytes_xfered);
 	}
+	mxs_dma_disable(host->dmach);
 }
 
 /* Begin sedning a command to the card */
@@ -672,6 +693,13 @@ static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 
 	dev_dbg(host->dev, "MMC request\n");
 
+	if (!host->present) {
+		mrq->cmd->error = -ETIMEDOUT;
+		mmc_request_done(mmc, mrq);
+		return;
+	}
+
+	BUG_ON(host->mrq != NULL);
 	host->mrq = mrq;
 
 	mxs_mmc_start_cmd(host, mrq->cmd);
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index e55ac792d68c..c8c0a7e4f0af 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -694,14 +694,14 @@ static int pxamci_remove(struct platform_device *pdev)
 	if (mmc) {
 		struct pxamci_host *host = mmc_priv(mmc);
 
+		mmc_remove_host(mmc);
+
 		if (host->vcc)
 			regulator_put(host->vcc);
 
 		if (host->pdata && host->pdata->exit)
 			host->pdata->exit(&pdev->dev, mmc);
 
-		mmc_remove_host(mmc);
-
 		pxamci_stop_clock(host);
 		writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
 		       END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
index 61ea833e0908..94bb61e19047 100644
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -282,16 +282,6 @@ static void fixup_s29gl032n_sectors(struct mtd_info *mtd, void *param)
 	}
 }
 
-static void fixup_M29W128G_write_buffer(struct mtd_info *mtd, void *param)
-{
-	struct map_info *map = mtd->priv;
-	struct cfi_private *cfi = map->fldrv_priv;
-	if (cfi->cfiq->BufWriteTimeoutTyp) {
-		pr_warning("Don't use write buffer on ST flash M29W128G\n");
-		cfi->cfiq->BufWriteTimeoutTyp = 0;
-	}
-}
-
 static struct cfi_fixup cfi_fixup_table[] = {
 	{ CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
 #ifdef AMD_BOOTLOC_BUG
@@ -308,7 +298,6 @@ static struct cfi_fixup cfi_fixup_table[] = {
 	{ CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors, NULL, },
 	{ CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors, NULL, },
 	{ CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors, NULL, },
-	{ CFI_MFR_ST,  0x227E, fixup_M29W128G_write_buffer, NULL, },
 #if !FORCE_WORD_WRITE
 	{ CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
 #endif
diff --git a/drivers/mtd/chips/cfi_util.c b/drivers/mtd/chips/cfi_util.c
index 34d40e25d312..c5a84fda5410 100644
--- a/drivers/mtd/chips/cfi_util.c
+++ b/drivers/mtd/chips/cfi_util.c
@@ -81,6 +81,10 @@ void __xipram cfi_qry_mode_off(uint32_t base, struct map_info *map,
 {
 	cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL);
 	cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL);
+	/* M29W128G flashes require an additional reset command
+	   when exit qry mode */
+	if ((cfi->mfr == CFI_MFR_ST) && (cfi->id == 0x227E || cfi->id == 0x7E))
+		cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL);
 }
 EXPORT_SYMBOL_GPL(cfi_qry_mode_off);
 
diff --git a/drivers/mtd/devices/mxc_dataflash.c b/drivers/mtd/devices/mxc_dataflash.c
index ab75d743a05b..0ed701d6778c 100644
--- a/drivers/mtd/devices/mxc_dataflash.c
+++ b/drivers/mtd/devices/mxc_dataflash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  * (c) 2005 MontaVista Software, Inc.
  *
  * This code is based on mtd_dataflash.c by adding FSL spi access.
@@ -22,10 +22,10 @@
 #include <linux/err.h>
 
 #include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <asm/mach/flash.h>
 
 /*
  * DataFlash is a kind of SPI flash.  Most AT45 chips have two buffers in
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 8f1eebf8d3b3..3fe91622b400 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -434,49 +434,9 @@ config MXC_NAND_LOW_LEVEL_ERASE
 	  This enables the erase of whole NAND flash. By
 	  default low level erase operation is disabled.
 
-config MTD_NAND_GPMI_LBA
-	tristate "GPMI LBA NAND driver"
-	depends on MTD_NAND && ARCH_STMP3XXX
-	help
-	 Enables support of LBA devices on GPMI on 37xx/378x SigmaTel
-	 boards
-
-config MTD_NAND_GPMI
-	tristate "GPMI NAND driver"
-	depends on MTD_NAND && ARCH_STMP3XXX && !MTD_NAND_GPMI_LBA
-	help
-	 Enables support of NAND devices on GPMI on 37xx/378x SigmaTel
-	 boards
-
-config MTD_NAND_GPMI_SYSFS_ENTRIES
-	bool "Create /sys entries for GPMI device"
-	depends on MTD_NAND_GPMI
-	help
-	  Check this to enable /sys entries for GPMI devices
-
-config MTD_NAND_GPMI_BCH
-	bool "Enable BCH HWECC"
-	depends on MTD_NAND_GPMI
-	depends on ARCH_STMP378X
-	default y
-	help
-	  Check this to enable /sys entries for GPMI devices
-
-config MTD_NAND_GPMI_TA1
-	bool "Support for TA1 NCB format (Hamming code 22,16)"
-	depends on MTD_NAND_GPMI
-	depends on ARCH_STMP378X
-	default y
-
-config MTD_NAND_GPMI_TA3
-	bool "Support for TA3 NCB format (Hamming code 13,8)"
-	depends on MTD_NAND_GPMI
-	depends on ARCH_STMP378X
-	default y
-
-config MTD_NAND_GPMI1
-        tristate "GPMI NAND Flash driver"
-        depends on MTD_NAND && ARCH_MX28
+config MTD_NAND_GPMI_NFC
+        tristate "GPMI NAND Flash Controller driver"
+        depends on MTD_NAND && (ARCH_MX23 || ARCH_MX28)
         help
          Enables NAND Flash support.
 
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 730f5db16e1d..2245a8df441b 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -41,9 +41,7 @@ obj-$(CONFIG_MTD_NAND_IMX_NFC)		+= imx_nfc.o
 obj-$(CONFIG_MTD_NAND_MXC)		+= mxc_nand.o
 obj-$(CONFIG_MTD_NAND_MXC_V2)		+= mxc_nd2.o nand_device_info.o
 obj-$(CONFIG_MTD_NAND_MXC_V3)		+= mxc_nd2.o nand_device_info.o
-obj-$(CONFIG_MTD_NAND_GPMI)		+= gpmi/ nand_device_info.o
-obj-$(CONFIG_MTD_NAND_GPMI1)		+= gpmi1/ nand_device_info.o
-obj-$(CONFIG_MTD_NAND_GPMI_LBA)		+= lba/
+obj-$(CONFIG_MTD_NAND_GPMI_NFC)		+= gpmi-nfc/ nand_device_info.o
 obj-$(CONFIG_MTD_NAND_SOCRATES)		+= socrates_nand.o
 obj-$(CONFIG_MTD_NAND_TXX9NDFMC)	+= txx9ndfmc.o
 
diff --git a/drivers/mtd/nand/gpmi-nfc/Makefile b/drivers/mtd/nand/gpmi-nfc/Makefile
new file mode 100644
index 000000000000..e3d5660735b6
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/Makefile
@@ -0,0 +1,10 @@
+obj-$(CONFIG_MTD_NAND_GPMI_NFC) += gpmi-nfc.o
+gpmi-nfc-objs += gpmi-nfc-main.o
+gpmi-nfc-objs += gpmi-nfc-event-reporting.o
+gpmi-nfc-objs += gpmi-nfc-hal-common.o
+gpmi-nfc-objs += gpmi-nfc-hal-v0.o
+gpmi-nfc-objs += gpmi-nfc-hal-v1.o
+gpmi-nfc-objs += gpmi-nfc-rom-common.o
+gpmi-nfc-objs += gpmi-nfc-rom-v0.o
+gpmi-nfc-objs += gpmi-nfc-rom-v1.o
+gpmi-nfc-objs += gpmi-nfc-mil.o
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h
new file mode 100644
index 000000000000..9af4feb29021
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h
@@ -0,0 +1,550 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __GPMI_NFC_BCH_REGS_H
+#define __GPMI_NFC_BCH_REGS_H
+
+/*============================================================================*/
+
+#define HW_BCH_CTRL	(0x00000000)
+#define HW_BCH_CTRL_SET	(0x00000004)
+#define HW_BCH_CTRL_CLR	(0x00000008)
+#define HW_BCH_CTRL_TOG	(0x0000000c)
+
+#define BM_BCH_CTRL_SFTRST	0x80000000
+#define BV_BCH_CTRL_SFTRST__RUN   0x0
+#define BV_BCH_CTRL_SFTRST__RESET 0x1
+#define BM_BCH_CTRL_CLKGATE	0x40000000
+#define BV_BCH_CTRL_CLKGATE__RUN     0x0
+#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1
+#define BP_BCH_CTRL_RSVD5	23
+#define BM_BCH_CTRL_RSVD5	0x3F800000
+#define BF_BCH_CTRL_RSVD5(v) (((v) << 23) & BM_BCH_CTRL_RSVD5)
+#define BM_BCH_CTRL_DEBUGSYNDROME	0x00400000
+#define BP_BCH_CTRL_RSVD4	20
+#define BM_BCH_CTRL_RSVD4	0x00300000
+#define BF_BCH_CTRL_RSVD4(v) (((v) << 20) & BM_BCH_CTRL_RSVD4)
+#define BP_BCH_CTRL_M2M_LAYOUT	18
+#define BM_BCH_CTRL_M2M_LAYOUT	0x000C0000
+#define BF_BCH_CTRL_M2M_LAYOUT(v) (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT)
+#define BM_BCH_CTRL_M2M_ENCODE	0x00020000
+#define BM_BCH_CTRL_M2M_ENABLE	0x00010000
+#define BP_BCH_CTRL_RSVD3	11
+#define BM_BCH_CTRL_RSVD3	0x0000F800
+#define BF_BCH_CTRL_RSVD3(v) (((v) << 11) & BM_BCH_CTRL_RSVD3)
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN	0x00000400
+#define BM_BCH_CTRL_RSVD2	0x00000200
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN	0x00000100
+#define BP_BCH_CTRL_RSVD1	4
+#define BM_BCH_CTRL_RSVD1	0x000000F0
+#define BF_BCH_CTRL_RSVD1(v) (((v) << 4) & BM_BCH_CTRL_RSVD1)
+#define BM_BCH_CTRL_BM_ERROR_IRQ	0x00000008
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ	0x00000004
+#define BM_BCH_CTRL_RSVD0	0x00000002
+#define BM_BCH_CTRL_COMPLETE_IRQ	0x00000001
+
+/*============================================================================*/
+
+#define HW_BCH_STATUS0	(0x00000010)
+
+#define BP_BCH_STATUS0_HANDLE	20
+#define BM_BCH_STATUS0_HANDLE	0xFFF00000
+#define BF_BCH_STATUS0_HANDLE(v) \
+		(((v) << 20) & BM_BCH_STATUS0_HANDLE)
+#define BP_BCH_STATUS0_COMPLETED_CE	16
+#define BM_BCH_STATUS0_COMPLETED_CE	0x000F0000
+#define BF_BCH_STATUS0_COMPLETED_CE(v)  \
+		(((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE)
+#define BP_BCH_STATUS0_STATUS_BLK0	8
+#define BM_BCH_STATUS0_STATUS_BLK0	0x0000FF00
+#define BF_BCH_STATUS0_STATUS_BLK0(v)  \
+		(((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0)
+#define BV_BCH_STATUS0_STATUS_BLK0__ZERO          0x00
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1        0x01
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2        0x02
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3        0x03
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4        0x04
+#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE
+#define BV_BCH_STATUS0_STATUS_BLK0__ERASED        0xFF
+#define BP_BCH_STATUS0_RSVD1	5
+#define BM_BCH_STATUS0_RSVD1	0x000000E0
+#define BF_BCH_STATUS0_RSVD1(v)  \
+		(((v) << 5) & BM_BCH_STATUS0_RSVD1)
+#define BM_BCH_STATUS0_ALLONES	0x00000010
+#define BM_BCH_STATUS0_CORRECTED	0x00000008
+#define BM_BCH_STATUS0_UNCORRECTABLE	0x00000004
+#define BP_BCH_STATUS0_RSVD0	0
+#define BM_BCH_STATUS0_RSVD0	0x00000003
+#define BF_BCH_STATUS0_RSVD0(v)  \
+		(((v) << 0) & BM_BCH_STATUS0_RSVD0)
+
+/*============================================================================*/
+
+#define HW_BCH_MODE	(0x00000020)
+
+#define BP_BCH_MODE_RSVD	8
+#define BM_BCH_MODE_RSVD	0xFFFFFF00
+#define BF_BCH_MODE_RSVD(v) \
+		(((v) << 8) & BM_BCH_MODE_RSVD)
+#define BP_BCH_MODE_ERASE_THRESHOLD	0
+#define BM_BCH_MODE_ERASE_THRESHOLD	0x000000FF
+#define BF_BCH_MODE_ERASE_THRESHOLD(v)  \
+		(((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD)
+
+/*============================================================================*/
+
+#define HW_BCH_ENCODEPTR	(0x00000030)
+
+#define BP_BCH_ENCODEPTR_ADDR	0
+#define BM_BCH_ENCODEPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_ENCODEPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DATAPTR	(0x00000040)
+
+#define BP_BCH_DATAPTR_ADDR	0
+#define BM_BCH_DATAPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_DATAPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_METAPTR	(0x00000050)
+
+#define BP_BCH_METAPTR_ADDR	0
+#define BM_BCH_METAPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_METAPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_LAYOUTSELECT	(0x00000070)
+
+#define BP_BCH_LAYOUTSELECT_CS15_SELECT	30
+#define BM_BCH_LAYOUTSELECT_CS15_SELECT	0xC0000000
+#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \
+		(((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS14_SELECT	28
+#define BM_BCH_LAYOUTSELECT_CS14_SELECT	0x30000000
+#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v)  \
+		(((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS13_SELECT	26
+#define BM_BCH_LAYOUTSELECT_CS13_SELECT	0x0C000000
+#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v)  \
+		(((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS12_SELECT	24
+#define BM_BCH_LAYOUTSELECT_CS12_SELECT	0x03000000
+#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v)  \
+		(((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS11_SELECT	22
+#define BM_BCH_LAYOUTSELECT_CS11_SELECT	0x00C00000
+#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v)  \
+		(((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS10_SELECT	20
+#define BM_BCH_LAYOUTSELECT_CS10_SELECT	0x00300000
+#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v)  \
+		(((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS9_SELECT	18
+#define BM_BCH_LAYOUTSELECT_CS9_SELECT	0x000C0000
+#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v)  \
+		(((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS8_SELECT	16
+#define BM_BCH_LAYOUTSELECT_CS8_SELECT	0x00030000
+#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v)  \
+		(((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS7_SELECT	14
+#define BM_BCH_LAYOUTSELECT_CS7_SELECT	0x0000C000
+#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v)  \
+		(((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS6_SELECT	12
+#define BM_BCH_LAYOUTSELECT_CS6_SELECT	0x00003000
+#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v)  \
+		(((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS5_SELECT	10
+#define BM_BCH_LAYOUTSELECT_CS5_SELECT	0x00000C00
+#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v)  \
+		(((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS4_SELECT	8
+#define BM_BCH_LAYOUTSELECT_CS4_SELECT	0x00000300
+#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v)  \
+		(((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS3_SELECT	6
+#define BM_BCH_LAYOUTSELECT_CS3_SELECT	0x000000C0
+#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v)  \
+		(((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS2_SELECT	4
+#define BM_BCH_LAYOUTSELECT_CS2_SELECT	0x00000030
+#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v)  \
+		(((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS1_SELECT	2
+#define BM_BCH_LAYOUTSELECT_CS1_SELECT	0x0000000C
+#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v)  \
+		(((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS0_SELECT	0
+#define BM_BCH_LAYOUTSELECT_CS0_SELECT	0x00000003
+#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v)  \
+		(((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT0	(0x00000080)
+
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH0LAYOUT0_ECC0	12
+#define BM_BCH_FLASH0LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH0LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0)
+#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT1	(0x00000090)
+
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH0LAYOUT1_ECCN	12
+#define BM_BCH_FLASH0LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH0LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN)
+#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT0	(0x000000a0)
+
+#define BP_BCH_FLASH1LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH1LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH1LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH1LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH1LAYOUT0_ECC0	12
+#define BM_BCH_FLASH1LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH1LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0)
+#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT1	(0x000000b0)
+
+#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH1LAYOUT1_ECCN	12
+#define BM_BCH_FLASH1LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH1LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN)
+#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT0	(0x000000c0)
+
+#define BP_BCH_FLASH2LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH2LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH2LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH2LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH2LAYOUT0_ECC0	12
+#define BM_BCH_FLASH2LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH2LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0)
+#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT1	(0x000000d0)
+
+#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH2LAYOUT1_ECCN	12
+#define BM_BCH_FLASH2LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH2LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN)
+#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT0	(0x000000e0)
+
+#define BP_BCH_FLASH3LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH3LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH3LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH3LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH3LAYOUT0_ECC0	12
+#define BM_BCH_FLASH3LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH3LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0)
+#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT1	(0x000000f0)
+
+#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH3LAYOUT1_ECCN	12
+#define BM_BCH_FLASH3LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH3LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN)
+#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_DEBUG0	(0x00000100)
+#define HW_BCH_DEBUG0_SET	(0x00000104)
+#define HW_BCH_DEBUG0_CLR	(0x00000108)
+#define HW_BCH_DEBUG0_TOG	(0x0000010c)
+
+#define BP_BCH_DEBUG0_RSVD1	27
+#define BM_BCH_DEBUG0_RSVD1	0xF8000000
+#define BF_BCH_DEBUG0_RSVD1(v) \
+		(((v) << 27) & BM_BCH_DEBUG0_RSVD1)
+#define BM_BCH_DEBUG0_ROM_BIST_ENABLE	0x04000000
+#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE	0x02000000
+#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL	16
+#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL	0x01FF0000
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)  \
+		(((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL)
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL    0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND	0x00008000
+#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG	0x00004000
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX  0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K	0x00002000
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_KICK	0x00001000
+#define BM_BCH_DEBUG0_KES_STANDALONE	0x00000800
+#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL    0x0
+#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_STEP	0x00000400
+#define BM_BCH_DEBUG0_KES_DEBUG_STALL	0x00000200
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT   0x1
+#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS	0x00000100
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL    0x0
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1
+#define BP_BCH_DEBUG0_RSVD0	6
+#define BM_BCH_DEBUG0_RSVD0	0x000000C0
+#define BF_BCH_DEBUG0_RSVD0(v)  \
+		(((v) << 6) & BM_BCH_DEBUG0_RSVD0)
+#define BP_BCH_DEBUG0_DEBUG_REG_SELECT	0
+#define BM_BCH_DEBUG0_DEBUG_REG_SELECT	0x0000003F
+#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v)  \
+		(((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGKESREAD	(0x00000110)
+
+#define BP_BCH_DBGKESREAD_VALUES	0
+#define BM_BCH_DBGKESREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGKESREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGCSFEREAD	(0x00000120)
+
+#define BP_BCH_DBGCSFEREAD_VALUES	0
+#define BM_BCH_DBGCSFEREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGCSFEREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGSYNDGENREAD	(0x00000130)
+
+#define BP_BCH_DBGSYNDGENREAD_VALUES	0
+#define BM_BCH_DBGSYNDGENREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGSYNDGENREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGAHBMREAD	(0x00000140)
+
+#define BP_BCH_DBGAHBMREAD_VALUES	0
+#define BM_BCH_DBGAHBMREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGAHBMREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_BLOCKNAME	(0x00000150)
+
+#define BP_BCH_BLOCKNAME_NAME	0
+#define BM_BCH_BLOCKNAME_NAME	0xFFFFFFFF
+#define BF_BCH_BLOCKNAME_NAME(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_VERSION	(0x00000160)
+
+#define BP_BCH_VERSION_MAJOR	24
+#define BM_BCH_VERSION_MAJOR	0xFF000000
+#define BF_BCH_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_BCH_VERSION_MAJOR)
+#define BP_BCH_VERSION_MINOR	16
+#define BM_BCH_VERSION_MINOR	0x00FF0000
+#define BF_BCH_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_BCH_VERSION_MINOR)
+#define BP_BCH_VERSION_STEP	0
+#define BM_BCH_VERSION_STEP	0x0000FFFF
+#define BF_BCH_VERSION_STEP(v)  \
+		(((v) << 0) & BM_BCH_VERSION_STEP)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h
new file mode 100644
index 000000000000..692db086de4d
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h
@@ -0,0 +1,557 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * Xml Revision: 2.5
+ * Template revision: 26195
+ */
+
+#ifndef __GPMI_NFC_BCH_REGS_H
+#define __GPMI_NFC_BCH_REGS_H
+
+/*============================================================================*/
+
+#define HW_BCH_CTRL	(0x00000000)
+#define HW_BCH_CTRL_SET	(0x00000004)
+#define HW_BCH_CTRL_CLR	(0x00000008)
+#define HW_BCH_CTRL_TOG	(0x0000000c)
+
+#define BM_BCH_CTRL_SFTRST	0x80000000
+#define BV_BCH_CTRL_SFTRST__RUN   0x0
+#define BV_BCH_CTRL_SFTRST__RESET 0x1
+#define BM_BCH_CTRL_CLKGATE	0x40000000
+#define BV_BCH_CTRL_CLKGATE__RUN     0x0
+#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1
+#define BP_BCH_CTRL_RSVD5	23
+#define BM_BCH_CTRL_RSVD5	0x3F800000
+#define BF_BCH_CTRL_RSVD5(v)  \
+		(((v) << 23) & BM_BCH_CTRL_RSVD5)
+#define BM_BCH_CTRL_DEBUGSYNDROME	0x00400000
+#define BP_BCH_CTRL_RSVD4	20
+#define BM_BCH_CTRL_RSVD4	0x00300000
+#define BF_BCH_CTRL_RSVD4(v)  \
+		(((v) << 20) & BM_BCH_CTRL_RSVD4)
+#define BP_BCH_CTRL_M2M_LAYOUT	18
+#define BM_BCH_CTRL_M2M_LAYOUT	0x000C0000
+#define BF_BCH_CTRL_M2M_LAYOUT(v)  \
+		(((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT)
+#define BM_BCH_CTRL_M2M_ENCODE	0x00020000
+#define BM_BCH_CTRL_M2M_ENABLE	0x00010000
+#define BP_BCH_CTRL_RSVD3	11
+#define BM_BCH_CTRL_RSVD3	0x0000F800
+#define BF_BCH_CTRL_RSVD3(v)  \
+		(((v) << 11) & BM_BCH_CTRL_RSVD3)
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN	0x00000400
+#define BM_BCH_CTRL_RSVD2	0x00000200
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN	0x00000100
+#define BP_BCH_CTRL_RSVD1	4
+#define BM_BCH_CTRL_RSVD1	0x000000F0
+#define BF_BCH_CTRL_RSVD1(v)  \
+		(((v) << 4) & BM_BCH_CTRL_RSVD1)
+#define BM_BCH_CTRL_BM_ERROR_IRQ	0x00000008
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ	0x00000004
+#define BM_BCH_CTRL_RSVD0	0x00000002
+#define BM_BCH_CTRL_COMPLETE_IRQ	0x00000001
+
+/*============================================================================*/
+
+#define HW_BCH_STATUS0	(0x00000010)
+
+#define BP_BCH_STATUS0_HANDLE	20
+#define BM_BCH_STATUS0_HANDLE	0xFFF00000
+#define BF_BCH_STATUS0_HANDLE(v) \
+		(((v) << 20) & BM_BCH_STATUS0_HANDLE)
+#define BP_BCH_STATUS0_COMPLETED_CE	16
+#define BM_BCH_STATUS0_COMPLETED_CE	0x000F0000
+#define BF_BCH_STATUS0_COMPLETED_CE(v)  \
+		(((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE)
+#define BP_BCH_STATUS0_STATUS_BLK0	8
+#define BM_BCH_STATUS0_STATUS_BLK0	0x0000FF00
+#define BF_BCH_STATUS0_STATUS_BLK0(v)  \
+		(((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0)
+#define BV_BCH_STATUS0_STATUS_BLK0__ZERO          0x00
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1        0x01
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2        0x02
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3        0x03
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4        0x04
+#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE
+#define BV_BCH_STATUS0_STATUS_BLK0__ERASED        0xFF
+#define BP_BCH_STATUS0_RSVD1	5
+#define BM_BCH_STATUS0_RSVD1	0x000000E0
+#define BF_BCH_STATUS0_RSVD1(v)  \
+		(((v) << 5) & BM_BCH_STATUS0_RSVD1)
+#define BM_BCH_STATUS0_ALLONES	0x00000010
+#define BM_BCH_STATUS0_CORRECTED	0x00000008
+#define BM_BCH_STATUS0_UNCORRECTABLE	0x00000004
+#define BP_BCH_STATUS0_RSVD0	0
+#define BM_BCH_STATUS0_RSVD0	0x00000003
+#define BF_BCH_STATUS0_RSVD0(v)  \
+		(((v) << 0) & BM_BCH_STATUS0_RSVD0)
+
+/*============================================================================*/
+
+#define HW_BCH_MODE	(0x00000020)
+
+#define BP_BCH_MODE_RSVD	8
+#define BM_BCH_MODE_RSVD	0xFFFFFF00
+#define BF_BCH_MODE_RSVD(v) \
+		(((v) << 8) & BM_BCH_MODE_RSVD)
+#define BP_BCH_MODE_ERASE_THRESHOLD	0
+#define BM_BCH_MODE_ERASE_THRESHOLD	0x000000FF
+#define BF_BCH_MODE_ERASE_THRESHOLD(v)  \
+		(((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD)
+
+/*============================================================================*/
+
+#define HW_BCH_ENCODEPTR	(0x00000030)
+
+#define BP_BCH_ENCODEPTR_ADDR	0
+#define BM_BCH_ENCODEPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_ENCODEPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DATAPTR	(0x00000040)
+
+#define BP_BCH_DATAPTR_ADDR	0
+#define BM_BCH_DATAPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_DATAPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_METAPTR	(0x00000050)
+
+#define BP_BCH_METAPTR_ADDR	0
+#define BM_BCH_METAPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_METAPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_LAYOUTSELECT	(0x00000070)
+
+#define BP_BCH_LAYOUTSELECT_CS15_SELECT	30
+#define BM_BCH_LAYOUTSELECT_CS15_SELECT	0xC0000000
+#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \
+		(((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS14_SELECT	28
+#define BM_BCH_LAYOUTSELECT_CS14_SELECT	0x30000000
+#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v)  \
+		(((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS13_SELECT	26
+#define BM_BCH_LAYOUTSELECT_CS13_SELECT	0x0C000000
+#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v)  \
+		(((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS12_SELECT	24
+#define BM_BCH_LAYOUTSELECT_CS12_SELECT	0x03000000
+#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v)  \
+		(((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS11_SELECT	22
+#define BM_BCH_LAYOUTSELECT_CS11_SELECT	0x00C00000
+#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v)  \
+		(((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS10_SELECT	20
+#define BM_BCH_LAYOUTSELECT_CS10_SELECT	0x00300000
+#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v)  \
+		(((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS9_SELECT	18
+#define BM_BCH_LAYOUTSELECT_CS9_SELECT	0x000C0000
+#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v)  \
+		(((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS8_SELECT	16
+#define BM_BCH_LAYOUTSELECT_CS8_SELECT	0x00030000
+#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v)  \
+		(((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS7_SELECT	14
+#define BM_BCH_LAYOUTSELECT_CS7_SELECT	0x0000C000
+#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v)  \
+		(((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS6_SELECT	12
+#define BM_BCH_LAYOUTSELECT_CS6_SELECT	0x00003000
+#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v)  \
+		(((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS5_SELECT	10
+#define BM_BCH_LAYOUTSELECT_CS5_SELECT	0x00000C00
+#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v)  \
+		(((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS4_SELECT	8
+#define BM_BCH_LAYOUTSELECT_CS4_SELECT	0x00000300
+#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v)  \
+		(((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS3_SELECT	6
+#define BM_BCH_LAYOUTSELECT_CS3_SELECT	0x000000C0
+#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v)  \
+		(((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS2_SELECT	4
+#define BM_BCH_LAYOUTSELECT_CS2_SELECT	0x00000030
+#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v)  \
+		(((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS1_SELECT	2
+#define BM_BCH_LAYOUTSELECT_CS1_SELECT	0x0000000C
+#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v)  \
+		(((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS0_SELECT	0
+#define BM_BCH_LAYOUTSELECT_CS0_SELECT	0x00000003
+#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v)  \
+		(((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT0	(0x00000080)
+
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH0LAYOUT0_ECC0	12
+#define BM_BCH_FLASH0LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH0LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0)
+#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT1	(0x00000090)
+
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH0LAYOUT1_ECCN	12
+#define BM_BCH_FLASH0LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH0LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN)
+#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT0	(0x000000a0)
+
+#define BP_BCH_FLASH1LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH1LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH1LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH1LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH1LAYOUT0_ECC0	12
+#define BM_BCH_FLASH1LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH1LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0)
+#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT1	(0x000000b0)
+
+#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH1LAYOUT1_ECCN	12
+#define BM_BCH_FLASH1LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH1LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN)
+#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT0	(0x000000c0)
+
+#define BP_BCH_FLASH2LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH2LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH2LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH2LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH2LAYOUT0_ECC0	12
+#define BM_BCH_FLASH2LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH2LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0)
+#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT1	(0x000000d0)
+
+#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH2LAYOUT1_ECCN	12
+#define BM_BCH_FLASH2LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH2LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN)
+#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT0	(0x000000e0)
+
+#define BP_BCH_FLASH3LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH3LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH3LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH3LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH3LAYOUT0_ECC0	12
+#define BM_BCH_FLASH3LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH3LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0)
+#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT1	(0x000000f0)
+
+#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH3LAYOUT1_ECCN	12
+#define BM_BCH_FLASH3LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH3LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN)
+#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_DEBUG0	(0x00000100)
+#define HW_BCH_DEBUG0_SET	(0x00000104)
+#define HW_BCH_DEBUG0_CLR	(0x00000108)
+#define HW_BCH_DEBUG0_TOG	(0x0000010c)
+
+#define BP_BCH_DEBUG0_RSVD1	27
+#define BM_BCH_DEBUG0_RSVD1	0xF8000000
+#define BF_BCH_DEBUG0_RSVD1(v) \
+		(((v) << 27) & BM_BCH_DEBUG0_RSVD1)
+#define BM_BCH_DEBUG0_ROM_BIST_ENABLE	0x04000000
+#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE	0x02000000
+#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL	16
+#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL	0x01FF0000
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)  \
+		(((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL)
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL    0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND	0x00008000
+#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG	0x00004000
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX  0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K	0x00002000
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_KICK	0x00001000
+#define BM_BCH_DEBUG0_KES_STANDALONE	0x00000800
+#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL    0x0
+#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_STEP	0x00000400
+#define BM_BCH_DEBUG0_KES_DEBUG_STALL	0x00000200
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT   0x1
+#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS	0x00000100
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL    0x0
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1
+#define BP_BCH_DEBUG0_RSVD0	6
+#define BM_BCH_DEBUG0_RSVD0	0x000000C0
+#define BF_BCH_DEBUG0_RSVD0(v)  \
+		(((v) << 6) & BM_BCH_DEBUG0_RSVD0)
+#define BP_BCH_DEBUG0_DEBUG_REG_SELECT	0
+#define BM_BCH_DEBUG0_DEBUG_REG_SELECT	0x0000003F
+#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v)  \
+		(((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGKESREAD	(0x00000110)
+
+#define BP_BCH_DBGKESREAD_VALUES	0
+#define BM_BCH_DBGKESREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGKESREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGCSFEREAD	(0x00000120)
+
+#define BP_BCH_DBGCSFEREAD_VALUES	0
+#define BM_BCH_DBGCSFEREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGCSFEREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGSYNDGENREAD	(0x00000130)
+
+#define BP_BCH_DBGSYNDGENREAD_VALUES	0
+#define BM_BCH_DBGSYNDGENREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGSYNDGENREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGAHBMREAD	(0x00000140)
+
+#define BP_BCH_DBGAHBMREAD_VALUES	0
+#define BM_BCH_DBGAHBMREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGAHBMREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_BLOCKNAME	(0x00000150)
+
+#define BP_BCH_BLOCKNAME_NAME	0
+#define BM_BCH_BLOCKNAME_NAME	0xFFFFFFFF
+#define BF_BCH_BLOCKNAME_NAME(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_VERSION	(0x00000160)
+
+#define BP_BCH_VERSION_MAJOR	24
+#define BM_BCH_VERSION_MAJOR	0xFF000000
+#define BF_BCH_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_BCH_VERSION_MAJOR)
+#define BP_BCH_VERSION_MINOR	16
+#define BM_BCH_VERSION_MINOR	0x00FF0000
+#define BF_BCH_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_BCH_VERSION_MINOR)
+#define BP_BCH_VERSION_STEP	0
+#define BM_BCH_VERSION_STEP	0x0000FFFF
+#define BF_BCH_VERSION_STEP(v)  \
+		(((v) << 0) & BM_BCH_VERSION_STEP)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-event-reporting.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-event-reporting.c
new file mode 100644
index 000000000000..45574391b0f0
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-event-reporting.c
@@ -0,0 +1,307 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+#if defined(EVENT_REPORTING)
+
+/*
+ * This variable and module parameter controls whether the driver reports event
+ * information by printing to the console.
+ */
+
+static int report_events;
+module_param(report_events, int, 0600);
+
+/**
+ * struct event - A single record in the event trace.
+ *
+ * @time:         The time at which the event occurred.
+ * @nesting:      Indicates function call nesting.
+ * @description:  A description of the event.
+ */
+
+struct event {
+	ktime_t       time;
+	unsigned int  nesting;
+	char          *description;
+};
+
+/**
+ * The event trace.
+ *
+ * @overhead:  The delay to take a time stamp and nothing else.
+ * @nesting:   The current nesting level.
+ * @overflow:  Indicates the trace overflowed.
+ * @next:      Index of the next event to write.
+ * @events:    The array of events.
+ */
+
+#define MAX_EVENT_COUNT  (200)
+
+static struct {
+	ktime_t       overhead;
+	int           nesting;
+	int           overflow;
+	unsigned int  next;
+	struct event  events[MAX_EVENT_COUNT];
+} event_trace;
+
+/**
+ * gpmi_nfc_reset_event_trace() - Resets the event trace.
+ */
+void gpmi_nfc_reset_event_trace(void)
+{
+	event_trace.nesting  = 0;
+	event_trace.overflow = false;
+	event_trace.next     = 0;
+}
+
+/**
+ * gpmi_nfc_add_event() - Adds an event to the event trace.
+ *
+ * @description:  A description of the event.
+ * @delta:        A delta to the nesting level for this event [-1, 0, 1].
+ */
+void gpmi_nfc_add_event(char *description, int delta)
+{
+	struct event  *event;
+
+	if (!report_events)
+		return;
+
+	if (event_trace.overflow)
+		return;
+
+	if (event_trace.next >= MAX_EVENT_COUNT) {
+		event_trace.overflow = true;
+		return;
+	}
+
+	event = event_trace.events + event_trace.next;
+
+	event->time = ktime_get();
+
+	event->description = description;
+
+	if (!delta)
+		event->nesting = event_trace.nesting;
+	else if (delta < 0) {
+		event->nesting = event_trace.nesting - 1;
+		event_trace.nesting -= 2;
+	} else {
+		event->nesting = event_trace.nesting + 1;
+		event_trace.nesting += 2;
+	}
+
+	if (event_trace.nesting < 0)
+		event_trace.nesting = 0;
+
+	event_trace.next++;
+
+}
+
+/**
+ * gpmi_nfc_start_event_trace() - Starts an event trace.
+ *
+ * @description:  A description of the first event.
+ */
+void gpmi_nfc_start_event_trace(char *description)
+{
+
+	ktime_t  t0;
+	ktime_t  t1;
+
+	if (!report_events)
+		return;
+
+	gpmi_nfc_reset_event_trace();
+
+	t0 = ktime_get();
+	t1 = ktime_get();
+
+	event_trace.overhead = ktime_sub(t1, t0);
+
+	gpmi_nfc_add_event(description, 1);
+
+}
+
+/**
+ * gpmi_nfc_dump_event_trace() - Dumps the event trace.
+ */
+void gpmi_nfc_dump_event_trace(void)
+{
+	unsigned int  i;
+	time_t        seconds;
+	long          nanoseconds;
+	char          line[100];
+	int           o;
+	struct event  *first_event;
+	struct event  *last_event;
+	struct event  *matching_event;
+	struct event  *event;
+	ktime_t       delta;
+
+	/* Check if event reporting is turned off. */
+
+	if (!report_events)
+		return;
+
+	/* Print important facts about this event trace. */
+
+	pr_info("\n+----------------\n");
+
+	pr_info("|  Overhead    : [%d:%d]\n", event_trace.overhead.tv.sec,
+						event_trace.overhead.tv.nsec);
+
+	if (!event_trace.next) {
+		pr_info("|  No Events\n");
+		return;
+	}
+
+	first_event = event_trace.events;
+	last_event  = event_trace.events + (event_trace.next - 1);
+
+	delta = ktime_sub(last_event->time, first_event->time);
+	pr_info("|  Elapsed Time: [%d:%d]\n", delta.tv.sec, delta.tv.nsec);
+
+	if (event_trace.overflow)
+		pr_info("|  Overflow!\n");
+
+	/* Print the events in this history. */
+
+	for (i = 0, event = event_trace.events;
+					i < event_trace.next; i++, event++) {
+
+		/* Get the delta between this event and the previous event. */
+
+		if (!i) {
+			seconds     = 0;
+			nanoseconds = 0;
+		} else {
+			delta = ktime_sub(event[0].time, event[-1].time);
+			seconds     = delta.tv.sec;
+			nanoseconds = delta.tv.nsec;
+		}
+
+		/* Print the current event. */
+
+		o = 0;
+
+		o = snprintf(line, sizeof(line) - o, "|  [%ld:% 10ld]%*s %s",
+							seconds, nanoseconds,
+							event->nesting, "",
+							event->description);
+		/* Check if this is the last event in a nested series. */
+
+		if (i && (event[0].nesting < event[-1].nesting)) {
+
+			for (matching_event = event - 1;; matching_event--) {
+
+				if (matching_event < event_trace.events) {
+					matching_event = 0;
+					break;
+				}
+
+				if (matching_event->nesting == event->nesting)
+					break;
+
+			}
+
+			if (matching_event) {
+				delta = ktime_sub(event->time,
+							matching_event->time);
+				o += snprintf(line + o, sizeof(line) - o,
+						" <%d:%d]", delta.tv.sec,
+								delta.tv.nsec);
+			}
+
+		}
+
+		/* Check if this is the first event in a nested series. */
+
+		if ((i < event_trace.next - 1) &&
+				(event[0].nesting < event[1].nesting)) {
+
+			for (matching_event = event + 1;; matching_event++) {
+
+				if (matching_event >=
+					(event_trace.events+event_trace.next)) {
+					matching_event = 0;
+					break;
+				}
+
+				if (matching_event->nesting == event->nesting)
+					break;
+
+			}
+
+			if (matching_event) {
+				delta = ktime_sub(matching_event->time,
+								event->time);
+				o += snprintf(line + o, sizeof(line) - o,
+						" [%d:%d>", delta.tv.sec,
+								delta.tv.nsec);
+			}
+
+		}
+
+		pr_info("%s\n", line);
+
+	}
+
+	pr_info("+----------------\n");
+
+}
+
+/**
+ * gpmi_nfc_stop_event_trace() - Stops an event trace.
+ *
+ * @description:  A description of the last event.
+ */
+void gpmi_nfc_stop_event_trace(char *description)
+{
+	struct event  *event;
+
+	if (!report_events)
+		return;
+
+	/*
+	 * We want the end of the trace, no matter what happens. If the trace
+	 * has already overflowed, or is about to, just jam this event into the
+	 * last spot. Otherwise, add this event like any other.
+	 */
+
+	if (event_trace.overflow || (event_trace.next >= MAX_EVENT_COUNT)) {
+		event = event_trace.events + (MAX_EVENT_COUNT - 1);
+		event->time = ktime_get();
+		event->description = description;
+		event->nesting     = 0;
+	} else {
+		gpmi_nfc_add_event(description, -1);
+	}
+
+	gpmi_nfc_dump_event_trace();
+	gpmi_nfc_reset_event_trace();
+
+}
+
+#endif /* EVENT_REPORTING */
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h
new file mode 100644
index 000000000000..2f9fce609a34
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h
@@ -0,0 +1,416 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __GPMI_NFC_GPMI_REGS_H
+#define __GPMI_NFC_GPMI_REGS_H
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL0      (0x00000000)
+#define HW_GPMI_CTRL0_SET  (0x00000004)
+#define HW_GPMI_CTRL0_CLR  (0x00000008)
+#define HW_GPMI_CTRL0_TOG  (0x0000000c)
+
+#define BM_GPMI_CTRL0_SFTRST	     0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN    0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET  0x1
+#define BM_GPMI_CTRL0_CLKGATE           0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN      0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS  0x1
+#define BM_GPMI_CTRL0_RUN        0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE  0x0
+#define BV_GPMI_CTRL0_RUN__BUSY  0x1
+#define BM_GPMI_CTRL0_DEV_IRQ_EN     0x10000000
+#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x08000000
+#define BM_GPMI_CTRL0_UDMA           0x04000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED  0x1
+#define BP_GPMI_CTRL0_COMMAND_MODE    24
+#define BM_GPMI_CTRL0_COMMAND_MODE    0x03000000
+#define BF_GPMI_CTRL0_COMMAND_MODE(v) \
+	(((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE)
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE            0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ             0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY   0x3
+#define BM_GPMI_CTRL0_WORD_LENGTH	   0x00800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT  0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT   0x1
+#define BM_GPMI_CTRL0_LOCK_CS            0x00400000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED  0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED   0x1
+#define BP_GPMI_CTRL0_CS     20
+#define BM_GPMI_CTRL0_CS     0x00300000
+#define BF_GPMI_CTRL0_CS(v)  (((v) << 20) & BM_GPMI_CTRL0_CS)
+#define BP_GPMI_CTRL0_ADDRESS	  17
+#define BM_GPMI_CTRL0_ADDRESS	  0x000E0000
+#define BF_GPMI_CTRL0_ADDRESS(v)  (((v) << 17) & BM_GPMI_CTRL0_ADDRESS)
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA  0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE   0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE   0x2
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT	  0x00010000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED  0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED   0x1
+#define BP_GPMI_CTRL0_XFER_COUNT    0
+#define BM_GPMI_CTRL0_XFER_COUNT    0x0000FFFF
+#define BF_GPMI_CTRL0_XFER_COUNT(v) \
+	(((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_COMPARE  (0x00000010)
+
+#define BP_GPMI_COMPARE_MASK	 16
+#define BM_GPMI_COMPARE_MASK	 0xFFFF0000
+#define BF_GPMI_COMPARE_MASK(v)  (((v) << 16) & BM_GPMI_COMPARE_MASK)
+#define BP_GPMI_COMPARE_REFERENCE    0
+#define BM_GPMI_COMPARE_REFERENCE    0x0000FFFF
+#define BF_GPMI_COMPARE_REFERENCE(v) \
+	(((v) << 0) & BM_GPMI_COMPARE_REFERENCE)
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCTRL  (0x00000020)
+#define HW_GPMI_ECCCTRL_SET  (0x00000024)
+#define HW_GPMI_ECCCTRL_CLR  (0x00000028)
+#define HW_GPMI_ECCCTRL_TOG  (0x0000002c)
+
+#define BP_GPMI_ECCCTRL_HANDLE	   16
+#define BM_GPMI_ECCCTRL_HANDLE	   0xFFFF0000
+#define BF_GPMI_ECCCTRL_HANDLE(v)  (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE)
+#define BM_GPMI_ECCCTRL_RSVD2  0x00008000
+#define BP_GPMI_ECCCTRL_ECC_CMD  13
+#define BM_GPMI_ECCCTRL_ECC_CMD  0x00006000
+#define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD)
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 0x3
+#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1
+#define BM_GPMI_ECCCTRL_ENABLE_ECC           0x00001000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE   0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE  0x0
+#define BP_GPMI_ECCCTRL_RSVD1      9
+#define BM_GPMI_ECCCTRL_RSVD1      0x00000E00
+#define BF_GPMI_ECCCTRL_RSVD1(v)   (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1)
+#define BP_GPMI_ECCCTRL_BUFFER_MASK	0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK	0x000001FF
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v)  \
+		(((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK)
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE    0x1FF
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY   0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7     0x080
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6     0x040
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5     0x020
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4     0x010
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3     0x008
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2     0x004
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1     0x002
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0     0x001
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCOUNT	(0x00000030)
+
+#define BP_GPMI_ECCCOUNT_RSVD2     16
+#define BM_GPMI_ECCCOUNT_RSVD2     0xFFFF0000
+#define BF_GPMI_ECCCOUNT_RSVD2(v)  (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2)
+#define BP_GPMI_ECCCOUNT_COUNT     0
+#define BM_GPMI_ECCCOUNT_COUNT     0x0000FFFF
+#define BF_GPMI_ECCCOUNT_COUNT(v)  (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_PAYLOAD	(0x00000040)
+
+#define BP_GPMI_PAYLOAD_ADDRESS	    2
+#define BM_GPMI_PAYLOAD_ADDRESS	    0xFFFFFFFC
+#define BF_GPMI_PAYLOAD_ADDRESS(v)  (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS)
+#define BP_GPMI_PAYLOAD_RSVD0     0
+#define BM_GPMI_PAYLOAD_RSVD0     0x00000003
+#define BF_GPMI_PAYLOAD_RSVD0(v)  (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_AUXILIARY	(0x00000050)
+
+#define BP_GPMI_AUXILIARY_ADDRESS    2
+#define BM_GPMI_AUXILIARY_ADDRESS    0xFFFFFFFC
+#define BF_GPMI_AUXILIARY_ADDRESS(v) \
+	(((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS)
+#define BP_GPMI_AUXILIARY_RSVD0     0
+#define BM_GPMI_AUXILIARY_RSVD0     0x00000003
+#define BF_GPMI_AUXILIARY_RSVD0(v)  (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL1  (0x00000060)
+#define HW_GPMI_CTRL1_SET  (0x00000064)
+#define HW_GPMI_CTRL1_CLR  (0x00000068)
+#define HW_GPMI_CTRL1_TOG  (0x0000006c)
+
+#define BP_GPMI_CTRL1_RSVD2	24
+#define BM_GPMI_CTRL1_RSVD2	0xFF000000
+#define BF_GPMI_CTRL1_RSVD2(v) \
+		(((v) << 24) & BM_GPMI_CTRL1_RSVD2)
+#define BM_GPMI_CTRL1_CE3_SEL	0x00800000
+#define BM_GPMI_CTRL1_CE2_SEL	0x00400000
+#define BM_GPMI_CTRL1_CE1_SEL	0x00200000
+#define BM_GPMI_CTRL1_CE0_SEL	0x00100000
+#define BM_GPMI_CTRL1_GANGED_RDYBUSY	0x00080000
+#define BM_GPMI_CTRL1_GPMI_MODE	0x00000001
+#define BP_GPMI_CTRL1_GPMI_MODE	0
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY	0x00000004
+#define BM_GPMI_CTRL1_DEV_RESET	0x00000008
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ	0x00000200
+#define BM_GPMI_CTRL1_DEV_IRQ	0x00000400
+#define BM_GPMI_CTRL1_RDN_DELAY	0x0000F000
+#define BP_GPMI_CTRL1_RDN_DELAY	12
+#define BM_GPMI_CTRL1_BCH_MODE	0x00040000
+#define BP_GPMI_CTRL1_DLL_ENABLE	17
+#define BM_GPMI_CTRL1_DLL_ENABLE	0x00020000
+#define BP_GPMI_CTRL1_HALF_PERIOD	16
+#define BM_GPMI_CTRL1_HALF_PERIOD	0x00010000
+#define BP_GPMI_CTRL1_RDN_DELAY	12
+#define BM_GPMI_CTRL1_RDN_DELAY	0x0000F000
+#define BF_GPMI_CTRL1_RDN_DELAY(v)  \
+		(((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY)
+#define BM_GPMI_CTRL1_DMA2ECC_MODE	0x00000800
+#define BM_GPMI_CTRL1_DEV_IRQ	0x00000400
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ	0x00000200
+#define BM_GPMI_CTRL1_BURST_EN	0x00000100
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3	0x00000080
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2	0x00000040
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1	0x00000020
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0	0x00000010
+#define BM_GPMI_CTRL1_DEV_RESET	0x00000008
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED  0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY	0x00000004
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW  0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
+#define BM_GPMI_CTRL1_CAMERA_MODE	0x00000002
+#define BM_GPMI_CTRL1_GPMI_MODE	0x00000001
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA  0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING0	(0x00000070)
+
+#define BP_GPMI_TIMING0_RSVD1	24
+#define BM_GPMI_TIMING0_RSVD1	0xFF000000
+#define BF_GPMI_TIMING0_RSVD1(v) \
+		(((v) << 24) & BM_GPMI_TIMING0_RSVD1)
+#define BP_GPMI_TIMING0_ADDRESS_SETUP	16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP	0x00FF0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)  \
+		(((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP)
+#define BP_GPMI_TIMING0_DATA_HOLD	8
+#define BM_GPMI_TIMING0_DATA_HOLD	0x0000FF00
+#define BF_GPMI_TIMING0_DATA_HOLD(v)  \
+		(((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD)
+#define BP_GPMI_TIMING0_DATA_SETUP	0
+#define BM_GPMI_TIMING0_DATA_SETUP	0x000000FF
+#define BF_GPMI_TIMING0_DATA_SETUP(v)  \
+		(((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING1	(0x00000080)
+
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT	16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT	0xFFFF0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \
+		(((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT)
+#define BP_GPMI_TIMING1_RSVD1	0
+#define BM_GPMI_TIMING1_RSVD1	0x0000FFFF
+#define BF_GPMI_TIMING1_RSVD1(v)  \
+		(((v) << 0) & BM_GPMI_TIMING1_RSVD1)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING2	(0x00000090)
+
+#define BP_GPMI_TIMING2_UDMA_TRP	24
+#define BM_GPMI_TIMING2_UDMA_TRP	0xFF000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v) \
+		(((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP)
+#define BP_GPMI_TIMING2_UDMA_ENV	16
+#define BM_GPMI_TIMING2_UDMA_ENV	0x00FF0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v)  \
+		(((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV)
+#define BP_GPMI_TIMING2_UDMA_HOLD	8
+#define BM_GPMI_TIMING2_UDMA_HOLD	0x0000FF00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v)  \
+		(((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD)
+#define BP_GPMI_TIMING2_UDMA_SETUP	0
+#define BM_GPMI_TIMING2_UDMA_SETUP	0x000000FF
+#define BF_GPMI_TIMING2_UDMA_SETUP(v)  \
+		(((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DATA	(0x000000a0)
+
+#define BP_GPMI_DATA_DATA	0
+#define BM_GPMI_DATA_DATA	0xFFFFFFFF
+#define BF_GPMI_DATA_DATA(v)	(v)
+
+/*============================================================================*/
+
+#define HW_GPMI_STAT	(0x000000b0)
+
+#define BM_GPMI_STAT_PRESENT	0x80000000
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE   0x1
+#define BP_GPMI_STAT_RSVD1	12
+#define BM_GPMI_STAT_RSVD1	0x7FFFF000
+#define BF_GPMI_STAT_RSVD1(v)  \
+		(((v) << 12) & BM_GPMI_STAT_RSVD1)
+#define BP_GPMI_STAT_RDY_TIMEOUT	8
+#define BM_GPMI_STAT_RDY_TIMEOUT	0x00000F00
+#define BF_GPMI_STAT_RDY_TIMEOUT(v)  \
+		(((v) << 8) & BM_GPMI_STAT_RDY_TIMEOUT)
+#define BM_GPMI_STAT_ATA_IRQ	0x00000080
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK	0x00000040
+#define BM_GPMI_STAT_FIFO_EMPTY	0x00000020
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY     0x1
+#define BM_GPMI_STAT_FIFO_FULL	0x00000010
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL     0x1
+#define BM_GPMI_STAT_DEV3_ERROR	0x00000008
+#define BM_GPMI_STAT_DEV2_ERROR	0x00000004
+#define BM_GPMI_STAT_DEV1_ERROR	0x00000002
+#define BM_GPMI_STAT_DEERROR	0x00000001
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG	(0x000000c0)
+
+#define BM_GPMI_DEBUG_READY3	0x80000000
+#define BM_GPMI_DEBUG_READY2	0x40000000
+#define BM_GPMI_DEBUG_READY1	0x20000000
+#define BM_GPMI_DEBUG_READY0	0x10000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3	0x08000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2	0x04000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1	0x02000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0	0x01000000
+#define BM_GPMI_DEBUG_SENSE3	0x00800000
+#define BM_GPMI_DEBUG_SENSE2	0x00400000
+#define BM_GPMI_DEBUG_SENSE1	0x00200000
+#define BM_GPMI_DEBUG_SENSE0	0x00100000
+#define BM_GPMI_DEBUG_DMAREQ3	0x00080000
+#define BM_GPMI_DEBUG_DMAREQ2	0x00040000
+#define BM_GPMI_DEBUG_DMAREQ1	0x00020000
+#define BM_GPMI_DEBUG_DMAREQ0	0x00010000
+#define BP_GPMI_DEBUG_CMD_END	12
+#define BM_GPMI_DEBUG_CMD_END	0x0000F000
+#define BF_GPMI_DEBUG_CMD_END(v)  \
+		(((v) << 12) & BM_GPMI_DEBUG_CMD_END)
+#define BP_GPMI_DEBUG_UDMA_STATE	8
+#define BM_GPMI_DEBUG_UDMA_STATE	0x00000F00
+#define BF_GPMI_DEBUG_UDMA_STATE(v)  \
+		(((v) << 8) & BM_GPMI_DEBUG_UDMA_STATE)
+#define BM_GPMI_DEBUG_BUSY	0x00000080
+#define BV_GPMI_DEBUG_BUSY__DISABLED 0x0
+#define BV_GPMI_DEBUG_BUSY__ENABLED  0x1
+#define BP_GPMI_DEBUG_PIN_STATE	4
+#define BM_GPMI_DEBUG_PIN_STATE	0x00000070
+#define BF_GPMI_DEBUG_PIN_STATE(v)  \
+		(((v) << 4) & BM_GPMI_DEBUG_PIN_STATE)
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE   0x0
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR   0x2
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL  0x3
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD  0x6
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE   0x7
+#define BP_GPMI_DEBUG_MAIN_STATE	0
+#define BM_GPMI_DEBUG_MAIN_STATE	0x0000000F
+#define BF_GPMI_DEBUG_MAIN_STATE(v)  \
+		(((v) << 0) & BM_GPMI_DEBUG_MAIN_STATE)
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE   0x0
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP  0x9
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE   0xA
+
+/*============================================================================*/
+
+#define HW_GPMI_VERSION	(0x000000d0)
+
+#define BP_GPMI_VERSION_MAJOR     24
+#define BM_GPMI_VERSION_MAJOR     0xFF000000
+#define BF_GPMI_VERSION_MAJOR(v)  (((v) << 24) & BM_GPMI_VERSION_MAJOR)
+#define BP_GPMI_VERSION_MINOR     16
+#define BM_GPMI_VERSION_MINOR     0x00FF0000
+#define BF_GPMI_VERSION_MINOR(v)  (((v) << 16) & BM_GPMI_VERSION_MINOR)
+#define BP_GPMI_VERSION_STEP      0
+#define BM_GPMI_VERSION_STEP      0x0000FFFF
+#define BF_GPMI_VERSION_STEP(v)   (((v) << 0) & BM_GPMI_VERSION_STEP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG2       (0x000000e0)
+
+#define BP_GPMI_DEBUG2_RSVD1	16
+#define BM_GPMI_DEBUG2_RSVD1	0xFFFF0000
+#define BF_GPMI_DEBUG2_RSVD1(v)	(((v) << 16) & BM_GPMI_DEBUG2_RSVD1)
+#define BP_GPMI_DEBUG2_SYND2GPMI_BE	12
+#define BM_GPMI_DEBUG2_SYND2GPMI_BE	0x0000F000
+#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v)  \
+		(((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE)
+#define BM_GPMI_DEBUG2_GPMI2SYND_VALID	0x00000800
+#define BM_GPMI_DEBUG2_GPMI2SYND_READY	0x00000400
+#define BM_GPMI_DEBUG2_SYND2GPMI_VALID	0x00000200
+#define BM_GPMI_DEBUG2_SYND2GPMI_READY	0x00000100
+#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN	0x00000080
+#define BM_GPMI_DEBUG2_UPDATE_WINDOW	0x00000040
+#define BP_GPMI_DEBUG2_RDN_TAP     0
+#define BM_GPMI_DEBUG2_RDN_TAP     0x0000003F
+#define BF_GPMI_DEBUG2_RDN_TAP(v)  (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG3       (0x000000f0)
+
+#define BP_GPMI_DEBUG3_APB_WORD_CNTR	16
+#define BM_GPMI_DEBUG3_APB_WORD_CNTR	0xFFFF0000
+#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \
+		(((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR)
+#define BP_GPMI_DEBUG3_DEV_WORD_CNTR	0
+#define BM_GPMI_DEBUG3_DEV_WORD_CNTR	0x0000FFFF
+#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v)  \
+		(((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR)
+
+/*============================================================================*/
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h
new file mode 100644
index 000000000000..dcb3b7d3fc88
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h
@@ -0,0 +1,421 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * Xml Revision: 2.2
+ * Template revision: 26195
+ */
+
+#ifndef __GPMI_NFC_GPMI_REGS_H
+#define __GPMI_NFC_GPMI_REGS_H
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL0	(0x00000000)
+#define HW_GPMI_CTRL0_SET	(0x00000004)
+#define HW_GPMI_CTRL0_CLR	(0x00000008)
+#define HW_GPMI_CTRL0_TOG	(0x0000000c)
+
+#define BM_GPMI_CTRL0_SFTRST	0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN   0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET 0x1
+#define BM_GPMI_CTRL0_CLKGATE	0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN     0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1
+#define BM_GPMI_CTRL0_RUN	0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE 0x0
+#define BV_GPMI_CTRL0_RUN__BUSY 0x1
+#define BM_GPMI_CTRL0_DEV_IRQ_EN	0x10000000
+#define BM_GPMI_CTRL0_LOCK_CS	0x08000000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED  0x1
+#define BM_GPMI_CTRL0_UDMA	0x04000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED  0x1
+#define BP_GPMI_CTRL0_COMMAND_MODE	24
+#define BM_GPMI_CTRL0_COMMAND_MODE	0x03000000
+#define BF_GPMI_CTRL0_COMMAND_MODE(v)  \
+		(((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE)
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE            0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ             0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY   0x3
+#define BM_GPMI_CTRL0_WORD_LENGTH	0x00800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT  0x1
+#define BP_GPMI_CTRL0_CS	20
+#define BM_GPMI_CTRL0_CS	0x00700000
+#define BF_GPMI_CTRL0_CS(v)  \
+		(((v) << 20) & BM_GPMI_CTRL0_CS)
+#define BP_GPMI_CTRL0_ADDRESS	17
+#define BM_GPMI_CTRL0_ADDRESS	0x000E0000
+#define BF_GPMI_CTRL0_ADDRESS(v)  \
+		(((v) << 17) & BM_GPMI_CTRL0_ADDRESS)
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE  0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE  0x2
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT	0x00010000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED  0x1
+#define BP_GPMI_CTRL0_XFER_COUNT	0
+#define BM_GPMI_CTRL0_XFER_COUNT	0x0000FFFF
+#define BF_GPMI_CTRL0_XFER_COUNT(v)  \
+		(((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_COMPARE	(0x00000010)
+
+#define BP_GPMI_COMPARE_MASK	16
+#define BM_GPMI_COMPARE_MASK	0xFFFF0000
+#define BF_GPMI_COMPARE_MASK(v) \
+		(((v) << 16) & BM_GPMI_COMPARE_MASK)
+#define BP_GPMI_COMPARE_REFERENCE	0
+#define BM_GPMI_COMPARE_REFERENCE	0x0000FFFF
+#define BF_GPMI_COMPARE_REFERENCE(v)  \
+		(((v) << 0) & BM_GPMI_COMPARE_REFERENCE)
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCTRL	(0x00000020)
+#define HW_GPMI_ECCCTRL_SET	(0x00000024)
+#define HW_GPMI_ECCCTRL_CLR	(0x00000028)
+#define HW_GPMI_ECCCTRL_TOG	(0x0000002c)
+
+#define BP_GPMI_ECCCTRL_HANDLE	16
+#define BM_GPMI_ECCCTRL_HANDLE	0xFFFF0000
+#define BF_GPMI_ECCCTRL_HANDLE(v) \
+		(((v) << 16) & BM_GPMI_ECCCTRL_HANDLE)
+#define BM_GPMI_ECCCTRL_RSVD2	0x00008000
+#define BP_GPMI_ECCCTRL_ECC_CMD	13
+#define BM_GPMI_ECCCTRL_ECC_CMD	0x00006000
+#define BF_GPMI_ECCCTRL_ECC_CMD(v)  \
+		(((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD)
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE   0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE   0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE2 0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE3 0x3
+#define BM_GPMI_ECCCTRL_ENABLE_ECC	0x00001000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE  0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0
+#define BP_GPMI_ECCCTRL_RSVD1	9
+#define BM_GPMI_ECCCTRL_RSVD1	0x00000E00
+#define BF_GPMI_ECCCTRL_RSVD1(v)  \
+		(((v) << 9) & BM_GPMI_ECCCTRL_RSVD1)
+#define BP_GPMI_ECCCTRL_BUFFER_MASK	0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK	0x000001FF
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v)  \
+		(((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK)
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE    0x1FF
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCOUNT	(0x00000030)
+
+#define BP_GPMI_ECCCOUNT_RSVD2	16
+#define BM_GPMI_ECCCOUNT_RSVD2	0xFFFF0000
+#define BF_GPMI_ECCCOUNT_RSVD2(v) \
+		(((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2)
+#define BP_GPMI_ECCCOUNT_COUNT	0
+#define BM_GPMI_ECCCOUNT_COUNT	0x0000FFFF
+#define BF_GPMI_ECCCOUNT_COUNT(v)  \
+		(((v) << 0) & BM_GPMI_ECCCOUNT_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_PAYLOAD	(0x00000040)
+
+#define BP_GPMI_PAYLOAD_ADDRESS	2
+#define BM_GPMI_PAYLOAD_ADDRESS	0xFFFFFFFC
+#define BF_GPMI_PAYLOAD_ADDRESS(v) \
+		(((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS)
+#define BP_GPMI_PAYLOAD_RSVD0	0
+#define BM_GPMI_PAYLOAD_RSVD0	0x00000003
+#define BF_GPMI_PAYLOAD_RSVD0(v)  \
+		(((v) << 0) & BM_GPMI_PAYLOAD_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_AUXILIARY	(0x00000050)
+
+#define BP_GPMI_AUXILIARY_ADDRESS	2
+#define BM_GPMI_AUXILIARY_ADDRESS	0xFFFFFFFC
+#define BF_GPMI_AUXILIARY_ADDRESS(v) \
+		(((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS)
+#define BP_GPMI_AUXILIARY_RSVD0	0
+#define BM_GPMI_AUXILIARY_RSVD0	0x00000003
+#define BF_GPMI_AUXILIARY_RSVD0(v)  \
+		(((v) << 0) & BM_GPMI_AUXILIARY_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL1	(0x00000060)
+#define HW_GPMI_CTRL1_SET	(0x00000064)
+#define HW_GPMI_CTRL1_CLR	(0x00000068)
+#define HW_GPMI_CTRL1_TOG	(0x0000006c)
+
+#define BP_GPMI_CTRL1_RSVD2	25
+#define BM_GPMI_CTRL1_RSVD2	0xFE000000
+#define BF_GPMI_CTRL1_RSVD2(v) \
+		(((v) << 25) & BM_GPMI_CTRL1_RSVD2)
+#define BM_GPMI_CTRL1_DECOUPLE_CS	0x01000000
+#define BP_GPMI_CTRL1_WRN_DLY_SEL	22
+#define BM_GPMI_CTRL1_WRN_DLY_SEL	0x00C00000
+#define BF_GPMI_CTRL1_WRN_DLY_SEL(v)  \
+		(((v) << 22) & BM_GPMI_CTRL1_WRN_DLY_SEL)
+#define BM_GPMI_CTRL1_RSVD1	0x00200000
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN	0x00100000
+#define BM_GPMI_CTRL1_GANGED_RDYBUSY	0x00080000
+#define BM_GPMI_CTRL1_BCH_MODE	0x00040000
+#define BP_GPMI_CTRL1_DLL_ENABLE	17
+#define BM_GPMI_CTRL1_DLL_ENABLE	0x00020000
+#define BP_GPMI_CTRL1_HALF_PERIOD	16
+#define BM_GPMI_CTRL1_HALF_PERIOD	0x00010000
+#define BP_GPMI_CTRL1_RDN_DELAY	12
+#define BM_GPMI_CTRL1_RDN_DELAY	0x0000F000
+#define BF_GPMI_CTRL1_RDN_DELAY(v)  \
+		(((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY)
+#define BM_GPMI_CTRL1_DMA2ECC_MODE	0x00000800
+#define BM_GPMI_CTRL1_DEV_IRQ	0x00000400
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ	0x00000200
+#define BM_GPMI_CTRL1_BURST_EN	0x00000100
+#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST	0x00000080
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL	4
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL	0x00000070
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v)  \
+		(((v) << 4) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL)
+#define BM_GPMI_CTRL1_DEV_RESET	0x00000008
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED  0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY	0x00000004
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW  0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
+#define BM_GPMI_CTRL1_CAMERA_MODE	0x00000002
+#define BM_GPMI_CTRL1_GPMI_MODE	0x00000001
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA  0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING0	(0x00000070)
+
+#define BP_GPMI_TIMING0_RSVD1	24
+#define BM_GPMI_TIMING0_RSVD1	0xFF000000
+#define BF_GPMI_TIMING0_RSVD1(v) \
+		(((v) << 24) & BM_GPMI_TIMING0_RSVD1)
+#define BP_GPMI_TIMING0_ADDRESS_SETUP	16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP	0x00FF0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)  \
+		(((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP)
+#define BP_GPMI_TIMING0_DATA_HOLD	8
+#define BM_GPMI_TIMING0_DATA_HOLD	0x0000FF00
+#define BF_GPMI_TIMING0_DATA_HOLD(v)  \
+		(((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD)
+#define BP_GPMI_TIMING0_DATA_SETUP	0
+#define BM_GPMI_TIMING0_DATA_SETUP	0x000000FF
+#define BF_GPMI_TIMING0_DATA_SETUP(v)  \
+		(((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING1	(0x00000080)
+
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT	16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT	0xFFFF0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \
+		(((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT)
+#define BP_GPMI_TIMING1_RSVD1	0
+#define BM_GPMI_TIMING1_RSVD1	0x0000FFFF
+#define BF_GPMI_TIMING1_RSVD1(v)  \
+		(((v) << 0) & BM_GPMI_TIMING1_RSVD1)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING2	(0x00000090)
+
+#define BP_GPMI_TIMING2_UDMA_TRP	24
+#define BM_GPMI_TIMING2_UDMA_TRP	0xFF000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v) \
+		(((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP)
+#define BP_GPMI_TIMING2_UDMA_ENV	16
+#define BM_GPMI_TIMING2_UDMA_ENV	0x00FF0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v)  \
+		(((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV)
+#define BP_GPMI_TIMING2_UDMA_HOLD	8
+#define BM_GPMI_TIMING2_UDMA_HOLD	0x0000FF00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v)  \
+		(((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD)
+#define BP_GPMI_TIMING2_UDMA_SETUP	0
+#define BM_GPMI_TIMING2_UDMA_SETUP	0x000000FF
+#define BF_GPMI_TIMING2_UDMA_SETUP(v)  \
+		(((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DATA	(0x000000a0)
+
+#define BP_GPMI_DATA_DATA	0
+#define BM_GPMI_DATA_DATA	0xFFFFFFFF
+#define BF_GPMI_DATA_DATA(v)	(v)
+
+#define HW_GPMI_STAT	(0x000000b0)
+
+#define BP_GPMI_STAT_READY_BUSY	24
+#define BM_GPMI_STAT_READY_BUSY	0xFF000000
+#define BF_GPMI_STAT_READY_BUSY(v) \
+		(((v) << 24) & BM_GPMI_STAT_READY_BUSY)
+#define BP_GPMI_STAT_RDY_TIMEOUT	16
+#define BM_GPMI_STAT_RDY_TIMEOUT	0x00FF0000
+#define BF_GPMI_STAT_RDY_TIMEOUT(v)  \
+		(((v) << 16) & BM_GPMI_STAT_RDY_TIMEOUT)
+#define BM_GPMI_STAT_DEV7_ERROR	0x00008000
+#define BM_GPMI_STAT_DEV6_ERROR	0x00004000
+#define BM_GPMI_STAT_DEV5_ERROR	0x00002000
+#define BM_GPMI_STAT_DEV4_ERROR	0x00001000
+#define BM_GPMI_STAT_DEV3_ERROR	0x00000800
+#define BM_GPMI_STAT_DEV2_ERROR	0x00000400
+#define BM_GPMI_STAT_DEERROR	0x00000200
+#define BM_GPMI_STAT_DEV0_ERROR	0x00000100
+#define BP_GPMI_STAT_RSVD1	5
+#define BM_GPMI_STAT_RSVD1	0x000000E0
+#define BF_GPMI_STAT_RSVD1(v)  \
+		(((v) << 5) & BM_GPMI_STAT_RSVD1)
+#define BM_GPMI_STAT_ATA_IRQ	0x00000010
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK	0x00000008
+#define BM_GPMI_STAT_FIFO_EMPTY	0x00000004
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY     0x1
+#define BM_GPMI_STAT_FIFO_FULL	0x00000002
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL     0x1
+#define BM_GPMI_STAT_PRESENT	0x00000001
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE   0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG	(0x000000c0)
+
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END	24
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END	0xFF000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) \
+		(((v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END)
+#define BP_GPMI_DEBUG_DMA_SENSE	16
+#define BM_GPMI_DEBUG_DMA_SENSE	0x00FF0000
+#define BF_GPMI_DEBUG_DMA_SENSE(v)  \
+		(((v) << 16) & BM_GPMI_DEBUG_DMA_SENSE)
+#define BP_GPMI_DEBUG_DMAREQ	8
+#define BM_GPMI_DEBUG_DMAREQ	0x0000FF00
+#define BF_GPMI_DEBUG_DMAREQ(v)  \
+		(((v) << 8) & BM_GPMI_DEBUG_DMAREQ)
+#define BP_GPMI_DEBUG_CMD_END	0
+#define BM_GPMI_DEBUG_CMD_END	0x000000FF
+#define BF_GPMI_DEBUG_CMD_END(v)  \
+		(((v) << 0) & BM_GPMI_DEBUG_CMD_END)
+
+/*============================================================================*/
+
+#define HW_GPMI_VERSION	(0x000000d0)
+
+#define BP_GPMI_VERSION_MAJOR	24
+#define BM_GPMI_VERSION_MAJOR	0xFF000000
+#define BF_GPMI_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_GPMI_VERSION_MAJOR)
+#define BP_GPMI_VERSION_MINOR	16
+#define BM_GPMI_VERSION_MINOR	0x00FF0000
+#define BF_GPMI_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_GPMI_VERSION_MINOR)
+#define BP_GPMI_VERSION_STEP	0
+#define BM_GPMI_VERSION_STEP	0x0000FFFF
+#define BF_GPMI_VERSION_STEP(v)  \
+		(((v) << 0) & BM_GPMI_VERSION_STEP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG2	(0x000000e0)
+
+#define BP_GPMI_DEBUG2_RSVD1	28
+#define BM_GPMI_DEBUG2_RSVD1	0xF0000000
+#define BF_GPMI_DEBUG2_RSVD1(v) \
+		(((v) << 28) & BM_GPMI_DEBUG2_RSVD1)
+#define BP_GPMI_DEBUG2_UDMA_STATE	24
+#define BM_GPMI_DEBUG2_UDMA_STATE	0x0F000000
+#define BF_GPMI_DEBUG2_UDMA_STATE(v)  \
+		(((v) << 24) & BM_GPMI_DEBUG2_UDMA_STATE)
+#define BM_GPMI_DEBUG2_BUSY	0x00800000
+#define BV_GPMI_DEBUG2_BUSY__DISABLED 0x0
+#define BV_GPMI_DEBUG2_BUSY__ENABLED  0x1
+#define BP_GPMI_DEBUG2_PIN_STATE	20
+#define BM_GPMI_DEBUG2_PIN_STATE	0x00700000
+#define BF_GPMI_DEBUG2_PIN_STATE(v)  \
+		(((v) << 20) & BM_GPMI_DEBUG2_PIN_STATE)
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_IDLE   0x0
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ADDR   0x2
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STALL  0x3
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STROBE 0x4
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ATARDY 0x5
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DHOLD  0x6
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DONE   0x7
+#define BP_GPMI_DEBUG2_MAIN_STATE	16
+#define BM_GPMI_DEBUG2_MAIN_STATE	0x000F0000
+#define BF_GPMI_DEBUG2_MAIN_STATE(v)  \
+		(((v) << 16) & BM_GPMI_DEBUG2_MAIN_STATE)
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_IDLE   0x0
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFE 0x2
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFR 0x3
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAREQ 0x4
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAACK 0x5
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFF 0x6
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDFIFO 0x7
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDDMAR 0x8
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_RDCMP  0x9
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DONE   0xA
+#define BP_GPMI_DEBUG2_SYND2GPMI_BE	12
+#define BM_GPMI_DEBUG2_SYND2GPMI_BE	0x0000F000
+#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v)  \
+		(((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE)
+#define BM_GPMI_DEBUG2_GPMI2SYND_VALID	0x00000800
+#define BM_GPMI_DEBUG2_GPMI2SYND_READY	0x00000400
+#define BM_GPMI_DEBUG2_SYND2GPMI_VALID	0x00000200
+#define BM_GPMI_DEBUG2_SYND2GPMI_READY	0x00000100
+#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN	0x00000080
+#define BM_GPMI_DEBUG2_UPDATE_WINDOW	0x00000040
+#define BP_GPMI_DEBUG2_RDN_TAP	0
+#define BM_GPMI_DEBUG2_RDN_TAP	0x0000003F
+#define BF_GPMI_DEBUG2_RDN_TAP(v)  \
+		(((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG3	(0x000000f0)
+
+#define BP_GPMI_DEBUG3_APB_WORD_CNTR	16
+#define BM_GPMI_DEBUG3_APB_WORD_CNTR	0xFFFF0000
+#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \
+		(((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR)
+#define BP_GPMI_DEBUG3_DEV_WORD_CNTR	0
+#define BM_GPMI_DEBUG3_DEV_WORD_CNTR	0x0000FFFF
+#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v)  \
+		(((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c
new file mode 100644
index 000000000000..b38d653a21fd
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c
@@ -0,0 +1,1037 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+/**
+ * gpmi_nfc_bch_isr - BCH interrupt service routine.
+ *
+ * @interrupt_number:  The interrupt number.
+ * @cookie:            A cookie that contains a pointer to the owning device
+ *                     data structure.
+ */
+irqreturn_t gpmi_nfc_bch_isr(int irq, void *cookie)
+{
+	struct gpmi_nfc_data  *this      = cookie;
+	struct nfc_hal        *nfc       =  this->nfc;
+
+	gpmi_nfc_add_event("> gpmi_nfc_bch_isr", 1);
+
+	/* Clear the interrupt. */
+
+	nfc->clear_bch(this);
+
+	/* Release the base level. */
+
+	complete(&(nfc->bch_done));
+
+	/* Return success. */
+
+	gpmi_nfc_add_event("< gpmi_nfc_bch_isr", -1);
+
+	return IRQ_HANDLED;
+
+}
+
+/**
+ * gpmi_nfc_dma_isr - DMA interrupt service routine.
+ *
+ * @interrupt_number:  The interrupt number.
+ * @cookie:            A cookie that contains a pointer to the owning device
+ *                     data structure.
+ */
+irqreturn_t gpmi_nfc_dma_isr(int irq, void *cookie)
+{
+	struct gpmi_nfc_data  *this = cookie;
+	struct nfc_hal        *nfc  =  this->nfc;
+
+	gpmi_nfc_add_event("> gpmi_nfc_dma_isr", 1);
+
+	/* Acknowledge the DMA channel's interrupt. */
+
+	mxs_dma_ack_irq(nfc->isr_dma_channel);
+
+	/* Release the base level. */
+
+	complete(&(nfc->dma_done));
+
+	/* Return success. */
+
+	gpmi_nfc_add_event("< gpmi_nfc_dma_isr", -1);
+
+	return IRQ_HANDLED;
+
+}
+
+/**
+ * gpmi_nfc_dma_init() - Initializes DMA.
+ *
+ * @this:  Per-device data.
+ */
+int gpmi_nfc_dma_init(struct gpmi_nfc_data *this)
+{
+	struct device   *dev = this->dev;
+	struct nfc_hal  *nfc = this->nfc;
+	int             i;
+	int             error;
+
+	/* Allocate the DMA descriptors. */
+
+	for (i = 0; i < NFC_DMA_DESCRIPTOR_COUNT; i++) {
+		nfc->dma_descriptors[i] = mxs_dma_alloc_desc();
+		if (!nfc->dma_descriptors[i]) {
+			dev_err(dev, "Cannot allocate all DMA descriptors.\n");
+			error = -ENOMEM;
+			goto exit_descriptor_allocation;
+		}
+	}
+
+	/* If control arrives here, all is well. */
+
+	return 0;
+
+	/* Control arrives here when something has gone wrong. */
+
+exit_descriptor_allocation:
+	while (--i >= 0)
+		mxs_dma_free_desc(this->nfc->dma_descriptors[i]);
+
+	return error;
+
+}
+
+/**
+ * gpmi_nfc_dma_exit() - Shuts down DMA.
+ *
+ * @this:  Per-device data.
+ */
+void gpmi_nfc_dma_exit(struct gpmi_nfc_data *this)
+{
+	struct nfc_hal  *nfc = this->nfc;
+	int             i;
+
+	/* Free the DMA descriptors. */
+
+	for (i = 0; i < NFC_DMA_DESCRIPTOR_COUNT; i++)
+		mxs_dma_free_desc(nfc->dma_descriptors[i]);
+
+}
+
+/**
+ * gpmi_nfc_set_geometry() - Shared NFC geometry configuration.
+ *
+ * In principle, computing the NFC geometry is version-specific. However, at
+ * this writing all, versions share the same page model, so this code can also
+ * be shared.
+ *
+ * @this:  Per-device data.
+ */
+int gpmi_nfc_set_geometry(struct gpmi_nfc_data *this)
+{
+	struct device             *dev      = this->dev;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct nfc_geometry       *geometry = &this->nfc_geometry;
+	struct boot_rom_helper    *rom      =  this->rom;
+	unsigned int              metadata_size;
+	unsigned int              status_size;
+	unsigned int              chunk_data_size_in_bits;
+	unsigned int              chunk_ecc_size_in_bits;
+	unsigned int              chunk_total_size_in_bits;
+	unsigned int              block_mark_chunk_number;
+	unsigned int              block_mark_chunk_bit_offset;
+	unsigned int              block_mark_bit_offset;
+
+	/* At this writing, we support only BCH. */
+
+	geometry->ecc_algorithm = "BCH";
+
+	/*
+	 * We always choose a metadata size of 10. Don't try to make sense of
+	 * it -- this is really only for historical compatibility.
+	 */
+
+	geometry->metadata_size_in_bytes = 10;
+
+	/*
+	 * At this writing, we always use 512-byte ECC chunks. Later hardware
+	 * will be able to support larger chunks, which will cause this
+	 * decision to move into version-specific code.
+	 */
+
+	geometry->ecc_chunk_size_in_bytes = 512;
+
+	/* Compute the page size based on the physical geometry. */
+
+	geometry->page_size_in_bytes =
+			physical->page_data_size_in_bytes +
+			physical->page_oob_size_in_bytes  ;
+
+	/*
+	 * Compute the total number of ECC chunks in a page. This includes the
+	 * slightly larger chunk at the beginning of the page, which contains
+	 * both data and metadata.
+	 */
+
+	geometry->ecc_chunk_count =
+			  physical->page_data_size_in_bytes /
+			/*---------------------------------*/
+			  geometry->ecc_chunk_size_in_bytes;
+
+	/*
+	 * We use the same ECC strength for all chunks, including the first one.
+	 * At this writing, we base our ECC strength choice entirely on the
+	 * the physical page geometry. In the future, this should be changed to
+	 * pay attention to the detailed device information we gathered earlier.
+	 */
+
+	geometry->ecc_strength = 0;
+
+	switch (physical->page_data_size_in_bytes) {
+	case 2048:
+		geometry->ecc_strength = 8;
+		break;
+	case 4096:
+		switch (physical->page_oob_size_in_bytes) {
+		case 128:
+			geometry->ecc_strength = 8;
+			break;
+		case 218:
+			geometry->ecc_strength = 16;
+			break;
+		}
+		break;
+	}
+
+	/* Check if we were able to figure out the ECC strength. */
+
+	if (!geometry->ecc_strength) {
+		dev_err(dev, "Unsupported page geometry: %u:%u\n",
+			physical->page_data_size_in_bytes,
+			physical->page_oob_size_in_bytes);
+		return !0;
+	}
+
+	/*
+	 * The payload buffer contains the data area of a page. The ECC engine
+	 * only needs what's required to hold the data.
+	 */
+
+	geometry->payload_size_in_bytes = physical->page_data_size_in_bytes;
+
+	/*
+	 * In principle, computing the auxiliary buffer geometry is NFC
+	 * version-specific. However, at this writing, all versions share the
+	 * same model, so this code can also be shared.
+	 *
+	 * The auxiliary buffer contains the metadata and the ECC status. The
+	 * metadata is padded to the nearest 32-bit boundary. The ECC status
+	 * contains one byte for every ECC chunk, and is also padded to the
+	 * nearest 32-bit boundary.
+	 */
+
+	metadata_size = (geometry->metadata_size_in_bytes + 0x3) & ~0x3;
+	status_size   = (geometry->ecc_chunk_count        + 0x3) & ~0x3;
+
+	geometry->auxiliary_size_in_bytes = metadata_size + status_size;
+	geometry->auxiliary_status_offset = metadata_size;
+
+	/* Check if we're going to do block mark swapping. */
+
+	if (!rom->swap_block_mark)
+		return 0;
+
+	/*
+	 * If control arrives here, we're doing block mark swapping, so we need
+	 * to compute the byte and bit offsets of the physical block mark within
+	 * the ECC-based view of the page data. In principle, this isn't a
+	 * difficult computation -- but it's very important and it's easy to get
+	 * it wrong, so we do it carefully.
+	 *
+	 * Note that this calculation is simpler because we use the same ECC
+	 * strength for all chunks, including the zero'th one, which contains
+	 * the metadata. The calculation would be slightly more complicated
+	 * otherwise.
+	 *
+	 * We start by computing the physical bit offset of the block mark. We
+	 * then subtract the number of metadata and ECC bits appearing before
+	 * the mark to arrive at its bit offset within the data alone.
+	 */
+
+	/* Compute some important facts about chunk geometry. */
+
+	chunk_data_size_in_bits = geometry->ecc_chunk_size_in_bytes * 8;
+	chunk_ecc_size_in_bits  = geometry->ecc_strength * 13;
+
+	chunk_total_size_in_bits =
+			chunk_data_size_in_bits + chunk_ecc_size_in_bits;
+
+	/* Compute the bit offset of the block mark within the physical page. */
+
+	block_mark_bit_offset = physical->page_data_size_in_bytes * 8;
+
+	/* Subtract the metadata bits. */
+
+	block_mark_bit_offset -= geometry->metadata_size_in_bytes * 8;
+
+	/*
+	 * Compute the chunk number (starting at zero) in which the block mark
+	 * appears.
+	 */
+
+	block_mark_chunk_number =
+			block_mark_bit_offset / chunk_total_size_in_bits;
+
+	/*
+	 * Compute the bit offset of the block mark within its chunk, and
+	 * validate it.
+	 */
+
+	block_mark_chunk_bit_offset =
+		block_mark_bit_offset -
+			(block_mark_chunk_number * chunk_total_size_in_bits);
+
+	if (block_mark_chunk_bit_offset > chunk_data_size_in_bits) {
+
+		/*
+		 * If control arrives here, the block mark actually appears in
+		 * the ECC bits of this chunk. This wont' work.
+		 */
+
+		dev_err(dev, "Unsupported page geometry "
+					"(block mark in ECC): %u:%u\n",
+					physical->page_data_size_in_bytes,
+					physical->page_oob_size_in_bytes);
+		return !0;
+
+	}
+
+	/*
+	 * Now that we know the chunk number in which the block mark appears,
+	 * we can subtract all the ECC bits that appear before it.
+	 */
+
+	block_mark_bit_offset -=
+			block_mark_chunk_number * chunk_ecc_size_in_bits;
+
+	/*
+	 * We now know the absolute bit offset of the block mark within the
+	 * ECC-based data. We can now compute the byte offset and the bit
+	 * offset within the byte.
+	 */
+
+	geometry->block_mark_byte_offset = block_mark_bit_offset / 8;
+	geometry->block_mark_bit_offset  = block_mark_bit_offset % 8;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/*
+ * This code is useful for debugging.
+ */
+
+/*#define DUMP_DMA_CONTEXT*/
+
+#if (defined DUMP_DMA_CONTEXT)
+
+int dump_dma_context_flag;
+
+void dump_dma_context(struct gpmi_nfc_data *this, char *title)
+{
+
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	void                 *q;
+	uint32_t             *p;
+	unsigned int         i;
+	unsigned int         j;
+
+	if (!dump_dma_context_flag)
+		return;
+
+	pr_info("%s\n", title);
+	pr_info("======\n");
+	pr_info("\n");
+
+	/*--------------------------------------------------------------------*/
+
+	pr_info("  Descriptors\n");
+	pr_info("  -----------\n");
+	{
+
+	for (i = 0; i < NFC_DMA_DESCRIPTOR_COUNT; i++, d++) {
+		pr_info("    #%u\n", i);
+		pr_info("    --\n");
+		pr_info("    Physical Address: 0x%08x\n" , (*d)->address);
+		pr_info("    Next            : 0x%08lx\n", (*d)->cmd.next);
+		pr_info("    Command         : 0x%08lx\n", (*d)->cmd.cmd.data);
+		pr_info("    Buffer          : 0x%08x\n" , (*d)->cmd.address);
+		for (j = 0; j < 6; j++)
+			pr_info("    PIO[%u]          : 0x%08lx\n",
+						j, (*d)->cmd.pio_words[j]);
+	}
+
+	}
+	pr_info("\n");
+
+	/*--------------------------------------------------------------------*/
+
+	pr_info("  DMA\n");
+	pr_info("  ---\n");
+	{
+	void  *DMA = IO_ADDRESS(APBH_DMA_PHYS_ADDR);
+
+	p = q = DMA + 0x200;
+
+	for (i = 0; i < 7; i++) {
+		pr_info("    [0x%03x] 0x%08x\n", q - DMA, *p);
+		q += 0x10;
+		p = q;
+	}
+
+	}
+	pr_info("\n");
+
+	/*--------------------------------------------------------------------*/
+
+	pr_info("  GPMI\n");
+	pr_info("  ----\n");
+	{
+	void  *GPMI = resources->gpmi_regs;
+
+	p = q = GPMI;
+
+	for (i = 0; i < 33; i++) {
+		pr_info("    [0x%03x] 0x%08x\n", q - GPMI, *p);
+		q += 0x10;
+		p = q;
+	}
+
+	}
+	pr_info("\n");
+
+	/*--------------------------------------------------------------------*/
+
+	pr_info("  BCH\n");
+	pr_info("  ---\n");
+	{
+	void  *BCH = resources->bch_regs;
+
+	p = q = BCH;
+
+	for (i = 0; i < 22; i++) {
+		pr_info("    [0x%03x] 0x%08x\n", q - BCH, *p);
+		q += 0x10;
+		p = q;
+	}
+
+	}
+	pr_info("\n");
+
+}
+
+#endif
+
+/**
+ * gpmi_nfc_dma_go - Run a DMA channel.
+ *
+ * @this:         Per-device data structure.
+ * @dma_channel:  The DMA channel we're going to use.
+ */
+int gpmi_nfc_dma_go(struct gpmi_nfc_data *this, int  dma_channel)
+{
+	struct device     *dev       =  this->dev;
+	struct resources  *resources = &this->resources;
+	struct nfc_hal    *nfc       =  this->nfc;
+	unsigned long     timeout;
+	int               error;
+	LIST_HEAD(tmp_desc_list);
+
+	gpmi_nfc_add_event("> gpmi_nfc_dma_go", 1);
+
+	/* Get ready... */
+
+	nfc->isr_dma_channel = dma_channel;
+	init_completion(&nfc->dma_done);
+	mxs_dma_enable_irq(dma_channel, 1);
+
+	/* Go! */
+
+	#if defined(DUMP_DMA_CONTEXT)
+		dump_dma_context(this, "BEFORE");
+	#endif
+
+	mxs_dma_enable(dma_channel);
+
+	/* Wait for it to finish. */
+
+	timeout = wait_for_completion_timeout(&nfc->dma_done,
+							msecs_to_jiffies(1000));
+
+	#if defined(DUMP_DMA_CONTEXT)
+		dump_dma_context(this, "AFTER");
+	#endif
+
+	error = (!timeout) ? -ETIMEDOUT : 0;
+
+	if (error) {
+		dev_err(dev, "[%s] Chip: %u, DMA Channel: %d, Error %d\n",
+			__func__, dma_channel - resources->dma_low_channel,
+			dma_channel, error);
+		gpmi_nfc_add_event("...DMA timed out", 0);
+	} else
+		gpmi_nfc_add_event("...Finished DMA successfully", 0);
+
+	/* Clear out the descriptors we just ran. */
+
+	mxs_dma_cooked(dma_channel, &tmp_desc_list);
+
+	/* Shut the DMA channel down. */
+
+	mxs_dma_reset(dma_channel);
+	mxs_dma_enable_irq(dma_channel, 0);
+	mxs_dma_disable(dma_channel);
+
+	/* Return. */
+
+	gpmi_nfc_add_event("< gpmi_nfc_dma_go", -1);
+
+	return error;
+
+}
+
+/**
+ * ns_to_cycles - Converts time in nanoseconds to cycles.
+ *
+ * @ntime:   The time, in nanoseconds.
+ * @period:  The cycle period, in nanoseconds.
+ * @min:     The minimum allowable number of cycles.
+ */
+static unsigned int ns_to_cycles(unsigned int time,
+					unsigned int period, unsigned int min)
+{
+	unsigned int k;
+
+	/*
+	 * Compute the minimum number of cycles that entirely contain the
+	 * given time.
+	 */
+
+	k = (time + period - 1) / period;
+
+	return max(k, min);
+
+}
+
+/**
+ * gpmi_compute_hardware_timing - Apply timing to current hardware conditions.
+ *
+ * @this:             Per-device data.
+ * @hardware_timing:  A pointer to a hardware timing structure that will receive
+ *                    the results of our calculations.
+ */
+int gpmi_nfc_compute_hardware_timing(struct gpmi_nfc_data *this,
+					struct gpmi_nfc_hardware_timing *hw)
+{
+	struct gpmi_nfc_platform_data  *pdata    =  this->pdata;
+	struct physical_geometry       *physical = &this->physical_geometry;
+	struct nfc_hal                 *nfc      =  this->nfc;
+	struct gpmi_nfc_timing         target    = nfc->timing;
+	bool           improved_timing_is_available;
+	unsigned long  clock_frequency_in_hz;
+	unsigned int   clock_period_in_ns;
+	bool           dll_use_half_periods;
+	unsigned int   dll_delay_shift;
+	unsigned int   max_sample_delay_in_ns;
+	unsigned int   address_setup_in_cycles;
+	unsigned int   data_setup_in_ns;
+	unsigned int   data_setup_in_cycles;
+	unsigned int   data_hold_in_cycles;
+	int            ideal_sample_delay_in_ns;
+	unsigned int   sample_delay_factor;
+	int            tEYE;
+	unsigned int   min_prop_delay_in_ns = pdata->min_prop_delay_in_ns;
+	unsigned int   max_prop_delay_in_ns = pdata->max_prop_delay_in_ns;
+
+	/*
+	 * If there are multiple chips, we need to relax the timings to allow
+	 * for signal distortion due to higher capacitance.
+	 */
+
+	if (physical->chip_count > 2) {
+		target.data_setup_in_ns    += 10;
+		target.data_hold_in_ns     += 10;
+		target.address_setup_in_ns += 10;
+	} else if (physical->chip_count > 1) {
+		target.data_setup_in_ns    += 5;
+		target.data_hold_in_ns     += 5;
+		target.address_setup_in_ns += 5;
+	}
+
+	/* Check if improved timing information is available. */
+
+	improved_timing_is_available =
+		(target.tREA_in_ns  >= 0) &&
+		(target.tRLOH_in_ns >= 0) &&
+		(target.tRHOH_in_ns >= 0) ;
+
+	/* Inspect the clock. */
+
+	clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+	clock_period_in_ns    = 1000000000 / clock_frequency_in_hz;
+
+	/*
+	 * The NFC quantizes setup and hold parameters in terms of clock cycles.
+	 * Here, we quantize the setup and hold timing parameters to the
+	 * next-highest clock period to make sure we apply at least the
+	 * specified times.
+	 *
+	 * For data setup and data hold, the hardware interprets a value of zero
+	 * as the largest possible delay. This is not what's intended by a zero
+	 * in the input parameter, so we impose a minimum of one cycle.
+	 */
+
+	data_setup_in_cycles    = ns_to_cycles(target.data_setup_in_ns,
+							clock_period_in_ns, 1);
+	data_hold_in_cycles     = ns_to_cycles(target.data_hold_in_ns,
+							clock_period_in_ns, 1);
+	address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns,
+							clock_period_in_ns, 0);
+
+	/*
+	 * The clock's period affects the sample delay in a number of ways:
+	 *
+	 * (1) The NFC HAL tells us the maximum clock period the sample delay
+	 *     DLL can tolerate. If the clock period is greater than half that
+	 *     maximum, we must configure the DLL to be driven by half periods.
+	 *
+	 * (2) We need to convert from an ideal sample delay, in ns, to a
+	 *     "sample delay factor," which the NFC uses. This factor depends on
+	 *     whether we're driving the DLL with full or half periods.
+	 *     Paraphrasing the reference manual:
+	 *
+	 *         AD = SDF x 0.125 x RP
+	 *
+	 * where:
+	 *
+	 *     AD   is the applied delay, in ns.
+	 *     SDF  is the sample delay factor, which is dimensionless.
+	 *     RP   is the reference period, in ns, which is a full clock period
+	 *          if the DLL is being driven by full periods, or half that if
+	 *          the DLL is being driven by half periods.
+	 *
+	 * Let's re-arrange this in a way that's more useful to us:
+	 *
+	 *                        8
+	 *         SDF  =  AD x ----
+	 *                       RP
+	 *
+	 * The reference period is either the clock period or half that, so this
+	 * is:
+	 *
+	 *                        8       AD x DDF
+	 *         SDF  =  AD x -----  =  --------
+	 *                      f x P        P
+	 *
+	 * where:
+	 *
+	 *       f  is 1 or 1/2, depending on how we're driving the DLL.
+	 *       P  is the clock period.
+	 *     DDF  is the DLL Delay Factor, a dimensionless value that
+	 *          incorporates all the constants in the conversion.
+	 *
+	 * DDF will be either 8 or 16, both of which are powers of two. We can
+	 * reduce the cost of this conversion by using bit shifts instead of
+	 * multiplication or division. Thus:
+	 *
+	 *                 AD << DDS
+	 *         SDF  =  ---------
+	 *                     P
+	 *
+	 *     or
+	 *
+	 *         AD  =  (SDF >> DDS) x P
+	 *
+	 * where:
+	 *
+	 *     DDS  is the DLL Delay Shift, the logarithm to base 2 of the DDF.
+	 */
+
+	if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) {
+		dll_use_half_periods = true;
+		dll_delay_shift      = 3 + 1;
+	} else {
+		dll_use_half_periods = false;
+		dll_delay_shift      = 3;
+	}
+
+	/*
+	 * Compute the maximum sample delay the NFC allows, under current
+	 * conditions. If the clock is running too slowly, no sample delay is
+	 * possible.
+	 */
+
+	if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns)
+		max_sample_delay_in_ns = 0;
+	else {
+
+		/*
+		 * Compute the delay implied by the largest sample delay factor
+		 * the NFC allows.
+		 */
+
+		max_sample_delay_in_ns =
+			(nfc->max_sample_delay_factor * clock_period_in_ns) >>
+								dll_delay_shift;
+
+		/*
+		 * Check if the implied sample delay larger than the NFC
+		 * actually allows.
+		 */
+
+		if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns)
+			max_sample_delay_in_ns = nfc->max_dll_delay_in_ns;
+
+	}
+
+	/*
+	 * Check if improved timing information is available. If not, we have to
+	 * use a less-sophisticated algorithm.
+	 */
+
+	if (!improved_timing_is_available) {
+
+		/*
+		 * Fold the read setup time required by the NFC into the ideal
+		 * sample delay.
+		 */
+
+		ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns +
+						nfc->internal_data_setup_in_ns;
+
+		/*
+		 * The ideal sample delay may be greater than the maximum
+		 * allowed by the NFC. If so, we can trade off sample delay time
+		 * for more data setup time.
+		 *
+		 * In each iteration of the following loop, we add a cycle to
+		 * the data setup time and subtract a corresponding amount from
+		 * the sample delay until we've satisified the constraints or
+		 * can't do any better.
+		 */
+
+		while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
+			(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+
+			data_setup_in_cycles++;
+			ideal_sample_delay_in_ns -= clock_period_in_ns;
+
+			if (ideal_sample_delay_in_ns < 0)
+				ideal_sample_delay_in_ns = 0;
+
+		}
+
+		/*
+		 * Compute the sample delay factor that corresponds most closely
+		 * to the ideal sample delay. If the result is too large for the
+		 * NFC, use the maximum value.
+		 *
+		 * Notice that we use the ns_to_cycles function to compute the
+		 * sample delay factor. We do this because the form of the
+		 * computation is the same as that for calculating cycles.
+		 */
+
+		sample_delay_factor =
+			ns_to_cycles(
+				ideal_sample_delay_in_ns << dll_delay_shift,
+							clock_period_in_ns, 0);
+
+		if (sample_delay_factor > nfc->max_sample_delay_factor)
+			sample_delay_factor = nfc->max_sample_delay_factor;
+
+		/* Skip to the part where we return our results. */
+
+		goto return_results;
+
+	}
+
+	/*
+	 * If control arrives here, we have more detailed timing information,
+	 * so we can use a better algorithm.
+	 */
+
+	/*
+	 * Fold the read setup time required by the NFC into the maximum
+	 * propagation delay.
+	 */
+
+	max_prop_delay_in_ns += nfc->internal_data_setup_in_ns;
+
+	/*
+	 * Earlier, we computed the number of clock cycles required to satisfy
+	 * the data setup time. Now, we need to know the actual nanoseconds.
+	 */
+
+	data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles;
+
+	/*
+	 * Compute tEYE, the width of the data eye when reading from the NAND
+	 * Flash. The eye width is fundamentally determined by the data setup
+	 * time, perturbed by propagation delays and some characteristics of the
+	 * NAND Flash device.
+	 *
+	 * start of the eye = max_prop_delay + tREA
+	 * end of the eye   = min_prop_delay + tRHOH + data_setup
+	 */
+
+	tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns +
+							(int)data_setup_in_ns;
+
+	tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns;
+
+	/*
+	 * The eye must be open. If it's not, we can try to open it by
+	 * increasing its main forcer, the data setup time.
+	 *
+	 * In each iteration of the following loop, we increase the data setup
+	 * time by a single clock cycle. We do this until either the eye is
+	 * open or we run into NFC limits.
+	 */
+
+	while ((tEYE <= 0) &&
+			(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+		/* Give a cycle to data setup. */
+		data_setup_in_cycles++;
+		/* Synchronize the data setup time with the cycles. */
+		data_setup_in_ns += clock_period_in_ns;
+		/* Adjust tEYE accordingly. */
+		tEYE += clock_period_in_ns;
+	}
+
+	/*
+	 * When control arrives here, the eye is open. The ideal time to sample
+	 * the data is in the center of the eye:
+	 *
+	 *     end of the eye + start of the eye
+	 *     ---------------------------------  -  data_setup
+	 *                    2
+	 *
+	 * After some algebra, this simplifies to the code immediately below.
+	 */
+
+	ideal_sample_delay_in_ns =
+		((int)max_prop_delay_in_ns +
+			(int)target.tREA_in_ns +
+				(int)min_prop_delay_in_ns +
+					(int)target.tRHOH_in_ns -
+						(int)data_setup_in_ns) >> 1;
+
+	/*
+	 * The following figure illustrates some aspects of a NAND Flash read:
+	 *
+	 *
+	 *           __                   _____________________________________
+	 * RDN         \_________________/
+	 *
+	 *                                         <---- tEYE ----->
+	 *                                        /-----------------\
+	 * Read Data ----------------------------<                   >---------
+	 *                                        \-----------------/
+	 *             ^                 ^                 ^              ^
+	 *             |                 |                 |              |
+	 *             |<--Data Setup -->|<--Delay Time -->|              |
+	 *             |                 |                 |              |
+	 *             |                 |                                |
+	 *             |                 |<--   Quantized Delay Time   -->|
+	 *             |                 |                                |
+	 *
+	 *
+	 * We have some issues we must now address:
+	 *
+	 * (1) The *ideal* sample delay time must not be negative. If it is, we
+	 *     jam it to zero.
+	 *
+	 * (2) The *ideal* sample delay time must not be greater than that
+	 *     allowed by the NFC. If it is, we can increase the data setup
+	 *     time, which will reduce the delay between the end of the data
+	 *     setup and the center of the eye. It will also make the eye
+	 *     larger, which might help with the next issue...
+	 *
+	 * (3) The *quantized* sample delay time must not fall either before the
+	 *     eye opens or after it closes (the latter is the problem
+	 *     illustrated in the above figure).
+	 */
+
+	/* Jam a negative ideal sample delay to zero. */
+
+	if (ideal_sample_delay_in_ns < 0)
+		ideal_sample_delay_in_ns = 0;
+
+	/*
+	 * Extend the data setup as needed to reduce the ideal sample delay
+	 * below the maximum permitted by the NFC.
+	 */
+
+	while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
+			(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+
+		/* Give a cycle to data setup. */
+		data_setup_in_cycles++;
+		/* Synchronize the data setup time with the cycles. */
+		data_setup_in_ns += clock_period_in_ns;
+		/* Adjust tEYE accordingly. */
+		tEYE += clock_period_in_ns;
+
+		/*
+		 * Decrease the ideal sample delay by one half cycle, to keep it
+		 * in the middle of the eye.
+		 */
+		ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
+
+		/* Jam a negative ideal sample delay to zero. */
+		if (ideal_sample_delay_in_ns < 0)
+			ideal_sample_delay_in_ns = 0;
+
+	}
+
+	/*
+	 * Compute the sample delay factor that corresponds to the ideal sample
+	 * delay. If the result is too large, then use the maximum allowed
+	 * value.
+	 *
+	 * Notice that we use the ns_to_cycles function to compute the sample
+	 * delay factor. We do this because the form of the computation is the
+	 * same as that for calculating cycles.
+	 */
+
+	sample_delay_factor =
+		ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift,
+							clock_period_in_ns, 0);
+
+	if (sample_delay_factor > nfc->max_sample_delay_factor)
+		sample_delay_factor = nfc->max_sample_delay_factor;
+
+	/*
+	 * These macros conveniently encapsulate a computation we'll use to
+	 * continuously evaluate whether or not the data sample delay is inside
+	 * the eye.
+	 */
+
+	#define IDEAL_DELAY  ((int) ideal_sample_delay_in_ns)
+
+	#define QUANTIZED_DELAY  \
+		((int) ((sample_delay_factor * clock_period_in_ns) >> \
+							dll_delay_shift))
+
+	#define DELAY_ERROR  (abs(QUANTIZED_DELAY - IDEAL_DELAY))
+
+	#define SAMPLE_IS_NOT_WITHIN_THE_EYE  (DELAY_ERROR > (tEYE >> 1))
+
+	/*
+	 * While the quantized sample time falls outside the eye, reduce the
+	 * sample delay or extend the data setup to move the sampling point back
+	 * toward the eye. Do not allow the number of data setup cycles to
+	 * exceed the maximum allowed by the NFC.
+	 */
+
+	while (SAMPLE_IS_NOT_WITHIN_THE_EYE &&
+			(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+
+		/*
+		 * If control arrives here, the quantized sample delay falls
+		 * outside the eye. Check if it's before the eye opens, or after
+		 * the eye closes.
+		 */
+
+		if (QUANTIZED_DELAY > IDEAL_DELAY) {
+
+			/*
+			 * If control arrives here, the quantized sample delay
+			 * falls after the eye closes. Decrease the quantized
+			 * delay time and then go back to re-evaluate.
+			 */
+
+			if (sample_delay_factor != 0)
+				sample_delay_factor--;
+
+			continue;
+
+		}
+
+		/*
+		 * If control arrives here, the quantized sample delay falls
+		 * before the eye opens. Shift the sample point by increasing
+		 * data setup time. This will also make the eye larger.
+		 */
+
+		/* Give a cycle to data setup. */
+		data_setup_in_cycles++;
+		/* Synchronize the data setup time with the cycles. */
+		data_setup_in_ns += clock_period_in_ns;
+		/* Adjust tEYE accordingly. */
+		tEYE += clock_period_in_ns;
+
+		/*
+		 * Decrease the ideal sample delay by one half cycle, to keep it
+		 * in the middle of the eye.
+		 */
+		ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
+
+		/* ...and one less period for the delay time. */
+		ideal_sample_delay_in_ns -= clock_period_in_ns;
+
+		/* Jam a negative ideal sample delay to zero. */
+		if (ideal_sample_delay_in_ns < 0)
+			ideal_sample_delay_in_ns = 0;
+
+		/*
+		 * We have a new ideal sample delay, so re-compute the quantized
+		 * delay.
+		 */
+
+		sample_delay_factor =
+			ns_to_cycles(
+				ideal_sample_delay_in_ns << dll_delay_shift,
+							clock_period_in_ns, 0);
+
+		if (sample_delay_factor > nfc->max_sample_delay_factor)
+			sample_delay_factor = nfc->max_sample_delay_factor;
+
+	}
+
+	/* Control arrives here when we're ready to return our results. */
+
+return_results:
+
+	hw->data_setup_in_cycles    = data_setup_in_cycles;
+	hw->data_hold_in_cycles     = data_hold_in_cycles;
+	hw->address_setup_in_cycles = address_setup_in_cycles;
+	hw->use_half_periods        = dll_use_half_periods;
+	hw->sample_delay_factor     = sample_delay_factor;
+
+	/* Return success. */
+
+	return 0;
+
+}
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c
new file mode 100644
index 000000000000..294bb9409581
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c
@@ -0,0 +1,924 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+#include "gpmi-nfc-gpmi-regs-v0.h"
+#include "gpmi-nfc-bch-regs-v0.h"
+
+/**
+ * init() - Initializes the NFC hardware.
+ *
+ * @this:  Per-device data.
+ */
+static int init(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+	int               error;
+
+	/* Initialize DMA. */
+
+	error = gpmi_nfc_dma_init(this);
+
+	if (error)
+		return error;
+
+	/* Enable the clock. It will stay on until the end of set_geometry(). */
+
+	clk_enable(resources->clock);
+
+	/* Reset the GPMI block. */
+
+	mxs_reset_block(resources->gpmi_regs + HW_GPMI_CTRL0, true);
+
+	/* Choose NAND mode. */
+	__raw_writel(BM_GPMI_CTRL1_GPMI_MODE,
+				resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+	/* Set the IRQ polarity. */
+	__raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Disable write protection. */
+	__raw_writel(BM_GPMI_CTRL1_DEV_RESET,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Select BCH ECC. */
+	__raw_writel(BM_GPMI_CTRL1_BCH_MODE,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+	/* If control arrives here, all is well. */
+
+	return 0;
+
+}
+
+/**
+ * set_geometry() - Configures the NFC geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+	struct resources     *resources = &this->resources;
+	struct nfc_geometry  *nfc       = &this->nfc_geometry;
+	unsigned int         block_count;
+	unsigned int         block_size;
+	unsigned int         metadata_size;
+	unsigned int         ecc_strength;
+	unsigned int         page_size;
+
+	/* We make the abstract choices in a common function. */
+
+	if (gpmi_nfc_set_geometry(this))
+		return !0;
+
+	/* Translate the abstract choices into register fields. */
+
+	block_count   = nfc->ecc_chunk_count - 1;
+	block_size    = nfc->ecc_chunk_size_in_bytes;
+	metadata_size = nfc->metadata_size_in_bytes;
+	ecc_strength  = nfc->ecc_strength >> 1;
+	page_size     = nfc->page_size_in_bytes;
+
+	/* Enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/*
+	 * Reset the BCH block. Notice that we pass in true for the just_enable
+	 * flag. This is because the soft reset for the version 0 BCH block
+	 * doesn't work. If you try to soft reset the BCH block, it becomes
+	 * unusable until the next hard reset.
+	 */
+
+	mxs_reset_block(resources->bch_regs, true);
+
+	/* Configure layout 0. */
+
+	__raw_writel(
+		BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)     |
+		BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) |
+		BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength)       |
+		BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size)   ,
+		resources->bch_regs + HW_BCH_FLASH0LAYOUT0);
+
+	__raw_writel(
+		BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)   |
+		BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength)     |
+		BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) ,
+		resources->bch_regs + HW_BCH_FLASH0LAYOUT1);
+
+	/* Set *all* chip selects to use layout 0. */
+
+	__raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT);
+
+	/* Enable interrupts. */
+
+	__raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
+				resources->bch_regs + HW_BCH_CTRL_SET);
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * set_timing() - Configures the NFC timing.
+ *
+ * @this:    Per-device data.
+ * @timing:  The timing of interest.
+ */
+static int set_timing(struct gpmi_nfc_data *this,
+					const struct gpmi_nfc_timing *timing)
+{
+	struct nfc_hal  *nfc = this->nfc;
+
+	/* Accept the new timing. */
+
+	nfc->timing = *timing;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * get_timing() - Retrieves the NFC hardware timing.
+ *
+ * @this:                    Per-device data.
+ * @clock_frequency_in_hz:   The clock frequency, in Hz, during the current
+ *                           I/O transaction. If no I/O transaction is in
+ *                           progress, this is the clock frequency during the
+ *                           most recent I/O transaction.
+ * @hardware_timing:         The hardware timing configuration in effect during
+ *                           the current I/O transaction. If no I/O transaction
+ *                           is in progress, this is the hardware timing
+ *                           configuration during the most recent I/O
+ *                           transaction.
+ */
+static void get_timing(struct gpmi_nfc_data *this,
+			unsigned long *clock_frequency_in_hz,
+			struct gpmi_nfc_hardware_timing *hardware_timing)
+{
+	struct resources                 *resources = &this->resources;
+	struct nfc_hal                   *nfc       =  this->nfc;
+	unsigned char                    *gpmi_regs = resources->gpmi_regs;
+	uint32_t                         register_image;
+
+	/* Return the clock frequency. */
+
+	*clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+
+	/* We'll be reading the hardware, so let's enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/* Retrieve the hardware timing. */
+
+	register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0);
+
+	hardware_timing->data_setup_in_cycles =
+		(register_image & BM_GPMI_TIMING0_DATA_SETUP) >>
+						BP_GPMI_TIMING0_DATA_SETUP;
+
+	hardware_timing->data_hold_in_cycles =
+		(register_image & BM_GPMI_TIMING0_DATA_HOLD) >>
+						BP_GPMI_TIMING0_DATA_HOLD;
+
+	hardware_timing->address_setup_in_cycles =
+		(register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >>
+						BP_GPMI_TIMING0_ADDRESS_SETUP;
+
+	register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1);
+
+	hardware_timing->use_half_periods =
+		(register_image & BM_GPMI_CTRL1_HALF_PERIOD) >>
+						BP_GPMI_CTRL1_HALF_PERIOD;
+
+	hardware_timing->sample_delay_factor =
+		(register_image & BM_GPMI_CTRL1_RDN_DELAY) >>
+						BP_GPMI_CTRL1_RDN_DELAY;
+
+	/* We're done reading the hardware, so disable the clock. */
+
+	clk_disable(resources->clock);
+
+}
+
+/**
+ * exit() - Shuts down the NFC hardware.
+ *
+ * @this:  Per-device data.
+ */
+static void exit(struct gpmi_nfc_data *this)
+{
+	gpmi_nfc_dma_exit(this);
+}
+
+/**
+ * begin() - Begin NFC I/O.
+ *
+ * @this:  Per-device data.
+ */
+static void begin(struct gpmi_nfc_data *this)
+{
+	struct resources                 *resources = &this->resources;
+	struct nfc_hal                   *nfc       =  this->nfc;
+	struct gpmi_nfc_hardware_timing  hw;
+	unsigned char                    *gpmi_regs = resources->gpmi_regs;
+	unsigned int                     clock_period_in_ns;
+	uint32_t                         register_image;
+	unsigned int                     dll_wait_time_in_us;
+
+	/* Enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/* Get the timing information we need. */
+
+	nfc->clock_frequency_in_hz = clk_get_rate(resources->clock);
+	clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
+
+	gpmi_nfc_compute_hardware_timing(this, &hw);
+
+	/* Set up all the simple timing parameters. */
+
+	register_image =
+		BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
+		BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles)         |
+		BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles)       ;
+
+	__raw_writel(register_image, gpmi_regs + HW_GPMI_TIMING0);
+
+	/*
+	 * HEY - PAY ATTENTION!
+	 *
+	 * DLL_ENABLE must be set to zero when setting RDN_DELAY or HALF_PERIOD.
+	 */
+
+	__raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+	/* Clear out the DLL control fields. */
+
+	__raw_writel(BM_GPMI_CTRL1_RDN_DELAY,   gpmi_regs + HW_GPMI_CTRL1_CLR);
+	__raw_writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+	/* If no sample delay is called for, return immediately. */
+
+	if (!hw.sample_delay_factor)
+		return;
+
+	/* Configure the HALF_PERIOD flag. */
+
+	if (hw.use_half_periods)
+		__raw_writel(BM_GPMI_CTRL1_HALF_PERIOD,
+						gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Set the delay factor. */
+
+	__raw_writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
+						gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Enable the DLL. */
+
+	__raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/*
+	 * After we enable the GPMI DLL, we have to wait 64 clock cycles before
+	 * we can use the GPMI.
+	 *
+	 * Calculate the amount of time we need to wait, in microseconds.
+	 */
+
+	dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
+
+	if (!dll_wait_time_in_us)
+		dll_wait_time_in_us = 1;
+
+	/* Wait for the DLL to settle. */
+
+	udelay(dll_wait_time_in_us);
+
+}
+
+/**
+ * end() - End NFC I/O.
+ *
+ * @this:  Per-device data.
+ */
+static void end(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+}
+
+/**
+ * clear_bch() - Clears a BCH interrupt.
+ *
+ * @this:  Per-device data.
+ */
+static void clear_bch(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+
+	__raw_writel(BM_BCH_CTRL_COMPLETE_IRQ,
+				resources->bch_regs + HW_BCH_CTRL_CLR);
+
+}
+
+/**
+ * is_ready() - Returns the ready/busy status of the given chip.
+ *
+ * @this:  Per-device data.
+ * @chip:  The chip of interest.
+ */
+static int is_ready(struct gpmi_nfc_data *this, unsigned chip)
+{
+	struct resources  *resources = &this->resources;
+	uint32_t          mask;
+	uint32_t          register_image;
+
+	/* Extract and return the status. */
+
+	mask = BM_GPMI_DEBUG_READY0 << chip;
+
+	register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_DEBUG);
+
+	return !!(register_image & mask);
+
+}
+
+/**
+ * send_command() - Sends a command and associated addresses.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that contains the command bytes.
+ * @length:  The number of bytes in the buffer.
+ */
+static int send_command(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that sends out the command. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_CLE;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = DMA_READ;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 3;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BM_GPMI_CTRL0_ADDRESS_INCREMENT          |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * send_data() - Sends data to the given chip.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that contains the data.
+ * @length:  The number of bytes in the buffer.
+ */
+static int send_data(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that writes a buffer out. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = DMA_READ;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 4;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+	(*d)->cmd.pio_words[3] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * read_data() - Receives data from the given chip.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that will receive the data.
+ * @length:  The number of bytes to read.
+ */
+static int read_data(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that reads the data. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = DMA_WRITE;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 1;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/*
+	 * A DMA descriptor that waits for the command to end and the chip to
+	 * become ready.
+	 *
+	 * I think we actually should *not* be waiting for the chip to become
+	 * ready because, after all, we don't care. I think the original code
+	 * did that and no one has re-thought it yet.
+	 */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 1;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 4;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+	(*d)->cmd.pio_words[3] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * send_page() - Sends a page, using ECC.
+ *
+ * @this:       Per-device data.
+ * @chip:       The chip of interest.
+ * @payload:    The physical address of the payload buffer.
+ * @auxiliary:  The physical address of the auxiliary buffer.
+ */
+static int send_page(struct gpmi_nfc_data *this, unsigned chip,
+				dma_addr_t payload, dma_addr_t auxiliary)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct nfc_geometry  *nfc_geo   = &this->nfc_geometry;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+	uint32_t             ecc_command;
+	uint32_t             buffer_mask;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that does an ECC page read. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+	ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
+	buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+				BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 6;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+
+	(*d)->cmd.pio_words[1] = 0;
+
+	(*d)->cmd.pio_words[2] =
+		BM_GPMI_ECCCTRL_ENABLE_ECC               |
+		BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)     |
+		BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+
+	(*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes;
+	(*d)->cmd.pio_words[4] = payload;
+	(*d)->cmd.pio_words[5] = auxiliary;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Prepare to receive an interrupt from the BCH block. */
+
+	init_completion(&nfc->bch_done);
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Wait for the interrupt from the BCH block. */
+
+	wait_for_completion(&nfc->bch_done);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * read_page() - Reads a page, using ECC.
+ *
+ * @this:       Per-device data.
+ * @chip:       The chip of interest.
+ * @payload:    The physical address of the payload buffer.
+ * @auxiliary:  The physical address of the auxiliary buffer.
+ */
+static int read_page(struct gpmi_nfc_data *this, unsigned chip,
+				dma_addr_t payload, dma_addr_t auxiliary)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct nfc_geometry  *nfc_geo   = &this->nfc_geometry;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+	uint32_t             ecc_command;
+	uint32_t             buffer_mask;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* Wait for the chip to report ready. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 1;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 1;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Enable the BCH block and read. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+	ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
+	buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+				BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 6;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode)              |
+		BM_GPMI_CTRL0_WORD_LENGTH                             |
+		BF_GPMI_CTRL0_CS(chip)                                |
+		BF_GPMI_CTRL0_ADDRESS(address)                        |
+		BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] =
+		BM_GPMI_ECCCTRL_ENABLE_ECC 	         |
+		BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)     |
+		BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+	(*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes;
+	(*d)->cmd.pio_words[4] = payload;
+	(*d)->cmd.pio_words[5] = auxiliary;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Disable the BCH block */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 1;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 3;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode)              |
+		BM_GPMI_CTRL0_WORD_LENGTH                             |
+		BF_GPMI_CTRL0_CS(chip)                                |
+		BF_GPMI_CTRL0_ADDRESS(address)                        |
+		BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Deassert the NAND lock and interrupt. */
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 0;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 0;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Prepare to receive an interrupt from the BCH block. */
+
+	init_completion(&nfc->bch_done);
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Wait for the interrupt from the BCH block. */
+
+	wait_for_completion(&nfc->bch_done);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/* This structure represents the NFC HAL for this version of the hardware. */
+
+struct nfc_hal  gpmi_nfc_hal_v0 = {
+	.version                     = 0,
+	.description                 = "4-chip GPMI and BCH",
+	.max_chip_count              = 4,
+	.max_data_setup_cycles       = (BM_GPMI_TIMING0_DATA_SETUP >>
+						BP_GPMI_TIMING0_DATA_SETUP),
+	.internal_data_setup_in_ns   = 0,
+	.max_sample_delay_factor     = (BM_GPMI_CTRL1_RDN_DELAY >>
+						BP_GPMI_CTRL1_RDN_DELAY),
+	.max_dll_clock_period_in_ns  = 32,
+	.max_dll_delay_in_ns         = 16,
+	.init                        = init,
+	.set_geometry                = set_geometry,
+	.set_timing                  = set_timing,
+	.get_timing                  = get_timing,
+	.exit                        = exit,
+	.begin                       = begin,
+	.end                         = end,
+	.clear_bch                   = clear_bch,
+	.is_ready                    = is_ready,
+	.send_command                = send_command,
+	.send_data                   = send_data,
+	.read_data                   = read_data,
+	.send_page                   = send_page,
+	.read_page                   = read_page,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c
new file mode 100644
index 000000000000..962efe686853
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c
@@ -0,0 +1,866 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+#include "gpmi-nfc-gpmi-regs-v1.h"
+#include "gpmi-nfc-bch-regs-v1.h"
+
+/**
+ * init() - Initializes the NFC hardware.
+ *
+ * @this:  Per-device data.
+ */
+static int init(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+	int               error;
+
+	/* Initialize DMA. */
+
+	error = gpmi_nfc_dma_init(this);
+
+	if (error)
+		return error;
+
+	/* Enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/* Reset the GPMI block. */
+
+	mxs_reset_block(resources->gpmi_regs + HW_GPMI_CTRL0, true);
+
+	/* Choose NAND mode. */
+	__raw_writel(BM_GPMI_CTRL1_GPMI_MODE,
+				resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+	/* Set the IRQ polarity. */
+	__raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Disable write protection. */
+	__raw_writel(BM_GPMI_CTRL1_DEV_RESET,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Select BCH ECC. */
+	__raw_writel(BM_GPMI_CTRL1_BCH_MODE,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+	/* If control arrives here, all is well. */
+
+	return 0;
+
+}
+
+/**
+ * set_geometry() - Configures the NFC geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+	struct resources     *resources = &this->resources;
+	struct nfc_geometry  *nfc       = &this->nfc_geometry;
+	unsigned int         block_count;
+	unsigned int         block_size;
+	unsigned int         metadata_size;
+	unsigned int         ecc_strength;
+	unsigned int         page_size;
+
+	/* We make the abstract choices in a common function. */
+
+	if (gpmi_nfc_set_geometry(this))
+		return !0;
+
+	/* Translate the abstract choices into register fields. */
+
+	block_count   = nfc->ecc_chunk_count - 1;
+	block_size    = nfc->ecc_chunk_size_in_bytes;
+	metadata_size = nfc->metadata_size_in_bytes;
+	ecc_strength  = nfc->ecc_strength >> 1;
+	page_size     = nfc->page_size_in_bytes;
+
+	/* Enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/*
+	 * Reset the BCH block. Notice that we pass in true for the just_enable
+	 * flag. This is because the soft reset for the version 0 BCH block
+	 * doesn't work and the version 1 BCH block is similar enough that we
+	 * suspect the same (though this has not been officially tested). If you
+	 * try to soft reset a version 0 BCH block, it becomes unusable until
+	 * the next hard reset.
+	 */
+
+	mxs_reset_block(resources->bch_regs, true);
+
+	/* Configure layout 0. */
+
+	__raw_writel(
+		BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)     |
+		BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) |
+		BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength)       |
+		BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size)   ,
+		resources->bch_regs + HW_BCH_FLASH0LAYOUT0);
+
+	__raw_writel(
+		BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)   |
+		BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength)     |
+		BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) ,
+		resources->bch_regs + HW_BCH_FLASH0LAYOUT1);
+
+	/* Set *all* chip selects to use layout 0. */
+
+	__raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT);
+
+	/* Enable interrupts. */
+
+	__raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
+				resources->bch_regs + HW_BCH_CTRL_SET);
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * set_timing() - Configures the NFC timing.
+ *
+ * @this:    Per-device data.
+ * @timing:  The timing of interest.
+ */
+static int set_timing(struct gpmi_nfc_data *this,
+					const struct gpmi_nfc_timing *timing)
+{
+	struct nfc_hal  *nfc = this->nfc;
+
+	/* Accept the new timing. */
+
+	nfc->timing = *timing;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * get_timing() - Retrieves the NFC hardware timing.
+ *
+ * @this:                    Per-device data.
+ * @clock_frequency_in_hz:   The clock frequency, in Hz, during the current
+ *                           I/O transaction. If no I/O transaction is in
+ *                           progress, this is the clock frequency during the
+ *                           most recent I/O transaction.
+ * @hardware_timing:         The hardware timing configuration in effect during
+ *                           the current I/O transaction. If no I/O transaction
+ *                           is in progress, this is the hardware timing
+ *                           configuration during the most recent I/O
+ *                           transaction.
+ */
+static void get_timing(struct gpmi_nfc_data *this,
+			unsigned long *clock_frequency_in_hz,
+			struct gpmi_nfc_hardware_timing *hardware_timing)
+{
+	struct resources                 *resources = &this->resources;
+	struct nfc_hal                   *nfc       =  this->nfc;
+	unsigned char                    *gpmi_regs = resources->gpmi_regs;
+	uint32_t                         register_image;
+
+	/* Return the clock frequency. */
+
+	*clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+
+	/* We'll be reading the hardware, so let's enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/* Retrieve the hardware timing. */
+
+	register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0);
+
+	hardware_timing->data_setup_in_cycles =
+		(register_image & BM_GPMI_TIMING0_DATA_SETUP) >>
+						BP_GPMI_TIMING0_DATA_SETUP;
+
+	hardware_timing->data_hold_in_cycles =
+		(register_image & BM_GPMI_TIMING0_DATA_HOLD) >>
+						BP_GPMI_TIMING0_DATA_HOLD;
+
+	hardware_timing->address_setup_in_cycles =
+		(register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >>
+						BP_GPMI_TIMING0_ADDRESS_SETUP;
+
+	register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1);
+
+	hardware_timing->use_half_periods =
+		(register_image & BM_GPMI_CTRL1_HALF_PERIOD) >>
+						BP_GPMI_CTRL1_HALF_PERIOD;
+
+	hardware_timing->sample_delay_factor =
+		(register_image & BM_GPMI_CTRL1_RDN_DELAY) >>
+						BP_GPMI_CTRL1_RDN_DELAY;
+
+	/* We're done reading the hardware, so disable the clock. */
+
+	clk_disable(resources->clock);
+
+}
+
+/**
+ * exit() - Shuts down the NFC hardware.
+ *
+ * @this:  Per-device data.
+ */
+static void exit(struct gpmi_nfc_data *this)
+{
+	gpmi_nfc_dma_exit(this);
+}
+
+/**
+ * begin() - Begin NFC I/O.
+ *
+ * @this:  Per-device data.
+ */
+static void begin(struct gpmi_nfc_data *this)
+{
+	struct resources                 *resources = &this->resources;
+	struct nfc_hal                   *nfc       =  this->nfc;
+	struct gpmi_nfc_hardware_timing  hw;
+
+	/* Enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/* Get the timing information we need. */
+
+	nfc->clock_frequency_in_hz = clk_get_rate(resources->clock);
+	gpmi_nfc_compute_hardware_timing(this, &hw);
+
+	/* Apply the hardware timing. */
+
+	/* Coming soon - the clock handling code isn't ready yet. */
+
+}
+
+/**
+ * end() - End NFC I/O.
+ *
+ * @this:  Per-device data.
+ */
+static void end(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+}
+
+/**
+ * clear_bch() - Clears a BCH interrupt.
+ *
+ * @this:  Per-device data.
+ */
+static void clear_bch(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+
+	__raw_writel(BM_BCH_CTRL_COMPLETE_IRQ,
+				resources->bch_regs + HW_BCH_CTRL_CLR);
+
+}
+
+/**
+ * is_ready() - Returns the ready/busy status of the given chip.
+ *
+ * @this:  Per-device data.
+ * @chip:  The chip of interest.
+ */
+static int is_ready(struct gpmi_nfc_data *this, unsigned chip)
+{
+	struct resources  *resources = &this->resources;
+	uint32_t          mask;
+	uint32_t          register_image;
+
+	/* Extract and return the status. */
+
+	mask = BF_GPMI_STAT_READY_BUSY(1 << chip);
+
+	register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_STAT);
+
+	return !!(register_image & mask);
+
+}
+
+/**
+ * send_command() - Sends a command and associated addresses.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that contains the command bytes.
+ * @length:  The number of bytes in the buffer.
+ */
+static int send_command(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that sends out the command. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_CLE;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = DMA_READ;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 3;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BM_GPMI_CTRL0_ADDRESS_INCREMENT          |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * send_data() - Sends data to the given chip.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that contains the data.
+ * @length:  The number of bytes in the buffer.
+ */
+static int send_data(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that writes a buffer out. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = DMA_READ;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 4;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+	(*d)->cmd.pio_words[3] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * read_data() - Receives data from the given chip.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that will receive the data.
+ * @length:  The number of bytes to read.
+ */
+static int read_data(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that reads the data. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = DMA_WRITE;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 1;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/*
+	 * A DMA descriptor that waits for the command to end and the chip to
+	 * become ready.
+	 *
+	 * I think we actually should *not* be waiting for the chip to become
+	 * ready because, after all, we don't care. I think the original code
+	 * did that and no one has re-thought it yet.
+	 */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 1;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 4;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+	(*d)->cmd.pio_words[3] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * send_page() - Sends a page, using ECC.
+ *
+ * @this:       Per-device data.
+ * @chip:       The chip of interest.
+ * @payload:    The physical address of the payload buffer.
+ * @auxiliary:  The physical address of the auxiliary buffer.
+ */
+static int send_page(struct gpmi_nfc_data *this, unsigned chip,
+				dma_addr_t payload, dma_addr_t auxiliary)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct nfc_geometry  *nfc_geo   = &this->nfc_geometry;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+	uint32_t             ecc_command;
+	uint32_t             buffer_mask;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that does an ECC page read. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+	ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__ENCODE;
+	buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+				BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 6;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+
+	(*d)->cmd.pio_words[1] = 0;
+
+	(*d)->cmd.pio_words[2] =
+		BM_GPMI_ECCCTRL_ENABLE_ECC               |
+		BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)     |
+		BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+
+	(*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes;
+	(*d)->cmd.pio_words[4] = payload;
+	(*d)->cmd.pio_words[5] = auxiliary;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Prepare to receive an interrupt from the BCH block. */
+
+	init_completion(&nfc->bch_done);
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Wait for the interrupt from the BCH block. */
+
+	wait_for_completion(&nfc->bch_done);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * read_page() - Reads a page, using ECC.
+ *
+ * @this:       Per-device data.
+ * @chip:       The chip of interest.
+ * @payload:    The physical address of the payload buffer.
+ * @auxiliary:  The physical address of the auxiliary buffer.
+ */
+static int read_page(struct gpmi_nfc_data *this, unsigned chip,
+				dma_addr_t payload, dma_addr_t auxiliary)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct nfc_geometry  *nfc_geo   = &this->nfc_geometry;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+	uint32_t             ecc_command;
+	uint32_t             buffer_mask;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* Wait for the chip to report ready. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 1;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 1;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Enable the BCH block and read. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+	ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__DECODE;
+	buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+				BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 6;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode)              |
+		BM_GPMI_CTRL0_WORD_LENGTH                             |
+		BF_GPMI_CTRL0_CS(chip)                                |
+		BF_GPMI_CTRL0_ADDRESS(address)                        |
+		BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] =
+		BM_GPMI_ECCCTRL_ENABLE_ECC 	         |
+		BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)     |
+		BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+	(*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes;
+	(*d)->cmd.pio_words[4] = payload;
+	(*d)->cmd.pio_words[5] = auxiliary;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Disable the BCH block */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 1;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 3;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode)              |
+		BM_GPMI_CTRL0_WORD_LENGTH                             |
+		BF_GPMI_CTRL0_CS(chip)                                |
+		BF_GPMI_CTRL0_ADDRESS(address)                        |
+		BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Deassert the NAND lock and interrupt. */
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 0;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 0;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Prepare to receive an interrupt from the BCH block. */
+
+	init_completion(&nfc->bch_done);
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Wait for the interrupt from the BCH block. */
+
+	wait_for_completion(&nfc->bch_done);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/* This structure represents the NFC HAL for this version of the hardware. */
+
+struct nfc_hal  gpmi_nfc_hal_v1 = {
+	.version                     = 1,
+	.description                 = "8-chip GPMI and BCH",
+	.max_chip_count              = 8,
+	.max_data_setup_cycles       = (BM_GPMI_TIMING0_DATA_SETUP >>
+						BP_GPMI_TIMING0_DATA_SETUP),
+	.internal_data_setup_in_ns   = 0,
+	.max_sample_delay_factor     = (BM_GPMI_CTRL1_RDN_DELAY >>
+						BP_GPMI_CTRL1_RDN_DELAY),
+	.max_dll_clock_period_in_ns  = 32,
+	.max_dll_delay_in_ns         = 16,
+	.init                        = init,
+	.set_geometry                = set_geometry,
+	.set_timing                  = set_timing,
+	.get_timing                  = get_timing,
+	.exit                        = exit,
+	.begin                       = begin,
+	.end                         = end,
+	.clear_bch                   = clear_bch,
+	.is_ready                    = is_ready,
+	.send_command                = send_command,
+	.send_data                   = send_data,
+	.read_data                   = read_data,
+	.send_page                   = send_page,
+	.read_page                   = read_page,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
new file mode 100644
index 000000000000..0143f1c358ff
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
@@ -0,0 +1,1879 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+/*
+ * This structure contains the "safe" GPMI timing that should succeed with any
+ * NAND Flash device (although, with less-than-optimal performance).
+ */
+
+static struct gpmi_nfc_timing  safe_timing = {
+	.data_setup_in_ns        = 80,
+	.data_hold_in_ns         = 60,
+	.address_setup_in_ns     = 25,
+	.gpmi_sample_delay_in_ns =  6,
+	.tREA_in_ns              = -1,
+	.tRLOH_in_ns             = -1,
+	.tRHOH_in_ns             = -1,
+};
+
+/*
+ * This array has a pointer to every NFC HAL structure. The probing process will
+ * find and install the one that matches the version given by the platform.
+ */
+
+static struct nfc_hal  *(nfc_hals[]) = {
+	&gpmi_nfc_hal_v0,
+	&gpmi_nfc_hal_v1,
+};
+
+/*
+ * This array has a pointer to every Boot ROM Helper structure. The probing
+ * process will find and install the one that matches the version given by the
+ * platform.
+ */
+
+static struct boot_rom_helper  *(boot_rom_helpers[]) = {
+	&gpmi_nfc_boot_rom_helper_v0,
+	&gpmi_nfc_boot_rom_helper_v1,
+};
+
+/**
+ * show_device_report() - Contains a shell script that creates a handy report.
+ *
+ * @d:     The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_report(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+
+	static const char *script =
+		"GPMISysDirectory=/sys/bus/platform/devices/gpmi-nfc.0\n"
+		"\n"
+		"NodeList='\n"
+		"physical_geometry\n"
+		"nfc_info\n"
+		"nfc_geometry\n"
+		"timing\n"
+		"timing_diagram\n"
+		"rom_geometry\n"
+		"mtd_nand_info\n"
+		"mtd_info\n"
+		"'\n"
+		"\n"
+		"cd ${GPMISysDirectory}\n"
+		"\n"
+		"printf '\\n'\n"
+		"\n"
+		"for NodeName in ${NodeList}\n"
+		"do\n"
+		"\n"
+		"    printf '--------------------------------------------\\n'\n"
+		"    printf '%s\\n' ${NodeName}\n"
+		"    printf '--------------------------------------------\\n'\n"
+		"    printf '\\n'\n"
+		"\n"
+		"    cat ${NodeName}\n"
+		"\n"
+		"    printf '\\n'\n"
+		"\n"
+		"done\n"
+		;
+
+	return sprintf(buf, "%s", script);
+
+}
+
+/**
+ * show_device_numchips() - Shows the number of physical chips.
+ *
+ * This node is made obsolete by the physical_geometry node, but we keep it for
+ * backward compatibility (especially for kobs).
+ *
+ * @d:     The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_numchips(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data      *this     = dev_get_drvdata(dev);
+	struct physical_geometry  *physical = &this->physical_geometry;
+
+	return sprintf(buf, "%d\n", physical->chip_count);
+
+}
+
+/**
+ * show_device_physical_geometry() - Shows the physical Flash device geometry.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_physical_geometry(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data      *this     = dev_get_drvdata(dev);
+	struct nand_device_info   *info     = &this->device_info;
+	struct physical_geometry  *physical = &this->physical_geometry;
+
+	return sprintf(buf,
+		"Description            : %s\n"
+		"Chip Count             : %u\n"
+		"Chip Size in Bytes     : %llu\n"
+		"Block Size in Bytes    : %u\n"
+		"Page Data Size in Bytes: %u\n"
+		"Page OOB Size in Bytes : %u\n"
+		,
+		info->description,
+		physical->chip_count,
+		physical->chip_size_in_bytes,
+		physical->block_size_in_bytes,
+		physical->page_data_size_in_bytes,
+		physical->page_oob_size_in_bytes
+	);
+
+}
+
+/**
+ * show_device_nfc_info() - Shows the NFC-specific information.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_nfc_info(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+	struct nfc_hal        *nfc  =  this->nfc;
+
+	return sprintf(buf,
+		"Version                   : %u\n"
+		"Description               : %s\n"
+		"Max Chip Count            : %u\n"
+		"Max Data Setup Cycles     : 0x%x\n"
+		"Internal Data Setup in ns : %u\n"
+		"Max Sample Delay Factor   : 0x%x\n"
+		"Max DLL Clock Period in ns: %u\n"
+		"Max DLL Delay in ns       : %u\n"
+		,
+		nfc->version,
+		nfc->description,
+		nfc->max_chip_count,
+		nfc->max_data_setup_cycles,
+		nfc->internal_data_setup_in_ns,
+		nfc->max_sample_delay_factor,
+		nfc->max_dll_clock_period_in_ns,
+		nfc->max_dll_delay_in_ns
+	);
+
+}
+
+/**
+ * show_device_nfc_geometry() - Shows the NFC view of the device geometry.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_nfc_geometry(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+	struct nfc_geometry   *nfc  = &this->nfc_geometry;
+
+	return sprintf(buf,
+		"ECC Algorithm          : %s\n"
+		"ECC Strength           : %u\n"
+		"Page Size in Bytes     : %u\n"
+		"Metadata Size in Bytes : %u\n"
+		"ECC Chunk Size in Bytes: %u\n"
+		"ECC Chunk Count        : %u\n"
+		"Payload Size in Bytes  : %u\n"
+		"Auxiliary Size in Bytes: %u\n"
+		"Auxiliary Status Offset: %u\n"
+		"Block Mark Byte Offset : %u\n"
+		"Block Mark Bit Offset  : %u\n"
+		,
+		nfc->ecc_algorithm,
+		nfc->ecc_strength,
+		nfc->page_size_in_bytes,
+		nfc->metadata_size_in_bytes,
+		nfc->ecc_chunk_size_in_bytes,
+		nfc->ecc_chunk_count,
+		nfc->payload_size_in_bytes,
+		nfc->auxiliary_size_in_bytes,
+		nfc->auxiliary_status_offset,
+		nfc->block_mark_byte_offset,
+		nfc->block_mark_bit_offset
+	);
+
+}
+
+/**
+ * show_device_rom_geometry() - Shows the Boot ROM Helper's geometry.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_rom_geometry(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data      *this = dev_get_drvdata(dev);
+	struct boot_rom_geometry  *rom  = &this->rom_geometry;
+
+	return sprintf(buf,
+		"Boot Area Count           : %u\n"
+		"Boot Area Size in Bytes   : %u\n"
+		"Stride Size in Pages      : %u\n"
+		"Seach Area Stride Exponent: %u\n"
+		,
+		rom->boot_area_count,
+		rom->boot_area_size_in_bytes,
+		rom->stride_size_in_pages,
+		rom->search_area_stride_exponent
+	);
+
+}
+
+/**
+ * show_device_mtd_nand_info() - Shows the device's MTD NAND-specific info.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_mtd_nand_info(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	int                        o = 0;
+	unsigned int               i;
+	unsigned int               j;
+	static const unsigned int  columns = 8;
+	struct gpmi_nfc_data       *this = dev_get_drvdata(dev);
+	struct mil                 *mil  = &this->mil;
+	struct nand_chip           *nand = &mil->nand;
+
+	o += sprintf(buf + o,
+		"Options                       : 0x%08x\n"
+		"Chip Count                    : %u\n"
+		"Chip Size in Bytes            : %llu\n"
+		"Minimum Writable Size in Bytes: %u\n"
+		"Page Shift                    : %u\n"
+		"Page Mask                     : 0x%x\n"
+		"Block Shift                   : %u\n"
+		"BBT Block Shift               : %u\n"
+		"Chip Shift                    : %u\n"
+		"Block Mark Offset             : %u\n"
+		"Cached Page Number            : %d\n"
+		,
+		nand->options,
+		nand->numchips,
+		nand->chipsize,
+		nand->subpagesize,
+		nand->page_shift,
+		nand->pagemask,
+		nand->phys_erase_shift,
+		nand->bbt_erase_shift,
+		nand->chip_shift,
+		nand->badblockpos,
+		nand->pagebuf
+	);
+
+	o += sprintf(buf + o,
+		"ECC Byte Count       : %u\n"
+		,
+		nand->ecc.layout->eccbytes
+	);
+
+	/* Loop over rows. */
+
+	for (i = 0; (i * columns) < nand->ecc.layout->eccbytes; i++) {
+
+		/* Loop over columns within rows. */
+
+		for (j = 0; j < columns; j++) {
+
+			if (((i * columns) + j) >= nand->ecc.layout->eccbytes)
+				break;
+
+			o += sprintf(buf + o, " %3u",
+				nand->ecc.layout->eccpos[(i * columns) + j]);
+
+		}
+
+		o += sprintf(buf + o, "\n");
+
+	}
+
+	o += sprintf(buf + o,
+		"OOB Available Bytes  : %u\n"
+		,
+		nand->ecc.layout->oobavail
+	);
+
+	j = 0;
+
+	for (i = 0; j < nand->ecc.layout->oobavail; i++) {
+
+		j += nand->ecc.layout->oobfree[i].length;
+
+		o += sprintf(buf + o,
+			"  [%3u, %2u]\n"
+			,
+			nand->ecc.layout->oobfree[i].offset,
+			nand->ecc.layout->oobfree[i].length
+		);
+
+	}
+
+	return o;
+
+}
+
+/**
+ * show_device_mtd_info() - Shows the device's MTD-specific information.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_mtd_info(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	int                        o = 0;
+	unsigned int               i;
+	unsigned int               j;
+	static const unsigned int  columns = 8;
+	struct gpmi_nfc_data       *this = dev_get_drvdata(dev);
+	struct mil                 *mil  = &this->mil;
+	struct mtd_info            *mtd  = &mil->mtd;
+
+	o += sprintf(buf + o,
+		"Name               : %s\n"
+		"Type               : %u\n"
+		"Flags              : 0x%08x\n"
+		"Size in Bytes      : %llu\n"
+		"Erase Region Count : %d\n"
+		"Erase Size in Bytes: %u\n"
+		"Write Size in Bytes: %u\n"
+		"OOB Size in Bytes  : %u\n"
+		"Errors Corrected   : %u\n"
+		"Failed Reads       : %u\n"
+		"Bad Block Count    : %u\n"
+		"BBT Block Count    : %u\n"
+		,
+		mtd->name,
+		mtd->type,
+		mtd->flags,
+		mtd->size,
+		mtd->numeraseregions,
+		mtd->erasesize,
+		mtd->writesize,
+		mtd->oobsize,
+		mtd->ecc_stats.corrected,
+		mtd->ecc_stats.failed,
+		mtd->ecc_stats.badblocks,
+		mtd->ecc_stats.bbtblocks
+	);
+
+	o += sprintf(buf + o,
+		"ECC Byte Count     : %u\n"
+		,
+		mtd->ecclayout->eccbytes
+	);
+
+	/* Loop over rows. */
+
+	for (i = 0; (i * columns) < mtd->ecclayout->eccbytes; i++) {
+
+		/* Loop over columns within rows. */
+
+		for (j = 0; j < columns; j++) {
+
+			if (((i * columns) + j) >= mtd->ecclayout->eccbytes)
+				break;
+
+			o += sprintf(buf + o, " %3u",
+				mtd->ecclayout->eccpos[(i * columns) + j]);
+
+		}
+
+		o += sprintf(buf + o, "\n");
+
+	}
+
+	o += sprintf(buf + o,
+		"OOB Available Bytes: %u\n"
+		,
+		mtd->ecclayout->oobavail
+	);
+
+	j = 0;
+
+	for (i = 0; j < mtd->ecclayout->oobavail; i++) {
+
+		j += mtd->ecclayout->oobfree[i].length;
+
+		o += sprintf(buf + o,
+			"  [%3u, %2u]\n"
+			,
+			mtd->ecclayout->oobfree[i].offset,
+			mtd->ecclayout->oobfree[i].length
+		);
+
+	}
+
+	return o;
+
+}
+
+/**
+  * show_device_timing_diagram() - Shows a timing diagram.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_timing_diagram(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data             *this      = dev_get_drvdata(dev);
+	struct gpmi_nfc_platform_data    *pdata     =  this->pdata;
+	struct nfc_hal                   *nfc       = this->nfc;
+	struct gpmi_nfc_timing           timing     = nfc->timing;
+	struct gpmi_nfc_hardware_timing  hardware_timing;
+	unsigned long                    clock_frequency_in_hz;
+	unsigned long                    clock_period_in_ns;
+	unsigned int                     data_setup_in_ns;
+	unsigned int                     dll_delay_shift;
+	unsigned int                     sample_delay_in_ns;
+	unsigned int                     tDS_in_ns;
+	unsigned int                     tOPEN_in_ns;
+	unsigned int                     tCLOSE_in_ns;
+	unsigned int                     tEYE_in_ns;
+	unsigned int                     tDELAY_in_ns;
+	unsigned int                     tDS;
+	unsigned int                     tOPEN;
+	unsigned int                     tCLOSE;
+	unsigned int                     tEYE;
+	unsigned int                     tDELAY;
+	const unsigned int               diagram_width_in_chars = 55;
+	unsigned int                     diagram_width_in_ns;
+	int                              o = 0;
+	unsigned int                     i;
+
+	/*
+	 * If there are any timing characteristics we need, but don't know, we
+	 * pretend they're zero.
+	 */
+
+	if (timing.tREA_in_ns < 0)
+		timing.tREA_in_ns = 0;
+
+	if (timing.tRHOH_in_ns < 0)
+		timing.tRHOH_in_ns = 0;
+
+	/* Get information about the current/last I/O transaction. */
+
+	nfc->get_timing(this, &clock_frequency_in_hz, &hardware_timing);
+
+	clock_period_in_ns = 1000000000 / clock_frequency_in_hz;
+
+	/* Compute basic timing facts. */
+
+	data_setup_in_ns =
+		hardware_timing.data_setup_in_cycles * clock_period_in_ns;
+
+	/* Compute data sample delay facts. */
+
+	dll_delay_shift = 3;
+
+	if (hardware_timing.use_half_periods)
+		dll_delay_shift++;
+
+	sample_delay_in_ns =
+		(hardware_timing.sample_delay_factor * clock_period_in_ns) >>
+								dll_delay_shift;
+
+	/* Compute the basic metrics in the diagram, in nanoseconds. */
+
+	tDS_in_ns    = data_setup_in_ns;
+	tOPEN_in_ns  = pdata->max_prop_delay_in_ns + timing.tREA_in_ns;
+	tCLOSE_in_ns = pdata->min_prop_delay_in_ns + timing.tRHOH_in_ns;
+	tEYE_in_ns   = tDS_in_ns + tCLOSE_in_ns - tOPEN_in_ns;
+	tDELAY_in_ns = sample_delay_in_ns;
+
+	/*
+	 * We need to translate nanosecond timings into character widths in the
+	 * diagram. The first step is to discover how "wide" the diagram is in
+	 * nanoseconds. That depends on which happens latest: the sample point
+	 * or the close of the eye.
+	 */
+
+	if (tCLOSE_in_ns >= tDELAY_in_ns)
+		diagram_width_in_ns = tDS_in_ns + tCLOSE_in_ns;
+	else
+		diagram_width_in_ns = tDS_in_ns + tDELAY_in_ns;
+
+	/* Convert the metrics that appear in the diagram. */
+
+	tDS    = (tDS_in_ns    * diagram_width_in_chars) / diagram_width_in_ns;
+	tOPEN  = (tOPEN_in_ns  * diagram_width_in_chars) / diagram_width_in_ns;
+	tCLOSE = (tCLOSE_in_ns * diagram_width_in_chars) / diagram_width_in_ns;
+	tEYE   = (tEYE_in_ns   * diagram_width_in_chars) / diagram_width_in_ns;
+	tDELAY = (tDELAY_in_ns * diagram_width_in_chars) / diagram_width_in_ns;
+
+	/*
+	 * Show the results.
+	 *
+	 * This code is really ugly, but it draws a pretty picture :)
+	 */
+
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "Sample ______");
+	for (i = 0; i < tDS; i++)
+		o += sprintf(buf + o, "_");
+	if (tDELAY > 0)
+		for (i = 0; i < (tDELAY - 1); i++)
+			o += sprintf(buf + o, "_");
+	o += sprintf(buf + o, "|");
+	for (i = 0; i < (diagram_width_in_chars - (tDS + tDELAY)); i++)
+		o += sprintf(buf + o, "_");
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "Strobe       ");
+	for (i = 0; i < tDS; i++)
+		o += sprintf(buf + o, " ");
+	o += sprintf(buf + o, "|");
+	if (tDELAY > 1) {
+		for (i = 2; i < tDELAY; i++)
+			o += sprintf(buf + o, "-");
+		o += sprintf(buf + o, "|");
+	}
+	o += sprintf(buf + o, " tDELAY\n");
+
+
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "         tDS ");
+	o += sprintf(buf + o, "|");
+	if (tDS > 1) {
+		for (i = 2; i < tDS; i++)
+			o += sprintf(buf + o, "-");
+		o += sprintf(buf + o, "|");
+	}
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "       ______");
+	for (i = 0; i < tDS; i++)
+		o += sprintf(buf + o, " ");
+	for (i = 0; i < (diagram_width_in_chars - tDS); i++)
+		o += sprintf(buf + o, "_");
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "RDN          ");
+	if (tDS > 0) {
+		if (tDS == 1)
+			o += sprintf(buf + o, "V");
+		else {
+			o += sprintf(buf + o, "\\");
+			for (i = 2; i < tDS; i++)
+				o += sprintf(buf + o, "_");
+			o += sprintf(buf + o, "/");
+		}
+	}
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "       tOPEN ");
+	o += sprintf(buf + o, "|");
+	if (tOPEN > 1) {
+		for (i = 2; i < tOPEN; i++)
+			o += sprintf(buf + o, "-");
+		o += sprintf(buf + o, "|");
+	}
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "             ");
+	for (i = 0; i < tDS; i++)
+		o += sprintf(buf + o, " ");
+	o += sprintf(buf + o, "|");
+	if (tCLOSE > 1) {
+		for (i = 2; i < tCLOSE; i++)
+			o += sprintf(buf + o, "-");
+		o += sprintf(buf + o, "|");
+	}
+	o += sprintf(buf + o, " tCLOSE\n");
+
+
+	o += sprintf(buf + o, "             ");
+	for (i = 0; i < tOPEN; i++)
+		o += sprintf(buf + o, " ");
+	if (tEYE > 2) {
+		o += sprintf(buf + o, " ");
+		for (i = 2; i < tEYE; i++)
+			o += sprintf(buf + o, "_");
+	}
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "Data   ______");
+	for (i = 0; i < tOPEN; i++)
+		o += sprintf(buf + o, "_");
+	if (tEYE > 0) {
+		if (tEYE == 1)
+			o += sprintf(buf + o, "|");
+		else {
+			o += sprintf(buf + o, "/");
+			for (i = 2; i < tEYE; i++)
+				o += sprintf(buf + o, " ");
+			o += sprintf(buf + o, "\\");
+		}
+	}
+	for (i = 0; i < (diagram_width_in_chars - (tOPEN + tEYE)); i++)
+		o += sprintf(buf + o, "_");
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "             ");
+	for (i = 0; i < tOPEN; i++)
+		o += sprintf(buf + o, " ");
+	if (tEYE > 0) {
+		if (tEYE == 1)
+			o += sprintf(buf + o, "|");
+		else {
+			o += sprintf(buf + o, "\\");
+			for (i = 2; i < tEYE; i++)
+				o += sprintf(buf + o, "_");
+			o += sprintf(buf + o, "/");
+		}
+	}
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "             ");
+	for (i = 0; i < tOPEN; i++)
+		o += sprintf(buf + o, " ");
+	o += sprintf(buf + o, "|");
+	if (tEYE > 1) {
+		for (i = 2; i < tEYE; i++)
+			o += sprintf(buf + o, "-");
+		o += sprintf(buf + o, "|");
+	}
+	o += sprintf(buf + o, " tEYE\n");
+
+
+	o += sprintf(buf + o, "\n");
+	o += sprintf(buf + o, "tDS   : %u ns\n", tDS_in_ns);
+	o += sprintf(buf + o, "tOPEN : %u ns\n", tOPEN_in_ns);
+	o += sprintf(buf + o, "tCLOSE: %u ns\n", tCLOSE_in_ns);
+	o += sprintf(buf + o, "tEYE  : %u ns\n", tEYE_in_ns);
+	o += sprintf(buf + o, "tDELAY: %u ns\n", tDELAY_in_ns);
+	o += sprintf(buf + o, "\n");
+
+
+	return o;
+
+}
+
+/**
+ * store_device_invalidate_page_cache() - Invalidates the device's page cache.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_invalidate_page_cache(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+
+	/* Invalidate the page cache. */
+
+	this->mil.nand.pagebuf = -1;
+
+	/* Return success. */
+
+	return size;
+
+}
+
+/**
+ * store_device_mark_block_bad() - Marks a block as bad.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_mark_block_bad(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+	struct mil            *mil  = &this->mil;
+	struct mtd_info       *mtd  = &mil->mtd;
+	struct nand_chip      *nand = &mil->nand;
+	unsigned long         block_number;
+	loff_t                byte_address;
+	int                   error;
+
+	/* Look for nonsense. */
+
+	if (!size)
+		return -EINVAL;
+
+	/* Try to understand the block number. */
+
+	if (strict_strtoul(buf, 0, &block_number))
+		return -EINVAL;
+
+	/* Compute the byte address of this block. */
+
+	byte_address = block_number << nand->phys_erase_shift;
+
+	/* Attempt to mark the block bad. */
+
+	error = mtd->block_markbad(mtd, byte_address);
+
+	if (error)
+		return error;
+
+	/* Return success. */
+
+	return size;
+
+}
+
+/**
+ * show_device_ignorebad() - Shows the value of the 'ignorebad' flag.
+ *
+ * @d:     The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_ignorebad(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+	struct mil            *mil  = &this->mil;
+
+	return sprintf(buf, "%d\n", mil->ignore_bad_block_marks);
+}
+
+/**
+ * store_device_ignorebad() - Sets the value of the 'ignorebad' flag.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_ignorebad(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+	struct mil            *mil  = &this->mil;
+	const char            *p = buf;
+	unsigned long         v;
+
+	/* Try to make sense of what arrived from user space. */
+
+	if (strict_strtoul(p, 0, &v) < 0)
+		return size;
+
+	if (v > 0)
+		v = 1;
+
+	/* Only do something if the value is changing. */
+
+	if (v != mil->ignore_bad_block_marks) {
+
+		if (v) {
+
+			/*
+			 * If control arrives here, we want to begin ignoring
+			 * bad block marks. Reach into the NAND Flash MTD data
+			 * structures and set the in-memory BBT pointer to NULL.
+			 * This will cause the NAND Flash MTD code to believe
+			 * that it never created a BBT and force it to call our
+			 * block_bad function.
+			 *
+			 * See mil_block_bad for more details.
+			 */
+
+			mil->saved_bbt = mil->nand.bbt;
+			mil->nand.bbt  = 0;
+
+		} else {
+
+			/*
+			 * If control arrives here, we want to stop ignoring
+			 * bad block marks. Restore the NAND Flash MTD's pointer
+			 * to its in-memory BBT.
+			 */
+
+			mil->nand.bbt = mil->saved_bbt;
+
+		}
+
+		mil->ignore_bad_block_marks = v;
+
+	}
+
+	return size;
+
+}
+
+/**
+ * show_device_inject_ecc_error() - Shows the device's error injection flag.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_inject_ecc_error(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+	struct mil            *mil  = &this->mil;
+
+	return sprintf(buf, "%d\n", mil->inject_ecc_error);
+
+}
+
+/**
+ * store_device_inject_ecc_error() - Sets the device's error injection flag.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_inject_ecc_error(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+	struct mil            *mil  = &this->mil;
+	long                  new_inject_ecc_error;
+
+	/* Look for nonsense. */
+
+	if (!size)
+		return -EINVAL;
+
+	/* Try to understand the ECC error count. */
+
+	if (strict_strtol(buf, 0, &new_inject_ecc_error))
+		return -EINVAL;
+
+	/* Store the value. */
+
+	mil->inject_ecc_error = new_inject_ecc_error;
+
+	/* Return success. */
+
+	return size;
+
+}
+
+/**
+ * show_device_timing_help() - Show help for setting timing.
+ *
+ * @d:     The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_timing_help(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+
+	static const char *help =
+		"<Data Setup>,<Data Hold>,<Address Setup>,<Sample Delay>,"
+						"<tREA>,<tRLOH>,<tRHOH>\n";
+
+	return sprintf(buf, "%s", help);
+
+}
+
+/**
+ * show_device_timing() - Shows the current timing.
+ *
+ * @d:     The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_timing(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data             *this      = dev_get_drvdata(dev);
+	struct gpmi_nfc_platform_data    *pdata     = this->pdata;
+	struct nfc_hal                   *nfc       = this->nfc;
+	struct gpmi_nfc_timing           *recorded  = &nfc->timing;
+	unsigned long                    clock_frequency_in_hz;
+	unsigned long                    clock_period_in_ns;
+	struct gpmi_nfc_hardware_timing  hardware;
+	unsigned int                     effective_data_setup_in_ns;
+	unsigned int                     effective_data_hold_in_ns;
+	unsigned int                     effective_address_setup_in_ns;
+	unsigned int                     dll_delay_shift;
+	unsigned int                     effective_sample_delay_in_ns;
+
+	/* Get information about the current/last I/O transaction. */
+
+	nfc->get_timing(this, &clock_frequency_in_hz, &hardware);
+
+	clock_period_in_ns = 1000000000 / clock_frequency_in_hz;
+
+	/* Compute basic timing facts. */
+
+	effective_data_setup_in_ns    =
+			hardware.data_setup_in_cycles    * clock_period_in_ns;
+	effective_data_hold_in_ns     =
+			hardware.data_hold_in_cycles     * clock_period_in_ns;
+	effective_address_setup_in_ns =
+			hardware.address_setup_in_cycles * clock_period_in_ns;
+
+	/* Compute data sample delay facts. */
+
+	dll_delay_shift = 3;
+
+	if (hardware.use_half_periods)
+		dll_delay_shift++;
+
+	effective_sample_delay_in_ns =
+		(hardware.sample_delay_factor * clock_period_in_ns) >>
+								dll_delay_shift;
+
+	/* Show the results. */
+
+	return sprintf(buf,
+		"Minimum Propagation Delay in ns  : %u\n"
+		"Maximum Propagation Delay in ns  : %u\n"
+		"Clock Frequency in Hz            : %lu\n"
+		"Clock Period in ns               : %lu\n"
+		"Recorded  Data Setup in ns       : %d\n"
+		"Hardware  Data Setup in cycles   : %u\n"
+		"Effective Data Setup in ns       : %u\n"
+		"Recorded  Data Hold in ns        : %d\n"
+		"Hardware  Data Hold in cycles    : %u\n"
+		"Effective Data Hold in ns        : %u\n"
+		"Recorded  Address Setup in ns    : %d\n"
+		"Hardware  Address Setup in cycles: %u\n"
+		"Effective Address Setup in ns    : %u\n"
+		"Using Half Period                : %s\n"
+		"Recorded  Sample Delay in ns     : %d\n"
+		"Hardware  Sample Delay Factor    : %u\n"
+		"Effective Sample Delay in ns     : %u\n"
+		"Recorded  tREA in ns             : %d\n"
+		"Recorded  tRLOH in ns            : %d\n"
+		"Recorded  tRHOH in ns            : %d\n"
+		,
+		pdata->min_prop_delay_in_ns,
+		pdata->max_prop_delay_in_ns,
+		clock_frequency_in_hz,
+		clock_period_in_ns,
+		recorded->data_setup_in_ns,
+		hardware .data_setup_in_cycles,
+		effective_data_setup_in_ns,
+		recorded->data_hold_in_ns,
+		hardware .data_hold_in_cycles,
+		effective_data_hold_in_ns,
+		recorded->address_setup_in_ns,
+		hardware .address_setup_in_cycles,
+		effective_address_setup_in_ns,
+		hardware .use_half_periods ? "Yes" : "No",
+		recorded->gpmi_sample_delay_in_ns,
+		hardware .sample_delay_factor,
+		effective_sample_delay_in_ns,
+		recorded->tREA_in_ns,
+		recorded->tRLOH_in_ns,
+		recorded->tRHOH_in_ns);
+
+}
+
+/**
+ * store_device_timing() - Sets the current timing.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_timing(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct gpmi_nfc_data    *this = dev_get_drvdata(dev);
+	struct nfc_hal          *nfc  = this->nfc;
+	const char              *p    = buf;
+	const char              *q;
+	char                    tmps[20];
+	long                    t;
+	struct gpmi_nfc_timing  new;
+
+	int8_t *field_pointers[] = {
+		&new.data_setup_in_ns,
+		&new.data_hold_in_ns,
+		&new.address_setup_in_ns,
+		&new.gpmi_sample_delay_in_ns,
+		&new.tREA_in_ns,
+		&new.tRLOH_in_ns,
+		&new.tRHOH_in_ns,
+		NULL,
+	};
+
+	int8_t **field_pointer = field_pointers;
+
+	/*
+	 * Loop over comma-separated timing values in the incoming buffer,
+	 * assigning them to fields in the timing structure as we go along.
+	 */
+
+	while (*field_pointer != NULL) {
+
+		/* Clear out the temporary buffer. */
+
+		memset(tmps, 0, sizeof(tmps));
+
+		/* Copy the timing value into the temporary buffer. */
+
+		q = strchr(p, ',');
+		if (q)
+			strncpy(tmps, p, min_t(int, sizeof(tmps) - 1, q - p));
+		else
+			strncpy(tmps, p, sizeof(tmps) - 1);
+
+		/* Attempt to convert the current timing value. */
+
+		if (strict_strtol(tmps, 0, &t) < 0)
+			return -EINVAL;
+
+		if ((t > 127) || (t < -128))
+			return -EINVAL;
+
+		/* Assign this value to the current field. */
+
+		**field_pointer = (int8_t) t;
+		field_pointer++;
+
+		/* Check if we ran out of input too soon. */
+
+		if (!q && *field_pointer)
+			return -EINVAL;
+
+		/* Move past the comma to the next timing value. */
+
+		p = q + 1;
+
+	}
+
+	/* Hand over the timing to the NFC. */
+
+	nfc->set_timing(this, &new);
+
+	/* Return success. */
+
+	return size;
+
+}
+
+/* Device attributes that appear in sysfs. */
+
+static DEVICE_ATTR(report           , 0555, show_device_report           , 0);
+static DEVICE_ATTR(numchips         , 0444, show_device_numchips         , 0);
+static DEVICE_ATTR(physical_geometry, 0444, show_device_physical_geometry, 0);
+static DEVICE_ATTR(nfc_info         , 0444, show_device_nfc_info         , 0);
+static DEVICE_ATTR(nfc_geometry     , 0444, show_device_nfc_geometry     , 0);
+static DEVICE_ATTR(rom_geometry     , 0444, show_device_rom_geometry     , 0);
+static DEVICE_ATTR(mtd_nand_info    , 0444, show_device_mtd_nand_info    , 0);
+static DEVICE_ATTR(mtd_info         , 0444, show_device_mtd_info         , 0);
+static DEVICE_ATTR(timing_diagram   , 0444, show_device_timing_diagram   , 0);
+static DEVICE_ATTR(timing_help      , 0444, show_device_timing_help      , 0);
+
+static DEVICE_ATTR(invalidate_page_cache, 0644,
+	0, store_device_invalidate_page_cache);
+
+static DEVICE_ATTR(mark_block_bad, 0200,
+	0, store_device_mark_block_bad);
+
+static DEVICE_ATTR(ignorebad, 0644,
+	show_device_ignorebad, store_device_ignorebad);
+
+static DEVICE_ATTR(inject_ecc_error, 0644,
+	show_device_inject_ecc_error, store_device_inject_ecc_error);
+
+static DEVICE_ATTR(timing, 0644,
+	show_device_timing, store_device_timing);
+
+static struct device_attribute *device_attributes[] = {
+	&dev_attr_report,
+	&dev_attr_numchips,
+	&dev_attr_physical_geometry,
+	&dev_attr_nfc_info,
+	&dev_attr_nfc_geometry,
+	&dev_attr_rom_geometry,
+	&dev_attr_mtd_nand_info,
+	&dev_attr_mtd_info,
+	&dev_attr_invalidate_page_cache,
+	&dev_attr_mark_block_bad,
+	&dev_attr_ignorebad,
+	&dev_attr_inject_ecc_error,
+	&dev_attr_timing,
+	&dev_attr_timing_help,
+	&dev_attr_timing_diagram,
+};
+
+/**
+ * validate_the_platform() - Validates information about the platform.
+ *
+ * @pdev:  A pointer to the platform device data structure.
+ */
+static int validate_the_platform(struct platform_device *pdev)
+{
+	struct device                  *dev   = &pdev->dev;
+	struct gpmi_nfc_platform_data  *pdata = pdev->dev.platform_data;
+
+	/* Validate the clock name. */
+
+	if (!pdata->clock_name) {
+		dev_err(dev, "No clock name\n");
+		return -ENXIO;
+	}
+
+	/* Validate the partitions. */
+
+	if ((pdata->partitions && (!pdata->partition_count)) ||
+			(!pdata->partitions && (pdata->partition_count))) {
+		dev_err(dev, "Bad partition data\n");
+		return -ENXIO;
+	}
+
+	/* Return success */
+
+	return 0;
+
+}
+
+/**
+ * acquire_register_block() - Tries to acquire and map a register block.
+ *
+ * @this:            Per-device data.
+ * @resource_name:   The name of the resource.
+ * @reg_block_base:  A pointer to a variable that will receive the address of
+ *                   the mapped register block.
+ */
+static int acquire_register_block(struct gpmi_nfc_data *this,
+			const char *resource_name, void **reg_block_base)
+{
+	struct platform_device  *pdev = this->pdev;
+	struct device           *dev  = this->dev;
+	void                    *p;
+	struct resource         *r;
+
+	/* Attempt to get information about the given resource. */
+
+	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, resource_name);
+
+	if (!r) {
+		dev_err(dev, "Can't get resource information for '%s'\n",
+								resource_name);
+		return -ENXIO;
+	}
+
+	/* Attempt to remap the register block. */
+
+	p = ioremap(r->start, r->end - r->start + 1);
+
+	if (!p) {
+		dev_err(dev, "Can't remap %s\n", resource_name);
+		return -EIO;
+	}
+
+	/* If control arrives here, everything went fine. */
+
+	*reg_block_base = p;
+
+	return 0;
+
+}
+
+/**
+ * release_register_block() - Releases a register block.
+ *
+ * @this:            Per-device data.
+ * @reg_block_base:  A pointer to the mapped register block.
+ */
+static void release_register_block(struct gpmi_nfc_data *this,
+							void *reg_block_base)
+{
+	iounmap(reg_block_base);
+}
+
+/**
+ * acquire_interrupt() - Tries to acquire an interrupt.
+ *
+ * @this:              Per-device data.
+ * @resource_name:     The name of the resource.
+ * @interrupt_handler: A pointer to the function that will handle interrupts
+ *                     from this interrupt number.
+ * @interrupt_number:  A pointer to a variable that will receive the acquired
+ *                     interrupt number.
+ */
+static int acquire_interrupt(
+			struct gpmi_nfc_data *this, const char *resource_name,
+			irq_handler_t interrupt_handler, int *interrupt_number)
+{
+	struct platform_device  *pdev = this->pdev;
+	struct device           *dev  = this->dev;
+	int                     error = 0;
+	int                     i;
+
+	/* Attempt to get information about the given resource. */
+
+	i = platform_get_irq_byname(pdev, resource_name);
+
+	if (i < 0) {
+		dev_err(dev, "Can't get resource information for '%s'\n",
+								resource_name);
+		return -ENXIO;
+	}
+
+	/* Attempt to own the interrupt. */
+
+	error = request_irq(i, interrupt_handler, 0, resource_name, this);
+
+	if (error) {
+		dev_err(dev, "Can't own %s\n", resource_name);
+		return -EIO;
+	}
+
+	/* If control arrives here, everything went fine. */
+
+	*interrupt_number = i;
+
+	return 0;
+
+}
+
+/**
+ * release_interrupt() - Releases an interrupt.
+ *
+ * @this:              Per-device data.
+ * @interrupt_number:  The interrupt number.
+ */
+static void release_interrupt(struct gpmi_nfc_data *this, int interrupt_number)
+{
+	free_irq(interrupt_number, this);
+}
+
+/**
+ * acquire_dma_channels() - Tries to acquire DMA channels.
+ *
+ * @this:           Per-device data.
+ * @resource_name:  The name of the resource.
+ * @low_channel:    A pointer to a variable that will receive the acquired
+ *                  low DMA channel number.
+ * @high_channel:   A pointer to a variable that will receive the acquired
+ *                  high DMA channel number.
+ */
+static int acquire_dma_channels(
+			struct gpmi_nfc_data *this, const char *resource_name,
+			unsigned *low_channel, unsigned *high_channel)
+{
+	struct platform_device  *pdev = this->pdev;
+	struct device           *dev  = this->dev;
+	int                     error = 0;
+	struct resource         *r;
+	unsigned int            dma_channel;
+
+	/* Attempt to get information about the given resource. */
+
+	r = platform_get_resource_byname(pdev, IORESOURCE_DMA, resource_name);
+
+	if (!r) {
+		dev_err(dev, "Can't get resource information for '%s'\n",
+								resource_name);
+		return -ENXIO;
+	}
+
+	/* Loop over DMA channels, attempting to own them. */
+
+	for (dma_channel = r->start; dma_channel <= r->end; dma_channel++) {
+
+		/* Attempt to own the current channel. */
+
+		error = mxs_dma_request(dma_channel, dev, resource_name);
+
+		/* Check if we successfully acquired the current channel. */
+
+		if (error) {
+
+			dev_err(dev, "Can't acquire DMA channel %u\n",
+								dma_channel);
+
+			/* Free all the channels we've already acquired. */
+
+			while (--dma_channel >= 0)
+				mxs_dma_release(dma_channel, dev);
+
+			return error;
+
+		}
+
+		/*
+		 * If control arrives here, we successfully acquired the
+		 * current channel. Continue initializing it.
+		 */
+
+		mxs_dma_reset(dma_channel);
+		mxs_dma_ack_irq(dma_channel);
+
+	}
+
+	/* If control arrives here, all went well. */
+
+	*low_channel  = r->start;
+	*high_channel = r->end;
+
+	return 0;
+
+}
+
+/**
+ * release_dma_channels() - Releases DMA channels.
+ *
+ * @this:          Per-device data.
+ * @low_channel:   The low DMA channel number.
+ * @high_channel:  The high DMA channel number.
+ */
+static void release_dma_channels(struct gpmi_nfc_data *this,
+				unsigned low_channel, unsigned high_channel)
+{
+	struct device  *dev = this->dev;
+	unsigned int   i;
+
+	for (i = low_channel; i <= high_channel; i++)
+		mxs_dma_release(i, dev);
+}
+
+/**
+ * acquire_clock() - Tries to acquire a clock.
+ *
+ * @this:           Per-device data.
+ * @resource_name:  The name of the clock.
+ * @high_channel:   A pointer to a variable that will receive the acquired
+ *                  clock address.
+ */
+static int acquire_clock(struct gpmi_nfc_data *this,
+				const char *clock_name, struct clk **clock)
+{
+	struct device  *dev  = this->dev;
+	int            error = 0;
+	struct clk     *c;
+
+	/* Try to get the clock. */
+
+	c = clk_get(dev, clock_name);
+
+	if (IS_ERR(c)) {
+		error = PTR_ERR(c);
+		dev_err(dev, "Can't own clock %s\n", clock_name);
+		return error;
+	}
+
+	/* If control arrives here, everything went fine. */
+
+	*clock = c;
+
+	return 0;
+
+}
+
+/**
+ * release_clock() - Releases a clock.
+ *
+ * @this:   Per-device data.
+ * @clock:  A pointer to the clock structure.
+ */
+static void release_clock(struct gpmi_nfc_data *this, struct clk *clock)
+{
+	clk_disable(clock);
+	clk_put(clock);
+}
+
+/**
+ * acquire_resources() - Tries to acquire resources.
+ *
+ * @this:  Per-device data.
+ */
+static int acquire_resources(struct gpmi_nfc_data *this)
+{
+	struct gpmi_nfc_platform_data  *pdata     =  this->pdata;
+	struct resources               *resources = &this->resources;
+	int                            error      = 0;
+
+	/* Attempt to acquire the GPMI register block. */
+
+	error = acquire_register_block(this,
+		GPMI_NFC_GPMI_REGS_ADDR_RES_NAME, &(resources->gpmi_regs));
+
+	if (error)
+		goto exit_gpmi_regs;
+
+	/* Attempt to acquire the BCH register block. */
+
+	error = acquire_register_block(this,
+		GPMI_NFC_BCH_REGS_ADDR_RES_NAME, &(resources->bch_regs));
+
+	if (error)
+		goto exit_bch_regs;
+
+	/* Attempt to acquire the BCH interrupt. */
+
+	error = acquire_interrupt(this,
+		GPMI_NFC_BCH_INTERRUPT_RES_NAME,
+		gpmi_nfc_bch_isr, &(resources->bch_interrupt));
+
+	if (error)
+		goto exit_bch_interrupt;
+
+	/* Attempt to acquire the DMA channels. */
+
+	error = acquire_dma_channels(this,
+		GPMI_NFC_DMA_CHANNELS_RES_NAME,
+		&(resources->dma_low_channel), &(resources->dma_high_channel));
+
+	if (error)
+		goto exit_dma_channels;
+
+	/* Attempt to acquire the DMA interrupt. */
+
+	error = acquire_interrupt(this,
+		GPMI_NFC_DMA_INTERRUPT_RES_NAME,
+		gpmi_nfc_dma_isr, &(resources->dma_interrupt));
+
+	if (error)
+		goto exit_dma_interrupt;
+
+	/* Attempt to acquire our clock. */
+
+	error = acquire_clock(this, pdata->clock_name, &(resources->clock));
+
+	if (error)
+		goto exit_clock;
+
+	/* If control arrives here, all went well. */
+
+	return 0;
+
+	/* Control arrives here if something went wrong. */
+
+exit_clock:
+	release_interrupt(this, resources->dma_interrupt);
+exit_dma_interrupt:
+	release_dma_channels(this,
+		resources->dma_low_channel, resources->dma_high_channel);
+exit_dma_channels:
+	release_interrupt(this, resources->bch_interrupt);
+exit_bch_interrupt:
+	release_register_block(this, resources->bch_regs);
+exit_bch_regs:
+	release_register_block(this, resources->gpmi_regs);
+exit_gpmi_regs:
+
+	return error;
+
+}
+
+/**
+ * release_resources() - Releases resources.
+ *
+ * @this:  Per-device data.
+ */
+static void release_resources(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+
+	release_clock(this, resources->clock);
+	release_register_block(this, resources->gpmi_regs);
+	release_register_block(this, resources->bch_regs);
+	release_interrupt(this, resources->bch_interrupt);
+	release_dma_channels(this,
+		resources->dma_low_channel, resources->dma_high_channel);
+	release_interrupt(this, resources->dma_interrupt);
+}
+
+/**
+ * set_up_nfc_hal() - Sets up the NFC HAL.
+ *
+ * @this:  Per-device data.
+ */
+static int set_up_nfc_hal(struct gpmi_nfc_data *this)
+{
+	struct gpmi_nfc_platform_data  *pdata = this->pdata;
+	struct device                  *dev   = this->dev;
+	struct nfc_hal                 *nfc;
+	int                            error = 0;
+	unsigned int                   i;
+
+	/* Attempt to find an NFC HAL that matches the given version. */
+
+	for (i = 0; i < ARRAY_SIZE(nfc_hals); i++) {
+
+		nfc = nfc_hals[i];
+
+		if (nfc->version == pdata->nfc_version) {
+			this->nfc = nfc;
+			break;
+		}
+
+	}
+
+	/* Check if we found a HAL. */
+
+	if (i >= ARRAY_SIZE(nfc_hals)) {
+		dev_err(dev, "Unkown NFC version %u\n", pdata->nfc_version);
+		return -ENXIO;
+	}
+
+	pr_info("NFC: Version %u, %s\n", nfc->version, nfc->description);
+
+	/*
+	 * Check if we can handle the number of chips called for by the platform
+	 * data.
+	 */
+
+	if (pdata->max_chip_count > nfc->max_chip_count) {
+		dev_err(dev, "Platform data calls for %u chips "
+				"but NFC supports a max of %u.\n",
+				pdata->max_chip_count, nfc->max_chip_count);
+		return -ENXIO;
+	}
+
+	/* Initialize the NFC HAL. */
+
+	error = nfc->init(this);
+
+	if (error)
+		return error;
+
+	/* Set up safe timing. */
+
+	nfc->set_timing(this, &safe_timing);
+
+	/*
+	 * If control arrives here, all is well.
+	 */
+
+	return 0;
+
+}
+
+/**
+ * set_up_boot_rom_helper() - Sets up the Boot ROM Helper.
+ *
+ * @this:  Per-device data.
+ */
+static int set_up_boot_rom_helper(struct gpmi_nfc_data *this)
+{
+	struct gpmi_nfc_platform_data  *pdata = this->pdata;
+	struct device                  *dev   = this->dev;
+	unsigned int                   i;
+	struct boot_rom_helper         *rom;
+
+	/* Attempt to find a Boot ROM Helper that matches the given version. */
+
+	for (i = 0; i < ARRAY_SIZE(boot_rom_helpers); i++) {
+
+		rom = boot_rom_helpers[i];
+
+		if (rom->version == pdata->boot_rom_version) {
+			this->rom = rom;
+			break;
+		}
+
+	}
+
+	/* Check if we found a Boot ROM Helper. */
+
+	if (i >= ARRAY_SIZE(boot_rom_helpers)) {
+		dev_err(dev, "Unkown Boot ROM version %u\n",
+						pdata->boot_rom_version);
+		return -ENXIO;
+	}
+
+	pr_info("Boot ROM: Version %u, %s\n", rom->version, rom->description);
+
+	/*
+	 * If control arrives here, all is well.
+	 */
+
+	return 0;
+
+}
+
+/**
+ * manage_sysfs_files() - Creates/removes sysfs files for this device.
+ *
+ * @this:  Per-device data.
+ */
+static void manage_sysfs_files(struct gpmi_nfc_data *this, int create)
+{
+	struct device            *dev = this->dev;
+	int                      error;
+	unsigned int             i;
+	struct device_attribute  **attr;
+
+	for (i = 0, attr = device_attributes;
+			i < ARRAY_SIZE(device_attributes); i++, attr++) {
+
+		if (create) {
+			error = device_create_file(dev, *attr);
+			if (error) {
+				while (--attr >= device_attributes)
+					device_remove_file(dev, *attr);
+				return;
+			}
+		} else {
+			device_remove_file(dev, *attr);
+		}
+
+	}
+
+}
+
+/**
+ * gpmi_nfc_probe() - Probes for a device and, if possible, takes ownership.
+ *
+ * @pdev:  A pointer to the platform device data structure.
+ */
+static int gpmi_nfc_probe(struct platform_device *pdev)
+{
+	int                            error  = 0;
+	struct device                  *dev   = &pdev->dev;
+	struct gpmi_nfc_platform_data  *pdata = pdev->dev.platform_data;
+	struct gpmi_nfc_data           *this  = 0;
+
+	/* Validate the platform device data. */
+
+	error = validate_the_platform(pdev);
+
+	if (error)
+		goto exit_validate_platform;
+
+	/* Allocate memory for the per-device data. */
+
+	this = kzalloc(sizeof(*this), GFP_KERNEL);
+
+	if (!this) {
+		dev_err(dev, "Failed to allocate per-device memory\n");
+		error = -ENOMEM;
+		goto exit_allocate_this;
+	}
+
+	/* Set up our data structures. */
+
+	platform_set_drvdata(pdev, this);
+
+	this->pdev  = pdev;
+	this->dev   = &pdev->dev;
+	this->pdata = pdata;
+
+	/* Acquire the resources we need. */
+
+	error = acquire_resources(this);
+
+	if (error)
+		goto exit_acquire_resources;
+
+	/* Set up the NFC. */
+
+	error = set_up_nfc_hal(this);
+
+	if (error)
+		goto exit_nfc_init;
+
+	/* Set up the platform. */
+
+	if (pdata->platform_init)
+		error = pdata->platform_init(pdata->max_chip_count);
+
+	if (error)
+		goto exit_platform_init;
+
+	/* Set up the Boot ROM Helper. */
+
+	error = set_up_boot_rom_helper(this);
+
+	if (error)
+		goto exit_boot_rom_helper_init;
+
+	/* Initialize the MTD Interface Layer. */
+
+	error = gpmi_nfc_mil_init(this);
+
+	if (error)
+		goto exit_mil_init;
+
+	/* Create sysfs entries for this device. */
+
+	manage_sysfs_files(this, true);
+
+	/* Return success. */
+
+	return 0;
+
+	/* Error return paths begin here. */
+
+exit_mil_init:
+exit_boot_rom_helper_init:
+	if (pdata->platform_exit)
+		pdata->platform_exit(pdata->max_chip_count);
+exit_platform_init:
+	this->nfc->exit(this);
+exit_nfc_init:
+	release_resources(this);
+exit_acquire_resources:
+	platform_set_drvdata(pdev, NULL);
+	kfree(this);
+exit_allocate_this:
+exit_validate_platform:
+	return error;
+
+}
+
+/**
+ * gpmi_nfc_remove() - Dissociates this driver from the given device.
+ *
+ * @pdev:  A pointer to the platform device data structure.
+ */
+static int __exit gpmi_nfc_remove(struct platform_device *pdev)
+{
+	struct gpmi_nfc_data           *this = platform_get_drvdata(pdev);
+	struct gpmi_nfc_platform_data  *pdata = this->pdata;
+
+	manage_sysfs_files(this, false);
+	gpmi_nfc_mil_exit(this);
+	if (pdata->platform_exit)
+		pdata->platform_exit(pdata->max_chip_count);
+	this->nfc->exit(this);
+	release_resources(this);
+	platform_set_drvdata(pdev, NULL);
+	kfree(this);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+
+/**
+ * gpmi_nfc_suspend() - Puts the NFC into a low power state.
+ *
+ * @pdev:  A pointer to the platform device data structure.
+ * @state: The new power state.
+ */
+static int gpmi_nfc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	return 0;
+}
+
+/**
+ * gpmi_nfc_resume() - Brings the NFC back from a low power state.
+ *
+ * @pdev:  A pointer to the platform device data structure.
+ */
+static int gpmi_nfc_resume(struct platform_device *pdev)
+{
+	return 0;
+}
+
+#else
+
+#define suspend  NULL
+#define resume   NULL
+
+#endif  /* CONFIG_PM */
+
+/*
+ * This structure represents this driver to the platform management system.
+ */
+static struct platform_driver gpmi_nfc_driver = {
+	.driver = {
+		.name = GPMI_NFC_DRIVER_NAME,
+	},
+	.probe   = gpmi_nfc_probe,
+	.remove  = __exit_p(gpmi_nfc_remove),
+	.suspend = gpmi_nfc_suspend,
+	.resume  = gpmi_nfc_resume,
+};
+
+/**
+ * gpmi_nfc_init() - Initializes this module.
+ */
+static int __init gpmi_nfc_init(void)
+{
+
+	pr_info("i.MX GPMI NFC\n");
+
+	/* Register this driver with the platform management system. */
+
+	if (platform_driver_register(&gpmi_nfc_driver) != 0) {
+		pr_err("i.MX GPMI NFC driver registration failed\n");
+		return -ENODEV;
+	}
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * gpmi_nfc_exit() - Deactivates this module.
+ */
+static void __exit gpmi_nfc_exit(void)
+{
+	platform_driver_unregister(&gpmi_nfc_driver);
+}
+
+module_init(gpmi_nfc_init);
+module_exit(gpmi_nfc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("i.MX GPMI NAND Flash Controller Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c
new file mode 100644
index 000000000000..34505b8e6546
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c
@@ -0,0 +1,2599 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+/*
+ * Indicates the driver should register the MTD that represents the entire
+ * medium, thus making it visible.
+ */
+
+static int register_main_mtd;
+module_param(register_main_mtd, int, 0400);
+
+/*
+ * Indicates the driver should attempt to perform DMA directly to/from buffers
+ * passed into this driver. This is true by default. If false, the driver will
+ * *always* copy incoming/outgoing data to/from its own DMA buffers.
+ */
+
+static int map_io_buffers = true;
+module_param(map_io_buffers, int, 0600);
+
+/**
+ * mil_outgoing_buffer_dma_begin() - Begins DMA on an outgoing buffer.
+ *
+ * @this:      Per-device data.
+ * @source:    The source buffer.
+ * @length:    The length of the data in the source buffer.
+ * @alt_virt:  The virtual address of an alternate buffer which is ready to be
+ *             used for DMA.
+ * @alt_phys:  The physical address of an alternate buffer which is ready to be
+ *             used for DMA.
+ * @alt_size:  The size of the alternate buffer.
+ * @use_virt:  A pointer to a variable that will receive the virtual address to
+ *             use.
+ * @use_phys:  A pointer to a variable that will receive the physical address to
+ *             use.
+ */
+static int mil_outgoing_buffer_dma_begin(struct gpmi_nfc_data *this,
+			const void *source, unsigned length,
+			void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+			const void **use_virt, dma_addr_t *use_phys)
+{
+	struct device  *dev = this->dev;
+	dma_addr_t     source_phys = ~0;
+
+	/*
+	 * If we can, we want to use the caller's buffer directly for DMA. Check
+	 * if the system will let us map them.
+	 */
+
+	if (map_io_buffers && virt_addr_valid(source))
+		source_phys =
+			dma_map_single(dev,
+				(void *) source, length, DMA_TO_DEVICE);
+
+	if (dma_mapping_error(dev, source_phys)) {
+
+		/*
+		 * If control arrives here, we're not mapping the source buffer.
+		 * Make sure the alternate is large enough.
+		 */
+
+		if (alt_size < length) {
+			dev_err(dev, "Alternate buffer is too small "
+							"for outgoing I/O\n");
+			return -ENOMEM;
+		}
+
+		/*
+		 * Copy the contents of the source buffer into the alternate
+		 * buffer and set up the return values accordingly.
+		 */
+
+		memcpy(alt_virt, source, length);
+
+		*use_virt = alt_virt;
+		*use_phys = alt_phys;
+
+	} else {
+
+		/*
+		 * If control arrives here, we're mapping the source buffer. Set
+		 * up the return values accordingly.
+		 */
+
+		*use_virt = source;
+		*use_phys = source_phys;
+
+	}
+
+	/* If control arrives here, all is well. */
+
+	return 0;
+
+}
+
+/**
+ * mil_outgoing_buffer_dma_end() - Ends DMA on an outgoing buffer.
+ *
+ * @this:       Per-device data.
+ * @source:     The source buffer.
+ * @length:     The length of the data in the source buffer.
+ * @alt_virt:   The virtual address of an alternate buffer which was ready to be
+ *              used for DMA.
+ * @alt_phys:   The physical address of an alternate buffer which was ready to
+ *              be used for DMA.
+ * @alt_size:   The size of the alternate buffer.
+ * @used_virt:  The virtual address that was used.
+ * @used_phys:  The physical address that was used.
+ */
+static void mil_outgoing_buffer_dma_end(struct gpmi_nfc_data *this,
+		const void *source, unsigned length,
+		void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+		const void *used_virt, dma_addr_t used_phys)
+{
+	struct device  *dev = this->dev;
+
+	/*
+	 * Check if we used the source buffer, and it's not one of our own DMA
+	 * buffers. If so, we need to unmap it.
+	 */
+
+	if (used_virt == source)
+		dma_unmap_single(dev, used_phys, length, DMA_TO_DEVICE);
+
+}
+
+/**
+ * mil_incoming_buffer_dma_begin() - Begins DMA on an incoming buffer.
+ *
+ * @this:         Per-device data.
+ * @destination:  The destination buffer.
+ * @length:       The length of the data that will arrive.
+ * @alt_virt:     The virtual address of an alternate buffer which is ready
+ *                to be used for DMA.
+ * @alt_phys:     The physical address of an alternate buffer which is ready
+ *                to be used for DMA.
+ * @alt_size:     The size of the alternate buffer.
+ * @use_virt:     A pointer to a variable that will receive the virtual address
+ *                to use.
+ * @use_phys:     A pointer to a variable that will receive the physical address
+ *                to use.
+ */
+static int mil_incoming_buffer_dma_begin(struct gpmi_nfc_data *this,
+			void *destination, unsigned length,
+			void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+			void **use_virt, dma_addr_t *use_phys)
+{
+	struct device  *dev = this->dev;
+	dma_addr_t     destination_phys = ~0;
+
+	/*
+	 * If we can, we want to use the caller's buffer directly for DMA. Check
+	 * if the system will let us map them.
+	 */
+
+	if (map_io_buffers && virt_addr_valid(destination))
+		destination_phys =
+			dma_map_single(dev,
+				(void *) destination, length, DMA_FROM_DEVICE);
+
+	if (dma_mapping_error(dev, destination_phys)) {
+
+		/*
+		 * If control arrives here, we're not mapping the destination
+		 * buffer. Make sure the alternate is large enough.
+		 */
+
+		if (alt_size < length) {
+			dev_err(dev, "Alternate buffer is too small "
+							"for incoming I/O\n");
+			return -ENOMEM;
+		}
+
+		/* Set up the return values to use the alternate. */
+
+		*use_virt = alt_virt;
+		*use_phys = alt_phys;
+
+	} else {
+
+		/*
+		 * If control arrives here, we're mapping the destination
+		 * buffer. Set up the return values accordingly.
+		 */
+
+		*use_virt = destination;
+		*use_phys = destination_phys;
+
+	}
+
+	/* If control arrives here, all is well. */
+
+	return 0;
+
+}
+
+/**
+ * mil_incoming_buffer_dma_end() - Ends DMA on an incoming buffer.
+ *
+ * @this:         Per-device data.
+ * @destination:  The destination buffer.
+ * @length:       The length of the data that arrived.
+ * @alt_virt:     The virtual address of an alternate buffer which was ready to
+ *                be used for DMA.
+ * @alt_phys:     The physical address of an alternate buffer which was ready to
+ *                be used for DMA.
+ * @alt_size:     The size of the alternate buffer.
+ * @used_virt:    The virtual address that was used.
+ * @used_phys:    The physical address that was used.
+ */
+static void mil_incoming_buffer_dma_end(struct gpmi_nfc_data *this,
+			void *destination, unsigned length,
+			void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+			void *used_virt, dma_addr_t used_phys)
+{
+	struct device  *dev = this->dev;
+
+	/*
+	 * Check if we used the destination buffer, and it's not one of our own
+	 * DMA buffers. If so, we need to unmap it.
+	 */
+
+	if (used_virt == destination)
+		dma_unmap_single(dev, used_phys, length, DMA_FROM_DEVICE);
+	else
+		memcpy(destination, alt_virt, length);
+
+}
+
+/**
+ * mil_cmd_ctrl - MTD Interface cmd_ctrl()
+ *
+ * This is the function that we install in the cmd_ctrl function pointer of the
+ * owning struct nand_chip. The only functions in the reference implementation
+ * that use these functions pointers are cmdfunc and select_chip.
+ *
+ * In this driver, we implement our own select_chip, so this function will only
+ * be called by the reference implementation's cmdfunc. For this reason, we can
+ * ignore the chip enable bit and concentrate only on sending bytes to the
+ * NAND Flash.
+ *
+ * @mtd:   The owning MTD.
+ * @data:  The value to push onto the data signals.
+ * @ctrl:  The values to push onto the control signals.
+ */
+static void mil_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
+{
+	struct nand_chip      *nand = mtd->priv;
+	struct gpmi_nfc_data  *this = nand->priv;
+	struct device         *dev  =  this->dev;
+	struct mil            *mil  = &this->mil;
+	struct nfc_hal        *nfc  =  this->nfc;
+	int                   error;
+#if defined(CONFIG_MTD_DEBUG)
+	unsigned int          i;
+	char                  display[MIL_COMMAND_BUFFER_SIZE * 5];
+#endif
+
+	/*
+	 * Every operation begins with a command byte and a series of zero or
+	 * more address bytes. These are distinguished by either the Address
+	 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
+	 * asserted. When MTD is ready to execute the command, it will deassert
+	 * both latch enables.
+	 *
+	 * Rather than run a separate DMA operation for every single byte, we
+	 * queue them up and run a single DMA operation for the entire series
+	 * of command and data bytes.
+	 */
+
+	if ((ctrl & (NAND_ALE | NAND_CLE))) {
+		if (data != NAND_CMD_NONE)
+			mil->cmd_virt[mil->command_length++] = data;
+		return;
+	}
+
+	/*
+	 * If control arrives here, MTD has deasserted both the ALE and CLE,
+	 * which means it's ready to run an operation. Check if we have any
+	 * bytes to send.
+	 */
+
+	if (!mil->command_length)
+		return;
+
+	/* Hand the command over to the NFC. */
+
+	gpmi_nfc_add_event("mil_cmd_ctrl sending command...", 1);
+
+#if defined(CONFIG_MTD_DEBUG)
+	display[0] = 0;
+	for (i = 0; i < mil->command_length; i++)
+		sprintf(display + strlen(display), " 0x%02x",
+						mil->cmd_virt[i] & 0xff);
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc cmd_ctrl] command: %s\n", display);
+#endif
+
+	error = nfc->send_command(this,
+			mil->current_chip, mil->cmd_phys, mil->command_length);
+
+	if (error) {
+		dev_err(dev, "[%s] Chip: %u, Error %d\n",
+					__func__, mil->current_chip, error);
+		print_hex_dump(KERN_ERR,
+			"    Command Bytes: ", DUMP_PREFIX_NONE, 16, 1,
+					mil->cmd_virt, mil->command_length, 0);
+	}
+
+	gpmi_nfc_add_event("...Finished", -1);
+
+	/* Reset. */
+
+	mil->command_length = 0;
+
+}
+
+/**
+ * mil_dev_ready() - MTD Interface dev_ready()
+ *
+ * @mtd:   A pointer to the owning MTD.
+ */
+static int mil_dev_ready(struct mtd_info *mtd)
+{
+	struct nand_chip      *nand = mtd->priv;
+	struct gpmi_nfc_data  *this = nand->priv;
+	struct nfc_hal        *nfc  = this->nfc;
+	struct mil            *mil  = &this->mil;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc dev_ready]\n");
+
+	gpmi_nfc_add_event("> mil_dev_ready", 1);
+
+	if (nfc->is_ready(this, mil->current_chip)) {
+		gpmi_nfc_add_event("< mil_dev_ready - Returning ready", -1);
+		return !0;
+	} else {
+		gpmi_nfc_add_event("< mil_dev_ready - Returning busy", -1);
+		return 0;
+	}
+
+}
+
+/**
+ * mil_select_chip() - MTD Interface select_chip()
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @chip:  The chip number to select, or -1 to select no chip.
+ */
+static void mil_select_chip(struct mtd_info *mtd, int chip)
+{
+	struct nand_chip      *nand  = mtd->priv;
+	struct gpmi_nfc_data  *this  = nand->priv;
+	struct mil            *mil   = &this->mil;
+	struct nfc_hal        *nfc   =  this->nfc;
+	struct clk            *clock =  this->resources.clock;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc select_chip] chip: %d\n", chip);
+
+	/* Figure out what kind of transition this is. */
+
+	if ((mil->current_chip < 0) && (chip >= 0)) {
+		gpmi_nfc_start_event_trace("> mil_select_chip");
+		clk_enable(clock);
+		nfc->begin(this);
+		gpmi_nfc_add_event("< mil_select_chip", -1);
+	} else if ((mil->current_chip >= 0) && (chip < 0)) {
+		gpmi_nfc_add_event("> mil_select_chip", 1);
+		clk_disable(clock);
+		nfc->end(this);
+		gpmi_nfc_stop_event_trace("< mil_select_chip");
+	} else {
+		gpmi_nfc_add_event("> mil_select_chip", 1);
+		gpmi_nfc_add_event("< mil_select_chip", -1);
+	}
+
+	mil->current_chip = chip;
+
+}
+
+/**
+ * mil_read_buf() - MTD Interface read_buf().
+ *
+ * @mtd:  A pointer to the owning MTD.
+ * @buf:  The destination buffer.
+ * @len:  The number of bytes to read.
+ */
+static void mil_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	struct nand_chip      *nand     = mtd->priv;
+	struct gpmi_nfc_data  *this     = nand->priv;
+	struct device         *dev      =  this->dev;
+	struct nfc_hal        *nfc      =  this->nfc;
+	struct nfc_geometry   *nfc_geo  = &this->nfc_geometry;
+	struct mil            *mil      = &this->mil;
+	void                  *use_virt =  0;
+	dma_addr_t            use_phys  = ~0;
+	int                   error;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc readbuf] len: %d\n", len);
+
+	gpmi_nfc_add_event("> mil_read_buf", 1);
+
+	/* Set up DMA. */
+
+	error = mil_incoming_buffer_dma_begin(this, buf, len,
+					mil->payload_virt, mil->payload_phys,
+					nfc_geo->payload_size_in_bytes,
+					&use_virt, &use_phys);
+
+	if (error) {
+		dev_err(dev, "[%s] Inadequate DMA buffer\n", __func__);
+		goto exit;
+	}
+
+	/* Ask the NFC. */
+
+	nfc->read_data(this, mil->current_chip, use_phys, len);
+
+	/* Finish with DMA. */
+
+	mil_incoming_buffer_dma_end(this, buf, len,
+					mil->payload_virt, mil->payload_phys,
+					nfc_geo->payload_size_in_bytes,
+					use_virt, use_phys);
+
+	/* Return. */
+
+exit:
+
+	gpmi_nfc_add_event("< mil_read_buf", -1);
+
+}
+
+/**
+ * mil_write_buf() - MTD Interface write_buf().
+ *
+ * @mtd:  A pointer to the owning MTD.
+ * @buf:  The source buffer.
+ * @len:  The number of bytes to read.
+ */
+static void mil_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+	struct nand_chip      *nand     = mtd->priv;
+	struct gpmi_nfc_data  *this     = nand->priv;
+	struct device         *dev      =  this->dev;
+	struct nfc_hal        *nfc      =  this->nfc;
+	struct nfc_geometry   *nfc_geo  = &this->nfc_geometry;
+	struct mil            *mil      = &this->mil;
+	const void            *use_virt =  0;
+	dma_addr_t            use_phys  = ~0;
+	int                   error;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc writebuf] len: %d\n", len);
+
+	gpmi_nfc_add_event("> mil_write_buf", 1);
+
+	/* Set up DMA. */
+
+	error = mil_outgoing_buffer_dma_begin(this, buf, len,
+					mil->payload_virt, mil->payload_phys,
+					nfc_geo->payload_size_in_bytes,
+					&use_virt, &use_phys);
+
+	if (error) {
+		dev_err(dev, "[%s] Inadequate DMA buffer\n", __func__);
+		goto exit;
+	}
+
+	/* Ask the NFC. */
+
+	nfc->send_data(this, mil->current_chip, use_phys, len);
+
+	/* Finish with DMA. */
+
+	mil_outgoing_buffer_dma_end(this, buf, len,
+					mil->payload_virt, mil->payload_phys,
+					nfc_geo->payload_size_in_bytes,
+					use_virt, use_phys);
+
+	/* Return. */
+
+exit:
+
+	gpmi_nfc_add_event("< mil_write_buf", -1);
+
+}
+
+/**
+ * mil_read_byte() - MTD Interface read_byte().
+ *
+ * @mtd:  A pointer to the owning MTD.
+ */
+static uint8_t mil_read_byte(struct mtd_info *mtd)
+{
+	uint8_t  byte;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc read_byte]\n");
+
+	gpmi_nfc_add_event("> mil_read_byte", 1);
+
+	mil_read_buf(mtd, (uint8_t *) &byte, 1);
+
+	gpmi_nfc_add_event("< mil_read_byte", -1);
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc read_byte]: 0x%02x\n", byte);
+
+	return byte;
+
+}
+
+/**
+ * mil_handle_block_mark_swapping() - Handles block mark swapping.
+ *
+ * Note that, when this function is called, it doesn't know whether it's
+ * swapping the block mark, or swapping it *back* -- but it doesn't matter
+ * because the the operation is the same.
+ *
+ * @this:       Per-device data.
+ * @payload:    A pointer to the payload buffer.
+ * @auxiliary:  A pointer to the auxiliary buffer.
+ */
+static void mil_handle_block_mark_swapping(struct gpmi_nfc_data *this,
+						void *payload, void *auxiliary)
+{
+	struct nfc_geometry     *nfc_geo = &this->nfc_geometry;
+	struct boot_rom_helper  *rom     =  this->rom;
+	unsigned char           *p;
+	unsigned char           *a;
+	unsigned int            bit;
+	unsigned char           mask;
+	unsigned char           from_data;
+	unsigned char           from_oob;
+
+	/* Check if we're doing block mark swapping. */
+
+	if (!rom->swap_block_mark)
+		return;
+
+	/*
+	 * If control arrives here, we're swapping. Make some convenience
+	 * variables.
+	 */
+
+	bit = nfc_geo->block_mark_bit_offset;
+	p   = ((unsigned char *) payload) + nfc_geo->block_mark_byte_offset;
+	a   = auxiliary;
+
+	/*
+	 * Get the byte from the data area that overlays the block mark. Since
+	 * the ECC engine applies its own view to the bits in the page, the
+	 * physical block mark won't (in general) appear on a byte boundary in
+	 * the data.
+	 */
+
+	from_data = (p[0] >> bit) | (p[1] << (8 - bit));
+
+	/* Get the byte from the OOB. */
+
+	from_oob = a[0];
+
+	/* Swap them. */
+
+	a[0] = from_data;
+
+	mask = (0x1 << bit) - 1;
+	p[0] = (p[0] & mask) | (from_oob << bit);
+
+	mask = ~0 << bit;
+	p[1] = (p[1] & mask) | (from_oob >> (8 - bit));
+
+}
+
+/**
+ * mil_ecc_read_page() - MTD Interface ecc.read_page().
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @nand:  A pointer to the owning NAND Flash MTD.
+ * @buf:   A pointer to the destination buffer.
+ */
+static int mil_ecc_read_page(struct mtd_info *mtd,
+					struct nand_chip *nand, uint8_t *buf)
+{
+	struct gpmi_nfc_data    *this    = nand->priv;
+	struct device           *dev     =  this->dev;
+	struct nfc_hal          *nfc     =  this->nfc;
+	struct nfc_geometry     *nfc_geo = &this->nfc_geometry;
+	struct mil              *mil     = &this->mil;
+	void                    *payload_virt   =  0;
+	dma_addr_t              payload_phys    = ~0;
+	void                    *auxiliary_virt =  0;
+	dma_addr_t              auxiliary_phys  = ~0;
+	unsigned int            i;
+	unsigned char           *status;
+	unsigned int            failed;
+	unsigned int            corrected;
+	int                     error = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc ecc_read_page]\n");
+
+	gpmi_nfc_add_event("> mil_ecc_read_page", 1);
+
+	/*
+	 * Set up DMA.
+	 *
+	 * Notice that we don't try to use the caller's buffer as the auxiliary.
+	 * We need to do a lot of fiddling to deliver the OOB, so there's no
+	 * point.
+	 */
+
+	error = mil_incoming_buffer_dma_begin(this, buf, mtd->writesize,
+					mil->payload_virt, mil->payload_phys,
+					nfc_geo->payload_size_in_bytes,
+					&payload_virt, &payload_phys);
+
+	if (error) {
+		dev_err(dev, "[%s] Inadequate DMA buffer\n", __func__);
+		error = -ENOMEM;
+		goto exit_payload;
+	}
+
+	auxiliary_virt = mil->auxiliary_virt;
+	auxiliary_phys = mil->auxiliary_phys;
+
+	/* Ask the NFC. */
+
+	error = nfc->read_page(this, mil->current_chip,
+						payload_phys, auxiliary_phys);
+
+	if (error) {
+		dev_err(dev, "[%s] Error in ECC-based read: %d\n",
+							__func__, error);
+		goto exit_nfc;
+	}
+
+	/* Handle block mark swapping. */
+
+	mil_handle_block_mark_swapping(this, payload_virt, auxiliary_virt);
+
+	/* Loop over status bytes, accumulating ECC status. */
+
+	failed    = 0;
+	corrected = 0;
+
+	status = ((unsigned char *) auxiliary_virt) +
+					nfc_geo->auxiliary_status_offset;
+
+	for (i = 0; i < nfc_geo->ecc_chunk_count; i++, status++) {
+
+		if ((*status == 0x00) || (*status == 0xff))
+			continue;
+
+		if (*status == 0xfe) {
+			failed++;
+			continue;
+		}
+
+		corrected += *status;
+
+	}
+
+	/* Propagate ECC status to the owning MTD. */
+
+	mtd->ecc_stats.failed    += failed;
+	mtd->ecc_stats.corrected += corrected;
+
+	/*
+	 * It's time to deliver the OOB bytes. See mil_ecc_read_oob() for
+	 * details about our policy for delivering the OOB.
+	 *
+	 * We fill the caller's buffer with set bits, and then copy the block
+	 * mark to th caller's buffer. Note that, if block mark swapping was
+	 * necessary, it has already been done, so we can rely on the first
+	 * byte of the auxiliary buffer to contain the block mark.
+	 */
+
+	memset(nand->oob_poi, ~0, mtd->oobsize);
+
+	nand->oob_poi[0] = ((uint8_t *) auxiliary_virt)[0];
+
+	/* Return. */
+
+exit_nfc:
+	mil_incoming_buffer_dma_end(this, buf, mtd->writesize,
+					mil->payload_virt, mil->payload_phys,
+					nfc_geo->payload_size_in_bytes,
+					payload_virt, payload_phys);
+exit_payload:
+
+	gpmi_nfc_add_event("< mil_ecc_read_page", -1);
+
+	return error;
+
+}
+
+/**
+ * mil_ecc_write_page() - MTD Interface ecc.write_page().
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @nand:  A pointer to the owning NAND Flash MTD.
+ * @buf:   A pointer to the source buffer.
+ */
+static void mil_ecc_write_page(struct mtd_info *mtd,
+				struct nand_chip *nand, const uint8_t *buf)
+{
+	struct gpmi_nfc_data    *this    = nand->priv;
+	struct device           *dev     =  this->dev;
+	struct nfc_hal          *nfc     =  this->nfc;
+	struct nfc_geometry     *nfc_geo = &this->nfc_geometry;
+	struct boot_rom_helper  *rom     =  this->rom;
+	struct mil              *mil     = &this->mil;
+	const void              *payload_virt   =  0;
+	dma_addr_t              payload_phys    = ~0;
+	const void              *auxiliary_virt =  0;
+	dma_addr_t              auxiliary_phys  = ~0;
+	int                     error;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc ecc_write_page]\n");
+
+	gpmi_nfc_add_event("> mil_ecc_write_page", 1);
+
+	/* Set up DMA. */
+
+	if (rom->swap_block_mark) {
+
+		/*
+		 * If control arrives here, we're doing block mark swapping.
+		 * Since we can't modify the caller's buffers, we must copy them
+		 * into our own.
+		 */
+
+		memcpy(mil->payload_virt, buf, mtd->writesize);
+		payload_virt = mil->payload_virt;
+		payload_phys = mil->payload_phys;
+
+		memcpy(mil->auxiliary_virt, nand->oob_poi, mtd->oobsize);
+		auxiliary_virt = mil->auxiliary_virt;
+		auxiliary_phys = mil->auxiliary_phys;
+
+		/* Handle block mark swapping. */
+
+		mil_handle_block_mark_swapping(this,
+				(void *) payload_virt, (void *) auxiliary_virt);
+
+	} else {
+
+		/*
+		 * If control arrives here, we're not doing block mark swapping,
+		 * so we can to try and use the caller's buffers.
+		 */
+
+		error = mil_outgoing_buffer_dma_begin(this,
+				buf, mtd->writesize,
+				mil->payload_virt, mil->payload_phys,
+				nfc_geo->payload_size_in_bytes,
+				&payload_virt, &payload_phys);
+
+		if (error) {
+			dev_err(dev, "[%s] Inadequate payload DMA buffer\n",
+								__func__);
+			goto exit_payload;
+		}
+
+		error = mil_outgoing_buffer_dma_begin(this,
+				nand->oob_poi, mtd->oobsize,
+				mil->auxiliary_virt, mil->auxiliary_phys,
+				nfc_geo->auxiliary_size_in_bytes,
+				&auxiliary_virt, &auxiliary_phys);
+
+		if (error) {
+			dev_err(dev, "[%s] Inadequate auxiliary DMA buffer\n",
+								__func__);
+			goto exit_auxiliary;
+		}
+
+	}
+
+	/* Ask the NFC. */
+
+	error = nfc->send_page(this, mil->current_chip,
+						payload_phys, auxiliary_phys);
+
+	if (error)
+		dev_err(dev, "[%s] Error in ECC-based write: %d\n",
+							__func__, error);
+
+	/* Return. */
+
+	if (!rom->swap_block_mark)
+		mil_outgoing_buffer_dma_end(this, nand->oob_poi, mtd->oobsize,
+				mil->auxiliary_virt, mil->auxiliary_phys,
+				nfc_geo->auxiliary_size_in_bytes,
+				auxiliary_virt, auxiliary_phys);
+exit_auxiliary:
+	if (!rom->swap_block_mark)
+		mil_outgoing_buffer_dma_end(this, buf, mtd->writesize,
+				mil->payload_virt, mil->payload_phys,
+				nfc_geo->payload_size_in_bytes,
+				payload_virt, payload_phys);
+exit_payload:
+
+	gpmi_nfc_add_event("< mil_ecc_write_page", -1);
+
+}
+
+/**
+ * mil_hook_read_oob() - Hooked MTD Interface read_oob().
+ *
+ * This function is a veneer that replaces the function originally installed by
+ * the NAND Flash MTD code. See the description of the raw_oob_mode field in
+ * struct mil for more information about this.
+ *
+ * @mtd:   A pointer to the MTD.
+ * @from:  The starting address to read.
+ * @ops:   Describes the operation.
+ */
+static int mil_hook_read_oob(struct mtd_info *mtd,
+					loff_t from, struct mtd_oob_ops *ops)
+{
+	register struct nand_chip  *chip = mtd->priv;
+	struct gpmi_nfc_data       *this = chip->priv;
+	struct mil                 *mil  = &this->mil;
+	int                        ret;
+
+	mil->raw_oob_mode = ops->mode == MTD_OOB_RAW;
+	ret = mil->hooked_read_oob(mtd, from, ops);
+	mil->raw_oob_mode = false;
+	return ret;
+}
+
+/**
+ * mil_hook_write_oob() - Hooked MTD Interface write_oob().
+ *
+ * This function is a veneer that replaces the function originally installed by
+ * the NAND Flash MTD code. See the description of the raw_oob_mode field in
+ * struct mil for more information about this.
+ *
+ * @mtd:   A pointer to the MTD.
+ * @to:    The starting address to write.
+ * @ops:   Describes the operation.
+ */
+static int mil_hook_write_oob(struct mtd_info *mtd,
+					loff_t to, struct mtd_oob_ops *ops)
+{
+	register struct nand_chip  *chip = mtd->priv;
+	struct gpmi_nfc_data       *this = chip->priv;
+	struct mil                 *mil  = &this->mil;
+	int                        ret;
+
+	mil->raw_oob_mode = ops->mode == MTD_OOB_RAW;
+	ret = mil->hooked_write_oob(mtd, to, ops);
+	mil->raw_oob_mode = false;
+	return ret;
+}
+
+/**
+ * mil_hook_block_markbad() - Hooked MTD Interface block_markbad().
+ *
+ * This function is a veneer that replaces the function originally installed by
+ * the NAND Flash MTD code. See the description of the marking_a_bad_block field
+ * in struct mil for more information about this.
+ *
+ * @mtd:  A pointer to the MTD.
+ * @ofs:  Byte address of the block to mark.
+ */
+static int mil_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+	register struct nand_chip  *chip = mtd->priv;
+	struct gpmi_nfc_data       *this = chip->priv;
+	struct mil                 *mil  = &this->mil;
+	int                        ret;
+
+	mil->marking_a_bad_block = true;
+	ret = mil->hooked_block_markbad(mtd, ofs);
+	mil->marking_a_bad_block = false;
+	return ret;
+}
+
+/**
+ * mil_ecc_read_oob() - MTD Interface ecc.read_oob().
+ *
+ * There are several places in this driver where we have to handle the OOB and
+ * block marks. This is the function where things are the most complicated, so
+ * this is where we try to explain it all. All the other places refer back to
+ * here.
+ *
+ * These are the rules, in order of decreasing importance:
+ *
+ * 1) Nothing the caller does can be allowed to imperil the block mark, so all
+ *    write operations take measures to protect it.
+ *
+ * 2) In read operations, the first byte of the OOB we return must reflect the
+ *    true state of the block mark, no matter where that block mark appears in
+ *    the physical page.
+ *
+ * 3) ECC-based read operations return an OOB full of set bits (since we never
+ *    allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
+ *    return).
+ *
+ * 4) "Raw" read operations return a direct view of the physical bytes in the
+ *    page, using the conventional definition of which bytes are data and which
+ *    are OOB. This gives the caller a way to see the actual, physical bytes
+ *    in the page, without the distortions applied by our ECC engine.
+ *
+ *
+ * What we do for this specific read operation depends on two questions:
+ *
+ * 1) Are we doing a "raw" read, or an ECC-based read?
+ *
+ * 2) Are we using block mark swapping or transcription?
+ *
+ * There are four cases, illustrated by the following Karnaugh map:
+ *
+ *                    |           Raw           |         ECC-based       |
+ *       -------------+-------------------------+-------------------------+
+ *                    | Read the conventional   |                         |
+ *                    | OOB at the end of the   |                         |
+ *       Swapping     | page and return it. It  |                         |
+ *                    | contains exactly what   |                         |
+ *                    | we want.                | Read the block mark and |
+ *       -------------+-------------------------+ return it in a buffer   |
+ *                    | Read the conventional   | full of set bits.       |
+ *                    | OOB at the end of the   |                         |
+ *                    | page and also the block |                         |
+ *       Transcribing | mark in the metadata.   |                         |
+ *                    | Copy the block mark     |                         |
+ *                    | into the first byte of  |                         |
+ *                    | the OOB.                |                         |
+ *       -------------+-------------------------+-------------------------+
+ *
+ * Note that we break rule #4 in the Transcribing/Raw case because we're not
+ * giving an accurate view of the actual, physical bytes in the page (we're
+ * overwriting the block mark). That's OK because it's more important to follow
+ * rule #2.
+ *
+ * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
+ * easy. When reading a page, for example, the NAND Flash MTD code calls our
+ * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
+ * ECC-based or raw view of the page is implicit in which function it calls
+ * (there is a similar pair of ECC-based/raw functions for writing).
+ *
+ * Since MTD assumes the OOB is not covered by ECC, there is no pair of
+ * ECC-based/raw functions for reading or or writing the OOB. The fact that the
+ * caller wants an ECC-based or raw view of the page is not propagated down to
+ * this driver.
+ *
+ * Since our OOB *is* covered by ECC, we need this information. So, we hook the
+ * ecc.read_oob and ecc.write_oob function pointers in the owning
+ * struct mtd_info with our own functions. These hook functions set the
+ * raw_oob_mode field so that, when control finally arrives here, we'll know
+ * what to do.
+ *
+ * @mtd:     A pointer to the owning MTD.
+ * @nand:    A pointer to the owning NAND Flash MTD.
+ * @page:    The page number to read.
+ * @sndcmd:  Indicates this function should send a command to the chip before
+ *           reading the out-of-band bytes. This is only false for small page
+ *           chips that support auto-increment.
+ */
+static int mil_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
+							int page, int sndcmd)
+{
+	struct gpmi_nfc_data      *this     = nand->priv;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct mil                *mil      = &this->mil;
+	struct boot_rom_helper    *rom      =  this->rom;
+	int                       block_mark_column;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc ecc_read_oob] "
+		"page: 0x%06x, sndcmd: %s\n", page, sndcmd ? "Yes" : "No");
+
+	gpmi_nfc_add_event("> mil_ecc_read_oob", 1);
+
+	/*
+	 * First, fill in the OOB buffer. If we're doing a raw read, we need to
+	 * get the bytes from the physical page. If we're not doing a raw read,
+	 * we need to fill the buffer with set bits.
+	 */
+
+	if (mil->raw_oob_mode) {
+
+		/*
+		 * If control arrives here, we're doing a "raw" read. Send the
+		 * command to read the conventional OOB.
+		 */
+
+		nand->cmdfunc(mtd, NAND_CMD_READ0,
+				physical->page_data_size_in_bytes, page);
+
+		/* Read out the conventional OOB. */
+
+		nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
+
+	} else {
+
+		/*
+		 * If control arrives here, we're not doing a "raw" read. Fill
+		 * the OOB buffer with set bits.
+		 */
+
+		memset(nand->oob_poi, ~0, mtd->oobsize);
+
+	}
+
+	/*
+	 * Now, we want to make sure the block mark is correct. In the
+	 * Swapping/Raw case, we already have it. Otherwise, we need to
+	 * explicitly read it.
+	 */
+
+	if (!(rom->swap_block_mark && mil->raw_oob_mode)) {
+
+		/* First, figure out where the block mark is. */
+
+		if (rom->swap_block_mark)
+			block_mark_column = physical->page_data_size_in_bytes;
+		else
+			block_mark_column = 0;
+
+		/* Send the command to read the block mark. */
+
+		nand->cmdfunc(mtd, NAND_CMD_READ0, block_mark_column, page);
+
+		/* Read the block mark into the first byte of the OOB buffer. */
+
+		nand->oob_poi[0] = nand->read_byte(mtd);
+
+	}
+
+	/*
+	 * Return true, indicating that the next call to this function must send
+	 * a command.
+	 */
+
+	gpmi_nfc_add_event("< mil_ecc_read_oob", -1);
+
+	return true;
+
+}
+
+/**
+ * mil_ecc_write_oob() - MTD Interface ecc.write_oob().
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @nand:  A pointer to the owning NAND Flash MTD.
+ * @page:  The page number to write.
+ */
+static int mil_ecc_write_oob(struct mtd_info *mtd,
+					struct nand_chip *nand, int page)
+{
+	struct gpmi_nfc_data      *this     = nand->priv;
+	struct device             *dev      =  this->dev;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct mil                *mil      = &this->mil;
+	struct boot_rom_helper    *rom      =  this->rom;
+	uint8_t                   block_mark = 0;
+	int                       block_mark_column;
+	int                       status;
+	int                       error = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL2,
+			"[gpmi_nfc ecc_write_oob] page: 0x%06x\n", page);
+
+	gpmi_nfc_add_event("> mil_ecc_write_oob", -1);
+
+	/*
+	 * There are fundamental incompatibilities between the i.MX GPMI NFC and
+	 * the NAND Flash MTD model that make it essentially impossible to write
+	 * the out-of-band bytes.
+	 *
+	 * We permit *ONE* exception. If the *intent* of writing the OOB is to
+	 * mark a block bad, we can do that.
+	 */
+
+	if (!mil->marking_a_bad_block) {
+		dev_emerg(dev, "This driver doesn't support writing the OOB\n");
+		WARN_ON(1);
+		error = -EIO;
+		goto exit;
+	}
+
+	/*
+	 * If control arrives here, we're marking a block bad. First, figure out
+	 * where the block mark is.
+	 *
+	 * If we're using swapping, the block mark is in the conventional
+	 * location. Otherwise, we're using transcription, and the block mark
+	 * appears in the first byte of the page.
+	 */
+
+	if (rom->swap_block_mark)
+		block_mark_column = physical->page_data_size_in_bytes;
+	else
+		block_mark_column = 0;
+
+	/* Write the block mark. */
+
+	nand->cmdfunc(mtd, NAND_CMD_SEQIN, block_mark_column, page);
+	nand->write_buf(mtd, &block_mark, 1);
+	nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+	status = nand->waitfunc(mtd, nand);
+
+	/* Check if it worked. */
+
+	if (status & NAND_STATUS_FAIL)
+		error = -EIO;
+
+	/* Return. */
+
+exit:
+
+	gpmi_nfc_add_event("< mil_ecc_write_oob", -1);
+
+	return error;
+
+}
+
+/**
+ * mil_block_bad - Claims all blocks are good.
+ *
+ * In principle, this function is *only* called when the NAND Flash MTD system
+ * isn't allowed to keep an in-memory bad block table, so it is forced to ask
+ * the driver for bad block information.
+ *
+ * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
+ * this function is *only* called when we take it away.
+ *
+ * We take away the in-memory BBT when the user sets the "ignorebad" parameter,
+ * which indicates that all blocks should be reported good.
+ *
+ * Thus, this function is only called when we want *all* blocks to look good,
+ * so it *always* return success.
+ *
+ * @mtd:      Ignored.
+ * @ofs:      Ignored.
+ * @getchip:  Ignored.
+ */
+static int mil_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+{
+	return 0;
+}
+
+/**
+ * mil_set_physical_geometry() - Set up the physical medium geometry.
+ *
+ * This function retrieves the physical geometry information discovered by
+ * nand_scan(), corrects it, and records it in the per-device data structure.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_set_physical_geometry(struct gpmi_nfc_data  *this)
+{
+	struct mil                *mil      = &this->mil;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct nand_chip          *nand     = &mil->nand;
+	struct nand_device_info   *info     = &this->device_info;
+	unsigned int              block_size_in_pages;
+	unsigned int              chip_size_in_blocks;
+	unsigned int              chip_size_in_pages;
+	uint64_t                  medium_size_in_bytes;
+
+	/*
+	 * Record the number of physical chips that MTD found.
+	 */
+
+	physical->chip_count = nand->numchips;
+
+	/*
+	 * We know the total size of a page. We need to break that down into the
+	 * data size and OOB size. The data size is the largest power of two
+	 * that will fit in the given page size. The OOB size is what's left
+	 * over.
+	 */
+
+	physical->page_data_size_in_bytes =
+				1 << (fls(info->page_total_size_in_bytes) - 1);
+
+	physical->page_oob_size_in_bytes =
+				info->page_total_size_in_bytes -
+					physical->page_data_size_in_bytes;
+
+	/*
+	 * Now that we know the page data size, we can multiply this by the
+	 * number of pages in a block to compute the block size.
+	 */
+
+	physical->block_size_in_bytes =
+		physical->page_data_size_in_bytes * info->block_size_in_pages;
+
+	/* Get the chip size. */
+
+	physical->chip_size_in_bytes = info->chip_size_in_bytes;
+
+	/* Compute some interesting facts. */
+
+	block_size_in_pages  =
+			physical->block_size_in_bytes >>
+				(fls(physical->page_data_size_in_bytes) - 1);
+	chip_size_in_pages   =
+			physical->chip_size_in_bytes >>
+				(fls(physical->page_data_size_in_bytes) - 1);
+	chip_size_in_blocks  =
+			physical->chip_size_in_bytes >>
+				(fls(physical->block_size_in_bytes) - 1);
+	medium_size_in_bytes =
+			physical->chip_size_in_bytes * physical->chip_count;
+
+	/* Report. */
+
+	#if defined(DETAILED_INFO)
+
+	pr_info("-----------------\n");
+	pr_info("Physical Geometry\n");
+	pr_info("-----------------\n");
+	pr_info("Chip Count             : %d\n", physical->chip_count);
+	pr_info("Page Data Size in Bytes: %u (0x%x)\n",
+			physical->page_data_size_in_bytes,
+			physical->page_data_size_in_bytes);
+	pr_info("Page OOB Size in Bytes : %u\n",
+			physical->page_oob_size_in_bytes);
+	pr_info("Block Size in Bytes    : %u (0x%x)\n",
+			physical->block_size_in_bytes,
+			physical->block_size_in_bytes);
+	pr_info("Block Size in Pages    : %u (0x%x)\n",
+			block_size_in_pages,
+			block_size_in_pages);
+	pr_info("Chip Size in Bytes     : %llu (0x%llx)\n",
+			physical->chip_size_in_bytes,
+			physical->chip_size_in_bytes);
+	pr_info("Chip Size in Pages     : %u (0x%x)\n",
+			chip_size_in_pages, chip_size_in_pages);
+	pr_info("Chip Size in Blocks    : %u (0x%x)\n",
+			chip_size_in_blocks, chip_size_in_blocks);
+	pr_info("Medium Size in Bytes   : %llu (0x%llx)\n",
+			medium_size_in_bytes, medium_size_in_bytes);
+
+	#endif
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_set_nfc_geometry() - Set up the NFC geometry.
+ *
+ * This function calls the NFC HAL to select an NFC geometry that is compatible
+ * with the medium's physical geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_set_nfc_geometry(struct gpmi_nfc_data  *this)
+{
+	struct nfc_hal       *nfc =  this->nfc;
+#if defined(DETAILED_INFO)
+	struct nfc_geometry  *geo = &this->nfc_geometry;
+#endif
+	/* Set the NFC geometry. */
+
+	if (nfc->set_geometry(this))
+		return !0;
+
+	/* Report. */
+
+	#if defined(DETAILED_INFO)
+
+	pr_info("------------\n");
+	pr_info("NFC Geometry\n");
+	pr_info("------------\n");
+	pr_info("ECC Algorithm          : %s\n", geo->ecc_algorithm);
+	pr_info("ECC Strength           : %u\n", geo->ecc_strength);
+	pr_info("Page Size in Bytes     : %u\n", geo->page_size_in_bytes);
+	pr_info("Metadata Size in Bytes : %u\n", geo->metadata_size_in_bytes);
+	pr_info("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size_in_bytes);
+	pr_info("ECC Chunk Count        : %u\n", geo->ecc_chunk_count);
+	pr_info("Payload Size in Bytes  : %u\n", geo->payload_size_in_bytes);
+	pr_info("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size_in_bytes);
+	pr_info("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset);
+	pr_info("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset);
+	pr_info("Block Mark Bit Offset  : %u\n", geo->block_mark_bit_offset);
+
+	#endif
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_set_boot_rom_helper_geometry() - Set up the Boot ROM Helper geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_set_boot_rom_helper_geometry(struct gpmi_nfc_data  *this)
+{
+	struct boot_rom_helper    *rom =  this->rom;
+#if defined(DETAILED_INFO)
+	struct boot_rom_geometry  *geo = &this->rom_geometry;
+#endif
+
+	/* Set the Boot ROM Helper geometry. */
+
+	if (rom->set_geometry(this))
+		return !0;
+
+	/* Report. */
+
+	#if defined(DETAILED_INFO)
+
+	pr_info("-----------------\n");
+	pr_info("Boot ROM Geometry\n");
+	pr_info("-----------------\n");
+	pr_info("Boot Area Count            : %u\n", geo->boot_area_count);
+	pr_info("Boot Area Size in Bytes    : %u (0x%x)\n",
+		geo->boot_area_size_in_bytes, geo->boot_area_size_in_bytes);
+	pr_info("Stride Size in Pages       : %u\n", geo->stride_size_in_pages);
+	pr_info("Search Area Stride Exponent: %u\n",
+					geo->search_area_stride_exponent);
+
+	#endif
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_set_mtd_geometry() - Set up the MTD geometry.
+ *
+ * This function adjusts the owning MTD data structures to match the logical
+ * geometry we've chosen.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_set_mtd_geometry(struct gpmi_nfc_data *this)
+{
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct mil                *mil      = &this->mil;
+	struct nand_ecclayout     *layout   = &mil->oob_layout;
+	struct nand_chip          *nand     = &mil->nand;
+	struct mtd_info           *mtd      = &mil->mtd;
+
+	/* Configure the struct nand_ecclayout. */
+
+	layout->eccbytes          = 0;
+	layout->oobavail          = physical->page_oob_size_in_bytes;
+	layout->oobfree[0].offset = 0;
+	layout->oobfree[0].length = physical->page_oob_size_in_bytes;
+
+	/* Configure the struct mtd_info. */
+
+	mtd->size        = nand->numchips * physical->chip_size_in_bytes;
+	mtd->erasesize   = physical->block_size_in_bytes;
+	mtd->writesize   = physical->page_data_size_in_bytes;
+	mtd->ecclayout   = layout;
+	mtd->oobavail    = mtd->ecclayout->oobavail;
+	mtd->oobsize     = mtd->ecclayout->oobavail + mtd->ecclayout->eccbytes;
+	mtd->subpage_sft = 0; /* We don't support sub-page writing. */
+
+	/* Configure the struct nand_chip. */
+
+	nand->chipsize         = physical->chip_size_in_bytes;
+	nand->page_shift       = ffs(mtd->writesize) - 1;
+	nand->pagemask         = (nand->chipsize >> nand->page_shift) - 1;
+	nand->subpagesize      = mtd->writesize >> mtd->subpage_sft;
+	nand->phys_erase_shift = ffs(mtd->erasesize) - 1;
+	nand->bbt_erase_shift  = nand->phys_erase_shift;
+	nand->oob_poi          = nand->buffers->databuf + mtd->writesize;
+	nand->ecc.layout       = layout;
+	if (nand->chipsize & 0xffffffff)
+		nand->chip_shift = ffs((unsigned) nand->chipsize) - 1;
+	else
+		nand->chip_shift =
+				ffs((unsigned) (nand->chipsize >> 32)) + 32 - 1;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_set_geometry() - Set up the medium geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_set_geometry(struct gpmi_nfc_data  *this)
+{
+	struct device        *dev      =  this->dev;
+	struct nfc_geometry  *nfc_geo  = &this->nfc_geometry;
+	struct mil           *mil      = &this->mil;
+
+	/* Set up the various layers of geometry, in this specific order. */
+
+	if (mil_set_physical_geometry(this))
+		return -ENXIO;
+
+	if (mil_set_nfc_geometry(this))
+		return -ENXIO;
+
+	if (mil_set_boot_rom_helper_geometry(this))
+		return -ENXIO;
+
+	if (mil_set_mtd_geometry(this))
+		return -ENXIO;
+
+	/*
+	 * Allocate the page buffer.
+	 *
+	 * Both the payload buffer and the auxiliary buffer must appear on
+	 * 32-bit boundaries. We presume the size of the payload buffer is a
+	 * power of two and is much larger than four, which guarantees the
+	 * auxiliary buffer will appear on a 32-bit boundary.
+	 */
+
+	mil->page_buffer_size = nfc_geo->payload_size_in_bytes +
+					nfc_geo->auxiliary_size_in_bytes;
+
+	mil->page_buffer_virt =
+		dma_alloc_coherent(dev, mil->page_buffer_size,
+					&mil->page_buffer_phys, GFP_DMA);
+
+	if (!mil->page_buffer_virt)
+		return -ENOMEM;
+
+	/* Slice up the page buffer. */
+
+	mil->payload_virt = mil->page_buffer_virt;
+	mil->payload_phys = mil->page_buffer_phys;
+
+	mil->auxiliary_virt = ((char *) mil->payload_virt) +
+						nfc_geo->payload_size_in_bytes;
+	mil->auxiliary_phys = mil->payload_phys +
+						nfc_geo->payload_size_in_bytes;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_pre_bbt_scan() - Prepare for the BBT scan.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_pre_bbt_scan(struct gpmi_nfc_data  *this)
+{
+	struct device             *dev      =  this->dev;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct boot_rom_helper    *rom      =  this->rom;
+	struct mil                *mil      = &this->mil;
+	struct nand_chip          *nand     = &mil->nand;
+	struct mtd_info           *mtd      = &mil->mtd;
+	unsigned int              block_count;
+	unsigned int              block;
+	int                       chip;
+	int                       page;
+	loff_t                    byte;
+	uint8_t                   block_mark;
+	int                       error;
+
+	/*
+	 * Check if we can use block mark swapping, which enables us to leave
+	 * the block marks where they are. If so, we don't need to do anything
+	 * at all.
+	 */
+
+	if (rom->swap_block_mark)
+		return 0;
+
+	/*
+	 * If control arrives here, we can't use block mark swapping, which
+	 * means we're forced to use transcription. First, scan for the
+	 * transcription stamp. If we find it, then we don't have to do
+	 * anything -- the block marks are already transcribed.
+	 */
+
+	if (rom->check_transcription_stamp(this))
+		return 0;
+
+	/*
+	 * If control arrives here, we couldn't find a transcription stamp, so
+	 * so we presume the block marks are in the conventional location.
+	 */
+
+	pr_info("Transcribing bad block marks...\n");
+
+	/* Compute the number of blocks in the entire medium. */
+
+	block_count =
+		physical->chip_size_in_bytes >> nand->phys_erase_shift;
+
+	/*
+	 * Loop over all the blocks in the medium, transcribing block marks as
+	 * we go.
+	 */
+
+	for (block = 0; block < block_count; block++) {
+
+		/*
+		 * Compute the chip, page and byte addresses for this block's
+		 * conventional mark.
+		 */
+
+		chip = block >> (nand->chip_shift - nand->phys_erase_shift);
+		page = block << (nand->phys_erase_shift - nand->page_shift);
+		byte = block <<  nand->phys_erase_shift;
+
+		/* Select the chip. */
+
+		nand->select_chip(mtd, chip);
+
+		/* Send the command to read the conventional block mark. */
+
+		nand->cmdfunc(mtd, NAND_CMD_READ0,
+				physical->page_data_size_in_bytes, page);
+
+		/* Read the conventional block mark. */
+
+		block_mark = nand->read_byte(mtd);
+
+		/*
+		 * Check if the block is marked bad. If so, we need to mark it
+		 * again, but this time the result will be a mark in the
+		 * location where we transcribe block marks.
+		 *
+		 * Notice that we have to explicitly set the marking_a_bad_block
+		 * member before we call through the block_markbad function
+		 * pointer in the owning struct nand_chip. If we could call
+		 * though the block_markbad function pointer in the owning
+		 * struct mtd_info, which we have hooked, then this would be
+		 * taken care of for us. Unfortunately, we can't because that
+		 * higher-level code path will do things like consulting the
+		 * in-memory bad block table -- which doesn't even exist yet!
+		 * So, we have to call at a lower level and handle some details
+		 * ourselves.
+		 */
+
+		if (block_mark != 0xff) {
+			pr_info("Transcribing mark in block %u\n", block);
+			mil->marking_a_bad_block = true;
+			error = nand->block_markbad(mtd, byte);
+			mil->marking_a_bad_block = false;
+			if (error)
+				dev_err(dev, "Failed to mark block bad with "
+							"error %d\n", error);
+		}
+
+		/* Deselect the chip. */
+
+		nand->select_chip(mtd, -1);
+
+	}
+
+	/* Write the stamp that indicates we've transcribed the block marks. */
+
+	rom->write_transcription_stamp(this);
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_scan_bbt() - MTD Interface scan_bbt().
+ *
+ * The HIL calls this function once, when it initializes the NAND Flash MTD.
+ *
+ * Nominally, the purpose of this function is to look for or create the bad
+ * block table. In fact, since the HIL calls this function at the very end of
+ * the initialization process started by nand_scan(), and the HIL doesn't have a
+ * more formal mechanism, everyone "hooks" this function to continue the
+ * initialization process.
+ *
+ * At this point, the physical NAND Flash chips have been identified and
+ * counted, so we know the physical geometry. This enables us to make some
+ * important configuration decisions.
+ *
+ * The return value of this function propogates directly back to this driver's
+ * call to nand_scan(). Anything other than zero will cause this driver to
+ * tear everything down and declare failure.
+ *
+ * @mtd:  A pointer to the owning MTD.
+ */
+static int mil_scan_bbt(struct mtd_info *mtd)
+{
+	struct nand_chip         *nand = mtd->priv;
+	struct gpmi_nfc_data     *this = nand->priv;
+	struct nfc_hal           *nfc  =  this->nfc;
+	struct mil               *mil  = &this->mil;
+	int                      saved_chip_number;
+	uint8_t                  id_bytes[NAND_DEVICE_ID_BYTE_COUNT];
+	struct nand_device_info  *info;
+	struct gpmi_nfc_timing   timing;
+	int                      error;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc scan_bbt] \n");
+
+	/*
+	 * Tell MTD users that the out-of-band area can't be written.
+	 *
+	 * This flag is not part of the standard kernel source tree. It comes
+	 * from a patch that touches both MTD and JFFS2.
+	 *
+	 * The problem is that, without this patch, JFFS2 believes it can write
+	 * the data area and the out-of-band area separately. This is wrong for
+	 * two reasons:
+	 *
+	 *     1)  Our NFC distributes out-of-band bytes throughout the page,
+	 *         intermingled with the data, and covered by the same ECC.
+	 *         Thus, it's not possible to write the out-of-band bytes and
+	 *         data bytes separately.
+	 *
+	 *     2)  Large page (MLC) Flash chips don't support partial page
+	 *         writes. You must write the entire page at a time. Thus, even
+	 *         if our NFC didn't force you to write out-of-band and data
+	 *         bytes together, it would *still* be a bad idea to do
+	 *         otherwise.
+	 */
+
+	mtd->flags &= ~MTD_OOB_WRITEABLE;
+
+	/*
+	 * MTD identified the attached NAND Flash devices, but we have a much
+	 * better database that we want to consult. First, we need to gather all
+	 * the ID bytes from the first chip (MTD only read the first two).
+	 */
+
+	saved_chip_number = mil->current_chip;
+	nand->select_chip(mtd, 0);
+
+	nand->cmdfunc(mtd, NAND_CMD_READID, 0, -1);
+	nand->read_buf(mtd, id_bytes, NAND_DEVICE_ID_BYTE_COUNT);
+
+	nand->select_chip(mtd, saved_chip_number);
+
+	/* Look up this device in our database. */
+
+	info = nand_device_get_info(id_bytes);
+
+	/* Check if we understand this device. */
+
+	if (!info) {
+		pr_err("Unrecognized NAND Flash device.\n");
+		return !0;
+	}
+
+	/* Display the information we discovered. */
+
+	#if defined(DETAILED_INFO)
+	pr_info("-----------------------------\n");
+	pr_info("NAND Flash Device Information\n");
+	pr_info("-----------------------------\n");
+	nand_device_print_info(info);
+	#endif
+
+	/*
+	 * Copy the device info into the per-device data. We can't just keep
+	 * the pointer because that storage is reclaimed after initialization.
+	 */
+
+	this->device_info = *info;
+	this->device_info.description = kstrdup(info->description, GFP_KERNEL);
+
+	/* Set up geometry. */
+
+	error = mil_set_geometry(this);
+
+	if (error)
+		return error;
+
+	/* Set up timing. */
+
+	timing.data_setup_in_ns        = info->data_setup_in_ns;
+	timing.data_hold_in_ns         = info->data_hold_in_ns;
+	timing.address_setup_in_ns     = info->address_setup_in_ns;
+	timing.gpmi_sample_delay_in_ns = info->gpmi_sample_delay_in_ns;
+	timing.tREA_in_ns              = info->tREA_in_ns;
+	timing.tRLOH_in_ns             = info->tRLOH_in_ns;
+	timing.tRHOH_in_ns             = info->tRHOH_in_ns;
+
+	error = nfc->set_timing(this, &timing);
+
+	if (error)
+		return error;
+
+	/* Prepare for the BBT scan. */
+
+	error = mil_pre_bbt_scan(this);
+
+	if (error)
+		return error;
+
+	/* We use the reference implementation for bad block management. */
+
+	error = nand_default_bbt(mtd);
+
+	if (error)
+		return error;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_boot_areas_init() - Initializes boot areas.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_boot_areas_init(struct gpmi_nfc_data *this)
+{
+	struct device                  *dev      =  this->dev;
+	struct physical_geometry       *physical = &this->physical_geometry;
+	struct boot_rom_geometry       *rom      = &this->rom_geometry;
+	struct mil                     *mil      = &this->mil;
+	struct mtd_info                *mtd      = &mil->mtd;
+	struct nand_chip               *nand     = &mil->nand;
+	int                            mtd_support_is_adequate;
+	unsigned int                   i;
+	struct mtd_partition           partitions[4];
+	struct mtd_info                *search_mtd;
+	struct mtd_info                *chip_0_remainder_mtd = 0;
+	struct mtd_info                *medium_remainder_mtd = 0;
+	struct mtd_info                *concatenate[2];
+
+	/*
+	 * Here we declare the static strings we use to name partitions. We use
+	 * static strings because, as of 2.6.31, the partitioning code *always*
+	 * registers the partition MTDs it creates and leaves behind *no* other
+	 * trace of its work. So, once we've created a partition, we must search
+	 * the master MTD table to find the MTDs we created. Since we're using
+	 * static strings, we can simply search the master table for an MTD with
+	 * a name field pointing to a known address.
+	 */
+
+	static char  *chip_0_boot_name      = "gpmi-nfc-0-boot";
+	static char  *chip_0_remainder_name = "gpmi-nfc-0-remainder";
+	static char  *chip_1_boot_name      = "gpmi-nfc-1-boot";
+	static char  *medium_remainder_name = "gpmi-nfc-remainder";
+	static char  *general_use_name      = "gpmi-nfc-general-use";
+
+	/* Check if we're protecting the boot areas.*/
+
+	if (!rom->boot_area_count) {
+
+		/*
+		 * If control arrives here, we're not protecting the boot areas.
+		 * In this case, there are not boot area partitons, and the main
+		 * MTD is the general use MTD.
+		 */
+
+		mil->general_use_mtd = &mil->mtd;
+
+		return 0;
+
+	}
+
+	/*
+	 * If control arrives here, we're protecting the boot areas. Check if we
+	 * have the MTD support we need.
+	 */
+
+	pr_info("Boot area protection is enabled.\n");
+
+	if (rom->boot_area_count > 1) {
+
+		/*
+		 * If the Boot ROM wants more than one boot area, then we'll
+		 * need to create partitions *and* concatenate them.
+		 */
+
+		#if defined(CONFIG_MTD_PARTITIONS) && defined(CONFIG_MTD_CONCAT)
+			mtd_support_is_adequate = true;
+		#else
+			mtd_support_is_adequate = false;
+		#endif
+
+	} else if (rom->boot_area_count == 1) {
+
+		/*
+		 * If the Boot ROM wants only one boot area, then we only need
+		 * to create partitions -- we don't need to concatenate them.
+		 */
+
+		#if defined(CONFIG_MTD_PARTITIONS)
+			mtd_support_is_adequate = true;
+		#else
+			mtd_support_is_adequate = false;
+		#endif
+
+	} else {
+
+		/*
+		 * If control arrives here, we're protecting the boot area, but
+		 * somehow the boot area count was set to zero. This doesn't
+		 * make any sense.
+		 */
+
+		dev_err(dev, "Internal error: boot area count is "
+						"incorrectly set to zero.");
+		return -ENXIO;
+
+	}
+
+	if (!mtd_support_is_adequate) {
+		dev_err(dev, "Configured MTD support is inadequate to "
+						"protect the boot area(s).");
+		return -ENXIO;
+	}
+
+	/*
+	 * If control arrives here, we're protecting boot areas and we have
+	 * everything we need to do so.
+	 *
+	 * We have special code to handle the case for one boot area.
+	 *
+	 * The code that handles "more than one" boot area actually only handles
+	 * two. We *could* write the general case, but that would take a lot of
+	 * time to both write and test -- and, right now, we don't have a chip
+	 * that cares.
+	 */
+
+	/* Check if a boot area is larger than a single chip. */
+
+	if (rom->boot_area_size_in_bytes > physical->chip_size_in_bytes) {
+		dev_emerg(dev, "Boot area size is larger than a chip");
+		return -ENXIO;
+	}
+
+	if (rom->boot_area_count == 1) {
+
+#if defined(CONFIG_MTD_PARTITIONS)
+
+		/*
+		 * We partition the medium like so:
+		 *
+		 * +------+----------------------------------------------------+
+		 * | Boot |                    General Use                     |
+		 * +------+----------------------------------------------------+
+		 */
+
+		/* Chip 0 Boot */
+
+		partitions[0].name       = chip_0_boot_name;
+		partitions[0].offset     = 0;
+		partitions[0].size       = rom->boot_area_size_in_bytes;
+		partitions[0].mask_flags = 0;
+
+		/* General Use */
+
+		partitions[1].name       = general_use_name;
+		partitions[1].offset     = rom->boot_area_size_in_bytes;
+		partitions[1].size       = MTDPART_SIZ_FULL;
+		partitions[1].mask_flags = 0;
+
+		/* Construct and register the partitions. */
+
+		add_mtd_partitions(mtd, partitions, 2);
+
+		/* Find the general use MTD. */
+
+		for (i = 0; i < MAX_MTD_DEVICES; i++) {
+
+			/* Get the current MTD so we can examine it. */
+
+			search_mtd = get_mtd_device(0, i);
+
+			/* Check if we got nonsense. */
+
+			if ((!search_mtd) || (search_mtd == ERR_PTR(-ENODEV)))
+				continue;
+
+			/* Check if the current MTD is one of our remainders. */
+
+			if (search_mtd->name == general_use_name)
+				mil->general_use_mtd = search_mtd;
+
+			/* Put the MTD back. We only wanted a quick look. */
+
+			put_mtd_device(search_mtd);
+
+		}
+
+		if (!mil->general_use_mtd) {
+			dev_emerg(dev, "Can't find general use MTD");
+			BUG();
+		}
+
+#endif
+
+	} else if (rom->boot_area_count == 2) {
+
+#if defined(CONFIG_MTD_PARTITIONS) && defined(CONFIG_MTD_CONCAT)
+
+		/*
+		 * If control arrives here, there is more than one boot area.
+		 * We partition the medium and concatenate the remainders like
+		 * so:
+		 *
+		 *  --- Chip 0 ---   --- Chip 1 --- ... ------- Chip N -------
+		 * /              \ /                                         \
+		 * +----+----------+----+--------------- ... ------------------+
+		 * |Boot|Remainder |Boot|              Remainder               |
+		 * +----+----------+----+--------------- ... ------------------+
+		 *      |          |   /                                      /
+		 *      |          |  /                                      /
+		 *      |          | /                                      /
+		 *      |          |/                                      /
+		 *      +----------+----------- ... ----------------------+
+		 *      |                   General Use                   |
+		 *      +---------------------- ... ----------------------+
+		 *
+		 * Notice that the results we leave in the master MTD table
+		 * look like this:
+		 *
+		 *    * Chip 0 Boot Area
+		 *    * Chip 1 Boot Area
+		 *    * General Use
+		 *
+		 * Some user space programs expect the boot partitions to
+		 * appear first. This is naive, but let's try not to cause
+		 * any trouble, where we can avoid it.
+		 */
+
+		/* Chip 0 Boot */
+
+		partitions[0].name       = chip_0_boot_name;
+		partitions[0].offset     = 0;
+		partitions[0].size       = rom->boot_area_size_in_bytes;
+		partitions[0].mask_flags = 0;
+
+		/* Chip 1 Boot */
+
+		partitions[1].name       = chip_1_boot_name;
+		partitions[1].offset     = nand->chipsize;
+		partitions[1].size       = rom->boot_area_size_in_bytes;
+		partitions[1].mask_flags = 0;
+
+		/* Chip 0 Remainder */
+
+		partitions[2].name       = chip_0_remainder_name;
+		partitions[2].offset     = rom->boot_area_size_in_bytes;
+		partitions[2].size       = nand->chipsize -
+						rom->boot_area_size_in_bytes;
+		partitions[2].mask_flags = 0;
+
+		/* Medium Remainder */
+
+		partitions[3].name       = medium_remainder_name;
+		partitions[3].offset     = nand->chipsize +
+						rom->boot_area_size_in_bytes;
+		partitions[3].size       = MTDPART_SIZ_FULL;
+		partitions[3].mask_flags = 0;
+
+		/* Construct and register the partitions. */
+
+		add_mtd_partitions(mtd, partitions, 4);
+
+		/* Find the remainder partitions. */
+
+		for (i = 0; i < MAX_MTD_DEVICES; i++) {
+
+			/* Get the current MTD so we can examine it. */
+
+			search_mtd = get_mtd_device(0, i);
+
+			/* Check if we got nonsense. */
+
+			if ((!search_mtd) || (search_mtd == ERR_PTR(-ENODEV)))
+				continue;
+
+			/* Check if the current MTD is one of our remainders. */
+
+			if (search_mtd->name == chip_0_remainder_name)
+				chip_0_remainder_mtd = search_mtd;
+
+			if (search_mtd->name == medium_remainder_name)
+				medium_remainder_mtd = search_mtd;
+
+			/* Put the MTD back. We only wanted a quick look. */
+
+			put_mtd_device(search_mtd);
+
+		}
+
+		if (!chip_0_remainder_mtd || !medium_remainder_mtd) {
+			dev_emerg(dev, "Can't find remainder partitions");
+			BUG();
+		}
+
+		/*
+		 * Unregister the remainder MTDs. Note that we are *not*
+		 * destroying these MTDs -- we're just removing from the
+		 * globally-visible list. There's no need for anyone to see
+		 * these.
+		 */
+
+		del_mtd_device(chip_0_remainder_mtd);
+		del_mtd_device(medium_remainder_mtd);
+
+		/* Concatenate the remainders and register the result. */
+
+		concatenate[0] = chip_0_remainder_mtd;
+		concatenate[1] = medium_remainder_mtd;
+
+		mil->general_use_mtd = mtd_concat_create(concatenate,
+							2, general_use_name);
+
+		add_mtd_device(mil->general_use_mtd);
+
+#endif
+
+	} else {
+		dev_err(dev, "Boot area count greater than two is "
+							"unimplemented.\n");
+		return -ENXIO;
+	}
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_boot_areas_exit() - Shuts down boot areas.
+ *
+ * @this:  Per-device data.
+ */
+static void mil_boot_areas_exit(struct gpmi_nfc_data *this)
+{
+	struct boot_rom_geometry  *rom = &this->rom_geometry;
+	struct mil                *mil = &this->mil;
+	struct mtd_info           *mtd = &mil->mtd;
+
+	/* Check if we're protecting the boot areas.*/
+
+	if (!rom->boot_area_count) {
+
+		/*
+		 * If control arrives here, we're not protecting the boot areas.
+		 * That means we never created any boot area partitions, and the
+		 * general use MTD is just the main MTD.
+		 */
+
+		mil->general_use_mtd = 0;
+
+		return;
+
+	}
+
+	/*
+	 * If control arrives here, we're protecting the boot areas.
+	 *
+	 * Start by checking if there is more than one boot area. If so, then
+	 * we both partitioned the medium and then concatenated some of the
+	 * partitions to form the general use MTD. The first step is to get rid
+	 * of the concatenation.
+	 */
+
+	#if defined(CONFIG_MTD_PARTITIONS) && defined(CONFIG_MTD_CONCAT)
+		if (rom->boot_area_count > 1) {
+				del_mtd_device(mil->general_use_mtd);
+				mtd_concat_destroy(mil->general_use_mtd);
+		}
+	#endif
+
+	/*
+	 * At this point, we're left only with the partitions of the main MTD.
+	 * Delete them.
+	 */
+
+	#if defined(CONFIG_MTD_PARTITIONS)
+		del_mtd_partitions(mtd);
+	#endif
+
+	/* The general use MTD no longer exists. */
+
+	mil->general_use_mtd = 0;
+
+}
+
+/**
+ * mil_construct_ubi_partitions() - Constructs partitions for UBI.
+ *
+ * MTD uses a 64-bit value to express the size of MTDs, but UBI is still using
+ * a 32-bit value. For this reason, UBI can't work on top of an MTD with size
+ * greater than 2GiB. In this function, we examine the general use MTD and, if
+ * it's larger than 2GiB, we construct a set of partitions for that MTD such
+ * that none are too large for UBI to comprehend.
+ *
+ * @this:  Per-device data.
+ */
+static void mil_construct_ubi_partitions(struct gpmi_nfc_data *this)
+{
+#if defined(CONFIG_MTD_PARTITIONS)
+	struct device                  *dev   =  this->dev;
+	struct mil                     *mil   = &this->mil;
+	unsigned int                   partition_count;
+	struct mtd_partition           *partitions;
+	unsigned int                   name_size;
+	char                           *names;
+	unsigned int                   memory_block_size;
+	unsigned int                   i;
+
+	static const char              *name_prefix = "gpmi-nfc-ubi-";
+
+	/*
+	 * If the general use MTD isn't larger than 2GiB, we have nothing to do.
+	 */
+
+	if (mil->general_use_mtd->size <= SZ_2G)
+		return;
+
+	/*
+	 * If control arrives here, the general use MTD is larger than 2GiB. We
+	 * need to split it up into some number of partitions. Find out how many
+	 * 2GiB partitions we'll be creating.
+	 */
+
+	partition_count = mil->general_use_mtd->size >> 31;
+
+	/*
+	 * If the MTD size doesn't evenly divide by 2GiB, we'll need another
+	 * partition to hold the extra.
+	 */
+
+	if (mil->general_use_mtd->size & ((1 << 30) - 1))
+		partition_count++;
+
+	/*
+	 * We're going to allocate a single memory block to contain all the
+	 * partition structures and their names. Calculate how large it must be.
+	 */
+
+	name_size = strlen(name_prefix) + 4;
+
+	memory_block_size = (sizeof(*partitions) + name_size) * partition_count;
+
+	/*
+	 * Attempt to allocate the block.
+	 */
+
+	partitions = kzalloc(memory_block_size, GFP_KERNEL);
+
+	if (!partitions) {
+		dev_err(dev, "Could not allocate memory for UBI partitions.\n");
+		return;
+	}
+
+	names = (char *)(partitions + partition_count);
+
+	/* Loop over partitions, filling in the details. */
+
+	for (i = 0; i < partition_count; i++) {
+
+		partitions[i].name   = names;
+		partitions[i].size   = SZ_2G;
+		partitions[i].offset = MTDPART_OFS_NXTBLK;
+
+		sprintf(names, "%s%u", name_prefix, i);
+		names += name_size;
+
+	}
+
+	/* Adjust the last partition to take up the remainder. */
+
+	partitions[i - 1].size = MTDPART_SIZ_FULL;
+
+	/* Record everything in the device data structure.  */
+
+	mil->partitions           = partitions;
+	mil->partition_count      = partition_count;
+	mil->ubi_partition_memory = partitions;
+
+#endif
+}
+
+/**
+ * mil_partitions_init() - Initializes partitions.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_partitions_init(struct gpmi_nfc_data *this)
+{
+	struct gpmi_nfc_platform_data  *pdata =  this->pdata;
+	struct mil                     *mil   = &this->mil;
+	struct mtd_info                *mtd   = &mil->mtd;
+	int                            error;
+
+	/*
+	 * Set up the boot areas. When this function returns, if there has been
+	 * no error, the boot area partitions (if any) will have been created
+	 * and registered. Also, the general_use_mtd field will point to an MTD
+	 * we can use.
+	 */
+
+	error = mil_boot_areas_init(this);
+
+	if (error)
+		return error;
+
+	/*
+	 * If we've been told to, register the MTD that represents the entire
+	 * medium. Normally, we don't register the main MTD because we only want
+	 * to expose the medium through the boot area partitions and the general
+	 * use partition.
+	 *
+	 * We do this *after* setting up the boot areas because, for historical
+	 * reasons, we like the lowest-numbered MTDs to be the boot areas.
+	 */
+
+	if (register_main_mtd) {
+		pr_info("Registering the main MTD.\n");
+		add_mtd_device(mtd);
+	}
+
+#if defined(CONFIG_MTD_PARTITIONS)
+
+	/*
+	 * If control arrives here, partitioning is available.
+	 *
+	 * There are three possible sets of partitions we might apply, in order
+	 * of decreasing priority:
+	 *
+	 * 1) Partitions dynamically discovered from sources defined by the
+	 *    platform. These can come from, for example, the command line or
+	 *    a partition table.
+	 *
+	 * 2) Partitions attached to the platform data.
+	 *
+	 * 3) Partitions we generate to deal with limitations in UBI.
+	 *
+	 * Recall that the pointer to the general use MTD *may* just point to
+	 * the main MTD.
+	 */
+
+	/*
+	 * First, try to get partition information from the sources defined by
+	 * the platform.
+	 */
+
+	if (pdata->partition_source_types)
+		mil->partition_count =
+			parse_mtd_partitions(mil->general_use_mtd,
+						pdata->partition_source_types,
+						&mil->partitions, 0);
+
+	/*
+	 * Check if we got anything. If not, then accept whatever partitions are
+	 * attached to the platform data.
+	 */
+
+	if ((mil->partition_count <= 0) && (pdata->partitions)) {
+		mil->partition_count = mil->partition_count;
+		mil->partitions      = mil->partitions;
+	}
+
+	/*
+	 * If we still don't have any partitions to apply, then we might want to
+	 * apply some of our own, to account for UBI's limitations.
+	 */
+
+	if (!mil->partition_count)
+		mil_construct_ubi_partitions(this);
+
+	/* If we came up with any partitions, apply them. */
+
+	if (mil->partition_count)
+		add_mtd_partitions(mil->general_use_mtd,
+					mil->partitions,
+					mil->partition_count);
+
+#endif
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_partitions_exit() - Shuts down partitions.
+ *
+ * @this:  Per-device data.
+ */
+static void mil_partitions_exit(struct gpmi_nfc_data *this)
+{
+	struct mil       *mil   = &this->mil;
+	struct mtd_info  *mtd   = &mil->mtd;
+
+	/* Check if we applied any partitions to the general use MTD. */
+
+	#if defined(CONFIG_MTD_PARTITIONS)
+
+		if (mil->partition_count)
+			del_mtd_partitions(mil->general_use_mtd);
+
+		kfree(mil->ubi_partition_memory);
+
+	#endif
+
+	/*
+	 * If we were told to register the MTD that represents the entire
+	 * medium, unregister it now. Note that this does *not* "destroy" the
+	 * MTD - it merely unregisters it. That's important because all our
+	 * other MTDs depend on this one.
+	 */
+
+	if (register_main_mtd)
+		del_mtd_device(mtd);
+
+	/* Tear down the boot areas. */
+
+	mil_boot_areas_exit(this);
+
+}
+
+/**
+ * gpmi_nfc_mil_init() - Initializes the MTD Interface Layer.
+ *
+ * @this:  Per-device data.
+ */
+int gpmi_nfc_mil_init(struct gpmi_nfc_data *this)
+{
+	struct device                  *dev   =  this->dev;
+	struct gpmi_nfc_platform_data  *pdata =  this->pdata;
+	struct mil                     *mil   = &this->mil;
+	struct mtd_info                *mtd   = &mil->mtd;
+	struct nand_chip               *nand  = &mil->nand;
+	static struct nand_ecclayout   fake_ecc_layout;
+	int                            error = 0;
+
+	/* Initialize MIL data. */
+
+	mil->current_chip   = -1;
+	mil->command_length =  0;
+
+	mil->page_buffer_virt =  0;
+	mil->page_buffer_phys = ~0;
+	mil->page_buffer_size =  0;
+
+	/* Initialize the MTD data structures. */
+
+	mtd->priv  = nand;
+	mtd->name  = "gpmi-nfc-main";
+	mtd->owner = THIS_MODULE;
+	nand->priv = this;
+
+	/*
+	 * Signal Control
+	 */
+
+	nand->cmd_ctrl = mil_cmd_ctrl;
+
+	/*
+	 * Chip Control
+	 *
+	 * We rely on the reference implementations of:
+	 *     - cmdfunc
+	 *     - waitfunc
+	 */
+
+	nand->dev_ready   = mil_dev_ready;
+	nand->select_chip = mil_select_chip;
+
+	/*
+	 * Low-level I/O
+	 *
+	 * We don't support a 16-bit NAND Flash bus, so we don't implement
+	 * read_word.
+	 *
+	 * We rely on the reference implentation of verify_buf.
+	 */
+
+	nand->read_byte = mil_read_byte;
+	nand->read_buf  = mil_read_buf;
+	nand->write_buf = mil_write_buf;
+
+	/*
+	 * ECC Control
+	 *
+	 * None of these functions are necessary for us:
+	 *     - ecc.hwctl
+	 *     - ecc.calculate
+	 *     - ecc.correct
+	 */
+
+	/*
+	 * ECC-aware I/O
+	 *
+	 * We rely on the reference implementations of:
+	 *     - ecc.read_page_raw
+	 *     - ecc.write_page_raw
+	 */
+
+	nand->ecc.read_page  = mil_ecc_read_page;
+	nand->ecc.write_page = mil_ecc_write_page;
+
+	/*
+	 * High-level I/O
+	 *
+	 * We rely on the reference implementations of:
+	 *     - write_page
+	 *     - erase_cmd
+	 */
+
+	nand->ecc.read_oob  = mil_ecc_read_oob;
+	nand->ecc.write_oob = mil_ecc_write_oob;
+
+	/*
+	 * Bad Block Management
+	 *
+	 * We rely on the reference implementations of:
+	 *     - block_bad
+	 *     - block_markbad
+	 */
+
+	nand->block_bad = mil_block_bad;
+	nand->scan_bbt  = mil_scan_bbt;
+
+	/*
+	 * Error Recovery Functions
+	 *
+	 * We don't fill in the errstat function pointer because it's optional
+	 * and we don't have a need for it.
+	 */
+
+	/*
+	 * Set up NAND Flash options. Specifically:
+	 *
+	 *     - Disallow partial page writes.
+	 */
+
+	nand->options |= NAND_NO_SUBPAGE_WRITE;
+
+	/*
+	 * Tell the NAND Flash MTD system that we'll be handling ECC with our
+	 * own hardware. It turns out that we still have to fill in the ECC size
+	 * because the MTD code will divide by it -- even though it doesn't
+	 * actually care.
+	 */
+
+	nand->ecc.mode = NAND_ECC_HW;
+	nand->ecc.size = 1;
+
+	/*
+	 * Install a "fake" ECC layout.
+	 *
+	 * We'll be calling nand_scan() to do the final MTD setup. If we haven't
+	 * already chosen an ECC layout, then nand_scan() will choose one based
+	 * on the part geometry it discovers. Unfortunately, it doesn't make
+	 * good choices. It would be best if we could install the correct ECC
+	 * layout now, before we call nand_scan(). We can't do that because we
+	 * don't know the medium geometry yet. Here, we install a "fake" ECC
+	 * layout just to stop nand_scan() from trying to pick one for itself.
+	 * Later, when we know the medium geometry, we'll install the correct
+	 * one.
+	 *
+	 * Of course, this tactic depends critically on the MTD code not doing
+	 * an I/O operation that depends on the ECC layout being sensible. This
+	 * is in fact the case.
+	 */
+
+	memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
+
+	nand->ecc.layout = &fake_ecc_layout;
+
+	/* Allocate a command buffer. */
+
+	mil->cmd_virt =
+		dma_alloc_coherent(dev,
+			MIL_COMMAND_BUFFER_SIZE, &mil->cmd_phys, GFP_DMA);
+
+	if (!mil->cmd_virt)
+		goto exit_cmd_allocation;
+
+	/*
+	 * Ask the NAND Flash system to scan for chips.
+	 *
+	 * This will fill in reference implementations for all the members of
+	 * the MTD structures that we didn't set, and will make the medium fully
+	 * usable.
+	 */
+
+	pr_info("Scanning for NAND Flash chips...\n");
+
+	error = nand_scan(mtd, pdata->max_chip_count);
+
+	if (error) {
+		dev_err(dev, "Chip scan failed\n");
+		goto exit_nand_scan;
+	}
+
+	/*
+	 * Hook some operations at the MTD level. See the descriptions of the
+	 * saved function pointer fields for details about why we hook these.
+	 */
+
+	mil->hooked_read_oob      = mtd->read_oob;
+	mtd->read_oob             = mil_hook_read_oob;
+
+	mil->hooked_write_oob     = mtd->write_oob;
+	mtd->write_oob            = mil_hook_write_oob;
+
+	mil->hooked_block_markbad = mtd->block_markbad;
+	mtd->block_markbad        = mil_hook_block_markbad;
+
+	/* Construct partitions as necessary. */
+
+	error = mil_partitions_init(this);
+
+	if (error)
+		goto exit_partitions;
+
+	/* Return success. */
+
+	return 0;
+
+	/* Control arrives here if something went wrong. */
+
+exit_partitions:
+	nand_release(&mil->mtd);
+exit_nand_scan:
+	dma_free_coherent(dev, MIL_COMMAND_BUFFER_SIZE,
+						mil->cmd_virt, mil->cmd_phys);
+	mil->cmd_virt =  0;
+	mil->cmd_phys = ~0;
+exit_cmd_allocation:
+
+	return error;
+
+}
+
+/**
+ * gpmi_nfc_mil_exit() - Shuts down the MTD Interface Layer.
+ *
+ * @this:  Per-device data.
+ */
+void gpmi_nfc_mil_exit(struct gpmi_nfc_data *this)
+{
+	struct device  *dev = this->dev;
+	struct mil     *mil = &this->mil;
+
+	/* Shut down partitions as necessary. */
+
+	mil_partitions_exit(this);
+
+	/* Get MTD to let go of our MTD. */
+
+	nand_release(&mil->mtd);
+
+	/* Free the page buffer, if it's been allocated. */
+
+	if (mil->page_buffer_virt)
+		dma_free_coherent(dev, mil->page_buffer_size,
+				mil->page_buffer_virt, mil->page_buffer_phys);
+
+	mil->page_buffer_size =  0;
+	mil->page_buffer_virt =  0;
+	mil->page_buffer_phys = ~0;
+
+	/* Free the command buffer, if it's been allocated. */
+
+	if (mil->cmd_virt)
+		dma_free_coherent(dev, MIL_COMMAND_BUFFER_SIZE,
+						mil->cmd_virt, mil->cmd_phys);
+
+	mil->cmd_virt =  0;
+	mil->cmd_phys = ~0;
+
+}
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c
new file mode 100644
index 000000000000..0cd0b39141fd
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c
@@ -0,0 +1,59 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+/**
+ * gpmi_nfc_rom_helper_set_geometry() - Sets geometry for the Boot ROM Helper.
+ *
+ * @this:  Per-device data.
+ */
+int gpmi_nfc_rom_helper_set_geometry(struct gpmi_nfc_data *this)
+{
+	struct boot_rom_geometry  *geometry = &this->rom_geometry;
+
+	/*
+	 * Set the boot block stride size.
+	 *
+	 * In principle, we should be reading this from the OTP bits, since
+	 * that's where the ROM is going to get it. In fact, we don't have any
+	 * way to read the OTP bits, so we go with the default and hope for the
+	 * best.
+	 */
+
+	geometry->stride_size_in_pages = 64;
+
+	/*
+	 * Set the search area stride exponent.
+	 *
+	 * In principle, we should be reading this from the OTP bits, since
+	 * that's where the ROM is going to get it. In fact, we don't have any
+	 * way to read the OTP bits, so we go with the default and hope for the
+	 * best.
+	 */
+
+	geometry->search_area_stride_exponent = 2;
+
+	/* Return success. */
+
+	return 0;
+
+}
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c
new file mode 100644
index 000000000000..35321cc25546
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c
@@ -0,0 +1,297 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+/*
+ * Useful variables for Boot ROM Helper version 0.
+ */
+
+static const char  *fingerprint = "STMP";
+
+/**
+ * set_geometry() - Sets geometry for the Boot ROM Helper.
+ *
+ * @this:  Per-device data.
+ */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+	struct gpmi_nfc_platform_data  *pdata    =  this->pdata;
+	struct physical_geometry       *physical = &this->physical_geometry;
+	struct boot_rom_geometry       *geometry = &this->rom_geometry;
+	int                             error;
+
+	/* Version-independent geometry. */
+
+	error = gpmi_nfc_rom_helper_set_geometry(this);
+
+	if (error)
+		return error;
+
+	/*
+	 * Check if the platform data indicates we are to protect the boot area.
+	 */
+
+	if (!pdata->boot_area_size_in_bytes) {
+		geometry->boot_area_count         = 0;
+		geometry->boot_area_size_in_bytes = 0;
+		return 0;
+	}
+
+	/*
+	 * If control arrives here, we are supposed to set up partitions to
+	 * protect the boot areas. In this version of the ROM, the number of
+	 * boot areas and their size depends on the number of chips.
+	 */
+
+	if (physical->chip_count == 1) {
+		geometry->boot_area_count = 1;
+		geometry->boot_area_size_in_bytes =
+					pdata->boot_area_size_in_bytes * 2;
+	} else {
+		geometry->boot_area_count = 2;
+		geometry->boot_area_size_in_bytes =
+					pdata->boot_area_size_in_bytes;
+	}
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * check_transcription_stamp() - Checks for a transcription stamp.
+ *
+ * Returns 0 if a stamp is not found.
+ *
+ * @this:  Per-device data.
+ */
+static int check_transcription_stamp(struct gpmi_nfc_data *this)
+{
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct boot_rom_geometry  *rom_geo  = &this->rom_geometry;
+	struct mil                *mil      = &this->mil;
+	struct mtd_info           *mtd      = &mil->mtd;
+	struct nand_chip          *nand     = &mil->nand;
+	unsigned int              search_area_size_in_strides;
+	unsigned int              stride;
+	unsigned int              page;
+	loff_t                    byte;
+	uint8_t                   *buffer = nand->buffers->databuf;
+	int                       saved_chip_number;
+	int                       found_an_ncb_fingerprint = false;
+
+	/* Compute the number of strides in a search area. */
+
+	search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;
+
+	/* Select chip 0. */
+
+	saved_chip_number = mil->current_chip;
+	nand->select_chip(mtd, 0);
+
+	/*
+	 * Loop through the first search area, looking for the NCB fingerprint.
+	 */
+
+	pr_info("Scanning for an NCB fingerprint...\n");
+
+	for (stride = 0; stride < search_area_size_in_strides; stride++) {
+
+		/* Compute the page and byte addresses. */
+
+		page = stride * rom_geo->stride_size_in_pages;
+		byte = page   * physical->page_data_size_in_bytes;
+
+		pr_info("  Looking for a fingerprint in page 0x%x\n", page);
+
+		/*
+		 * Read the NCB fingerprint. The fingerprint is four bytes long
+		 * and starts in the 12th byte of the page.
+		 */
+
+		nand->cmdfunc(mtd, NAND_CMD_READ0, 12, page);
+		nand->read_buf(mtd, buffer, strlen(fingerprint));
+
+		/* Look for the fingerprint. */
+
+		if (!memcmp(buffer, fingerprint,
+					strlen(fingerprint))) {
+			found_an_ncb_fingerprint = true;
+			break;
+		}
+
+	}
+
+	/* Deselect chip 0. */
+
+	nand->select_chip(mtd, saved_chip_number);
+
+	/* Return. */
+
+	if (found_an_ncb_fingerprint)
+		pr_info("  Found a fingerprint\n");
+	else
+		pr_info("  No fingerprint found\n");
+
+	return found_an_ncb_fingerprint;
+
+}
+
+/**
+ * write_transcription_stamp() - Writes a transcription stamp.
+ *
+ * @this:  Per-device data.
+ */
+static int write_transcription_stamp(struct gpmi_nfc_data *this)
+{
+	struct device             *dev      =  this->dev;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct boot_rom_geometry  *rom_geo  = &this->rom_geometry;
+	struct mil                *mil      = &this->mil;
+	struct mtd_info           *mtd      = &mil->mtd;
+	struct nand_chip          *nand     = &mil->nand;
+	unsigned int              block_size_in_pages;
+	unsigned int              search_area_size_in_strides;
+	unsigned int              search_area_size_in_pages;
+	unsigned int              search_area_size_in_blocks;
+	unsigned int              block;
+	unsigned int              stride;
+	unsigned int              page;
+	loff_t                    byte;
+	uint8_t                   *buffer = nand->buffers->databuf;
+	int                       saved_chip_number;
+	int                       status;
+
+	/* Compute the search area geometry. */
+
+	block_size_in_pages = physical->block_size_in_bytes >>
+				(ffs(physical->page_data_size_in_bytes) - 1);
+
+	search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;
+
+	search_area_size_in_pages = search_area_size_in_strides *
+						rom_geo->stride_size_in_pages;
+
+	search_area_size_in_blocks =
+		  (search_area_size_in_pages + (block_size_in_pages - 1)) /
+		/*-------------------------------------------------------*/
+				    block_size_in_pages;
+
+	#if defined(DETAILED_INFO)
+
+	pr_info("--------------------\n");
+	pr_info("Search Area Geometry\n");
+	pr_info("--------------------\n");
+	pr_info("Search Area Size in Blocks : %u", search_area_size_in_blocks);
+	pr_info("Search Area Size in Strides: %u", search_area_size_in_strides);
+	pr_info("Search Area Size in Pages  : %u", search_area_size_in_pages);
+
+	#endif
+
+	/* Select chip 0. */
+
+	saved_chip_number = mil->current_chip;
+	nand->select_chip(mtd, 0);
+
+	/* Loop over blocks in the first search area, erasing them. */
+
+	pr_info("Erasing the search area...\n");
+
+	for (block = 0; block < search_area_size_in_blocks; block++) {
+
+		/* Compute the page address. */
+
+		page = block * block_size_in_pages;
+
+		/* Erase this block. */
+
+		pr_info("  Erasing block 0x%x\n", block);
+
+		nand->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+		nand->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
+
+		/* Wait for the erase to finish. */
+
+		status = nand->waitfunc(mtd, nand);
+
+		if (status & NAND_STATUS_FAIL)
+			dev_err(dev, "[%s] Erase failed.\n", __func__);
+
+	}
+
+	/* Write the NCB fingerprint into the page buffer. */
+
+	memset(buffer, ~0, mtd->writesize);
+	memset(nand->oob_poi, ~0, mtd->oobsize);
+
+	memcpy(buffer + 12, fingerprint, strlen(fingerprint));
+
+	/* Loop through the first search area, writing NCB fingerprints. */
+
+	pr_info("Writing NCB fingerprints...\n");
+
+	for (stride = 0; stride < search_area_size_in_strides; stride++) {
+
+		/* Compute the page and byte addresses. */
+
+		page = stride * rom_geo->stride_size_in_pages;
+		byte = page   * physical->page_data_size_in_bytes;
+
+		/* Write the first page of the current stride. */
+
+		pr_info("  Writing an NCB fingerprint in page 0x%x\n", page);
+
+		nand->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+		nand->ecc.write_page_raw(mtd, nand, buffer);
+		nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+		/* Wait for the write to finish. */
+
+		status = nand->waitfunc(mtd, nand);
+
+		if (status & NAND_STATUS_FAIL)
+			dev_err(dev, "[%s] Write failed.\n", __func__);
+
+	}
+
+	/* Deselect chip 0. */
+
+	nand->select_chip(mtd, saved_chip_number);
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/* This structure represents the Boot ROM Helper for this version. */
+
+struct boot_rom_helper  gpmi_nfc_boot_rom_helper_v0 = {
+	.version                   = 0,
+	.description               = "Single/dual-chip boot area, "
+						"no block mark swapping",
+	.swap_block_mark           = false,
+	.set_geometry              = set_geometry,
+	.check_transcription_stamp = check_transcription_stamp,
+	.write_transcription_stamp = write_transcription_stamp,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c
new file mode 100644
index 000000000000..49cb329ccdd4
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c
@@ -0,0 +1,82 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+/**
+ * set_geometry() - Sets geometry for the Boot ROM Helper.
+ *
+ * @this:  Per-device data.
+ */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+	struct gpmi_nfc_platform_data  *pdata    =  this->pdata;
+	struct boot_rom_geometry       *geometry = &this->rom_geometry;
+	int                            error;
+
+	/* Version-independent geometry. */
+
+	error = gpmi_nfc_rom_helper_set_geometry(this);
+
+	if (error)
+		return error;
+
+	/*
+	 * Check if the platform data indicates we are to protect the boot area.
+	 */
+
+	if (!pdata->boot_area_size_in_bytes) {
+		geometry->boot_area_count         = 0;
+		geometry->boot_area_size_in_bytes = 0;
+		return 0;
+	}
+
+	/*
+	 * If control arrives here, we are supposed to set up partitions to
+	 * protect the boot areas. In this version of the ROM, we support only
+	 * one boot area.
+	 */
+
+	geometry->boot_area_count = 1;
+
+	/*
+	 * Use the platform's boot area size.
+	 */
+
+	geometry->boot_area_size_in_bytes = pdata->boot_area_size_in_bytes;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/* This structure represents the Boot ROM Helper for this version. */
+
+struct boot_rom_helper  gpmi_nfc_boot_rom_helper_v1 = {
+	.version                   = 1,
+	.description               = "Single-chip boot area, "
+						"block mark swapping supported",
+	.swap_block_mark           = true,
+	.set_geometry              = set_geometry,
+	.check_transcription_stamp = 0,
+	.write_transcription_stamp = 0,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
new file mode 100644
index 000000000000..6f14b73dd93d
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
@@ -0,0 +1,643 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __DRIVERS_MTD_NAND_GPMI_NFC_H
+#define __DRIVERS_MTD_NAND_GPMI_NFC_H
+
+/* Linux header files. */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/concat.h>
+#include <linux/gpmi-nfc.h>
+#include <asm/sizes.h>
+
+/* Platform header files. */
+
+#include <mach/system.h>
+#include <mach/dmaengine.h>
+#include <mach/device.h>
+#include <mach/clock.h>
+
+/* Driver header files. */
+
+#include "../nand_device_info.h"
+
+/*
+ *------------------------------------------------------------------------------
+ * Fundamental Macros
+ *------------------------------------------------------------------------------
+ */
+
+/* Define this macro to enable detailed information messages. */
+
+#define DETAILED_INFO
+
+/* Define this macro to enable event reporting. */
+
+/*#define EVENT_REPORTING*/
+
+/*
+ *------------------------------------------------------------------------------
+ * Fundamental Data Structures
+ *------------------------------------------------------------------------------
+ */
+
+/**
+ * struct resources - The collection of resources the driver needs.
+ *
+ * @gpmi_regs:         A pointer to the GPMI registers.
+ * @bch_regs:          A pointer to the BCH registers.
+ * @bch_interrupt:     The BCH interrupt number.
+ * @dma_low_channel:   The low  DMA channel.
+ * @dma_high_channel:  The high DMA channel.
+ * @dma_interrupt:     The DMA interrupt number.
+ * @clock:             A pointer to the struct clk for the NFC's clock.
+ */
+
+struct resources {
+	void          *gpmi_regs;
+	void          *bch_regs;
+	unsigned int  bch_interrupt;
+	unsigned int  dma_low_channel;
+	unsigned int  dma_high_channel;
+	unsigned int  dma_interrupt;
+	struct clk    *clock;
+};
+
+/**
+ * struct mil - State for the MTD Interface Layer.
+ *
+ * @nand:                    The NAND Flash MTD data structure that represents
+ *                           the NAND Flash medium.
+ * @mtd:                     The MTD data structure that represents the NAND
+ *                           Flash medium.
+ * @oob_layout:              A structure that describes how bytes are laid out
+ *                           in the OOB.
+ * @general_use_mtd:         A pointer to an MTD we export for general use.
+ *                           This *may* simply be a pointer to the mtd field, if
+ *                           we've been instructed NOT to protect the boot
+ *                           areas.
+ * @partitions:              A pointer to a set of partitions applied to the
+ *                           general use MTD.
+ * @partition_count:         The number of partitions.
+ * @ubi_partition_memory:    If not NULL, a block of memory used to create a set
+ *                           of partitions that help with the problem that UBI
+ *                           can't handle an MTD larger than 2GiB.
+ * @current_chip:            The chip currently selected by the NAND Fash MTD
+ *                           code. A negative value indicates that no chip is
+ *                           selected.
+ * @command_length:          The length of the command that appears in the
+ *                           command buffer (see cmd_virt, below).
+ * @inject_ecc_error:        Indicates the driver should inject a "fake" ECC
+ *                           error into the next read operation that uses ECC.
+ *                           User space programs can set this value through the
+ *                           sysfs node of the same name. If this value is less
+ *                           than zero, the driver will inject an uncorrectable
+ *                           ECC error. If this value is greater than zero, the
+ *                           driver will inject that number of correctable
+ *                           errors, capped by the maximum possible number of
+ *                           errors that could appear in a single read.
+ * @ignore_bad_block_marks:  Indicates we are ignoring bad block marks.
+ * @saved_bbt:               A saved pointer to the in-memory NAND Flash MTD bad
+ *                           block table. See show_device_ignorebad() for more
+ *                           details.
+ * @raw_oob_mode:            Indicates the OOB is to be read/written in "raw"
+ *                           mode. See mil_ecc_read_oob() for details.
+ * @hooked_read_oob:         A pointer to the ecc.read_oob() function we
+ *                           "hooked." See mil_ecc_read_oob() for details.
+ * @hooked_write_oob:        A pointer to the ecc.write_oob() function pointer
+ *                           we "hooked." See mil_ecc_read_oob() for details.
+ * @marking_a_bad_block:     Indicates the caller is marking a bad block. See
+ *                           mil_ecc_write_oob() for details.
+ * @hooked_block_markbad:    A pointer to the block_markbad() function we
+ *                           we "hooked." See mil_ecc_write_oob() for details.
+ * @cmd_virt:                A pointer to a DMA-coherent buffer in which we
+ *                           accumulate command bytes before we give them to the
+ *                           NFC layer. See mil_cmd_ctrl() for more details.
+ * @cmd_phys:                The physical address for the cmd_virt buffer.
+ * @page_buffer_virt:        A pointer to a DMA-coherent buffer we use for
+ *                           reading and writing pages. This buffer includes
+ *                           space for both the payload data and the auxiliary
+ *                           data (including status bytes, but not syndrome
+ *                           bytes).
+ * @page_buffer_phys:        The physical address for the page_buffer_virt
+ *                           buffer.
+ * @page_buffer_size:        The size of the page buffer.
+ * @payload_virt:            A pointer to a location in the page buffer used
+ *                           for payload bytes. The size of this buffer is
+ *                           determined by struct nfc_geometry.
+ * @payload_phys:            The physical address for payload_virt.
+ * @payload_size:            The size of the payload area in the page buffer.
+ * @auxiliary_virt:          A pointer to a location in the page buffer used
+ *                           for auxiliary bytes. The size of this buffer is
+ *                           determined by struct nfc_geometry.
+ * @auxiliary_phys:          The physical address for auxiliary_virt.
+ * @auxiliary_size:          The size of the auxiliary area in the page buffer.
+ */
+
+#define MIL_COMMAND_BUFFER_SIZE (10)
+
+struct mil {
+
+	/* MTD Data Structures */
+
+	struct nand_chip       nand;
+	struct mtd_info        mtd;
+	struct nand_ecclayout  oob_layout;
+
+	/* Partitioning and Boot Area Protection */
+
+	struct mtd_info        *general_use_mtd;
+	struct mtd_partition   *partitions;
+	unsigned int           partition_count;
+	void                   *ubi_partition_memory;
+
+	/* General-use Variables */
+
+	int                    current_chip;
+	unsigned int           command_length;
+	int                    inject_ecc_error;
+	int                    ignore_bad_block_marks;
+	void                   *saved_bbt;
+
+	/* MTD Function Pointer Hooks */
+
+	int                    raw_oob_mode;
+	int                    (*hooked_read_oob)(struct mtd_info *mtd,
+					loff_t from, struct mtd_oob_ops *ops);
+	int                    (*hooked_write_oob)(struct mtd_info *mtd,
+					loff_t to, struct mtd_oob_ops *ops);
+
+	int                    marking_a_bad_block;
+	int                    (*hooked_block_markbad)(struct mtd_info *mtd,
+					loff_t ofs);
+
+	/* DMA Buffers */
+
+	char                   *cmd_virt;
+	dma_addr_t             cmd_phys;
+
+	void                   *page_buffer_virt;
+	dma_addr_t             page_buffer_phys;
+	unsigned int           page_buffer_size;
+
+	void                   *payload_virt;
+	dma_addr_t             payload_phys;
+
+	void                   *auxiliary_virt;
+	dma_addr_t             auxiliary_phys;
+
+};
+
+/**
+ * struct physical_geometry - Physical geometry description.
+ *
+ * This structure describes the physical geometry of the medium.
+ *
+ * @chip_count:                    The number of chips in the medium.
+ * @chip_size_in_bytes:            The size, in bytes, of a single chip
+ *                                 (excluding the out-of-band bytes).
+ * @block_size_in_bytes:           The size, in bytes, of a single block
+ *                                 (excluding the out-of-band bytes).
+ * @page_data_size_in_bytes:       The size, in bytes, of the data area in a
+ *                                 page (excluding the out-of-band bytes).
+ * @page_oob_size_in_bytes:        The size, in bytes, of the out-of-band area
+ *                                 in a page.
+ */
+
+struct physical_geometry {
+	unsigned int  chip_count;
+	uint64_t      chip_size_in_bytes;
+	unsigned int  block_size_in_bytes;
+	unsigned int  page_data_size_in_bytes;
+	unsigned int  page_oob_size_in_bytes;
+};
+
+/**
+ * struct nfc_geometry - NFC geometry description.
+ *
+ * This structure describes the NFC's view of the medium geometry.
+ *
+ * @ecc_algorithm:            The human-readable name of the ECC algorithm
+ *                            (e.g., "Reed-Solomon" or "BCH").
+ * @ecc_strength:             A number that describes the strength of the ECC
+ *                            algorithm.
+ * @page_size_in_bytes:       The size, in bytes, of a physical page, including
+ *                            both data and OOB.
+ * @metadata_size_in_bytes:   The size, in bytes, of the metadata.
+ * @ecc_chunk_size_in_bytes:  The size, in bytes, of a single ECC chunk. Note
+ *                            the first chunk in the page includes both data and
+ *                            metadata, so it's a bit larger than this value.
+ * @ecc_chunk_count:          The number of ECC chunks in the page,
+ * @payload_size_in_bytes:    The size, in bytes, of the payload buffer.
+ * @auxiliary_size_in_bytes:  The size, in bytes, of the auxiliary buffer.
+ * @auxiliary_status_offset:  The offset into the auxiliary buffer at which
+ *                            the ECC status appears.
+ * @block_mark_byte_offset:   The byte offset in the ECC-based page view at
+ *                            which the underlying physical block mark appears.
+ * @block_mark_bit_offset:    The bit offset into the ECC-based page view at
+ *                            which the underlying physical block mark appears.
+ */
+
+struct nfc_geometry {
+	char          *ecc_algorithm;
+	unsigned int  ecc_strength;
+	unsigned int  page_size_in_bytes;
+	unsigned int  metadata_size_in_bytes;
+	unsigned int  ecc_chunk_size_in_bytes;
+	unsigned int  ecc_chunk_count;
+	unsigned int  payload_size_in_bytes;
+	unsigned int  auxiliary_size_in_bytes;
+	unsigned int  auxiliary_status_offset;
+	unsigned int  block_mark_byte_offset;
+	unsigned int  block_mark_bit_offset;
+};
+
+/**
+ * struct boot_rom_geometry - Boot ROM geometry description.
+ *
+ * This structure encapsulates decisions made by the Boot ROM Helper.
+ *
+ * @boot_area_count:             The number of boot areas. The first boot area
+ *                               appears at the beginning of chip 0, the next
+ *                               at the beginning of chip 1, etc.
+ * @boot_area_size_in_bytes:     The size, in bytes, of each boot area.
+ * @stride_size_in_pages:        The size of a boot block stride, in pages.
+ * @search_area_stride_exponent: The logarithm to base 2 of the size of a
+ *                               search area in boot block strides.
+ */
+
+struct boot_rom_geometry {
+	unsigned int  boot_area_count;
+	unsigned int  boot_area_size_in_bytes;
+	unsigned int  stride_size_in_pages;
+	unsigned int  search_area_stride_exponent;
+};
+
+/**
+ * struct gpmi_nfc_data - i.MX NFC per-device data.
+ *
+ * Note that the "device" managed by this driver represents the NAND Flash
+ * controller *and* the NAND Flash medium behind it. Thus, the per-device data
+ * structure has information about the controller, the chips to which it is
+ * connected, and properties of the medium as a whole.
+ *
+ * @dev:                 A pointer to the owning struct device.
+ * @pdev:                A pointer to the owning struct platform_device.
+ * @pdata:               A pointer to the device's platform data.
+ * @resources:           Information about system resources used by this driver.
+ * @device_info:         A structure that contains detailed information about
+ *                       the NAND Flash device.
+ * @physical_geometry:   A description of the medium's physical geometry.
+ * @nfc:                 A pointer to a structure that represents the underlying
+ *                       NFC hardware.
+ * @nfc_geometry:        A description of the medium geometry as viewed by the
+ *                       NFC.
+ * @rom:                 A pointer to a structure that represents the underlying
+ *                       Boot ROM.
+ * @rom_geometry:        A description of the medium geometry as viewed by the
+ *                       Boot ROM.
+ * @mil:                 A collection of information used by the MTD Interface
+ *                       Layer.
+ */
+
+struct gpmi_nfc_data {
+
+	/* System Interface */
+	struct device                  *dev;
+	struct platform_device         *pdev;
+	struct gpmi_nfc_platform_data  *pdata;
+
+	/* Resources */
+	struct resources               resources;
+
+	/* Flash Hardware */
+	struct nand_device_info        device_info;
+	struct physical_geometry       physical_geometry;
+
+	/* NFC HAL */
+	struct nfc_hal                 *nfc;
+	struct nfc_geometry            nfc_geometry;
+
+	/* Boot ROM Helper */
+	struct boot_rom_helper         *rom;
+	struct boot_rom_geometry       rom_geometry;
+
+	/* MTD Interface Layer */
+	struct mil                     mil;
+
+};
+
+/**
+ * struct gpmi_nfc_timing - GPMI NFC timing parameters.
+ *
+ * This structure contains the fundamental timing attributes for the NAND Flash
+ * bus and the GPMI NFC hardware.
+ *
+ * @data_setup_in_ns:         The data setup time, in nanoseconds. Usually the
+ *                            maximum of tDS and tWP. A negative value
+ *                            indicates this characteristic isn't known.
+ * @data_hold_in_ns:          The data hold time, in nanoseconds. Usually the
+ *                            maximum of tDH, tWH and tREH. A negative value
+ *                            indicates this characteristic isn't known.
+ * @address_setup_in_ns:      The address setup time, in nanoseconds. Usually
+ *                            the maximum of tCLS, tCS and tALS. A negative
+ *                            value indicates this characteristic isn't known.
+ * @gpmi_sample_delay_in_ns:  A GPMI-specific timing parameter. A negative value
+ *                            indicates this characteristic isn't known.
+ * @tREA_in_ns:               tREA, in nanoseconds, from the data sheet. A
+ *                            negative value indicates this characteristic isn't
+ *                            known.
+ * @tRLOH_in_ns:              tRLOH, in nanoseconds, from the data sheet. A
+ *                            negative value indicates this characteristic isn't
+ *                            known.
+ * @tRHOH_in_ns:              tRHOH, in nanoseconds, from the data sheet. A
+ *                            negative value indicates this characteristic isn't
+ *                            known.
+ */
+
+struct gpmi_nfc_timing {
+	int8_t  data_setup_in_ns;
+	int8_t  data_hold_in_ns;
+	int8_t  address_setup_in_ns;
+	int8_t  gpmi_sample_delay_in_ns;
+	int8_t  tREA_in_ns;
+	int8_t  tRLOH_in_ns;
+	int8_t  tRHOH_in_ns;
+};
+
+/**
+ * struct gpmi_nfc_hardware_timing - GPMI NFC hardware timing parameters.
+ *
+ * This structure contains timing information expressed in a form directly
+ * usable by the GPMI NFC hardware.
+ *
+ * @data_setup_in_cycles:      The data setup time, in cycles.
+ * @data_hold_in_cycles:       The data hold time, in cycles.
+ * @address_setup_in_cycles:   The address setup time, in cycles.
+ * @use_half_periods:          Indicates the clock is running slowly, so the
+ *                             NFC DLL should use half-periods.
+ * @sample_delay_factor:       The sample delay factor.
+ */
+
+struct gpmi_nfc_hardware_timing {
+	uint8_t  data_setup_in_cycles;
+	uint8_t  data_hold_in_cycles;
+	uint8_t  address_setup_in_cycles;
+	bool     use_half_periods;
+	uint8_t  sample_delay_factor;
+};
+
+/**
+ * struct nfc_hal - GPMI NFC HAL
+ *
+ * This structure embodies an abstract interface to the underlying NFC hardware.
+ *
+ * @version:                     The NFC hardware version.
+ * @description:                 A pointer to a human-readable description of
+ *                               the NFC hardware.
+ * @max_chip_count:              The maximum number of chips the NFC can
+ *                               possibly support (this value is a constant for
+ *                               each NFC version). This may *not* be the actual
+ *                               number of chips connected.
+ * @max_data_setup_cycles:       The maximum number of data setup cycles that
+ *                               can be expressed in the hardware.
+ * @internal_data_setup_in_ns:   The time, in ns, that the NFC hardware requires
+ *                               for data read internal setup. In the Reference
+ *                               Manual, see the chapter "High-Speed NAND
+ *                               Timing" for more details.
+ * @max_sample_delay_factor:     The maximum sample delay factor that can be
+ *                               expressed in the hardware.
+ * @max_dll_clock_period_in_ns:  The maximum period of the GPMI clock that the
+ *                               sample delay DLL hardware can possibly work
+ *                               with (the DLL is unusable with longer periods).
+ *                               If the full-cycle period is greater than HALF
+ *                               this value, the DLL must be configured to use
+ *                               half-periods.
+ * @max_dll_delay_in_ns:         The maximum amount of delay, in ns, that the
+ *                               DLL can implement.
+ * @dma_descriptors:             A pool of DMA descriptors.
+ * @isr_dma_channel:             The DMA channel with which the NFC HAL is
+ *                               working. We record this here so the ISR knows
+ *                               which DMA channel to acknowledge.
+ * @dma_done:                    The completion structure used for DMA
+ *                               interrupts.
+ * @bch_done:                    The completion structure used for BCH
+ *                               interrupts.
+ * @timing:                      The current timing configuration.
+ * @clock_frequency_in_hz:       The clock frequency, in Hz, during the current
+ *                               I/O transaction. If no I/O transaction is in
+ *                               progress, this is the clock frequency during
+ *                               the most recent I/O transaction.
+ * @hardware_timing:             The hardware timing configuration in effect
+ *                               during the current I/O transaction. If no I/O
+ *                               transaction is in progress, this is the
+ *                               hardware timing configuration during the most
+ *                               recent I/O transaction.
+ * @init:                        Initializes the NFC hardware and data
+ *                               structures. This function will be called after
+ *                               everything has been set up for communication
+ *                               with the NFC itself, but before the platform
+ *                               has set up off-chip communication. Thus, this
+ *                               function must not attempt to communicate with
+ *                               the NAND Flash hardware.
+ * @set_geometry:                Configures the NFC hardware and data structures
+ *                               to match the physical NAND Flash geometry.
+ * @set_geometry:                Configures the NFC hardware and data structures
+ *                               to match the physical NAND Flash geometry.
+ * @set_timing:                  Configures the NFC hardware and data structures
+ *                               to match the given NAND Flash bus timing.
+ * @get_timing:                  Returns the the clock frequency, in Hz, and
+ *                               the hardware timing configuration during the
+ *                               current I/O transaction. If no I/O transaction
+ *                               is in progress, this is the timing state during
+ *                               the most recent I/O transaction.
+ * @exit:                        Shuts down the NFC hardware and data
+ *                               structures. This function will be called after
+ *                               the platform has shut down off-chip
+ *                               communication but while communication with the
+ *                               NFC itself still works.
+ * @clear_bch:                   Clears a BCH interrupt (intended to be called
+ *                               by a more general interrupt handler to do
+ *                               device-specific clearing).
+ * @is_ready:                    Returns true if the given chip is ready.
+ * @begin:                       Begins an interaction with the NFC. This
+ *                               function must be called before *any* of the
+ *                               following functions so the NFC can prepare
+ *                               itself.
+ * @end:                         Ends interaction with the NFC. This function
+ *                               should be called to give the NFC a chance to,
+ *                               among other things, enter a lower-power state.
+ * @send_command:                Sends the given buffer of command bytes.
+ * @send_data:                   Sends the given buffer of data bytes.
+ * @read_data:                   Reads data bytes into the given buffer.
+ * @send_page:                   Sends the given given data and OOB bytes,
+ *                               using the ECC engine.
+ * @read_page:                   Reads a page through the ECC engine and
+ *                               delivers the data and OOB bytes to the given
+ *                               buffers.
+ */
+
+#define  NFC_DMA_DESCRIPTOR_COUNT  (4)
+
+struct nfc_hal {
+
+	/* Hardware attributes. */
+
+	const unsigned int      version;
+	const char              *description;
+	const unsigned int      max_chip_count;
+	const unsigned int      max_data_setup_cycles;
+	const unsigned int      internal_data_setup_in_ns;
+	const unsigned int      max_sample_delay_factor;
+	const unsigned int      max_dll_clock_period_in_ns;
+	const unsigned int      max_dll_delay_in_ns;
+
+	/* Working variables. */
+
+	struct mxs_dma_desc     *dma_descriptors[NFC_DMA_DESCRIPTOR_COUNT];
+	int                     isr_dma_channel;
+	struct completion       dma_done;
+	struct completion       bch_done;
+	struct gpmi_nfc_timing  timing;
+	unsigned long           clock_frequency_in_hz;
+
+	/* Configuration functions. */
+
+	int   (*init)        (struct gpmi_nfc_data *);
+	int   (*set_geometry)(struct gpmi_nfc_data *);
+	int   (*set_timing)  (struct gpmi_nfc_data *,
+					const struct gpmi_nfc_timing *);
+	void  (*get_timing)  (struct gpmi_nfc_data *,
+					unsigned long *clock_frequency_in_hz,
+					struct gpmi_nfc_hardware_timing *);
+	void  (*exit)        (struct gpmi_nfc_data *);
+
+	/* Call these functions to begin and end I/O. */
+
+	void  (*begin)       (struct gpmi_nfc_data *);
+	void  (*end)         (struct gpmi_nfc_data *);
+
+	/* Call these I/O functions only between begin() and end(). */
+
+	void  (*clear_bch)   (struct gpmi_nfc_data *);
+	int   (*is_ready)    (struct gpmi_nfc_data *, unsigned chip);
+	int   (*send_command)(struct gpmi_nfc_data *, unsigned chip,
+				dma_addr_t buffer, unsigned length);
+	int   (*send_data)   (struct gpmi_nfc_data *, unsigned chip,
+				dma_addr_t buffer, unsigned length);
+	int   (*read_data)   (struct gpmi_nfc_data *, unsigned chip,
+				dma_addr_t buffer, unsigned length);
+	int   (*send_page)   (struct gpmi_nfc_data *, unsigned chip,
+				dma_addr_t payload, dma_addr_t auxiliary);
+	int   (*read_page)   (struct gpmi_nfc_data *, unsigned chip,
+				dma_addr_t payload, dma_addr_t auxiliary);
+};
+
+/**
+ * struct boot_rom_helper - Boot ROM Helper
+ *
+ * This structure embodies the interface to an object that assists the driver
+ * in making decisions that relate to the Boot ROM.
+ *
+ * @version:                    The Boot ROM version.
+ * @description:                A pointer to a human-readable description of the
+ *                              Boot ROM.
+ * @swap_block_mark:            Indicates that the Boot ROM will swap the block
+ *                              mark with the first byte of the OOB.
+ * @set_geometry:               Configures the Boot ROM geometry.
+ * @check_transcription_stamp:  Checks for a transcription stamp. This pointer
+ *                              is ignored if swap_block_mark is set.
+ * @write_transcription_stamp:  Writes a transcription stamp. This pointer
+ *                              is ignored if swap_block_mark is set.
+ */
+
+struct boot_rom_helper {
+	const unsigned int  version;
+	const char          *description;
+	const int           swap_block_mark;
+	int  (*set_geometry)             (struct gpmi_nfc_data *);
+	int  (*check_transcription_stamp)(struct gpmi_nfc_data *);
+	int  (*write_transcription_stamp)(struct gpmi_nfc_data *);
+};
+
+/*
+ *------------------------------------------------------------------------------
+ * External Symbols
+ *------------------------------------------------------------------------------
+ */
+
+/* Event Reporting */
+
+#if defined(EVENT_REPORTING)
+	extern void gpmi_nfc_start_event_trace(char *description);
+	extern void gpmi_nfc_add_event(char *description, int delta);
+	extern void gpmi_nfc_stop_event_trace(char *description);
+	extern void gpmi_nfc_dump_event_trace(void);
+#else
+	#define gpmi_nfc_start_event_trace(description)  do {} while (0)
+	#define gpmi_nfc_add_event(description, delta)   do {} while (0)
+	#define gpmi_nfc_stop_event_trace(description)   do {} while (0)
+	#define gpmi_nfc_dump_event_trace()              do {} while (0)
+#endif
+
+/* NFC HAL Common Services */
+
+extern irqreturn_t gpmi_nfc_bch_isr(int irq, void *cookie);
+extern irqreturn_t gpmi_nfc_dma_isr(int irq, void *cookie);
+extern int gpmi_nfc_dma_init(struct gpmi_nfc_data *this);
+extern void gpmi_nfc_dma_exit(struct gpmi_nfc_data *this);
+extern int gpmi_nfc_set_geometry(struct gpmi_nfc_data *this);
+extern int gpmi_nfc_dma_go(struct gpmi_nfc_data *this, int  dma_channel);
+extern int gpmi_nfc_compute_hardware_timing(struct gpmi_nfc_data *this,
+					struct gpmi_nfc_hardware_timing *hw);
+
+/* NFC HAL Structures */
+
+extern struct nfc_hal  gpmi_nfc_hal_v0;
+extern struct nfc_hal  gpmi_nfc_hal_v1;
+
+/* Boot ROM Helper Common Services */
+
+extern int gpmi_nfc_rom_helper_set_geometry(struct gpmi_nfc_data *this);
+
+/* Boot ROM Helper Structures */
+
+extern struct boot_rom_helper  gpmi_nfc_boot_rom_helper_v0;
+extern struct boot_rom_helper  gpmi_nfc_boot_rom_helper_v1;
+
+/* MTD Interface Layer */
+
+extern int  gpmi_nfc_mil_init(struct gpmi_nfc_data *this);
+extern void gpmi_nfc_mil_exit(struct gpmi_nfc_data *this);
+
+#endif
diff --git a/drivers/mtd/nand/mxc_nd2.c b/drivers/mtd/nand/mxc_nd2.c
index 46e6380fe462..5ace73501cbb 100644
--- a/drivers/mtd/nand/mxc_nd2.c
+++ b/drivers/mtd/nand/mxc_nd2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -38,6 +38,7 @@ struct mxc_mtd_s {
 	struct nand_chip nand;
 	struct mtd_partition *parts;
 	struct device *dev;
+	int disable_bi_swap; /* disable bi swap */
 };
 
 static struct mxc_mtd_s *mxc_nand_data;
@@ -117,6 +118,49 @@ static const char *part_probes[] = {
 
 static wait_queue_head_t irq_waitq;
 
+#if 0
+static void nand_page_dump(struct mtd_info *mtd, u8 *dbuf, u8* obuf)
+{
+        int i;
+
+        if (dbuf != NULL) {
+                printk("\nData buffer:");
+                for (i = 0; i < mtd->writesize; i++) {
+                        if (!(i % 8))   printk("\n%03x: ", i);
+                        printk("%02x ", dbuf[i]);
+                }
+        }
+        printk("\n");
+        if (obuf != NULL) {
+                printk("\nOOB buffer:");
+                for (i = 0; i < mtd->oobsize; i++) {
+                        if (!(i % 8))   printk("\n%02x: ", i);
+                        printk("%02x ", obuf[i]);
+                }
+        }
+        printk("\n");
+}
+#endif
+
+#ifdef CONFIG_MXC_NAND_SWAP_BI
+#define PART_UBOOT_SIZE         0xc0000
+#define SKIP_SWAP_BI_MAX_PAGE           (PART_UBOOT_SIZE / 0x800)
+inline int skip_swap_bi(int page)
+{
+        /**
+         * Seems that the boot code of the i.mx515 rom is not able to
+         * boot from a nand flash when the data has been written swapping
+	 * the bad block byte. Avoid doing that (the swapping) when
+	 * programming U-Boot into the flash.
+         */
+        if (page < SKIP_SWAP_BI_MAX_PAGE)
+                return 1;
+        return 0;
+}
+#else
+inline int skip_swap_bi(int page_addr) { return 1; }
+#endif
+
 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 {
 	/* Disable Interuupt */
@@ -126,6 +170,30 @@ static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
+static void mxc_nand_bi_swap(struct mtd_info *mtd, int page_addr)
+{
+	u16 ma, sa, nma, nsa;
+
+	if (!IS_LARGE_PAGE_NAND)
+		return;
+
+	/* Disable bi swap if the user set disable_bi_swap at sys entry */
+	if (mxc_nand_data->disable_bi_swap)
+		return;
+
+        if (skip_swap_bi(page_addr))
+                return;
+
+	ma = __raw_readw(BAD_BLK_MARKER_MAIN);
+	sa = __raw_readw(BAD_BLK_MARKER_SP);
+
+	nma = (ma & 0xFF00) | (sa >> 8);
+	nsa = (sa & 0x00FF) | (ma << 8);
+
+	__raw_writew(nma, BAD_BLK_MARKER_MAIN);
+	__raw_writew(nsa, BAD_BLK_MARKER_SP);
+}
+
 static void nfc_memcpy(void *dest, void *src, int len)
 {
 	u8 *d = dest;
@@ -287,6 +355,7 @@ static void auto_cmd_interleave(struct mtd_info *mtd, u16 cmd)
 			/* data transfer */
 			memcpy(MAIN_AREA0, dbuf, dlen);
 			copy_spare(mtd, obuf, SPARE_AREA0, olen, false);
+                        mxc_nand_bi_swap(mtd, page_addr - 1);
 
 			/* update the value */
 			dbuf += dlen;
@@ -316,6 +385,7 @@ static void auto_cmd_interleave(struct mtd_info *mtd, u16 cmd)
 			mxc_check_ecc_status(mtd);
 
 			/* data transfer */
+                        mxc_nand_bi_swap(mtd, page_addr - 1);
 			memcpy(dbuf, MAIN_AREA0, dlen);
 			copy_spare(mtd, obuf, SPARE_AREA0, olen, true);
 
@@ -558,10 +628,7 @@ static int mxc_check_ecc_status(struct mtd_info *mtd)
 	u32 ecc_stat, err;
 	int no_subpages = 1;
 	int ret = 0;
-	u8 ecc_bit_mask, err_limit;
-
-	ecc_bit_mask = (IS_4BIT_ECC ? 0x7 : 0xf);
-	err_limit = (IS_4BIT_ECC ? 0x4 : 0x8);
+	u8 ecc_bit_mask = 0xf;
 
 	no_subpages = mtd->writesize >> 9;
 
@@ -570,7 +637,7 @@ static int mxc_check_ecc_status(struct mtd_info *mtd)
 	ecc_stat = GET_NFC_ECC_STATUS();
 	do {
 		err = ecc_stat & ecc_bit_mask;
-		if (err > err_limit) {
+		if (err == ecc_bit_mask) {
 			mtd->ecc_stats.failed++;
 			printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
 			return -1;
@@ -580,8 +647,7 @@ static int mxc_check_ecc_status(struct mtd_info *mtd)
 		ecc_stat >>= 4;
 	} while (--no_subpages);
 
-	mtd->ecc_stats.corrected += ret;
-	pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
+	pr_debug("Correctable ECC Error(%d)\n", ret);
 
 	return ret;
 }
@@ -930,6 +996,7 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 		 */
 		nfc_memcpy(MAIN_AREA0, data_buf, mtd->writesize);
 		copy_spare(mtd, oob_buf, SPARE_AREA0, mtd->oobsize, false);
+                mxc_nand_bi_swap(mtd, page_addr);
 #endif
 
 		if (IS_LARGE_PAGE_NAND)
@@ -980,10 +1047,10 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 		 * byte alignment, so we can use
 		 * memcpy safely
 		 */
+                mxc_nand_bi_swap(mtd, page_addr);
 		nfc_memcpy(data_buf, MAIN_AREA0, mtd->writesize);
 		copy_spare(mtd, oob_buf, SPARE_AREA0, mtd->oobsize, true);
 #endif
-
 		break;
 
 	case NAND_CMD_READID:
@@ -1096,6 +1163,14 @@ static int mxc_nand_scan_bbt(struct mtd_info *mtd)
 	/* jffs2 not write oob */
 	mtd->flags &= ~MTD_OOB_WRITEABLE;
 
+	/* fix up the offset */
+	largepage_memorybased.offs = BAD_BLK_MARKER_OOB_OFFS;
+	/* keep compatible for bbt table with old soc */
+	if (cpu_is_mx53()) {
+		bbt_mirror_descr.offs = BAD_BLK_MARKER_OOB_OFFS + 2;
+		bbt_main_descr.offs = BAD_BLK_MARKER_OOB_OFFS + 2;
+	}
+
 	/* use flash based bbt */
 	this->bbt_td = &bbt_main_descr;
 	this->bbt_md = &bbt_mirror_descr;
@@ -1126,6 +1201,52 @@ static int mxc_nand_scan_bbt(struct mtd_info *mtd)
 	return nand_scan_bbt(mtd, this->badblock_pattern);
 }
 
+static int mxc_get_resources(struct platform_device *pdev)
+{
+	struct resource *r;
+	int error = 0;
+
+#define	MXC_NFC_NO_IP_REG \
+	(cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx32() || cpu_is_mx35())
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!r) {
+		error = -ENXIO;
+		goto out_0;
+	}
+	nfc_axi_base = ioremap(r->start, resource_size(r));
+
+	if (!MXC_NFC_NO_IP_REG) {
+		r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (!r) {
+			error = -ENXIO;
+			goto out_1;
+		}
+	}
+	nfc_ip_base = ioremap(r->start, resource_size(r));
+
+	r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!r) {
+		error = -ENXIO;
+		goto out_2;
+	}
+
+	init_waitqueue_head(&irq_waitq);
+	error = request_irq(r->start, mxc_nfc_irq, 0, "mxc_nd", NULL);
+	if (error)
+		goto out_3;
+
+	return 0;
+out_3:
+out_2:
+	if (!MXC_NFC_NO_IP_REG)
+		iounmap(nfc_ip_base);
+out_1:
+	iounmap(nfc_axi_base);
+out_0:
+	return error;
+}
+
 static void mxc_nfc_init(void)
 {
 	/* Disable interrupt */
@@ -1137,11 +1258,13 @@ static void mxc_nfc_init(void)
 	/* Unlock the internal RAM Buffer */
 	raw_write(NFC_SET_BLS(NFC_BLS_UNLCOKED), REG_NFC_BLS);
 
-	/* Blocks to be unlocked */
-	UNLOCK_ADDR(0x0, 0xFFFF);
+	if (!(cpu_is_mx53())) {
+		/* Blocks to be unlocked */
+		UNLOCK_ADDR(0x0, 0xFFFF);
 
-	/* Unlock Block Command for given address range */
-	raw_write(NFC_SET_WPC(NFC_WPC_UNLOCK), REG_NFC_WPC);
+		/* Unlock Block Command for given address range */
+		raw_write(NFC_SET_WPC(NFC_WPC_UNLOCK), REG_NFC_WPC);
+	}
 
 	/* Enable symetric mode by default except mx37TO1.0 */
 	if (!(cpu_is_mx37_rev(CHIP_REV_1_0) == 1))
@@ -1232,6 +1355,81 @@ int nand_scan_mid(struct mtd_info *mtd)
 	return 0;
 }
 
+/*!
+ * show_device_disable_bi_swap()
+ * Shows the value of the 'disable_bi_swap' flag.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_disable_bi_swap(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	return sprintf(buf, "%d\n", mxc_nand_data->disable_bi_swap);
+}
+
+/*!
+ * store_device_disable_bi_swap()
+ * Sets the value of the 'disable_bi_swap' flag.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_disable_bi_swap(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	const char *p = buf;
+	unsigned long v;
+
+	/* Try to make sense of what arrived from user space. */
+
+	if (strict_strtoul(p, 0, &v) < 0)
+		return size;
+
+	if (v > 0)
+		v = 1;
+	mxc_nand_data->disable_bi_swap = v;
+	return size;
+
+}
+
+static DEVICE_ATTR(disable_bi_swap, 0644,
+	show_device_disable_bi_swap, store_device_disable_bi_swap);
+static struct device_attribute *device_attributes[] = {
+	&dev_attr_disable_bi_swap,
+};
+/*!
+ * manage_sysfs_files() - Creates/removes sysfs files for this device.
+ *
+ * @create: create/remove the sys entry.
+ */
+static void manage_sysfs_files(int create)
+{
+	struct device *dev = mxc_nand_data->dev;
+	int error;
+	unsigned int i;
+	struct device_attribute **attr;
+
+	for (i = 0, attr = device_attributes;
+			i < ARRAY_SIZE(device_attributes); i++, attr++) {
+
+		if (create) {
+			error = device_create_file(dev, *attr);
+			if (error) {
+				while (--attr >= device_attributes)
+					device_remove_file(dev, *attr);
+				return;
+			}
+		} else {
+			device_remove_file(dev, *attr);
+		}
+	}
+
+}
+
 
 /*!
  * This function is called during the driver binding process.
@@ -1249,8 +1447,10 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 	struct flash_platform_data *flash = pdev->dev.platform_data;
 	int nr_parts = 0, err = 0;
 
-	nfc_axi_base = IO_ADDRESS(NFC_AXI_BASE_ADDR);
-	nfc_ip_base = IO_ADDRESS(NFC_BASE_ADDR);
+	/* get the resource */
+	err = mxc_get_resources(pdev);
+	if (err)
+		goto out;
 
 	/* init the nfc */
 	mxc_nfc_init();
@@ -1299,12 +1499,6 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 	nfc_clk = clk_get(&pdev->dev, "nfc_clk");
 	clk_enable(nfc_clk);
 
-	init_waitqueue_head(&irq_waitq);
-	err = request_irq(MXC_INT_NANDFC, mxc_nfc_irq, 0, "mxc_nd", NULL);
-	if (err) {
-		goto out_1;
-	}
-
 	if (hardware_ecc) {
 		this->ecc.read_page = mxc_nand_read_page;
 		this->ecc.write_page = mxc_nand_write_page;
@@ -1359,6 +1553,16 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 		add_mtd_device(mtd);
 	}
 
+#ifdef CONFIG_MODULE_CCXMX51
+        {
+                extern u8 ccwmx51_swap_bi;
+                mxc_nand_data->disable_bi_swap = !ccwmx51_swap_bi;
+                pr_info("%sUsing swap BI (%x)\n", ccwmx51_swap_bi ? "" : "No ", ccwmx51_swap_bi);
+        }
+#endif
+	/* Create sysfs entries for this device. */
+	manage_sysfs_files(true);
+
 	platform_set_drvdata(pdev, mtd);
 
 	return 0;
@@ -1386,6 +1590,7 @@ static int __exit mxcnd_remove(struct platform_device *pdev)
 	if (flash->exit)
 		flash->exit();
 
+	manage_sysfs_files(false);
 	mxc_free_buf();
 
 	clk_disable(nfc_clk);
diff --git a/drivers/mtd/nand/mxc_nd2.h b/drivers/mtd/nand/mxc_nd2.h
index ea128f6da41b..e8ef125ce8e7 100644
--- a/drivers/mtd/nand/mxc_nd2.h
+++ b/drivers/mtd/nand/mxc_nd2.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -32,16 +32,37 @@
 #define IS_LARGE_PAGE_NAND      ((mtd->writesize / num_of_interleave) > 512)
 
 #define GET_NAND_OOB_SIZE	(mtd->oobsize / num_of_interleave)
+#define GET_NAND_PAGE_SIZE      (mtd->writesize / num_of_interleave)
 
 #define NAND_PAGESIZE_2KB	2048
 #define NAND_PAGESIZE_4KB	4096
 
+/*
+ * main area for bad block marker is in the last data section
+ * the spare area for swapped bad block marker is the second
+ * byte of last spare section
+ */
+#define NAND_SECTIONS        (GET_NAND_PAGE_SIZE >> 9)
+#define NAND_OOB_PER_SECTION (((GET_NAND_OOB_SIZE / NAND_SECTIONS) >> 1) << 1)
+#define NAND_CHUNKS	     (GET_NAND_PAGE_SIZE / (512 + NAND_OOB_PER_SECTION))
+
+#define BAD_BLK_MARKER_MAIN_OFFS \
+	(GET_NAND_PAGE_SIZE - NAND_CHUNKS * NAND_OOB_PER_SECTION)
+
+#define BAD_BLK_MARKER_SP_OFFS (NAND_CHUNKS * SPARE_LEN)
+
+#define BAD_BLK_MARKER_OOB_OFFS (NAND_CHUNKS * NAND_OOB_PER_SECTION)
+
+#define BAD_BLK_MARKER_MAIN  \
+	((u32)MAIN_AREA0 + BAD_BLK_MARKER_MAIN_OFFS)
+
+#define BAD_BLK_MARKER_SP  \
+	((u32)SPARE_AREA0 + BAD_BLK_MARKER_SP_OFFS)
+
 #ifdef CONFIG_ARCH_MXC_HAS_NFC_V3
 /*
  * For V3 NFC registers Definition
  */
-/* AXI Bus Mapped */
-#define NFC_AXI_BASE_ADDR		MX51_NFC_BASE_ADDR_AXI
 
 #if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1)	/* mx37 */
 #define MXC_INT_NANDFC			MXC_INT_EMI
@@ -106,13 +127,6 @@
 #define NFC_SPAS_WIDTH 8
 #define NFC_SPAS_SHIFT 16
 
-#define IS_4BIT_ECC \
-( \
-	cpu_is_mx51_rev(CHIP_REV_2_0) > 0 ? \
-		!((raw_read(NFC_CONFIG2) & NFC_ECC_MODE_4) >> 6) : \
-		((raw_read(NFC_CONFIG2) & NFC_ECC_MODE_4) >> 6) \
-)
-
 #define NFC_SET_SPAS(v)			\
 	raw_write((((raw_read(NFC_CONFIG2) & \
 	NFC_FIELD_RESET(NFC_SPAS_WIDTH, NFC_SPAS_SHIFT)) | ((v) << 16))), \
@@ -120,24 +134,32 @@
 
 #define NFC_SET_ECC_MODE(v)		\
 do { \
-	if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) { \
+	if (cpu_is_mx53() > 0) { \
 		if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \
 			raw_write(((raw_read(NFC_CONFIG2) & \
-					NFC_ECC_MODE_MASK) | \
-					NFC_ECC_MODE_4), NFC_CONFIG2); \
+					~(3 << 6)) | \
+					NFC_ECC_MODE_16), NFC_CONFIG2); \
 		else \
 			raw_write(((raw_read(NFC_CONFIG2) & \
-					NFC_ECC_MODE_MASK) & \
+					~(3 << 6)) & \
+					NFC_ECC_MODE_4), NFC_CONFIG2); \
+	} else if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) { \
+		if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \
+			raw_write(((raw_read(NFC_CONFIG2) & \
+					~(1 << 6)) | \
 					NFC_ECC_MODE_8), NFC_CONFIG2); \
+		else \
+			raw_write(((raw_read(NFC_CONFIG2) & \
+					~(1 << 6)) & \
+                                        ~NFC_ECC_MODE_8), NFC_CONFIG2); \
 	} else { \
 		if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \
 			raw_write(((raw_read(NFC_CONFIG2) & \
-					NFC_ECC_MODE_MASK) & \
-					NFC_ECC_MODE_8), NFC_CONFIG2); \
+					~(1 << 6))), NFC_CONFIG2); \
 		else \
 			raw_write(((raw_read(NFC_CONFIG2) & \
-					NFC_ECC_MODE_MASK) | \
-					NFC_ECC_MODE_4), NFC_CONFIG2); \
+					~(1 << 6)) | \
+                                        NFC_ECC_MODE_8), NFC_CONFIG2); \
 	} \
 } while (0)
 
@@ -151,7 +173,6 @@ do { \
 	} while(0)
 
 #else
-#define IS_4BIT_ECC			1
 #define NFC_SET_SPAS(v)
 #define NFC_SET_ECC_MODE(v)
 #define NFC_SET_NFMS(v)	(NFMS |= (v))
@@ -292,9 +313,10 @@ do { \
 #define NFC_WPC_RESET			~(7)
 #if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) || \
     defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2)
-#define NFC_ECC_MODE_4    		(1 << 6)
-#define NFC_ECC_MODE_8			~(1 << 6)
-#define NFC_ECC_MODE_MASK 		~(1 << 6)
+#define NFC_ECC_MODE_4    		(0x0 << 6)
+#define NFC_ECC_MODE_8			(0x1 << 6)
+#define NFC_ECC_MODE_14                 (0x3 << 6)
+#define NFC_ECC_MODE_16                 (0x3 << 6)
 #define NFC_SPAS_16			8
 #define NFC_SPAS_64		 	32
 #define NFC_SPAS_128			64
@@ -454,7 +476,8 @@ do {	\
 		NFC_SET_ST_CMD(0x70); \
 		raw_write(raw_read(NFC_CONFIG3) | NFC_NO_SDMA, NFC_CONFIG3); \
 		raw_write(raw_read(NFC_CONFIG3) | NFC_RBB_MODE, NFC_CONFIG3); \
-		SET_NFC_DELAY_LINE(0); \
+		if (cpu_is_mx51()) \
+			SET_NFC_DELAY_LINE(0); \
 	} \
 } while (0)
 #endif
@@ -472,14 +495,13 @@ do {	\
  * For V1/V2 NFC registers Definition
  */
 
-#define NFC_AXI_BASE_ADDR      		0x00
 /*
  * Addresses for NFC registers
  */
 #ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1
-#define NFC_REG_BASE			(nfc_ip_base + 0x1000)
+#define NFC_REG_BASE			(nfc_axi_base + 0x1000)
 #else
-#define NFC_REG_BASE			nfc_ip_base
+#define NFC_REG_BASE			nfc_axi_base
 #endif
 #define NFC_BUF_SIZE            	(NFC_REG_BASE + 0xE00)
 #define NFC_BUF_ADDR            	(NFC_REG_BASE + 0xE04)
@@ -517,18 +539,18 @@ do {	\
 /*!
  * Addresses for NFC RAM BUFFER Main area 0
  */
-#define MAIN_AREA0      		(u16 *)(nfc_ip_base + 0x000)
-#define MAIN_AREA1      		(u16 *)(nfc_ip_base + 0x200)
+#define MAIN_AREA0      		(u16 *)(nfc_axi_base + 0x000)
+#define MAIN_AREA1      		(u16 *)(nfc_axi_base + 0x200)
 
 /*!
  * Addresses for NFC SPARE BUFFER Spare area 0
  */
 #ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1
-#define SPARE_AREA0     		(u16 *)(nfc_ip_base + 0x1000)
+#define SPARE_AREA0     		(u16 *)(nfc_axi_base + 0x1000)
 #define SPARE_LEN			64
 #define SPARE_COUNT			8
 #else
-#define SPARE_AREA0     		(u16 *)(nfc_ip_base + 0x800)
+#define SPARE_AREA0     		(u16 *)(nfc_axi_base + 0x800)
 #define SPARE_LEN       		16
 #define SPARE_COUNT     		4
 #endif
@@ -539,8 +561,6 @@ do {	\
 #define SPAS_SHIFT		(0)
 #define REG_NFC_SPAS NFC_SPAS
 #define SPAS_MASK	(0xFF00)
-#define IS_4BIT_ECC			\
-	((raw_read(REG_NFC_ECC_MODE) & NFC_ECC_MODE_4) >> 0)
 
 #define NFC_SET_SPAS(v)			\
 	raw_write(((raw_read(REG_NFC_SPAS) & SPAS_MASK) | ((v<<SPAS_SHIFT))), \
@@ -578,7 +598,6 @@ do { \
 	} \
 } while (0)
 #else
-#define IS_4BIT_ECC			(1)
 #define NFC_SET_SPAS(v)
 #define NFC_SET_ECC_MODE(v)
 #define GET_ECC_STATUS()  raw_read(REG_NFC_ECC_STATUS_RESULT);
diff --git a/drivers/mtd/nand/nand_device_info.c b/drivers/mtd/nand/nand_device_info.c
index ecd5b21189cc..1ab1d1d21811 100644
--- a/drivers/mtd/nand/nand_device_info.c
+++ b/drivers/mtd/nand/nand_device_info.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -1284,9 +1284,9 @@ static struct nand_device_info nand_device_info_table_type_9[] __initdata =
 	.data_hold_in_ns          = 10,
 	.address_setup_in_ns      = 25,
 	.gpmi_sample_delay_in_ns  = 6,
-	.tREA_in_ns               = -1,
-	.tRLOH_in_ns              = -1,
-	.tRHOH_in_ns              = -1,
+	.tREA_in_ns               = 20,
+	.tRLOH_in_ns              = 5,
+	.tRHOH_in_ns              = 15,
 	"K9LBG08U0D",
 	},
 	{
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 89bf85af642c..40b5658bdbe6 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -102,8 +102,8 @@ static int ndfc_calculate_ecc(struct mtd_info *mtd,
 	wmb();
 	ecc = in_be32(ndfc->ndfcbase + NDFC_ECC);
 	/* The NDFC uses Smart Media (SMC) bytes order */
-	ecc_code[0] = p[2];
-	ecc_code[1] = p[1];
+	ecc_code[0] = p[1];
+	ecc_code[1] = p[2];
 	ecc_code[2] = p[3];
 
 	return 0;
diff --git a/drivers/mtd/ofpart.c b/drivers/mtd/ofpart.c
index 3e164f0c9295..62d6a78c4eee 100644
--- a/drivers/mtd/ofpart.c
+++ b/drivers/mtd/ofpart.c
@@ -46,21 +46,12 @@ int __devinit of_mtd_parse_partitions(struct device *dev,
 		const u32 *reg;
 		int len;
 
-		/* check if this is a partition node */
-		partname = of_get_property(pp, "name", &len);
-		if (strcmp(partname, "partition") != 0) {
+		reg = of_get_property(pp, "reg", &len);
+		if (!reg) {
 			nr_parts--;
 			continue;
 		}
 
-		reg = of_get_property(pp, "reg", &len);
-		if (!reg || (len != 2 * sizeof(u32))) {
-			of_node_put(pp);
-			dev_err(dev, "Invalid 'reg' on %s\n", node->full_name);
-			kfree(*pparts);
-			*pparts = NULL;
-			return -EINVAL;
-		}
 		(*pparts)[i].offset = reg[0];
 		(*pparts)[i].size = reg[1];
 
@@ -75,6 +66,14 @@ int __devinit of_mtd_parse_partitions(struct device *dev,
 		i++;
 	}
 
+	if (!i) {
+		of_node_put(pp);
+		dev_err(dev, "No valid partition found on %s\n", node->full_name);
+		kfree(*pparts);
+		*pparts = NULL;
+		return -EINVAL;
+	}
+
 	return nr_parts;
 }
 EXPORT_SYMBOL(of_mtd_parse_partitions);
diff --git a/drivers/mtd/ubi/cdev.c b/drivers/mtd/ubi/cdev.c
index f237ddbb2713..111ea41c4ecd 100644
--- a/drivers/mtd/ubi/cdev.c
+++ b/drivers/mtd/ubi/cdev.c
@@ -853,7 +853,6 @@ static long ubi_cdev_ioctl(struct file *file, unsigned int cmd,
 			break;
 		}
 
-		req.name[req.name_len] = '\0';
 		err = verify_mkvol_req(ubi, &req);
 		if (err)
 			break;
diff --git a/drivers/mxc/Kconfig b/drivers/mxc/Kconfig
index 6e67087d2efa..b26c1dc11ad6 100644
--- a/drivers/mxc/Kconfig
+++ b/drivers/mxc/Kconfig
@@ -33,6 +33,7 @@ source "drivers/mxc/bt/Kconfig"
 source "drivers/mxc/gps_ioctrl/Kconfig"
 source "drivers/mxc/mlb/Kconfig"
 source "drivers/mxc/adc/Kconfig"
+source "drivers/mxc/amd-gpu/Kconfig"
 
 endmenu
 
diff --git a/drivers/mxc/Makefile b/drivers/mxc/Makefile
index 6416bc429888..5193fa50eb9f 100644
--- a/drivers/mxc/Makefile
+++ b/drivers/mxc/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_MXC_BLUETOOTH)		+= bt/
 obj-$(CONFIG_GPS_IOCTRL)		+= gps_ioctrl/
 obj-$(CONFIG_MXC_MLB)                   += mlb/
 obj-$(CONFIG_IMX_ADC)                   += adc/
+obj-$(CONFIG_MXC_AMD_GPU)                   += amd-gpu/
diff --git a/drivers/mxc/amd-gpu/Kconfig b/drivers/mxc/amd-gpu/Kconfig
new file mode 100644
index 000000000000..f4f442787deb
--- /dev/null
+++ b/drivers/mxc/amd-gpu/Kconfig
@@ -0,0 +1,13 @@
+#
+# Bluetooth configuration
+#
+
+menu "MXC GPU support"
+
+config MXC_AMD_GPU
+	tristate "MXC GPU support"
+	depends on ARCH_MX35 || ARCH_MX51 || ARCH_MX53
+	---help---
+         Say Y to get the GPU driver support.
+
+endmenu
diff --git a/drivers/mxc/amd-gpu/Makefile b/drivers/mxc/amd-gpu/Makefile
new file mode 100644
index 000000000000..a661de4d6a76
--- /dev/null
+++ b/drivers/mxc/amd-gpu/Makefile
@@ -0,0 +1,49 @@
+EXTRA_CFLAGS := \
+	-D_LINUX \
+	-I$(obj)/include \
+	-I$(obj)/include/api \
+	-I$(obj)/include/ucode \
+	-I$(obj)/platform/hal/linux \
+	-I$(obj)/os/include \
+	-I$(obj)/os/kernel/include \
+	-I$(obj)/os/user/include
+
+obj-$(CONFIG_MXC_AMD_GPU) += gpu.o
+gpu-objs += 	common/gsl_cmdstream.o \
+		common/gsl_cmdwindow.o \
+		common/gsl_context.o \
+		common/gsl_debug_pm4.o \
+		common/gsl_device.o \
+		common/gsl_drawctxt.o \
+		common/gsl_driver.o \
+		common/gsl_g12.o \
+		common/gsl_intrmgr.o \
+		common/gsl_memmgr.o \
+		common/gsl_mmu.o \
+		common/gsl_ringbuffer.o \
+		common/gsl_sharedmem.o \
+		common/gsl_yamato.o \
+		platform/hal/linux/gsl_linux_map.o \
+		platform/hal/linux/gsl_kmod.o \
+		platform/hal/linux/gsl_kmod_cleanup.o \
+		platform/hal/linux/misc.o \
+		os/kernel/src/linux/kos_lib.o
+ifeq ($(CONFIG_ARCH_MX5),y)
+EXTRA_CFLAGS += -DMX51=1 \
+		-I$(obj)/platform/hal/MX51 \
+		-I$(obj)/platform/hal/MX51/linux \
+		-I$(obj)/platform/hal/MX51/memcfg
+
+gpu-objs +=	platform/hal/MX51/linux/gsl_hal.o \
+		platform/hal/MX51/memcfg/gsl_memcfg.o
+endif
+
+ifeq ($(CONFIG_ARCH_MX35),y)
+EXTRA_CFLAGS += -DMX35=1 \
+		-I$(obj)/platform/hal/MX35 \
+		-I$(obj)/platform/hal/MX35/linux \
+		-I$(obj)/platform/hal/MX35/memcfg
+
+gpu-objs +=	platform/hal/MX35/linux/gsl_hal.o \
+		platform/hal/MX35/memcfg/gsl_memcfg.o
+endif
diff --git a/drivers/mxc/amd-gpu/common/gsl_cmdstream.c b/drivers/mxc/amd-gpu/common/gsl_cmdstream.c
new file mode 100644
index 000000000000..338192c7ba32
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_cmdstream.c
@@ -0,0 +1,239 @@
+/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#include "gsl_cmdstream.h"
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_cmdstream_init(gsl_device_t *device)
+{
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_cmdstream_close(gsl_device_t *device)
+{
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+gsl_timestamp_t
+kgsl_cmdstream_readtimestamp0(gsl_deviceid_t device_id, gsl_timestamp_type_t type)
+{
+    gsl_timestamp_t   timestamp = -1;
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_timestamp_t kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id=%d gsl_timestamp_type_t type=%d)\n", device_id, type );
+#if (defined(GSL_BLD_G12) && defined(IRQTHREAD_POLL))
+    kos_event_signal(device->irqthread_event);
+#endif
+    if (type == GSL_TIMESTAMP_CONSUMED)
+    {
+        // start-of-pipeline timestamp
+        GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, (unsigned int*)&timestamp);
+    }
+    else if (type == GSL_TIMESTAMP_RETIRED)
+    {
+		// end-of-pipeline timestamp
+		GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (unsigned int*)&timestamp);
+    }
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_readtimestamp. Return value %d\n", timestamp );
+    return (timestamp);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API gsl_timestamp_t
+kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id, gsl_timestamp_type_t type)
+{
+	gsl_timestamp_t timestamp = -1;
+	GSL_API_MUTEX_LOCK();
+	timestamp = kgsl_cmdstream_readtimestamp0(device_id, type);
+	GSL_API_MUTEX_UNLOCK();
+	return timestamp;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_cmdstream_issueibcmds(gsl_deviceid_t device_id, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    int status = GSL_FAILURE;
+    GSL_API_MUTEX_LOCK();
+    
+    kgsl_device_active(device);
+     
+    if (device->ftbl.cmdstream_issueibcmds)
+    {
+        status = device->ftbl.cmdstream_issueibcmds(device, drawctxt_index, ibaddr, sizedwords, timestamp, flags);
+    }
+    GSL_API_MUTEX_UNLOCK();
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_add_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t *timestamp)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    int status = GSL_FAILURE;
+    GSL_API_MUTEX_LOCK();
+    if (device->ftbl.device_addtimestamp)
+    {
+        status = device->ftbl.device_addtimestamp(device, timestamp);
+    }
+    GSL_API_MUTEX_UNLOCK();
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API
+int kgsl_cmdstream_waittimestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp, unsigned int timeout)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+	int status = GSL_FAILURE;
+	if (device->ftbl.device_waittimestamp)
+    {
+        status = device->ftbl.device_waittimestamp(device, timestamp, timeout);
+    }
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_cmdstream_memqueue_drain(gsl_device_t *device)
+{
+    gsl_memnode_t     *memnode, *nextnode, *freehead;
+    gsl_timestamp_t   timestamp, ts_processed;
+    gsl_memqueue_t    *memqueue = &device->memqueue;
+    // check head
+    if (memqueue->head == NULL)
+    {
+        return;
+    }
+    // get current EOP timestamp
+    ts_processed = kgsl_cmdstream_readtimestamp0(device->id, GSL_TIMESTAMP_RETIRED);
+    timestamp = memqueue->head->timestamp;
+    // check head timestamp
+    if (!(((ts_processed - timestamp) >= 0) || ((ts_processed - timestamp) < -20000)))
+    {
+        return;
+    }
+    memnode  = memqueue->head;
+    freehead = memqueue->head;
+    // get node list to free
+    for(;;)
+    {
+        nextnode  = memnode->next;
+        if (nextnode == NULL)
+        {
+            // entire queue drained
+            memqueue->head = NULL;
+            memqueue->tail = NULL;
+            break;
+        }
+        timestamp = nextnode->timestamp;
+        if (!(((ts_processed - timestamp) >= 0) || ((ts_processed - timestamp) < -20000)))
+        {
+            // drained up to a point
+            memqueue->head = nextnode;
+            memnode->next  = NULL;
+            break;
+        }
+        memnode = nextnode;
+    }
+    // free nodes
+    while (freehead)
+    {
+        memnode  = freehead;
+        freehead = memnode->next;
+        kgsl_sharedmem_free0(&memnode->memdesc, memnode->pid);
+        kos_free(memnode);
+    }
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_cmdstream_freememontimestamp(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type)
+{
+    gsl_memnode_t  *memnode;
+    gsl_device_t   *device = &gsl_driver.device[device_id-1];
+    gsl_memqueue_t *memqueue;
+    (void)type; // unref. For now just use EOP timestamp
+
+	GSL_API_MUTEX_LOCK();
+
+	memqueue = &device->memqueue;
+
+    memnode  = kos_malloc(sizeof(gsl_memnode_t));
+
+    if (!memnode)
+    {
+        // other solution is to idle and free which given that the upper level driver probably wont check, probably a better idea
+		GSL_API_MUTEX_UNLOCK();
+        return (GSL_FAILURE);
+    }
+
+    memnode->timestamp = timestamp;
+    memnode->pid       = GSL_CALLER_PROCESSID_GET();
+    memnode->next      = NULL;
+    kos_memcpy(&memnode->memdesc, memdesc, sizeof(gsl_memdesc_t));
+
+    // add to end of queue
+    if (memqueue->tail != NULL)
+    {
+        memqueue->tail->next = memnode;
+        memqueue->tail       = memnode;
+    }
+    else
+    {
+        KOS_ASSERT(memqueue->head == NULL);
+        memqueue->head = memnode;
+        memqueue->tail = memnode;
+    }
+
+	GSL_API_MUTEX_UNLOCK();
+
+    return (GSL_SUCCESS);
+}
+
+static int kgsl_cmdstream_timestamp_cmp(gsl_timestamp_t ts_new, gsl_timestamp_t ts_old)
+{
+	gsl_timestamp_t ts_diff = ts_new - ts_old;
+	return (ts_diff >= 0) || (ts_diff < -20000);
+}
+
+int kgsl_cmdstream_check_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp)
+{
+	gsl_timestamp_t ts_processed;
+	ts_processed = kgsl_cmdstream_readtimestamp0(device_id, GSL_TIMESTAMP_RETIRED);
+	return kgsl_cmdstream_timestamp_cmp(ts_processed, timestamp);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c b/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c
new file mode 100644
index 000000000000..4d70da5b25c8
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c
@@ -0,0 +1,136 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+#ifdef GSL_BLD_G12
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_CMDWINDOW_TARGET_MASK       0x000000FF
+#define GSL_CMDWINDOW_ADDR_MASK         0x00FFFF00
+#define GSL_CMDWINDOW_TARGET_SHIFT      0
+#define GSL_CMDWINDOW_ADDR_SHIFT        8
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_cmdwindow_init(gsl_device_t *device)
+{
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int 
+kgsl_cmdwindow_close(gsl_device_t *device)
+{
+    return (GSL_SUCCESS);
+}
+
+#endif // GSL_BLD_G12
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_cmdwindow_write0(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data)
+{
+#ifdef GSL_BLD_G12
+    gsl_device_t  *device;
+    unsigned int  cmdwinaddr;
+    unsigned int  cmdstream;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_cmdwindow_write( gsl_device_id_t device_id=%d, gsl_cmdwindow_t target=%d, unsigned int addr=0x%08x, unsigned int data=0x%08x)\n", device_id, target, addr, data );
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    if (target < GSL_CMDWINDOW_MIN || target > GSL_CMDWINDOW_MAX)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid target.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    if ((!(device->flags & GSL_FLAGS_INITIALIZED) && target == GSL_CMDWINDOW_MMU) ||
+        (!(device->flags & GSL_FLAGS_STARTED)     && target != GSL_CMDWINDOW_MMU))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device state to write to selected targer.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // set command stream
+    if (target == GSL_CMDWINDOW_MMU)
+    {
+#ifdef GSL_NO_MMU
+        return (GSL_SUCCESS);
+#endif
+        cmdstream = ADDR_VGC_MMUCOMMANDSTREAM;
+    }
+    else
+    {
+        cmdstream = ADDR_VGC_COMMANDSTREAM;
+    }
+
+
+    // set command window address
+    cmdwinaddr  = ((target << GSL_CMDWINDOW_TARGET_SHIFT) & GSL_CMDWINDOW_TARGET_MASK);
+    cmdwinaddr |= ((addr   << GSL_CMDWINDOW_ADDR_SHIFT)   & GSL_CMDWINDOW_ADDR_MASK);
+
+#ifndef GSL_NO_MMU
+    // set mmu pagetable
+	kgsl_mmu_setpagetable(device, GSL_CALLER_PROCESSID_GET());
+#endif
+
+    // write command window address
+    device->ftbl.device_regwrite(device, (cmdstream)>>2, cmdwinaddr);
+
+    // write data
+    device->ftbl.device_regwrite(device, (cmdstream)>>2, data);
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+#else
+    // unreferenced formal parameter
+    (void) device_id;
+    (void) target;
+    (void) addr;
+    (void) data;
+
+    return (GSL_FAILURE);
+#endif // GSL_BLD_G12
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_cmdwindow_write(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_cmdwindow_write0(device_id, target, addr, data);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_context.c b/drivers/mxc/amd-gpu/common/gsl_context.c
new file mode 100644
index 000000000000..c999247b3afd
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_context.c
@@ -0,0 +1,74 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#include "gsl_context.h"
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+KGSL_API int
+kgsl_context_create(gsl_deviceid_t device_id, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    int status;
+
+    GSL_API_MUTEX_LOCK();
+
+    if (device->ftbl.context_create)
+    {
+        status = device->ftbl.context_create(device, type, drawctxt_id, flags);
+    }
+    else
+    {
+        status = GSL_FAILURE;
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_context_destroy(gsl_deviceid_t device_id, unsigned int drawctxt_id)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    int status;
+
+    GSL_API_MUTEX_LOCK();
+
+    if (device->ftbl.context_destroy)
+    {
+        status = device->ftbl.context_destroy(device, drawctxt_id);
+    }
+    else
+    {
+        status = GSL_FAILURE;
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
diff --git a/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c b/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c
new file mode 100644
index 000000000000..847df8dbe386
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c
@@ -0,0 +1,1015 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+#if defined(_WIN32) && defined (GSL_BLD_YAMATO)
+
+#include <stdio.h>
+#include <string.h>
+#include <stdarg.h>
+
+//#define PM4_DEBUG_USE_MEMBUF
+
+#ifdef PM4_DEBUG_USE_MEMBUF
+
+#define MEMBUF_SIZE 100000
+#define BUFFER_END_MARGIN 1000
+char memBuf[MEMBUF_SIZE];
+static int writePtr = 0;
+static unsigned int lineNumber = 0;
+//#define fprintf(A,...); writePtr += sprintf( memBuf+writePtr, __VA_ARGS__ ); sprintf( memBuf+writePtr, "###" ); if( writePtr > MEMBUF_SIZE-BUFFER_END_MARGIN ) { memset(memBuf+writePtr, '#', MEMBUF_SIZE-writePtr); writePtr = 0; }
+#define FILE char
+#define fopen(X,Y) 0
+#define fclose(X)
+
+int printString( FILE *_File, const char * _Format, ...)
+{
+    int ret;
+    va_list ap;
+    (void)_File;
+
+    va_start(ap, _Format);
+    if( writePtr > 0 && memBuf[writePtr-1] == '\n' )
+    {
+        // Add line number if last written character was newline
+        writePtr += sprintf( memBuf+writePtr, "%d: ", lineNumber++ );
+    }
+    ret = vsprintf(memBuf+writePtr, _Format, ap);
+    writePtr += ret;
+    sprintf( memBuf+writePtr, "###" );
+    if( writePtr > MEMBUF_SIZE-BUFFER_END_MARGIN ) 
+    { 
+        memset(memBuf+writePtr, '#', MEMBUF_SIZE-writePtr); 
+        writePtr = 0;
+    }
+
+    va_end(ap);
+
+    return ret;
+}
+
+#else
+
+int printString( FILE *_File, const char * _Format, ...)
+{
+    int ret;
+    va_list ap;
+    va_start(ap, _Format);
+    ret = vfprintf(_File, _Format, ap);
+    va_end(ap);
+    fflush(_File);
+    return ret;
+}
+
+#endif
+
+#ifndef    _WIN32_WCE
+#define PM4_DUMPFILE    "pm4dump.txt"
+#else
+#define PM4_DUMPFILE    "\\Release\\pm4dump.txt"
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+// defines
+//////////////////////////////////////////////////////////////////////////////
+#define EXPAND_OPCODE(opcode) ((opcode << 8) | PM4_PKT_MASK)
+
+#define GetString_uint                       GetString_int
+#define GetString_fixed12_4(val, szValue)    GetString_fixed(val, 12, 4, szValue)
+#define GetString_signedint15(val, szValue)  GetString_signedint(val, 15, szValue)
+
+// Need a prototype for this function
+void WritePM4Packet_Type3(FILE* pFile, unsigned int dwHeader, unsigned int** ppBuffer);
+
+static int indirectionLevel = 0;
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+void WriteDWORD(FILE* pFile, unsigned int dwValue)
+{
+    printString(pFile, "    0x%08x", dwValue);
+}
+
+void WriteDWORD2(FILE* pFile, unsigned int dwValue)
+{
+    printString(pFile, "    0x%08x\n", dwValue);
+}
+
+//----------------------------------------------------------------------------
+
+// Generate the GetString_## functions for enumerated types
+#define START_ENUMTYPE(__type)                      \
+void GetString_##__type(unsigned int val, char* szValue)   \
+{                                                   \
+    switch(val)                                     \
+    {
+
+#define GENERATE_ENUM(__enumname, __val)            \
+        case __val:                                 \
+            kos_strcpy(szValue, #__enumname);        \
+            break;
+
+#define END_ENUMTYPE(__type)                        \
+        default:                                    \
+            sprintf(szValue, "Unknown: %d", val);   \
+            break;                                  \
+    }                                               \
+}
+
+#include _YAMATO_GENENUM_H
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_hex(unsigned int val, char* szValue)
+{
+    sprintf(szValue, "0x%x", val);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_float(unsigned int val, char* szValue)
+{
+    float fval = *((float*) &val);
+    sprintf(szValue, "%.4f", fval);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_bool(unsigned int val, char* szValue)
+{
+    if (val)
+    {
+        kos_strcpy(szValue, "TRUE");
+    }
+    else
+    {
+        kos_strcpy(szValue, "FALSE");
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void GetString_int(unsigned int val, char* szValue)
+{
+    sprintf(szValue, "%d", val);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_intMinusOne(unsigned int val, char* szValue)
+{
+    sprintf(szValue, "%d+1", val);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_signedint(unsigned int val, unsigned int dwNumBits, char* szValue)
+{
+    int nValue = val;
+
+    if (val & (1<<(dwNumBits-1)))
+    {
+        nValue |= 0xffffffff << dwNumBits;
+    }
+
+    sprintf(szValue, "%d", nValue);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_fixed(unsigned int val, unsigned int dwNumInt, unsigned int dwNumFrac, char* szValue)
+{
+
+   (void) dwNumInt;     // unreferenced formal parameter
+
+    if (val>>dwNumFrac == 0)
+    {
+        // Integer part is 0 - just print out the fractional part
+        sprintf(szValue, "%d/%d",
+            val&((1<<dwNumFrac)-1),
+            1<<dwNumFrac);
+    }
+    else
+    {
+        // Print out as a mixed fraction
+        sprintf(szValue, "%d %d/%d",
+            val>>dwNumFrac,
+            val&((1<<dwNumFrac)-1),
+            1<<dwNumFrac);
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_Register(unsigned int dwBaseIndex, unsigned int dwValue, char* pszString)
+{
+    char szValue[64];
+    char szField[128];
+
+    // Empty the string
+    pszString[0] = '\0';
+
+    switch(dwBaseIndex)
+    {
+#define START_REGISTER(__reg)               \
+        case mm##__reg:                     \
+            {                               \
+                reg##__reg reg;             \
+                reg.u32All = dwValue;       \
+                strcat(pszString, #__reg ", (");
+
+#define GENERATE_FIELD(__name, __type)                                \
+                GetString_##__type(reg.bitfields.__name, szValue);    \
+                sprintf(szField, #__name " = %s, ", szValue);         \
+                strcat(pszString, szField);
+
+#define END_REGISTER(__reg)                           \
+                pszString[strlen(pszString)-2]='\0';  \
+                strcat(pszString, ")");               \
+            }                                         \
+            break;
+
+#include _YAMATO_GENREG_H
+
+        default:
+            break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_Type3Opcode(unsigned int opcode, char* pszValue)
+{
+switch(EXPAND_OPCODE(opcode))
+    {
+#define TYPE3SWITCH(__opcode)                  \
+        case PM4_PACKET3_##__opcode:           \
+            kos_strcpy(pszValue, #__opcode);    \
+            break;
+
+        TYPE3SWITCH(NOP)
+        TYPE3SWITCH(IB_PREFETCH_END)
+        TYPE3SWITCH(SUBBLK_PREFETCH)
+
+        TYPE3SWITCH(INSTR_PREFETCH)
+        TYPE3SWITCH(REG_RMW)
+        TYPE3SWITCH(DRAW_INDX)
+        TYPE3SWITCH(VIZ_QUERY)
+        TYPE3SWITCH(SET_STATE)
+        TYPE3SWITCH(WAIT_FOR_IDLE)
+        TYPE3SWITCH(IM_LOAD)
+        TYPE3SWITCH(IM_LOAD_IMMEDIATE)
+        TYPE3SWITCH(SET_CONSTANT)
+        TYPE3SWITCH(LOAD_CONSTANT_CONTEXT)
+        TYPE3SWITCH(LOAD_ALU_CONSTANT)
+
+        TYPE3SWITCH(DRAW_INDX_BIN)
+        TYPE3SWITCH(3D_DRAW_INDX_2_BIN)
+        TYPE3SWITCH(3D_DRAW_INDX_2)
+        TYPE3SWITCH(INDIRECT_BUFFER_PFD)
+        TYPE3SWITCH(INVALIDATE_STATE)
+        TYPE3SWITCH(WAIT_REG_MEM)
+        TYPE3SWITCH(MEM_WRITE)
+        TYPE3SWITCH(REG_TO_MEM)
+        TYPE3SWITCH(INDIRECT_BUFFER)
+
+        TYPE3SWITCH(CP_INTERRUPT)
+        TYPE3SWITCH(COND_EXEC)
+        TYPE3SWITCH(COND_WRITE)
+        TYPE3SWITCH(EVENT_WRITE)
+        TYPE3SWITCH(INSTR_MATCH)
+        TYPE3SWITCH(ME_INIT)
+        TYPE3SWITCH(CONST_PREFETCH)
+        TYPE3SWITCH(MEM_WRITE_CNTR)
+
+        TYPE3SWITCH(SET_BIN_MASK)
+        TYPE3SWITCH(SET_BIN_SELECT)
+        TYPE3SWITCH(WAIT_REG_EQ)
+        TYPE3SWITCH(WAIT_REG_GTE)
+        TYPE3SWITCH(INCR_UPDT_STATE)
+        TYPE3SWITCH(INCR_UPDT_CONST)
+        TYPE3SWITCH(INCR_UPDT_INSTR)
+        TYPE3SWITCH(EVENT_WRITE_SHD)
+        TYPE3SWITCH(EVENT_WRITE_CFL)
+        TYPE3SWITCH(EVENT_WRITE_ZPD)
+        TYPE3SWITCH(WAIT_UNTIL_READ)
+        TYPE3SWITCH(WAIT_IB_PFD_COMPLETE)
+        TYPE3SWITCH(CONTEXT_UPDATE)
+
+        default:
+            sprintf(pszValue, "Unknown: %d", opcode);
+            break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void 
+WritePM4Packet_Type0(FILE* pFile, unsigned int dwHeader, unsigned int** ppBuffer)
+{
+    pm4_type0 header = *((pm4_type0*) &dwHeader);
+    unsigned int* pBuffer = *ppBuffer;
+    unsigned int dwIndex;
+
+    WriteDWORD(pFile, dwHeader);
+    printString(pFile, "    // Type-0 packet (BASE_INDEX = 0x%x, ONE_REG_WR = %d, COUNT = %d+1)\n",
+        header.base_index, header.one_reg_wr, header.count);   
+
+    // Now go through and write the dwNumDWORDs 
+    for (dwIndex = 0; dwIndex < header.count+1; dwIndex++)
+    {
+        char szRegister[1024];
+        unsigned int dwRegIndex;
+        unsigned int dwRegValue = *(pBuffer++);
+
+        if (header.one_reg_wr)
+        {
+            dwRegIndex = header.base_index;
+        }
+        else
+        {
+            dwRegIndex = header.base_index + dwIndex;
+        }
+
+        WriteDWORD(pFile, dwRegValue);
+        // Write register string based on fields
+        GetString_Register(dwRegIndex, dwRegValue, szRegister);
+        printString(pFile, "    // %s\n", szRegister);
+
+        // Write actual unsigned int
+        
+    }
+
+    *ppBuffer = pBuffer;
+}
+
+//----------------------------------------------------------------------------
+
+void 
+WritePM4Packet_Type2(FILE* pFile, unsigned int dwHeader, unsigned int** ppBuffer)
+{
+    unsigned int* pBuffer = *ppBuffer;
+
+    WriteDWORD(pFile, dwHeader);
+    printString(pFile, "    // Type-2 packet\n");
+    
+    *ppBuffer = pBuffer;
+}
+
+//----------------------------------------------------------------------------
+
+void
+AnalyzePacketType(FILE *pFile, unsigned int dwHeader, unsigned int**ppBuffer)
+{
+    switch(dwHeader & PM4_PKT_MASK)
+    {
+    case PM4_TYPE0_PKT:
+        WritePM4Packet_Type0(pFile, dwHeader, ppBuffer);
+        break;
+
+    case PM4_TYPE1_PKT:
+        break;
+
+    case PM4_TYPE2_PKT:
+        WritePM4Packet_Type2(pFile, dwHeader, ppBuffer);
+        break;
+
+    case PM4_TYPE3_PKT:
+        WritePM4Packet_Type3(pFile, dwHeader, ppBuffer);
+        break;
+    }
+}
+
+void 
+WritePM4Packet_Type3(FILE* pFile, unsigned int dwHeader, unsigned int** ppBuffer)
+{
+    pm4_type3 header = *((pm4_type3*) &dwHeader);
+    unsigned int* pBuffer = *ppBuffer;
+    unsigned int dwIndex;
+    char szOpcode[64];
+
+    if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER) ||
+       (EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER_PFD))
+    {
+        unsigned int *pIndirectBuffer = (unsigned int *) *(pBuffer++); // ordinal 2 of IB packet is an address
+        unsigned int *pIndirectBufferEnd = pIndirectBuffer + *(pBuffer++); // ordinal 3 of IB packet is size
+        unsigned int gpuaddr = kgsl_sharedmem_convertaddr((unsigned int) pIndirectBuffer, 1);
+
+        indirectionLevel++;
+
+        WriteDWORD2(pFile, dwHeader);
+        WriteDWORD2(pFile, gpuaddr);
+        WriteDWORD2(pFile, (unsigned int) (pIndirectBufferEnd-pIndirectBuffer));
+
+        if (indirectionLevel == 1)
+        {
+            printString(pFile, "Start_IB1, base=0x%x, size=%d\n", gpuaddr, (unsigned int)(pIndirectBufferEnd - pIndirectBuffer));
+        }
+        else
+        {
+            printString(pFile, "Start_IB2, base=0x%x, size=%d\n", gpuaddr, (unsigned int)(pIndirectBufferEnd - pIndirectBuffer));
+        }
+
+        while(pIndirectBuffer < pIndirectBufferEnd)
+        {
+            unsigned int _dwHeader = *(pIndirectBuffer++);
+
+            AnalyzePacketType(pFile, _dwHeader, &pIndirectBuffer);
+        }
+
+        if (indirectionLevel == 1)
+        {
+            printString(pFile, "End_IB1\n");
+        }
+        else
+        {
+            printString(pFile, "End_IB2\n");
+        }
+
+        indirectionLevel--;
+    }
+    else
+    {
+        unsigned int registerAddr = 0xffffffff;
+        char szRegister[1024];
+
+        GetString_Type3Opcode(header.it_opcode, szOpcode);
+
+        WriteDWORD(pFile, dwHeader);
+        printString(pFile, "    // Type-3 packet (PREDICATE = %d, IT_OPCODE = %s, COUNT = %d+1)\n",
+            header.predicate, szOpcode, header.count);
+        
+        // Go through each command
+        for (dwIndex = 0; dwIndex < header.count+1; dwIndex++)
+        {
+            // Check for a register write
+            if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_SET_CONSTANT) && (((*pBuffer) >> 16) == 0x4))
+                registerAddr = (*pBuffer) & 0xffff;
+
+            // Write unsigned int
+            WriteDWORD(pFile, *pBuffer);
+
+            // Starting at Ordinal 2 is actual register values
+            if((dwIndex > 0) && (registerAddr != 0xffffffff))
+            {
+                // Write register string based on address
+                GetString_Register(registerAddr + 0x2000, *pBuffer, szRegister);
+                printString(pFile, "    // %s\n", szRegister);
+                registerAddr++;
+            }
+            else
+            {
+                // Write out newline if we aren't augmenting with register fields
+                printString(pFile, "\n");
+            }
+
+            pBuffer++;
+        }
+    }
+    *ppBuffer = pBuffer;
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpInitParams(unsigned int dwEDRAMBase, unsigned int dwEDRAMSize)
+{
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "InitParams, edrambase=0x%x, edramsize=%d\n",
+        dwEDRAMBase, dwEDRAMSize);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpSwapBuffers(unsigned int dwAddress, unsigned int dwWidth,
+    unsigned int dwHeight, unsigned int dwPitch, unsigned int dwAlignedHeight, unsigned int dwBitsPerPixel)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "SwapBuffers, address=0x%08x, width=%d, height=%d, pitch=%d, alignedheight=%d, bpp=%d\n",
+        dwAddress, dwWidth, dwHeight, dwPitch, dwAlignedHeight, dwBitsPerPixel);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpRegSpace(gsl_device_t *device)
+{
+    int           regsPerLine = 0x20;
+    unsigned int  dwOffset;
+    unsigned int  value;
+
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "Start_RegisterSpace\n");
+    
+    for (dwOffset = 0; dwOffset < device->regspace.sizebytes; dwOffset += 4)
+    {
+        if (dwOffset % regsPerLine == 0)
+        {
+           printString(pFile, "    0x%08x   ", dwOffset);
+        }
+
+        GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (dwOffset >> 2), &value);
+
+        printString(pFile, " 0x%08x", value);
+
+        if (((dwOffset + 4) % regsPerLine == 0) && ((dwOffset + 4) < device->regspace.sizebytes))
+        {
+           printString(pFile, "\n");
+        }
+    }
+
+    printString(pFile, "\nEnd_RegisterSpace\n");
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+Yamato_DumpAllocateMemory(unsigned int dwSize, unsigned int dwFlags, unsigned int dwAddress,
+    unsigned int dwActualSize)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "AllocateMemory, size=%d, flags=0x%x, address=0x%x, actualSize=%d\n",
+        dwSize, dwFlags, dwAddress, dwActualSize);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpFreeMemory(unsigned int dwAddress)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "FreeMemory, address=0x%x\n", dwAddress);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+Yamato_DumpWriteMemory(unsigned int dwAddress, unsigned int dwSize, void* pData)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+    unsigned int dwNumDWORDs;
+    unsigned int dwIndex;
+    unsigned int *pDataPtr;
+
+    printString(pFile, "StartWriteMemory, address=0x%x, size=%d\n", dwAddress, dwSize);
+
+    // Now write the data, in dwNumDWORDs
+    dwNumDWORDs = dwSize >> 2;
+
+    // If there are spillover bytes into the next dword, increment the amount dumped out here.
+    // The reader needs to take care of not overwriting the nonvalid bytes
+    if((dwSize % 4) != 0)
+        dwNumDWORDs++;
+
+    for (dwIndex = 0, pDataPtr = (unsigned int *)pData; dwIndex < dwNumDWORDs; dwIndex++, pDataPtr++)
+    {
+        WriteDWORD2(pFile, *pDataPtr);
+    }
+
+    printString(pFile, "EndWriteMemory\n");
+
+    fclose(pFile);
+}
+
+void 
+Yamato_DumpSetMemory(unsigned int dwAddress, unsigned int dwSize, unsigned int pData)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+//    unsigned int* pDataPtr;
+
+    printString(pFile, "SetMemory, address=0x%x, size=%d, value=0x%x\n",
+        dwAddress, dwSize, pData);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+void 
+Yamato_ConvertIBAddr(unsigned int dwHeader, unsigned int *pBuffer, int gpuToHost)
+{
+    unsigned int hostaddr;
+    unsigned int *ibend;
+    unsigned int *addr;
+    unsigned int *ib    = pBuffer;
+    pm4_type3    header = *((pm4_type3*) &dwHeader);
+
+    // convert ib1 base address
+    if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER) ||
+       (EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER_PFD))
+    {
+        if (gpuToHost)
+        {
+            // from gpu to host
+            *ib = kgsl_sharedmem_convertaddr(*ib, 0);
+
+            hostaddr = *ib;
+        }
+        else
+        {
+            // from host to gpu
+            hostaddr = *ib;
+            *ib = kgsl_sharedmem_convertaddr(*ib, 1);
+        }
+
+        // walk through ib1 and convert any ib2 base address
+
+        ib    = (unsigned int *) hostaddr;
+        ibend = (unsigned int *) (ib + *(++pBuffer));
+
+        while (ib < ibend)
+        {
+            dwHeader = *(ib);
+            header   = *((pm4_type3*) (&dwHeader));
+
+            switch(dwHeader & PM4_PKT_MASK)
+            {
+            case PM4_TYPE0_PKT:
+                ib += header.count + 2;
+                break;
+
+            case PM4_TYPE1_PKT:
+                break;
+
+            case PM4_TYPE2_PKT:
+                ib++;
+                break;
+
+            case PM4_TYPE3_PKT:
+                if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER) ||
+                   (EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER_PFD))
+                {
+                    addr = ib + 1;
+                    if (gpuToHost)
+                    {
+                        // from gpu to host
+                        *addr = kgsl_sharedmem_convertaddr(*addr, 0);
+                    }
+                    else
+                    {
+                        // from host to gpu
+                        *addr = kgsl_sharedmem_convertaddr(*addr, 1);
+                    }
+                }
+                ib += header.count + 2;
+                break;
+            }
+        }
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpPM4(unsigned int* pBuffer, unsigned int sizeDWords)
+{
+    unsigned int *pBufferEnd = pBuffer + sizeDWords;
+    unsigned int *tmp;
+
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "Start_PM4Buffer\n");//, count=%d\n", sizeDWords);
+
+    // So look at the first unsigned int - should be a header
+    while(pBuffer < pBufferEnd)
+    {
+        unsigned int dwHeader = *(pBuffer++);
+
+        //printString(pFile, "  Start_Packet\n");
+        switch(dwHeader & PM4_PKT_MASK)
+        {
+            case PM4_TYPE0_PKT:
+                WritePM4Packet_Type0(pFile, dwHeader, &pBuffer);
+                break;
+
+            case PM4_TYPE1_PKT:
+                break;
+
+            case PM4_TYPE2_PKT:
+                WritePM4Packet_Type2(pFile, dwHeader, &pBuffer);
+                break;
+
+            case PM4_TYPE3_PKT:
+                indirectionLevel = 0;
+                tmp = pBuffer;
+                Yamato_ConvertIBAddr(dwHeader, tmp, 1);
+                WritePM4Packet_Type3(pFile, dwHeader, &pBuffer);
+                Yamato_ConvertIBAddr(dwHeader, tmp, 0);
+                break;
+        }
+        //printString(pFile, "  End_Packet\n");
+    }
+
+    printString(pFile, "End_PM4Buffer\n");
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpRegisterWrite(unsigned int dwAddress, unsigned int value)
+{
+    FILE *pFile;
+
+    // Build a Type-0 packet that maps to this register write
+    unsigned int pBuffer[100], *pBuf = &pBuffer[1];
+
+    // Don't dump CP_RB_WPTR (switch statement may be necessary here for future additions)
+    if(dwAddress == mmCP_RB_WPTR)
+        return;
+
+    pFile = fopen(PM4_DUMPFILE, "a");
+
+    pBuffer[0] = dwAddress;
+    pBuffer[1] = value;
+
+    printString(pFile, "StartRegisterWrite\n");
+    WritePM4Packet_Type0(pFile, pBuffer[0], &pBuf);
+    printString(pFile, "EndRegisterWrite\n");
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpFbStart(gsl_device_t *device)
+{
+    FILE *pFile;
+
+    static int firstCall = 0;
+
+    // We only want to call this once
+    if(firstCall)
+        return;
+
+    pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "FbStart, value=0x%x\n", device->mmu.mpu_base);
+    printString(pFile, "FbSize, value=0x%x\n", device->mmu.mpu_range);
+
+    fclose(pFile);
+
+    firstCall = 1;
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpWindow(unsigned int addr, unsigned int width, unsigned int height)
+{
+    FILE *pFile;
+
+    pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "DumpWindow, addr=0x%x, width=0x%x, height=0x%x\n", addr, width, height);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+#ifdef _DEBUG
+
+#define ADDRESS_STACK_SIZE 256
+#define GET_PM4_TYPE3_OPCODE(x) ((*(x) >> 8) & 0xFF)
+#define IF_REGISTER_IN_RANGE(reg, base, count)         \
+    offset = (reg) - (base);                           \
+    if(offset >= 0 && offset <= (count) - 2)
+#define GET_CP_CONSTANT_DATA(x) (*((x) + offset + 2))
+
+static const char format2bpp[] =
+{
+    2,  // COLORX_4_4_4_4 
+    2,  // COLORX_1_5_5_5 
+    2,  // COLORX_5_6_5 
+    1,  // COLORX_8 
+    2,  // COLORX_8_8 
+    4,  // COLORX_8_8_8_8 
+    4,  // COLORX_S8_8_8_8 
+    2,  // COLORX_16_FLOAT 
+    4,  // COLORX_16_16_FLOAT 
+    8,  // COLORX_16_16_16_16_FLOAT 
+    4,  // COLORX_32_FLOAT 
+    8,  // COLORX_32_32_FLOAT 
+    16, // COLORX_32_32_32_32_FLOAT ,
+    1,  // COLORX_2_3_3 
+    3,  // COLORX_8_8_8
+};
+
+static unsigned int kgsl_dumpx_addr_count = 0; //unique command buffer addresses encountered
+static int kgsl_dumpx_handle_type3(unsigned int* hostaddr, int count)
+{
+    // For swap detection we need to find the below declared static values, and detect DI during EDRAM copy
+    static unsigned int width = 0, height = 0, format = 0, baseaddr = 0, iscopy = 0;
+
+    static unsigned int addr_stack[ADDRESS_STACK_SIZE];
+    static unsigned int size_stack[ADDRESS_STACK_SIZE];
+    int swap = 0; // have we encountered a swap during recursion (return value)
+
+    switch(GET_PM4_TYPE3_OPCODE(hostaddr))
+    {
+        case PM4_INDIRECT_BUFFER_PFD:
+        case PM4_INDIRECT_BUFFER:
+        {
+            // traverse indirect buffers
+            unsigned int i;
+            unsigned int ibaddr = *(hostaddr+1);
+            unsigned int ibsize = *(hostaddr+2);
+            
+            // is this address already in encountered?
+            for(i = 0; i < kgsl_dumpx_addr_count && addr_stack[i] != ibaddr; i++);
+            
+            if(kgsl_dumpx_addr_count == i)
+            {
+                // yes it was, store the address so we don't dump this buffer twice
+                addr_stack[kgsl_dumpx_addr_count] = ibaddr;
+                // just for sanity checking
+                size_stack[kgsl_dumpx_addr_count++] = ibsize; 
+                KOS_ASSERT(kgsl_dumpx_addr_count < ADDRESS_STACK_SIZE);
+
+                // recursively follow the indirect link and update swap if indirect buffer had resolve
+                swap |= kgsl_dumpx_parse_ibs(ibaddr, ibsize); 
+            }
+            else
+            {
+                KOS_ASSERT(size_stack[i] == ibsize);
+            }
+        } 
+        break;
+
+        case PM4_SET_CONSTANT:
+        if((*(hostaddr+1) >> 16) == 0x4)
+        {   
+            // parse register writes, and figure out framebuffer configuration
+
+            unsigned int regaddr = (*(hostaddr + 1) & 0xFFFF) + 0x2000; //dword address in register space
+            int offset; // used by the macros
+
+            IF_REGISTER_IN_RANGE(mmPA_SC_WINDOW_SCISSOR_BR, regaddr, count)
+            {
+                // found write to PA_SC_WINDOW_SCISSOR_BR, we use this to detect current
+                // width and height of the framebuffer (TODO: find more reliable way of achieving this)
+                unsigned int data = GET_CP_CONSTANT_DATA(hostaddr);
+                width  = data & 0xFFFF;
+                height = data >> 16;
+            }
+            
+            IF_REGISTER_IN_RANGE(mmRB_MODECONTROL, regaddr, count)
+            {
+                // found write to RB_MODECONTROL, we use this to find out if next DI is resolve
+                unsigned int data = GET_CP_CONSTANT_DATA(hostaddr);
+                iscopy = (data & RB_MODECONTROL__EDRAM_MODE_MASK) == (EDRAM_COPY << RB_MODECONTROL__EDRAM_MODE__SHIFT);
+            }
+
+            IF_REGISTER_IN_RANGE(mmRB_COPY_DEST_BASE, regaddr, count)
+            {
+                // found write to RB_COPY_DEST_BASE, we use this to find out the framebuffer base address
+                unsigned int data = GET_CP_CONSTANT_DATA(hostaddr);
+                baseaddr = (data & RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK);
+            }
+
+            IF_REGISTER_IN_RANGE(mmRB_COPY_DEST_INFO, regaddr, count)
+            {
+               // found write to RB_COPY_DEST_INFO, we use this to find out the framebuffer format
+                unsigned int data = GET_CP_CONSTANT_DATA(hostaddr);
+                format = (data & RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT;
+            }             
+        }
+        break;
+
+        case PM4_DRAW_INDX:
+        case PM4_DRAW_INDX_2:
+        {
+            // DI found
+            // check if it is resolve
+            if(iscopy && !swap)
+            {
+                // printf("resolve: %ix%i @ 0x%08x, format = 0x%08x\n", width, height, baseaddr, format);
+                KOS_ASSERT(format < 15);
+
+                // yes it was and we need to update color buffer config because this is the first bin
+                // dumpx framebuffer base address, and dimensions
+                KGSL_DEBUG_DUMPX( BB_DUMP_CBUF_AWH, (unsigned int)baseaddr, width, height, " ");
+
+                // find aligned width
+                width = (width + 31) & ~31;
+
+                //dump bytes-per-pixel and aligned width
+                KGSL_DEBUG_DUMPX( BB_DUMP_CBUF_FS, format2bpp[format], width, 0, " ");
+                swap = 1;
+            }
+            
+        }
+        break;
+
+        default:
+        break;
+    }
+    return swap;
+}
+           
+// Traverse IBs and dump them to test vector. Detect swap by inspecting register 
+// writes, keeping note of the current state, and dump framebuffer config to test vector 
+int kgsl_dumpx_parse_ibs(gpuaddr_t gpuaddr, int sizedwords)
+{
+    static unsigned int level = 0; //recursion level
+
+    int swap = 0; // have we encountered a swap during recursion (return value)
+    unsigned int *hostaddr;
+    int dwords_left = sizedwords; //dwords left in the current command buffer
+
+    level++;
+
+    KOS_ASSERT(sizeof(unsigned int *) == sizeof(unsigned int));
+    KOS_ASSERT(level <= 2);
+    hostaddr = (unsigned int *)kgsl_sharedmem_convertaddr(gpuaddr, 0);    
+
+    // dump the IB to test vector
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, gpuaddr, (unsigned int)hostaddr, sizedwords*4, "kgsl_dumpx_write_ibs"));
+
+    while(dwords_left)
+    {
+        int count = 0; //dword count including packet header
+
+        switch(*hostaddr >> 30)
+        {
+        case 0x0: // type-0
+            count = (*hostaddr >> 16)+2;
+            break;
+        case 0x1: // type-1
+            count = 2;
+            break;
+        case 0x3: // type-3
+            count = ((*hostaddr >> 16) & 0x3fff) + 2;
+            swap |= kgsl_dumpx_handle_type3(hostaddr, count);
+            break; // type-3
+        default:
+            KOS_ASSERT(!"unknown packet type");
+        }
+        
+        // jump to next packet
+        dwords_left -= count;
+        hostaddr += count;
+        KOS_ASSERT(dwords_left >= 0 && "PM4 parsing error");
+    }
+
+    level--;
+
+    // if this is the starting level of recursion, we are done. clean-up
+    if(level == 0) kgsl_dumpx_addr_count = 0;
+
+    return swap;
+}
+#endif
+
+#endif // WIN32
+
diff --git a/drivers/mxc/amd-gpu/common/gsl_device.c b/drivers/mxc/amd-gpu/common/gsl_device.c
new file mode 100644
index 000000000000..bcb557e69d6d
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_device.c
@@ -0,0 +1,663 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl.h"
+#include "gsl_hal.h"
+#ifdef _LINUX
+#include <linux/sched.h>
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+//  inline functions
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE void
+kgsl_device_getfunctable(gsl_deviceid_t device_id, gsl_functable_t *ftbl)
+{
+    switch (device_id)
+    {
+#ifdef GSL_BLD_YAMATO
+    case GSL_DEVICE_YAMATO:
+        kgsl_yamato_getfunctable(ftbl);
+        break;
+#endif // GSL_BLD_YAMATO
+#ifdef GSL_BLD_G12
+    case GSL_DEVICE_G12:
+        kgsl_g12_getfunctable(ftbl);
+        break;
+#endif // GSL_BLD_G12
+    default:
+        break;
+    }
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_device_init(gsl_device_t *device, gsl_deviceid_t device_id)
+{
+    int              status = GSL_SUCCESS;
+    gsl_devconfig_t  config;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_init(gsl_device_t *device=0x%08x, gsl_deviceid_t device_id=%D )\n", device, device_id );
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_init. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    kos_memset(device, 0, sizeof(gsl_device_t));
+
+    // if device configuration is present
+    if (kgsl_hal_getdevconfig(device_id, &config) == GSL_SUCCESS)
+    {
+        kgsl_device_getfunctable(device_id, &device->ftbl);
+
+        kos_memcpy(&device->regspace,  &config.regspace,  sizeof(gsl_memregion_t));
+#ifdef GSL_BLD_YAMATO
+        kos_memcpy(&device->gmemspace, &config.gmemspace, sizeof(gsl_memregion_t));
+#endif // GSL_BLD_YAMATO
+
+        device->refcnt        = 0;
+        device->id            = device_id;
+
+#ifndef GSL_NO_MMU
+        device->mmu.config    = config.mmu_config;
+        device->mmu.mpu_base  = config.mpu_base;
+        device->mmu.mpu_range = config.mpu_range;
+        device->mmu.va_base   = config.va_base;
+        device->mmu.va_range  = config.va_range;
+#endif
+
+        if (device->ftbl.device_init)
+        {
+            status = device->ftbl.device_init(device);
+        }
+        else
+        {
+            status = GSL_FAILURE_NOTINITIALIZED;
+        }
+
+        // allocate memory store
+        status = kgsl_sharedmem_alloc0(device->id, GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_CONPHYS, sizeof(gsl_devmemstore_t), &device->memstore);
+
+        KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+        {
+            // dumpx needs this to be in EMEM0 aperture
+            kgsl_sharedmem_free0(&device->memstore, GSL_CALLER_PROCESSID_GET());
+            status = kgsl_sharedmem_alloc0(device->id, GSL_MEMFLAGS_ALIGNPAGE, sizeof(gsl_devmemstore_t), &device->memstore);
+        });
+
+        if (status != GSL_SUCCESS)
+        {
+            kgsl_device_stop(device->id);
+            return (status);
+        }
+        kgsl_sharedmem_set0(&device->memstore, 0, 0, device->memstore.size);
+
+        // init memqueue
+        device->memqueue.head = NULL;
+        device->memqueue.tail = NULL;
+
+        // init cmdstream
+        status = kgsl_cmdstream_init(device);
+        if (status != GSL_SUCCESS)
+        {
+            kgsl_device_stop(device->id);
+            return (status);
+        }
+
+#ifndef _LINUX		
+        // Create timestamp event
+        device->timestamp_event = kos_event_create(0);
+        if( !device->timestamp_event )
+        {
+            kgsl_device_stop(device->id);
+            return (status);
+        }
+#else
+		// Create timestamp wait queue
+		init_waitqueue_head(&device->timestamp_waitq);
+#endif	
+
+        //
+        //  Read the chip ID after the device has been initialized.
+        //
+        device->chip_id       = kgsl_hal_getchipid(device->id);
+    }
+
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_init. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_close(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE_NOTINITIALIZED;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_close(gsl_device_t *device=0x%08x )\n", device );
+
+    /* make sure the device is stopped before close
+       kgsl_device_close is only called for last running caller process
+    */
+    while (device->refcnt > 0) {
+	GSL_API_MUTEX_UNLOCK();
+	kgsl_device_stop(device->id);
+	GSL_API_MUTEX_LOCK();
+    }
+
+    // close cmdstream
+    status = kgsl_cmdstream_close(device);
+    if( status != GSL_SUCCESS ) return status;
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (device->ftbl.device_close)
+        {
+            status = device->ftbl.device_close(device);
+        }
+    }
+
+    // DumpX allocates memstore from MMU aperture
+    if ((device->refcnt == 0) && device->memstore.hostptr
+	&& !(gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX))
+    {
+	kgsl_sharedmem_free0(&device->memstore, GSL_CALLER_PROCESSID_GET());
+    }
+
+#ifndef _LINUX	
+    // destroy timestamp event
+    if(device->timestamp_event)
+    {
+        kos_event_signal(device->timestamp_event);  // wake up waiting threads before destroying the structure
+        kos_event_destroy( device->timestamp_event );
+        device->timestamp_event = 0;
+    }
+#else
+    wake_up_interruptible_all(&(device->timestamp_waitq));
+#endif	
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_close. Return value %B\n", status );
+    
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_destroy(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE_NOTINITIALIZED;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_destroy(gsl_device_t *device=0x%08x )\n", device );
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (device->ftbl.device_destroy)
+        {
+            status = device->ftbl.device_destroy(device);
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_destroy. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_attachcallback(gsl_device_t *device, unsigned int pid)
+{
+    int  status = GSL_SUCCESS;
+    int  pindex;
+
+#ifndef GSL_NO_MMU
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_device_attachcallback(gsl_device_t *device=0x%08x, unsigned int pid=0x%08x)\n", device, pid );
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (kgsl_driver_getcallerprocessindex(pid, &pindex) == GSL_SUCCESS)
+        {
+            device->callerprocess[pindex] = pid;
+
+            status = kgsl_mmu_attachcallback(&device->mmu, pid);
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_attachcallback. Return value: %B\n", status );
+
+#else
+    (void)pid;
+    (void)device;
+#endif
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_detachcallback(gsl_device_t *device, unsigned int pid)
+{
+    int  status = GSL_SUCCESS;
+    int  pindex;
+
+#ifndef GSL_NO_MMU
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_device_detachcallback(gsl_device_t *device=0x%08x, unsigned int pid=0x%08x)\n", device, pid );
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (kgsl_driver_getcallerprocessindex(pid, &pindex) == GSL_SUCCESS)
+        {
+            status |= kgsl_mmu_detachcallback(&device->mmu, pid);
+
+            device->callerprocess[pindex] = 0;
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_detachcallback. Return value: %B\n", status );
+
+#else
+    (void)pid;
+    (void)device;
+#endif
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_getproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int           status  = GSL_SUCCESS;
+    gsl_device_t  *device = &gsl_driver.device[device_id-1];        // device_id is 1 based
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_getproperty(gsl_deviceid_t device_id=%D, gsl_property_type_t type=%d, void *value=0x08x, unsigned int sizebytes=%d)\n", device_id, type, value, sizebytes );
+
+    KOS_ASSERT(value);
+
+#ifndef _DEBUG
+    (void) sizebytes;       // unreferenced formal parameter
+#endif
+
+    switch (type)
+    {
+    case GSL_PROP_SHMEM:
+        {
+        gsl_shmemprop_t  *shem = (gsl_shmemprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_shmemprop_t));
+
+        shem->numapertures   = gsl_driver.shmem.numapertures;
+        shem->aperture_mask  = GSL_APERTURE_MASK;
+        shem->aperture_shift = GSL_APERTURE_SHIFT;
+
+        break;
+        }
+
+    case GSL_PROP_SHMEM_APERTURES:
+        {
+        int i;
+        gsl_apertureprop_t  *aperture = (gsl_apertureprop_t *) value;
+
+        KOS_ASSERT(sizebytes == (sizeof(gsl_apertureprop_t) * gsl_driver.shmem.numapertures));
+
+        for (i = 0; i < gsl_driver.shmem.numapertures; i++)
+        {
+            if (gsl_driver.shmem.apertures[i].memarena)
+            {
+                aperture->gpuaddr  = GSL_APERTURE_GETGPUADDR(gsl_driver.shmem, i);
+                aperture->hostaddr = GSL_APERTURE_GETHOSTADDR(gsl_driver.shmem, i);
+            }
+            else
+            {
+                aperture->gpuaddr  = 0x0;
+                aperture->hostaddr = 0x0;
+            }
+            aperture++;
+        }
+
+        break;
+        }
+
+    case GSL_PROP_DEVICE_SHADOW:
+        {
+        gsl_shadowprop_t  *shadowprop = (gsl_shadowprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_shadowprop_t));
+
+        kos_memset(shadowprop, 0, sizeof(gsl_shadowprop_t));
+
+#ifdef  GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+        if (device->memstore.hostptr)
+        {
+            shadowprop->hostaddr = (unsigned int) device->memstore.hostptr;
+            shadowprop->size     = device->memstore.size;
+            shadowprop->flags    = GSL_FLAGS_INITIALIZED;
+        }
+#endif // GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+
+        break;
+        }
+
+    default:
+        {
+        if (device->ftbl.device_getproperty)
+        {
+            status = device->ftbl.device_getproperty(device, type, value, sizebytes);
+        }
+
+        break;
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_getproperty. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_setproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int           status = GSL_SUCCESS;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_setproperty(gsl_deviceid_t device_id=%D, gsl_property_type_t type=%d, void *value=0x08x, unsigned int sizebytes=%d)\n", device_id, type, value, sizebytes );
+
+    KOS_ASSERT(value);
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (device->ftbl.device_setproperty)
+        {
+            status = device->ftbl.device_setproperty(device, type, value, sizebytes);
+        }
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_setproperty. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_start(gsl_deviceid_t device_id, gsl_flags_t flags)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_start(gsl_deviceid_t device_id=%D, gsl_flags_t flags=%d)\n", device_id, flags );
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+    
+    kgsl_device_active(device);
+    
+    if (!(device->flags & GSL_FLAGS_INITIALIZED))
+    {
+        GSL_API_MUTEX_UNLOCK();
+
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_ERROR, "ERROR: Trying to start uninitialized device.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    device->refcnt++;
+
+    if (device->flags & GSL_FLAGS_STARTED)
+    {
+        GSL_API_MUTEX_UNLOCK();
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    // start device in safe mode
+    if (flags & GSL_FLAGS_SAFEMODE)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_INFO, "Running the device in safe mode.\n" );
+        device->flags |= GSL_FLAGS_SAFEMODE;
+    }
+
+    if (device->ftbl.device_start)
+    {
+        status = device->ftbl.device_start(device, flags);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_stop(gsl_deviceid_t device_id)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_stop(gsl_deviceid_t device_id=%D)\n", device_id );
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    if (device->flags & GSL_FLAGS_STARTED)
+    {
+        KOS_ASSERT(device->refcnt);
+
+        device->refcnt--;
+
+        if (device->refcnt == 0)
+        {
+            if (device->ftbl.device_stop)
+            {
+                status = device->ftbl.device_stop(device);
+            }
+        }
+        else
+        {
+            status = GSL_SUCCESS;
+        }
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_stop. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_idle(gsl_deviceid_t device_id, unsigned int timeout)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_idle(gsl_deviceid_t device_id=%D, unsigned int timeout=%d)\n", device_id, timeout );
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    kgsl_device_active(device);
+    
+    if (device->ftbl.device_idle)
+    {
+        status = device->ftbl.device_idle(device, timeout);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_idle. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_regread(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int *value)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+
+#ifdef GSL_LOG
+    if( offsetwords != mmRBBM_STATUS && offsetwords != mmCP_RB_RPTR ) // Would otherwise flood the log
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                        "--> int kgsl_device_regread(gsl_deviceid_t device_id=%D, unsigned int offsetwords=%R, unsigned int *value=0x%08x)\n", device_id, offsetwords, value );
+#endif
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    KOS_ASSERT(value);
+    KOS_ASSERT(offsetwords < device->regspace.sizebytes);
+
+    if (device->ftbl.device_regread)
+    {
+        status = device->ftbl.device_regread(device, offsetwords, value);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+#ifdef GSL_LOG
+    if( offsetwords != mmRBBM_STATUS && offsetwords != mmCP_RB_RPTR )
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_regread. Return value %B\n", status );
+#endif
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_regwrite(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int value)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_regwrite(gsl_deviceid_t device_id=%D, unsigned int offsetwords=%R, unsigned int value=0x%08x)\n", device_id, offsetwords, value );
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    KOS_ASSERT(offsetwords < device->regspace.sizebytes);
+
+    if (device->ftbl.device_regwrite)
+    {
+        status = device->ftbl.device_regwrite(device, offsetwords, value);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_regwrite. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_waitirq(gsl_deviceid_t device_id, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_waitirq(gsl_deviceid_t device_id=%D, gsl_intrid_t intr_id=%d, unsigned int *count=0x%08x, unsigned int timout=0x%08x)\n", device_id, intr_id, count, timeout);
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    if (device->ftbl.device_waitirq)
+    {
+        status = device->ftbl.device_waitirq(device, intr_id, count, timeout);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_waitirq. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_runpending(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE_NOTINITIALIZED;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_runpending(gsl_device_t *device=0x%08x )\n", device );
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (device->ftbl.device_runpending)
+        {
+            status = device->ftbl.device_runpending(device);
+        }
+    }
+
+    // free any pending freeontimestamps
+    kgsl_cmdstream_memqueue_drain(device);
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_runpending. Return value %B\n", status );
+
+    return (status);
+}
+
diff --git a/drivers/mxc/amd-gpu/common/gsl_drawctxt.c b/drivers/mxc/amd-gpu/common/gsl_drawctxt.c
new file mode 100644
index 000000000000..afa44e618794
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_drawctxt.c
@@ -0,0 +1,1796 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#ifdef _LINUX
+#include <asm/div64.h>
+#endif
+
+#ifdef GSL_BLD_YAMATO
+
+//#define DISABLE_SHADOW_WRITES
+
+/*
+//////////////////////////////////////////////////////////////////////////////
+//
+// Memory Map for Register, Constant & Instruction Shadow, and Command Buffers (34.5KB)
+//
+// +---------------------+------------+-------------+---+---------------------+
+// | ALU Constant Shadow | Reg Shadow | C&V Buffers |Tex| Shader Instr Shadow |
+// +---------------------+------------+-------------+---+---------------------+
+//   ________________________________/               \___________________
+//  /                                                                    \
+// +--------------+-----------+------+-----------+------------------------+
+// | Restore Regs | Save Regs | Quad | Gmem Save | Gmem Restore | unused  |
+// +--------------+-----------+------+-----------+------------------------+
+//
+//       8K - ALU Constant Shadow (8K aligned)
+//       4K - H/W Register Shadow (8K aligned)
+//       9K - Command and Vertex Buffers
+//              - Indirect command buffer : Const/Reg restore
+//                      - includes Loop & Bool const shadows
+//              - Indirect command buffer : Const/Reg save
+//              - Quad vertices & texture coordinates
+//              - Indirect command buffer : Gmem save
+//              - Indirect command buffer : Gmem restore
+//              - Unused (padding to 8KB boundary)
+//      <1K - Texture Constant Shadow (768 bytes) (8K aligned)
+//      18K - Shader Instruction Shadow
+//              - 6K vertex (32 byte aligned)
+//              - 6K pixel  (32 byte aligned)
+//              - 6K shared (32 byte aligned)
+//
+// Note: Reading constants into a shadow, one at a time using REG_TO_MEM, takes
+// 3 DWORDS per DWORD transfered, plus 1 DWORD for the shadow, for a total of
+// 16 bytes per constant.  If the texture constants were transfered this way,
+// the Command & Vertex Buffers section would extend past the 16K boundary.
+// By moving the texture constant shadow area to start at 16KB boundary, we
+// only require approximately 40 bytes more memory, but are able to use the
+// LOAD_CONSTANT_CONTEXT shadowing feature for the textures, speeding up
+// context switching.
+//
+// [Using LOAD_CONSTANT_CONTEXT shadowing feature for the Loop and/or Bool
+// constants would require an additional 8KB each, for alignment.]
+//
+//////////////////////////////////////////////////////////////////////////////
+*/
+
+//////////////////////////////////////////////////////////////////////////////
+// Constants
+//////////////////////////////////////////////////////////////////////////////
+
+
+
+
+#define ALU_CONSTANTS           2048                // DWORDS
+#define NUM_REGISTERS           1024                // DWORDS
+#ifdef DISABLE_SHADOW_WRITES
+    #define CMD_BUFFER_LEN          9216            // DWORDS
+#else
+    #define CMD_BUFFER_LEN          3072            // DWORDS
+#endif
+#define TEX_CONSTANTS           (32*6)              // DWORDS
+#define BOOL_CONSTANTS          8                   // DWORDS
+#define LOOP_CONSTANTS          56                  // DWORDS
+#define SHADER_INSTRUCT_LOG2    9U                  // 2^n == SHADER_INSTRUCTIONS
+
+#if defined(PM4_IM_STORE)
+#define SHADER_INSTRUCT         (1<<SHADER_INSTRUCT_LOG2)   // 96-bit instructions
+#else
+#define SHADER_INSTRUCT         0
+#endif
+
+// LOAD_CONSTANT_CONTEXT shadow size
+#define LCC_SHADOW_SIZE         0x2000              // 8KB
+
+#define ALU_SHADOW_SIZE         LCC_SHADOW_SIZE     // 8KB
+#define REG_SHADOW_SIZE         0x1000              // 4KB
+#ifdef DISABLE_SHADOW_WRITES
+    #define CMD_BUFFER_SIZE         0x9000          // 36KB
+#else
+    #define CMD_BUFFER_SIZE         0x3000          // 12KB
+#endif
+#define TEX_SHADOW_SIZE         (TEX_CONSTANTS*4)   // 768 bytes
+#define SHADER_SHADOW_SIZE      (SHADER_INSTRUCT*12)// 6KB
+
+#define REG_OFFSET              LCC_SHADOW_SIZE
+#define CMD_OFFSET              (REG_OFFSET + REG_SHADOW_SIZE)
+#define TEX_OFFSET              (CMD_OFFSET + CMD_BUFFER_SIZE)
+#define SHADER_OFFSET           ((TEX_OFFSET + TEX_SHADOW_SIZE + 32) & ~31)
+
+#define CONTEXT_SIZE            (SHADER_OFFSET + 3 * SHADER_SHADOW_SIZE)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// temporary work structure
+//////////////////////////////////////////////////////////////////////////////
+
+typedef struct
+{
+    unsigned int    *start;         // Command & Vertex buffer start
+    unsigned int    *cmd;           // Next available dword in C&V buffer
+
+    // address of buffers, needed when creating IB1 command buffers.
+    gpuaddr_t       bool_shadow;    // Address where bool constants are shadowed
+    gpuaddr_t       loop_shadow;    // Address where loop constants are shadowed
+
+#if defined(PM4_IM_STORE)
+    gpuaddr_t       shader_shared;  // Address of shared shader instruction shadow
+    gpuaddr_t       shader_vertex;  // Address of vertex shader instruction shadow
+    gpuaddr_t       shader_pixel;   // Address of pixel shader instruction shadow
+#endif
+
+    gpuaddr_t       reg_values[2];  // Addresses in command buffer where separately handled registers are saved
+    gpuaddr_t       chicken_restore;// Address where the TP0_CHICKEN register value is written
+    gpuaddr_t       gmem_base;      // Base gpu address of GMEM
+}
+ctx_t;
+
+//////////////////////////////////////////////////////////////////////////////
+// Helper function to calculate IEEE754 single precision float values without FPU
+//////////////////////////////////////////////////////////////////////////////
+unsigned int uint2float( unsigned int uintval )
+{
+    unsigned int exp = 0;
+    unsigned int frac = 0;
+    unsigned int u = uintval;
+
+    // Handle zero separately
+    if( uintval == 0 ) return 0;
+
+    // Find log2 of u
+    if(u>=0x10000) { exp+=16; u>>=16; }
+    if(u>=0x100  ) { exp+=8;  u>>=8;  }
+    if(u>=0x10   ) { exp+=4;  u>>=4;  }
+    if(u>=0x4    ) { exp+=2;  u>>=2;  }
+    if(u>=0x2    ) { exp+=1;  u>>=1;  }
+
+    // Calculate fraction
+    frac = ( uintval & ( ~( 1 << exp ) ) ) << ( 23 - exp );
+
+    // Exp is biased by 127 and shifted 23 bits
+    exp = ( exp + 127 ) << 23;
+
+    return ( exp | frac );
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// Helper function to divide two unsigned ints and return the result as a floating point value
+//////////////////////////////////////////////////////////////////////////////
+unsigned int uintdivide(unsigned int a, unsigned int b)
+{
+#ifdef _LINUX
+    uint64_t a_fixed = a << 16;
+    uint64_t b_fixed = b << 16;
+#else
+    unsigned int a_fixed = a << 16;
+    unsigned int b_fixed = b << 16;
+#endif
+    // Assume the result is 0.fraction
+    unsigned int fraction;
+    unsigned int exp = 126;
+
+    if( b == 0 ) return 0;
+
+#ifdef _LINUX
+    a_fixed = a_fixed << 32;
+	do_div(a_fixed, b_fixed);
+    fraction = (unsigned int)a_fixed;
+#else
+    fraction = ((unsigned int)((((__int64)a_fixed) << 32) / (__int64)b_fixed));
+#endif
+
+    if( fraction == 0 ) return 0;
+
+    // Normalize
+    while( !(fraction & (1<<31)) )
+    {
+        fraction <<= 1;
+        exp--;
+    }
+    // Remove hidden bit
+    fraction <<= 1;
+
+    // Round
+    if( ( fraction & 0x1ff ) > 256 )
+    {
+        int rounded = 0;
+        int i = 9;
+
+        // Do the bit addition
+        while( !rounded )
+        {
+            if( fraction & (1<<i) )
+            {
+                // 1b + 1b = 0b, carry = 1
+                fraction &= ~(1<<i);
+                i++;
+            }
+            else
+            {
+                fraction |= (1<<i);
+                rounded = 1;
+            }
+        }
+    }
+
+    // Use 23 most significant bits for the fraction
+    fraction >>= 9;
+
+    return ( ( exp << 23 ) | fraction );
+}
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+//                  context save (gmem -> sys)
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// pre-compiled vertex shader program
+//
+// attribute vec4  P;
+// void main(void)
+// {
+//   gl_Position = P;
+// }
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#define GMEM2SYS_VTX_PGM_LEN    0x12
+
+static const unsigned int gmem2sys_vtx_pgm[GMEM2SYS_VTX_PGM_LEN] = {
+    0x00011003, 0x00001000, 0xc2000000,
+    0x00001004, 0x00001000, 0xc4000000,
+    0x00001005, 0x00002000, 0x00000000,
+    0x1cb81000, 0x00398a88, 0x00000003,
+    0x140f803e, 0x00000000, 0xe2010100,
+    0x14000000, 0x00000000, 0xe2000000
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// pre-compiled fragment shader program
+//
+// precision highp float;
+// uniform   vec4  clear_color;
+// void main(void)
+// {
+//    gl_FragColor = clear_color;
+// }
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#define GMEM2SYS_FRAG_PGM_LEN   0x0c
+
+static const unsigned int gmem2sys_frag_pgm[GMEM2SYS_FRAG_PGM_LEN] = {
+    0x00000000, 0x1002c400, 0x10000000,
+    0x00001003, 0x00002000, 0x00000000,
+    0x140f8000, 0x00000000, 0x22000000,
+    0x14000000, 0x00000000, 0xe2000000
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+//                  context restore (sys -> gmem)
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// pre-compiled vertex shader program
+//
+// attribute vec4 position;
+// attribute vec4 texcoord;
+// varying   vec4 texcoord0;
+// void main()
+// {
+//    gl_Position = position;
+//    texcoord0 = texcoord;
+// }
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#define SYS2GMEM_VTX_PGM_LEN    0x18
+
+static const unsigned int sys2gmem_vtx_pgm[SYS2GMEM_VTX_PGM_LEN] = {
+    0x00052003, 0x00001000, 0xc2000000, 0x00001005,
+    0x00001000, 0xc4000000, 0x00001006, 0x10071000,
+    0x20000000, 0x18981000, 0x0039ba88, 0x00000003,
+    0x12982000, 0x40257b08, 0x00000002, 0x140f803e,
+    0x00000000, 0xe2010100, 0x140f8000, 0x00000000,
+    0xe2020200, 0x14000000, 0x00000000, 0xe2000000
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// pre-compiled fragment shader program
+//
+// precision mediump   float;
+// uniform   sampler2D tex0;
+// varying   vec4      texcoord0;
+// void main()
+// {
+//    gl_FragColor = texture2D(tex0, texcoord0.xy);
+// }
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#define SYS2GMEM_FRAG_PGM_LEN   0x0f
+
+static const unsigned int sys2gmem_frag_pgm[SYS2GMEM_FRAG_PGM_LEN] = {
+    0x00011002, 0x00001000, 0xc4000000, 0x00001003,
+    0x10041000, 0x20000000, 0x10000001, 0x1ffff688,
+    0x00000002, 0x140f8000, 0x00000000, 0xe2000000,
+    0x14000000, 0x00000000, 0xe2000000
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// shader texture constants (sysmem -> gmem)
+//////////////////////////////////////////////////////////////////////////////
+
+#define SYS2GMEM_TEX_CONST_LEN  6
+
+static unsigned int sys2gmem_tex_const[SYS2GMEM_TEX_CONST_LEN] =
+{
+    // Texture, FormatXYZW=Unsigned, ClampXYZ=Wrap/Repeat,RFMode=ZeroClamp-1,Dim=1:2d
+    0x00000002,  // Pitch = TBD
+
+    // Format=6:8888_WZYX, EndianSwap=0:None, ReqSize=0:256bit, DimHi=0, NearestClamp=1:OGL Mode
+    0x00000806,  // Address[31:12] = TBD
+
+    // Width, Height, EndianSwap=0:None
+    0, // Width & Height = TBD
+
+    // NumFormat=0:RF, DstSelXYZW=XYZW, ExpAdj=0, MagFilt=MinFilt=0:Point, Mip=2:BaseMap
+    0 << 1 | 1 << 4 | 2 << 7 | 3 << 10 | 2 << 23,
+
+    // VolMag=VolMin=0:Point, MinMipLvl=0, MaxMipLvl=1, LodBiasH=V=0, Dim3d=0
+    0,
+
+    // BorderColor=0:ABGRBlack, ForceBC=0:diable, TriJuice=0, Aniso=0, Dim=1:2d, MipPacking=0
+    1 << 9  // Mip Address[31:12] = TBD
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// quad for copying GMEM to context shadow
+//////////////////////////////////////////////////////////////////////////////
+
+#define QUAD_LEN                12
+
+static unsigned int gmem_copy_quad[QUAD_LEN] = {
+    0x00000000, 0x00000000, 0x3f800000,
+    0x00000000, 0x00000000, 0x3f800000,
+    0x00000000, 0x00000000, 0x3f800000,
+    0x00000000, 0x00000000, 0x3f800000
+};
+
+#define TEXCOORD_LEN            8
+
+static unsigned int gmem_copy_texcoord[TEXCOORD_LEN] = {
+    0x00000000, 0x3f800000,
+    0x3f800000, 0x3f800000,
+    0x00000000, 0x00000000,
+    0x3f800000, 0x00000000
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// shader linkage info
+//////////////////////////////////////////////////////////////////////////////
+
+#define SHADER_CONST_ADDR       (11 * 6 + 3)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// gmem command buffer length
+//////////////////////////////////////////////////////////////////////////////
+
+#define PM4_REG(reg)            ((0x4 << 16) | (GSL_HAL_SUBBLOCK_OFFSET(reg)))
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+config_gmemsize(gmem_shadow_t *shadow, int gmem_size)
+{
+    int w=64, h=64; // 16KB surface, minimum
+
+    // convert from bytes to 32-bit words
+    gmem_size = (gmem_size + 3)/4;
+
+    // find the right surface size, close to a square.
+    while (w * h < gmem_size)
+        if (w < h)
+            w *= 2;
+        else
+            h *= 2;
+
+    shadow->width  = w;
+    shadow->pitch  = w;
+    shadow->height = h;
+
+    shadow->size = shadow->pitch * shadow->height * 4;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int
+gpuaddr(unsigned int *cmd, gsl_memdesc_t *memdesc)
+{
+    return memdesc->gpuaddr + ((char *)cmd - (char *)memdesc->hostptr);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+create_ib1(gsl_drawctxt_t *drawctxt, unsigned int *cmd, unsigned int *start, unsigned int *end)
+{
+    cmd[0] = PM4_HDR_INDIRECT_BUFFER_PFD;
+    cmd[1] = gpuaddr(start, &drawctxt->gpustate);
+    cmd[2] = end - start;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int *
+program_shader(unsigned int *cmds, int vtxfrag, const unsigned int *shader_pgm, int dwords)
+{
+    // load the patched vertex shader stream
+    *cmds++ = pm4_type3_packet(PM4_IM_LOAD_IMMEDIATE, 2 + dwords);
+    *cmds++ = vtxfrag;                      // 0=vertex shader, 1=fragment shader
+    *cmds++ = ( (0 << 16) | dwords );       // instruction start & size (in 32-bit words)
+
+    kos_memcpy(cmds, shader_pgm, dwords<<2);
+    cmds += dwords;
+
+    return cmds;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int *
+reg_to_mem(unsigned int *cmds, gpuaddr_t dst, gpuaddr_t src, int dwords)
+{
+    while (dwords-- > 0)
+    {
+        *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+        *cmds++ = src++;
+        *cmds++ = dst;
+        dst += 4;
+    }
+
+    return cmds;
+}
+
+
+
+#ifdef DISABLE_SHADOW_WRITES
+
+static void build_reg_to_mem_range(unsigned int start, unsigned int end, unsigned int** cmd, /*ctx_t *ctx, unsigned int* offset) //*/gsl_drawctxt_t *drawctxt)
+{
+    unsigned int i = start;
+
+    for(i=start; i<=end; i++)
+    {
+        *(*cmd)++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+        *(*cmd)++ = i | (1<<30);
+        *(*cmd)++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) + (i-0x2000)*4;
+    }
+}
+
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+// chicken restore
+//////////////////////////////////////////////////////////////////////////////
+static unsigned int*
+build_chicken_restore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int *start = ctx->cmd;
+    unsigned int *cmds = start;
+
+    *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmds++ = 0;
+
+    *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1);
+    ctx->chicken_restore = gpuaddr(cmds, &drawctxt->gpustate);
+    *cmds++ = 0x00000000;
+
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->chicken_restore, start, cmds);
+
+    return cmds;
+}
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+// context save
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// save h/w regs, alu constants, texture contants, etc. ...
+//   requires: bool_shadow_gpuaddr, loop_shadow_gpuaddr
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+build_regsave_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int *start = ctx->cmd;
+    unsigned int *cmd = start;
+
+#ifdef DISABLE_SHADOW_WRITES
+    // Write HW registers into shadow
+    build_reg_to_mem_range(mmRB_SURFACE_INFO, mmRB_DEPTH_INFO, &cmd, drawctxt);
+    build_reg_to_mem_range(mmCOHER_DEST_BASE_0, mmPA_SC_SCREEN_SCISSOR_BR, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SC_WINDOW_OFFSET, mmPA_SC_WINDOW_SCISSOR_BR, &cmd, drawctxt);
+    build_reg_to_mem_range(mmVGT_MAX_VTX_INDX, mmRB_FOG_COLOR, &cmd, drawctxt);
+    build_reg_to_mem_range(mmRB_STENCILREFMASK_BF, mmPA_CL_VPORT_ZOFFSET, &cmd, drawctxt);
+    build_reg_to_mem_range(mmSQ_PROGRAM_CNTL, mmSQ_WRAPPING_1, &cmd, drawctxt);
+    build_reg_to_mem_range(mmRB_DEPTHCONTROL, mmRB_MODECONTROL, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SU_POINT_SIZE, mmPA_SC_LINE_STIPPLE, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SC_VIZ_QUERY, mmPA_SC_VIZ_QUERY, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SC_LINE_CNTL, mmSQ_PS_CONST, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SC_AA_MASK, mmPA_SC_AA_MASK, &cmd, drawctxt);
+    build_reg_to_mem_range(mmVGT_VERTEX_REUSE_BLOCK_CNTL, mmRB_DEPTH_CLEAR, &cmd, drawctxt);
+    build_reg_to_mem_range(mmRB_SAMPLE_COUNT_CTL, mmRB_COLOR_DEST_MASK, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SU_POLY_OFFSET_FRONT_SCALE, mmPA_SU_POLY_OFFSET_BACK_OFFSET, &cmd, drawctxt);
+
+    // Copy ALU constants
+    cmd = reg_to_mem(cmd, (drawctxt->gpustate.gpuaddr) & 0xFFFFE000, mmSQ_CONSTANT_0, ALU_CONSTANTS);
+
+    // Copy Tex constants
+    cmd = reg_to_mem(cmd, (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000, mmSQ_FETCH_0, TEX_CONSTANTS);
+#else
+    // H/w registers are already shadowed; just need to disable shadowing to prevent corruption.
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000;
+    *cmd++ = 4 << 16;                       // regs, start=0
+    *cmd++ = 0x0;                           // count = 0
+
+    // ALU constants are already shadowed; just need to disable shadowing to prevent corruption.
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000;
+    *cmd++ = 0 << 16;                       // ALU, start=0
+    *cmd++ = 0x0;                           // count = 0
+
+    // Tex constants are already shadowed; just need to disable shadowing to prevent corruption.
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000;
+    *cmd++ = 1 << 16;                       // Tex, start=0
+    *cmd++ = 0x0;                           // count = 0
+#endif
+
+
+
+
+    // Need to handle some of the registers separately
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmSQ_GPR_MANAGEMENT;
+    *cmd++ = ctx->reg_values[0];
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmTP0_CHICKEN;
+    *cmd++ = ctx->reg_values[1];
+
+    // Copy Boolean constants
+    cmd = reg_to_mem(cmd, ctx->bool_shadow, mmSQ_CF_BOOLEANS, BOOL_CONSTANTS);
+
+    // Copy Loop constants
+    cmd = reg_to_mem(cmd, ctx->loop_shadow, mmSQ_CF_LOOP, LOOP_CONSTANTS);
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->reg_save, start, cmd);
+
+    ctx->cmd = cmd;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// copy colour, depth, & stencil buffers from graphics memory to system memory
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int*
+build_gmem2sys_cmds(gsl_drawctxt_t *drawctxt, ctx_t* ctx, gmem_shadow_t *shadow)
+{
+    unsigned int *cmds = shadow->gmem_save_commands;
+    unsigned int *start = cmds;
+
+    // Store TP0_CHICKEN register
+    *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmds++ = mmTP0_CHICKEN;
+    if( ctx )
+        *cmds++ = ctx->chicken_restore;
+    else
+        cmds++;
+
+    *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmds++ = 0;
+
+    // Set TP0_CHICKEN to zero
+    *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1);
+    *cmds++ = 0x00000000;
+
+    // --------------
+    // program shader
+    // --------------
+
+    // load shader vtx constants ... 5 dwords
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4);
+    *cmds++ = (0x1 << 16) | SHADER_CONST_ADDR;
+    *cmds++ = 0;
+    *cmds++ = shadow->quad_vertices.gpuaddr | 0x3;      // valid(?) vtx constant flag & addr
+    *cmds++ = 0x00000030;                   // limit = 12 dwords
+
+    // Invalidate L2 cache to make sure vertices are updated
+    *cmds++ = pm4_type0_packet(mmTC_CNTL_STATUS, 1);
+    *cmds++ = 0x1;
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4);
+    *cmds++ = PM4_REG(mmVGT_MAX_VTX_INDX);
+    *cmds++ = 0x00ffffff; //mmVGT_MAX_VTX_INDX
+    *cmds++ = 0x0;        //mmVGT_MIN_VTX_INDX
+    *cmds++ = 0x00000000; //mmVGT_INDX_OFFSET
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SC_AA_MASK);
+    *cmds++ = 0x0000ffff; //mmPA_SC_AA_MASK
+
+
+    // load the patched vertex shader stream
+    cmds = program_shader(cmds, 0, gmem2sys_vtx_pgm, GMEM2SYS_VTX_PGM_LEN);
+
+    // Load the patched fragment shader stream
+    cmds = program_shader(cmds, 1, gmem2sys_frag_pgm, GMEM2SYS_FRAG_PGM_LEN);
+
+    // SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmSQ_PROGRAM_CNTL);
+    *cmds++ = 0x10010001;
+    *cmds++ = 0x00000008;
+
+
+    // --------------
+    // resolve
+    // --------------
+
+    // PA_CL_VTE_CNTL
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_CL_VTE_CNTL);
+    *cmds++ = 0x00000b00;               // disable X/Y/Z transforms, X/Y/Z are premultiplied by W
+
+    // change colour buffer to RGBA8888, MSAA = 1, and matching pitch
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmRB_SURFACE_INFO);
+    *cmds++ = drawctxt->context_gmem_shadow.pitch; // GMEM pitch is equal to context GMEM shadow pitch
+
+    // RB_COLOR_INFO        Endian=none, Linear, Format=RGBA8888, Swap=0, Base=gmem_base
+    if( ctx )
+    {
+        KOS_ASSERT((ctx->gmem_base & 0xFFF) == 0);   // gmem base assumed 4K aligned.
+        *cmds++ = (COLORX_8_8_8_8 << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | ctx->gmem_base;
+    }
+    else
+        cmds++;
+
+    // disable Z
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_DEPTHCONTROL);
+    *cmds++ = 0;
+
+    // set mmPA_SU_SC_MODE_CNTL
+    //      Front_ptype = draw triangles
+    //      Back_ptype = draw triangles
+    //      Provoking vertex = last
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SU_SC_MODE_CNTL);
+    *cmds++ = 0x00080240;
+
+    // set the scissor to the extents of the draw surface
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_SC_SCREEN_SCISSOR_TL);
+    *cmds++ = (0 << 16) | 0;
+    *cmds++ = (drawctxt->context_gmem_shadow.height << 16) | drawctxt->context_gmem_shadow.width;
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_SC_WINDOW_SCISSOR_TL);
+    *cmds++ = (unsigned int) ((1U << 31) | (0 << 16) | 0);
+    *cmds++ = (drawctxt->context_gmem_shadow.height << 16) | drawctxt->context_gmem_shadow.width;
+
+    // load the viewport so that z scale = clear depth and z offset = 0.0f
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_CL_VPORT_ZSCALE);
+    *cmds++ = 0xbf800000; // -1.0f
+    *cmds++ = 0x0;
+
+    // load the COPY state
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 6);
+    *cmds++ = PM4_REG(mmRB_COPY_CONTROL);
+    *cmds++ = 0;                                                // RB_COPY_CONTROL
+
+    *cmds++ = (shadow->gmemshadow.gpuaddr+shadow->offset*4) & 0xfffff000;   // RB_COPY_DEST_BASE
+
+    *cmds++ = shadow->pitch >> 5;           // RB_COPY_DEST_PITCH
+    *cmds++ = 0x0003c058;                   // Endian=none, Linear, Format=RGBA8888,Swap=0,!Dither,MaskWrite:R=G=B=A=1
+
+    {
+        // Calculate the new offset based on the adjusted base
+        unsigned int addr = (shadow->gmemshadow.gpuaddr+shadow->offset*4);
+        unsigned int offset = (addr-(addr&0xfffff000))/4;
+
+        kos_assert( (offset & 0xfffff000) == 0 ); // Make sure we stay in offsetx field.
+
+        *cmds++ = offset;
+    }
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_MODECONTROL);
+    *cmds++ = 0x6;                          // EDRAM copy
+
+    // queue the draw packet
+    *cmds++ = pm4_type3_packet(PM4_DRAW_INDX, 2);
+    *cmds++ = 0;                            // viz query info.
+    *cmds++ = 0x00030088;                   // PrimType=RectList, NumIndices=3, SrcSel=AutoIndex
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, shadow->gmem_save, start, cmds);
+
+    return cmds;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// context restore
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// copy colour, depth, & stencil buffers from system memory to graphics memory
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int*
+build_sys2gmem_cmds(gsl_drawctxt_t *drawctxt, ctx_t* ctx, gmem_shadow_t *shadow)
+{
+    unsigned int *cmds = shadow->gmem_restore_commands;
+    unsigned int *start = cmds;
+
+    // Store TP0_CHICKEN register
+    *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmds++ = mmTP0_CHICKEN;
+    if( ctx )
+        *cmds++ = ctx->chicken_restore;
+    else
+        cmds++;
+
+    *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmds++ = 0;
+
+    // Set TP0_CHICKEN to zero
+    *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1);
+    *cmds++ = 0x00000000;
+
+    // ----------------
+    // shader constants
+    // ----------------
+
+    // vertex buffer constants
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 7);
+
+    *cmds++ = (0x1 << 16) | (9 * 6);
+    *cmds++ = shadow->quad_vertices.gpuaddr | 0x3;          // valid(?) vtx constant flag & addr
+    *cmds++ = 0x00000030;                       // limit = 12 dwords
+    *cmds++ = shadow->quad_texcoords.gpuaddr | 0x3;         // valid(?) vtx constant flag & addr
+    *cmds++ = 0x00000020;                       // limit = 8 dwords
+    *cmds++ = 0;
+    *cmds++ = 0;
+
+    // Invalidate L2 cache to make sure vertices and texture coordinates are updated
+    *cmds++ = pm4_type0_packet(mmTC_CNTL_STATUS, 1);
+    *cmds++ = 0x1;
+
+    // load the patched vertex shader stream
+    cmds = program_shader(cmds, 0, sys2gmem_vtx_pgm, SYS2GMEM_VTX_PGM_LEN);
+
+    // Load the patched fragment shader stream
+    cmds = program_shader(cmds, 1, sys2gmem_frag_pgm, SYS2GMEM_FRAG_PGM_LEN);
+
+    // SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmSQ_PROGRAM_CNTL);
+    *cmds++ = 0x10030002;
+    *cmds++ = 0x00000008;
+
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SC_AA_MASK);
+    *cmds++ = 0x0000ffff; //mmPA_SC_AA_MASK
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SC_VIZ_QUERY);
+    *cmds++ = 0x0;        //mmPA_SC_VIZ_QUERY
+
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_COLORCONTROL);
+    *cmds++ = 0x00000c20; // RB_COLORCONTROL
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4);
+    *cmds++ = PM4_REG(mmVGT_MAX_VTX_INDX);
+    *cmds++ = 0x00ffffff; //mmVGT_MAX_VTX_INDX
+    *cmds++ = 0x0;        //mmVGT_MIN_VTX_INDX
+    *cmds++ = 0x00000000; //mmVGT_INDX_OFFSET
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmVGT_VERTEX_REUSE_BLOCK_CNTL);
+    *cmds++ = 0x00000002; //mmVGT_VERTEX_REUSE_BLOCK_CNTL
+    *cmds++ = 0x00000002; //mmVGT_OUT_DEALLOC_CNTL
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmSQ_INTERPOLATOR_CNTL);
+    //*cmds++ = 0x0000ffff; //mmSQ_INTERPOLATOR_CNTL
+    *cmds++ = 0xffffffff; //mmSQ_INTERPOLATOR_CNTL
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SC_AA_CONFIG);
+    *cmds++ = 0x00000000; //mmPA_SC_AA_CONFIG
+
+
+    // set mmPA_SU_SC_MODE_CNTL
+    //      Front_ptype = draw triangles
+    //      Back_ptype = draw triangles
+    //      Provoking vertex = last
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SU_SC_MODE_CNTL);
+    *cmds++ = 0x00080240;
+
+    // texture constants
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, (SYS2GMEM_TEX_CONST_LEN + 1));
+    *cmds++ = (0x1 << 16) | (0 * 6);
+    kos_memcpy(cmds, sys2gmem_tex_const, SYS2GMEM_TEX_CONST_LEN<<2);
+    cmds[0] |= (shadow->pitch >> 5) << 22;
+    cmds[1] |= shadow->gmemshadow.gpuaddr;
+    cmds[2] |= (shadow->width+shadow->offset_x-1) | (shadow->height+shadow->offset_y-1) << 13;
+    cmds += SYS2GMEM_TEX_CONST_LEN;
+
+    // change colour buffer to RGBA8888, MSAA = 1, and matching pitch
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmRB_SURFACE_INFO);
+    *cmds++ = drawctxt->context_gmem_shadow.pitch; // GMEM pitch is equal to context GMEM shadow pitch
+
+
+    // RB_COLOR_INFO        Endian=none, Linear, Format=RGBA8888, Swap=0, Base=gmem_base
+    if( ctx )
+        *cmds++ = (COLORX_8_8_8_8 << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | ctx->gmem_base;
+    else
+        cmds++;
+
+    // RB_DEPTHCONTROL
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_DEPTHCONTROL);
+    *cmds++ = 0;                            // disable Z
+
+
+    // set the scissor to the extents of the draw surface
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_SC_SCREEN_SCISSOR_TL);
+    *cmds++ = (0 << 16) | 0;
+    *cmds++ = (drawctxt->context_gmem_shadow.height << 16) | drawctxt->context_gmem_shadow.width;
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_SC_WINDOW_SCISSOR_TL);
+    *cmds++ = (unsigned int) ((1U << 31) | (shadow->gmem_offset_y << 16) | shadow->gmem_offset_x);
+    *cmds++ = (drawctxt->context_gmem_shadow.height << 16) | drawctxt->context_gmem_shadow.width;
+
+    // PA_CL_VTE_CNTL
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_CL_VTE_CNTL);
+    *cmds++ = 0x00000b00;                   // disable X/Y/Z transforms, X/Y/Z are premultiplied by W
+
+    // load the viewport so that z scale = clear depth and z offset = 0.0f
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_CL_VPORT_ZSCALE);
+    *cmds++ = 0xbf800000;
+    *cmds++ = 0x0;
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_COLOR_MASK);
+    *cmds++ = 0x0000000f;                   // R = G = B = 1:enabled
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_COLOR_DEST_MASK);
+    *cmds++ = 0xffffffff;
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmSQ_WRAPPING_0);
+    *cmds++ = 0x00000000;
+    *cmds++ = 0x00000000;
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_MODECONTROL);
+    *cmds++ = 0x4;                          // draw pixels with color and depth/stencil component
+
+    // queue the draw packet
+    *cmds++ = pm4_type3_packet(PM4_DRAW_INDX, 2);
+    *cmds++ = 0;                            // viz query info.
+    *cmds++ = 0x00030088;                   // PrimType=RectList, NumIndices=3, SrcSel=AutoIndex
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, shadow->gmem_restore, start, cmds);
+
+    return cmds;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// restore h/w regs, alu constants, texture constants, etc. ...
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned *
+reg_range(unsigned int *cmd, unsigned int start, unsigned int end)
+{
+    *cmd++ = PM4_REG(start);                // h/w regs, start addr
+    *cmd++ = end - start + 1;               // count
+    return cmd;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+build_regrestore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int *start = ctx->cmd;
+    unsigned int *cmd = start;
+
+
+    //*cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    //*cmd++ = 0;
+
+    // H/W Registers
+    cmd++; // deferred pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, ???);
+#ifdef DISABLE_SHADOW_WRITES
+    *cmd++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) | 1; // Force mismatch
+#else
+    *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000;
+#endif
+
+    cmd = reg_range(cmd, mmRB_SURFACE_INFO,                 mmPA_SC_SCREEN_SCISSOR_BR);
+    cmd = reg_range(cmd, mmPA_SC_WINDOW_OFFSET,             mmPA_SC_WINDOW_SCISSOR_BR);
+    cmd = reg_range(cmd, mmVGT_MAX_VTX_INDX,                mmPA_CL_VPORT_ZOFFSET);
+    cmd = reg_range(cmd, mmSQ_PROGRAM_CNTL,                 mmSQ_WRAPPING_1);
+    cmd = reg_range(cmd, mmRB_DEPTHCONTROL,                 mmRB_MODECONTROL);
+    cmd = reg_range(cmd, mmPA_SU_POINT_SIZE,                mmPA_SC_VIZ_QUERY/*mmVGT_ENHANCE*/);
+    cmd = reg_range(cmd, mmPA_SC_LINE_CNTL,                 mmRB_COLOR_DEST_MASK);
+    cmd = reg_range(cmd, mmPA_SU_POLY_OFFSET_FRONT_SCALE,   mmPA_SU_POLY_OFFSET_BACK_OFFSET);
+
+    // Now we know how many register blocks we have, we can compute command length
+    start[0] = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, (cmd-start)-1);
+#ifdef DISABLE_SHADOW_WRITES
+    start[2] |= (0<<24) | (4 << 16);    // Disable shadowing.
+#else
+    start[2] |= (1<<24) | (4 << 16);    // Enable shadowing for the entire register block.
+#endif
+
+    // Need to handle some of the registers separately
+    *cmd++ = pm4_type0_packet(mmSQ_GPR_MANAGEMENT, 1);
+    ctx->reg_values[0] = gpuaddr(cmd, &drawctxt->gpustate);
+    *cmd++ = 0x00040400;
+
+    *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmd++ = 0;
+    *cmd++ = pm4_type0_packet(mmTP0_CHICKEN, 1);
+    ctx->reg_values[1] = gpuaddr(cmd, &drawctxt->gpustate);
+    *cmd++ = 0x00000000;
+
+    // ALU Constants
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000;
+#ifdef DISABLE_SHADOW_WRITES
+    *cmd++ = (0<<24) | (0<<16) | 0; // Disable shadowing
+#else
+    *cmd++ = (1<<24) | (0<<16) | 0;
+#endif
+    *cmd++ = ALU_CONSTANTS;
+
+
+    // Texture Constants
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000;
+#ifdef DISABLE_SHADOW_WRITES
+    *cmd++ = (0<<24) | (1<<16) | 0; // Disable shadowing
+#else
+    *cmd++ = (1<<24) | (1<<16) | 0;
+#endif
+    *cmd++ = TEX_CONSTANTS;
+
+
+    // Boolean Constants
+    *cmd++ = pm4_type3_packet(PM4_SET_CONSTANT, 1 + BOOL_CONSTANTS);
+    *cmd++ = (2<<16) | 0;
+
+    // the next BOOL_CONSTANT dwords is the shadow area for boolean constants.
+    ctx->bool_shadow = gpuaddr(cmd, &drawctxt->gpustate);
+    cmd += BOOL_CONSTANTS;
+
+
+    // Loop Constants
+    *cmd++ = pm4_type3_packet(PM4_SET_CONSTANT, 1 + LOOP_CONSTANTS);
+    *cmd++ = (3<<16) | 0;
+
+    // the next LOOP_CONSTANTS dwords is the shadow area for loop constants.
+    ctx->loop_shadow = gpuaddr(cmd, &drawctxt->gpustate);
+    cmd += LOOP_CONSTANTS;
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->reg_restore, start, cmd);
+
+    ctx->cmd = cmd;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// quad for saving/restoring gmem
+//////////////////////////////////////////////////////////////////////////////
+
+static void set_gmem_copy_quad( gmem_shadow_t* shadow )
+{
+    unsigned int tex_offset[2];
+
+    // set vertex buffer values
+
+    gmem_copy_quad[1] = uint2float( shadow->height + shadow->gmem_offset_y );
+    gmem_copy_quad[3] = uint2float( shadow->width + shadow->gmem_offset_x );
+    gmem_copy_quad[4] = uint2float( shadow->height + shadow->gmem_offset_y );
+    gmem_copy_quad[9] = uint2float( shadow->width + shadow->gmem_offset_x );
+
+    gmem_copy_quad[0] = uint2float( shadow->gmem_offset_x );
+    gmem_copy_quad[6] = uint2float( shadow->gmem_offset_x );
+    gmem_copy_quad[7] = uint2float( shadow->gmem_offset_y );
+    gmem_copy_quad[10] = uint2float( shadow->gmem_offset_y );
+
+    tex_offset[0] = uintdivide( shadow->offset_x, (shadow->offset_x+shadow->width) );
+    tex_offset[1] = uintdivide( shadow->offset_y, (shadow->offset_y+shadow->height) );
+
+    gmem_copy_texcoord[0] = gmem_copy_texcoord[4] = tex_offset[0];
+    gmem_copy_texcoord[5] = gmem_copy_texcoord[7] = tex_offset[1];
+
+    // copy quad data to vertex buffer
+    kos_memcpy(shadow->quad_vertices.hostptr, gmem_copy_quad, QUAD_LEN << 2);
+
+    // copy tex coord data to tex coord buffer
+    kos_memcpy(shadow->quad_texcoords.hostptr, gmem_copy_texcoord, TEXCOORD_LEN << 2);
+}
+
+
+static void
+build_quad_vtxbuff(gsl_drawctxt_t *drawctxt, ctx_t *ctx, gmem_shadow_t* shadow)
+{
+    unsigned int *cmd = ctx->cmd;
+
+    // quad vertex buffer location
+    shadow->quad_vertices.hostptr = cmd;
+    shadow->quad_vertices.gpuaddr = gpuaddr(cmd, &drawctxt->gpustate);
+    cmd += QUAD_LEN;
+
+    // tex coord buffer location (in GPU space)
+    shadow->quad_texcoords.hostptr = cmd;
+    shadow->quad_texcoords.gpuaddr = gpuaddr(cmd, &drawctxt->gpustate);
+
+
+    cmd += TEXCOORD_LEN;
+
+    set_gmem_copy_quad(shadow);
+
+
+    ctx->cmd = cmd;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+build_shader_save_restore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int *cmd = ctx->cmd;
+    unsigned int *save, *restore, *fixup;
+#if defined(PM4_IM_STORE)
+    unsigned int *startSizeVtx, *startSizePix, *startSizeShared;
+#endif
+    unsigned int *partition1;
+    unsigned int *shaderBases, *partition2;
+
+#if defined(PM4_IM_STORE)
+    // compute vertex, pixel and shared instruction shadow GPU addresses
+    ctx->shader_vertex = drawctxt->gpustate.gpuaddr + SHADER_OFFSET;
+    ctx->shader_pixel  = ctx->shader_vertex + SHADER_SHADOW_SIZE;
+    ctx->shader_shared = ctx->shader_pixel  + SHADER_SHADOW_SIZE;
+#endif
+
+
+    //-------------------------------------------------------------------
+    // restore shader partitioning and instructions
+    //-------------------------------------------------------------------
+
+    restore = cmd;  // start address
+
+    // Invalidate Vertex & Pixel instruction code address and sizes
+    *cmd++ = pm4_type3_packet(PM4_INVALIDATE_STATE, 1);
+    *cmd++ = 0x00000300;                        // 0x100 = Vertex, 0x200 = Pixel
+
+    // Restore previous shader vertex & pixel instruction bases.
+    *cmd++ = pm4_type3_packet(PM4_SET_SHADER_BASES, 1);
+    shaderBases = cmd++;                        // TBD #5: shader bases (from fixup)
+
+    // write the shader partition information to a scratch register
+    *cmd++ = pm4_type0_packet(mmSQ_INST_STORE_MANAGMENT, 1);
+    partition1 = cmd++;                         // TBD #4a: partition info (from save)
+
+#if defined(PM4_IM_STORE)
+    // load vertex shader instructions from the shadow.
+    *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2);
+    *cmd++ = ctx->shader_vertex + 0x0;          // 0x0 = Vertex
+    startSizeVtx = cmd++;                       // TBD #1: start/size (from save)
+
+    // load pixel shader instructions from the shadow.
+    *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2);
+    *cmd++ = ctx->shader_pixel + 0x1;           // 0x1 = Pixel
+    startSizePix = cmd++;                       // TBD #2: start/size (from save)
+
+    // load shared shader instructions from the shadow.
+    *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2);
+    *cmd++ = ctx->shader_shared + 0x2;          // 0x2 = Shared
+    startSizeShared = cmd++;                    // TBD #3: start/size (from save)
+#endif
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->shader_restore, restore, cmd);
+
+
+    //-------------------------------------------------------------------
+    // fixup SET_SHADER_BASES data
+    //
+    // since self-modifying PM4 code is being used here, a seperate
+    // command buffer is used for this fixup operation, to ensure the
+    // commands are not read by the PM4 engine before the data fields
+    // have been written.
+    //-------------------------------------------------------------------
+
+    fixup = cmd;        // start address
+
+    // write the shader partition information to a scratch register
+    *cmd++ = pm4_type0_packet(mmSCRATCH_REG2, 1);
+    partition2 = cmd++;                                 // TBD #4b: partition info (from save)
+
+    // mask off unused bits, then OR with shader instruction memory size
+    *cmd++ = pm4_type3_packet(PM4_REG_RMW, 3);
+    *cmd++ = mmSCRATCH_REG2;
+    *cmd++ = 0x0FFF0FFF;                                // AND off invalid bits.
+    *cmd++ = (unsigned int)((SHADER_INSTRUCT_LOG2-5U) << 29);               // OR in instruction memory size
+
+    // write the computed value to the SET_SHADER_BASES data field
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmSCRATCH_REG2;
+    *cmd++ = gpuaddr(shaderBases, &drawctxt->gpustate); // TBD #5: shader bases (to restore)
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->shader_fixup, fixup, cmd);
+
+
+    //-------------------------------------------------------------------
+    // save shader partitioning and instructions
+    //-------------------------------------------------------------------
+
+    save = cmd;     // start address
+
+    *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmd++ = 0;
+
+    // Fetch the SQ_INST_STORE_MANAGMENT register value,
+    // Store the value in the data fields of the SET_CONSTANT commands above.
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmSQ_INST_STORE_MANAGMENT;
+    *cmd++ = gpuaddr(partition1, &drawctxt->gpustate);      // TBD #4a: partition info (to restore)
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmSQ_INST_STORE_MANAGMENT;
+    *cmd++ = gpuaddr(partition2, &drawctxt->gpustate);      // TBD #4b: partition info (to fixup)
+
+#if defined(PM4_IM_STORE)
+    // Store the vertex shader instructions
+    *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2);
+    *cmd++ = ctx->shader_vertex + 0x0;                      // 0x0 = Vertex
+    *cmd++ = gpuaddr(startSizeVtx, &drawctxt->gpustate);    // TBD #1: start/size (to restore)
+
+    // store the pixel shader instructions
+    *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2);
+    *cmd++ = ctx->shader_pixel + 0x1;                       // 0x1 = Pixel
+    *cmd++ = gpuaddr(startSizePix, &drawctxt->gpustate);    // TBD #2: start/size (to restore)
+
+    // Store the shared shader instructions
+    *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2);
+    *cmd++ = ctx->shader_shared + 0x2;                      // 0x2 = Shared
+    *cmd++ = gpuaddr(startSizeShared, &drawctxt->gpustate); // TBD #3: start/size (to restore)
+#endif
+
+    *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmd++ = 0;
+
+
+
+    // Create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->shader_save, save, cmd);
+
+
+    ctx->cmd = cmd;
+}
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+// create buffers for saving/restoring registers and constants
+//////////////////////////////////////////////////////////////////////////////
+
+static int
+create_gpustate_shadow(gsl_device_t *device, gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    gsl_flags_t flags;
+
+    flags = (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGN8K);
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = (GSL_MEMFLAGS_EMEM | GSL_MEMFLAGS_ALIGN8K));
+
+    // allocate memory to allow HW to save sub-blocks for efficient context save/restore
+    if (kgsl_sharedmem_alloc0(device->id, flags, CONTEXT_SIZE, &drawctxt->gpustate) != GSL_SUCCESS)
+        return GSL_FAILURE;
+
+    drawctxt->flags |= CTXT_FLAGS_STATE_SHADOW;
+
+    // Blank out h/w register, constant, and command buffer shadows.
+    kgsl_sharedmem_set0(&drawctxt->gpustate, 0, 0, CONTEXT_SIZE);
+
+    // set-up command and vertex buffer pointers
+    ctx->cmd = ctx->start = (unsigned int *) ((char *)drawctxt->gpustate.hostptr + CMD_OFFSET);
+
+    // build indirect command buffers to save & restore regs/constants
+    build_regrestore_cmds(drawctxt, ctx);
+    build_regsave_cmds(drawctxt, ctx);
+
+    build_shader_save_restore_cmds(drawctxt, ctx);
+
+    return GSL_SUCCESS;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// Allocate GMEM shadow buffer
+//////////////////////////////////////////////////////////////////////////////
+static int
+allocate_gmem_shadow_buffer(gsl_device_t *device, gsl_drawctxt_t *drawctxt)
+{
+    // allocate memory for GMEM shadow
+    if (kgsl_sharedmem_alloc0(device->id, (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGN8K),
+        drawctxt->context_gmem_shadow.size, &drawctxt->context_gmem_shadow.gmemshadow) != GSL_SUCCESS)
+        return GSL_FAILURE;
+
+    // blank out gmem shadow.
+    kgsl_sharedmem_set0(&drawctxt->context_gmem_shadow.gmemshadow, 0, 0, drawctxt->context_gmem_shadow.size);
+
+    return GSL_SUCCESS;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// create GMEM save/restore specific stuff
+//////////////////////////////////////////////////////////////////////////////
+
+static int
+create_gmem_shadow(gsl_device_t *device, gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int i;
+    config_gmemsize(&drawctxt->context_gmem_shadow, device->gmemspace.sizebytes);
+    ctx->gmem_base = device->gmemspace.gpu_base;
+
+    if( drawctxt->flags & CTXT_FLAGS_GMEM_SHADOW )
+    {
+        if( allocate_gmem_shadow_buffer(device, drawctxt) != GSL_SUCCESS )
+            return GSL_FAILURE;
+    }
+    else
+    {
+        kos_memset( &drawctxt->context_gmem_shadow.gmemshadow, 0, sizeof( gsl_memdesc_t ) );
+    }
+
+    // build quad vertex buffer
+    build_quad_vtxbuff(drawctxt, ctx, &drawctxt->context_gmem_shadow);
+
+    // build TP0_CHICKEN register restore command buffer
+    ctx->cmd = build_chicken_restore_cmds(drawctxt, ctx);
+
+    // build indirect command buffers to save & restore gmem
+    drawctxt->context_gmem_shadow.gmem_save_commands = ctx->cmd;
+    ctx->cmd = build_gmem2sys_cmds(drawctxt, ctx, &drawctxt->context_gmem_shadow);
+    drawctxt->context_gmem_shadow.gmem_restore_commands = ctx->cmd;
+    ctx->cmd = build_sys2gmem_cmds(drawctxt, ctx, &drawctxt->context_gmem_shadow);
+
+    for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ )
+    {
+        // build quad vertex buffer
+        build_quad_vtxbuff(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]);
+
+        // build indirect command buffers to save & restore gmem
+        drawctxt->user_gmem_shadow[i].gmem_save_commands = ctx->cmd;
+        ctx->cmd = build_gmem2sys_cmds(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]);
+
+        drawctxt->user_gmem_shadow[i].gmem_restore_commands = ctx->cmd;
+        ctx->cmd = build_sys2gmem_cmds(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]);
+    }
+
+    return GSL_SUCCESS;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// init draw context
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_drawctxt_init(gsl_device_t *device)
+{
+    return (GSL_SUCCESS);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// close draw context
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_drawctxt_close(gsl_device_t *device)
+{
+    return (GSL_SUCCESS);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// create a new drawing context
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_drawctxt_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags)
+{
+    gsl_drawctxt_t  *drawctxt;
+    int             index;
+    ctx_t           ctx;
+
+    kgsl_device_active(device);
+    
+    if (device->drawctxt_count >= GSL_CONTEXT_MAX)
+    {
+        return (GSL_FAILURE);
+    }
+
+    // find a free context slot
+    index = 0;
+    while (index < GSL_CONTEXT_MAX)
+    {
+        if (device->drawctxt[index].flags == CTXT_FLAGS_NOT_IN_USE)
+            break;
+
+        index++;
+    }
+
+    if (index >= GSL_CONTEXT_MAX)
+    {
+        return (GSL_FAILURE);
+    }
+
+    drawctxt = &device->drawctxt[index];
+
+    kos_memset( &drawctxt->context_gmem_shadow, 0, sizeof( gmem_shadow_t ) );
+
+	drawctxt->pid   = GSL_CALLER_PROCESSID_GET();
+    drawctxt->flags = CTXT_FLAGS_IN_USE;
+    drawctxt->type  = type;
+
+    device->drawctxt_count++;
+
+    // create context shadows, when not running in safe mode
+    if (!(device->flags & GSL_FLAGS_SAFEMODE))
+    {
+        if (create_gpustate_shadow(device, drawctxt, &ctx) != GSL_SUCCESS)
+        {
+            kgsl_drawctxt_destroy(device, index);
+            return (GSL_FAILURE);
+        }
+
+        // Save the shader instruction memory on context switching
+        drawctxt->flags |= CTXT_FLAGS_SHADER_SAVE;
+
+        if(!(flags & GSL_CONTEXT_NO_GMEM_ALLOC))
+            drawctxt->flags |= CTXT_FLAGS_GMEM_SHADOW;
+
+        // Clear out user defined GMEM shadow buffer structs
+        kos_memset( drawctxt->user_gmem_shadow, 0, sizeof(gmem_shadow_t)*GSL_MAX_GMEM_SHADOW_BUFFERS );
+
+        // create gmem shadow
+        if (create_gmem_shadow(device, drawctxt, &ctx) != GSL_SUCCESS)
+        {
+            kgsl_drawctxt_destroy(device, index);
+            return (GSL_FAILURE);
+        }
+
+
+        KOS_ASSERT(ctx.cmd - ctx.start <= CMD_BUFFER_LEN);
+    }
+
+    *drawctxt_id = index;
+
+    return (GSL_SUCCESS);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// destroy a drawing context
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_drawctxt_destroy(gsl_device_t* device, unsigned int drawctxt_id)
+{
+    gsl_drawctxt_t *drawctxt;
+
+    drawctxt = &device->drawctxt[drawctxt_id];
+
+    if (drawctxt->flags != CTXT_FLAGS_NOT_IN_USE)
+    {
+        // deactivate context
+        if (device->drawctxt_active == drawctxt)
+        {
+            // no need to save GMEM or shader, the context is being destroyed.
+            drawctxt->flags &= ~(CTXT_FLAGS_GMEM_SAVE | CTXT_FLAGS_SHADER_SAVE);
+
+            kgsl_drawctxt_switch(device, GSL_CONTEXT_NONE, 0);
+        }
+
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+
+        // destroy state shadow, if allocated
+        if (drawctxt->flags & CTXT_FLAGS_STATE_SHADOW)
+            kgsl_sharedmem_free0(&drawctxt->gpustate, GSL_CALLER_PROCESSID_GET());
+
+
+        // destroy gmem shadow, if allocated
+        if (drawctxt->context_gmem_shadow.gmemshadow.size > 0)
+        {
+            kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET());
+            drawctxt->context_gmem_shadow.gmemshadow.size = 0;
+        }
+
+        drawctxt->flags = CTXT_FLAGS_NOT_IN_USE;
+		drawctxt->pid   = 0;
+
+        device->drawctxt_count--;
+        KOS_ASSERT(device->drawctxt_count >= 0);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// Binds a user specified buffer as GMEM shadow area
+//
+// gmem_rect:   defines the rectangle that is copied from GMEM. X and Y
+//              coordinates need to be multiples of 8 after conversion to 32bpp.
+//              X, Y, width, and height need to be at 32-bit boundary to avoid
+//              rounding.
+//
+// shadow_x & shadow_y: Position in GMEM shadow buffer where the contents of
+//                      gmem_rect is copied. Both must be multiples of 8 after
+//                      conversion to 32bpp. They also need to be at 32-bit
+//                      boundary to avoid rounding.
+//
+// shadow_buffer:   Description of the GMEM shadow buffer. BPP needs to be
+//                  8, 16, 32, 64, or 128. Enabled tells if the buffer is
+//                  used or not (values 0 and 1). All the other buffer
+//                  parameters are ignored when enabled=0.
+//
+// buffer_id: Two different buffers can be defined. Use buffer IDs 0 and 1.
+//
+//
+//////////////////////////////////////////////////////////////////////////////
+KGSL_API int kgsl_drawctxt_bind_gmem_shadow(gsl_deviceid_t device_id, unsigned int drawctxt_id, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id)
+{
+    gsl_device_t   *device;
+    gsl_drawctxt_t *drawctxt;
+    gmem_shadow_t  *shadow; // Shadow struct being modified
+    unsigned int    i;
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    drawctxt = &device->drawctxt[drawctxt_id];
+
+    shadow = &drawctxt->user_gmem_shadow[buffer_id];
+
+    if( !shadow_buffer->enabled )
+    {
+        // Disable shadow
+        shadow->gmemshadow.size = 0;
+    }
+    else
+    {
+        // Binding to a buffer
+        unsigned int width, height, gmem_x, gmem_y, gmem_width, gmem_height, pixel_ratio;
+
+        KOS_ASSERT(shadow_buffer->stride_bytes%4 == 0);
+
+        // Convert to 32bpp pixel units
+        if( shadow_buffer->bpp <= 32 )
+        {
+            KOS_ASSERT(32%shadow_buffer->bpp==0);
+            pixel_ratio = 32/shadow_buffer->bpp;
+            KOS_ASSERT(gmem_rect->x%pixel_ratio==0); // Needs to be at 32bit boundary
+            gmem_x = gmem_rect->x/pixel_ratio;
+            KOS_ASSERT(gmem_x%8==0); // Needs to be a multiple of 8
+            KOS_ASSERT(gmem_rect->y%pixel_ratio==0);  // Needs to be at 32bit boundary
+            gmem_y = gmem_rect->y/pixel_ratio;
+            KOS_ASSERT(gmem_y%8==0);  // Needs to be a multiple of 8
+            KOS_ASSERT(gmem_rect->width%pixel_ratio==0);  // Needs to be at 32bit boundary
+            gmem_width = gmem_rect->width/pixel_ratio;
+            KOS_ASSERT(gmem_rect->height%pixel_ratio==0);  // Needs to be at 32bit boundary
+            gmem_height = gmem_rect->height/pixel_ratio;
+            KOS_ASSERT(shadow_x%pixel_ratio==0);  // Needs to be at 32bit boundary
+            shadow_x = shadow_x/pixel_ratio;
+            KOS_ASSERT(shadow_x%8==0);  // Needs to be a multiple of 8
+            KOS_ASSERT(shadow_y%pixel_ratio==0);  // Needs to be at 32bit boundary
+            shadow_y = shadow_y/pixel_ratio;
+            KOS_ASSERT(shadow_y%8==0);  // Needs to be a multiple of 8
+        }
+        else
+        {
+            KOS_ASSERT(shadow_buffer->bpp==64 || shadow_buffer->bpp==128);
+            pixel_ratio = shadow_buffer->bpp/32;
+            gmem_x = gmem_rect->x*pixel_ratio;
+            KOS_ASSERT(gmem_x%8==0); // Needs to be a multiple of 8
+            gmem_y = gmem_rect->y*pixel_ratio;
+            KOS_ASSERT(gmem_y%8==0);  // Needs to be a multiple of 8
+            gmem_width = gmem_rect->width*pixel_ratio;
+            gmem_height = gmem_rect->height*pixel_ratio;
+            shadow_x = shadow_x*pixel_ratio;
+            KOS_ASSERT(shadow_x%8==0);  // Needs to be a multiple of 8
+            shadow_y = shadow_y*pixel_ratio;
+            KOS_ASSERT(shadow_y%8==0);  // Needs to be a multiple of 8
+        }
+
+        KOS_ASSERT( buffer_id >= 0 && buffer_id < GSL_MAX_GMEM_SHADOW_BUFFERS );
+
+        width = gmem_width < drawctxt->context_gmem_shadow.width ? gmem_width : drawctxt->context_gmem_shadow.width;
+        height = gmem_height < drawctxt->context_gmem_shadow.height ? gmem_height : drawctxt->context_gmem_shadow.height;
+
+        drawctxt->user_gmem_shadow[buffer_id].width = width;
+        drawctxt->user_gmem_shadow[buffer_id].height = height;
+        drawctxt->user_gmem_shadow[buffer_id].pitch = shadow_buffer->stride_bytes/4;
+
+        kos_memcpy( &drawctxt->user_gmem_shadow[buffer_id].gmemshadow, &shadow_buffer->data, sizeof( gsl_memdesc_t ) );
+        // Calculate offset
+        drawctxt->user_gmem_shadow[buffer_id].offset = (int)shadow_buffer->stride_bytes/4*((int)shadow_y-(int)gmem_y)+(int)shadow_x-(int)gmem_x;
+
+        drawctxt->user_gmem_shadow[buffer_id].offset_x = shadow_x;
+        drawctxt->user_gmem_shadow[buffer_id].offset_y = shadow_y;
+        drawctxt->user_gmem_shadow[buffer_id].gmem_offset_x = gmem_x;
+        drawctxt->user_gmem_shadow[buffer_id].gmem_offset_y = gmem_y;
+
+        drawctxt->user_gmem_shadow[buffer_id].size = drawctxt->user_gmem_shadow[buffer_id].gmemshadow.size;
+
+        // Modify quad vertices
+        set_gmem_copy_quad(shadow);
+
+        // Modify commands
+        build_gmem2sys_cmds(drawctxt, NULL, shadow);
+        build_sys2gmem_cmds(drawctxt, NULL, shadow);
+
+        // Release context GMEM shadow if found
+        if (drawctxt->context_gmem_shadow.gmemshadow.size > 0)
+        {
+            kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET());
+            drawctxt->context_gmem_shadow.gmemshadow.size = 0;
+        }
+    }
+
+    // Enable GMEM shadowing if we have any of the user buffers enabled
+    drawctxt->flags &= ~CTXT_FLAGS_GMEM_SHADOW;
+    for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ )
+    {
+        if( drawctxt->user_gmem_shadow[i].gmemshadow.size > 0 )
+        {
+            drawctxt->flags |= CTXT_FLAGS_GMEM_SHADOW;
+        }
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    return (GSL_SUCCESS);
+}
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+// switch drawing contexts
+//////////////////////////////////////////////////////////////////////////////
+
+void
+kgsl_drawctxt_switch(gsl_device_t *device, gsl_drawctxt_t *drawctxt, gsl_flags_t flags)
+{
+    gsl_drawctxt_t *active_ctxt = device->drawctxt_active;
+
+	if (drawctxt != GSL_CONTEXT_NONE)
+	{
+		if(0) // flags & GSL_CONTEXT_SAVE_GMEM )
+		{
+			// Set the flag in context so that the save is done when this context is switched out.
+			drawctxt->flags |= CTXT_FLAGS_GMEM_SAVE;
+		}
+		else
+		{
+			// Remove GMEM saving flag from the context
+			drawctxt->flags &= ~CTXT_FLAGS_GMEM_SAVE;
+		}
+	}
+
+    // already current?
+    if (active_ctxt == drawctxt)
+    {
+        return;
+    }
+
+    // save old context, when not running in safe mode
+    if (active_ctxt != GSL_CONTEXT_NONE && !(device->flags & GSL_FLAGS_SAFEMODE))
+    {
+        // save registers and constants.
+        kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->reg_save, 3, active_ctxt->pid);
+
+        if (active_ctxt->flags & CTXT_FLAGS_SHADER_SAVE)
+        {
+            // save shader partitioning and instructions.
+			kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->shader_save, 3, active_ctxt->pid);
+
+            // fixup shader partitioning parameter for SET_SHADER_BASES.
+			kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->shader_fixup, 3, active_ctxt->pid);
+
+            active_ctxt->flags |= CTXT_FLAGS_SHADER_RESTORE;
+        }
+
+        if (active_ctxt->flags & CTXT_FLAGS_GMEM_SHADOW && active_ctxt->flags & CTXT_FLAGS_GMEM_SAVE )
+        {
+            // save gmem.  (note: changes shader.  shader must already be saved.)
+
+            unsigned int i, numbuffers = 0;
+
+            for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ )
+            {
+                if( active_ctxt->user_gmem_shadow[i].gmemshadow.size > 0 )
+                {
+					kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->user_gmem_shadow[i].gmem_save, 3, active_ctxt->pid);
+
+                    // Restore TP0_CHICKEN
+					kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->chicken_restore, 3, active_ctxt->pid);
+                    numbuffers++;
+                }
+            }
+            if( numbuffers == 0 )
+            {
+                // No user defined buffers -> use context default
+				kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->context_gmem_shadow.gmem_save, 3, active_ctxt->pid);
+                // Restore TP0_CHICKEN
+				kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->chicken_restore, 3, active_ctxt->pid);
+            }
+
+            active_ctxt->flags |= CTXT_FLAGS_GMEM_RESTORE;
+        }
+    }
+
+    device->drawctxt_active = drawctxt;
+
+    // restore new context, when not running in safe mode
+    if (drawctxt != GSL_CONTEXT_NONE && !(device->flags & GSL_FLAGS_SAFEMODE))
+    {
+        KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, drawctxt->gpustate.gpuaddr, (unsigned int)drawctxt->gpustate.hostptr, LCC_SHADOW_SIZE + REG_SHADOW_SIZE + CMD_BUFFER_SIZE + TEX_SHADOW_SIZE , "kgsl_drawctxt_switch"));
+
+        // restore gmem.  (note: changes shader.  shader must not already be restored.)
+        if (drawctxt->flags & CTXT_FLAGS_GMEM_RESTORE)
+        {
+            unsigned int i, numbuffers = 0;
+
+            for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ )
+            {
+                if( drawctxt->user_gmem_shadow[i].gmemshadow.size > 0 )
+                {
+					kgsl_ringbuffer_issuecmds(device, 1, drawctxt->user_gmem_shadow[i].gmem_restore, 3, drawctxt->pid);
+
+                    // Restore TP0_CHICKEN
+					kgsl_ringbuffer_issuecmds(device, 0, drawctxt->chicken_restore, 3, drawctxt->pid);
+                    numbuffers++;
+                }
+            }
+            if( numbuffers == 0 )
+            {
+                // No user defined buffers -> use context default
+				kgsl_ringbuffer_issuecmds(device, 1, drawctxt->context_gmem_shadow.gmem_restore, 3, drawctxt->pid);
+                // Restore TP0_CHICKEN
+				kgsl_ringbuffer_issuecmds(device, 0, drawctxt->chicken_restore, 3, drawctxt->pid);
+            }
+
+            drawctxt->flags &= ~CTXT_FLAGS_GMEM_RESTORE;
+        }
+
+        // restore registers and constants.
+		kgsl_ringbuffer_issuecmds(device, 0, drawctxt->reg_restore, 3, drawctxt->pid);
+
+        // restore shader instructions & partitioning.
+        if (drawctxt->flags & CTXT_FLAGS_SHADER_RESTORE)
+        {
+			kgsl_ringbuffer_issuecmds(device, 0, drawctxt->shader_restore, 3, drawctxt->pid);
+        }
+    }
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// destroy all drawing contexts
+//////////////////////////////////////////////////////////////////////////////
+int
+kgsl_drawctxt_destroyall(gsl_device_t *device)
+{
+    int             i;
+    gsl_drawctxt_t  *drawctxt;
+
+    for (i = 0; i < GSL_CONTEXT_MAX; i++)
+    {
+        drawctxt = &device->drawctxt[i];
+
+        if (drawctxt->flags != CTXT_FLAGS_NOT_IN_USE)
+        {
+            // destroy state shadow, if allocated
+            if (drawctxt->flags & CTXT_FLAGS_STATE_SHADOW)
+                kgsl_sharedmem_free0(&drawctxt->gpustate, GSL_CALLER_PROCESSID_GET());
+
+            // destroy gmem shadow, if allocated
+            if (drawctxt->context_gmem_shadow.gmemshadow.size > 0)
+            {
+                kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET());
+                drawctxt->context_gmem_shadow.gmemshadow.size = 0;
+            }
+
+            drawctxt->flags = CTXT_FLAGS_NOT_IN_USE;
+
+            device->drawctxt_count--;
+            KOS_ASSERT(device->drawctxt_count >= 0);
+        }
+    }
+
+    return (GSL_SUCCESS);
+}
+
+#endif
diff --git a/drivers/mxc/amd-gpu/common/gsl_driver.c b/drivers/mxc/amd-gpu/common/gsl_driver.c
new file mode 100644
index 000000000000..fd4bcc0df96a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_driver.c
@@ -0,0 +1,330 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_PROCESSID_NONE          0x00000000
+
+#define GSL_DRVFLAGS_EXTERNAL       0x10000000
+#define GSL_DRVFLAGS_INTERNAL       0x20000000
+
+
+//////////////////////////////////////////////////////////////////////////////
+// globals
+//////////////////////////////////////////////////////////////////////////////
+#ifndef KGSL_USER_MODE
+static gsl_flags_t  gsl_driver_initialized = 0;
+gsl_driver_t        gsl_driver;
+#else
+extern gsl_flags_t  gsl_driver_initialized;
+extern gsl_driver_t gsl_driver;
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_driver_init0(gsl_flags_t flags, gsl_flags_t flags_debug)
+{
+    int  status = GSL_SUCCESS;
+
+    if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED0))
+    {
+#ifdef GSL_LOG
+        // Uncomment these to enable logging.
+        //kgsl_log_init();
+        //kgsl_log_open_stdout( KGSL_LOG_GROUP_ALL | KGSL_LOG_LEVEL_ALL | KGSL_LOG_TIMESTAMP
+        //                      | KGSL_LOG_THREAD_ID | KGSL_LOG_PROCESS_ID );
+        //kgsl_log_open_file( "c:\\kgsl_log.txt", KGSL_LOG_GROUP_ALL | KGSL_LOG_LEVEL_ALL | KGSL_LOG_TIMESTAMP
+        //                      | KGSL_LOG_THREAD_ID | KGSL_LOG_PROCESS_ID );
+#endif
+        kos_memset(&gsl_driver, 0, sizeof(gsl_driver_t));
+
+        GSL_API_MUTEX_CREATE();
+    }
+
+#ifdef _DEBUG
+    // set debug flags on every entry, and prior to hal initialization
+    gsl_driver.flags_debug |= flags_debug;
+#else
+    (void) flags_debug;     // unref formal parameter
+#endif // _DEBUG
+
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+    {
+        KGSL_DEBUG_DUMPX_OPEN("dumpx.tb", 0);
+        KGSL_DEBUG_DUMPX( BB_DUMP_ENABLE, 0, 0, 0, " ");
+    });
+
+    KGSL_DEBUG_TBDUMP_OPEN("tbdump.txt");
+
+    if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED0))
+    {
+        GSL_API_MUTEX_LOCK();
+
+        // init hal
+        status = kgsl_hal_init();
+
+        if (status == GSL_SUCCESS)
+        {
+            gsl_driver_initialized |= flags;
+            gsl_driver_initialized |= GSL_FLAGS_INITIALIZED0;
+        }
+
+        GSL_API_MUTEX_UNLOCK();
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_driver_close0(gsl_flags_t flags)
+{
+    int  status = GSL_SUCCESS;
+
+    if ((gsl_driver_initialized & GSL_FLAGS_INITIALIZED0) && (gsl_driver_initialized & flags))
+    {
+        GSL_API_MUTEX_LOCK();
+
+        // close hall
+        status = kgsl_hal_close();
+
+        GSL_API_MUTEX_UNLOCK();
+
+        GSL_API_MUTEX_FREE();
+
+#ifdef GSL_LOG
+        kgsl_log_close();
+#endif
+
+        gsl_driver_initialized &= ~flags;
+        gsl_driver_initialized &= ~GSL_FLAGS_INITIALIZED0;
+
+        KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+        {
+            KGSL_DEBUG_DUMPX_CLOSE();
+        });
+
+        KGSL_DEBUG_TBDUMP_CLOSE();
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_init()
+{
+    // only an external (platform specific device driver) component should call this
+
+    return(kgsl_driver_init0(GSL_DRVFLAGS_EXTERNAL, 0));
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_close()
+{
+    // only an external (platform specific device driver) component should call this
+
+    return(kgsl_driver_close0(GSL_DRVFLAGS_EXTERNAL));
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_entry(gsl_flags_t flags)
+{
+    int           status = GSL_FAILURE;
+    int           index, i;
+    unsigned int  pid;
+
+    if (kgsl_driver_init0(GSL_DRVFLAGS_INTERNAL, flags) != GSL_SUCCESS)
+    {
+        return (GSL_FAILURE);
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_driver_entry( gsl_flags_t flags=%d )\n", flags );
+
+    GSL_API_MUTEX_LOCK();
+
+    pid = GSL_CALLER_PROCESSID_GET();
+
+    // if caller process has not already opened access
+    status = kgsl_driver_getcallerprocessindex(pid, &index);
+    if (status != GSL_SUCCESS)
+    {
+        // then, add caller pid to process table
+        status = kgsl_driver_getcallerprocessindex(GSL_PROCESSID_NONE, &index);
+        if (status == GSL_SUCCESS)
+        {
+            gsl_driver.callerprocess[index] = pid;
+            gsl_driver.refcnt++;
+        }
+    }
+
+    if (status == GSL_SUCCESS)
+    {
+        if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED))
+        {
+            // init memory apertures
+            status = kgsl_sharedmem_init(&gsl_driver.shmem);
+            if (status == GSL_SUCCESS)
+            {
+                // init devices
+                for (i = 0; i < GSL_DEVICE_MAX; i++)
+                {
+                    status = kgsl_device_init(&gsl_driver.device[i], (gsl_deviceid_t)(i + 1));
+                    if (status != GSL_SUCCESS)
+                    {
+                        break;
+                    }
+                }
+            }
+
+            if (status == GSL_SUCCESS)
+            {
+                gsl_driver_initialized |= GSL_FLAGS_INITIALIZED;
+            }
+        }
+
+        // walk through process attach callbacks
+        if (status == GSL_SUCCESS)
+        {
+            for (i = 0; i < GSL_DEVICE_MAX; i++)
+            {
+                status = kgsl_device_attachcallback(&gsl_driver.device[i], pid);
+                if (status != GSL_SUCCESS)
+                {
+                    break;
+                }
+            }
+        }
+
+        // if something went wrong
+        if (status != GSL_SUCCESS)
+        {
+            // then, remove caller pid from process table
+            if (kgsl_driver_getcallerprocessindex(pid, &index) == GSL_SUCCESS)
+            {
+                gsl_driver.callerprocess[index] = GSL_PROCESSID_NONE;
+                gsl_driver.refcnt--;
+            }
+        }
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_driver_entry. Return value: %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_driver_exit0(unsigned int pid)
+{
+    int  status = GSL_SUCCESS;
+    int  index, i;
+
+    GSL_API_MUTEX_LOCK();
+
+    if (gsl_driver_initialized & GSL_FLAGS_INITIALIZED)
+    {
+        if (kgsl_driver_getcallerprocessindex(pid, &index) == GSL_SUCCESS)
+        {
+            // walk through process detach callbacks
+            for (i = 0; i < GSL_DEVICE_MAX; i++)
+            {
+                // Empty the freememqueue of this device
+                kgsl_cmdstream_memqueue_drain(&gsl_driver.device[i]);
+
+                // Detach callback
+                status = kgsl_device_detachcallback(&gsl_driver.device[i], pid);
+                if (status != GSL_SUCCESS)
+                {
+                    break;
+                }
+            }
+
+            // last running caller process
+            if (gsl_driver.refcnt - 1 == 0)
+            {
+                // close devices
+                for (i = 0; i < GSL_DEVICE_MAX; i++)
+                {
+                    kgsl_device_close(&gsl_driver.device[i]);
+                }
+
+                // shutdown memory apertures
+                kgsl_sharedmem_close(&gsl_driver.shmem);
+
+                gsl_driver_initialized &= ~GSL_FLAGS_INITIALIZED;
+            }
+
+            // remove caller pid from process table
+            gsl_driver.callerprocess[index] = GSL_PROCESSID_NONE;
+            gsl_driver.refcnt--;
+        }
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_driver_close0(GSL_DRVFLAGS_INTERNAL);
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_exit(void)
+{
+    int status;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_driver_exit()\n" );
+
+    status = kgsl_driver_exit0(GSL_CALLER_PROCESSID_GET());
+
+    kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_driver_exit(). Return value: %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_destroy(unsigned int pid)
+{
+    return (kgsl_driver_exit0(pid));
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_g12.c b/drivers/mxc/amd-gpu/common/gsl_g12.c
new file mode 100644
index 000000000000..513f6728a842
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_g12.c
@@ -0,0 +1,987 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#include "kos_libapi.h"
+#include "gsl_cmdstream.h"
+#ifdef _LINUX
+#include <linux/sched.h>
+#endif
+
+#ifdef GSL_BLD_G12
+#define GSL_TIMESTAMP_EPSILON   20000
+#define GSL_IRQ_TIMEOUT         200
+
+
+//----------------------------------------------------------------------------
+
+#define GSL_HAL_NUMCMDBUFFERS           5
+#define GSL_HAL_CMDBUFFERSIZE           (1024 + 13) * sizeof(unsigned int)
+
+#define     ALIGN_IN_BYTES( dim, alignment ) ( ( (dim) + (alignment-1) ) & ~(alignment-1) )
+
+
+#ifdef _Z180
+#define     NUMTEXUNITS                         4
+#define     TEXUNITREGCOUNT                     25
+#define     VG_REGCOUNT                         0x39
+#define     GSL_HAL_EDGE0BUFSIZE                0x3E8+64
+#define     GSL_HAL_EDGE1BUFSIZE                0x8000+64
+#define     GSL_HAL_EDGE2BUFSIZE                0x80020+64
+#define     GSL_HAL_EDGE0REG                    ADDR_VGV1_CBUF
+#define     GSL_HAL_EDGE1REG                    ADDR_VGV1_BBUF
+#define     GSL_HAL_EDGE2REG                    ADDR_VGV1_EBUF
+#else
+#define     NUMTEXUNITS                          2
+#define     TEXUNITREGCOUNT                      24
+#define     VG_REGCOUNT                          0x3A
+#define     L1TILESIZE                           64
+#define     GSL_HAL_EDGE0BUFSIZE                 L1TILESIZE*L1TILESIZE*4+64
+#define     GSL_HAL_EDGE1BUFSIZE                 L1TILESIZE*L1TILESIZE*16+64
+#define     GSL_HAL_EDGE0REG                     ADDR_VGV1_CBASE1
+#define     GSL_HAL_EDGE1REG                     ADDR_VGV1_UBASE2
+#endif
+
+#define     PACKETSIZE_BEGIN        3
+#define     PACKETSIZE_G2DCOLOR     2
+#define     PACKETSIZE_TEXUNIT      (TEXUNITREGCOUNT*2)
+#define     PACKETSIZE_REG          (VG_REGCOUNT*2)
+#define     PACKETSIZE_STATE        (PACKETSIZE_TEXUNIT*NUMTEXUNITS + PACKETSIZE_REG + PACKETSIZE_BEGIN + PACKETSIZE_G2DCOLOR)
+#define     PACKETSIZE_STATESTREAM   ALIGN_IN_BYTES((PACKETSIZE_STATE*sizeof(unsigned int)), 32) / sizeof(unsigned int) 
+
+//----------------------------------------------------------------------------
+
+typedef struct
+{
+    unsigned int id;
+   // unsigned int regs[];
+}gsl_hal_z1xxdrawctx_t;
+
+typedef struct
+{
+  unsigned int      offs;
+  unsigned int      curr;
+  unsigned int      prevctx;
+
+  gsl_memdesc_t     e0;
+  gsl_memdesc_t     e1;
+  gsl_memdesc_t     e2;
+  unsigned int*     cmdbuf[GSL_HAL_NUMCMDBUFFERS];
+  gsl_memdesc_t     cmdbufdesc[GSL_HAL_NUMCMDBUFFERS];
+  gsl_timestamp_t   timestamp[GSL_HAL_NUMCMDBUFFERS];
+
+  unsigned int      numcontext;
+}gsl_z1xx_t;
+
+static gsl_z1xx_t   g_z1xx      = {0}; 
+
+//----------------------------------------------------------------------------
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+static int kgsl_g12_addtimestamp(gsl_device_t* device, gsl_timestamp_t *timestamp);
+static int kgsl_g12_issueibcmds(gsl_device_t* device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags);
+static int kgsl_g12_context_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags);
+static int kgsl_g12_context_destroy(gsl_device_t* device, unsigned int drawctxt_id);
+static unsigned int drawctx_id  = 0;
+static int kgsl_g12_idle(gsl_device_t *device, unsigned int timeout);
+#ifndef _LINUX
+static void irq_thread(void);
+#endif
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_g12_intrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_device_t  *device = (gsl_device_t *) cookie;
+
+    switch(id)
+    {
+        // non-error condition interrupt
+        case GSL_INTR_G12_G2D:
+#ifdef _LINUX
+			queue_work(device->irq_workq, &(device->irq_work));
+			break;
+#endif		
+#ifndef _Z180
+        case GSL_INTR_G12_FBC:
+#endif //_Z180
+            // signal intr completion event
+            kos_event_signal(device->intr.evnt[id]);
+            break;
+
+        // error condition interrupt
+        case GSL_INTR_G12_FIFO:
+            device->ftbl.device_destroy(device);
+            break;
+
+        case GSL_INTR_G12_MH:
+            // don't do anything. this is handled by the MMU manager
+            break;
+
+        default:
+            break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_isr(gsl_device_t *device)
+{
+    unsigned int           status;
+#ifdef _DEBUG
+    REG_MH_MMU_PAGE_FAULT  page_fault = {0};
+    REG_MH_AXI_ERROR       axi_error  = {0};
+#endif // DEBUG
+
+    // determine if G12 is interrupting
+    device->ftbl.device_regread(device, (ADDR_VGC_IRQSTATUS >> 2), &status);
+
+    if (status)
+    {
+        // if G12 MH is interrupting, clear MH block interrupt first, then master G12 MH interrupt
+        if (status & (1 << VGC_IRQSTATUS_MH_FSHIFT))
+        {
+#ifdef _DEBUG
+            // obtain mh error information
+            device->ftbl.device_regread(device, ADDR_MH_MMU_PAGE_FAULT, (unsigned int *)&page_fault);
+            device->ftbl.device_regread(device, ADDR_MH_AXI_ERROR, (unsigned int *)&axi_error);
+#endif // DEBUG
+
+            kgsl_intr_decode(device, GSL_INTR_BLOCK_G12_MH);
+        }
+
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_G12);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_tlbinvalidate(gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid)
+{
+#ifndef GSL_NO_MMU
+    REG_MH_MMU_INVALIDATE  mh_mmu_invalidate = {0};
+
+    // unreferenced formal parameter
+	(void) pid;
+
+    mh_mmu_invalidate.INVALIDATE_ALL = 1;
+    mh_mmu_invalidate.INVALIDATE_TC  = 1;
+
+    device->ftbl.device_regwrite(device, reg_invalidate, *(unsigned int *) &mh_mmu_invalidate);
+#else
+    (void)device;
+    (void)reg_invalidate;
+#endif
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_setpagetable(gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid)
+{
+	// unreferenced formal parameter
+	(void) pid;
+#ifndef GSL_NO_MMU
+    device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+	device->ftbl.device_regwrite(device, reg_ptbase, ptbase);
+#else
+    (void)device;
+    (void)reg_ptbase;
+    (void)reg_varange;
+#endif
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _LINUX
+static void kgsl_g12_updatetimestamp(gsl_device_t *device)
+{
+	unsigned int count = 0;
+	device->ftbl.device_regread(device, (ADDR_VGC_IRQ_ACTIVE_CNT >> 2), &count);
+	count >>= 8;
+	count &= 255;
+	device->timestamp += count;	
+	kgsl_sharedmem_write0(&device->memstore, GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), &device->timestamp, 4, 0);
+}
+
+//----------------------------------------------------------------------------
+
+static void kgsl_g12_irqtask(struct work_struct *work)
+{
+	gsl_device_t *device = &gsl_driver.device[GSL_DEVICE_G12-1];
+	kgsl_g12_updatetimestamp(device);
+	wake_up_interruptible_all(&device->timestamp_waitq);
+}
+#endif
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_init(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE; 
+
+    device->flags |= GSL_FLAGS_INITIALIZED;
+
+    kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_ON, 100);
+
+    // setup MH arbiter - MH offsets are considered to be dword based, therefore no down shift
+    device->ftbl.device_regwrite(device, ADDR_MH_ARBITER_CONFIG, *(unsigned int *) &gsl_cfg_g12_mharb);
+
+    // init interrupt
+    status = kgsl_intr_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    // enable irq
+    device->ftbl.device_regwrite(device, (ADDR_VGC_IRQENABLE >> 2), 0x3);
+
+#ifndef GSL_NO_MMU
+    // enable master interrupt for G12 MH
+    kgsl_intr_attach(&device->intr, GSL_INTR_G12_MH, kgsl_g12_intrcallback, (void *) device);
+    kgsl_intr_enable(&device->intr, GSL_INTR_G12_MH);
+
+    // init mmu
+    status = kgsl_mmu_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+#endif
+
+#ifdef IRQTHREAD_POLL
+    // Create event to trigger IRQ polling thread
+    device->irqthread_event = kos_event_create(0);
+#endif
+
+    // enable interrupts
+    kgsl_intr_attach(&device->intr, GSL_INTR_G12_G2D,  kgsl_g12_intrcallback, (void *) device);
+    kgsl_intr_attach(&device->intr, GSL_INTR_G12_FIFO, kgsl_g12_intrcallback, (void *) device);
+    kgsl_intr_enable(&device->intr, GSL_INTR_G12_G2D);
+    kgsl_intr_enable(&device->intr, GSL_INTR_G12_FIFO);
+
+#ifndef _Z180
+    kgsl_intr_attach(&device->intr, GSL_INTR_G12_FBC,  kgsl_g12_intrcallback, (void *) device);
+  //kgsl_intr_enable(&device->intr, GSL_INTR_G12_FBC);
+#endif //_Z180
+
+    // create thread for IRQ handling
+#if defined(__SYMBIAN32__)
+    kos_thread_create( (oshandle_t)irq_thread, &(device->irq_thread) );
+#elif defined(_LINUX)
+	device->irq_workq = create_singlethread_workqueue("z1xx_workq");
+	INIT_WORK(&device->irq_work, kgsl_g12_irqtask);
+#else
+    #pragma warning(disable:4152)
+    device->irq_thread_handle = kos_thread_create( (oshandle_t)irq_thread, &(device->irq_thread) );
+#endif
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_close(gsl_device_t *device)
+{
+    int status = GSL_FAILURE; 
+
+    if (device->refcnt == 0)
+    {
+        // wait pending interrupts before shutting down G12 intr thread to
+        // empty irq counters. Otherwise there's a possibility to have them in
+        // registers next time systems starts up and this results in a hang.
+        status = device->ftbl.device_idle(device, 1000);
+        KOS_ASSERT(status == GSL_SUCCESS);
+
+#ifndef _LINUX
+        kos_thread_destroy(device->irq_thread_handle);
+#else
+		destroy_workqueue(device->irq_workq);
+#endif
+
+        // shutdown command window
+        kgsl_cmdwindow_close(device);
+
+#ifndef GSL_NO_MMU
+        // shutdown mmu
+        kgsl_mmu_close(device);
+#endif
+        // disable interrupts
+        kgsl_intr_detach(&device->intr, GSL_INTR_G12_MH);
+        kgsl_intr_detach(&device->intr, GSL_INTR_G12_G2D);
+        kgsl_intr_detach(&device->intr, GSL_INTR_G12_FIFO);
+#ifndef _Z180
+        kgsl_intr_detach(&device->intr, GSL_INTR_G12_FBC);
+#endif //_Z180
+
+        // shutdown interrupt
+        kgsl_intr_close(device);
+
+        kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_OFF, 0);
+
+        device->ftbl.device_idle(device, GSL_TIMEOUT_NONE);
+        device->flags &= ~GSL_FLAGS_INITIALIZED;
+
+#if defined(__SYMBIAN32__)
+        while(device->irq_thread)
+        {
+            kos_sleep(20);
+        }
+#endif
+        drawctx_id = 0;
+
+        KOS_ASSERT(g_z1xx.numcontext == 0);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_destroy(gsl_device_t *device)
+{
+    int           i;
+    unsigned int  pid;
+
+#ifdef _DEBUG
+    // for now, signal catastrophic failure in a brute force way
+    KOS_ASSERT(0);
+#endif // _DEBUG
+
+    //todo: hard reset core?
+
+    for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++)
+    {
+        pid = device->callerprocess[i];
+        if (pid)
+        {
+            device->ftbl.device_stop(device);
+            kgsl_driver_destroy(pid);
+
+            // todo: terminate client process?
+        }
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_start(gsl_device_t *device, gsl_flags_t flags)
+{
+    int  status = GSL_SUCCESS;
+
+    (void) flags;       // unreferenced formal parameter
+
+    kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_ON, 100);
+
+    // init command window
+    status = kgsl_cmdwindow_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    KOS_ASSERT(g_z1xx.numcontext == 0);
+
+    device->flags |= GSL_FLAGS_STARTED;
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_stop(gsl_device_t *device)
+{
+    int status;
+
+    KOS_ASSERT(device->refcnt == 0);
+
+    /* wait for device to idle before setting it's clock off */
+    status = device->ftbl.device_idle(device, 1000);
+    KOS_ASSERT(status == GSL_SUCCESS);
+
+    status = kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_OFF, 0);
+    device->flags &= ~GSL_FLAGS_STARTED;
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_getproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int  status = GSL_FAILURE;
+    // unreferenced formal parameter
+    (void) sizebytes;
+
+    if (type == GSL_PROP_DEVICE_INFO)
+    {
+        gsl_devinfo_t  *devinfo = (gsl_devinfo_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_devinfo_t));
+
+        devinfo->device_id   = device->id;
+        devinfo->chip_id     = (gsl_chipid_t)device->chip_id;
+#ifndef GSL_NO_MMU
+        devinfo->mmu_enabled = kgsl_mmu_isenabled(&device->mmu);
+#endif
+
+        status = GSL_SUCCESS;
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_setproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int  status = GSL_FAILURE;
+
+    // unreferenced formal parameters
+    (void) device;          
+
+    if (type == GSL_PROP_DEVICE_POWER)
+    {
+        gsl_powerprop_t  *power = (gsl_powerprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_powerprop_t));
+
+        if (!(device->flags & GSL_FLAGS_SAFEMODE))
+        {
+            kgsl_hal_setpowerstate(device->id, power->flags, power->value);
+        }
+
+        status = GSL_SUCCESS;
+    }
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int             
+kgsl_g12_idle(gsl_device_t *device, unsigned int timeout)
+{
+	if ( device->flags & GSL_FLAGS_STARTED )
+	{
+		for ( ; ; )
+		{
+			gsl_timestamp_t retired = kgsl_cmdstream_readtimestamp0( device->id, GSL_TIMESTAMP_RETIRED );
+			gsl_timestamp_t ts_diff = retired - device->current_timestamp;
+			if ( ts_diff >= 0 || ts_diff < -GSL_TIMESTAMP_EPSILON )
+				break;
+			kos_sleep(10);
+		}
+	}
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int    
+kgsl_g12_regread(gsl_device_t *device, unsigned int offsetwords, unsigned int *value)
+{
+    // G12 MH register values can only be retrieved via dedicated read registers
+    if ((offsetwords >= ADDR_MH_ARBITER_CONFIG && offsetwords <= ADDR_MH_AXI_HALT_CONTROL) ||
+        (offsetwords >= ADDR_MH_MMU_CONFIG     && offsetwords <= ADDR_MH_MMU_MPU_END))
+    {
+#ifdef _Z180
+        device->ftbl.device_regwrite(device, (ADDR_VGC_MH_READ_ADDR >> 2), offsetwords);
+        GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (ADDR_VGC_MH_READ_ADDR >> 2), value);
+#else
+        device->ftbl.device_regwrite(device, (ADDR_MMU_READ_ADDR >> 2), offsetwords);
+        GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (ADDR_MMU_READ_DATA >> 2), value);
+#endif
+    }
+    else
+    {
+        GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_regwrite(gsl_device_t *device, unsigned int offsetwords, unsigned int value)
+{
+    // G12 MH registers can only be written via the command window
+    if ((offsetwords >= ADDR_MH_ARBITER_CONFIG && offsetwords <= ADDR_MH_AXI_HALT_CONTROL) ||
+        (offsetwords >= ADDR_MH_MMU_CONFIG     && offsetwords <= ADDR_MH_MMU_MPU_END))
+    {
+        kgsl_cmdwindow_write0(device->id, GSL_CMDWINDOW_MMU, offsetwords, value);
+    }
+    else
+    {
+        GSL_HAL_REG_WRITE(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value);
+    }
+
+    // idle device when running in safe mode
+    if (device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_waitirq(gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout)
+{
+    int  status = GSL_FAILURE_NOTSUPPORTED;
+#ifdef VG_HDK
+    (void)timeout;
+#endif
+
+#ifndef _Z180
+    if (intr_id == GSL_INTR_G12_G2D || intr_id == GSL_INTR_G12_FBC)
+#else
+        if (intr_id == GSL_INTR_G12_G2D)
+#endif //_Z180
+        {
+#ifndef VG_HDK
+            if (kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS)
+#endif
+            {
+                // wait until intr completion event is received and check that 
+                // the interrupt is still enabled. If event is received, but
+                // interrupt is not enabled any more, the driver is shutting 
+                // down and event structure is not valid anymore.
+#ifndef VG_HDK
+                if (kos_event_wait(device->intr.evnt[intr_id], timeout) == OS_SUCCESS && kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS)
+#endif
+                {
+                    unsigned int cntrs;
+                    int          i;
+                    kgsl_device_active(device);
+#ifndef VG_HDK
+                    kos_event_reset(device->intr.evnt[intr_id]);
+                    device->ftbl.device_regread(device, (ADDR_VGC_IRQ_ACTIVE_CNT >> 2), &cntrs);
+#else
+                    device->ftbl.device_regread(device, (0x38 >> 2), &cntrs);
+#endif
+
+                    for (i = 0; i < GSL_G12_INTR_COUNT; i++) 
+                    {
+                        int intrcnt = cntrs >> ((8 * i)) & 255;
+
+                        // maximum allowed counter value is 254. if set to 255 then something has gone wrong
+                        if (intrcnt && (intrcnt < 0xFF))
+                        {
+                            device->intrcnt[i] += intrcnt;
+                        }
+                    }
+
+                    *count = device->intrcnt[intr_id - GSL_INTR_G12_MH];
+                    device->intrcnt[intr_id - GSL_INTR_G12_MH] = 0;
+                    status = GSL_SUCCESS;
+                }
+#ifndef VG_HDK
+                else
+                {
+                    status = GSL_FAILURE_TIMEOUT;
+                }
+#endif
+            }
+        }
+    else if(intr_id == GSL_INTR_FOOBAR)
+    {
+        if (kgsl_intr_isenabled(&device->intr, GSL_INTR_G12_G2D) == GSL_SUCCESS)
+        {
+            kos_event_signal(device->intr.evnt[GSL_INTR_G12_G2D]);
+        }
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_waittimestamp(gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout)
+{
+#ifndef _LINUX
+	return kos_event_wait( device->timestamp_event, timeout );
+#else
+	int status = wait_event_interruptible_timeout(device->timestamp_waitq,
+	                                              kgsl_cmdstream_check_timestamp(device->id, timestamp),
+												  msecs_to_jiffies(timeout));
+	if (status > 0)
+		return GSL_SUCCESS;
+	else
+		return GSL_FAILURE;
+#endif
+}
+
+int
+kgsl_g12_getfunctable(gsl_functable_t *ftbl)
+{
+    ftbl->device_init           = kgsl_g12_init;
+    ftbl->device_close          = kgsl_g12_close;
+    ftbl->device_destroy        = kgsl_g12_destroy;
+    ftbl->device_start          = kgsl_g12_start;
+    ftbl->device_stop           = kgsl_g12_stop;
+    ftbl->device_getproperty    = kgsl_g12_getproperty;
+    ftbl->device_setproperty    = kgsl_g12_setproperty;
+    ftbl->device_idle           = kgsl_g12_idle;
+    ftbl->device_regread        = kgsl_g12_regread;
+    ftbl->device_regwrite       = kgsl_g12_regwrite;
+    ftbl->device_waitirq        = kgsl_g12_waitirq;
+	ftbl->device_waittimestamp  = kgsl_g12_waittimestamp;
+    ftbl->device_runpending     = NULL;
+    ftbl->device_addtimestamp   = kgsl_g12_addtimestamp;
+    ftbl->intr_isr              = kgsl_g12_isr;
+    ftbl->mmu_tlbinvalidate     = kgsl_g12_tlbinvalidate;
+    ftbl->mmu_setpagetable      = kgsl_g12_setpagetable;
+    ftbl->cmdstream_issueibcmds = kgsl_g12_issueibcmds;
+    ftbl->context_create        = kgsl_g12_context_create;
+    ftbl->context_destroy       = kgsl_g12_context_destroy;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+static void addmarker(gsl_z1xx_t* z1xx)
+{
+    KOS_ASSERT(z1xx);
+    {
+        unsigned int *p = z1xx->cmdbuf[z1xx->curr];
+        /* todo: use symbolic values */
+        p[z1xx->offs++] = 0x7C000176;
+        p[z1xx->offs++] = (0x8000|5);
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = 0x7C000176;
+        p[z1xx->offs++] = 5;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    }
+}
+
+//----------------------------------------------------------------------------
+static void beginpacket(gsl_z1xx_t* z1xx, gpuaddr_t cmd, unsigned int nextcnt)
+{
+    unsigned int *p = z1xx->cmdbuf[z1xx->curr];
+   
+    p[z1xx->offs++] = 0x7C000176;
+    p[z1xx->offs++] = 5;
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    p[z1xx->offs++] = 0x7C000275;
+    p[z1xx->offs++] = cmd;
+    p[z1xx->offs++] = 0x1000|nextcnt;  // nextcount
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_g12_issueibcmds(gsl_device_t* device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags)
+{
+    unsigned int ofs      = PACKETSIZE_STATESTREAM*sizeof(unsigned int);
+    unsigned int cnt      = 5;
+    unsigned int cmd      = ibaddr; 
+    unsigned int nextbuf  = (g_z1xx.curr+1)%GSL_HAL_NUMCMDBUFFERS;
+    unsigned int nextaddr = g_z1xx.cmdbufdesc[nextbuf].gpuaddr;
+    unsigned int nextcnt  = 0x9000|5;
+    gsl_memdesc_t tmp     = {0};
+    gsl_timestamp_t processed_timestamp;
+
+    (void) flags;
+
+    // read what is the latest timestamp device have processed
+    GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)&processed_timestamp);
+
+	/* wait for the next buffer's timestamp to occur */
+    while(processed_timestamp < g_z1xx.timestamp[nextbuf])
+    {
+#ifndef _LINUX	
+		kos_event_wait(device->timestamp_event, 1000);
+		kos_event_reset(device->timestamp_event);
+#else
+		kgsl_cmdstream_waittimestamp(device->id, g_z1xx.timestamp[nextbuf], 1000);
+#endif		
+		GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)&processed_timestamp);
+    }
+	
+    *timestamp = g_z1xx.timestamp[nextbuf] = device->current_timestamp + 1;
+
+    /* context switch */
+    if (drawctxt_index != (int)g_z1xx.prevctx)
+    {
+        cnt = PACKETSIZE_STATESTREAM;
+        ofs = 0; 
+    }
+    g_z1xx.prevctx = drawctxt_index;
+
+    g_z1xx.offs = 10;
+    beginpacket(&g_z1xx, cmd+ofs, cnt);
+
+    tmp.gpuaddr=ibaddr+(sizedwords*sizeof(unsigned int));
+    kgsl_sharedmem_write0(&tmp, 4, &nextaddr, 4, false);
+    kgsl_sharedmem_write0(&tmp, 8, &nextcnt,  4, false);
+
+    /* sync mem */ 
+    kgsl_sharedmem_write0((const gsl_memdesc_t *)&g_z1xx.cmdbufdesc[g_z1xx.curr], 0, g_z1xx.cmdbuf[g_z1xx.curr], (512 + 13) * sizeof(unsigned int), false);
+
+    g_z1xx.offs = 0;
+    g_z1xx.curr = nextbuf;
+
+    /* increment mark counter */
+    kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, flags);
+    kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0);
+
+    /* increment consumed timestamp */
+    device->current_timestamp++;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_g12_context_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags)
+{
+    int status = 0;
+    int i;
+    int cmd;
+	gsl_flags_t gslflags = (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGNPAGE);
+
+    // unreferenced formal parameters
+    (void) device;
+    (void) type;
+    //(void) drawctxt_id;
+    (void) flags;
+    
+    kgsl_device_active(device);
+    
+    if (g_z1xx.numcontext==0)
+    {
+         /* todo: move this to device create or start. Error checking!! */ 
+        for (i=0;i<GSL_HAL_NUMCMDBUFFERS;i++)
+        {
+            status = kgsl_sharedmem_alloc0(GSL_DEVICE_ANY, gslflags, GSL_HAL_CMDBUFFERSIZE, &g_z1xx.cmdbufdesc[i]);
+            KOS_ASSERT(status == GSL_SUCCESS);          
+            g_z1xx.cmdbuf[i]=kos_malloc(GSL_HAL_CMDBUFFERSIZE);
+            KOS_ASSERT(g_z1xx.cmdbuf[i]);
+            kos_memset((void*)g_z1xx.cmdbuf[i], 0, GSL_HAL_CMDBUFFERSIZE);
+                  
+            g_z1xx.curr = i;
+            g_z1xx.offs = 0;
+            addmarker(&g_z1xx);
+            status = kgsl_sharedmem_write0(&g_z1xx.cmdbufdesc[i],0, g_z1xx.cmdbuf[i],  (512 + 13) * sizeof(unsigned int), false);
+            KOS_ASSERT(status == GSL_SUCCESS);
+        }
+        g_z1xx.curr = 0;
+        cmd = (int)(((VGV3_NEXTCMD_JUMP) & VGV3_NEXTCMD_NEXTCMD_FMASK)<< VGV3_NEXTCMD_NEXTCMD_FSHIFT);
+
+        /* set cmd stream buffer to hw */
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, ADDR_VGV3_MODE, 4);
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, ADDR_VGV3_NEXTADDR, g_z1xx.cmdbufdesc[0].gpuaddr );
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, ADDR_VGV3_NEXTCMD,  cmd | 5);
+
+        KOS_ASSERT(status == GSL_SUCCESS);
+
+        /* Edge buffer setup todo: move register setup to own function. 
+           This function can be then called, if power managemnet is used and clocks are turned off and then on.
+        */ 
+        status |= kgsl_sharedmem_alloc0(GSL_DEVICE_ANY, gslflags, GSL_HAL_EDGE0BUFSIZE, &g_z1xx.e0);
+        status |= kgsl_sharedmem_alloc0(GSL_DEVICE_ANY, gslflags, GSL_HAL_EDGE1BUFSIZE, &g_z1xx.e1);
+        status |= kgsl_sharedmem_set0(&g_z1xx.e0, 0, 0, GSL_HAL_EDGE0BUFSIZE);
+        status |= kgsl_sharedmem_set0(&g_z1xx.e1, 0, 0, GSL_HAL_EDGE1BUFSIZE);
+
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, GSL_HAL_EDGE0REG, g_z1xx.e0.gpuaddr);
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, GSL_HAL_EDGE1REG, g_z1xx.e1.gpuaddr);
+#ifdef _Z180
+        kgsl_sharedmem_alloc0(GSL_DEVICE_ANY, gslflags, GSL_HAL_EDGE2BUFSIZE, &g_z1xx.e2);
+        kgsl_sharedmem_set0(&g_z1xx.e2, 0, 0, GSL_HAL_EDGE2BUFSIZE);
+        kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, GSL_HAL_EDGE2REG, g_z1xx.e2.gpuaddr);
+#endif  
+        KOS_ASSERT(status == GSL_SUCCESS);
+    } 
+
+    if(g_z1xx.numcontext < GSL_CONTEXT_MAX)
+    {
+        g_z1xx.numcontext++;
+        *drawctxt_id=g_z1xx.numcontext;
+        status = GSL_SUCCESS;
+    }
+    else
+    {
+        status = GSL_FAILURE;
+    }
+
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_g12_context_destroy(gsl_device_t* device, unsigned int drawctxt_id)
+{
+
+    // unreferenced formal parameters
+    (void) device;
+    (void) drawctxt_id;
+
+    g_z1xx.numcontext--;
+    if (g_z1xx.numcontext<0)
+    {
+        g_z1xx.numcontext=0;
+        return (GSL_FAILURE);
+    }
+
+    if (g_z1xx.numcontext==0)
+    {
+        int i;
+        for (i=0;i<GSL_HAL_NUMCMDBUFFERS;i++)
+        {
+            kgsl_sharedmem_free0(&g_z1xx.cmdbufdesc[i], GSL_CALLER_PROCESSID_GET());
+            kos_free(g_z1xx.cmdbuf[i]);
+        }
+        kgsl_sharedmem_free0(&g_z1xx.e0, GSL_CALLER_PROCESSID_GET());
+        kgsl_sharedmem_free0(&g_z1xx.e1, GSL_CALLER_PROCESSID_GET());
+#ifdef _Z180
+        kgsl_sharedmem_free0(&g_z1xx.e2, GSL_CALLER_PROCESSID_GET());
+#endif
+        kos_memset(&g_z1xx,0,sizeof(gsl_z1xx_t));
+    }
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+#if !defined GSL_BLD_YAMATO && (!defined __SYMBIAN32__ || defined __WINSCW__)
+KGSL_API int kgsl_drawctxt_bind_gmem_shadow(gsl_deviceid_t device_id, unsigned int drawctxt_id, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id)
+{
+    (void)device_id;
+    (void)drawctxt_id;
+    (void)gmem_rect;
+    (void)shadow_x;
+    (void)shadow_y;
+    (void)shadow_buffer;
+    (void)buffer_id;
+    return (GSL_FAILURE);
+}
+#endif
+//----------------------------------------------------------------------------
+
+#ifndef _LINUX
+static void irq_thread(void)
+{
+	int error = 0;
+    unsigned int irq_count;
+    gsl_device_t* device  = &gsl_driver.device[GSL_DEVICE_G12-1];
+    gsl_timestamp_t timestamp;
+
+    while( !error )
+    {
+#ifdef IRQTHREAD_POLL
+        if(kos_event_wait(device->irqthread_event, GSL_IRQ_TIMEOUT)==GSL_SUCCESS)
+        {
+            kgsl_g12_waitirq(device, GSL_INTR_G12_G2D, &irq_count, GSL_IRQ_TIMEOUT);
+#else
+
+        if( kgsl_g12_waitirq(device, GSL_INTR_G12_G2D, &irq_count, GSL_IRQ_TIMEOUT) == GSL_SUCCESS )
+        {
+#endif
+            /* Read a timestamp value */
+#ifdef VG_HDK            
+            timestamp = device->timestamp;
+#else
+            GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)&timestamp);
+#endif
+            /* Increase the timestamp value */
+            timestamp += irq_count;
+
+            KOS_ASSERT( timestamp <= device->current_timestamp );
+            /* Write the new timestamp value */
+#ifdef VG_HDK
+            device->timestamp = timestamp;
+#else
+            kgsl_sharedmem_write0(&device->memstore, GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), &timestamp, 4, false);
+#endif
+
+            /* Notify timestamp event */
+#ifndef _LINUX
+            kos_event_signal( device->timestamp_event );
+#else
+            wake_up_interruptible_all(&(device->timestamp_waitq));
+#endif
+        }
+        else
+        {
+            /* Timeout */
+
+           
+            if(!(device->flags&GSL_FLAGS_INITIALIZED))
+            {
+                /* if device is closed -> thread exit */
+#if defined(__SYMBIAN32__)
+                device->irq_thread = 0;
+#endif
+                return;
+            }
+        }
+    }
+}
+#endif
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_g12_addtimestamp(gsl_device_t* device, gsl_timestamp_t *timestamp)
+{    
+    device->current_timestamp++;
+    *timestamp = device->current_timestamp;
+ 
+    return (GSL_SUCCESS);
+}
+#endif
diff --git a/drivers/mxc/amd-gpu/common/gsl_intrmgr.c b/drivers/mxc/amd-gpu/common/gsl_intrmgr.c
new file mode 100644
index 000000000000..2c8b278dfe7a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_intrmgr.c
@@ -0,0 +1,305 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl.h"
+
+//////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_INTRID_VALIDATE(id) (((id) < 0) || ((id) >= GSL_INTR_COUNT))
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+static const gsl_intrblock_reg_t * 
+kgsl_intr_id2block(gsl_intrid_t id)
+{
+    const gsl_intrblock_reg_t  *block;
+    int                        i;
+
+    // interrupt id to hw block
+    for (i = 0; i < GSL_INTR_BLOCK_COUNT; i++) 
+    {
+        block = &gsl_cfg_intrblock_reg[i];
+
+        if (block->first_id <= id && id <= block->last_id) 
+        {
+            return (block);
+        }
+    }
+
+    return (NULL);
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_intr_decode(gsl_device_t *device, gsl_intrblock_t block_id)
+{
+    const gsl_intrblock_reg_t  *block = &gsl_cfg_intrblock_reg[block_id];
+    gsl_intrid_t               id;
+    unsigned int               status;
+
+    // read the block's interrupt status bits
+    device->ftbl.device_regread(device, block->status_reg, &status);
+
+    // mask off any interrupts which are disabled
+    status &= device->intr.enabled[block->id];
+
+    // acknowledge the block's interrupts
+    device->ftbl.device_regwrite(device, block->clear_reg, status);
+
+    // loop through the block's masks, determine which interrupt bits are active, and call callback (or TODO queue DPC)
+    for (id = block->first_id; id <= block->last_id; id++) 
+    {
+        if (status & gsl_cfg_intr_mask[id])
+        {
+            device->intr.handler[id].callback(id, device->intr.handler[id].cookie);
+        }
+    }
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API void
+kgsl_intr_isr()
+{
+    gsl_deviceid_t  device_id;
+    gsl_device_t    *device;
+
+    // loop through the devices, and call device specific isr
+    for (device_id = (gsl_deviceid_t)(GSL_DEVICE_ANY + 1); device_id <= GSL_DEVICE_MAX; device_id++)
+    {
+        device = &gsl_driver.device[device_id-1];    // device_id is 1 based
+
+        if (device->intr.flags & GSL_FLAGS_INITIALIZED)
+        {
+            kgsl_device_active(device);
+            device->ftbl.intr_isr(device);
+        }
+    }
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_intr_init(gsl_device_t *device)
+{
+    if (device->ftbl.intr_isr == NULL)
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (device->intr.flags & GSL_FLAGS_INITIALIZED)
+    {
+        return (GSL_SUCCESS);
+    }
+
+    device->intr.device  = device;
+    device->intr.flags  |= GSL_FLAGS_INITIALIZED;
+
+    // os_interrupt_setcallback(YAMATO_INTR, kgsl_intr_isr);
+    // os_interrupt_enable(YAMATO_INTR);
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_intr_close(gsl_device_t *device)
+{
+    const gsl_intrblock_reg_t  *block;
+    int                        i, id;
+
+    if (device->intr.flags & GSL_FLAGS_INITIALIZED)
+    {
+        // check if there are any enabled interrupts lingering around
+        for (i = 0; i < GSL_INTR_BLOCK_COUNT; i++) 
+        {
+            if (device->intr.enabled[i]) 
+            {
+                block = &gsl_cfg_intrblock_reg[i];
+
+                // loop through the block's masks, disable interrupts which active
+                for (id = block->first_id; id <= block->last_id; id++) 
+                {
+                    if (device->intr.enabled[i] & gsl_cfg_intr_mask[id])
+                    {
+                        kgsl_intr_disable(&device->intr, (gsl_intrid_t)id);
+                    }
+                }
+            }
+        }
+
+        kos_memset(&device->intr, 0, sizeof(gsl_intr_t));
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_intr_enable(gsl_intr_t *intr, gsl_intrid_t id)
+{
+    const gsl_intrblock_reg_t  *block;
+    unsigned int               mask;
+    unsigned int               enabled;
+
+    if (GSL_INTRID_VALIDATE(id)) 
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (intr->handler[id].callback == NULL) 
+    {
+        return (GSL_FAILURE_NOTINITIALIZED);
+    }
+
+    block = kgsl_intr_id2block(id);
+    if (block == NULL) 
+    {
+        return (GSL_FAILURE_SYSTEMERROR);
+    }
+
+    mask    = gsl_cfg_intr_mask[id];
+    enabled = intr->enabled[block->id];
+
+    if (mask && !(enabled & mask))
+    {
+        intr->evnt[id] = kos_event_create(0);
+
+        enabled                 |= mask;
+        intr->enabled[block->id] = enabled;
+        intr->device->ftbl.device_regwrite(intr->device, block->mask_reg, enabled);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_intr_disable(gsl_intr_t *intr, gsl_intrid_t id)
+{
+    const gsl_intrblock_reg_t  *block;
+    unsigned int               mask;
+    unsigned int               enabled;
+
+    if (GSL_INTRID_VALIDATE(id))
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (intr->handler[id].callback == NULL) 
+    {
+        return (GSL_FAILURE_NOTINITIALIZED);
+    }
+
+    block = kgsl_intr_id2block(id);
+    if (block == NULL) 
+    {
+        return (GSL_FAILURE_SYSTEMERROR);
+    }
+
+    mask    = gsl_cfg_intr_mask[id];
+    enabled = intr->enabled[block->id];
+
+    if (enabled & mask) 
+    {
+        enabled                 &= ~mask;
+        intr->enabled[block->id] = enabled;
+        intr->device->ftbl.device_regwrite(intr->device, block->mask_reg, enabled);
+
+        kos_event_signal(intr->evnt[id]); // wake up waiting threads before destroying the event
+        kos_event_destroy(intr->evnt[id]);
+        intr->evnt[id] = 0;
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_intr_attach(gsl_intr_t *intr, gsl_intrid_t id, gsl_intr_callback_t callback, void *cookie)
+{
+    if (GSL_INTRID_VALIDATE(id) || callback == NULL) 
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (intr->handler[id].callback != NULL) 
+    {
+        if (intr->handler[id].callback == callback && intr->handler[id].cookie == cookie) 
+        {
+            return (GSL_FAILURE_ALREADYINITIALIZED);
+        } 
+        else 
+        {
+            return (GSL_FAILURE_NOMOREAVAILABLE);
+        }
+    }
+
+    intr->handler[id].callback = callback;
+    intr->handler[id].cookie   = cookie;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_intr_detach(gsl_intr_t *intr, gsl_intrid_t id)
+{
+    if (GSL_INTRID_VALIDATE(id)) 
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (intr->handler[id].callback == NULL) 
+    {
+        return (GSL_FAILURE_NOTINITIALIZED);
+    }
+
+    kgsl_intr_disable(intr, id);
+
+    intr->handler[id].callback = NULL;
+    intr->handler[id].cookie   = NULL;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_intr_isenabled(gsl_intr_t *intr, gsl_intrid_t id)
+{
+    int                        status = GSL_FAILURE;
+    const gsl_intrblock_reg_t  *block = kgsl_intr_id2block(id);
+
+    if (block != NULL)
+    {
+        // check if interrupt is enabled
+        if (intr->enabled[block->id] & gsl_cfg_intr_mask[id])
+        {
+            status = GSL_SUCCESS;
+        }
+    }
+
+    return (status);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_log.c b/drivers/mxc/amd-gpu/common/gsl_log.c
new file mode 100644
index 000000000000..79a14a5f4b21
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_log.c
@@ -0,0 +1,591 @@
+/* Copyright (c) 2002,2008-2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#ifdef GSL_LOG
+
+#define _CRT_SECURE_NO_WARNINGS
+
+#include <stdarg.h>
+#include <stdio.h>
+#include <string.h>
+#include "gsl.h"
+
+#define KGSL_OUTPUT_TYPE_MEMBUF 0
+#define KGSL_OUTPUT_TYPE_STDOUT 1
+#define KGSL_OUTPUT_TYPE_FILE   2
+
+#define REG_OUTPUT( X ) case X: b += sprintf( b, "%s", #X ); break;
+#define INTRID_OUTPUT( X ) case X: b += sprintf( b, "%s", #X ); break;
+
+typedef struct log_output
+{
+    unsigned char       type;
+    unsigned int        flags;
+    oshandle_t         file;
+
+    struct log_output*  next;
+} log_output_t;
+
+static log_output_t* outputs = NULL;
+
+static oshandle_t   log_mutex = NULL;
+static char         buffer[256];
+static char         buffer2[256];
+static int          log_initialized = 0;
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_init()
+{
+    log_mutex = kos_mutex_create( "log_mutex" );
+
+    log_initialized = 1;
+    
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_close()
+{
+    if( !log_initialized ) return GSL_SUCCESS;
+
+    // Go throught output list and free every node
+    while( outputs != NULL )
+    {
+        log_output_t* temp = outputs->next;
+        
+        switch( outputs->type )
+        {
+            case KGSL_OUTPUT_TYPE_FILE:
+                kos_fclose( outputs->file );
+            break;
+        }
+
+        kos_free( outputs );
+        outputs = temp;
+    }
+
+    kos_mutex_free( log_mutex );
+
+    log_initialized = 0;
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_open_stdout( unsigned int log_flags )
+{
+    log_output_t* output;
+    
+    if( !log_initialized ) return GSL_SUCCESS;
+    
+    output = kos_malloc( sizeof( log_output_t ) );
+    output->type = KGSL_OUTPUT_TYPE_STDOUT;
+    output->flags = log_flags;
+
+    // Add to the list
+    if( outputs == NULL )    
+    {
+        // First node in the list.
+        outputs = output;
+        output->next = NULL;
+    }
+    else
+    {
+        // Add to the start of the list
+        output->next = outputs;
+        outputs = output;
+    }
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags )
+{
+    // TODO
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_open_file( char* filename, unsigned int log_flags )
+{
+    log_output_t* output;
+    
+    if( !log_initialized ) return GSL_SUCCESS;
+    
+    output = kos_malloc( sizeof( log_output_t ) );
+    output->type = KGSL_OUTPUT_TYPE_FILE;
+    output->flags = log_flags;
+    output->file = kos_fopen( filename, "w" );
+
+    // Add to the list
+    if( outputs == NULL )    
+    {
+        // First node in the list.
+        outputs = output;
+        output->next = NULL;
+    }
+    else
+    {
+        // Add to the start of the list
+        output->next = outputs;
+        outputs = output;
+    }
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_flush_membuf( char* filename, int memBufId )
+{
+    // TODO
+
+    return GSL_SUCCESS;
+}
+//----------------------------------------------------------------------------
+
+int kgsl_log_write( unsigned int log_flags, char* format, ... )
+{
+    char            *c = format;
+    char            *b = buffer;
+    char            *p1, *p2;
+    log_output_t*   output;
+    va_list         arguments;
+
+    if( !log_initialized ) return GSL_SUCCESS;
+
+    // Acquire mutex lock as we are using shared buffer for the string parsing
+    kos_mutex_lock( log_mutex );
+
+    // Add separator
+    *(b++) = '|'; *(b++) = ' ';
+
+    va_start( arguments, format );
+
+    while( 1 )
+    {
+        // Find the first occurence of %
+        p1 = strchr( c, '%' );
+        if( !p1 ) 
+        {
+            // No more % characters -> copy rest of the string
+            strcpy( b, c );
+
+            break;
+        }
+
+        // Find the second occurence of % and handle the string until that point
+        p2 = strchr( p1+1, '%' );
+
+        // If not found, just use the end of the buffer
+        if( !p2 ) p2 = strchr( p1+1, '\0' );
+
+        // Break the string to this point
+        kos_memcpy( buffer2, c, p2-c );
+        *(buffer2+(unsigned int)(p2-c)) = '\0';
+
+        switch( *(p1+1) )
+        {
+            // gsl_memdesc_t
+            case 'M':
+            {
+                gsl_memdesc_t val = va_arg( arguments, gsl_memdesc_t );
+                // Handle string before %M
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %M
+                b += sprintf( b, "[hostptr=0x%08x, gpuaddr=0x%08x]", val.hostptr, val.gpuaddr );
+                // Handle string after %M
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+
+            // GSL_SUCCESS/GSL_FAILURE
+            case 'B':
+            {
+                int val = va_arg( arguments, int );
+                // Handle string before %B
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %B
+                if( val == GSL_SUCCESS )
+                    b += sprintf( b, "%s", "GSL_SUCCESS" );
+                else
+                    b += sprintf( b, "%s", "GSL_FAILURE" );
+                // Handle string after %B
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+
+            // gsl_deviceid_t
+            case 'D':
+            {
+                gsl_deviceid_t val = va_arg( arguments, gsl_deviceid_t );
+                // Handle string before %D
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %D
+                switch( val )
+                {
+                    case GSL_DEVICE_ANY:
+                        b += sprintf( b, "%s", "GSL_DEVICE_ANY" );
+                    break;
+                    case GSL_DEVICE_YAMATO:
+                        b += sprintf( b, "%s", "GSL_DEVICE_YAMATO" );
+                    break;
+                    case GSL_DEVICE_G12:
+                        b += sprintf( b, "%s", "GSL_DEVICE_G12" );
+                    break;
+                    default:
+                        b += sprintf( b, "%s", "UNKNOWN DEVICE" );
+                    break;
+                }
+                // Handle string after %D
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+            
+            // gsl_intrid_t
+            case 'I':
+            {
+                unsigned int val = va_arg( arguments, unsigned int );
+                // Handle string before %I
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %I
+                switch( val )
+                {
+                    INTRID_OUTPUT( GSL_INTR_YDX_MH_AXI_READ_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_MH_AXI_WRITE_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_MH_MMU_PAGE_FAULT );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_SW_INT );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_T0_PACKET_IN_IB );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_OPCODE_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_RESERVED_BIT_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_IB_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_IB2_INT );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_IB1_INT );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_RING_BUFFER );
+                    INTRID_OUTPUT( GSL_INTR_YDX_RBBM_READ_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_RBBM_DISPLAY_UPDATE );
+                    INTRID_OUTPUT( GSL_INTR_YDX_RBBM_GUI_IDLE );
+                    INTRID_OUTPUT( GSL_INTR_YDX_SQ_PS_WATCHDOG );
+                    INTRID_OUTPUT( GSL_INTR_YDX_SQ_VS_WATCHDOG );
+                    INTRID_OUTPUT( GSL_INTR_G12_MH );
+                    INTRID_OUTPUT( GSL_INTR_G12_G2D );
+                    INTRID_OUTPUT( GSL_INTR_G12_FIFO );
+#ifndef _Z180
+                    INTRID_OUTPUT( GSL_INTR_G12_FBC );
+#endif // _Z180
+                    INTRID_OUTPUT( GSL_INTR_G12_MH_AXI_READ_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_G12_MH_AXI_WRITE_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_G12_MH_MMU_PAGE_FAULT );
+                    INTRID_OUTPUT( GSL_INTR_COUNT );
+                    INTRID_OUTPUT( GSL_INTR_FOOBAR );
+
+                    default:
+                        b += sprintf( b, "%s", "UNKNOWN INTERRUPT ID" );
+                    break;
+                }
+                // Handle string after %I
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+
+            // Register offset
+            case 'R':
+            {
+                unsigned int val = va_arg( arguments, unsigned int );
+                
+                // Handle string before %R
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %R
+                switch( val )
+                {
+                    REG_OUTPUT( mmPA_CL_VPORT_XSCALE ); REG_OUTPUT( mmPA_CL_VPORT_XOFFSET ); REG_OUTPUT( mmPA_CL_VPORT_YSCALE );
+                    REG_OUTPUT( mmPA_CL_VPORT_YOFFSET ); REG_OUTPUT( mmPA_CL_VPORT_ZSCALE ); REG_OUTPUT( mmPA_CL_VPORT_ZOFFSET );
+                    REG_OUTPUT( mmPA_CL_VTE_CNTL ); REG_OUTPUT( mmPA_CL_CLIP_CNTL ); REG_OUTPUT( mmPA_CL_GB_VERT_CLIP_ADJ );
+                    REG_OUTPUT( mmPA_CL_GB_VERT_DISC_ADJ ); REG_OUTPUT( mmPA_CL_GB_HORZ_CLIP_ADJ ); REG_OUTPUT( mmPA_CL_GB_HORZ_DISC_ADJ );
+                    REG_OUTPUT( mmPA_CL_ENHANCE ); REG_OUTPUT( mmPA_SC_ENHANCE ); REG_OUTPUT( mmPA_SU_VTX_CNTL );
+                    REG_OUTPUT( mmPA_SU_POINT_SIZE ); REG_OUTPUT( mmPA_SU_POINT_MINMAX ); REG_OUTPUT( mmPA_SU_LINE_CNTL );
+                    REG_OUTPUT( mmPA_SU_FACE_DATA ); REG_OUTPUT( mmPA_SU_SC_MODE_CNTL ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_FRONT_SCALE );
+                    REG_OUTPUT( mmPA_SU_POLY_OFFSET_FRONT_OFFSET ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_BACK_SCALE ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_BACK_OFFSET );
+                    REG_OUTPUT( mmPA_SU_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER2_SELECT );
+                    REG_OUTPUT( mmPA_SU_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER0_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER0_HI );
+                    REG_OUTPUT( mmPA_SU_PERFCOUNTER1_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER1_HI ); REG_OUTPUT( mmPA_SU_PERFCOUNTER2_LOW );
+                    REG_OUTPUT( mmPA_SU_PERFCOUNTER2_HI ); REG_OUTPUT( mmPA_SU_PERFCOUNTER3_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER3_HI );
+                    REG_OUTPUT( mmPA_SC_WINDOW_OFFSET ); REG_OUTPUT( mmPA_SC_AA_CONFIG ); REG_OUTPUT( mmPA_SC_AA_MASK );
+                    REG_OUTPUT( mmPA_SC_LINE_STIPPLE ); REG_OUTPUT( mmPA_SC_LINE_CNTL ); REG_OUTPUT( mmPA_SC_WINDOW_SCISSOR_TL );
+                    REG_OUTPUT( mmPA_SC_WINDOW_SCISSOR_BR ); REG_OUTPUT( mmPA_SC_SCREEN_SCISSOR_TL ); REG_OUTPUT( mmPA_SC_SCREEN_SCISSOR_BR );
+                    REG_OUTPUT( mmPA_SC_VIZ_QUERY ); REG_OUTPUT( mmPA_SC_VIZ_QUERY_STATUS ); REG_OUTPUT( mmPA_SC_LINE_STIPPLE_STATE );
+                    REG_OUTPUT( mmPA_SC_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmPA_SC_PERFCOUNTER0_LOW ); REG_OUTPUT( mmPA_SC_PERFCOUNTER0_HI );
+                    REG_OUTPUT( mmPA_CL_CNTL_STATUS ); REG_OUTPUT( mmPA_SU_CNTL_STATUS ); REG_OUTPUT( mmPA_SC_CNTL_STATUS );
+                    REG_OUTPUT( mmPA_SU_DEBUG_CNTL ); REG_OUTPUT( mmPA_SU_DEBUG_DATA ); REG_OUTPUT( mmPA_SC_DEBUG_CNTL );
+                    REG_OUTPUT( mmPA_SC_DEBUG_DATA ); REG_OUTPUT( mmGFX_COPY_STATE ); REG_OUTPUT( mmVGT_DRAW_INITIATOR );
+                    REG_OUTPUT( mmVGT_EVENT_INITIATOR ); REG_OUTPUT( mmVGT_DMA_BASE ); REG_OUTPUT( mmVGT_DMA_SIZE );
+                    REG_OUTPUT( mmVGT_BIN_BASE ); REG_OUTPUT( mmVGT_BIN_SIZE ); REG_OUTPUT( mmVGT_CURRENT_BIN_ID_MIN );
+                    REG_OUTPUT( mmVGT_CURRENT_BIN_ID_MAX ); REG_OUTPUT( mmVGT_IMMED_DATA ); REG_OUTPUT( mmVGT_MAX_VTX_INDX );
+                    REG_OUTPUT( mmVGT_MIN_VTX_INDX ); REG_OUTPUT( mmVGT_INDX_OFFSET ); REG_OUTPUT( mmVGT_VERTEX_REUSE_BLOCK_CNTL );
+                    REG_OUTPUT( mmVGT_OUT_DEALLOC_CNTL ); REG_OUTPUT( mmVGT_MULTI_PRIM_IB_RESET_INDX ); REG_OUTPUT( mmVGT_ENHANCE );
+                    REG_OUTPUT( mmVGT_VTX_VECT_EJECT_REG ); REG_OUTPUT( mmVGT_LAST_COPY_STATE ); REG_OUTPUT( mmVGT_DEBUG_CNTL );
+                    REG_OUTPUT( mmVGT_DEBUG_DATA ); REG_OUTPUT( mmVGT_CNTL_STATUS ); REG_OUTPUT( mmVGT_CRC_SQ_DATA );
+                    REG_OUTPUT( mmVGT_CRC_SQ_CTRL ); REG_OUTPUT( mmVGT_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER1_SELECT );
+                    REG_OUTPUT( mmVGT_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER0_LOW );
+                    REG_OUTPUT( mmVGT_PERFCOUNTER1_LOW ); REG_OUTPUT( mmVGT_PERFCOUNTER2_LOW ); REG_OUTPUT( mmVGT_PERFCOUNTER3_LOW );
+                    REG_OUTPUT( mmVGT_PERFCOUNTER0_HI ); REG_OUTPUT( mmVGT_PERFCOUNTER1_HI ); REG_OUTPUT( mmVGT_PERFCOUNTER2_HI );
+                    REG_OUTPUT( mmVGT_PERFCOUNTER3_HI ); REG_OUTPUT( mmTC_CNTL_STATUS ); REG_OUTPUT( mmTCR_CHICKEN );
+                    REG_OUTPUT( mmTCF_CHICKEN ); REG_OUTPUT( mmTCM_CHICKEN ); REG_OUTPUT( mmTCR_PERFCOUNTER0_SELECT );
+                    REG_OUTPUT( mmTCR_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmTCR_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCR_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmTCR_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTCR_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTP_TC_CLKGATE_CNTL );
+                    REG_OUTPUT( mmTPC_CNTL_STATUS ); REG_OUTPUT( mmTPC_DEBUG0 ); REG_OUTPUT( mmTPC_DEBUG1 );
+                    REG_OUTPUT( mmTPC_CHICKEN ); REG_OUTPUT( mmTP0_CNTL_STATUS ); REG_OUTPUT( mmTP0_DEBUG );
+                    REG_OUTPUT( mmTP0_CHICKEN ); REG_OUTPUT( mmTP0_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTP0_PERFCOUNTER0_HI );
+                    REG_OUTPUT( mmTP0_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTP0_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmTP0_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmTP0_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTCM_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTCM_PERFCOUNTER1_SELECT );
+                    REG_OUTPUT( mmTCM_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCM_PERFCOUNTER1_HI ); REG_OUTPUT( mmTCM_PERFCOUNTER0_LOW );
+                    REG_OUTPUT( mmTCM_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER1_SELECT );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER4_SELECT );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER5_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER6_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER7_SELECT );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER8_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER9_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER10_SELECT );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER11_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER2_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER3_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER4_HI );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER5_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER6_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER7_HI );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER8_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER9_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER10_HI );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER11_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER1_LOW );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER2_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER3_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER4_LOW );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER5_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER6_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER7_LOW );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER8_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER9_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER10_LOW );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER11_LOW ); REG_OUTPUT( mmTCF_DEBUG ); REG_OUTPUT( mmTCA_FIFO_DEBUG );
+                    REG_OUTPUT( mmTCA_PROBE_DEBUG ); REG_OUTPUT( mmTCA_TPC_DEBUG ); REG_OUTPUT( mmTCB_CORE_DEBUG );
+                    REG_OUTPUT( mmTCB_TAG0_DEBUG ); REG_OUTPUT( mmTCB_TAG1_DEBUG ); REG_OUTPUT( mmTCB_TAG2_DEBUG );
+                    REG_OUTPUT( mmTCB_TAG3_DEBUG ); REG_OUTPUT( mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG ); REG_OUTPUT( mmTCB_FETCH_GEN_WALKER_DEBUG );
+                    REG_OUTPUT( mmTCB_FETCH_GEN_PIPE0_DEBUG ); REG_OUTPUT( mmTCD_INPUT0_DEBUG ); REG_OUTPUT( mmTCD_DEGAMMA_DEBUG );
+                    REG_OUTPUT( mmTCD_DXTMUX_SCTARB_DEBUG ); REG_OUTPUT( mmTCD_DXTC_ARB_DEBUG ); REG_OUTPUT( mmTCD_STALLS_DEBUG );
+                    REG_OUTPUT( mmTCO_STALLS_DEBUG ); REG_OUTPUT( mmTCO_QUAD0_DEBUG0 ); REG_OUTPUT( mmTCO_QUAD0_DEBUG1 );
+                    REG_OUTPUT( mmSQ_GPR_MANAGEMENT ); REG_OUTPUT( mmSQ_FLOW_CONTROL ); REG_OUTPUT( mmSQ_INST_STORE_MANAGMENT );
+                    REG_OUTPUT( mmSQ_RESOURCE_MANAGMENT ); REG_OUTPUT( mmSQ_EO_RT ); REG_OUTPUT( mmSQ_DEBUG_MISC );
+                    REG_OUTPUT( mmSQ_ACTIVITY_METER_CNTL ); REG_OUTPUT( mmSQ_ACTIVITY_METER_STATUS ); REG_OUTPUT( mmSQ_INPUT_ARB_PRIORITY );
+                    REG_OUTPUT( mmSQ_THREAD_ARB_PRIORITY ); REG_OUTPUT( mmSQ_VS_WATCHDOG_TIMER ); REG_OUTPUT( mmSQ_PS_WATCHDOG_TIMER );
+                    REG_OUTPUT( mmSQ_INT_CNTL ); REG_OUTPUT( mmSQ_INT_STATUS ); REG_OUTPUT( mmSQ_INT_ACK );
+                    REG_OUTPUT( mmSQ_DEBUG_INPUT_FSM ); REG_OUTPUT( mmSQ_DEBUG_CONST_MGR_FSM ); REG_OUTPUT( mmSQ_DEBUG_TP_FSM );
+                    REG_OUTPUT( mmSQ_DEBUG_FSM_ALU_0 ); REG_OUTPUT( mmSQ_DEBUG_FSM_ALU_1 ); REG_OUTPUT( mmSQ_DEBUG_EXP_ALLOC );
+                    REG_OUTPUT( mmSQ_DEBUG_PTR_BUFF ); REG_OUTPUT( mmSQ_DEBUG_GPR_VTX ); REG_OUTPUT( mmSQ_DEBUG_GPR_PIX );
+                    REG_OUTPUT( mmSQ_DEBUG_TB_STATUS_SEL ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_0 ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_1 );
+                    REG_OUTPUT( mmSQ_DEBUG_VTX_TB_STATUS_REG ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_STATE_MEM ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_0 );
+                    REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_0 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_1 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_2 );
+                    REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_3 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATE_MEM ); REG_OUTPUT( mmSQ_PERFCOUNTER0_SELECT );
+                    REG_OUTPUT( mmSQ_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmSQ_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmSQ_PERFCOUNTER3_SELECT );
+                    REG_OUTPUT( mmSQ_PERFCOUNTER0_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER0_HI ); REG_OUTPUT( mmSQ_PERFCOUNTER1_LOW );
+                    REG_OUTPUT( mmSQ_PERFCOUNTER1_HI ); REG_OUTPUT( mmSQ_PERFCOUNTER2_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER2_HI );
+                    REG_OUTPUT( mmSQ_PERFCOUNTER3_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER3_HI ); REG_OUTPUT( mmSX_PERFCOUNTER0_SELECT );
+                    REG_OUTPUT( mmSX_PERFCOUNTER0_LOW ); REG_OUTPUT( mmSX_PERFCOUNTER0_HI ); REG_OUTPUT( mmSQ_INSTRUCTION_ALU_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_ALU_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_ALU_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_2 ); REG_OUTPUT( mmSQ_CONSTANT_0 );
+                    REG_OUTPUT( mmSQ_CONSTANT_1 ); REG_OUTPUT( mmSQ_CONSTANT_2 ); REG_OUTPUT( mmSQ_CONSTANT_3 );
+                    REG_OUTPUT( mmSQ_FETCH_0 ); REG_OUTPUT( mmSQ_FETCH_1 ); REG_OUTPUT( mmSQ_FETCH_2 );
+                    REG_OUTPUT( mmSQ_FETCH_3 ); REG_OUTPUT( mmSQ_FETCH_4 ); REG_OUTPUT( mmSQ_FETCH_5 );
+                    REG_OUTPUT( mmSQ_CONSTANT_VFETCH_0 ); REG_OUTPUT( mmSQ_CONSTANT_VFETCH_1 ); REG_OUTPUT( mmSQ_CONSTANT_T2 );
+                    REG_OUTPUT( mmSQ_CONSTANT_T3 ); REG_OUTPUT( mmSQ_CF_BOOLEANS ); REG_OUTPUT( mmSQ_CF_LOOP );
+                    REG_OUTPUT( mmSQ_CONSTANT_RT_0 ); REG_OUTPUT( mmSQ_CONSTANT_RT_1 ); REG_OUTPUT( mmSQ_CONSTANT_RT_2 );
+                    REG_OUTPUT( mmSQ_CONSTANT_RT_3 ); REG_OUTPUT( mmSQ_FETCH_RT_0 ); REG_OUTPUT( mmSQ_FETCH_RT_1 );
+                    REG_OUTPUT( mmSQ_FETCH_RT_2 ); REG_OUTPUT( mmSQ_FETCH_RT_3 ); REG_OUTPUT( mmSQ_FETCH_RT_4 );
+                    REG_OUTPUT( mmSQ_FETCH_RT_5 ); REG_OUTPUT( mmSQ_CF_RT_BOOLEANS ); REG_OUTPUT( mmSQ_CF_RT_LOOP );
+                    REG_OUTPUT( mmSQ_VS_PROGRAM ); REG_OUTPUT( mmSQ_PS_PROGRAM ); REG_OUTPUT( mmSQ_CF_PROGRAM_SIZE );
+                    REG_OUTPUT( mmSQ_INTERPOLATOR_CNTL ); REG_OUTPUT( mmSQ_PROGRAM_CNTL ); REG_OUTPUT( mmSQ_WRAPPING_0 );
+                    REG_OUTPUT( mmSQ_WRAPPING_1 ); REG_OUTPUT( mmSQ_VS_CONST ); REG_OUTPUT( mmSQ_PS_CONST );
+                    REG_OUTPUT( mmSQ_CONTEXT_MISC ); REG_OUTPUT( mmSQ_CF_RD_BASE ); REG_OUTPUT( mmSQ_DEBUG_MISC_0 );
+                    REG_OUTPUT( mmSQ_DEBUG_MISC_1 ); REG_OUTPUT( mmMH_ARBITER_CONFIG ); REG_OUTPUT( mmMH_CLNT_AXI_ID_REUSE );
+                    REG_OUTPUT( mmMH_INTERRUPT_MASK ); REG_OUTPUT( mmMH_INTERRUPT_STATUS ); REG_OUTPUT( mmMH_INTERRUPT_CLEAR );
+                    REG_OUTPUT( mmMH_AXI_ERROR ); REG_OUTPUT( mmMH_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmMH_PERFCOUNTER1_SELECT );
+                    REG_OUTPUT( mmMH_PERFCOUNTER0_CONFIG ); REG_OUTPUT( mmMH_PERFCOUNTER1_CONFIG ); REG_OUTPUT( mmMH_PERFCOUNTER0_LOW );
+                    REG_OUTPUT( mmMH_PERFCOUNTER1_LOW ); REG_OUTPUT( mmMH_PERFCOUNTER0_HI ); REG_OUTPUT( mmMH_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmMH_DEBUG_CTRL ); REG_OUTPUT( mmMH_DEBUG_DATA ); REG_OUTPUT( mmMH_AXI_HALT_CONTROL );
+                    REG_OUTPUT( mmMH_MMU_CONFIG ); REG_OUTPUT( mmMH_MMU_VA_RANGE ); REG_OUTPUT( mmMH_MMU_PT_BASE );
+                    REG_OUTPUT( mmMH_MMU_PAGE_FAULT ); REG_OUTPUT( mmMH_MMU_TRAN_ERROR ); REG_OUTPUT( mmMH_MMU_INVALIDATE );
+                    REG_OUTPUT( mmMH_MMU_MPU_BASE ); REG_OUTPUT( mmMH_MMU_MPU_END ); REG_OUTPUT( mmWAIT_UNTIL );
+                    REG_OUTPUT( mmRBBM_ISYNC_CNTL ); REG_OUTPUT( mmRBBM_STATUS ); REG_OUTPUT( mmRBBM_DSPLY );
+                    REG_OUTPUT( mmRBBM_RENDER_LATEST ); REG_OUTPUT( mmRBBM_RTL_RELEASE ); REG_OUTPUT( mmRBBM_PATCH_RELEASE );
+                    REG_OUTPUT( mmRBBM_AUXILIARY_CONFIG ); REG_OUTPUT( mmRBBM_PERIPHID0 ); REG_OUTPUT( mmRBBM_PERIPHID1 );
+                    REG_OUTPUT( mmRBBM_PERIPHID2 ); REG_OUTPUT( mmRBBM_PERIPHID3 ); REG_OUTPUT( mmRBBM_CNTL );
+                    REG_OUTPUT( mmRBBM_SKEW_CNTL ); REG_OUTPUT( mmRBBM_SOFT_RESET ); REG_OUTPUT( mmRBBM_PM_OVERRIDE1 );
+                    REG_OUTPUT( mmRBBM_PM_OVERRIDE2 ); REG_OUTPUT( mmGC_SYS_IDLE ); REG_OUTPUT( mmNQWAIT_UNTIL );
+                    REG_OUTPUT( mmRBBM_DEBUG_OUT ); REG_OUTPUT( mmRBBM_DEBUG_CNTL ); REG_OUTPUT( mmRBBM_DEBUG );
+                    REG_OUTPUT( mmRBBM_READ_ERROR ); REG_OUTPUT( mmRBBM_WAIT_IDLE_CLOCKS ); REG_OUTPUT( mmRBBM_INT_CNTL );
+                    REG_OUTPUT( mmRBBM_INT_STATUS ); REG_OUTPUT( mmRBBM_INT_ACK ); REG_OUTPUT( mmMASTER_INT_SIGNAL );
+                    REG_OUTPUT( mmRBBM_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmRBBM_PERFCOUNTER1_LO ); REG_OUTPUT( mmRBBM_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmCP_RB_BASE ); REG_OUTPUT( mmCP_RB_CNTL ); REG_OUTPUT( mmCP_RB_RPTR_ADDR );
+                    REG_OUTPUT( mmCP_RB_RPTR ); REG_OUTPUT( mmCP_RB_RPTR_WR ); REG_OUTPUT( mmCP_RB_WPTR );
+                    REG_OUTPUT( mmCP_RB_WPTR_DELAY ); REG_OUTPUT( mmCP_RB_WPTR_BASE ); REG_OUTPUT( mmCP_IB1_BASE );
+                    REG_OUTPUT( mmCP_IB1_BUFSZ ); REG_OUTPUT( mmCP_IB2_BASE ); REG_OUTPUT( mmCP_IB2_BUFSZ );
+                    REG_OUTPUT( mmCP_ST_BASE ); REG_OUTPUT( mmCP_ST_BUFSZ ); REG_OUTPUT( mmCP_QUEUE_THRESHOLDS );
+                    REG_OUTPUT( mmCP_MEQ_THRESHOLDS ); REG_OUTPUT( mmCP_CSQ_AVAIL ); REG_OUTPUT( mmCP_STQ_AVAIL );
+                    REG_OUTPUT( mmCP_MEQ_AVAIL ); REG_OUTPUT( mmCP_CSQ_RB_STAT ); REG_OUTPUT( mmCP_CSQ_IB1_STAT );
+                    REG_OUTPUT( mmCP_CSQ_IB2_STAT ); REG_OUTPUT( mmCP_NON_PREFETCH_CNTRS ); REG_OUTPUT( mmCP_STQ_ST_STAT );
+                    REG_OUTPUT( mmCP_MEQ_STAT ); REG_OUTPUT( mmCP_MIU_TAG_STAT ); REG_OUTPUT( mmCP_CMD_INDEX );
+                    REG_OUTPUT( mmCP_CMD_DATA ); REG_OUTPUT( mmCP_ME_CNTL ); REG_OUTPUT( mmCP_ME_STATUS );
+                    REG_OUTPUT( mmCP_ME_RAM_WADDR ); REG_OUTPUT( mmCP_ME_RAM_RADDR ); REG_OUTPUT( mmCP_ME_RAM_DATA );
+                    REG_OUTPUT( mmCP_ME_RDADDR ); REG_OUTPUT( mmCP_DEBUG ); REG_OUTPUT( mmSCRATCH_REG0 );
+                    REG_OUTPUT( mmSCRATCH_REG1 ); REG_OUTPUT( mmSCRATCH_REG2 ); REG_OUTPUT( mmSCRATCH_REG3 );
+                    REG_OUTPUT( mmSCRATCH_REG4 ); REG_OUTPUT( mmSCRATCH_REG5 ); REG_OUTPUT( mmSCRATCH_REG6 );
+                    REG_OUTPUT( mmSCRATCH_REG7 );
+                    REG_OUTPUT( mmSCRATCH_UMSK ); REG_OUTPUT( mmSCRATCH_ADDR ); REG_OUTPUT( mmCP_ME_VS_EVENT_SRC );
+                    REG_OUTPUT( mmCP_ME_VS_EVENT_ADDR ); REG_OUTPUT( mmCP_ME_VS_EVENT_DATA ); REG_OUTPUT( mmCP_ME_VS_EVENT_ADDR_SWM );
+                    REG_OUTPUT( mmCP_ME_VS_EVENT_DATA_SWM ); REG_OUTPUT( mmCP_ME_PS_EVENT_SRC ); REG_OUTPUT( mmCP_ME_PS_EVENT_ADDR );
+                    REG_OUTPUT( mmCP_ME_PS_EVENT_DATA ); REG_OUTPUT( mmCP_ME_PS_EVENT_ADDR_SWM ); REG_OUTPUT( mmCP_ME_PS_EVENT_DATA_SWM );
+                    REG_OUTPUT( mmCP_ME_CF_EVENT_SRC ); REG_OUTPUT( mmCP_ME_CF_EVENT_ADDR ); REG_OUTPUT( mmCP_ME_CF_EVENT_DATA );
+                    REG_OUTPUT( mmCP_ME_NRT_ADDR ); REG_OUTPUT( mmCP_ME_NRT_DATA ); REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_SRC );
+                    REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_ADDR ); REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_DATA ); REG_OUTPUT( mmCP_INT_CNTL );
+                    REG_OUTPUT( mmCP_INT_STATUS ); REG_OUTPUT( mmCP_INT_ACK ); REG_OUTPUT( mmCP_PFP_UCODE_ADDR );
+                    REG_OUTPUT( mmCP_PFP_UCODE_DATA ); REG_OUTPUT( mmCP_PERFMON_CNTL ); REG_OUTPUT( mmCP_PERFCOUNTER_SELECT );
+                    REG_OUTPUT( mmCP_PERFCOUNTER_LO ); REG_OUTPUT( mmCP_PERFCOUNTER_HI ); REG_OUTPUT( mmCP_BIN_MASK_LO );
+                    REG_OUTPUT( mmCP_BIN_MASK_HI ); REG_OUTPUT( mmCP_BIN_SELECT_LO ); REG_OUTPUT( mmCP_BIN_SELECT_HI );
+                    REG_OUTPUT( mmCP_NV_FLAGS_0 ); REG_OUTPUT( mmCP_NV_FLAGS_1 ); REG_OUTPUT( mmCP_NV_FLAGS_2 );
+                    REG_OUTPUT( mmCP_NV_FLAGS_3 ); REG_OUTPUT( mmCP_STATE_DEBUG_INDEX ); REG_OUTPUT( mmCP_STATE_DEBUG_DATA );
+                    REG_OUTPUT( mmCP_PROG_COUNTER ); REG_OUTPUT( mmCP_STAT ); REG_OUTPUT( mmBIOS_0_SCRATCH );
+                    REG_OUTPUT( mmBIOS_1_SCRATCH ); REG_OUTPUT( mmBIOS_2_SCRATCH ); REG_OUTPUT( mmBIOS_3_SCRATCH );
+                    REG_OUTPUT( mmBIOS_4_SCRATCH ); REG_OUTPUT( mmBIOS_5_SCRATCH ); REG_OUTPUT( mmBIOS_6_SCRATCH );
+                    REG_OUTPUT( mmBIOS_7_SCRATCH ); REG_OUTPUT( mmBIOS_8_SCRATCH ); REG_OUTPUT( mmBIOS_9_SCRATCH );
+                    REG_OUTPUT( mmBIOS_10_SCRATCH ); REG_OUTPUT( mmBIOS_11_SCRATCH ); REG_OUTPUT( mmBIOS_12_SCRATCH );
+                    REG_OUTPUT( mmBIOS_13_SCRATCH ); REG_OUTPUT( mmBIOS_14_SCRATCH ); REG_OUTPUT( mmBIOS_15_SCRATCH );
+                    REG_OUTPUT( mmCOHER_SIZE_PM4 ); REG_OUTPUT( mmCOHER_BASE_PM4 ); REG_OUTPUT( mmCOHER_STATUS_PM4 );
+                    REG_OUTPUT( mmCOHER_SIZE_HOST ); REG_OUTPUT( mmCOHER_BASE_HOST ); REG_OUTPUT( mmCOHER_STATUS_HOST );
+                    REG_OUTPUT( mmCOHER_DEST_BASE_0 ); REG_OUTPUT( mmCOHER_DEST_BASE_1 ); REG_OUTPUT( mmCOHER_DEST_BASE_2 );
+                    REG_OUTPUT( mmCOHER_DEST_BASE_3 ); REG_OUTPUT( mmCOHER_DEST_BASE_4 ); REG_OUTPUT( mmCOHER_DEST_BASE_5 );
+                    REG_OUTPUT( mmCOHER_DEST_BASE_6 ); REG_OUTPUT( mmCOHER_DEST_BASE_7 ); REG_OUTPUT( mmRB_SURFACE_INFO );
+                    REG_OUTPUT( mmRB_COLOR_INFO ); REG_OUTPUT( mmRB_DEPTH_INFO ); REG_OUTPUT( mmRB_STENCILREFMASK );
+                    REG_OUTPUT( mmRB_ALPHA_REF ); REG_OUTPUT( mmRB_COLOR_MASK ); REG_OUTPUT( mmRB_BLEND_RED );
+                    REG_OUTPUT( mmRB_BLEND_GREEN ); REG_OUTPUT( mmRB_BLEND_BLUE ); REG_OUTPUT( mmRB_BLEND_ALPHA );
+                    REG_OUTPUT( mmRB_FOG_COLOR ); REG_OUTPUT( mmRB_STENCILREFMASK_BF ); REG_OUTPUT( mmRB_DEPTHCONTROL );
+                    REG_OUTPUT( mmRB_BLENDCONTROL ); REG_OUTPUT( mmRB_COLORCONTROL ); REG_OUTPUT( mmRB_MODECONTROL );
+                    REG_OUTPUT( mmRB_COLOR_DEST_MASK ); REG_OUTPUT( mmRB_COPY_CONTROL ); REG_OUTPUT( mmRB_COPY_DEST_BASE );
+                    REG_OUTPUT( mmRB_COPY_DEST_PITCH ); REG_OUTPUT( mmRB_COPY_DEST_INFO ); REG_OUTPUT( mmRB_COPY_DEST_PIXEL_OFFSET );
+                    REG_OUTPUT( mmRB_DEPTH_CLEAR ); REG_OUTPUT( mmRB_SAMPLE_COUNT_CTL ); REG_OUTPUT( mmRB_SAMPLE_COUNT_ADDR );
+                    REG_OUTPUT( mmRB_BC_CONTROL ); REG_OUTPUT( mmRB_EDRAM_INFO ); REG_OUTPUT( mmRB_CRC_RD_PORT );
+                    REG_OUTPUT( mmRB_CRC_CONTROL ); REG_OUTPUT( mmRB_CRC_MASK ); REG_OUTPUT( mmRB_PERFCOUNTER0_SELECT );
+                    REG_OUTPUT( mmRB_PERFCOUNTER0_LOW ); REG_OUTPUT( mmRB_PERFCOUNTER0_HI ); REG_OUTPUT( mmRB_TOTAL_SAMPLES );
+                    REG_OUTPUT( mmRB_ZPASS_SAMPLES ); REG_OUTPUT( mmRB_ZFAIL_SAMPLES ); REG_OUTPUT( mmRB_SFAIL_SAMPLES );
+                    REG_OUTPUT( mmRB_DEBUG_0 ); REG_OUTPUT( mmRB_DEBUG_1 ); REG_OUTPUT( mmRB_DEBUG_2 );
+                    REG_OUTPUT( mmRB_DEBUG_3 ); REG_OUTPUT( mmRB_DEBUG_4 ); REG_OUTPUT( mmRB_FLAG_CONTROL );
+                    REG_OUTPUT( mmRB_BC_SPARES ); REG_OUTPUT( mmBC_DUMMY_CRAYRB_ENUMS ); REG_OUTPUT( mmBC_DUMMY_CRAYRB_MOREENUMS );
+
+                    default:
+                        b += sprintf( b, "%s", "UNKNOWN REGISTER OFFSET" );
+                    break;
+                }
+                // Handle string after %R
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+
+
+            default:
+            {
+                int val = va_arg( arguments, int );
+                // Standard format. Use vsprintf.
+                b += sprintf( b, buffer2, val );
+            }
+            break;
+        }
+        
+
+        c = p2;
+    }
+
+    // Add this string to all outputs
+    output = outputs;
+
+    while( output != NULL )
+    {
+        // Filter according to the flags
+        if( ( output->flags & log_flags ) == log_flags )
+        {
+            // Passed the filter. Now commit this message.
+            switch( output->type )
+            {
+                case KGSL_OUTPUT_TYPE_MEMBUF:
+                    // TODO
+                break;
+
+                case KGSL_OUTPUT_TYPE_STDOUT:
+                    // Write timestamp if enabled
+                    if( output->flags & KGSL_LOG_TIMESTAMP )
+                        printf( "[Timestamp: %d] ", kos_timestamp() );
+                    // Write process id if enabled
+                    if( output->flags & KGSL_LOG_PROCESS_ID )
+                        printf( "[Process ID: %d] ", kos_process_getid() );
+                    // Write thread id if enabled
+                    if( output->flags & KGSL_LOG_THREAD_ID )
+                        printf( "[Thread ID: %d] ", kos_thread_getid() );
+
+                    // Write the message
+                    printf( buffer );
+                break;
+                
+                case KGSL_OUTPUT_TYPE_FILE:
+                    // Write timestamp if enabled
+                    if( output->flags & KGSL_LOG_TIMESTAMP )
+                        kos_fprintf( output->file, "[Timestamp: %d] ", kos_timestamp() );
+                    // Write process id if enabled
+                    if( output->flags & KGSL_LOG_PROCESS_ID )
+                        kos_fprintf( output->file, "[Process ID: %d] ", kos_process_getid() );
+                    // Write thread id if enabled
+                    if( output->flags & KGSL_LOG_THREAD_ID )
+                        kos_fprintf( output->file, "[Thread ID: %d] ", kos_thread_getid() );
+
+                    // Write the message
+                    kos_fprintf( output->file, buffer );
+                break;
+            }
+        }
+            
+        output = output->next;
+    }
+
+    va_end( arguments );
+
+    kos_mutex_unlock( log_mutex );
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+#endif
diff --git a/drivers/mxc/amd-gpu/common/gsl_memmgr.c b/drivers/mxc/amd-gpu/common/gsl_memmgr.c
new file mode 100644
index 000000000000..75f250ae59b1
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_memmgr.c
@@ -0,0 +1,949 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl.h"
+#include "gsl_hal.h"
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMARENAPRIV_SIGNATURE_MASK         0x0000FFFF
+#define GSL_MEMARENAPRIV_APERTUREID_MASK        0xF0000000
+#define GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK    0x0F000000
+
+#define GSL_MEMARENAPRIV_SIGNATURE_SHIFT        0
+#define GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT   24
+#define GSL_MEMARENAPRIV_APERTUREID_SHIFT       28
+
+#define GSL_MEMARENA_INSTANCE_SIGNATURE         0x0000CAFE
+
+#ifdef GSL_STATS_MEM
+#define GSL_MEMARENA_STATS(x)   x
+#else
+#define GSL_MEMARENA_STATS(x)
+#endif // GSL_STATS_MEM
+
+
+/////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMARENA_LOCK()                 kos_mutex_lock(memarena->mutex)
+#define GSL_MEMARENA_UNLOCK()               kos_mutex_unlock(memarena->mutex)
+
+#define GSL_MEMARENA_SET_SIGNATURE          (memarena->priv |= ((GSL_MEMARENA_INSTANCE_SIGNATURE << GSL_MEMARENAPRIV_SIGNATURE_SHIFT) & GSL_MEMARENAPRIV_SIGNATURE_MASK))
+#define GSL_MEMARENA_SET_MMU_VIRTUALIZED    (memarena->priv |= ((mmu_virtualized << GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT) & GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK))
+#define GSL_MEMARENA_SET_ID                 (memarena->priv |= ((aperture_id << GSL_MEMARENAPRIV_APERTUREID_SHIFT) & GSL_MEMARENAPRIV_APERTUREID_MASK))
+
+#define GSL_MEMARENA_GET_SIGNATURE          ((memarena->priv & GSL_MEMARENAPRIV_SIGNATURE_MASK)   >> GSL_MEMARENAPRIV_SIGNATURE_SHIFT)
+#define GSL_MEMARENA_IS_MMU_VIRTUALIZED     ((memarena->priv & GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK) >> GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT)
+#define GSL_MEMARENA_GET_ID                 ((memarena->priv & GSL_MEMARENAPRIV_APERTUREID_MASK)  >> GSL_MEMARENAPRIV_APERTUREID_SHIFT)
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  validate
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMARENA_VALIDATE(memarena)                                 \
+    KOS_ASSERT(memarena);                                               \
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE)  \
+    {                                                                   \
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR,   \
+                        "ERROR: Memarena validation failed.\n" );       \
+        return (GSL_FAILURE);                                           \
+    }
+
+//////////////////////////////////////////////////////////////////////////////
+//  block alignment shift count
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE unsigned int
+gsl_memarena_alignmentshift(gsl_flags_t flags)
+{
+    int alignshift = ((flags & GSL_MEMFLAGS_ALIGN_MASK) >> GSL_MEMFLAGS_ALIGN_SHIFT);
+    if (alignshift == 0)
+        alignshift = 5; //  32 bytes is the minimum alignment boundary
+    return (alignshift);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  address alignment
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE unsigned int
+gsl_memarena_alignaddr(unsigned int address, int shift)
+{
+    //
+    //  the value of the returned address is guaranteed to be an even multiple
+    //  of the block alignment shift specified.
+    //
+    unsigned int alignedbaseaddr = ((address) >> shift) << shift;
+    if (alignedbaseaddr < address)
+    {
+        alignedbaseaddr += (1 << shift);
+    }
+    return (alignedbaseaddr);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//                         memory management API
+//////////////////////////////////////////////////////////////////////////////
+
+OSINLINE memblk_t*
+kgsl_memarena_getmemblknode(gsl_memarena_t *memarena)
+{
+#ifdef GSL_MEMARENA_NODE_POOL_ENABLED
+    gsl_nodepool_t  *nodepool    = memarena->nodepool;
+    memblk_t        *memblk      = NULL;
+    int             allocnewpool = 1;
+    int             i;
+
+    if (nodepool)
+    {
+        // walk through list of existing pools
+        for ( ; ; )
+        {
+            // if there is a pool with a free memblk node
+            if (nodepool->priv != (1 << GSL_MEMARENA_NODE_POOL_MAX)-1)
+            {
+                // get index of the first free memblk node
+                for (i = 0; i < GSL_MEMARENA_NODE_POOL_MAX; i++)
+                {
+                    if (((nodepool->priv >> i) & 0x1) == 0)
+                    {
+                        break;
+                    }
+                }
+
+                // mark memblk node as used
+                nodepool->priv |= 1 << i;
+
+                memblk                = &nodepool->memblk[i];
+                memblk->nodepoolindex = i;
+                memblk->blkaddr       = 0;
+                memblk->blksize       = 0;
+
+                allocnewpool = 0;
+
+                break;
+            }
+            else        
+            {
+                nodepool = nodepool->next;
+
+                if (nodepool == memarena->nodepool)
+                {
+                    // no free memblk node found
+                    break;
+                }
+            }
+        }
+    }
+
+    // if no existing pool has a free memblk node
+    if (allocnewpool)
+    {
+        // alloc new pool of memblk nodes
+        nodepool = ((gsl_nodepool_t *)kos_malloc(sizeof(gsl_nodepool_t)));
+        if (nodepool)
+        {
+            kos_memset(nodepool, 0, sizeof(gsl_nodepool_t));
+
+            if (memarena->nodepool)
+            {
+                nodepool->next                 = memarena->nodepool->next;
+                nodepool->prev                 = memarena->nodepool;
+                memarena->nodepool->next->prev = nodepool;
+                memarena->nodepool->next       = nodepool;
+            }
+            else
+            {
+                nodepool->next = nodepool;
+                nodepool->prev = nodepool;
+            }
+
+            // reposition pool head
+            memarena->nodepool = nodepool;
+
+            // mark memblk node as used
+            nodepool->priv       |= 0x1;
+
+            memblk                = &nodepool->memblk[0];
+            memblk->nodepoolindex = 0;
+        }
+    }
+
+    KOS_ASSERT(memblk);
+
+    return (memblk);
+#else
+    // unreferenced formal parameter
+    (void) memarena;
+
+    return ((memblk_t *)kos_malloc(sizeof(memblk_t)));
+#endif // GSL_MEMARENA_NODE_POOL_ENABLED
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_memarena_releasememblknode(gsl_memarena_t *memarena, memblk_t *memblk)
+{
+#ifdef GSL_MEMARENA_NODE_POOL_ENABLED
+    gsl_nodepool_t *nodepool = memarena->nodepool;
+
+    KOS_ASSERT(memblk);
+    KOS_ASSERT(nodepool);
+
+    // locate pool to which this memblk node belongs
+    while (((unsigned int) memblk) < ((unsigned int) nodepool) || 
+           ((unsigned int) memblk) > ((unsigned int) nodepool) + sizeof(gsl_nodepool_t))
+    {
+        nodepool = nodepool->prev;
+
+        KOS_ASSERT(nodepool != memarena->nodepool);
+    }
+
+    // mark memblk node as unused
+    nodepool->priv &= ~(1 << memblk->nodepoolindex);
+
+    // free pool when all its memblk nodes are unused
+    if (nodepool->priv == 0)
+    {
+        if (nodepool != nodepool->prev)
+        {
+            // reposition pool head
+            if (nodepool == memarena->nodepool)
+            {
+                memarena->nodepool = nodepool->prev;
+            }
+
+            nodepool->prev->next = nodepool->next;
+            nodepool->next->prev = nodepool->prev;
+        }
+        else
+        {
+            memarena->nodepool = NULL;
+        }
+
+        kos_free((void *)nodepool);
+    }
+    else
+    {
+        // leave pool head in last pool a memblk node was released
+        memarena->nodepool = nodepool;
+    }
+#else
+    // unreferenced formal parameter
+    (void) memarena;
+
+    kos_free((void *)memblk);
+#endif // GSL_MEMARENA_NODE_POOL_ENABLED
+}
+
+//----------------------------------------------------------------------------
+
+gsl_memarena_t*
+kgsl_memarena_create(int aperture_id, int mmu_virtualized, unsigned int hostbaseaddr, gpuaddr_t gpubaseaddr, int sizebytes)
+{
+    static int      count = 0;
+    char            name[100], id_str[2];
+    int             len;
+    gsl_memarena_t  *memarena;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_memarena_t* kgsl_memarena_create(int aperture_id=%d, gpuaddr_t gpubaseaddr=0x%08x, int sizebytes=%d)\n", aperture_id, gpubaseaddr, sizebytes );
+
+    memarena = (gsl_memarena_t *)kos_malloc(sizeof(gsl_memarena_t));
+
+    if (!memarena) 
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR,
+                        "ERROR: Memarena allocation failed.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "<-- kgsl_memarena_create. Return value: 0x%08x\n", NULL );
+        return (NULL);
+    }
+
+    kos_memset(memarena, 0, sizeof(gsl_memarena_t));
+
+    GSL_MEMARENA_SET_SIGNATURE;
+    GSL_MEMARENA_SET_MMU_VIRTUALIZED;
+    GSL_MEMARENA_SET_ID;
+
+    // define unique mutex for each memory arena instance
+    id_str[0] = (char) (count + '0');
+    id_str[1] = '\0';
+    kos_strcpy(name, "GSL_memory_arena_");
+    len = kos_strlen(name);
+    kos_strcpy(&name[len], id_str);
+
+    memarena->mutex = kos_mutex_create(name);
+
+    // set up the memory arena
+    memarena->hostbaseaddr = hostbaseaddr;
+    memarena->gpubaseaddr  = gpubaseaddr;
+    memarena->sizebytes    = sizebytes;
+
+    // allocate a memory block in free list which represents all memory in arena
+    memarena->freelist.head          = kgsl_memarena_getmemblknode(memarena);
+    memarena->freelist.head->blkaddr = 0;
+    memarena->freelist.head->blksize = memarena->sizebytes;
+    memarena->freelist.head->next    = memarena->freelist.head;
+    memarena->freelist.head->prev    = memarena->freelist.head;
+    memarena->freelist.allocrover    = memarena->freelist.head;
+    memarena->freelist.freerover     = memarena->freelist.head;
+
+    count++;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_create. Return value: 0x%08x\n", memarena );
+
+    return (memarena);
+}
+
+//----------------------------------------------------------------------------
+
+int         
+kgsl_memarena_destroy(gsl_memarena_t *memarena)
+{
+    int       status = GSL_SUCCESS;
+    memblk_t  *p, *next;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_destroy(gsl_memarena_t *memarena=0x%08x)\n", memarena );
+
+    GSL_MEMARENA_VALIDATE(memarena);
+
+    GSL_MEMARENA_LOCK();
+
+#ifdef _DEBUG
+    // memory leak check
+    if (memarena->freelist.head->blksize != memarena->sizebytes)
+    {
+        if (GSL_MEMARENA_GET_ID == GSL_APERTURE_EMEM)
+        {
+            // external memory leak detected
+            kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL,
+                            "ERROR: External memory leak detected.\n" );
+            return (GSL_FAILURE);
+        }
+    }
+#endif // _DEBUG
+
+    p = memarena->freelist.head;
+    do
+    {
+        next = p->next;
+        kgsl_memarena_releasememblknode(memarena, p);
+        p = next;
+    } while (p != memarena->freelist.head);
+
+    GSL_MEMARENA_UNLOCK();
+
+    if (memarena->mutex)
+    {
+        kos_mutex_free(memarena->mutex);
+    }
+
+    kos_free((void *)memarena);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_destroy. Return value: %B\n", GSL_SUCCESS );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_memarena_isvirtualized(gsl_memarena_t *memarena)
+{
+    // mmu virtualization enabled
+    return (GSL_MEMARENA_IS_MMU_VIRTUALIZED);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_memarena_checkconsistency(gsl_memarena_t *memarena)
+{
+    memblk_t *p;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_checkconsistency(gsl_memarena_t *memarena=0x%08x)\n", memarena );
+
+    // go through list of free blocks and make sure there are no detectable errors
+
+    p = memarena->freelist.head;
+    do
+    {
+        if (p->next->blkaddr != memarena->freelist.head->blkaddr)
+        {
+            if (p->prev->next->blkaddr  != p->blkaddr || 
+                p->next->prev->blkaddr  != p->blkaddr ||
+                p->blkaddr + p->blksize >= p->next->blkaddr)
+            {
+                KOS_ASSERT(0);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkconsistency. Return value: %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+        }
+        p = p->next;
+
+    } while (p != memarena->freelist.head);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkconsistency. Return value: %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int             
+kgsl_memarena_querystats(gsl_memarena_t *memarena, gsl_memarena_stats_t *stats)
+{
+#ifdef GSL_STATS_MEM
+    KOS_ASSERT(stats);
+    GSL_MEMARENA_VALIDATE(memarena);
+
+    kos_memcpy(stats, &memarena->stats, sizeof(gsl_memarena_stats_t));
+    
+    return (GSL_SUCCESS);
+#else
+    // unreferenced formal parameters
+    (void) memarena;
+    (void) stats;
+
+    return (GSL_FAILURE_NOTSUPPORTED);
+#endif // GSL_STATS_MEM
+}
+
+//----------------------------------------------------------------------------
+
+int         
+kgsl_memarena_checkfreeblock(gsl_memarena_t *memarena, int bytesneeded)
+{
+    memblk_t  *p;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_checkfreeblock(gsl_memarena_t *memarena=0x%08x, int bytesneeded=%d)\n", memarena, bytesneeded );
+
+    GSL_MEMARENA_VALIDATE(memarena);
+
+    if (bytesneeded < 1)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Illegal number of bytes needed.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    GSL_MEMARENA_LOCK();
+
+    p = memarena->freelist.head;
+    do
+    {
+        if (p->blksize >= (unsigned int)bytesneeded)
+        {
+            kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_SUCCESS );
+            return (GSL_SUCCESS);
+        }
+
+        p = p->next;
+    } while (p != memarena->freelist.head);
+
+    GSL_MEMARENA_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_FAILURE );
+
+    return (GSL_FAILURE);
+}
+
+//----------------------------------------------------------------------------
+
+int 
+kgsl_memarena_alloc(gsl_memarena_t *memarena, gsl_flags_t flags, int size, gsl_memdesc_t *memdesc)
+{
+    int           result = GSL_FAILURE_OUTOFMEM;
+    memblk_t      *ptrfree, *ptrlast, *p;
+    unsigned int  blksize;
+    unsigned int  baseaddr, alignedbaseaddr, alignfragment;
+    int           freeblk, alignmentshift;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_alloc(gsl_memarena_t *memarena=0x%08x, gsl_flags_t flags=0x%08x, int size=%d, gsl_memdesc_t *memdesc=%M)\n", memarena, flags, size, memdesc );
+
+    GSL_MEMARENA_VALIDATE(memarena);
+
+    if (size <= 0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid size for memory allocation.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_alloc. Return value: %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    //
+    // go through the list of free blocks.  check to find block which can satisfy the alloc request
+    //
+    // if no block can satisfy the alloc request this implies that the memory is too fragmented
+    // and the requestor needs to free up other memory blocks and re-request the allocation
+    //
+    // if we do find a block that can satisfy the alloc request then reduce the size of free block
+    // by blksize and return the address after allocating the memory.  if the free block size becomes
+    // 0 then remove this node from the free list
+    //
+    // there would be no node on the free list if all available memory were to be allocated.  
+    // handling an empty list would require executing error checking code in the main branch which 
+    // is not desired.  instead, the free list will have at least one node at all times. This node 
+    // could have a block size of zero
+    //
+    // we use a next fit allocation mechanism that uses a roving pointer on a circular free block list. 
+    // the pointer is advanced along the chain when searching for a fit. Thus each allocation begins
+    // looking where the previous one finished. 
+    //
+
+    // when allocating from external memory aperture, round up size of requested block to multiple of page size if needed
+    if (GSL_MEMARENA_GET_ID == GSL_APERTURE_EMEM)
+    {
+        if ((flags & GSL_MEMFLAGS_FORCEPAGESIZE) || GSL_MEMARENA_IS_MMU_VIRTUALIZED)
+        {
+            if (size & (GSL_PAGESIZE-1))
+            {
+                size = ((size >> GSL_PAGESIZE_SHIFT) + 1) << GSL_PAGESIZE_SHIFT;
+            }
+        }
+    }
+
+    // determine shift count for alignment requested
+    alignmentshift = gsl_memarena_alignmentshift(flags);
+
+    // adjust size of requested block to include alignment
+    blksize = (unsigned int)((size + ((1 << alignmentshift) - 1)) >> alignmentshift) << alignmentshift;
+
+    GSL_MEMARENA_LOCK();
+
+    // check consistency, debug only
+    KGSL_DEBUG(GSL_DBGFLAGS_MEMMGR, kgsl_memarena_checkconsistency(memarena));
+
+    ptrfree = memarena->freelist.allocrover;
+    ptrlast = memarena->freelist.head->prev;
+    freeblk = 0;
+
+    do
+    { 
+        // align base address
+        baseaddr = ptrfree->blkaddr + memarena->gpubaseaddr;
+        alignedbaseaddr = gsl_memarena_alignaddr(baseaddr, alignmentshift);
+       
+        alignfragment = alignedbaseaddr - baseaddr;
+
+        if (ptrfree->blksize >= blksize + alignfragment)
+        {
+            result  = GSL_SUCCESS;
+            freeblk = 1;
+
+            memdesc->gpuaddr = alignedbaseaddr;
+            memdesc->hostptr = kgsl_memarena_gethostptr(memarena, memdesc->gpuaddr);
+            memdesc->size    = blksize;
+
+            if (alignfragment > 0)
+            {
+                // insert new node to handle newly created (small) fragment
+                p = kgsl_memarena_getmemblknode(memarena);
+                p->blkaddr = ptrfree->blkaddr;
+                p->blksize = alignfragment;
+
+                p->next = ptrfree;
+                p->prev = ptrfree->prev;
+                ptrfree->prev->next = p;
+                ptrfree->prev       = p;
+
+                if (ptrfree == memarena->freelist.head)
+                {
+                    memarena->freelist.head = p;
+                }
+            }
+
+            ptrfree->blkaddr += alignfragment + blksize;
+            ptrfree->blksize -= alignfragment + blksize;
+
+            memarena->freelist.allocrover = ptrfree;
+
+            if (ptrfree->blksize == 0 && ptrfree != ptrlast)
+            {
+                ptrfree->prev->next = ptrfree->next;
+                ptrfree->next->prev = ptrfree->prev;
+                if (ptrfree == memarena->freelist.head)
+                {
+                    memarena->freelist.head = ptrfree->next;
+                }
+                if (ptrfree == memarena->freelist.allocrover)
+                {
+                    memarena->freelist.allocrover = ptrfree->next;
+                }
+                if (ptrfree == memarena->freelist.freerover)
+                {
+                    memarena->freelist.freerover = ptrfree->prev;
+                }
+                p       = ptrfree;
+                ptrfree = ptrfree->prev;
+                kgsl_memarena_releasememblknode(memarena, p);
+            }
+        }
+
+        ptrfree = ptrfree->next;
+
+    } while (!freeblk && ptrfree != memarena->freelist.allocrover);
+
+    GSL_MEMARENA_UNLOCK();
+
+    if (result == GSL_SUCCESS)
+    {
+        GSL_MEMARENA_STATS(
+        {   
+            int i = 0;
+            while (memdesc->size >> (GSL_PAGESIZE_SHIFT + i))
+            {
+                i++;
+            }
+            i = i > (GSL_MEMARENA_PAGE_DIST_MAX-1) ? (GSL_MEMARENA_PAGE_DIST_MAX-1) : i;
+            memarena->stats.allocs_pagedistribution[i]++;
+        });
+
+        GSL_MEMARENA_STATS(memarena->stats.allocs_success++);
+    }
+    else
+    {
+        GSL_MEMARENA_STATS(memarena->stats.allocs_fail++);
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_alloc. Return value: %B\n", result );
+        
+    return (result);
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_memarena_free(gsl_memarena_t *memarena, gsl_memdesc_t *memdesc)
+{
+    //
+    // request to free a malloc'ed block from the memory arena
+    // add this block to the free list
+    // adding a block to the free list requires the following:
+    // going through the list of free blocks to decide where to add this free block (based on address)
+    // coalesce free blocks
+    //
+    memblk_t      *ptrfree, *ptrend, *p;
+    int           mallocfreeblk, clockwise;
+    unsigned int  addrtofree;
+    
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> void kgsl_memarena_free(gsl_memarena_t *memarena=0x%08x, gsl_memdesc_t *memdesc=%M)\n", memarena, memdesc );
+
+    KOS_ASSERT(memarena);
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" );
+        return;
+    }
+
+    // check size of malloc'ed block 
+    if (memdesc->size <= 0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Illegal size for the memdesc.\n" );
+        KOS_ASSERT(0);
+
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" );
+        return;
+    }
+
+    // check address range
+    KOS_ASSERT( memarena->gpubaseaddr <= memdesc->gpuaddr);
+    KOS_ASSERT((memarena->gpubaseaddr + memarena->sizebytes) >= memdesc->gpuaddr + memdesc->size);
+
+    GSL_MEMARENA_LOCK();
+
+    // check consistency of memory map, debug only
+    KGSL_DEBUG(GSL_DBGFLAGS_MEMMGR, kgsl_memarena_checkconsistency(memarena));
+
+    addrtofree    = memdesc->gpuaddr - memarena->gpubaseaddr;
+    mallocfreeblk = 1;
+
+    if (addrtofree < memarena->freelist.head->blkaddr)
+    {
+        // add node to head of free list
+
+        if (addrtofree + memdesc->size == memarena->freelist.head->blkaddr)
+        {
+            memarena->freelist.head->blkaddr  = addrtofree;
+            memarena->freelist.head->blksize += memdesc->size;
+
+            mallocfreeblk = 0;
+        }
+
+        ptrfree = memarena->freelist.head->prev;
+    }
+    else if (addrtofree >= memarena->freelist.head->prev->blkaddr)
+    {
+        // add node to tail of free list
+
+        ptrfree = memarena->freelist.head->prev;
+
+        if (ptrfree->blkaddr + ptrfree->blksize == addrtofree)
+        {
+            ptrfree->blksize += memdesc->size;
+
+            mallocfreeblk = 0;
+        }
+    }
+    else
+    {
+        // determine range of free list nodes to traverse and orientation in which to traverse them
+        // keep this code segment unrolled for performance reasons!
+        if (addrtofree > memarena->freelist.freerover->blkaddr)
+        {
+            if (addrtofree - memarena->freelist.freerover->blkaddr < memarena->freelist.head->prev->blkaddr - addrtofree)
+            {
+                ptrfree   = memarena->freelist.freerover;       // rover
+                ptrend    = memarena->freelist.head->prev;      // tail
+                clockwise = 1;
+            }
+            else
+            {
+                ptrfree   = memarena->freelist.head->prev->prev; // tail
+                ptrend    = memarena->freelist.freerover->prev;  // rover
+                clockwise = 0;
+            }
+        }
+        else
+        {
+            if (addrtofree - memarena->freelist.head->blkaddr < memarena->freelist.freerover->blkaddr - addrtofree)
+            {
+                ptrfree   = memarena->freelist.head;            // head
+                ptrend    = memarena->freelist.freerover;       // rover
+                clockwise = 1;
+            }
+            else
+            {
+                ptrfree   = memarena->freelist.freerover->prev; // rover
+                ptrend    = memarena->freelist.head->prev;      // head
+                clockwise = 0;
+            }
+        }
+
+        // traverse the nodes
+        do
+        {
+            if ((addrtofree >= ptrfree->blkaddr + ptrfree->blksize) && 
+                (addrtofree + memdesc->size <= ptrfree->next->blkaddr))
+            {
+                if (addrtofree == ptrfree->blkaddr + ptrfree->blksize)
+                {
+                    memblk_t  *next;
+
+                    ptrfree->blksize += memdesc->size;
+                    next              = ptrfree->next;
+
+                    if (ptrfree->blkaddr + ptrfree->blksize == next->blkaddr)
+                    {
+                        ptrfree->blksize += next->blksize;
+                        ptrfree->next     = next->next;
+                        next->next->prev  = ptrfree;
+
+                        if (next == memarena->freelist.allocrover)
+                        {
+                            memarena->freelist.allocrover = ptrfree;
+                        }
+
+                        kgsl_memarena_releasememblknode(memarena, next);
+                    }
+
+                    mallocfreeblk = 0;
+                }
+                else if (addrtofree + memdesc->size == ptrfree->next->blkaddr)
+                {
+                    ptrfree->next->blkaddr  = addrtofree;
+                    ptrfree->next->blksize += memdesc->size;
+
+                    mallocfreeblk  = 0;
+                }
+
+                break;
+            }
+
+            if (clockwise)
+            {
+                ptrfree = ptrfree->next;
+            }
+            else
+            {
+                ptrfree = ptrfree->prev;
+            }
+
+        } while (ptrfree != ptrend);
+    }
+
+    // this free block could not be coalesced, so create a new free block
+    // and add it to the free list in the memory arena
+    if (mallocfreeblk)
+    {
+        p = kgsl_memarena_getmemblknode(memarena);
+        p->blkaddr = addrtofree;
+        p->blksize = memdesc->size;
+
+        p->next             = ptrfree->next;
+        p->prev             = ptrfree;
+        ptrfree->next->prev = p;
+        ptrfree->next       = p;
+
+        if (p->blkaddr < memarena->freelist.head->blkaddr)
+        {
+            memarena->freelist.head = p;
+        }
+
+        memarena->freelist.freerover = p;
+    }
+    else
+    {
+        memarena->freelist.freerover = ptrfree;
+    }
+
+    GSL_MEMARENA_UNLOCK();
+
+    GSL_MEMARENA_STATS(
+    {   
+        int i = 0;
+        while (memdesc->size >> (GSL_PAGESIZE_SHIFT + i))
+        {
+            i++;
+        }
+        i = i > (GSL_MEMARENA_PAGE_DIST_MAX-1) ? (GSL_MEMARENA_PAGE_DIST_MAX-1) : i;
+        memarena->stats.frees_pagedistribution[i]++;
+    });
+
+    GSL_MEMARENA_STATS(memarena->stats.frees++);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+void *          
+kgsl_memarena_gethostptr(gsl_memarena_t *memarena, gpuaddr_t gpuaddr)
+{
+    //
+    // get the host mapped address for a hardware device address
+    //
+
+    void  *hostptr = NULL;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> void* kgsl_memarena_gethostptr(gsl_memarena_t *memarena=0x%08x, gpuaddr_t gpuaddr=0x%08x)\n", memarena, gpuaddr );
+
+    KOS_ASSERT(memarena);
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_gethostptr. Return value: 0x%08x\n", NULL );
+        return (NULL);
+    }
+
+    // check address range
+    KOS_ASSERT(gpuaddr >= memarena->gpubaseaddr);
+    KOS_ASSERT(gpuaddr <  memarena->gpubaseaddr + memarena->sizebytes);
+
+    hostptr = (void *)((gpuaddr - memarena->gpubaseaddr) + memarena->hostbaseaddr);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_gethostptr. Return value: 0x%08x\n", hostptr );
+
+    return (hostptr);
+}
+
+//----------------------------------------------------------------------------
+
+gpuaddr_t           
+kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena, void *hostptr)
+{
+    //
+    // get the hardware device address for a host mapped address
+    //
+
+    gpuaddr_t  gpuaddr = 0;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena=0x%08x, void *hostptr=0x%08x)\n", memarena, hostptr );
+
+    KOS_ASSERT(memarena);
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getgpuaddr. Return value: 0x%08x\n", 0 );
+        return (0);
+    }
+
+    // check address range
+    KOS_ASSERT(hostptr >= (void *)memarena->hostbaseaddr);
+    KOS_ASSERT(hostptr <  (void *)(memarena->hostbaseaddr + memarena->sizebytes));
+    
+    gpuaddr = ((unsigned int)hostptr - memarena->hostbaseaddr) + memarena->gpubaseaddr;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getgpuaddr. Return value: 0x%08x\n", gpuaddr );
+
+    return (gpuaddr);
+}
+
+//----------------------------------------------------------------------------
+
+unsigned int    
+kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena, gsl_flags_t flags)
+{
+    memblk_t      *ptrfree;
+    unsigned int  blocksize, largestblocksize = 0;
+    int           alignmentshift; 
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> unsigned int kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena=0x%08x, gsl_flags_t flags=0x%08x)\n", memarena, flags );
+
+    KOS_ASSERT(memarena);
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE) 
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getlargestfreeblock. Return value: %d\n", 0 );
+        return (0);
+    }
+
+    // determine shift count for alignment requested
+    alignmentshift = gsl_memarena_alignmentshift(flags);
+
+    GSL_MEMARENA_LOCK();
+
+    ptrfree = memarena->freelist.head;
+
+    do
+    {
+        blocksize = ptrfree->blksize - (ptrfree->blkaddr - ((ptrfree->blkaddr >> alignmentshift) << alignmentshift));
+
+        if (blocksize > largestblocksize)
+        {
+            largestblocksize = blocksize;
+        }
+
+        ptrfree = ptrfree->next;
+
+    } while (ptrfree != memarena->freelist.head);
+
+    GSL_MEMARENA_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getlargestfreeblock. Return value: %d\n", largestblocksize );
+
+    return (largestblocksize);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_mmu.c b/drivers/mxc/amd-gpu/common/gsl_mmu.c
new file mode 100644
index 000000000000..310677d926f0
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_mmu.c
@@ -0,0 +1,1036 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+// ---------
+// pte debug
+// ---------
+
+typedef struct _gsl_pte_debug_t
+{
+    unsigned int    write     :1;
+    unsigned int    read      :1;
+    unsigned int    reserved  :10;
+    unsigned int    phyaddr   :20;
+} gsl_pte_debug_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_PT_ENTRY_SIZEBYTES              4
+#define GSL_PT_EXTRA_ENTRIES                16
+
+#define GSL_PT_PAGE_WRITE                   0x00000001
+#define GSL_PT_PAGE_READ                    0x00000002
+
+#define GSL_PT_PAGE_AP_MASK                 0x00000003
+#define GSL_PT_PAGE_ADDR_MASK               ~(GSL_PAGESIZE-1)
+
+#define GSL_MMUFLAGS_TLBFLUSH               0x80000000
+
+#define GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS   (sizeof(unsigned char) * 8)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// constants
+//////////////////////////////////////////////////////////////////////////////
+const unsigned int GSL_PT_PAGE_AP[4] = {(GSL_PT_PAGE_READ | GSL_PT_PAGE_WRITE), GSL_PT_PAGE_READ, GSL_PT_PAGE_WRITE, 0};
+
+
+/////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+
+#define GSL_PT_ENTRY_GET(va)                ((va - pagetable->va_base) >> GSL_PAGESIZE_SHIFT)
+#define GSL_PT_VIRT_GET(pte)                (pagetable->va_base + (pte * GSL_PAGESIZE))
+
+#define GSL_PT_MAP_APDEFAULT                GSL_PT_PAGE_AP[0]
+
+#define GSL_PT_MAP_GET(pte)                 *((unsigned int *)(((unsigned int)pagetable->base.hostptr) + ((pte) * GSL_PT_ENTRY_SIZEBYTES)))
+#define GSL_PT_MAP_GETADDR(pte)             (GSL_PT_MAP_GET(pte) & GSL_PT_PAGE_ADDR_MASK)
+
+#define GSL_PT_MAP_DEBUG(pte)               ((gsl_pte_debug_t*) &GSL_PT_MAP_GET(pte))
+
+#define GSL_PT_MAP_SETBITS(pte, bits)       (GSL_PT_MAP_GET(pte) |= (((unsigned int) bits) & GSL_PT_PAGE_AP_MASK))
+#define GSL_PT_MAP_SETADDR(pte, pageaddr)   (GSL_PT_MAP_GET(pte)  = (GSL_PT_MAP_GET(pte) & ~GSL_PT_PAGE_ADDR_MASK) | (((unsigned int) pageaddr) & GSL_PT_PAGE_ADDR_MASK))
+
+#define GSL_PT_MAP_RESET(pte)               (GSL_PT_MAP_GET(pte)  = 0)
+#define GSL_PT_MAP_RESETBITS(pte, bits)     (GSL_PT_MAP_GET(pte) &= ~(((unsigned int) bits) & GSL_PT_PAGE_AP_MASK))
+
+#define GSL_MMU_VIRT_TO_PAGE(va)            *((unsigned int *)(pagetable->base.gpuaddr + (GSL_PT_ENTRY_GET(va) * GSL_PT_ENTRY_SIZEBYTES)))
+#define GSL_MMU_VIRT_TO_PHYS(va)            ((GSL_MMU_VIRT_TO_PAGE(va) & GSL_PT_PAGE_ADDR_MASK) + (va & (GSL_PAGESIZE-1)))
+
+#define GSL_TLBFLUSH_FILTER_GET(superpte)       *((unsigned char *)(((unsigned int)mmu->tlbflushfilter.base) + (superpte / GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS)))
+#define GSL_TLBFLUSH_FILTER_SETDIRTY(superpte)  (GSL_TLBFLUSH_FILTER_GET((superpte)) |= 1 << (superpte % GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS))
+#define GSL_TLBFLUSH_FILTER_ISDIRTY(superpte)   (GSL_TLBFLUSH_FILTER_GET((superpte)) & (1 << (superpte % GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS)))
+#define GSL_TLBFLUSH_FILTER_RESET()             kos_memset(mmu->tlbflushfilter.base, 0, mmu->tlbflushfilter.size)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// process index in pagetable object table
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE int
+kgsl_mmu_getprocessindex(unsigned int pid, int *pindex)
+{
+    int status = GSL_SUCCESS;
+#ifdef GSL_MMU_PAGETABLE_PERPROCESS
+    if (kgsl_driver_getcallerprocessindex(pid, pindex) != GSL_SUCCESS)
+    {
+        status = GSL_FAILURE;
+    }
+#else
+    (void) pid;      // unreferenced formal parameter
+    *pindex = 0;
+#endif // GSL_MMU_PAGETABLE_PERPROCESS
+    return (status);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// pagetable object for current caller process
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE gsl_pagetable_t*
+kgsl_mmu_getpagetableobject(gsl_mmu_t *mmu, unsigned int pid)
+{
+    int pindex = 0;
+    if (kgsl_mmu_getprocessindex(pid, &pindex) == GSL_SUCCESS)
+    {
+        return (mmu->pagetable[pindex]);
+    }
+    else
+    {
+        return (NULL);
+    }
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  functions
+//////////////////////////////////////////////////////////////////////////////
+
+void
+kgsl_mh_intrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_mmu_t     *mmu = (gsl_mmu_t *) cookie;
+    unsigned int   devindex = mmu->device->id-1;        // device_id is 1 based
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> void kgsl_mh_ntrcallback(gsl_intrid_t id=%I, void *cookie=0x%08x)\n", id, cookie );
+
+    // error condition interrupt
+    if (id == gsl_cfg_mh_intr[devindex].AXI_READ_ERROR  ||
+        id == gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR ||
+        id == gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT)
+    {
+        mmu->device->ftbl.device_destroy(mmu->device);
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mh_intrcallback.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _DEBUG
+static void
+kgsl_mmu_debug(gsl_mmu_t *mmu, gsl_mmu_debug_t *regs)
+{
+    unsigned int  devindex = mmu->device->id-1;         // device_id is 1 based
+
+    kos_memset(regs, 0, sizeof(gsl_mmu_debug_t));
+
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].CONFIG,     &regs->config);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].MPU_BASE,   &regs->mpu_base);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].MPU_END,    &regs->mpu_end);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].VA_RANGE,   &regs->va_range);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].PT_BASE,    &regs->pt_base);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].PAGE_FAULT, &regs->page_fault);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].TRAN_ERROR, &regs->trans_error);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].INVALIDATE, &regs->invalidate);
+}
+#endif
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_checkconsistency(gsl_pagetable_t *pagetable)
+{
+    unsigned int     pte;
+    unsigned int     data;
+    gsl_pte_debug_t  *pte_debug;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_mmu_checkconsistency(gsl_pagetable_t *pagetable=0x%08x)\n", pagetable );
+
+    if (pagetable->last_superpte % GSL_PT_SUPER_PTE != 0)
+    {
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_checkconsistency. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // go through page table and make sure there are no detectable errors
+    pte = 0;
+    while (pte < pagetable->max_entries)
+    {
+        pte_debug = GSL_PT_MAP_DEBUG(pte);
+
+        if (GSL_PT_MAP_GETADDR(pte) != 0)
+        {
+            // pte is in use
+
+            // access first couple bytes of a page
+            data = *((unsigned int *)GSL_PT_VIRT_GET(pte));
+        }
+
+        pte++;
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_checkconsistency. Return value %B\n", GSL_SUCCESS );
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_destroypagetableobject(gsl_mmu_t *mmu, unsigned int pid)
+{
+    gsl_deviceid_t   tmp_id;
+    gsl_device_t     *tmp_device;
+    int              pindex;
+    gsl_pagetable_t  *pagetable;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> gsl_pagetable_t* kgsl_mmu_destroypagetableobject(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid );
+
+    if (kgsl_mmu_getprocessindex(pid, &pindex) != GSL_SUCCESS)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_destroypagetableobject. Return value 0x%08x\n", GSL_SUCCESS );
+        return (GSL_FAILURE);
+    }
+
+    pagetable = mmu->pagetable[pindex];
+
+    // if pagetable object exists for current "current device mmu"/"current caller process" combination
+    if (pagetable)
+    {
+        // no more "device mmu"/"caller process" combinations attached to current pagetable object
+        if (pagetable->refcnt == 0)
+        {
+#ifdef _DEBUG
+            // memory leak check
+            if (pagetable->last_superpte != 0 || GSL_PT_MAP_GETADDR(pagetable->last_superpte))
+            {
+                /* many dumpx test cases forcefully exit, and thus trigger this assert. */
+                /* Because it is an annoyance for HW guys, it is disabled for dumpx */
+                if(!gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX)
+                {
+                    KOS_ASSERT(0);
+                    return (GSL_FAILURE);
+                }
+            }
+#endif // _DEBUG
+
+            if (pagetable->base.gpuaddr)
+            {
+                kgsl_sharedmem_free0(&pagetable->base, GSL_CALLER_PROCESSID_GET());
+            }
+
+            kos_free(pagetable);
+
+            // clear pagetable object reference for all "device mmu"/"current caller process" combinations
+            for (tmp_id = GSL_DEVICE_ANY + 1; tmp_id <= GSL_DEVICE_MAX; tmp_id++)
+            {
+                tmp_device = &gsl_driver.device[tmp_id-1];
+
+                if (tmp_device->mmu.flags & GSL_FLAGS_STARTED)
+                {
+                    tmp_device->mmu.pagetable[pindex] = NULL;
+                }
+            }
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_destroypagetableobject. Return value 0x%08x\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+gsl_pagetable_t*
+kgsl_mmu_createpagetableobject(gsl_mmu_t *mmu, unsigned int pid)
+{
+    //
+    // create pagetable object for "current device mmu"/"current caller
+    // process" combination. If none exists, setup a new pagetable object.
+    //
+    int              status         = GSL_SUCCESS;
+    gsl_pagetable_t  *tmp_pagetable = NULL;
+    gsl_deviceid_t   tmp_id;
+    gsl_device_t     *tmp_device;
+    int              pindex;
+    gsl_flags_t      flags;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> gsl_pagetable_t* kgsl_mmu_createpagetableobject(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid );
+
+    status = kgsl_mmu_getprocessindex(pid, &pindex);
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", NULL );
+        return (NULL);
+    }
+    // if pagetable object does not already exists for "current device mmu"/"current caller process" combination
+    if (!mmu->pagetable[pindex])
+    {
+        // then, check if pagetable object already exists for any "other device mmu"/"current caller process" combination
+        for (tmp_id = GSL_DEVICE_ANY + 1; tmp_id <= GSL_DEVICE_MAX; tmp_id++)
+        {
+            tmp_device = &gsl_driver.device[tmp_id-1];
+
+            if (tmp_device->mmu.flags & GSL_FLAGS_STARTED)
+            {
+                if (tmp_device->mmu.pagetable[pindex])
+                {
+                    tmp_pagetable = tmp_device->mmu.pagetable[pindex];
+                    break;
+                }
+            }
+        }
+
+        // pagetable object exists
+        if (tmp_pagetable)
+        {
+            KOS_ASSERT(tmp_pagetable->va_base  == mmu->va_base);
+            KOS_ASSERT(tmp_pagetable->va_range == mmu->va_range);
+
+            // set pagetable object reference
+            mmu->pagetable[pindex] = tmp_pagetable;
+        }
+        // create new pagetable object
+        else
+        {
+            mmu->pagetable[pindex] = (void *)kos_malloc(sizeof(gsl_pagetable_t));
+            if (!mmu->pagetable[pindex])
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate pagetable object.\n" );
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", NULL );
+                return (NULL);
+            }
+
+            kos_memset(mmu->pagetable[pindex], 0, sizeof(gsl_pagetable_t));
+
+			mmu->pagetable[pindex]->pid           = pid;
+            mmu->pagetable[pindex]->refcnt        = 0;
+            mmu->pagetable[pindex]->va_base       = mmu->va_base;
+            mmu->pagetable[pindex]->va_range      = mmu->va_range;
+            mmu->pagetable[pindex]->last_superpte = 0;
+            mmu->pagetable[pindex]->max_entries   = (mmu->va_range >> GSL_PAGESIZE_SHIFT) + GSL_PT_EXTRA_ENTRIES;
+
+            // allocate page table memory
+            flags  = (GSL_MEMFLAGS_ALIGN4K | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST);
+            status = kgsl_sharedmem_alloc0(mmu->device->id, flags, mmu->pagetable[pindex]->max_entries * GSL_PT_ENTRY_SIZEBYTES, &mmu->pagetable[pindex]->base);
+
+            if (status == GSL_SUCCESS)
+            {
+                // reset page table entries
+                kgsl_sharedmem_set0(&mmu->pagetable[pindex]->base, 0, 0, mmu->pagetable[pindex]->base.size);
+
+                KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MMU_TBLADDR, mmu->pagetable[pindex]->base.gpuaddr, 0, mmu->pagetable[pindex]->base.size, "kgsl_mmu_init"));
+            }
+            else
+            {
+                kgsl_mmu_destroypagetableobject(mmu, pid);
+            }
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", mmu->pagetable[pindex] );
+
+    return (mmu->pagetable[pindex]);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_setpagetable(gsl_device_t *device, unsigned int pid)
+{
+    //
+    // set device mmu to use current caller process's page table
+    //
+    int              status   = GSL_SUCCESS;
+    unsigned int     devindex = device->id-1;       // device_id is 1 based
+    gsl_mmu_t        *mmu     = &device->mmu;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_pagetable_t* kgsl_mmu_setpagetable(gsl_device_t *device=0x%08x)\n", device );
+
+    if (mmu->flags & GSL_FLAGS_STARTED)
+    {
+#ifdef GSL_MMU_PAGETABLE_PERPROCESS
+		// page table not current, then setup mmu to use new specified page table
+		if (mmu->hwpagetable->pid != pid)
+		{
+			gsl_pagetable_t  *pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+			if (pagetable)
+			{
+				mmu->hwpagetable = pagetable;
+
+				// flag tlb flush	
+				mmu->flags |= GSL_MMUFLAGS_TLBFLUSH;
+
+				status = mmu->device->ftbl.mmu_setpagetable(mmu->device, gsl_cfg_mmu_reg[devindex].PT_BASE, pagetable->base.gpuaddr, pid);
+
+				GSL_MMU_STATS(mmu->stats.pt.switches++);
+			}
+			else
+			{
+				status = GSL_FAILURE;
+			}
+		}
+#endif // GSL_MMU_PAGETABLE_PERPROCESS
+
+        // if needed, invalidate device specific tlb
+		if ((mmu->flags & GSL_MMUFLAGS_TLBFLUSH) && status == GSL_SUCCESS)
+        {
+            mmu->flags &= ~GSL_MMUFLAGS_TLBFLUSH;
+
+            GSL_TLBFLUSH_FILTER_RESET();
+
+			status = mmu->device->ftbl.mmu_tlbinvalidate(mmu->device, gsl_cfg_mmu_reg[devindex].INVALIDATE, pid);
+
+			GSL_MMU_STATS(mmu->stats.tlbflushes++);
+		}
+	}
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_setpagetable. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_init(gsl_device_t *device)
+{
+    //
+    // intialize device mmu
+    //
+    // call this with the global lock held
+    //
+    int              status;
+    gsl_flags_t      flags;
+    gsl_pagetable_t  *pagetable;
+    unsigned int     devindex = device->id-1;       // device_id is 1 based
+    gsl_mmu_t        *mmu     = &device->mmu;
+#ifdef _DEBUG
+    gsl_mmu_debug_t  regs;
+#endif // _DEBUG
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_mmu_init(gsl_device_t *device=0x%08x)\n", device );
+
+    if (device->ftbl.mmu_tlbinvalidate == NULL || device->ftbl.mmu_setpagetable == NULL ||
+        !(device->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    if (mmu->flags & GSL_FLAGS_INITIALIZED0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_INFO, "MMU already initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    // setup backward reference
+    mmu->device = device;
+
+    // disable MMU when running in safe mode
+    if (device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        mmu->config = 0x00000000;
+    }
+
+    // setup MMU and sub-client behavior
+    device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].CONFIG, mmu->config);
+
+    // enable axi interrupts
+    kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR, kgsl_mh_intrcallback, (void *) mmu);
+    kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR, kgsl_mh_intrcallback, (void *) mmu);
+    kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR);
+    kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR);
+
+    mmu->refcnt  = 0;
+    mmu->flags  |= GSL_FLAGS_INITIALIZED0;
+
+    // MMU enabled
+    if (mmu->config & 0x1)
+    {
+        // idle device
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+
+        // make sure aligned to pagesize
+        KOS_ASSERT((mmu->mpu_base & ((1 << GSL_PAGESIZE_SHIFT)-1)) == 0);
+        KOS_ASSERT(((mmu->mpu_base + mmu->mpu_range) & ((1 << GSL_PAGESIZE_SHIFT)-1)) == 0);
+
+        // define physical memory range accessible by the core
+        device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].MPU_BASE, mmu->mpu_base);
+        device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].MPU_END,  mmu->mpu_base + mmu->mpu_range);
+
+        // enable page fault interrupt
+        kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT, kgsl_mh_intrcallback, (void *) mmu);
+        kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT);
+
+        mmu->flags |= GSL_FLAGS_INITIALIZED;
+
+        // sub-client MMU lookups require address translation
+        if ((mmu->config & ~0x1) > 0)
+        {
+            // make sure virtual address range is a multiple of 64Kb
+            KOS_ASSERT((mmu->va_range & ((1 << 16)-1)) == 0);
+
+            // setup pagetable object
+            pagetable = kgsl_mmu_createpagetableobject(mmu, GSL_CALLER_PROCESSID_GET());
+            if (!pagetable)
+            {
+                kgsl_mmu_close(device);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+
+            mmu->hwpagetable = pagetable;
+
+            // create tlb flush filter to track dirty superPTE's -- one bit per superPTE
+            mmu->tlbflushfilter.size = (mmu->va_range / (GSL_PAGESIZE * GSL_PT_SUPER_PTE * 8)) + 1;
+            mmu->tlbflushfilter.base = (unsigned int *)kos_malloc(mmu->tlbflushfilter.size);
+            if (!mmu->tlbflushfilter.base)
+            {
+                kgsl_mmu_close(device);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+
+            GSL_TLBFLUSH_FILTER_RESET();
+
+            // set page table base
+            device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].PT_BASE, mmu->hwpagetable->base.gpuaddr);
+
+            // define virtual address range
+            device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].VA_RANGE, (mmu->hwpagetable->va_base | (mmu->hwpagetable->va_range >> 16)));
+
+            // allocate memory used for completing r/w operations that cannot be mapped by the MMU
+            flags  = (GSL_MEMFLAGS_ALIGN32 | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST);
+            status = kgsl_sharedmem_alloc0(device->id, flags, 32, &mmu->dummyspace);
+            if (status != GSL_SUCCESS)
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate dummy space memory.\n" );
+                kgsl_mmu_close(device);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", status );
+                return (status);
+            }
+
+            device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].TRAN_ERROR, mmu->dummyspace.gpuaddr);
+
+            // call device specific tlb invalidate
+			device->ftbl.mmu_tlbinvalidate(device, gsl_cfg_mmu_reg[devindex].INVALIDATE, mmu->hwpagetable->pid);
+
+			GSL_MMU_STATS(mmu->stats.tlbflushes++);
+
+            mmu->flags |= GSL_FLAGS_STARTED;
+        }
+    }
+
+    KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_debug(&device->mmu, &regs));
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_map(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, const gsl_scatterlist_t *scatterlist, gsl_flags_t flags, unsigned int pid)
+{
+    //
+    // map physical pages into the gpu page table
+    //
+    int              status = GSL_SUCCESS;
+    unsigned int     i, phyaddr, ap;
+    unsigned int     pte, ptefirst, ptelast, superpte;
+    int              flushtlb;
+    gsl_pagetable_t  *pagetable;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_mmu_map(gsl_mmu_t *mmu=0x%08x, gpuaddr_t gpubaseaddr=0x%08x, gsl_scatterlist_t *scatterlist=%M, gsl_flags_t flags=%d, unsigned int pid=%d)\n",
+                    mmu, gpubaseaddr, scatterlist, flags, pid );
+
+    KOS_ASSERT(scatterlist);
+
+    if (scatterlist->num <= 0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: num pages is too small.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_map. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // get gpu access permissions
+    ap = GSL_PT_PAGE_AP[((flags & GSL_MEMFLAGS_GPUAP_MASK) >> GSL_MEMFLAGS_GPUAP_SHIFT)];
+
+    pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+    if (!pagetable)
+    {
+        return (GSL_FAILURE);
+    }
+
+    // check consistency, debug only
+    KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_checkconsistency(pagetable));
+
+    ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr);
+    ptelast  = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (scatterlist->num-1)));
+    flushtlb = 0;
+
+    if (!GSL_PT_MAP_GETADDR(ptefirst))
+    {
+        // tlb needs to be flushed when the first and last pte are not at superpte boundaries
+        if ((ptefirst & (GSL_PT_SUPER_PTE-1)) != 0 || ((ptelast+1) & (GSL_PT_SUPER_PTE-1)) != 0)
+        {
+            flushtlb = 1;
+        }
+
+        // create page table entries
+        for (pte = ptefirst; pte <= ptelast; pte++)
+        {
+            if (scatterlist->contiguous)
+            {
+                phyaddr = scatterlist->pages[0] + ((pte-ptefirst) * GSL_PAGESIZE);
+            }
+            else
+            {
+                phyaddr = scatterlist->pages[pte-ptefirst];
+            }
+
+            GSL_PT_MAP_SETADDR(pte, phyaddr);
+            GSL_PT_MAP_SETBITS(pte, ap);
+
+            // tlb needs to be flushed when a dirty superPTE gets backed
+            if ((pte & (GSL_PT_SUPER_PTE-1)) == 0)
+            {
+                if (GSL_TLBFLUSH_FILTER_ISDIRTY(pte / GSL_PT_SUPER_PTE))
+                {
+                    flushtlb = 1;
+                }
+            }
+
+            KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_SET_MMUTBL, pte , *(unsigned int*)(((char*)pagetable->base.hostptr) + (pte * GSL_PT_ENTRY_SIZEBYTES)), 0, "kgsl_mmu_map"));
+        }
+
+        if (flushtlb)
+        {
+            // every device's tlb needs to be flushed because the current page table is shared among all devices
+            for (i = 0; i < GSL_DEVICE_MAX; i++)
+            {
+                if (gsl_driver.device[i].flags & GSL_FLAGS_INITIALIZED)
+                {
+                    gsl_driver.device[i].mmu.flags |= GSL_MMUFLAGS_TLBFLUSH;
+                }
+            }
+        }
+
+        // determine new last mapped superPTE 
+        superpte = ptelast - (ptelast & (GSL_PT_SUPER_PTE-1));
+        if (superpte > pagetable->last_superpte)
+        {
+            pagetable->last_superpte = superpte;
+        }
+
+		GSL_MMU_STATS(mmu->stats.pt.maps++);
+    }
+    else
+    {
+        // this should never happen
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL, "FATAL: This should never happen.\n" );
+        KOS_ASSERT(0);
+        status = GSL_FAILURE;
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_map. Return value %B\n", GSL_SUCCESS );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_unmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, unsigned int pid)
+{
+    //
+    // remove mappings in the specified address range from the gpu page table
+    //
+    int              status = GSL_SUCCESS;
+    gsl_pagetable_t  *pagetable;
+    unsigned int     numpages;
+    unsigned int     pte, ptefirst, ptelast, superpte;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_mmu_unmap(gsl_mmu_t *mmu=0x%08x, gpuaddr_t gpubaseaddr=0x%08x, int range=%d, unsigned int pid=%d)\n",
+                    mmu, gpubaseaddr, range, pid );
+
+    if (range <= 0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Range is too small.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_unmap. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    numpages = (range >> GSL_PAGESIZE_SHIFT);
+    if (range & (GSL_PAGESIZE-1))
+    {
+        numpages++;
+    }
+
+    pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+    if (!pagetable)
+    {
+        return (GSL_FAILURE);
+    }
+
+    // check consistency, debug only
+    KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_checkconsistency(pagetable));
+
+    ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr);
+    ptelast  = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (numpages-1)));
+
+    if (GSL_PT_MAP_GETADDR(ptefirst))
+    {
+        superpte = ptefirst - (ptefirst & (GSL_PT_SUPER_PTE-1));
+        GSL_TLBFLUSH_FILTER_SETDIRTY(superpte / GSL_PT_SUPER_PTE);
+
+        // remove page table entries
+        for (pte = ptefirst; pte <= ptelast; pte++)
+        {
+            GSL_PT_MAP_RESET(pte);
+
+            superpte = pte - (pte & (GSL_PT_SUPER_PTE-1));
+            if (pte == superpte)
+            {
+                GSL_TLBFLUSH_FILTER_SETDIRTY(superpte / GSL_PT_SUPER_PTE);
+            }
+
+			KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_SET_MMUTBL, pte, *(unsigned int*)(((char*)pagetable->base.hostptr) + (pte * GSL_PT_ENTRY_SIZEBYTES)), 0, "kgsl_mmu_unmap, reset superPTE"));
+        }
+
+        // determine new last mapped superPTE 
+        superpte = ptelast - (ptelast & (GSL_PT_SUPER_PTE-1));
+        if (superpte == pagetable->last_superpte && pagetable->last_superpte >= GSL_PT_SUPER_PTE)
+        {
+            do
+            {
+                pagetable->last_superpte -= GSL_PT_SUPER_PTE;
+            } while (!GSL_PT_MAP_GETADDR(pagetable->last_superpte) && pagetable->last_superpte >= GSL_PT_SUPER_PTE);
+        }
+
+		GSL_MMU_STATS(mmu->stats.pt.unmaps++);
+    }
+    else
+    {
+        // this should never happen
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL, "FATAL: This should never happen.\n" );
+        KOS_ASSERT(0);
+        status = GSL_FAILURE;
+    }
+
+    // invalidate tlb, debug only
+	KGSL_DEBUG(GSL_DBGFLAGS_MMU, mmu->device->ftbl.mmu_tlbinvalidate(mmu->device, gsl_cfg_mmu_reg[mmu->device->id-1].INVALIDATE, pagetable->pid));
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_unmap. Return value %B\n", GSL_SUCCESS );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int         
+kgsl_mmu_getmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, gsl_scatterlist_t *scatterlist, unsigned int pid)
+{
+    //
+    // obtain scatter list of physical pages for the given gpu address range.
+    // if all pages are physically contiguous they are coalesced into a single
+    // scatterlist entry.
+    //
+    gsl_pagetable_t  *pagetable;
+    unsigned int     numpages;
+    unsigned int     pte, ptefirst, ptelast;
+    unsigned int     contiguous = 1;
+
+    numpages = (range >> GSL_PAGESIZE_SHIFT);
+    if (range & (GSL_PAGESIZE-1))
+    {
+        numpages++;
+    }
+
+    if (range <= 0 || scatterlist->num != numpages)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Range is too small.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_getmap. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+    if (!pagetable)
+    {
+        return (GSL_FAILURE);
+    }
+
+    ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr);
+    ptelast  = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (numpages-1)));
+
+    // determine whether pages are physically contiguous
+    if (numpages > 1)
+    {
+        for (pte = ptefirst; pte <= ptelast-1; pte++)
+        {
+            if (GSL_PT_MAP_GETADDR(pte) + GSL_PAGESIZE != GSL_PT_MAP_GETADDR(pte+1))
+            {
+                contiguous = 0;
+                break;
+            }
+        }
+    }
+
+    if (!contiguous)
+    {
+        // populate scatter list
+        for (pte = ptefirst; pte <= ptelast; pte++)
+        {
+            scatterlist->pages[pte-ptefirst] = GSL_PT_MAP_GETADDR(pte);
+        }
+    }
+    else
+    {
+        // coalesce physically contiguous pages into a single scatter list entry
+        scatterlist->pages[0] = GSL_PT_MAP_GETADDR(ptefirst);
+    }
+
+    scatterlist->contiguous = contiguous;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_close(gsl_device_t *device)
+{
+    //
+    // close device mmu
+    //
+    // call this with the global lock held
+    //
+    gsl_mmu_t     *mmu     = &device->mmu;
+    unsigned int  devindex = mmu->device->id-1;         // device_id is 1 based
+#ifdef _DEBUG
+    int           i;
+#endif // _DEBUG
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_close(gsl_device_t *device=0x%08x)\n", device );
+
+    if (mmu->flags & GSL_FLAGS_INITIALIZED0)
+    {
+        if (mmu->flags & GSL_FLAGS_STARTED)
+        {
+            // terminate pagetable object
+            kgsl_mmu_destroypagetableobject(mmu, GSL_CALLER_PROCESSID_GET());
+        }
+
+        // no more processes attached to current device mmu
+        if (mmu->refcnt == 0)
+        {
+#ifdef _DEBUG
+            // check if there are any orphaned pagetable objects lingering around
+            for (i = 0; i < GSL_MMU_PAGETABLE_MAX; i++)
+            {
+                if (mmu->pagetable[i])
+                {
+                    /* many dumpx test cases forcefully exit, and thus trigger this assert. */
+                    /* Because it is an annoyance for HW guys, it is disabled for dumpx */
+                    if(!gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX)
+                    {
+                        KOS_ASSERT(0);
+                        return (GSL_FAILURE);
+                    }
+                }
+            }
+#endif // _DEBUG
+
+            // disable mh interrupts
+            kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR);
+            kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR);
+            kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT);
+
+            // disable MMU
+            device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].CONFIG, 0x00000000);
+
+            if (mmu->tlbflushfilter.base)
+            {
+                kos_free(mmu->tlbflushfilter.base);
+            }
+
+            if (mmu->dummyspace.gpuaddr)
+            {
+                kgsl_sharedmem_free0(&mmu->dummyspace, GSL_CALLER_PROCESSID_GET());
+            }
+
+            mmu->flags &= ~GSL_FLAGS_STARTED;
+            mmu->flags &= ~GSL_FLAGS_INITIALIZED;
+            mmu->flags &= ~GSL_FLAGS_INITIALIZED0;
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_close. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_attachcallback(gsl_mmu_t *mmu, unsigned int pid)
+{
+    //
+    // attach process
+    //
+    // call this with the global lock held
+    //
+    int              status = GSL_SUCCESS;
+    gsl_pagetable_t  *pagetable;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_attachcallback(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid );
+
+    if (mmu->flags & GSL_FLAGS_INITIALIZED0)
+    {
+        // attach to current device mmu
+        mmu->refcnt++;
+
+        if (mmu->flags & GSL_FLAGS_STARTED)
+        {
+            // attach to pagetable object
+            pagetable = kgsl_mmu_createpagetableobject(mmu, pid);
+            if(pagetable)
+            {
+                pagetable->refcnt++;
+            }
+            else
+            {
+                status = GSL_FAILURE;
+            }
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_attachcallback. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_detachcallback(gsl_mmu_t *mmu, unsigned int pid)
+{
+    //
+    // detach process
+    //
+    int              status = GSL_SUCCESS;
+    gsl_pagetable_t  *pagetable;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_detachcallback(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid );
+
+    if (mmu->flags & GSL_FLAGS_INITIALIZED0)
+    {
+        // detach from current device mmu
+        mmu->refcnt--;
+
+        if (mmu->flags & GSL_FLAGS_STARTED)
+        {
+            // detach from pagetable object
+            pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+            if(pagetable)
+            {
+                pagetable->refcnt--;
+            }
+            else
+            {
+                status = GSL_FAILURE;
+            }
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_detachcallback. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_querystats(gsl_mmu_t *mmu, gsl_mmustats_t *stats)
+{
+#ifdef GSL_STATS_MMU
+    int              status = GSL_SUCCESS;
+
+    KOS_ASSERT(stats);
+
+    if (mmu->flags & GSL_FLAGS_STARTED)
+    {
+		kos_memcpy(stats, &mmu->stats, sizeof(gsl_mmustats_t));
+    }
+    else
+    {
+		kos_memset(stats, 0, sizeof(gsl_mmustats_t));
+    }
+
+    return (status);
+#else
+    // unreferenced formal parameters
+    (void) mmu;
+    (void) stats;
+
+    return (GSL_FAILURE_NOTSUPPORTED);
+#endif // GSL_STATS_MMU
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_bist(gsl_mmu_t *mmu)
+{
+    // unreferenced formal parameter
+    (void) mmu;
+
+    return (GSL_SUCCESS);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c b/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c
new file mode 100644
index 000000000000..c4b62b0174d2
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c
@@ -0,0 +1,1154 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#include "gsl_cmdstream.h"
+
+#ifdef GSL_BLD_YAMATO
+
+//////////////////////////////////////////////////////////////////////////////
+// ucode
+//////////////////////////////////////////////////////////////////////////////
+#define uint32 unsigned int
+
+#include "pm4_microcode.inl"
+#include "pfp_microcode_nrt.inl"
+
+#undef  uint32
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_RB_NOP_SIZEDWORDS               2               // default is 2
+#define GSL_RB_PROTECTED_MODE_CONTROL       0x00000000      // protected mode error checking below register address 0x800
+                                                            // note: if CP_INTERRUPT packet is used then checking needs
+                                                            // to change to below register address 0x7C8
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  ringbuffer size log2 quadwords equivalent
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE unsigned int
+gsl_ringbuffer_sizelog2quadwords(unsigned int sizedwords)
+{
+    unsigned int sizelog2quadwords = 0;
+    int i = sizedwords >> 1;
+    while (i >>= 1)
+    {
+       sizelog2quadwords++;
+    }
+    return (sizelog2quadwords);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// private prototypes
+//////////////////////////////////////////////////////////////////////////////
+#ifdef _DEBUG
+static void     kgsl_ringbuffer_debug(gsl_ringbuffer_t *rb, gsl_rb_debug_t *rb_debug);
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+void
+kgsl_cp_intrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_ringbuffer_t  *rb = (gsl_ringbuffer_t *) cookie;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> void kgsl_cp_intrcallback(gsl_intrid_t id=%I, void *cookie=0x%08x)\n", id, cookie );
+
+    switch(id)
+    {
+        // error condition interrupt
+        case GSL_INTR_YDX_CP_T0_PACKET_IN_IB:
+        case GSL_INTR_YDX_CP_OPCODE_ERROR:
+        case GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR:
+        case GSL_INTR_YDX_CP_RESERVED_BIT_ERROR:
+        case GSL_INTR_YDX_CP_IB_ERROR:
+
+            rb->device->ftbl.device_destroy(rb->device);
+            break;
+
+        // non-error condition interrupt
+        case GSL_INTR_YDX_CP_SW_INT:
+        case GSL_INTR_YDX_CP_IB2_INT:
+        case GSL_INTR_YDX_CP_IB1_INT:
+        case GSL_INTR_YDX_CP_RING_BUFFER:
+
+            // signal intr completion event
+            kos_event_signal(rb->device->intr.evnt[id]);
+            break;
+
+        default:
+
+            break;
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cp_intrcallback.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_ringbuffer_watchdog()
+{
+    gsl_ringbuffer_t  *rb = &(gsl_driver.device[GSL_DEVICE_YAMATO-1]).ringbuffer;       // device_id is 1 based
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> void kgsl_ringbuffer_watchdog()\n" );
+
+    if (rb->flags & GSL_FLAGS_STARTED)
+    {
+        GSL_RB_GET_READPTR(rb, &rb->rptr);
+
+        // ringbuffer is currently not empty
+        if (rb->rptr != rb->wptr)
+        {
+            // and a rptr sample was taken during interval n-1
+            if (rb->watchdog.flags & GSL_FLAGS_ACTIVE)
+            {
+                // and the rptr did not advance between interval n-1 and n
+                if (rb->rptr == rb->watchdog.rptr_sample)
+                {
+                    // then the core has hung
+                    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_FATAL,
+                                     "ERROR: Watchdog detected core hung.\n" );
+
+                    rb->device->ftbl.device_destroy(rb->device);
+                    return;
+                }
+            }
+
+            // save rptr sample for interval n
+            rb->watchdog.flags       |= GSL_FLAGS_ACTIVE;
+            rb->watchdog.rptr_sample  = rb->rptr;
+        }
+        else
+        {
+            // clear rptr sample for interval n
+            rb->watchdog.flags &= ~GSL_FLAGS_ACTIVE;
+        }
+
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_watchdog.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _DEBUG
+
+OSINLINE void
+kgsl_ringbuffer_checkregister(unsigned int reg, int pmodecheck)
+{
+	if (pmodecheck)
+	{
+		// check for register protection mode violation
+		if (reg <= (GSL_RB_PROTECTED_MODE_CONTROL & 0x3FFF))
+		{
+			kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Register protection mode violation.\n" );
+			KOS_ASSERT(0);
+		}
+	}
+
+	// range check register offset 
+	if (reg > (gsl_driver.device[GSL_DEVICE_YAMATO-1].regspace.sizebytes >> 2))
+	{
+		kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Register out of range.\n" );
+		KOS_ASSERT(0);
+	}
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_ringbuffer_checkpm4type0(unsigned int header, unsigned int** cmds, int pmodeoff)
+{
+    pm4_type0     pm4header = *((pm4_type0*) &header);
+    unsigned int  reg;
+
+    if (pm4header.one_reg_wr)
+    {
+        reg = pm4header.base_index;
+    }
+    else
+    {
+        reg = pm4header.base_index + pm4header.count;
+    }
+
+	kgsl_ringbuffer_checkregister(reg, !pmodeoff);
+
+    *cmds += pm4header.count + 1;
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_ringbuffer_checkpm4type3(unsigned int header, unsigned int** cmds, int indirection, int pmodeoff)
+{
+    pm4_type3     pm4header = *((pm4_type3*) &header);
+    unsigned int  *ordinal2 = *cmds;
+    unsigned int  *ibcmds, *end;
+    unsigned int  reg, length;
+
+	// check indirect buffer level
+	if (indirection > 2)
+	{
+		kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Only two levels of indirection supported.\n" );
+		KOS_ASSERT(0);
+	}
+
+    switch(pm4header.it_opcode)
+    {
+    case PM4_INDIRECT_BUFFER:
+    case PM4_INDIRECT_BUFFER_PFD:
+
+        // determine ib host base and end address
+        ibcmds = (unsigned int*) kgsl_sharedmem_convertaddr(*ordinal2, 0);
+        end    = ibcmds + *(ordinal2 + 1);
+
+        // walk through the ib
+        while(ibcmds < end)
+        {
+            unsigned int tmpheader = *(ibcmds++);
+
+            switch(tmpheader & PM4_PKT_MASK)
+            {
+            case PM4_TYPE0_PKT:
+                kgsl_ringbuffer_checkpm4type0(tmpheader, &ibcmds, pmodeoff);
+                break;
+
+            case PM4_TYPE1_PKT:
+            case PM4_TYPE2_PKT:
+                break;
+
+            case PM4_TYPE3_PKT:
+                kgsl_ringbuffer_checkpm4type3(tmpheader, &ibcmds, (indirection + 1), pmodeoff);
+                break;
+            }
+        }
+        break;
+
+    case PM4_ME_INIT:
+
+        if(indirection != 0)
+        {
+			kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: ME INIT packet cannot reside in an ib.\n" );
+            KOS_ASSERT(0);
+        }
+        break;
+
+    case PM4_REG_RMW:
+
+        reg = (*ordinal2) & 0x1FFF;
+
+		kgsl_ringbuffer_checkregister(reg, !pmodeoff);
+
+        break;
+
+    case PM4_SET_CONSTANT:
+
+        if((((*ordinal2) >> 16) & 0xFF) == 0x4)         // incremental register update
+        {
+            reg    = 0x2000 + ((*ordinal2) & 0x3FF);    // gfx decode space address starts at 0x2000
+            length = pm4header.count - 1;
+
+			kgsl_ringbuffer_checkregister(reg + length, 0);
+        }
+        break;
+
+    case PM4_LOAD_CONSTANT_CONTEXT:
+
+        if(((*(ordinal2 + 1) >> 16) & 0xFF) == 0x4)      // incremental register update
+        {
+            reg    = 0x2000 + (*(ordinal2 + 1) & 0x3FF); // gfx decode space address starts at 0x2000
+            length = *(ordinal2 + 2);
+
+			kgsl_ringbuffer_checkregister(reg + length, 0);
+        }
+        break;
+
+    case PM4_COND_WRITE:
+
+        if(((*ordinal2) & 0x00000100) == 0x0)           // write to register
+        {
+            reg = *(ordinal2 + 4) & 0x3FFF;
+
+			kgsl_ringbuffer_checkregister(reg, !pmodeoff);
+        }
+        break;
+    }
+
+    *cmds += pm4header.count + 1;
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_ringbuffer_checkpm4(unsigned int* cmds, unsigned int sizedwords, int pmodeoff)
+{
+    unsigned int *ringcmds = cmds;
+    unsigned int *end      = cmds + sizedwords;
+
+    while(ringcmds < end)
+    {
+        unsigned int header = *(ringcmds++);
+
+        switch(header & PM4_PKT_MASK)
+        {
+            case PM4_TYPE0_PKT:
+                kgsl_ringbuffer_checkpm4type0(header, &ringcmds, pmodeoff);
+                break;
+
+            case PM4_TYPE1_PKT:
+            case PM4_TYPE2_PKT:
+                break;
+
+            case PM4_TYPE3_PKT:
+                kgsl_ringbuffer_checkpm4type3(header, &ringcmds, 0, pmodeoff);
+                break;
+        }
+    }
+}
+
+#endif // _DEBUG
+
+//----------------------------------------------------------------------------
+
+static void
+kgsl_ringbuffer_submit(gsl_ringbuffer_t *rb)
+{
+    unsigned int value;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static void kgsl_ringbuffer_submit(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    KOS_ASSERT(rb->wptr != 0);
+
+    kgsl_device_active(rb->device);
+    
+    GSL_RB_UPDATE_WPTR_POLLING(rb);
+
+    // send the wptr to the hw
+    rb->device->ftbl.device_regwrite(rb->device, mmCP_RB_WPTR, rb->wptr);
+
+    // force wptr register to be updated
+    do
+    {
+        rb->device->ftbl.device_regread(rb->device, mmCP_RB_WPTR, &value);
+    } while (value != rb->wptr);
+
+    rb->flags |= GSL_FLAGS_ACTIVE;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_submit.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_ringbuffer_waitspace(gsl_ringbuffer_t *rb, unsigned int numcmds, int wptr_ahead)
+{
+    int           nopcount;
+    unsigned int  freecmds;
+    unsigned int  *cmds;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static int kgsl_ringbuffer_waitspace(gsl_ringbuffer_t *rb=0x%08x, unsigned int numcmds=%d, int wptr_ahead=%d)\n",
+                    rb, numcmds, wptr_ahead );
+
+
+    // if wptr ahead, fill the remaining with NOPs
+    if (wptr_ahead)
+    {
+        nopcount = rb->sizedwords - rb->wptr - 1;   // -1 for header
+
+        cmds = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr;
+        GSL_RB_WRITE(cmds, pm4_nop_packet(nopcount));
+        rb->wptr++;
+
+        kgsl_ringbuffer_submit(rb);
+
+        rb->wptr = 0;
+
+        GSL_RB_STATS(rb->stats.wraps++);
+    }
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RBWAIT, GSL_DEVICE_YAMATO, rb->wptr, numcmds, "kgsl_ringbuffer_waitspace"));
+
+    // wait for space in ringbuffer
+    for( ; ; )
+    {
+        GSL_RB_GET_READPTR(rb, &rb->rptr);
+
+        freecmds = rb->rptr - rb->wptr;
+
+        if ((freecmds == 0) || (freecmds > numcmds))
+        {
+            break;
+        }
+
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+static unsigned int *
+kgsl_ringbuffer_addcmds(gsl_ringbuffer_t *rb, unsigned int numcmds)
+{
+    unsigned int  *ptr;
+    int           status = GSL_SUCCESS;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static unsigned int* kgsl_ringbuffer_addcmds(gsl_ringbuffer_t *rb=0x%08x, unsigned int numcmds=%d)\n",
+                    rb, numcmds );
+
+    KOS_ASSERT(numcmds < rb->sizedwords);
+
+    // update host copy of read pointer when running in safe mode
+    if (rb->device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        GSL_RB_GET_READPTR(rb, &rb->rptr);
+    }
+
+    // check for available space
+    if (rb->wptr >= rb->rptr)
+    {
+        // wptr ahead or equal to rptr
+        if ((rb->wptr + numcmds) > (rb->sizedwords - GSL_RB_NOP_SIZEDWORDS))   // reserve dwords for nop packet
+        {
+            status = kgsl_ringbuffer_waitspace(rb, numcmds, 1);
+        }
+    }
+    else
+    {
+        // wptr behind rptr
+        if ((rb->wptr + numcmds) >= rb->rptr)
+        {
+            status  = kgsl_ringbuffer_waitspace(rb, numcmds, 0);
+        }
+
+        // check for remaining space
+        if ((rb->wptr + numcmds) > (rb->sizedwords - GSL_RB_NOP_SIZEDWORDS))   // reserve dwords for nop packet
+        {
+            status = kgsl_ringbuffer_waitspace(rb, numcmds, 1);
+        }
+    }
+
+    ptr       = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr;
+    rb->wptr += numcmds;
+
+    if (status == GSL_SUCCESS)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value 0x%08x\n", ptr );
+        return (ptr);
+    }
+    else
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value 0x%08x\n", NULL );
+        return (NULL);
+    }
+}
+
+//----------------------------------------------------------------------------
+int
+kgsl_ringbuffer_start(gsl_ringbuffer_t *rb)
+{
+    int           status;
+    cp_rb_cntl_u  cp_rb_cntl;
+    int           i;
+    unsigned int  *cmds;
+    gsl_device_t  *device = rb->device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static int kgsl_ringbuffer_start(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    if (rb->flags & GSL_FLAGS_STARTED)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_start. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    // clear memptrs values
+    kgsl_sharedmem_set0(&rb->memptrs_desc, 0, 0, sizeof(gsl_rbmemptrs_t));
+
+    // clear ringbuffer
+    kgsl_sharedmem_set0(&rb->buffer_desc, 0, 0x12341234, (rb->sizedwords << 2));
+
+    // setup WPTR polling address
+    device->ftbl.device_regwrite(device, mmCP_RB_WPTR_BASE, (rb->memptrs_desc.gpuaddr + GSL_RB_MEMPTRS_WPTRPOLL_OFFSET));
+
+    // setup WPTR delay
+    device->ftbl.device_regwrite(device, mmCP_RB_WPTR_DELAY, 0/*0x70000010*/);
+
+    // setup RB_CNTL
+    device->ftbl.device_regread(device, mmCP_RB_CNTL, (unsigned int *)&cp_rb_cntl);
+
+    cp_rb_cntl.f.rb_bufsz       = gsl_ringbuffer_sizelog2quadwords(rb->sizedwords); // size of ringbuffer
+    cp_rb_cntl.f.rb_blksz       = rb->blksizequadwords;                             // quadwords to read before updating mem RPTR
+    cp_rb_cntl.f.rb_poll_en     = GSL_RB_CNTL_POLL_EN;                              // WPTR polling
+    cp_rb_cntl.f.rb_no_update   = GSL_RB_CNTL_NO_UPDATE;                            // mem RPTR writebacks
+
+    device->ftbl.device_regwrite(device, mmCP_RB_CNTL, cp_rb_cntl.val);
+
+    // setup RB_BASE
+    device->ftbl.device_regwrite(device, mmCP_RB_BASE, rb->buffer_desc.gpuaddr);
+
+    // setup RPTR_ADDR
+    device->ftbl.device_regwrite(device, mmCP_RB_RPTR_ADDR, rb->memptrs_desc.gpuaddr + GSL_RB_MEMPTRS_RPTR_OFFSET);
+
+    // explicitly clear all cp interrupts when running in safe mode
+    if (rb->device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        device->ftbl.device_regwrite(device, mmCP_INT_ACK, 0xFFFFFFFF);
+    }
+
+    // setup scratch/timestamp addr
+    device->ftbl.device_regwrite(device, mmSCRATCH_ADDR, device->memstore.gpuaddr + GSL_DEVICE_MEMSTORE_OFFSET(soptimestamp));
+
+    // setup scratch/timestamp mask
+    device->ftbl.device_regwrite(device, mmSCRATCH_UMSK, GSL_RB_MEMPTRS_SCRATCH_MASK);
+
+    // load the CP ucode
+    device->ftbl.device_regwrite(device, mmCP_DEBUG, 0x02000000);
+    device->ftbl.device_regwrite(device, mmCP_ME_RAM_WADDR, 0);
+
+    for (i = 0; i < PM4_MICROCODE_SIZE; i++ )
+    {
+        device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][0]);
+        device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][1]);
+        device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][2]);
+    }
+
+    // load the prefetch parser ucode
+    device->ftbl.device_regwrite(device, mmCP_PFP_UCODE_ADDR, 0);
+
+    for ( i = 0; i < PFP_MICROCODE_SIZE_NRT; i++ )
+    {
+        device->ftbl.device_regwrite(device, mmCP_PFP_UCODE_DATA, aPFP_Microcode_nrt[i]);
+    }
+
+    // queue thresholds ???
+    device->ftbl.device_regwrite(device, mmCP_QUEUE_THRESHOLDS, 0x000C0804);
+
+    // reset pointers
+    rb->rptr = 0;
+    rb->wptr = 0;
+
+    // init timestamp
+    rb->timestamp    = 0;
+    GSL_RB_INIT_TIMESTAMP(rb);
+
+    // clear ME_HALT to start micro engine
+    device->ftbl.device_regwrite(device, mmCP_ME_CNTL, 0);
+
+    // ME_INIT
+    cmds  = kgsl_ringbuffer_addcmds(rb, 19);
+
+    GSL_RB_WRITE(cmds, PM4_HDR_ME_INIT);
+    GSL_RB_WRITE(cmds, 0x000003ff);                         // All fields present (bits 9:0)
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Disable/Enable Real-Time Stream processing (present but ignored)
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Enable (2D to 3D) and (3D to 2D) implicit synchronization (present but ignored)
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmRB_SURFACE_INFO));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SC_WINDOW_OFFSET));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmVGT_MAX_VTX_INDX));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmSQ_PROGRAM_CNTL));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmRB_DEPTHCONTROL));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SU_POINT_SIZE));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SC_LINE_CNTL));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SU_POLY_OFFSET_FRONT_SCALE));
+    GSL_RB_WRITE(cmds, 0x80000180);                         // Vertex and Pixel Shader Start Addresses in instructions (3 DWORDS per instruction)
+    GSL_RB_WRITE(cmds, 0x00000001);                         // Maximum Contexts
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Write Confirm Interval and The CP will wait the wait_interval * 16 clocks between polling
+    GSL_RB_WRITE(cmds, 0x00000000);                         // NQ and External Memory Swap
+    GSL_RB_WRITE(cmds, GSL_RB_PROTECTED_MODE_CONTROL);      // Protected mode error checking
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Disable header dumping and Header dump address
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Header dump size
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4CHECK, kgsl_ringbuffer_checkpm4((unsigned int *)rb->buffer_desc.hostptr, 19, 1));
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPPM4((unsigned int *)rb->buffer_desc.hostptr, 19));
+
+    kgsl_ringbuffer_submit(rb);
+
+    // idle device to validate ME INIT
+    status = device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+
+    if (status == GSL_SUCCESS)
+    {
+        rb->flags |= GSL_FLAGS_STARTED;
+    }
+
+    // enable cp interrupts
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_SW_INT, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB_ERROR, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB2_INT, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB1_INT, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_SW_INT);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB2_INT);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB1_INT);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER);
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_start. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb)
+{
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static int kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    if (rb->flags & GSL_FLAGS_STARTED)
+    {
+        // disable cp interrupts
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_SW_INT);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB_ERROR);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB2_INT);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB1_INT);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_RING_BUFFER);
+
+        // ME_HALT
+        rb->device->ftbl.device_regwrite(rb->device, mmCP_ME_CNTL, 0x10000000);
+
+        rb->flags &= ~GSL_FLAGS_STARTED;
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_stop. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_init(gsl_device_t *device)
+{
+    int               status;
+    gsl_flags_t       flags;
+    gsl_ringbuffer_t  *rb = &device->ringbuffer;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_ringbuffer_init(gsl_device_t *device=0x%08x)\n", device );
+
+    rb->device           = device;
+    rb->sizedwords       = (2 << gsl_cfg_rb_sizelog2quadwords);
+    rb->blksizequadwords = gsl_cfg_rb_blksizequadwords;
+
+    // allocate memory for ringbuffer, needs to be double octword aligned
+    // align on page from contiguous physical memory
+    flags = (GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST);
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = (GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_STRICTREQUEST)); /* set MMU table for ringbuffer */
+
+    status = kgsl_sharedmem_alloc0(device->id, flags, (rb->sizedwords << 2), &rb->buffer_desc);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RINGBUF_SET, (unsigned int)rb->buffer_desc.gpuaddr, (unsigned int)rb->buffer_desc.hostptr, 0, "kgsl_ringbuffer_init"));
+
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_ringbuffer_close(rb);
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status );
+        return (status);
+    }
+
+    // allocate memory for polling and timestamps
+    flags = (GSL_MEMFLAGS_ALIGN32 | GSL_MEMFLAGS_CONPHYS);
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = GSL_MEMFLAGS_ALIGN32);
+
+    status = kgsl_sharedmem_alloc0(device->id, flags, sizeof(gsl_rbmemptrs_t), &rb->memptrs_desc);
+
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_ringbuffer_close(rb);
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status );
+        return (status);
+    }
+
+    // overlay structure on memptrs memory
+    rb->memptrs = (gsl_rbmemptrs_t *)rb->memptrs_desc.hostptr;
+
+    rb->flags |= GSL_FLAGS_INITIALIZED;
+
+	// validate command stream data when running in safe mode
+	if (device->flags & GSL_FLAGS_SAFEMODE)
+	{
+		gsl_driver.flags_debug |= GSL_DBGFLAGS_PM4CHECK;
+	}
+
+    // start ringbuffer
+    status = kgsl_ringbuffer_start(rb);
+
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_ringbuffer_close(rb);
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status );
+        return (status);
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", GSL_SUCCESS );
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_close(gsl_ringbuffer_t *rb)
+{
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_ringbuffer_close(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    // stop ringbuffer
+    kgsl_ringbuffer_stop(rb);
+
+    // free buffer
+    if (rb->buffer_desc.hostptr)
+    {
+        kgsl_sharedmem_free0(&rb->buffer_desc, GSL_CALLER_PROCESSID_GET());
+    }
+
+    // free memory pointers
+    if (rb->memptrs_desc.hostptr)
+    {
+        kgsl_sharedmem_free0(&rb->memptrs_desc, GSL_CALLER_PROCESSID_GET());
+    }
+
+    rb->flags &= ~GSL_FLAGS_INITIALIZED;
+
+    kos_memset(rb, 0, sizeof(gsl_ringbuffer_t));
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_close. Return value %B\n", GSL_SUCCESS );
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+gsl_timestamp_t
+kgsl_ringbuffer_issuecmds(gsl_device_t *device, int pmodeoff, unsigned int *cmds, int sizedwords, unsigned int pid)
+{
+    gsl_ringbuffer_t  *rb = &device->ringbuffer;
+    unsigned int      pmodesizedwords;
+    unsigned int      *ringcmds;
+    unsigned int      timestamp;
+
+    pmodeoff = 0;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_timestamp_t kgsl_ringbuffer_issuecmds(gsl_device_t *device=0x%08x, int pmodeoff=%d, unsigned int *cmds=0x%08x, int sizedwords=%d, unsigned int pid=0x%08x)\n",
+                     device, pmodeoff, cmds, sizedwords, pid );
+
+	if (!(device->ringbuffer.flags & GSL_FLAGS_STARTED))
+	{
+		return (0);
+	}
+
+    // set mmu pagetable
+	kgsl_mmu_setpagetable(device, pid);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4CHECK, kgsl_ringbuffer_checkpm4(cmds, sizedwords, pmodeoff));
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPPM4(cmds, sizedwords));
+
+    // reserve space to temporarily turn off protected mode error checking if needed
+    pmodesizedwords = pmodeoff ? 8 : 0;
+
+#if defined GSL_RB_TIMESTAMP_INTERUPT
+    pmodesizedwords += 2;
+#endif        
+    // allocate space in ringbuffer
+    ringcmds = kgsl_ringbuffer_addcmds(rb, pmodesizedwords + sizedwords + 6);
+
+    if (pmodeoff)
+    {
+        // disable protected mode error checking
+        *ringcmds++ = pm4_type3_packet(PM4_ME_INIT, 2);
+        *ringcmds++ = 0x00000080;
+        *ringcmds++ = 0x00000000;
+    }
+
+    // copy the cmds to the ringbuffer
+    kos_memcpy(ringcmds, cmds, (sizedwords << 2));
+
+    ringcmds += sizedwords;
+
+    if (pmodeoff)
+    {
+        *ringcmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+        *ringcmds++ = 0;
+
+        // re-enable protected mode error checking
+        *ringcmds++ = pm4_type3_packet(PM4_ME_INIT, 2);
+        *ringcmds++ = 0x00000080;
+        *ringcmds++ = GSL_RB_PROTECTED_MODE_CONTROL;
+    }
+
+    // increment timestamp
+    rb->timestamp++;
+    timestamp = rb->timestamp;
+
+    // start-of-pipeline and end-of-pipeline timestamps
+    *ringcmds++ = pm4_type0_packet(mmCP_TIMESTAMP, 1);
+    *ringcmds++ = rb->timestamp;
+    *ringcmds++ = pm4_type3_packet(PM4_EVENT_WRITE, 3);
+    *ringcmds++ = CACHE_FLUSH_TS;
+    *ringcmds++ = device->memstore.gpuaddr + GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp);
+    *ringcmds++ = rb->timestamp;
+
+#if defined GSL_RB_TIMESTAMP_INTERUPT    
+    *ringcmds++ = pm4_type3_packet(PM4_INTERRUPT, 1);
+    *ringcmds++ = 0x80000000;
+#endif
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, (unsigned int)((char*)ringcmds - ((pmodesizedwords + sizedwords + 6) << 2)), (unsigned int)((char*)ringcmds - ((pmodesizedwords + sizedwords + 6) << 2)), (pmodesizedwords + sizedwords + 6) << 2, "kgsl_ringbuffer_issuecmds"));
+
+    // issue the commands
+    kgsl_ringbuffer_submit(rb);
+
+    // stats
+    GSL_RB_STATS(rb->stats.wordstotal += sizedwords);
+    GSL_RB_STATS(rb->stats.issues++);
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issuecmds. Return value %d\n", timestamp );
+
+    // return timestamp of issued commands
+    return (timestamp);
+}
+
+//----------------------------------------------------------------------------
+int
+kgsl_ringbuffer_issueibcmds(gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags)
+{
+    unsigned int  link[3];
+    int dumpx_swap;
+    (void)dumpx_swap; // used only when BB_DUMPX is defined
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_timestamp_t kgsl_ringbuffer_issueibcmds(gsl_device_t device=%0x%08x, int drawctxt_index=%d, gpuaddr_t ibaddr=0x%08x, int sizedwords=%d, gsl_timestamp_t *timestamp=0x%08x)\n",
+                     device, drawctxt_index, ibaddr, sizedwords, timestamp );
+
+    if (!(device->ringbuffer.flags & GSL_FLAGS_STARTED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issueibcmds. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    KOS_ASSERT(ibaddr);
+    KOS_ASSERT(sizedwords);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, dumpx_swap = kgsl_dumpx_parse_ibs(ibaddr, sizedwords));
+
+	// context switch if needed
+	kgsl_drawctxt_switch(device, &device->drawctxt[drawctxt_index], flags);
+
+    link[0] = PM4_HDR_INDIRECT_BUFFER_PFD;
+    link[1] = ibaddr;
+    link[2] = sizedwords;
+
+	*timestamp = kgsl_ringbuffer_issuecmds(device, 0, &link[0], 3, GSL_CALLER_PROCESSID_GET());
+
+    // idle device when running in safe mode
+    if (device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+    }
+    else
+    {
+        KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+        {
+            // insert wait for idle after every IB1
+            // this is conservative but works reliably and is ok even for performance simulations
+            device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+        });
+    }
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+    {
+        if(dumpx_swap)
+        {
+            KGSL_DEBUG_DUMPX( BB_DUMP_EXPORT_CBUF, 0, 0, 0, "resolve");
+            KGSL_DEBUG_DUMPX( BB_DUMP_FLUSH,0,0,0," ");
+        }
+    });
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issueibcmds. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _DEBUG
+static void
+kgsl_ringbuffer_debug(gsl_ringbuffer_t *rb, gsl_rb_debug_t *rb_debug)
+{
+    kos_memset(rb_debug, 0, sizeof(gsl_rb_debug_t));
+
+    rb_debug->pm4_ucode_rel = PM4_MICROCODE_VERSION;
+    rb_debug->pfp_ucode_rel = PFP_MICROCODE_VERSION;
+
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_BASE,      (unsigned int *)&rb_debug->cp_rb_base);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_CNTL,      (unsigned int *)&rb_debug->cp_rb_cntl);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_RPTR_ADDR, (unsigned int *)&rb_debug->cp_rb_rptr_addr);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_RPTR,      (unsigned int *)&rb_debug->cp_rb_rptr);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_WPTR,      (unsigned int *)&rb_debug->cp_rb_wptr);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_WPTR_BASE, (unsigned int *)&rb_debug->cp_rb_wptr_base);
+    rb->device->ftbl.device_regread(rb->device, mmSCRATCH_UMSK,    (unsigned int *)&rb_debug->scratch_umsk);
+    rb->device->ftbl.device_regread(rb->device, mmSCRATCH_ADDR,    (unsigned int *)&rb_debug->scratch_addr);
+    rb->device->ftbl.device_regread(rb->device, mmCP_ME_CNTL,      (unsigned int *)&rb_debug->cp_me_cntl);
+    rb->device->ftbl.device_regread(rb->device, mmCP_ME_STATUS,    (unsigned int *)&rb_debug->cp_me_status);
+    rb->device->ftbl.device_regread(rb->device, mmCP_DEBUG,        (unsigned int *)&rb_debug->cp_debug);
+    rb->device->ftbl.device_regread(rb->device, mmCP_STAT,         (unsigned int *)&rb_debug->cp_stat);
+    rb->device->ftbl.device_regread(rb->device, mmRBBM_STATUS,     (unsigned int *)&rb_debug->rbbm_status);
+    rb_debug->sop_timestamp = kgsl_cmdstream_readtimestamp(rb->device->id, GSL_TIMESTAMP_CONSUMED);
+    rb_debug->eop_timestamp = kgsl_cmdstream_readtimestamp(rb->device->id, GSL_TIMESTAMP_RETIRED);
+}
+#endif
+
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_querystats(gsl_ringbuffer_t *rb, gsl_rbstats_t *stats)
+{
+#ifdef GSL_STATS_RINGBUFFER
+    KOS_ASSERT(stats);
+
+    if (!(rb->flags & GSL_FLAGS_STARTED))
+    {
+        return (GSL_FAILURE);
+    }
+
+    kos_memcpy(stats, &rb->stats, sizeof(gsl_rbstats_t));
+
+    return (GSL_SUCCESS);
+#else
+    // unreferenced formal parameters
+    (void) rb;
+    (void) stats;
+
+    return (GSL_FAILURE_NOTSUPPORTED);
+#endif // GSL_STATS_RINGBUFFER
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb)
+{
+    unsigned int    *cmds;
+    unsigned int    temp, k, j;
+    int             status;
+    int             i;
+#ifdef _DEBUG
+    gsl_rb_debug_t  rb_debug;
+#endif
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    if (!(rb->flags & GSL_FLAGS_STARTED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // simple nop submit
+    cmds = kgsl_ringbuffer_addcmds(rb, 2);
+    if (!cmds)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    GSL_RB_WRITE(cmds, pm4_nop_packet(1));
+    GSL_RB_WRITE(cmds, 0xDEADBEEF);
+
+    kgsl_ringbuffer_submit(rb);
+
+    status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT);
+
+    if (status != GSL_SUCCESS)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status );
+        return (status);
+    }
+
+    // simple scratch submit
+    cmds = kgsl_ringbuffer_addcmds(rb, 2);
+    if (!cmds)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    GSL_RB_WRITE(cmds, pm4_type0_packet(mmSCRATCH_REG7, 1));
+    GSL_RB_WRITE(cmds, 0xFEEDF00D);
+
+    kgsl_ringbuffer_submit(rb);
+
+    status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT);
+
+    if (status != GSL_SUCCESS)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status );
+        return (status);
+    }
+
+    rb->device->ftbl.device_regread(rb->device, mmSCRATCH_REG7, &temp);
+
+    if (temp != 0xFEEDF00D)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // simple wraps
+    for (i = 0; i < 256; i+=2)
+    {
+        j    = ((rb->sizedwords >> 2) - 256) + i;
+
+        cmds = kgsl_ringbuffer_addcmds(rb, j);
+        if (!cmds)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+            return (GSL_FAILURE);
+        }
+
+        k = 0;
+
+        while (k < j)
+        {
+            k+=2;
+            GSL_RB_WRITE(cmds, pm4_type0_packet(mmSCRATCH_REG7, 1));
+            GSL_RB_WRITE(cmds, k);
+        }
+
+        kgsl_ringbuffer_submit(rb);
+
+        status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT);
+
+        if (status != GSL_SUCCESS)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status );
+            return (status);
+        }
+
+        rb->device->ftbl.device_regread(rb->device, mmSCRATCH_REG7, &temp);
+
+        if (temp != k)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+            return (GSL_FAILURE);
+        }
+    }
+
+    // max size submits, TODO do this at least with regreads
+    for (i = 0; i < 256; i++)
+    {
+        cmds = kgsl_ringbuffer_addcmds(rb, (rb->sizedwords >> 2));
+        if (!cmds)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+            return (GSL_FAILURE);
+        }
+
+        GSL_RB_WRITE(cmds, pm4_nop_packet((rb->sizedwords >> 2) - 1));
+
+        kgsl_ringbuffer_submit(rb);
+
+        status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT);
+
+        if (status != GSL_SUCCESS)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status );
+            return (status);
+        }
+    }
+
+    // submit load with randomness
+
+#ifdef GSL_RB_USE_MEM_TIMESTAMP
+    // scratch memptr validate
+#endif // GSL_RB_USE_MEM_TIMESTAMP
+
+#ifdef GSL_RB_USE_MEM_RPTR
+    // rptr memptr validate
+#endif // GSL_RB_USE_MEM_RPTR
+
+#ifdef  GSL_RB_USE_WPTR_POLLING
+    // wptr memptr validate
+#endif // GSL_RB_USE_WPTR_POLLING
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+#endif
+
diff --git a/drivers/mxc/amd-gpu/common/gsl_sharedmem.c b/drivers/mxc/amd-gpu/common/gsl_sharedmem.c
new file mode 100644
index 000000000000..51e66f97c52e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_sharedmem.c
@@ -0,0 +1,937 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+/////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_SHMEM_APERTURE_MARK(aperture_id)    \
+    (shmem->priv |= (((aperture_id + 1) << GSL_APERTURE_SHIFT) & GSL_APERTURE_MASK))
+
+#define GSL_SHMEM_APERTURE_ISMARKED(aperture_id)    \
+    (((shmem->priv & GSL_APERTURE_MASK) >> GSL_APERTURE_SHIFT) & (aperture_id + 1))
+
+#define GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id)                                                       \
+    aperture_id = (gsl_apertureid_t)((flags & GSL_MEMFLAGS_APERTURE_MASK) >> GSL_MEMFLAGS_APERTURE_SHIFT);  \
+    KOS_ASSERT(aperture_id < GSL_APERTURE_MAX);
+
+#define GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id)                                                     \
+    channel_id = (gsl_channelid_t)((flags & GSL_MEMFLAGS_CHANNEL_MASK) >> GSL_MEMFLAGS_CHANNEL_SHIFT);  \
+    KOS_ASSERT(channel_id < GSL_CHANNEL_MAX);
+
+#define GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index)   \
+    memdesc->priv = (memdesc->priv & ~GSL_APERTURE_MASK) | ((aperture_index << GSL_APERTURE_SHIFT) & GSL_APERTURE_MASK);
+
+#define GSL_MEMDESC_DEVICE_SET(memdesc, device_id)  \
+    memdesc->priv = (memdesc->priv & ~GSL_DEVICEID_MASK) | ((device_id << GSL_DEVICEID_SHIFT) & GSL_DEVICEID_MASK);
+
+#define GSL_MEMDESC_EXTALLOC_SET(memdesc, flag) \
+    memdesc->priv = (memdesc->priv & ~GSL_EXTALLOC_MASK) | ((flag << GSL_EXTALLOC_SHIFT) & GSL_EXTALLOC_MASK);
+
+#define GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index)                           \
+    KOS_ASSERT(memdesc);                                                            \
+    aperture_index = ((memdesc->priv & GSL_APERTURE_MASK) >> GSL_APERTURE_SHIFT);   \
+    KOS_ASSERT(aperture_index < GSL_SHMEM_MAX_APERTURES);
+
+#define GSL_MEMDESC_DEVICE_GET(memdesc, device_id)                                              \
+    KOS_ASSERT(memdesc);                                                                        \
+    device_id = (gsl_deviceid_t)((memdesc->priv & GSL_DEVICEID_MASK) >> GSL_DEVICEID_SHIFT);    \
+    KOS_ASSERT(device_id <= GSL_DEVICE_MAX);
+
+#define GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc)  \
+    ((memdesc->priv & GSL_EXTALLOC_MASK) >> GSL_EXTALLOC_SHIFT)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// aperture index in shared memory object
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE int
+kgsl_sharedmem_getapertureindex(gsl_sharedmem_t *shmem, gsl_apertureid_t aperture_id, gsl_channelid_t channel_id)
+{
+    KOS_ASSERT(shmem->aperturelookup[aperture_id][channel_id] < shmem->numapertures);
+
+    return (shmem->aperturelookup[aperture_id][channel_id]);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_sharedmem_init(gsl_sharedmem_t *shmem)
+{
+    int                i;
+    int                status;
+    gsl_shmemconfig_t  config;
+    int                mmu_virtualized;
+    gsl_apertureid_t   aperture_id;
+    gsl_channelid_t    channel_id;
+    unsigned int       hostbaseaddr;
+    gpuaddr_t          gpubaseaddr;
+    int                sizebytes;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_init(gsl_sharedmem_t *shmem=0x%08x)\n", shmem );
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    status = kgsl_hal_getshmemconfig(&config);
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to get sharedmem config.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", status );
+        return (status);
+    }
+
+    shmem->numapertures = config.numapertures;
+
+    for (i = 0; i < shmem->numapertures; i++)
+    {
+        aperture_id     = config.apertures[i].id;
+        channel_id      = config.apertures[i].channel;
+        hostbaseaddr    = config.apertures[i].hostbase;
+        gpubaseaddr     = config.apertures[i].gpubase;
+        sizebytes       = config.apertures[i].sizebytes;
+        mmu_virtualized = 0;
+
+        // handle mmu virtualized aperture
+        if (aperture_id == GSL_APERTURE_MMU)
+        {
+            mmu_virtualized = 1;
+            aperture_id     = GSL_APERTURE_EMEM;
+        }
+
+        // make sure aligned to page size
+        KOS_ASSERT((gpubaseaddr & ((1 << GSL_PAGESIZE_SHIFT) - 1)) == 0);
+
+        // make a multiple of page size
+        sizebytes = (sizebytes & ~((1 << GSL_PAGESIZE_SHIFT) - 1));
+
+        if (sizebytes > 0)
+        {
+            shmem->apertures[i].memarena = kgsl_memarena_create(aperture_id, mmu_virtualized, hostbaseaddr, gpubaseaddr, sizebytes);
+
+            if (!shmem->apertures[i].memarena)
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate memarena.\n" );
+                kgsl_sharedmem_close(shmem);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+
+            shmem->apertures[i].id       = aperture_id;
+            shmem->apertures[i].channel  = channel_id;
+            shmem->apertures[i].numbanks = 1;
+
+            // create aperture lookup table
+            if (GSL_SHMEM_APERTURE_ISMARKED(aperture_id))
+            {
+                // update "current aperture_id"/"current channel_id" index
+                shmem->aperturelookup[aperture_id][channel_id] = i;
+            }
+            else
+            {
+                // initialize "current aperture_id"/"channel_id" indexes
+                for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++)
+                {
+                    shmem->aperturelookup[aperture_id][channel_id] = i;
+                }
+
+                GSL_SHMEM_APERTURE_MARK(aperture_id);
+            }
+        }
+    }
+
+    shmem->flags |= GSL_FLAGS_INITIALIZED;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_close(gsl_sharedmem_t *shmem)
+{
+    int  i;
+    int  result = GSL_SUCCESS;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_close(gsl_sharedmem_t *shmem=0x%08x)\n", shmem );
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        for (i = 0; i < shmem->numapertures; i++)
+        {
+            if (shmem->apertures[i].memarena)
+            {
+                result = kgsl_memarena_destroy(shmem->apertures[i].memarena);
+            }
+        }
+
+        kos_memset(shmem, 0, sizeof(gsl_sharedmem_t));
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_close. Return value %B\n", result );
+
+    return (result);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_alloc0(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc)
+{
+    gsl_apertureid_t  aperture_id;
+    gsl_channelid_t   channel_id;
+    gsl_deviceid_t    tmp_id;
+    int               aperture_index, org_index;
+    int               result  = GSL_FAILURE;
+    gsl_mmu_t         *mmu    = NULL;
+    gsl_sharedmem_t   *shmem  = &gsl_driver.shmem;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_alloc(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x, int sizebytes=%d, gsl_memdesc_t *memdesc=%M)\n",
+                    device_id, flags, sizebytes, memdesc );
+
+    KOS_ASSERT(sizebytes);
+    KOS_ASSERT(memdesc);
+
+    GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id);
+    GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id);
+
+    kos_memset(memdesc, 0, sizeof(gsl_memdesc_t));
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // execute pending device action
+    tmp_id = (device_id != GSL_DEVICE_ANY) ? device_id : device_id+1;
+    for ( ; tmp_id <= GSL_DEVICE_MAX; tmp_id++)
+    {
+        if (gsl_driver.device[tmp_id-1].flags & GSL_FLAGS_INITIALIZED)
+        {
+            kgsl_device_runpending(&gsl_driver.device[tmp_id-1]);
+
+            if (tmp_id == device_id)
+            {
+                break;
+            }
+        }
+    }
+
+    // convert any device to an actual existing device
+    if (device_id == GSL_DEVICE_ANY)
+    {
+        for ( ; ; )
+        {
+            device_id++;
+
+            if (device_id <= GSL_DEVICE_MAX)
+            {
+                if (gsl_driver.device[device_id-1].flags & GSL_FLAGS_INITIALIZED)
+                {
+                    break;
+                }
+            }
+            else
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device.\n" );
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+        }
+    }
+
+    KOS_ASSERT(device_id > GSL_DEVICE_ANY && device_id <= GSL_DEVICE_MAX);
+
+    // get mmu reference
+    mmu = &gsl_driver.device[device_id-1].mmu;
+
+    aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id);
+
+    //do not proceed if it is a strict request, the aperture requested is not present, and the MMU is enabled
+    if (!((flags & GSL_MEMFLAGS_STRICTREQUEST) && aperture_id != shmem->apertures[aperture_index].id && kgsl_mmu_isenabled(mmu)))
+    {
+        // do allocation
+        result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc);
+
+        // if allocation failed
+        if (result != GSL_SUCCESS)
+        {
+            org_index = aperture_index;
+
+            // then failover to other channels within the current aperture
+            for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++)
+            {
+                aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id);
+
+                if (aperture_index != org_index)
+                {
+                    // do allocation
+                    result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc);
+
+                    if (result == GSL_SUCCESS)
+                    {
+                        break;
+                    }
+                }
+            }
+
+            // if allocation still has not succeeded, then failover to EMEM/MMU aperture, but
+            // not if it's a strict request and the MMU is enabled
+            if (result != GSL_SUCCESS && aperture_id != GSL_APERTURE_EMEM
+                && !((flags & GSL_MEMFLAGS_STRICTREQUEST) && kgsl_mmu_isenabled(mmu)))
+            {
+                aperture_id = GSL_APERTURE_EMEM;
+
+                // try every channel
+                for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++)
+                {
+                    aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id);
+
+                    if (aperture_index != org_index)
+                    {
+                        // do allocation
+                        result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc);
+
+                        if (result == GSL_SUCCESS)
+                        {
+                            break;
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    if (result == GSL_SUCCESS)
+    {
+        GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index);
+        GSL_MEMDESC_DEVICE_SET(memdesc, device_id);
+
+        if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena))
+        {
+            gsl_scatterlist_t scatterlist;
+
+            scatterlist.contiguous = 0;
+            scatterlist.num        = memdesc->size / GSL_PAGESIZE;
+
+            if (memdesc->size & (GSL_PAGESIZE-1))
+            {
+                scatterlist.num++;
+            }
+
+            scatterlist.pages = kos_malloc(sizeof(unsigned int) * scatterlist.num);
+            if (scatterlist.pages)
+            {
+                // allocate physical pages
+                result = kgsl_hal_allocphysical(memdesc->gpuaddr, scatterlist.num, scatterlist.pages);
+                if (result == GSL_SUCCESS)
+                {
+                    result = kgsl_mmu_map(mmu, memdesc->gpuaddr, &scatterlist, flags, GSL_CALLER_PROCESSID_GET());
+                    if (result != GSL_SUCCESS)
+                    {
+                        kgsl_hal_freephysical(memdesc->gpuaddr, scatterlist.num, scatterlist.pages);
+                    }
+                }
+
+                kos_free(scatterlist.pages);
+            }
+            else
+            {
+                result = GSL_FAILURE;
+            }
+
+            if (result != GSL_SUCCESS)
+            {
+                kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc);
+            }
+        }
+    }
+
+    KGSL_DEBUG_TBDUMP_SETMEM( memdesc->gpuaddr, 0, memdesc->size );
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", result );
+
+    return (result);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_alloc(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_sharedmem_alloc0(device_id, flags, sizebytes, memdesc);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_free0(gsl_memdesc_t *memdesc, unsigned int pid)
+{
+    int              status = GSL_SUCCESS;
+    int              aperture_index;
+    gsl_deviceid_t   device_id;
+    gsl_sharedmem_t  *shmem;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_free(gsl_memdesc_t *memdesc=%M)\n", memdesc );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+    GSL_MEMDESC_DEVICE_GET(memdesc, device_id);
+
+    shmem = &gsl_driver.shmem;
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena))
+        {
+            status |= kgsl_mmu_unmap(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, memdesc->size, pid);
+
+            if (!GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc))
+            {
+                status |= kgsl_hal_freephysical(memdesc->gpuaddr, memdesc->size / GSL_PAGESIZE, NULL);
+            }
+        }
+
+        kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc);
+
+        // clear descriptor
+        kos_memset(memdesc, 0, sizeof(gsl_memdesc_t));
+    }
+    else
+    {
+        status = GSL_FAILURE;
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_free. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_free(gsl_memdesc_t *memdesc)
+{
+	int status = GSL_SUCCESS;
+    GSL_API_MUTEX_LOCK();
+    status = kgsl_sharedmem_free0(memdesc, GSL_CALLER_PROCESSID_GET());
+    GSL_API_MUTEX_UNLOCK();
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_read0(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace)
+{
+    int              aperture_index;
+    gsl_sharedmem_t  *shmem;
+    unsigned int     gpuoffsetbytes;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_read(gsl_memdesc_t *memdesc=%M, void *dst=0x%08x, unsigned int offsetbytes=%d, unsigned int sizebytes=%d)\n",
+                    memdesc, dst, offsetbytes, sizebytes );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+
+    if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_FAILURE_BADPARAM );
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    shmem = &gsl_driver.shmem;
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    KOS_ASSERT(dst);
+    KOS_ASSERT(sizebytes);
+
+    if (memdesc->gpuaddr < shmem->apertures[aperture_index].memarena->gpubaseaddr)
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (memdesc->gpuaddr + sizebytes > shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes)
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes;
+
+    GSL_HAL_MEM_READ(dst, shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, sizebytes, touserspace);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_sharedmem_read0(memdesc, dst, offsetbytes, sizebytes, touserspace);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_write0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace)
+{
+    int              aperture_index;
+    gsl_sharedmem_t  *shmem;
+    unsigned int     gpuoffsetbytes;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_write(gsl_memdesc_t *memdesc=%M, unsigned int offsetbytes=%d, void *src=0x%08x, unsigned int sizebytes=%d)\n",
+                    memdesc, offsetbytes, src, sizebytes );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+
+    if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_FAILURE_BADPARAM );
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    shmem = &gsl_driver.shmem;
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    KOS_ASSERT(src);
+    KOS_ASSERT(sizebytes);
+    KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr);
+    KOS_ASSERT((memdesc->gpuaddr + sizebytes) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes));
+
+    gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes;
+
+    GSL_HAL_MEM_WRITE(shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, src, sizebytes, fromuserspace);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4MEM, KGSL_DEBUG_DUMPMEMWRITE((memdesc->gpuaddr + offsetbytes), sizebytes, src));
+
+    KGSL_DEBUG_TBDUMP_SYNCMEM( (memdesc->gpuaddr + offsetbytes), src, sizebytes );
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_write(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_sharedmem_write0(memdesc, offsetbytes, src, sizebytes, fromuserspace);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_set0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes)
+{
+    int              aperture_index;
+    gsl_sharedmem_t  *shmem;
+    unsigned int     gpuoffsetbytes;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_set(gsl_memdesc_t *memdesc=%M, unsigned int offsetbytes=%d, unsigned int value=0x%08x, unsigned int sizebytes=%d)\n",
+                    memdesc, offsetbytes, value, sizebytes );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+
+    if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_FAILURE_BADPARAM );
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    shmem = &gsl_driver.shmem;
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    KOS_ASSERT(sizebytes);
+    KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr);
+    KOS_ASSERT((memdesc->gpuaddr + sizebytes) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes));
+
+    gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes;
+
+    GSL_HAL_MEM_SET(shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, value, sizebytes);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4MEM, KGSL_DEBUG_DUMPMEMSET((memdesc->gpuaddr + offsetbytes), sizebytes, value));
+
+    KGSL_DEBUG_TBDUMP_SETMEM( (memdesc->gpuaddr + offsetbytes), value, sizebytes );
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_sharedmem_set0(memdesc, offsetbytes, value, sizebytes);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API unsigned int
+kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags)
+{
+    gsl_apertureid_t  aperture_id;
+    gsl_channelid_t   channel_id;
+    int               aperture_index;
+    unsigned int      result = 0;
+    gsl_sharedmem_t   *shmem;
+
+    // device_id is ignored at this level, it would be used with per-device memarena's
+
+    // unreferenced formal parameter
+    (void) device_id;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x)\n",
+                    device_id, flags );
+
+    GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id);
+    GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id);
+
+    GSL_API_MUTEX_LOCK();
+
+    shmem = &gsl_driver.shmem;
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        GSL_API_MUTEX_UNLOCK();
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_largestfreeblock. Return value %d\n", 0 );
+        return (0);
+    }
+
+    aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id);
+
+    if (aperture_id == shmem->apertures[aperture_index].id)
+    {
+        result = kgsl_memarena_getlargestfreeblock(shmem->apertures[aperture_index].memarena, flags);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_largestfreeblock. Return value %d\n", result );
+
+    return (result);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_map(gsl_deviceid_t device_id, gsl_flags_t flags, const gsl_scatterlist_t *scatterlist, gsl_memdesc_t *memdesc)
+{
+    int              status = GSL_FAILURE;
+    gsl_sharedmem_t  *shmem = &gsl_driver.shmem;
+    int              aperture_index;
+    gsl_deviceid_t   tmp_id;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_map(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x, gsl_scatterlist_t scatterlist=%M, gsl_memdesc_t *memdesc=%M)\n",
+                    device_id, flags, memdesc, scatterlist );
+
+    // execute pending device action
+    tmp_id = (device_id != GSL_DEVICE_ANY) ? device_id : device_id+1;
+    for ( ; tmp_id <= GSL_DEVICE_MAX; tmp_id++)
+    {
+        if (gsl_driver.device[tmp_id-1].flags & GSL_FLAGS_INITIALIZED)
+        {
+            kgsl_device_runpending(&gsl_driver.device[tmp_id-1]);
+
+            if (tmp_id == device_id)
+            {
+                break;
+            }
+        }
+    }
+
+    // convert any device to an actual existing device
+    if (device_id == GSL_DEVICE_ANY)
+    {
+        for ( ; ; )
+        {
+            device_id++;
+
+            if (device_id <= GSL_DEVICE_MAX)
+            {
+                if (gsl_driver.device[device_id-1].flags & GSL_FLAGS_INITIALIZED)
+                {
+                    break;
+                }
+            }
+            else
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device.\n" );
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_map. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+        }
+    }
+
+    KOS_ASSERT(device_id > GSL_DEVICE_ANY && device_id <= GSL_DEVICE_MAX);
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        aperture_index = kgsl_sharedmem_getapertureindex(shmem, GSL_APERTURE_EMEM, GSL_CHANNEL_1);
+
+        if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena))
+        {
+            KOS_ASSERT(scatterlist->num);
+            KOS_ASSERT(scatterlist->pages);
+
+            status = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, scatterlist->num *GSL_PAGESIZE, memdesc);
+            if (status == GSL_SUCCESS)
+            {
+                GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index);
+                GSL_MEMDESC_DEVICE_SET(memdesc, device_id);
+
+                // mark descriptor's memory as externally allocated -- i.e. outside GSL
+                GSL_MEMDESC_EXTALLOC_SET(memdesc, 1);
+
+                status = kgsl_mmu_map(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, scatterlist, flags, GSL_CALLER_PROCESSID_GET());
+                if (status != GSL_SUCCESS)
+                {
+                    kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc);
+                }
+            }
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_map. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_unmap(gsl_memdesc_t *memdesc)
+{
+    return (kgsl_sharedmem_free0(memdesc, GSL_CALLER_PROCESSID_GET()));
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_getmap(const gsl_memdesc_t *memdesc, gsl_scatterlist_t *scatterlist)
+{
+    int              status = GSL_SUCCESS;
+    int              aperture_index;
+    gsl_deviceid_t   device_id;
+    gsl_sharedmem_t  *shmem;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_getmap(gsl_memdesc_t *memdesc=%M, gsl_scatterlist_t scatterlist=%M)\n",
+                    memdesc, scatterlist );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+    GSL_MEMDESC_DEVICE_GET(memdesc, device_id);
+
+    shmem = &gsl_driver.shmem;
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        KOS_ASSERT(scatterlist->num);
+        KOS_ASSERT(scatterlist->pages);
+        KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr);
+        KOS_ASSERT((memdesc->gpuaddr + memdesc->size) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes));
+
+        kos_memset(scatterlist->pages, 0, sizeof(unsigned int) * scatterlist->num);
+
+        if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena))
+        {
+            status = kgsl_mmu_getmap(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, memdesc->size, scatterlist, GSL_CALLER_PROCESSID_GET());
+        }
+        else
+        {
+            // coalesce physically contiguous pages into a single scatter list entry
+            scatterlist->pages[0]   = memdesc->gpuaddr;
+            scatterlist->contiguous = 1;
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_getmap. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_querystats(gsl_sharedmem_t *shmem, gsl_sharedmem_stats_t *stats)
+{
+#ifdef GSL_STATS_MEM
+    int  status = GSL_SUCCESS;
+    int  i;
+
+    KOS_ASSERT(stats);
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        for (i = 0; i < shmem->numapertures; i++)
+        {
+            if (shmem->apertures[i].memarena)
+            {
+                stats->apertures[i].id      = shmem->apertures[i].id;
+                stats->apertures[i].channel = shmem->apertures[i].channel;
+
+                status |= kgsl_memarena_querystats(shmem->apertures[i].memarena, &stats->apertures[i].memarena);
+            }
+        }
+    }
+    else
+    {
+        kos_memset(stats, 0, sizeof(gsl_sharedmem_stats_t));
+    }
+
+    return (status);
+#else
+    // unreferenced formal parameters
+    (void) shmem;
+    (void) stats;
+
+    return (GSL_FAILURE_NOTSUPPORTED);
+#endif // GSL_STATS_MEM
+}
+
+//----------------------------------------------------------------------------
+
+unsigned int
+kgsl_sharedmem_convertaddr(unsigned int addr, int type)
+{
+    gsl_sharedmem_t  *shmem  = &gsl_driver.shmem;
+    unsigned int     cvtaddr = 0;
+    unsigned int     gpubaseaddr, hostbaseaddr, sizebytes;
+    int              i;
+
+    if ((shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        for (i = 0; i < shmem->numapertures; i++)
+        {
+            hostbaseaddr = shmem->apertures[i].memarena->hostbaseaddr;
+            gpubaseaddr  = shmem->apertures[i].memarena->gpubaseaddr;
+            sizebytes    = shmem->apertures[i].memarena->sizebytes;
+
+            // convert from gpu to host
+            if (type == 0)
+            {
+                if (addr >= gpubaseaddr && addr < (gpubaseaddr + sizebytes))
+                {
+                    cvtaddr = hostbaseaddr + (addr - gpubaseaddr);
+                    break;
+                }
+            }
+            // convert from host to gpu
+            else if (type == 1)
+            {
+                if (addr >= hostbaseaddr && addr < (hostbaseaddr + sizebytes))
+                {
+                    cvtaddr = gpubaseaddr + (addr - hostbaseaddr);
+                    break;
+                }
+            }
+        }
+    }
+
+    return (cvtaddr);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation)
+{
+    int status  = GSL_FAILURE;
+
+    /* unreferenced formal parameter */
+    (void)memdesc;
+    (void)offsetbytes;
+    (void)sizebytes;
+    (void)operation;
+
+    /* do cache operation */
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr)
+{
+    int status  = GSL_FAILURE;
+
+    memdesc->gpuaddr = (gpuaddr_t)hostptr;  /* map physical address with hostptr    */
+    memdesc->hostptr = hostptr;             /* set virtual address also in memdesc  */
+
+    /* unreferenced formal parameter */
+    (void)device_id;
+
+    return (status);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_tbdump.c b/drivers/mxc/amd-gpu/common/gsl_tbdump.c
new file mode 100644
index 000000000000..e22cf894f7b2
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_tbdump.c
@@ -0,0 +1,228 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include <stdio.h>
+#ifdef WIN32
+#include <windows.h>
+#endif
+#include "gsl.h"
+#include "gsl_tbdump.h"
+#include "kos_libapi.h"
+
+#ifdef TBDUMP
+
+typedef struct TBDump_
+{
+    void* file;
+} TBDump;
+
+
+static TBDump g_tb;
+static oshandle_t tbdump_mutex = 0;
+#define TBDUMP_MUTEX_LOCK() if( tbdump_mutex ) kos_mutex_lock( tbdump_mutex )
+#define TBDUMP_MUTEX_UNLOCK() if( tbdump_mutex ) kos_mutex_unlock( tbdump_mutex )
+
+/* ------------------------------------------------------------------------ */
+/* ------------------------------------------------------------------------ */
+/* ------------------------------------------------------------------------ */
+
+static void tbdump_printline(const char* format, ...)
+{
+    if(g_tb.file)
+    {
+        va_list va;
+        va_start(va, format);
+        vfprintf((FILE*)g_tb.file, format, va);
+        va_end(va);
+        fprintf((FILE*)g_tb.file, "\n");
+    }
+}
+
+static void tbdump_printinfo(const char* message )
+{
+    tbdump_printline("15 %s", message);
+}
+
+static void tbdump_getmemhex(char* buffer, unsigned int addr, unsigned int sizewords)
+{
+    unsigned int i = 0;
+    static const char* hexChars = "0123456789abcdef";
+    unsigned char* ptr = (unsigned char*)addr;
+
+    for (i = 0; i < sizewords; i++)
+    {
+        buffer[(sizewords - i) * 2 - 1] = hexChars[ptr[i] & 0x0f];
+        buffer[(sizewords - i) * 2 - 2] = hexChars[ptr[i] >> 4];
+    }
+    buffer[sizewords * 2] = '\0';
+}
+
+/* ------------------------------------------------------------------------ */
+
+void tbdump_open(char* filename)
+{
+    if( !tbdump_mutex ) tbdump_mutex = kos_mutex_create( "TBDUMP_MUTEX" );
+
+    kos_memset( &g_tb, 0, sizeof( g_tb ) );
+
+    g_tb.file = kos_fopen( filename, "wt" );
+
+    tbdump_printinfo("reset");
+    tbdump_printline("0");
+    tbdump_printline("1 00000000 00000eff");
+
+    /* Enable interrupts */
+    tbdump_printline("1 00000000 00000003");
+}
+
+void tbdump_close()
+{
+    TBDUMP_MUTEX_LOCK();
+
+    kos_fclose( g_tb.file );
+    g_tb.file = 0;
+
+    TBDUMP_MUTEX_UNLOCK();
+
+    if( tbdump_mutex ) kos_mutex_free( tbdump_mutex );
+}
+
+/* ------------------------------------------------------------------------ */
+
+void tbdump_syncmem(unsigned int addr, unsigned int src, unsigned int sizebytes)
+{
+    /* Align starting address and size */
+    unsigned int beg = addr;
+    unsigned int end = addr+sizebytes;
+    char buffer[65];
+
+    TBDUMP_MUTEX_LOCK();
+
+    beg = (beg+15) & ~15;
+    end &= ~15;
+
+    if( sizebytes <= 16 )
+    {
+        tbdump_getmemhex(buffer, src, 16);
+
+        tbdump_printline("19 %08x %i 1 %s", addr, sizebytes, buffer);
+
+        TBDUMP_MUTEX_UNLOCK();
+        return;
+    }
+
+    /* Handle unaligned start */
+    if( beg != addr )
+    {
+        tbdump_getmemhex(buffer, src, 16);
+
+        tbdump_printline("19 %08x %i 1 %s", addr, beg-addr, buffer);
+
+        src += beg-addr;
+    }
+
+    /* Dump the memory writes */
+    while( beg < end )
+    {
+        tbdump_getmemhex(buffer, src, 16);
+
+        tbdump_printline("2 %08x %s", beg, buffer);
+
+        beg += 16;
+        src += 16;
+    }
+
+    /* Handle unaligned end */
+    if( end != addr+sizebytes )
+    {
+        tbdump_getmemhex(buffer, src, 16);
+
+        tbdump_printline("19 %08x %i 1 %s", end, (addr+sizebytes)-end, buffer);
+    }
+
+    TBDUMP_MUTEX_UNLOCK();
+}
+
+/* ------------------------------------------------------------------------ */
+
+void tbdump_setmem(unsigned int addr, unsigned int value, unsigned int sizebytes)
+{
+    TBDUMP_MUTEX_LOCK();
+
+    tbdump_printline("19 %08x 4 %i %032x", addr, (sizebytes+3)/4, value );
+
+    TBDUMP_MUTEX_UNLOCK();
+}
+
+/* ------------------------------------------------------------------------ */
+
+void tbdump_slavewrite(unsigned int addr, unsigned int value)
+{
+    TBDUMP_MUTEX_LOCK();
+
+    tbdump_printline("1 %08x %08x", addr, value);
+
+    TBDUMP_MUTEX_UNLOCK();
+}
+
+/* ------------------------------------------------------------------------ */
+
+
+KGSL_API int
+kgsl_tbdump_waitirq()
+{
+    if(!g_tb.file) return GSL_FAILURE;
+
+    TBDUMP_MUTEX_LOCK();
+
+    tbdump_printinfo("wait irq");
+    tbdump_printline("10");
+
+    /* ACK IRQ */
+    tbdump_printline("1 00000418 00000003");
+    tbdump_printline("18 00000018 00000000 # slave read & assert");
+
+    TBDUMP_MUTEX_UNLOCK();
+
+    return GSL_SUCCESS;
+}
+
+/* ------------------------------------------------------------------------ */
+
+KGSL_API int
+kgsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height)
+{
+    static char filename[20];
+    static int numframe = 0;
+
+    if(!g_tb.file) return GSL_FAILURE;
+
+    TBDUMP_MUTEX_LOCK();
+    #pragma warning(disable:4996)
+    sprintf( filename, "tbdump_%08d.bmp", numframe++ );
+
+    tbdump_printline("13 %s %d %08x %d %d %d 0", filename, format, (unsigned int)addr, stride, width, height);
+
+    TBDUMP_MUTEX_UNLOCK();
+
+    return GSL_SUCCESS;
+}
+
+/* ------------------------------------------------------------------------ */
+
+#endif /* TBDUMP */
diff --git a/drivers/mxc/amd-gpu/common/gsl_yamato.c b/drivers/mxc/amd-gpu/common/gsl_yamato.c
new file mode 100644
index 000000000000..d74c9efe2f36
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_yamato.c
@@ -0,0 +1,886 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#ifdef _LINUX
+#include <linux/sched.h>
+#endif
+
+#ifdef GSL_BLD_YAMATO
+
+#include "gsl_ringbuffer.h"
+#include "gsl_drawctxt.h"
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+static int
+kgsl_yamato_gmeminit(gsl_device_t *device)
+{
+    rb_edram_info_u rb_edram_info = {0};
+    unsigned int    gmem_size;
+    unsigned int    edram_value = 0;
+
+    // make sure edram range is aligned to size
+    KOS_ASSERT((device->gmemspace.gpu_base  & (device->gmemspace.sizebytes - 1)) == 0);
+
+    // get edram_size value equivalent
+    gmem_size = (device->gmemspace.sizebytes >> 14);
+    while (gmem_size >>= 1)
+    {
+       edram_value++;
+    }
+
+    rb_edram_info.f.edram_size         = edram_value;
+    rb_edram_info.f.edram_mapping_mode = 0;                                     // EDRAM_MAP_UPPER
+    rb_edram_info.f.edram_range        = (device->gmemspace.gpu_base >> 14);    // must be aligned to size
+
+    device->ftbl.device_regwrite(device, mmRB_EDRAM_INFO, (unsigned int)rb_edram_info.val);
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_yamato_gmemclose(gsl_device_t *device)
+{
+    device->ftbl.device_regwrite(device, mmRB_EDRAM_INFO, 0x00000000);
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_yamato_rbbmintrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_device_t  *device = (gsl_device_t *) cookie;
+
+    switch(id)
+    {
+        // error condition interrupt
+        case GSL_INTR_YDX_RBBM_READ_ERROR:
+
+            device->ftbl.device_destroy(device);
+            break;
+
+        // non-error condition interrupt
+        case GSL_INTR_YDX_RBBM_DISPLAY_UPDATE:
+        case GSL_INTR_YDX_RBBM_GUI_IDLE:
+
+            kos_event_signal(device->intr.evnt[id]);
+            break;
+
+        default:
+
+            break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_yamato_cpintrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_device_t  *device = (gsl_device_t *) cookie;
+
+    switch(id)
+    {
+        case GSL_INTR_YDX_CP_RING_BUFFER:
+#ifndef _LINUX		
+              kos_event_signal(device->timestamp_event);
+#else
+			  wake_up_interruptible_all(&(device->timestamp_waitq));
+#endif
+            break;
+        default:
+            break;
+    }
+}
+//----------------------------------------------------------------------------
+
+void
+kgsl_yamato_sqintrcallback(gsl_intrid_t id, void *cookie)
+{
+    (void) cookie;      // unreferenced formal parameter
+	/*gsl_device_t  *device = (gsl_device_t *) cookie;*/
+
+    switch(id)
+    {
+        // error condition interrupt
+        case GSL_INTR_YDX_SQ_PS_WATCHDOG:
+        case GSL_INTR_YDX_SQ_VS_WATCHDOG:
+
+			// todo: take appropriate action
+
+			break;
+
+		default:
+
+			break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _DEBUG
+
+static int
+kgsl_yamato_bist(gsl_device_t *device)
+{
+    int           status = GSL_FAILURE;
+    unsigned int  link[2];
+
+    if (!(device->flags & GSL_FLAGS_STARTED))
+    {
+        return (GSL_FAILURE);
+    }
+
+    status = kgsl_ringbuffer_bist(&device->ringbuffer);
+    if (status != GSL_SUCCESS)
+    {
+        return (status);
+    }
+
+    // interrupt bist
+    link[0] = pm4_type3_packet(PM4_INTERRUPT, 1);
+    link[1] = CP_INT_CNTL__RB_INT_MASK;
+	kgsl_ringbuffer_issuecmds(device, 1, &link[0], 2, GSL_CALLER_PROCESSID_GET());
+
+    status = kgsl_mmu_bist(&device->mmu);
+    if (status != GSL_SUCCESS)
+    {
+        return (status);
+    }
+
+    return (status);
+}
+#endif
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_isr(gsl_device_t *device)
+{
+    unsigned int            status;
+#ifdef _DEBUG
+    mh_mmu_page_fault_u     page_fault        = {0};
+    mh_axi_error_u          axi_error         = {0};
+    mh_clnt_axi_id_reuse_u  clnt_axi_id_reuse = {0};
+    rbbm_read_error_u       read_error        = {0};
+#endif // DEBUG
+
+    // determine if yamato is interrupting, and if so, which block
+    device->ftbl.device_regread(device, mmMASTER_INT_SIGNAL, &status);
+
+    if (status & MASTER_INT_SIGNAL__MH_INT_STAT)
+    {
+#ifdef _DEBUG
+        // obtain mh error information
+        device->ftbl.device_regread(device, mmMH_MMU_PAGE_FAULT, (unsigned int *)&page_fault);
+        device->ftbl.device_regread(device, mmMH_AXI_ERROR, (unsigned int *)&axi_error);
+        device->ftbl.device_regread(device, mmMH_CLNT_AXI_ID_REUSE, (unsigned int *)&clnt_axi_id_reuse);
+#endif // DEBUG
+
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_MH);
+    }
+
+    if (status & MASTER_INT_SIGNAL__CP_INT_STAT)
+    {
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_CP);
+    }
+
+    if (status & MASTER_INT_SIGNAL__RBBM_INT_STAT)
+    {
+#ifdef _DEBUG
+        // obtain rbbm error information
+        device->ftbl.device_regread(device, mmRBBM_READ_ERROR, (unsigned int *)&read_error);
+#endif // DEBUG
+
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_RBBM);
+    }
+
+    if (status & MASTER_INT_SIGNAL__SQ_INT_STAT)
+    {
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_SQ);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_tlbinvalidate(gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid)
+{
+	unsigned int		 link[2];
+    mh_mmu_invalidate_u  mh_mmu_invalidate = {0};
+
+    mh_mmu_invalidate.f.invalidate_all = 1;
+    mh_mmu_invalidate.f.invalidate_tc  = 1;
+
+	// if possible, invalidate via command stream, otherwise via direct register writes
+	if (device->flags & GSL_FLAGS_STARTED)
+	{
+		link[0] = pm4_type0_packet(reg_invalidate, 1);
+		link[1] = mh_mmu_invalidate.val;
+
+		kgsl_ringbuffer_issuecmds(device, 1, &link[0], 2, pid);
+	}
+	else
+	{
+
+        device->ftbl.device_regwrite(device, reg_invalidate, mh_mmu_invalidate.val);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_setpagetable(gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid)
+{
+	unsigned int  link[25];
+
+    // if there is an active draw context, set via command stream,
+	if (device->flags & GSL_FLAGS_STARTED)
+    {
+        // wait for graphics pipe to be idle
+        link[0] = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+        link[1] = 0x00000000;
+
+        // set page table base
+        link[2] = pm4_type0_packet(reg_ptbase, 1);
+		link[3] = ptbase;
+
+        // HW workaround: to resolve MMU page fault interrupts caused by the VGT. It prevents 
+		// the CP PFP from filling the VGT DMA request fifo too early, thereby ensuring that 
+		// the VGT will not fetch vertex/bin data until after the page table base register 
+		// has been updated.
+		//
+		// Two null DRAW_INDX_BIN packets are inserted right after the page table base update, 
+		// followed by a wait for idle. The null packets will fill up the VGT DMA request 
+		// fifo and prevent any further vertex/bin updates from occurring until the wait 
+		// has finished.
+		link[4]  = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+		link[5]  = (0x4 << 16) | (mmPA_SU_SC_MODE_CNTL - 0x2000);
+		link[6]  = 0;          // disable faceness generation
+		link[7]  = pm4_type3_packet(PM4_SET_BIN_BASE_OFFSET, 1);
+		link[8]  = device->mmu.dummyspace.gpuaddr;
+		link[9]  = pm4_type3_packet(PM4_DRAW_INDX_BIN, 6);
+		link[10] = 0;          // viz query info
+		link[11] = 0x0003C004; // draw indicator
+		link[12] = 0;          // bin base
+		link[13] = 3;          // bin size
+		link[14] = device->mmu.dummyspace.gpuaddr; // dma base
+		link[15] = 6;          // dma size
+		link[16] = pm4_type3_packet(PM4_DRAW_INDX_BIN, 6);
+		link[17] = 0;          // viz query info
+		link[18] = 0x0003C004; // draw indicator
+		link[19] = 0;          // bin base
+		link[20] = 3;          // bin size
+		link[21] = device->mmu.dummyspace.gpuaddr; // dma base
+		link[22] = 6;          // dma size
+		link[23] = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+		link[24] = 0x00000000;
+
+		kgsl_ringbuffer_issuecmds(device, 1, &link[0], 25, pid);
+	}
+	else
+	{
+		device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+		device->ftbl.device_regwrite(device, reg_ptbase, ptbase);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_init(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE;
+
+    device->flags |= GSL_FLAGS_INITIALIZED;
+
+    kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_ON, 100);
+
+    //We need to make sure all blocks are powered up and clocked before
+    //issuing a soft reset.  The overrides will be turned off (set to 0)
+    //later in kgsl_yamato_start.
+    device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0xfffffffe);
+    device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0xffffffff);
+
+    // soft reset
+    device->ftbl.device_regwrite(device, mmRBBM_SOFT_RESET, 0xFFFFFFFF);
+    kos_sleep(50);
+    device->ftbl.device_regwrite(device, mmRBBM_SOFT_RESET, 0x00000000);
+
+    // RBBM control
+    device->ftbl.device_regwrite(device, mmRBBM_CNTL, 0x00004442);
+
+    // setup MH arbiter
+    device->ftbl.device_regwrite(device, mmMH_ARBITER_CONFIG, *(unsigned int *) &gsl_cfg_yamato_mharb);
+
+    // SQ_*_PROGRAM
+    device->ftbl.device_regwrite(device, mmSQ_VS_PROGRAM, 0x00000000);
+    device->ftbl.device_regwrite(device, mmSQ_PS_PROGRAM, 0x00000000);
+
+    // init interrupt
+    status = kgsl_intr_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    // init mmu
+    status = kgsl_mmu_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    return(status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_close(gsl_device_t *device)
+{
+    if (device->refcnt == 0)
+    {
+        // shutdown mmu
+        kgsl_mmu_close(device);
+
+        // shutdown interrupt
+        kgsl_intr_close(device);
+
+        kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_OFF, 0);
+
+        device->flags &= ~GSL_FLAGS_INITIALIZED;
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_destroy(gsl_device_t *device)
+{
+    int           i;
+    unsigned int  pid;
+
+#ifdef _DEBUG
+    // for now, signal catastrophic failure in a brute force way
+    KOS_ASSERT(0);
+#endif // _DEBUG
+
+    // todo: - hard reset core?
+
+    kgsl_drawctxt_destroyall(device);
+
+    for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++)
+    {
+        pid = device->callerprocess[i];
+        if (pid)
+        {
+            device->ftbl.device_stop(device);
+            kgsl_driver_destroy(pid);
+
+            // todo: terminate client process?
+        }
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_start(gsl_device_t *device, gsl_flags_t flags)
+{
+    int           status = GSL_FAILURE;
+    unsigned int  pm1, pm2;
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPFBSTART(device));
+
+    (void) flags;      // unreferenced formal parameter
+
+    kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_ON, 100);
+
+    // default power management override when running in safe mode
+    pm1 = (device->flags & GSL_FLAGS_SAFEMODE) ? 0xFFFFFFFE : 0x00000000;
+    pm2 = (device->flags & GSL_FLAGS_SAFEMODE) ? 0x000000FF : 0x00000000;
+    device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, pm1);
+    device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, pm2);
+
+    // enable rbbm interrupts
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR, kgsl_yamato_rbbmintrcallback, (void *) device);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE, kgsl_yamato_rbbmintrcallback, (void *) device);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE, kgsl_yamato_rbbmintrcallback, (void *) device);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE);
+#if defined GSL_RB_TIMESTAMP_INTERUPT	
+	kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER, kgsl_yamato_cpintrcallback, (void *) device);    
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER);
+#endif
+
+  //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE);
+
+    // enable sq interrupts
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG, kgsl_yamato_sqintrcallback, (void *) device);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG, kgsl_yamato_sqintrcallback, (void *) device);
+  //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG);
+  //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG);
+
+    // init gmem
+    kgsl_yamato_gmeminit(device);
+
+    // init ring buffer
+    status = kgsl_ringbuffer_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    // init draw context
+    status = kgsl_drawctxt_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    device->flags |= GSL_FLAGS_STARTED;
+
+    KGSL_DEBUG(GSL_DBGFLAGS_BIST, kgsl_yamato_bist(device));
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_stop(gsl_device_t *device)
+{
+    // disable rbbm interrupts
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR);
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE);
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE);
+#if defined GSL_RB_TIMESTAMP_INTERUPT	
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER);
+#endif
+
+    // disable sq interrupts
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG);
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG);
+
+    kgsl_drawctxt_close(device);
+
+    // shutdown ringbuffer
+    kgsl_ringbuffer_close(&device->ringbuffer);
+
+    // shutdown gmem
+    kgsl_yamato_gmemclose(device);
+
+    if(device->refcnt == 0)
+    {
+        kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_OFF, 0);
+    }
+
+    device->flags &= ~GSL_FLAGS_STARTED;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_getproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int  status = GSL_FAILURE;
+
+#ifndef _DEBUG
+    (void) sizebytes;       // unreferenced formal parameter
+#endif
+
+    if (type == GSL_PROP_DEVICE_INFO)
+    {
+        gsl_devinfo_t  *devinfo = (gsl_devinfo_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_devinfo_t));
+
+        devinfo->device_id         = device->id;
+        devinfo->chip_id           = (gsl_chipid_t)device->chip_id;
+        devinfo->mmu_enabled       = kgsl_mmu_isenabled(&device->mmu);
+        devinfo->gmem_hostbaseaddr = device->gmemspace.mmio_virt_base;
+        devinfo->gmem_gpubaseaddr  = device->gmemspace.gpu_base;
+        devinfo->gmem_sizebytes    = device->gmemspace.sizebytes;
+
+        status = GSL_SUCCESS;
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_setproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int  status = GSL_FAILURE;
+
+#ifndef _DEBUG
+    (void) sizebytes;           // unreferenced formal parameter
+#endif
+
+    if (type == GSL_PROP_DEVICE_POWER)
+    {
+        gsl_powerprop_t  *power = (gsl_powerprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_powerprop_t));
+
+        if (!(device->flags & GSL_FLAGS_SAFEMODE))
+        {
+            if (power->flags & GSL_PWRFLAGS_OVERRIDE_ON)
+            {
+                device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0xfffffffe);
+                device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0xffffffff);
+            }
+            else if (power->flags & GSL_PWRFLAGS_OVERRIDE_OFF)
+            {
+                device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0x00000000);
+                device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0x00000000);
+            }
+            else
+            {
+                kgsl_hal_setpowerstate(device->id, power->flags, power->value);
+            }
+        }
+
+        status = GSL_SUCCESS;
+    }
+    else if (type == GSL_PROP_DEVICE_DMI)
+    {
+        gsl_dmiprop_t  *dmi = (gsl_dmiprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_dmiprop_t));
+
+        //
+        //  In order to enable DMI, it must not already be enabled.
+        //
+        switch (dmi->flags)
+        {
+            case GSL_DMIFLAGS_ENABLE_SINGLE:
+            case GSL_DMIFLAGS_ENABLE_DOUBLE:
+                if (!gsl_driver.dmi_state)
+                {
+                    gsl_driver.dmi_state = OS_TRUE;
+                    gsl_driver.dmi_mode  = dmi->flags;
+                    gsl_driver.dmi_frame = -1;
+                    status = GSL_SUCCESS;
+                }
+                break;
+            case GSL_DMIFLAGS_DISABLE:
+                //
+                //  To disable, we must be enabled.
+                //
+                if (gsl_driver.dmi_state)
+                {
+                    gsl_driver.dmi_state = OS_FALSE;
+                    gsl_driver.dmi_mode  = -1;
+                    gsl_driver.dmi_frame = -2;
+                    status = GSL_SUCCESS;
+                }
+                break;
+            case GSL_DMIFLAGS_NEXT_BUFFER:
+                //
+                //  Going to the next buffer is dependent upon what mod we are in with respect to single, double, or triple buffering.
+                //  DMI must also be enabled.
+                //
+                if (gsl_driver.dmi_state)
+                {
+                    unsigned int    cmdbuf[10];
+                    unsigned int    *cmds = &cmdbuf[0];
+                    int             size;
+
+                    if (gsl_driver.dmi_frame == -1)
+                    {
+                        size = 8;
+
+                        *cmds++ =  pm4_type0_packet(mmRBBM_DSPLY, 1);
+                        switch (gsl_driver.dmi_mode)
+                        {
+                            case GSL_DMIFLAGS_ENABLE_SINGLE:
+                                gsl_driver.dmi_max_frame = 1;
+                                *cmds++ = 0x041000410;
+                                break;
+                            case GSL_DMIFLAGS_ENABLE_DOUBLE:
+                                gsl_driver.dmi_max_frame = 2;
+                                *cmds++ = 0x041000510;
+                                break;
+                            case GSL_DMIFLAGS_ENABLE_TRIPLE:
+                                gsl_driver.dmi_max_frame = 3;
+                                *cmds++ = 0x041000610;
+                                break;
+                        }
+                    }
+                    else
+                    {
+                        size = 6;
+                    }
+
+
+                    //
+                    //  Wait for 3D core to be idle and wait for vsync
+                    //
+                    *cmds++ =  pm4_type0_packet(mmWAIT_UNTIL, 1);
+                    *cmds++ = 0x00008000;           //  3d idle
+                    // *cmds++ = 0x00008008;         //  3d idle & vsync
+
+                    //
+                    //  Update the render latest register.
+                    //
+                    *cmds++ =  pm4_type0_packet(mmRBBM_RENDER_LATEST, 1);
+                    switch (gsl_driver.dmi_frame)
+                    {
+                        case 0:
+                            //
+                            //  Render frame 0
+                            //
+                            *cmds++ = 0;
+                            //
+                            //  Wait for our max frame # indicator to be de-asserted
+                            //
+                            *cmds++ =  pm4_type0_packet(mmWAIT_UNTIL, 1);
+                            *cmds++ = 0x00000008 << gsl_driver.dmi_max_frame;
+                            gsl_driver.dmi_frame = 1;
+                            break;
+                        case -1:
+                        case 1:
+                            //
+                            //  Render frame 1
+                            //
+                            *cmds++ = 1;
+                            *cmds++ =  pm4_type0_packet(mmWAIT_UNTIL, 1);
+                            *cmds++ = 0x00000010;   //  Wait for frame 0 to be deasserted
+                            gsl_driver.dmi_frame = 2;
+                            break;
+                        case 2:
+                            //
+                            //  Render frame 2
+                            //
+                            *cmds++ = 2;
+                            *cmds++ =  pm4_type0_packet(mmWAIT_UNTIL, 1);
+                            *cmds++ = 0x00000020;   //  Wait for frame 1 to be deasserted
+                            gsl_driver.dmi_frame = 0;
+                            break;
+                    }
+                    
+                    // issue the commands
+                    kgsl_ringbuffer_issuecmds(device, 1, &cmdbuf[0], size, GSL_CALLER_PROCESSID_GET());
+
+                    gsl_driver.dmi_frame %= gsl_driver.dmi_max_frame;
+                    status = GSL_SUCCESS;
+                }
+                break;
+            default:
+                status = GSL_FAILURE;
+                break;
+        }
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_idle(gsl_device_t *device, unsigned int timeout)
+{
+    int               status  = GSL_FAILURE;
+    gsl_ringbuffer_t  *rb     = &device->ringbuffer;
+    rbbm_status_u     rbbm_status;
+
+    (void) timeout;      // unreferenced formal parameter
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_REGPOLL, device->id, mmRBBM_STATUS, 0x80000000, "kgsl_yamato_idle"));
+
+    // first, wait until the CP has consumed all the commands in the ring buffer
+    if (rb->flags & GSL_FLAGS_STARTED)
+    {
+        do
+        {
+            GSL_RB_GET_READPTR(rb, &rb->rptr);
+
+        } while (rb->rptr != rb->wptr);
+    }
+
+    // now, wait for the GPU to finish its operations
+    for ( ; ; )
+    {
+        device->ftbl.device_regread(device, mmRBBM_STATUS, (unsigned int *)&rbbm_status);
+
+        if (!(rbbm_status.val & 0x80000000))
+        {
+            status = GSL_SUCCESS;
+            break;
+        }
+
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_regread(gsl_device_t *device, unsigned int offsetwords, unsigned int *value)
+{
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+            {
+                if (!(gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX_WITHOUT_IFH))
+                {
+                    if(offsetwords == mmCP_RB_RPTR || offsetwords == mmCP_RB_WPTR)
+                    {
+                        *value = device->ringbuffer.wptr;
+                        return (GSL_SUCCESS);
+                    }
+                }
+            });
+
+    GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value);
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_regwrite(gsl_device_t *device, unsigned int offsetwords, unsigned int value)
+{
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPREGWRITE(offsetwords, value));
+
+    GSL_HAL_REG_WRITE(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value);
+
+    // idle device when running in safe mode
+    if (device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_waitirq(gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout)
+{
+    int  status = GSL_FAILURE_NOTSUPPORTED;
+
+    if (intr_id == GSL_INTR_YDX_CP_IB1_INT || intr_id == GSL_INTR_YDX_CP_IB2_INT ||
+        intr_id == GSL_INTR_YDX_CP_SW_INT  || intr_id == GSL_INTR_YDX_RBBM_DISPLAY_UPDATE)
+    {
+        if (kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS)
+        {
+            // wait until intr completion event is received
+            if (kos_event_wait(device->intr.evnt[intr_id], timeout) == OS_SUCCESS)
+            {
+                *count = 1;
+                status = GSL_SUCCESS;
+            }
+            else
+            {
+                status = GSL_FAILURE_TIMEOUT;
+            }
+        }
+    }
+
+    return (status);
+}
+
+int
+kgsl_yamato_waittimestamp(gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout)
+{
+#if defined GSL_RB_TIMESTAMP_INTERUPT
+#ifndef _LINUX
+	return kos_event_wait( device->timestamp_event, timeout );
+#else
+	int status = wait_event_interruptible_timeout(device->timestamp_waitq,
+	                                              kgsl_cmdstream_check_timestamp(device->id, timestamp),
+												  msecs_to_jiffies(timeout));
+	if (status > 0)
+		return GSL_SUCCESS;
+	else
+		return GSL_FAILURE;
+#endif
+#else
+	return (GSL_SUCCESS);
+#endif
+}
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_runpending(gsl_device_t *device)
+{
+    (void) device;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_getfunctable(gsl_functable_t *ftbl)
+{
+    ftbl->device_init           = kgsl_yamato_init;
+    ftbl->device_close          = kgsl_yamato_close;
+    ftbl->device_destroy        = kgsl_yamato_destroy;
+    ftbl->device_start          = kgsl_yamato_start;
+    ftbl->device_stop           = kgsl_yamato_stop;
+    ftbl->device_getproperty    = kgsl_yamato_getproperty;
+    ftbl->device_setproperty    = kgsl_yamato_setproperty;
+    ftbl->device_idle           = kgsl_yamato_idle;
+	ftbl->device_waittimestamp  = kgsl_yamato_waittimestamp;
+    ftbl->device_regread        = kgsl_yamato_regread;
+    ftbl->device_regwrite       = kgsl_yamato_regwrite;
+    ftbl->device_waitirq        = kgsl_yamato_waitirq;
+    ftbl->device_runpending     = kgsl_yamato_runpending;
+    ftbl->intr_isr              = kgsl_yamato_isr;
+    ftbl->mmu_tlbinvalidate     = kgsl_yamato_tlbinvalidate;
+    ftbl->mmu_setpagetable      = kgsl_yamato_setpagetable;
+    ftbl->cmdstream_issueibcmds = kgsl_ringbuffer_issueibcmds;
+    ftbl->context_create        = kgsl_drawctxt_create;
+    ftbl->context_destroy       = kgsl_drawctxt_destroy;
+
+    return (GSL_SUCCESS);
+}
+
+#endif
+
diff --git a/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl b/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl
new file mode 100644
index 000000000000..dfe61295e9ef
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl
@@ -0,0 +1,327 @@
+/* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of QUALCOMM Incorporated nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef PFP_MICROCODE_NRT_H
+#define PFP_MICROCODE_NRT_H
+
+#define PFP_MICROCODE_VERSION 308308
+
+#define PFP_MICROCODE_SIZE_NRT 288
+
+uint32 aPFP_Microcode_nrt[PFP_MICROCODE_SIZE_NRT]={
+0xc60400,
+0x7e424b,
+0xa00000,
+0x7e828b,
+0x800001,
+0xc60400,
+0xcc4003,
+0x800000,
+0xd60003,
+0x800000,
+0xc62c00,
+0xc80c35,
+0x98c000,
+0xc80c35,
+0x880000,
+0xc80c1d,
+0x84000b,
+0xc60800,
+0x98c007,
+0xc61000,
+0x978003,
+0xcc4003,
+0xd60004,
+0x800000,
+0xcd0003,
+0x9783e8,
+0xc60400,
+0x800000,
+0xc60400,
+0x84000b,
+0xc60800,
+0x98c00c,
+0xc61000,
+0xcc4003,
+0xc61400,
+0xc61800,
+0x7d6d40,
+0xcd401e,
+0x978003,
+0xcd801e,
+0xd60004,
+0x800000,
+0xcd0003,
+0x800000,
+0xd6001f,
+0x84000b,
+0xc60800,
+0x98c007,
+0xc60c00,
+0xcc4003,
+0xcc8003,
+0xccc003,
+0x800000,
+0xd60003,
+0x800000,
+0xd6001f,
+0xc60800,
+0x348c08,
+0x98c006,
+0xc80c1e,
+0x98c000,
+0xc80c1e,
+0x800041,
+0xcc8007,
+0xcc8008,
+0xcc4003,
+0x800000,
+0xcc8003,
+0xc60400,
+0x1a9c07,
+0xca8821,
+0x95c3b9,
+0xc8102c,
+0x98800a,
+0x329418,
+0x9a4004,
+0xcc6810,
+0x042401,
+0xd00143,
+0xd00162,
+0xcd0002,
+0x7d514c,
+0xcd4003,
+0x9b8007,
+0x06a801,
+0x964003,
+0xc28000,
+0xcf4003,
+0x800001,
+0xc60400,
+0x800045,
+0xc60400,
+0x800001,
+0xc60400,
+0xc60800,
+0xc60c00,
+0xc8102d,
+0x349402,
+0x99000b,
+0xc8182e,
+0xcd4002,
+0xcd8002,
+0xd001e3,
+0xd001c3,
+0xccc003,
+0xcc801c,
+0xcd801d,
+0x800001,
+0xc60400,
+0xd00203,
+0x800000,
+0xd001c3,
+0xc8081f,
+0xc60c00,
+0xc80c20,
+0x988000,
+0xc8081f,
+0xcc4003,
+0xccc003,
+0xd60003,
+0xccc022,
+0xcc001f,
+0x800000,
+0xcc001f,
+0xc81c2f,
+0xc60400,
+0xc60800,
+0xc60c00,
+0xc81030,
+0x99c000,
+0xc81c2f,
+0xcc8021,
+0xcc4020,
+0x990011,
+0xc107ff,
+0xd00223,
+0xd00243,
+0x345402,
+0x7cb18b,
+0x7d95cc,
+0xcdc002,
+0xccc002,
+0xd00263,
+0x978005,
+0xccc003,
+0xc60800,
+0x80008a,
+0xc60c00,
+0x800000,
+0xd00283,
+0x97836b,
+0xc60400,
+0xd6001f,
+0x800001,
+0xc60400,
+0xd2000d,
+0xcc000d,
+0x800000,
+0xcc000d,
+0xc60800,
+0xc60c00,
+0xca1433,
+0xd022a0,
+0xcce000,
+0x99435c,
+0xcce005,
+0x800000,
+0x062001,
+0xc60800,
+0xc60c00,
+0xd202c3,
+0xcc8003,
+0xccc003,
+0xcce027,
+0x800000,
+0x062001,
+0xca0831,
+0x9883ff,
+0xca0831,
+0xd6001f,
+0x800001,
+0xc60400,
+0x0a2001,
+0x800001,
+0xc60400,
+0xd20009,
+0xd2000a,
+0xcc001f,
+0x800000,
+0xcc001f,
+0xd2000b,
+0xd2000c,
+0xcc001f,
+0x800000,
+0xcc001f,
+0xcc0023,
+0xcc4003,
+0xce0003,
+0x800000,
+0xd60003,
+0xd00303,
+0xcc0024,
+0xcc4003,
+0x800000,
+0xd60003,
+0xd00323,
+0xcc0025,
+0xcc4003,
+0x800000,
+0xd60003,
+0xd00343,
+0xcc0026,
+0xcc4003,
+0x800000,
+0xd60003,
+0x800000,
+0xd6001f,
+0x280401,
+0xd20001,
+0xcc4001,
+0xcc4006,
+0x8400e7,
+0xc40802,
+0xc40c02,
+0xcc402b,
+0x98831f,
+0xc63800,
+0x8400e7,
+0xcf802b,
+0x800000,
+0xd6001f,
+0xcc001f,
+0x880000,
+0xcc001f,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x0100c8,
+0x0200cd,
+0x0300d2,
+0x050004,
+0x1000d7,
+0x1700b6,
+0x220010,
+0x230038,
+0x250044,
+0x27005e,
+0x2d0070,
+0x2e007c,
+0x4b0009,
+0x34001d,
+0x36002d,
+0x3700a8,
+0x3b009b,
+0x3f009f,
+0x4400d9,
+0x4800c3,
+0x5000b9,
+0x5100be,
+0x5500c9,
+0x5600ce,
+0x5700d3,
+0x5d00b0,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+};
+
+#endif
diff --git a/drivers/mxc/amd-gpu/common/pm4_microcode.inl b/drivers/mxc/amd-gpu/common/pm4_microcode.inl
new file mode 100644
index 000000000000..03f6f4cd35e4
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/pm4_microcode.inl
@@ -0,0 +1,815 @@
+/* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of QUALCOMM Incorporated nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef PM4_MICROCODE_H
+#define PM4_MICROCODE_H
+
+#define PM4_MICROCODE_VERSION 300684
+
+#define PM4_MICROCODE_SIZE 768
+
+
+#ifdef _PRIMLIB_INCLUDE
+extern uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3];
+#else
+uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x000001f3, 0x00204411, 0x000 },
+    { 0x01000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00400000, 0x004 },
+    { 0x0000ffff, 0x00284621, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x34e00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x0000ffff, 0xc0280a20, 0x000 },
+    { 0x00000000, 0x00294582, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x0000ffff, 0xc0284620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a8 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x000021fc, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404803, 0x021 },
+    { 0x00000000, 0x00600000, 0x2a8 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x000021fc, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x0000a1fd, 0x0029462c, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x021 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00001000, 0x00281223, 0x000 },
+    { 0x00001000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x0000000e, 0x00404811, 0x000 },
+    { 0x00000394, 0x00204411, 0x000 },
+    { 0x00000001, 0xc0404811, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a8 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000008, 0xc0210a20, 0x000 },
+    { 0x00000000, 0x14e00000, 0x02d },
+    { 0x00000007, 0x00404811, 0x000 },
+    { 0x00000008, 0x00404811, 0x000 },
+    { 0x0000001f, 0x40280a20, 0x000 },
+    { 0x0000001b, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x043 },
+    { 0x00000002, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x04a },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x051 },
+    { 0x00000004, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x058 },
+    { 0x00000014, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x058 },
+    { 0x00000015, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x060 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0xc0404802, 0x000 },
+    { 0x0000001f, 0x40280a20, 0x000 },
+    { 0x0000001b, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x043 },
+    { 0x00000002, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x04a },
+    { 0x00000000, 0x00400000, 0x051 },
+    { 0x0000001f, 0xc0210e20, 0x000 },
+    { 0x00000612, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000001e, 0xc0210e20, 0x000 },
+    { 0x00000600, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000001e, 0xc0210e20, 0x000 },
+    { 0x00000605, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000001f, 0x40280a20, 0x000 },
+    { 0x0000001f, 0xc0210e20, 0x000 },
+    { 0x0000060a, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000001f, 0xc0680a20, 0x2a8 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00001fff, 0x40280a20, 0x000 },
+    { 0x80000000, 0x40280e20, 0x000 },
+    { 0x40000000, 0xc0281220, 0x000 },
+    { 0x00040000, 0x00694622, 0x2b2 },
+    { 0x00000000, 0x00201410, 0x000 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x06d },
+    { 0x00000000, 0xc0401800, 0x070 },
+    { 0x00001fff, 0xc0281a20, 0x000 },
+    { 0x00040000, 0x00694626, 0x2b2 },
+    { 0x00000000, 0x00201810, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x073 },
+    { 0x00000000, 0xc0401c00, 0x076 },
+    { 0x00001fff, 0xc0281e20, 0x000 },
+    { 0x00040000, 0x00694627, 0x2b2 },
+    { 0x00000000, 0x00201c10, 0x000 },
+    { 0x00000000, 0x00204402, 0x000 },
+    { 0x00000000, 0x002820c5, 0x000 },
+    { 0x00000000, 0x004948e8, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x00000010, 0x40210a20, 0x000 },
+    { 0x000000ff, 0x00280a22, 0x000 },
+    { 0x000007ff, 0x40280e20, 0x000 },
+    { 0x00000002, 0x00221e23, 0x000 },
+    { 0x00000005, 0xc0211220, 0x000 },
+    { 0x00080000, 0x00281224, 0x000 },
+    { 0x00000013, 0x00210224, 0x000 },
+    { 0x00000000, 0x14c00000, 0x084 },
+    { 0xa100ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x088 },
+    { 0x00000000, 0x0020162d, 0x000 },
+    { 0x00004000, 0x00500e23, 0x097 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x08c },
+    { 0x00000001, 0x0020162d, 0x000 },
+    { 0x00004800, 0x00500e23, 0x097 },
+    { 0x00000002, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x090 },
+    { 0x00000003, 0x0020162d, 0x000 },
+    { 0x00004900, 0x00500e23, 0x097 },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x094 },
+    { 0x00000002, 0x0020162d, 0x000 },
+    { 0x00004908, 0x00500e23, 0x097 },
+    { 0x00000012, 0x0020162d, 0x000 },
+    { 0x00002000, 0x00300e23, 0x000 },
+    { 0x00000000, 0x00290d83, 0x000 },
+    { 0x9400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948e5, 0x000 },
+    { 0x00000000, 0x00294483, 0x000 },
+    { 0x00000000, 0x40201800, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000013, 0x00210224, 0x000 },
+    { 0x00000000, 0x14c00000, 0x000 },
+    { 0x9400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948e5, 0x000 },
+    { 0x9300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404806, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000000, 0xc0201400, 0x000 },
+    { 0x0000001f, 0x00211a25, 0x000 },
+    { 0x00000000, 0x14e00000, 0x000 },
+    { 0x000007ff, 0x00280e25, 0x000 },
+    { 0x00000010, 0x00211225, 0x000 },
+    { 0x8300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0ae },
+    { 0x00000000, 0x00203622, 0x000 },
+    { 0x00004000, 0x00504a23, 0x0bd },
+    { 0x00000001, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0b2 },
+    { 0x00000001, 0x00203622, 0x000 },
+    { 0x00004800, 0x00504a23, 0x0bd },
+    { 0x00000002, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0b6 },
+    { 0x00000003, 0x00203622, 0x000 },
+    { 0x00004900, 0x00504a23, 0x0bd },
+    { 0x00000003, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0ba },
+    { 0x00000002, 0x00203622, 0x000 },
+    { 0x00004908, 0x00504a23, 0x0bd },
+    { 0x00000012, 0x00203622, 0x000 },
+    { 0x00000000, 0x00290d83, 0x000 },
+    { 0x00002000, 0x00304a23, 0x000 },
+    { 0x8400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x21000000, 0x000 },
+    { 0x00000000, 0x00400000, 0x0a4 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00040578, 0x00604411, 0x2b2 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x00000000, 0xc0201400, 0x000 },
+    { 0x00000000, 0xc0201800, 0x000 },
+    { 0x00007f00, 0x00280a21, 0x000 },
+    { 0x00004500, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0cd },
+    { 0x00000000, 0xc0201c00, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x00000010, 0x00280a23, 0x000 },
+    { 0x00000010, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d5 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00040000, 0x00694624, 0x2b2 },
+    { 0x00000000, 0x00400000, 0x0d6 },
+    { 0x00000000, 0x00600000, 0x135 },
+    { 0x00000000, 0x002820d0, 0x000 },
+    { 0x00000007, 0x00280a23, 0x000 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0dd },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x04e00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000002, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0e2 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x02e00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0e7 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000004, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0ec },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000005, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0f1 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x06e00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000006, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0f6 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x08e00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00007f00, 0x00280a21, 0x000 },
+    { 0x00004500, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x000 },
+    { 0x00000008, 0x00210a23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x11b },
+    { 0x00000000, 0xc0204400, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00007f00, 0x00280a21, 0x000 },
+    { 0x00004500, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x102 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000000, 0x00404c07, 0x0cd },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x00000000, 0xc0201400, 0x000 },
+    { 0x00000000, 0xc0201800, 0x000 },
+    { 0x00000000, 0xc0201c00, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00040000, 0x00694624, 0x2b2 },
+    { 0x00000000, 0x002820d0, 0x000 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00404c07, 0x107 },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x00000000, 0xc0201400, 0x000 },
+    { 0x00000000, 0xc0201800, 0x000 },
+    { 0x00000000, 0xc0201c00, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00040000, 0x00694624, 0x2b2 },
+    { 0x00000000, 0x002820d0, 0x000 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x06e00000, 0x000 },
+    { 0x00000000, 0x00404c07, 0x113 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000860e, 0x00204411, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000009, 0x00204811, 0x000 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x00404810, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00007fff, 0x00281a22, 0x000 },
+    { 0x00040000, 0x00694626, 0x2b2 },
+    { 0x00000000, 0x00200c10, 0x000 },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x80000000, 0x00281a22, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x132 },
+    { 0x00000000, 0x00600000, 0x135 },
+    { 0x00000000, 0x00201c10, 0x000 },
+    { 0x00000000, 0x00300c67, 0x000 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00404803, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0xa400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x000001ea, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x13b },
+    { 0x9e00ffff, 0x00204411, 0x000 },
+    { 0xdeadbeef, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x13e },
+    { 0xa400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x0080480b, 0x000 },
+    { 0x000001f3, 0x00204411, 0x000 },
+    { 0xe0000000, 0xc0484a20, 0x000 },
+    { 0x00000000, 0xd9000000, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x8c00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000fff, 0x00281223, 0x000 },
+    { 0x0000000f, 0x00203624, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00301224, 0x000 },
+    { 0x0000000e, 0x00203624, 0x000 },
+    { 0x8700ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000001, 0x00331224, 0x000 },
+    { 0x8600ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x0000001d, 0x00211223, 0x000 },
+    { 0x00000020, 0x00222091, 0x000 },
+    { 0x00000003, 0x00381228, 0x000 },
+    { 0x8800ffff, 0x00204411, 0x000 },
+    { 0x00004fff, 0x00304a24, 0x000 },
+    { 0x00000010, 0x00211623, 0x000 },
+    { 0x00000fff, 0x00281625, 0x000 },
+    { 0x00000fff, 0x00281a23, 0x000 },
+    { 0x00000000, 0x00331ca6, 0x000 },
+    { 0x8f00ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a27, 0x000 },
+    { 0x00000010, 0x00211223, 0x000 },
+    { 0x00000fff, 0x00281224, 0x000 },
+    { 0x0000000d, 0x00203624, 0x000 },
+    { 0x8b00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00301224, 0x000 },
+    { 0x0000000c, 0x00203624, 0x000 },
+    { 0x8500ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00331cc8, 0x000 },
+    { 0x9000ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a27, 0x000 },
+    { 0x00300000, 0x00493a2e, 0x000 },
+    { 0x00000000, 0x00202c11, 0x000 },
+    { 0x00000001, 0x00303e2f, 0x000 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x172 },
+    { 0x00000000, 0xd9000000, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000002, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0230, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x175 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000009, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x17d },
+    { 0x00000000, 0x00600000, 0x2af },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x00000016, 0x00203623, 0x000 },
+    { 0x00000000, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x180 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000001, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x183 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000002, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x18d },
+    { 0x00000004, 0xc0203620, 0x000 },
+    { 0x00000005, 0xc0203620, 0x000 },
+    { 0x00000006, 0xc0203620, 0x000 },
+    { 0x00000007, 0xc0203620, 0x000 },
+    { 0x00000008, 0xc0203620, 0x000 },
+    { 0x00000009, 0xc0203620, 0x000 },
+    { 0x0000000a, 0xc0203620, 0x000 },
+    { 0x0000000b, 0xc0203620, 0x000 },
+    { 0x00000003, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1b5 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x8c00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000fff, 0x00281223, 0x000 },
+    { 0x0000000f, 0x00203624, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00301224, 0x000 },
+    { 0x0000000e, 0x00203624, 0x000 },
+    { 0x8700ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000001, 0x00331224, 0x000 },
+    { 0x8600ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x0000001d, 0x00211223, 0x000 },
+    { 0x00000020, 0x00222091, 0x000 },
+    { 0x00000003, 0x00381228, 0x000 },
+    { 0x8800ffff, 0x00204411, 0x000 },
+    { 0x00004fff, 0x00304a24, 0x000 },
+    { 0x00000010, 0x00211623, 0x000 },
+    { 0x00000fff, 0x00281625, 0x000 },
+    { 0x00000fff, 0x00281a23, 0x000 },
+    { 0x00000000, 0x00331ca6, 0x000 },
+    { 0x8f00ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a27, 0x000 },
+    { 0x00000010, 0x00211223, 0x000 },
+    { 0x00000fff, 0x00281224, 0x000 },
+    { 0x0000000d, 0x00203624, 0x000 },
+    { 0x8b00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00301224, 0x000 },
+    { 0x0000000c, 0x00203624, 0x000 },
+    { 0x8500ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00331cc8, 0x000 },
+    { 0x9000ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a27, 0x000 },
+    { 0x00300000, 0x00293a2e, 0x000 },
+    { 0x00000004, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1bd },
+    { 0xa300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x40204800, 0x000 },
+    { 0x0000000a, 0xc0220e20, 0x000 },
+    { 0x00000011, 0x00203623, 0x000 },
+    { 0x000021f4, 0x00204411, 0x000 },
+    { 0x0000000a, 0x00614a2c, 0x2af },
+    { 0x00000005, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1c0 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000006, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1c6 },
+    { 0x9c00ffff, 0x00204411, 0x000 },
+    { 0x0000001f, 0x40214a20, 0x000 },
+    { 0x9600ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000007, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1d0 },
+    { 0x3fffffff, 0x00283a2e, 0x000 },
+    { 0xc0000000, 0x40280e20, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x18000000, 0x40280e20, 0x000 },
+    { 0x00000016, 0x00203623, 0x000 },
+    { 0xa400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0202c00, 0x000 },
+    { 0x00000000, 0x0020480b, 0x000 },
+    { 0x00000008, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1dc },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000015, 0x00203623, 0x000 },
+    { 0x00000002, 0x40221220, 0x000 },
+    { 0x00000000, 0x00301083, 0x000 },
+    { 0x00000014, 0x00203624, 0x000 },
+    { 0x00000003, 0xc0210e20, 0x000 },
+    { 0x10000000, 0x00280e23, 0x000 },
+    { 0xefffffff, 0x00283a2e, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x0000001f, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14e00000, 0x000 },
+    { 0x000003ff, 0x00280e22, 0x000 },
+    { 0x00000018, 0x00211222, 0x000 },
+    { 0x00000004, 0x00301224, 0x000 },
+    { 0x00000000, 0x0020108d, 0x000 },
+    { 0x00002000, 0x00291224, 0x000 },
+    { 0x8300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00294984, 0x000 },
+    { 0x8400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x21000000, 0x000 },
+    { 0x00000000, 0x00400000, 0x1de },
+    { 0x8200ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00003fff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x1fb },
+    { 0x00000000, 0x2ae00000, 0x205 },
+    { 0x20000080, 0x00281e2e, 0x000 },
+    { 0x00000080, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1f8 },
+    { 0x00000000, 0x00401c0c, 0x1f9 },
+    { 0x00000010, 0x00201e2d, 0x000 },
+    { 0x000021f9, 0x00294627, 0x000 },
+    { 0x00000000, 0x00404811, 0x205 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x23a },
+    { 0x00000000, 0x28e00000, 0x205 },
+    { 0x00800080, 0x00281e2e, 0x000 },
+    { 0x00000080, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x202 },
+    { 0x00000000, 0x00401c0c, 0x203 },
+    { 0x00000010, 0x00201e2d, 0x000 },
+    { 0x000021f9, 0x00294627, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x20c },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x0000000c, 0x0020162d, 0x000 },
+    { 0x0000000d, 0x00201a2d, 0x000 },
+    { 0xffdfffff, 0x00483a2e, 0x210 },
+    { 0x00000004, 0x00204811, 0x000 },
+    { 0x0000000e, 0x0020162d, 0x000 },
+    { 0x0000000f, 0x00201a2d, 0x000 },
+    { 0xffefffff, 0x00283a2e, 0x000 },
+    { 0x00000000, 0x00201c10, 0x000 },
+    { 0x00000000, 0x002f0067, 0x000 },
+    { 0x00000000, 0x04e00000, 0x205 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x8300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x8900ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204806, 0x000 },
+    { 0x8400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x21000000, 0x000 },
+    { 0x00000000, 0x00601010, 0x28c },
+    { 0x0000000c, 0x00221e24, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x22d },
+    { 0x20000000, 0x00293a2e, 0x000 },
+    { 0x000021f7, 0x0029462c, 0x000 },
+    { 0x00000000, 0x002948c7, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x0000000c, 0x00203630, 0x000 },
+    { 0x00000007, 0x00204811, 0x000 },
+    { 0x0000000d, 0x00203630, 0x000 },
+    { 0x9100ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x23000000, 0x000 },
+    { 0x8d00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404803, 0x240 },
+    { 0x00800000, 0x00293a2e, 0x000 },
+    { 0x000021f6, 0x0029462c, 0x000 },
+    { 0x00000000, 0x002948c7, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x0000000e, 0x00203630, 0x000 },
+    { 0x00000007, 0x00204811, 0x000 },
+    { 0x0000000f, 0x00203630, 0x000 },
+    { 0x9200ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x25000000, 0x000 },
+    { 0x8e00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404803, 0x240 },
+    { 0x8300ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00304a24, 0x000 },
+    { 0x8400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x21000000, 0x000 },
+    { 0x8200ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404811, 0x000 },
+    { 0x00000003, 0x40280a20, 0x000 },
+    { 0xffffffe0, 0xc0280e20, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x24a },
+    { 0x000021f6, 0x0029122c, 0x000 },
+    { 0x00040000, 0x00494624, 0x24c },
+    { 0x000021f7, 0x0029122c, 0x000 },
+    { 0x00040000, 0x00294624, 0x000 },
+    { 0x00000000, 0x00600000, 0x2b2 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x252 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x252 },
+    { 0x00000000, 0x00481630, 0x258 },
+    { 0x00000fff, 0x00281630, 0x000 },
+    { 0x0000000c, 0x00211a30, 0x000 },
+    { 0x00000fff, 0x00281a26, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x258 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00040d02, 0x00604411, 0x2b2 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x25d },
+    { 0x00000010, 0x00211e30, 0x000 },
+    { 0x00000fff, 0x00482630, 0x267 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x261 },
+    { 0x00000fff, 0x00281e30, 0x000 },
+    { 0x00000200, 0x00402411, 0x267 },
+    { 0x00000000, 0x00281e30, 0x000 },
+    { 0x00000010, 0x00212630, 0x000 },
+    { 0x00000010, 0x00211a30, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x258 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000003, 0x00381625, 0x000 },
+    { 0x00000003, 0x00381a26, 0x000 },
+    { 0x00000003, 0x00381e27, 0x000 },
+    { 0x00000003, 0x00382629, 0x000 },
+    { 0x00005000, 0x00302629, 0x000 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x00204806, 0x000 },
+    { 0x00005000, 0x00302225, 0x000 },
+    { 0x00040000, 0x00694628, 0x2b2 },
+    { 0x00000001, 0x00302228, 0x000 },
+    { 0x00000000, 0x00202810, 0x000 },
+    { 0x00040000, 0x00694628, 0x2b2 },
+    { 0x00000001, 0x00302228, 0x000 },
+    { 0x00000000, 0x00200810, 0x000 },
+    { 0x00040000, 0x00694628, 0x2b2 },
+    { 0x00000001, 0x00302228, 0x000 },
+    { 0x00000000, 0x00201410, 0x000 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x0000860e, 0x00204411, 0x000 },
+    { 0x00000000, 0x0020480a, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x00000000, 0x002f0128, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x282 },
+    { 0x00005000, 0x00302227, 0x000 },
+    { 0x0000000c, 0x00300e23, 0x000 },
+    { 0x00000003, 0x00331a26, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x270 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x000001f3, 0x00204411, 0x000 },
+    { 0x04000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00400000, 0x289 },
+    { 0x00000000, 0xc0600000, 0x28c },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x0ec00000, 0x28e },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x00000000, 0x0020280c, 0x000 },
+    { 0x00000011, 0x0020262d, 0x000 },
+    { 0x00000000, 0x002f012c, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x295 },
+    { 0x00000000, 0x00403011, 0x296 },
+    { 0x00000400, 0x0030322c, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000002, 0x00204811, 0x000 },
+    { 0x0000000a, 0x0021262c, 0x000 },
+    { 0x00000000, 0x00210130, 0x000 },
+    { 0x00000000, 0x14c00000, 0x29d },
+    { 0xa500ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00404811, 0x299 },
+    { 0xa500ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x000021f4, 0x0029462c, 0x000 },
+    { 0x0000000a, 0x00214a2a, 0x000 },
+    { 0xa200ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000002, 0x00204811, 0x000 },
+    { 0x00000000, 0x00210130, 0x000 },
+    { 0xdf7fffff, 0x00283a2e, 0x000 },
+    { 0x00000010, 0x0080362a, 0x000 },
+    { 0x9700ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x0020480c, 0x000 },
+    { 0xa200ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000002, 0x00204811, 0x000 },
+    { 0x00000000, 0x00810130, 0x000 },
+    { 0x00000000, 0x00203011, 0x000 },
+    { 0x00000010, 0x0080362c, 0x000 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x2b2 },
+    { 0x9f00ffff, 0x00204411, 0x000 },
+    { 0xdeadbeef, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x2b5 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00020143, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x01dd0002, 0x000 },
+    { 0x006301ee, 0x00280012, 0x000 },
+    { 0x00020002, 0x00020026, 0x000 },
+    { 0x00020002, 0x01ec0002, 0x000 },
+    { 0x00790242, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00200012, 0x00020016, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x011b00c5, 0x00020125, 0x000 },
+    { 0x00020141, 0x00020002, 0x000 },
+    { 0x00c50002, 0x0143002e, 0x000 },
+    { 0x00a2016b, 0x00020145, 0x000 },
+    { 0x00020002, 0x01200002, 0x000 },
+    { 0x00020002, 0x010f0103, 0x000 },
+    { 0x00090002, 0x000e000e, 0x000 },
+    { 0x0058003d, 0x00600002, 0x000 },
+    { 0x000200c1, 0x0002028a, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x000502b1, 0x00020008, 0x000 },
+};
+
+#endif
+static const uint32 ME_JUMP_TABLE_START = 740;
+static const uint32 ME_JUMP_TABLE_END   = 768;
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h b/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h
new file mode 100644
index 000000000000..7ec10b0c2556
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h
@@ -0,0 +1,86 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+	
+#ifndef __GSL_DISPLAYAPI_H
+#define __GSL_DISPLAYAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+//////////////////////////////////////////////////////////////////////////////
+//  entrypoints
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __GSLDISPLAY_EXPORTS
+#define DISP_API                    OS_DLLEXPORT
+#else
+#define DISP_API                    OS_DLLIMPORT
+#endif // __GSLDISPLAY_EXPORTS
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_DISPLAY_PANEL_TOSHIBA_640x480     0
+#define GSL_DISPLAY_PANEL_HITACHI_240x320     1
+#define GSL_DISPLAY_PANEL_DEFAULT             GSL_DISPLAY_PANEL_TOSHIBA_640x480
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+typedef int     gsl_display_id_t;
+typedef int     gsl_surface_id_t;
+
+typedef struct _gsl_displaymode_t {
+    int panel_id;
+    int width;
+    int height;
+    int bpp;
+    int orientation;
+    int frequency;
+} gsl_displaymode_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+DISP_API gsl_display_id_t   gsl_display_open(gsl_devhandle_t devhandle, int panel_id);
+DISP_API int                gsl_display_close(gsl_display_id_t display_id);
+DISP_API int                gsl_display_getcount(void);
+DISP_API int                gsl_display_setmode(gsl_display_id_t display_id, gsl_displaymode_t displaymode);
+DISP_API int                gsl_display_getmode(gsl_display_id_t display_id, gsl_displaymode_t *displaymode);
+DISP_API gsl_surface_id_t   gsl_display_setsurface(gsl_display_id_t display_id, void *buffer);
+DISP_API int                gsl_display_getactivesurface(gsl_display_id_t display_id, void **buffer);
+DISP_API int                gsl_display_flipsurface(gsl_display_id_t display_id, gsl_surface_id_t surface_id);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // __GSL_DISPLAYAPI_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h b/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h
new file mode 100644
index 000000000000..8476f5a95969
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h
@@ -0,0 +1,135 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_KLIBAPI_H
+#define __GSL_KLIBAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include "gsl_types.h"
+#include "gsl_properties.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  entrypoints
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __KGSLLIB_EXPORTS
+#define KGSL_API                    OS_DLLEXPORT
+#else
+#ifdef __KERNEL_MODE__
+#define KGSL_API                    extern
+#else
+#define KGSL_API                    OS_DLLIMPORT
+#endif
+#endif // __KGSLLIB_EXPORTS
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  version control                    
+//////////////////////////////////////////////////////////////////////////////
+#define KGSLLIB_NAME            "AMD GSL Kernel Library"
+#define KGSLLIB_VERSION         "0.1"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  library API
+//////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_driver_init(void);
+KGSL_API int                kgsl_driver_close(void);
+KGSL_API int                kgsl_driver_entry(gsl_flags_t flags);
+KGSL_API int                kgsl_driver_exit(void);
+KGSL_API int                kgsl_driver_destroy(unsigned int pid);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  device API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_device_start(gsl_deviceid_t device_id, gsl_flags_t flags);
+KGSL_API int                kgsl_device_stop(gsl_deviceid_t device_id);
+KGSL_API int                kgsl_device_idle(gsl_deviceid_t device_id, unsigned int timeout);
+KGSL_API int                kgsl_device_getproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes);
+KGSL_API int                kgsl_device_setproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes);
+KGSL_API int                kgsl_device_regread(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int *value);
+KGSL_API int                kgsl_device_regwrite(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int value);
+KGSL_API int                kgsl_device_waitirq(gsl_deviceid_t device_id, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  command API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_cmdstream_issueibcmds(gsl_deviceid_t device_id, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags);
+KGSL_API gsl_timestamp_t    kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id, gsl_timestamp_type_t type);
+KGSL_API int                kgsl_cmdstream_freememontimestamp(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type);
+KGSL_API int                kgsl_cmdstream_waittimestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp, unsigned int timeout);
+KGSL_API int                kgsl_cmdwindow_write(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data);
+KGSL_API int                kgsl_add_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t *timestamp);
+KGSL_API int                kgsl_cmdstream_check_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp);
+
+////////////////////////////////////////////////////////////////////////////
+//  context API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_context_create(gsl_deviceid_t device_id, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags);
+KGSL_API int                kgsl_context_destroy(gsl_deviceid_t device_id, unsigned int drawctxt_id);
+KGSL_API int                kgsl_drawctxt_bind_gmem_shadow(gsl_deviceid_t device_id, unsigned int drawctxt_id, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  sharedmem API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_sharedmem_alloc(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc);
+KGSL_API int                kgsl_sharedmem_free(gsl_memdesc_t *memdesc);
+KGSL_API int                kgsl_sharedmem_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace);
+KGSL_API int                kgsl_sharedmem_write(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace);
+KGSL_API int                kgsl_sharedmem_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes);
+KGSL_API unsigned int       kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags);
+KGSL_API int                kgsl_sharedmem_map(gsl_deviceid_t device_id, gsl_flags_t flags, const gsl_scatterlist_t *scatterlist, gsl_memdesc_t *memdesc);
+KGSL_API int                kgsl_sharedmem_unmap(gsl_memdesc_t *memdesc);
+KGSL_API int                kgsl_sharedmem_getmap(const gsl_memdesc_t *memdesc, gsl_scatterlist_t *scatterlist);
+KGSL_API int                kgsl_sharedmem_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation);
+KGSL_API int                kgsl_sharedmem_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  interrupt API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API void               kgsl_intr_isr(void);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  TB dump API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_tbdump_waitirq(void);
+KGSL_API int                kgsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif  // __GSL_KLIBAPI_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_libapi.h b/drivers/mxc/amd-gpu/include/api/gsl_libapi.h
new file mode 100644
index 000000000000..7a5be862f3ee
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_libapi.h
@@ -0,0 +1,142 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_LIBAPI_H
+#define __GSL_LIBAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include "gsl_types.h"
+
+//////////////////////////////////////////////////////////////////////////////
+//  entrypoints
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __GSLLIB_EXPORTS
+#define GSL_API                 OS_DLLEXPORT
+#else
+#define GSL_API                 OS_DLLIMPORT
+#endif // __GSLLIB_EXPORTS
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSLLIB_NAME            "AMD GSL User Library"
+#define GSLLIB_VERSION         "0.1"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  libary API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_library_open(gsl_flags_t flags);
+GSL_API int                     gsl_library_close(void);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  device API
+////////////////////////////////////////////////////////////////////////////
+GSL_API gsl_devhandle_t         gsl_device_open(gsl_deviceid_t device_id, gsl_flags_t flags);
+GSL_API int                     gsl_device_close(gsl_devhandle_t devhandle);
+GSL_API int                     gsl_device_idle(gsl_devhandle_t devhandle, unsigned int timeout);
+GSL_API int                     gsl_device_getcount(void);
+GSL_API int                     gsl_device_getinfo(gsl_devhandle_t devhandle, gsl_devinfo_t *devinfo);
+GSL_API int                     gsl_device_setpowerstate(gsl_devhandle_t devhandle, gsl_flags_t flags);
+GSL_API int                     gsl_device_setdmistate(gsl_devhandle_t devhandle,  gsl_flags_t flags);
+GSL_API int                     gsl_device_waitirq(gsl_devhandle_t devhandle, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout);
+GSL_API int                     gsl_device_waittimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t timestamp, unsigned int timeout);
+GSL_API int                     gsl_device_addtimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t *timestamp);
+
+//////////////////////////////////////////////////////////////////////////////
+//  direct register API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_register_read(gsl_devhandle_t devhandle, unsigned int offsetwords, unsigned int *data);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  command API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_cp_issueibcommands(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle, gpuaddr_t ibaddr, unsigned int sizewords, gsl_timestamp_t *timestamp, gsl_flags_t flags);
+GSL_API gsl_timestamp_t         gsl_cp_readtimestamp(gsl_devhandle_t devhandle, gsl_timestamp_type_t type);
+GSL_API int                     gsl_cp_checktimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t timestamp, gsl_timestamp_type_t type);
+GSL_API int                     gsl_cp_freememontimestamp(gsl_devhandle_t devhandle, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type);
+GSL_API int                     gsl_v3_issuecommand(gsl_devhandle_t devhandle, gsl_cmdwindow_t target, unsigned int addr, unsigned int data);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  context API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API gsl_ctxthandle_t        gsl_context_create(gsl_devhandle_t devhandle, gsl_context_type_t type, gsl_flags_t flags);
+GSL_API int                     gsl_context_destroy(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle);
+GSL_API int                     gsl_context_bind_gmem_shadow(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id);
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  sharedmem API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_memory_alloc(gsl_deviceid_t device_id, unsigned int sizebytes, gsl_flags_t flags, gsl_memdesc_t *memdesc);
+GSL_API int                     gsl_memory_free(gsl_memdesc_t *memdesc);
+GSL_API int                     gsl_memory_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int sizebytes, unsigned int offsetbytes);
+GSL_API int                     gsl_memory_write(const gsl_memdesc_t *memdesc, void *src, unsigned int sizebytes, unsigned int offsetbytes);
+GSL_API int                     gsl_memory_write_multiple(const gsl_memdesc_t *memdesc, void *src, unsigned int srcstridebytes, unsigned int dststridebytes, unsigned int blocksizebytes, unsigned int numblocks, unsigned int offsetbytes);
+GSL_API unsigned int            gsl_memory_getlargestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags);
+GSL_API int                     gsl_memory_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes);
+GSL_API int                     gsl_memory_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation);
+GSL_API int                     gsl_memory_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr);
+
+#ifdef _DIRECT_MAPPED
+GSL_API unsigned int            gsl_sharedmem_gethostaddr(const gsl_memdesc_t *memdesc);
+#endif // _DIRECT_MAPPED
+
+//////////////////////////////////////////////////////////////////////////////
+//  address translation API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_translate_physaddr(void* virtAddr, unsigned int* physAddr);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  TB dump API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_tbdump_waitirq();
+GSL_API int                     gsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height);
+
+//////////////////////////////////////////////////////////////////////////////
+//  OS specific APIs - need to go into their own gsl_libapi_platform.h file
+//////////////////////////////////////////////////////////////////////////////
+#ifdef WM7
+GSL_API int                     gsl_kos_wm7_surfobjfromhbitmap(HBITMAP hbitmap, SURFOBJ *surfobj);
+#endif // WM7
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif  // __GSL_LIBAPI_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h b/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h
new file mode 100644
index 000000000000..891c7b645ad6
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h
@@ -0,0 +1,157 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_PM4TYPES_H
+#define __GSL_PM4TYPES_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// packet mask
+//////////////////////////////////////////////////////////////////////////////
+#define PM4_PKT_MASK                0xc0000000
+
+
+//////////////////////////////////////////////////////////////////////////////
+// packet types
+//////////////////////////////////////////////////////////////////////////////
+#define PM4_TYPE0_PKT               ((unsigned int)0 << 30)
+#define PM4_TYPE1_PKT               ((unsigned int)1 << 30)
+#define PM4_TYPE2_PKT               ((unsigned int)2 << 30)
+#define PM4_TYPE3_PKT               ((unsigned int)3 << 30)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// type3 packets
+//////////////////////////////////////////////////////////////////////////////
+#define PM4_ME_INIT                 0x48    // initialize CP's micro-engine
+
+#define PM4_NOP                     0x10    // skip N 32-bit words to get to the next packet
+
+#define PM4_INDIRECT_BUFFER         0x3f    // indirect buffer dispatch.  prefetch parser uses this packet type to determine whether to pre-fetch the IB
+#define PM4_INDIRECT_BUFFER_PFD     0x37    // indirect buffer dispatch.  same as IB, but init is pipelined
+
+#define PM4_WAIT_FOR_IDLE           0x26    // wait for the IDLE state of the engine
+#define PM4_WAIT_REG_MEM            0x3c    // wait until a register or memory location is a specific value
+#define PM4_WAIT_REG_EQ             0x52    // wait until a register location is equal to a specific value
+#define PM4_WAT_REG_GTE             0x53    // wait until a register location is >= a specific value
+#define PM4_WAIT_UNTIL_READ         0x5c    // wait until a read completes
+#define PM4_WAIT_IB_PFD_COMPLETE    0x5d    // wait until all base/size writes from an IB_PFD packet have completed
+
+#define PM4_REG_RMW                 0x21    // register read/modify/write
+#define PM4_REG_TO_MEM              0x3e    // reads register in chip and writes to memory
+#define PM4_MEM_WRITE               0x3d    // write N 32-bit words to memory
+#define PM4_MEM_WRITE_CNTR          0x4f    // write CP_PROG_COUNTER value to memory
+#define PM4_COND_EXEC               0x44    // conditional execution of a sequence of packets
+#define PM4_COND_WRITE              0x45    // conditional write to memory or register
+
+#define PM4_EVENT_WRITE             0x46    // generate an event that creates a write to memory when completed
+#define PM4_EVENT_WRITE_SHD         0x58    // generate a VS|PS_done event
+#define PM4_EVENT_WRITE_CFL         0x59    // generate a cache flush done event
+#define PM4_EVENT_WRITE_ZPD         0x5b    // generate a z_pass done event
+
+#define PM4_DRAW_INDX               0x22    // initiate fetch of index buffer and draw
+#define PM4_DRAW_INDX_2             0x36    // draw using supplied indices in packet
+#define PM4_DRAW_INDX_BIN           0x34    // initiate fetch of index buffer and binIDs and draw
+#define PM4_DRAW_INDX_2_BIN         0x35    // initiate fetch of bin IDs and draw using supplied indices
+
+#define PM4_VIZ_QUERY               0x23    // begin/end initiator for viz query extent processing
+#define PM4_SET_STATE               0x25    // fetch state sub-blocks and initiate shader code DMAs
+#define PM4_SET_CONSTANT            0x2d    // load constant into chip and to memory
+#define PM4_IM_LOAD                 0x27    // load sequencer instruction memory (pointer-based)
+#define PM4_IM_LOAD_IMMEDIATE       0x2b    // load sequencer instruction memory (code embedded in packet)
+#define PM4_LOAD_CONSTANT_CONTEXT   0x2e    // load constants from a location in memory
+#define PM4_INVALIDATE_STATE        0x3b    // selective invalidation of state pointers
+
+#define PM4_SET_SHADER_BASES        0x4A    // dynamically changes shader instruction memory partition
+#define PM4_SET_BIN_BASE_OFFSET     0x4B    // program an offset that will added to the BIN_BASE value of the 3D_DRAW_INDX_BIN packet
+#define PM4_SET_BIN_MASK            0x50    // sets the 64-bit BIN_MASK register in the PFP
+#define PM4_SET_BIN_SELECT          0x51    // sets the 64-bit BIN_SELECT register in the PFP
+
+#define PM4_CONTEXT_UPDATE          0x5e    // updates the current context, if needed
+#define PM4_INTERRUPT               0x40    // generate interrupt from the command stream
+
+#define PM4_IM_STORE                0x2c    // copy sequencer instruction memory to system memory
+
+
+//////////////////////////////////////////////////////////////////////////////
+// packet header building macros
+//////////////////////////////////////////////////////////////////////////////
+#define pm4_type0_packet(regindx, cnt)                      (PM4_TYPE0_PKT | (((cnt)-1) << 16)  | ((regindx) & 0x7FFF))
+#define pm4_type0_packet_for_sameregister(regindx, cnt)     (PM4_TYPE0_PKT | (((cnt)-1) << 16)  | ((1 << 15) | ((regindx) & 0x7FFF))
+#define pm4_type1_packet(reg0, reg1)                        (PM4_TYPE1_PKT                      | ((reg1) << 12) | (reg0))
+#define pm4_type3_packet(opcode, cnt)                       (PM4_TYPE3_PKT | (((cnt)-1) << 16)  | (((opcode) & 0xFF) << 8))
+#define pm4_predicated_type3_packet(opcode, cnt)            (PM4_TYPE3_PKT | (((cnt)-1) << 16)  | (((opcode) & 0xFF) << 8) | 0x1))
+#define pm4_nop_packet(cnt)                                 (PM4_TYPE3_PKT | (((cnt)-1) << 16)  | (PM4_NOP << 8))
+
+
+//////////////////////////////////////////////////////////////////////////////
+// packet headers
+//////////////////////////////////////////////////////////////////////////////
+#define PM4_HDR_ME_INIT                 pm4_type3_packet(PM4_ME_INIT, 18)
+#define PM4_HDR_INDIRECT_BUFFER_PFD     pm4_type3_packet(PM4_INDIRECT_BUFFER_PFD, 2)
+#define PM4_HDR_INDIRECT_BUFFER         pm4_type3_packet(PM4_INDIRECT_BUFFER, 2)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+// -----------------------
+// pm4 type0 packet header
+// -----------------------
+typedef struct __pm4_type0
+{
+    unsigned int       base_index  :15;
+    unsigned int       one_reg_wr  :1;
+    unsigned int       count       :14;
+    unsigned int       type        :2;
+} pm4_type0;
+
+// -----------------------
+// pm4 type2 packet header
+// -----------------------
+typedef struct __pm4_type2
+{
+    unsigned int       reserved    :30;
+    unsigned int       type        :2;
+} pm4_type2;
+
+// -----------------------
+// pm4 type3 packet header
+// -----------------------
+typedef struct __pm4_type3
+{
+    unsigned int       predicate   :1;
+    unsigned int       reserved1   :7;
+    unsigned int       it_opcode   :7;
+    unsigned int       reserved2   :1;
+    unsigned int       count       :14;
+    unsigned int       type        :2;
+} pm4_type3;
+
+#endif  // __GSL_PM4TYPES_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_properties.h b/drivers/mxc/amd-gpu/include/api/gsl_properties.h
new file mode 100644
index 000000000000..520761fe3490
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_properties.h
@@ -0,0 +1,94 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_PROPERTIES_H
+#define __GSL_PROPERTIES_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+// --------------
+// property types
+// --------------
+typedef enum _gsl_property_type_t
+{
+    GSL_PROP_DEVICE_INFO      = 0x00000001,
+    GSL_PROP_DEVICE_SHADOW    = 0x00000002,
+    GSL_PROP_DEVICE_POWER     = 0x00000003,
+    GSL_PROP_SHMEM            = 0x00000004,
+    GSL_PROP_SHMEM_APERTURES  = 0x00000005,
+    GSL_PROP_DEVICE_DMI       = 0x00000006
+} gsl_property_type_t;
+
+// -----------------
+// aperture property
+// -----------------
+typedef struct _gsl_apertureprop_t {
+    unsigned int  gpuaddr;
+    unsigned int  hostaddr;
+} gsl_apertureprop_t;
+
+// --------------
+// shmem property
+// --------------
+typedef struct _gsl_shmemprop_t {
+    int                 numapertures;
+    unsigned int        aperture_mask;
+    unsigned int        aperture_shift;
+    gsl_apertureprop_t  *aperture;
+} gsl_shmemprop_t;
+
+// -----------------------------
+// device shadow memory property
+// -----------------------------
+typedef struct _gsl_shadowprop_t {
+    unsigned int  hostaddr;
+    unsigned int  size;
+    gsl_flags_t   flags;
+} gsl_shadowprop_t;
+
+// ---------------------
+// device power property
+// ---------------------
+typedef struct _gsl_powerprop_t {
+    unsigned int  value;
+    gsl_flags_t   flags;
+} gsl_powerprop_t;
+
+
+// ---------------------
+// device DMI property
+// ---------------------
+typedef struct _gsl_dmiprop_t {
+    unsigned int  value;
+    gsl_flags_t   flags;
+} gsl_dmiprop_t;
+
+#endif  // __GSL_PROPERTIES_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_types.h b/drivers/mxc/amd-gpu/include/api/gsl_types.h
new file mode 100644
index 000000000000..99f389deee84
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_types.h
@@ -0,0 +1,478 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_TYPES_H
+#define __GSL_TYPES_H
+
+#include "stddef.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+// status
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_SUCCESS                     OS_SUCCESS                  
+#define GSL_FAILURE                     OS_FAILURE                  
+#define GSL_FAILURE_SYSTEMERROR         OS_FAILURE_SYSTEMERROR      
+#define GSL_FAILURE_DEVICEERROR         OS_FAILURE_DEVICEERROR  
+#define GSL_FAILURE_OUTOFMEM            OS_FAILURE_OUTOFMEM         
+#define GSL_FAILURE_BADPARAM            OS_FAILURE_BADPARAM         
+#define GSL_FAILURE_OFFSETINVALID       OS_FAILURE_OFFSETINVALID
+#define GSL_FAILURE_NOTSUPPORTED        OS_FAILURE_NOTSUPPORTED     
+#define GSL_FAILURE_NOMOREAVAILABLE     OS_FAILURE_NOMOREAVAILABLE  
+#define GSL_FAILURE_NOTINITIALIZED      OS_FAILURE_NOTINITIALIZED 
+#define GSL_FAILURE_ALREADYINITIALIZED  OS_FAILURE_ALREADYINITIALIZED
+#define GSL_FAILURE_TIMEOUT             OS_FAILURE_TIMEOUT
+
+
+//////////////////////////////////////////////////////////////////////////////
+// memory allocation flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMFLAGS_ANY                0x00000000      // dont care
+
+#define GSL_MEMFLAGS_CHANNELANY         0x00000000
+#define GSL_MEMFLAGS_CHANNEL1           0x00000000
+#define GSL_MEMFLAGS_CHANNEL2           0x00000001
+#define GSL_MEMFLAGS_CHANNEL3           0x00000002
+#define GSL_MEMFLAGS_CHANNEL4           0x00000003
+                                        
+#define GSL_MEMFLAGS_BANKANY            0x00000000
+#define GSL_MEMFLAGS_BANK1              0x00000010
+#define GSL_MEMFLAGS_BANK2              0x00000020
+#define GSL_MEMFLAGS_BANK3              0x00000040
+#define GSL_MEMFLAGS_BANK4              0x00000080
+                                        
+#define GSL_MEMFLAGS_DIRANY             0x00000000
+#define GSL_MEMFLAGS_DIRTOP             0x00000100
+#define GSL_MEMFLAGS_DIRBOT             0x00000200
+                                        
+#define GSL_MEMFLAGS_APERTUREANY        0x00000000
+#define GSL_MEMFLAGS_EMEM               0x00000000
+#define GSL_MEMFLAGS_CONPHYS            0x00001000
+                                        
+#define GSL_MEMFLAGS_ALIGNANY           0x00000000      // minimum alignment is 32 bytes 
+#define GSL_MEMFLAGS_ALIGN32            0x00000000
+#define GSL_MEMFLAGS_ALIGN64            0x00060000
+#define GSL_MEMFLAGS_ALIGN128           0x00070000
+#define GSL_MEMFLAGS_ALIGN256           0x00080000
+#define GSL_MEMFLAGS_ALIGN512           0x00090000
+#define GSL_MEMFLAGS_ALIGN1K            0x000A0000
+#define GSL_MEMFLAGS_ALIGN2K            0x000B0000
+#define GSL_MEMFLAGS_ALIGN4K            0x000C0000
+#define GSL_MEMFLAGS_ALIGN8K            0x000D0000
+#define GSL_MEMFLAGS_ALIGN16K           0x000E0000
+#define GSL_MEMFLAGS_ALIGN32K           0x000F0000
+#define GSL_MEMFLAGS_ALIGN64K           0x00100000
+#define GSL_MEMFLAGS_ALIGNPAGE          GSL_MEMFLAGS_ALIGN4K
+
+#define GSL_MEMFLAGS_GPUREADWRITE       0x00000000
+#define GSL_MEMFLAGS_GPUREADONLY        0x01000000
+#define GSL_MEMFLAGS_GPUWRITEONLY       0x02000000
+#define GSL_MEMFLAGS_GPUNOACCESS        0x04000000
+
+#define GSL_MEMFLAGS_FORCEPAGESIZE      0x40000000
+#define GSL_MEMFLAGS_STRICTREQUEST      0x80000000      // fail the alloc if the flags cannot be honored 
+                    
+#define GSL_MEMFLAGS_CHANNEL_MASK       0x0000000F
+#define GSL_MEMFLAGS_BANK_MASK          0x000000F0
+#define GSL_MEMFLAGS_DIR_MASK           0x00000F00
+#define GSL_MEMFLAGS_APERTURE_MASK      0x0000F000
+#define GSL_MEMFLAGS_ALIGN_MASK         0x00FF0000
+#define GSL_MEMFLAGS_GPUAP_MASK         0x0F000000
+
+#define GSL_MEMFLAGS_CHANNEL_SHIFT      0
+#define GSL_MEMFLAGS_BANK_SHIFT         4
+#define GSL_MEMFLAGS_DIR_SHIFT          8
+#define GSL_MEMFLAGS_APERTURE_SHIFT     12
+#define GSL_MEMFLAGS_ALIGN_SHIFT        16
+#define GSL_MEMFLAGS_GPUAP_SHIFT        24
+
+
+//////////////////////////////////////////////////////////////////////////////
+// debug flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_DBGFLAGS_ALL                0xFFFFFFFF
+#define GSL_DBGFLAGS_DEVICE             0x00000001
+#define GSL_DBGFLAGS_CTXT               0x00000002
+#define GSL_DBGFLAGS_MEMMGR             0x00000004
+#define GSL_DBGFLAGS_MMU                0x00000008
+#define GSL_DBGFLAGS_POWER              0x00000010
+#define GSL_DBGFLAGS_IRQ                0x00000020
+#define GSL_DBGFLAGS_BIST               0x00000040
+#define GSL_DBGFLAGS_PM4                0x00000080
+#define GSL_DBGFLAGS_PM4MEM             0x00000100
+#define GSL_DBGFLAGS_PM4CHECK           0x00000200
+#define GSL_DBGFLAGS_DUMPX              0x00000400
+#define GSL_DBGFLAGS_DUMPX_WITHOUT_IFH  0x00000800
+#define GSL_DBGFLAGS_IFH                0x00001000
+#define GSL_DBGFLAGS_NULL               0x00002000
+
+
+//////////////////////////////////////////////////////////////////////////////
+// generic flag values
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_FLAGS_NORMALMODE            0x00000000
+#define GSL_FLAGS_SAFEMODE              0x00000001
+#define GSL_FLAGS_INITIALIZED0          0x00000002
+#define GSL_FLAGS_INITIALIZED           0x00000004
+#define GSL_FLAGS_STARTED               0x00000008
+#define GSL_FLAGS_ACTIVE                0x00000010
+#define GSL_FLAGS_RESERVED0             0x00000020
+#define GSL_FLAGS_RESERVED1             0x00000040
+#define GSL_FLAGS_RESERVED2             0x00000080
+
+
+//////////////////////////////////////////////////////////////////////////////
+// power flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_PWRFLAGS_POWER_OFF          0x00000001
+#define GSL_PWRFLAGS_POWER_ON           0x00000002
+#define GSL_PWRFLAGS_CLK_ON             0x00000004
+#define GSL_PWRFLAGS_CLK_OFF            0x00000008
+#define GSL_PWRFLAGS_OVERRIDE_ON        0x00000010
+#define GSL_PWRFLAGS_OVERRIDE_OFF       0x00000020
+
+//////////////////////////////////////////////////////////////////////////////
+// DMI flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_DMIFLAGS_ENABLE_SINGLE      0x00000001  //  Single buffered DMI
+#define GSL_DMIFLAGS_ENABLE_DOUBLE      0x00000002  //  Double buffered DMI
+#define GSL_DMIFLAGS_ENABLE_TRIPLE      0x00000004  //  Triple buffered DMI
+#define GSL_DMIFLAGS_DISABLE            0x00000008
+#define GSL_DMIFLAGS_NEXT_BUFFER        0x00000010
+
+//////////////////////////////////////////////////////////////////////////////
+// cache flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_CACHEFLAGS_CLEAN            0x00000001  /* flush cache          */
+#define GSL_CACHEFLAGS_INVALIDATE       0x00000002  /* invalidate cache     */
+#define GSL_CACHEFLAGS_WRITECLEAN       0x00000004  /* flush write cache    */
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  context
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_CONTEXT_MAX             20
+#define GSL_CONTEXT_NONE            0
+#define GSL_CONTEXT_SAVE_GMEM       1
+#define GSL_CONTEXT_NO_GMEM_ALLOC   2
+
+
+//////////////////////////////////////////////////////////////////////////////
+// other
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_TIMEOUT_NONE                        0
+#define GSL_TIMEOUT_DEFAULT                     0xFFFFFFFF
+
+#ifdef _LINUX
+#define GSL_PAGESIZE                            PAGE_SIZE
+#define GSL_PAGESIZE_SHIFT                      PAGE_SHIFT
+#else
+#define GSL_PAGESIZE                            0x1000
+#define GSL_PAGESIZE_SHIFT                      12
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+typedef unsigned int        gsl_devhandle_t;
+typedef unsigned int        gsl_ctxthandle_t;
+typedef int                 gsl_timestamp_t;
+typedef unsigned int        gsl_flags_t;
+typedef unsigned int        gpuaddr_t;
+
+// ---------
+// device id
+// ---------
+typedef enum _gsl_deviceid_t
+{
+    GSL_DEVICE_ANY    = 0,
+    GSL_DEVICE_YAMATO = 1,
+    GSL_DEVICE_G12    = 2,
+    GSL_DEVICE_MAX    = 2,
+
+    GSL_DEVICE_FOOBAR = 0x7FFFFFFF
+} gsl_deviceid_t;
+
+// ----------------
+// chip revision id
+// ----------------
+//
+// coreid:8 majorrev:8 minorrev:8 patch:8
+// 
+// coreid = 0x00 = YAMATO_DX
+// coreid = 0x80 = G12
+//
+
+#define COREID(x)   ((((unsigned int)x & 0xFF) << 24))
+#define MAJORID(x)  ((((unsigned int)x & 0xFF) << 16))
+#define MINORID(x)  ((((unsigned int)x & 0xFF) <<  8))
+#define PATCHID(x)  ((((unsigned int)x & 0xFF) <<  0))
+
+typedef enum _gsl_chipid_t
+{
+    GSL_CHIPID_YAMATODX_REV13   = (COREID(0x00) | MAJORID(0x01) | MINORID(0x03) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV14   = (COREID(0x00) | MAJORID(0x01) | MINORID(0x04) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV20   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x00) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV21   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x01) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV211  = (COREID(0x00) | MAJORID(0x02) | MINORID(0x01) | PATCHID(0x01)),
+    GSL_CHIPID_YAMATODX_REV22   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x02) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV23   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x03) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV231  = (COREID(0x00) | MAJORID(0x02) | MINORID(0x03) | PATCHID(0x01)),
+    GSL_CHIPID_YAMATODX_REV24   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x04) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV25   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x05) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV251  = (COREID(0x00) | MAJORID(0x02) | MINORID(0x05) | PATCHID(0x01)),
+    GSL_CHIPID_G12_REV00        = (int)(COREID(0x80) | MAJORID(0x00) | MINORID(0x00) | PATCHID(0x00)),
+    GSL_CHIPID_ERROR            = (int)0xFFFFFFFF
+
+} gsl_chipid_t;
+
+#undef COREID
+#undef MAJORID
+#undef MINORID
+#undef PATCHID
+
+// -----------
+// device info
+// -----------
+typedef struct _gsl_devinfo_t {
+
+    gsl_deviceid_t  device_id;          // ID of this device
+    gsl_chipid_t    chip_id;
+    int             mmu_enabled;        // mmu address translation enabled
+    unsigned int    gmem_gpubaseaddr;
+    void *          gmem_hostbaseaddr;  // if gmem_hostbaseaddr is NULL, we would know its not mapped into mmio space
+    unsigned int    gmem_sizebytes;
+
+} gsl_devinfo_t;
+
+// -------------------
+// device memory store
+// -------------------
+typedef struct _gsl_devmemstore_t {
+    volatile unsigned int  soptimestamp;
+    unsigned int           sbz;
+    volatile unsigned int  eoptimestamp;
+    unsigned int           sbz2;
+} gsl_devmemstore_t;
+
+#define GSL_DEVICE_MEMSTORE_OFFSET(field)       offsetof(gsl_devmemstore_t, field)
+
+// -----------
+// aperture id
+// -----------
+typedef enum _gsl_apertureid_t
+{
+    GSL_APERTURE_EMEM   = (GSL_MEMFLAGS_EMEM),
+    GSL_APERTURE_PHYS   = (GSL_MEMFLAGS_CONPHYS >> GSL_MEMFLAGS_APERTURE_SHIFT),
+    GSL_APERTURE_MMU    = (GSL_APERTURE_EMEM | 0x10000000),
+    GSL_APERTURE_MAX    = 2,
+
+    GSL_APERTURE_FOOBAR = 0x7FFFFFFF
+} gsl_apertureid_t;
+
+// ----------
+// channel id
+// ----------
+typedef enum _gsl_channelid_t
+{
+    GSL_CHANNEL_1      = (GSL_MEMFLAGS_CHANNEL1 >> GSL_MEMFLAGS_CHANNEL_SHIFT),
+    GSL_CHANNEL_2      = (GSL_MEMFLAGS_CHANNEL2 >> GSL_MEMFLAGS_CHANNEL_SHIFT),
+    GSL_CHANNEL_3      = (GSL_MEMFLAGS_CHANNEL3 >> GSL_MEMFLAGS_CHANNEL_SHIFT),
+    GSL_CHANNEL_4      = (GSL_MEMFLAGS_CHANNEL4 >> GSL_MEMFLAGS_CHANNEL_SHIFT),
+    GSL_CHANNEL_MAX    = 4,
+
+    GSL_CHANNEL_FOOBAR = 0x7FFFFFFF
+} gsl_channelid_t;
+
+// ----------------------
+// page access permission
+// ----------------------
+typedef enum _gsl_ap_t
+{
+    GSL_AP_NULL   = 0x0,
+    GSL_AP_R      = 0x1,
+    GSL_AP_W      = 0x2,
+    GSL_AP_RW     = 0x3,
+    GSL_AP_X      = 0x4,
+    GSL_AP_RWX    = 0x5,
+    GSL_AP_MAX    = 0x6,
+
+    GSL_AP_FOOBAR = 0x7FFFFFFF
+} gsl_ap_t;
+
+// -------------
+// memory region
+// -------------
+typedef struct _gsl_memregion_t {
+    unsigned char  *mmio_virt_base;
+    unsigned int   mmio_phys_base;
+    gpuaddr_t      gpu_base;
+    unsigned int   sizebytes;
+} gsl_memregion_t;
+
+// ------------------------
+// shared memory allocation
+// ------------------------
+typedef struct _gsl_memdesc_t {
+    void          *hostptr;
+    gpuaddr_t      gpuaddr;
+    int            size;
+    unsigned int   priv;                // private
+    unsigned int   priv2;               // private
+
+} gsl_memdesc_t;
+
+// ---------------------------------
+// physical page scatter/gatter list
+// ---------------------------------
+typedef struct _gsl_scatterlist_t {
+    int           contiguous;       // flag whether pages on the list are physically contiguous
+    unsigned int  num;
+    unsigned int  *pages;
+} gsl_scatterlist_t;
+
+// --------------
+// mem free queue
+// --------------
+//
+// this could be compressed down into the just the memdesc for the node
+//
+typedef struct _gsl_memnode_t {
+    gsl_timestamp_t       timestamp;
+    gsl_memdesc_t         memdesc;
+    unsigned int          pid;
+    struct _gsl_memnode_t *next;
+} gsl_memnode_t;
+
+typedef struct _gsl_memqueue_t {
+    gsl_memnode_t   *head;
+    gsl_memnode_t   *tail;
+} gsl_memqueue_t;
+
+// ------------
+// timestamp id
+// ------------
+typedef enum _gsl_timestamp_type_t
+{
+    GSL_TIMESTAMP_CONSUMED = 1, // start-of-pipeline timestamp
+    GSL_TIMESTAMP_RETIRED  = 2, // end-of-pipeline timestamp
+    GSL_TIMESTAMP_MAX      = 2,
+
+    GSL_TIMESTAMP_FOOBAR   = 0x7FFFFFFF
+} gsl_timestamp_type_t;
+
+// ------------
+// context type
+// ------------
+typedef enum _gsl_context_type_t
+{
+    GSL_CONTEXT_TYPE_GENERIC = 1,
+    GSL_CONTEXT_TYPE_OPENGL  = 2,
+    GSL_CONTEXT_TYPE_OPENVG  = 3,
+
+    GSL_CONTEXT_TYPE_FOOBAR  = 0x7FFFFFFF
+} gsl_context_type_t;
+
+// ---------
+// rectangle
+// ---------
+typedef struct _gsl_rect_t {
+    unsigned int x;
+    unsigned int y;
+    unsigned int width;
+    unsigned int height;
+} gsl_rect_t;
+
+// -----------------------
+// pixel buffer descriptor
+// -----------------------
+typedef struct _gsl_buffer_desc_t {
+    gsl_memdesc_t data;
+    unsigned int stride_bytes;
+    unsigned int bpp;
+    unsigned int enabled;
+} gsl_buffer_desc_t;
+
+// ---------------------
+// command window target
+// ---------------------
+typedef enum _gsl_cmdwindow_t
+{
+    GSL_CMDWINDOW_MIN     = 0x00000000,
+    GSL_CMDWINDOW_2D      = 0x00000000,
+    GSL_CMDWINDOW_3D      = 0x00000001,     // legacy
+    GSL_CMDWINDOW_MMU     = 0x00000002,
+    GSL_CMDWINDOW_ARBITER = 0x000000FF,
+    GSL_CMDWINDOW_MAX     = 0x000000FF,
+
+    GSL_CMDWINDOW_FOOBAR  = 0x7FFFFFFF
+} gsl_cmdwindow_t;
+
+// ------------
+// interrupt id
+// ------------
+typedef enum _gsl_intrid_t
+{
+  GSL_INTR_YDX_MH_AXI_READ_ERROR = 0,
+  GSL_INTR_YDX_MH_AXI_WRITE_ERROR,
+  GSL_INTR_YDX_MH_MMU_PAGE_FAULT,
+
+  GSL_INTR_YDX_CP_SW_INT,
+  GSL_INTR_YDX_CP_T0_PACKET_IN_IB,
+  GSL_INTR_YDX_CP_OPCODE_ERROR,
+  GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR,
+  GSL_INTR_YDX_CP_RESERVED_BIT_ERROR,
+  GSL_INTR_YDX_CP_IB_ERROR,
+  GSL_INTR_YDX_CP_IB2_INT,
+  GSL_INTR_YDX_CP_IB1_INT,
+  GSL_INTR_YDX_CP_RING_BUFFER,
+
+  GSL_INTR_YDX_RBBM_READ_ERROR,
+  GSL_INTR_YDX_RBBM_DISPLAY_UPDATE,
+  GSL_INTR_YDX_RBBM_GUI_IDLE,
+
+  GSL_INTR_YDX_SQ_PS_WATCHDOG,
+  GSL_INTR_YDX_SQ_VS_WATCHDOG,
+
+  GSL_INTR_G12_MH,
+  GSL_INTR_G12_G2D,
+  GSL_INTR_G12_FIFO,
+#ifndef _Z180
+  GSL_INTR_G12_FBC,
+#endif // _Z180
+
+  GSL_INTR_G12_MH_AXI_READ_ERROR,
+  GSL_INTR_G12_MH_AXI_WRITE_ERROR,
+  GSL_INTR_G12_MH_MMU_PAGE_FAULT,
+
+  GSL_INTR_COUNT,
+
+  GSL_INTR_FOOBAR = 0x7FFFFFFF
+} gsl_intrid_t;
+
+#endif  // __GSL_TYPES_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_utils.h b/drivers/mxc/amd-gpu/include/api/gsl_utils.h
new file mode 100644
index 000000000000..1078b634173d
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_utils.h
@@ -0,0 +1,43 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_UTILS_H
+#define __GSL_UTILS_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_QUADPOW2_TO_SIZEBYTES(quadpow2)     (8 << (quadpow2))
+#define GSL_QUADPOW2_TO_SIZEDWORDS(quadpow2)    (2 << (quadpow2))
+#define GSL_POW2TEST(size)                      ((size) && !((size) & ((size) - 1)))
+#define GSL_POW2ALIGN_DOWN(addr, alignsize)     ((addr) & ~((alignsize) - 1));
+#define GSL_POW2ALIGN_UP(addr, alignsize)       (((addr) + ((alignsize) - 1)) & ~((alignsize) - 1))
+
+
+#endif  // __GSL_UTILS_H
diff --git a/drivers/mxc/amd-gpu/include/gsl.h b/drivers/mxc/amd-gpu/include/gsl.h
new file mode 100644
index 000000000000..07d8e97dcee3
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl.h
@@ -0,0 +1,79 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_H
+#define __GSL_H
+
+//#define __KGSLLIB_EXPORTS
+#define __KERNEL_MODE__
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  forward typedefs
+//////////////////////////////////////////////////////////////////////////////
+//struct _gsl_device_t;
+typedef struct _gsl_device_t    gsl_device_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  includes
+//////////////////////////////////////////////////////////////////////////////
+#include "gsl_buildconfig.h"
+
+#include "kos_libapi.h"
+
+#include "gsl_klibapi.h"
+
+#ifdef GSL_BLD_YAMATO
+#include <reg/yamato.h>
+
+#include "gsl_pm4types.h"
+#include "gsl_utils.h"
+#include "gsl_drawctxt.h"
+#include "gsl_ringbuffer.h"
+#endif
+
+#ifdef GSL_BLD_G12
+#include <reg/g12_reg.h>
+
+#include "gsl_cmdwindow.h"
+#endif
+
+#include "gsl_debug.h"
+#include "gsl_mmu.h"
+#include "gsl_memmgr.h"
+#include "gsl_sharedmem.h"
+#include "gsl_intrmgr.h"
+#include "gsl_cmdstream.h"
+#include "gsl_device.h"
+#include "gsl_driver.h"
+#include "gsl_log.h"
+
+#include "gsl_config.h"
+
+#endif // __GSL_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_cmdstream.h b/drivers/mxc/amd-gpu/include/gsl_cmdstream.h
new file mode 100644
index 000000000000..550d5d0005ab
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_cmdstream.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_CMDSTREAM_H
+#define __GSL_CMDSTREAM_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+
+#ifdef VG_HDK
+#define GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, data)
+#else
+#define GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, data)   kgsl_sharedmem_read0(&device->memstore, (data), GSL_DEVICE_MEMSTORE_OFFSET(soptimestamp), 4, false)
+#endif
+
+#ifdef VG_HDK
+#define GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, data)   (*((int*)data) = (gsl_driver.device[GSL_DEVICE_G12-1]).timestamp)
+#else
+#define GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, data)   kgsl_sharedmem_read0(&device->memstore, (data), GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), 4, false)
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+gsl_timestamp_t kgsl_cmdstream_readtimestamp0(gsl_deviceid_t device_id, gsl_timestamp_type_t type);
+void kgsl_cmdstream_memqueue_drain(gsl_device_t *device);
+int kgsl_cmdstream_init(gsl_device_t *device);
+int kgsl_cmdstream_close(gsl_device_t *device);
+
+#endif  // __GSL_CMDSTREAM_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h b/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h
new file mode 100644
index 000000000000..0152dd75a631
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h
@@ -0,0 +1,51 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_CMDWINDOW_H
+#define __GSL_CMDWINDOW_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// defines
+//////////////////////////////////////////////////////////////////////////////
+#ifndef _Z180
+#define GSL_G12_INTR_COUNT                  4
+#else
+#define GSL_G12_INTR_COUNT                  3
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int     kgsl_cmdwindow_init(gsl_device_t *device);
+int     kgsl_cmdwindow_close(gsl_device_t *device);
+int     kgsl_cmdwindow_write0(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data);
+
+#endif // __GSL_CMDWINDOW_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_context.h b/drivers/mxc/amd-gpu/include/gsl_context.h
new file mode 100644
index 000000000000..6e83bdb34036
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_context.h
@@ -0,0 +1,45 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_CONTEXT_H
+#define __GSL_CONTEXT_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+#endif  // __GSL_CONTEXT_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_debug.h b/drivers/mxc/amd-gpu/include/gsl_debug.h
new file mode 100644
index 000000000000..1275278f9eae
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_debug.h
@@ -0,0 +1,126 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DEBUG_H
+#define __GSL_DEBUG_H
+
+#ifdef BB_DUMPX
+#include "dumpx.h"
+#endif
+
+#ifdef TBDUMP
+#include "gsl_tbdump.h"
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  macros
+//////////////////////////////////////////////////////////////////////////////
+#ifdef _DEBUG
+#define KGSL_DEBUG(flag, action)                            if (gsl_driver.flags_debug & flag) {action;}
+#ifdef GSL_BLD_YAMATO
+#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords)                Yamato_DumpPM4((cmds), (sizedwords))
+#define KGSL_DEBUG_DUMPREGWRITE(addr, value)                Yamato_DumpRegisterWrite((addr), (value))
+#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data)      Yamato_DumpWriteMemory(addr, sizebytes, data)
+#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value)       Yamato_DumpSetMemory(addr, sizebytes, value)
+#define KGSL_DEBUG_DUMPFBSTART(device)                      Yamato_DumpFbStart(device)
+#define KGSL_DEBUG_DUMPREGSPACE(device)                     Yamato_DumpRegSpace(device)
+#define KGSL_DEBUG_DUMPWINDOW(addr, width, height)          Yamato_DumpWindow(addr, width, height)
+#else
+#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords)                
+#define KGSL_DEBUG_DUMPREGWRITE(addr, value)                
+#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data)      
+#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value)       
+#define KGSL_DEBUG_DUMPFBSTART(device)                      
+#define KGSL_DEBUG_DUMPREGSPACE(device)
+#define KGSL_DEBUG_DUMPWINDOW(addr, width, height)          
+#endif
+#ifdef TBDUMP
+
+#define KGSL_DEBUG_TBDUMP_OPEN(filename)                    tbdump_open(filename)
+#define KGSL_DEBUG_TBDUMP_CLOSE()                           tbdump_close()
+#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes)     tbdump_syncmem((unsigned int)addr, (unsigned int)src, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes)    tbdump_setmem((unsigned int)addr, value, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value)           tbdump_slavewrite(addr, value)
+#define KGSL_DEBUG_TBDUMP_WAITIRQ()                         tbdump_waitirq()
+
+#else
+#define KGSL_DEBUG_TBDUMP_OPEN(file)
+#define KGSL_DEBUG_TBDUMP_CLOSE()
+#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value)
+#define KGSL_DEBUG_TBDUMP_WAITIRQ()
+#endif
+#ifdef BB_DUMPX
+#define KGSL_DEBUG_DUMPX_OPEN(filename, param)              dumpx_open((filename), (param))
+#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment)    dumpx(cmd, (par1), (par2), (par3), (comment))
+#define KGSL_DEBUG_DUMPX_CLOSE()                            dumpx_close()
+#else
+#define KGSL_DEBUG_DUMPX_OPEN(filename, param)
+#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment)
+#define KGSL_DEBUG_DUMPX_CLOSE()
+#endif
+#else
+#define KGSL_DEBUG(flag, action)
+#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords)
+#define KGSL_DEBUG_DUMPREGWRITE(addr, value)
+#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data)
+#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value)
+#define KGSL_DEBUG_DUMPFBSTART(device)
+#define KGSL_DEBUG_DUMPREGSPACE(device)
+#define KGSL_DEBUG_DUMPWINDOW(addr, width, height)
+#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment)
+
+#define KGSL_DEBUG_TBDUMP_OPEN(file)
+#define KGSL_DEBUG_TBDUMP_CLOSE()
+#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value)
+#define KGSL_DEBUG_TBDUMP_WAITIRQ()
+#endif // _DEBUG
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+#ifdef GSL_BLD_YAMATO
+void            Yamato_DumpPM4(unsigned int *cmds, unsigned int sizedwords);
+void            Yamato_DumpRegisterWrite(unsigned int dwAddress, unsigned int value);
+void            Yamato_DumpWriteMemory(unsigned int dwAddress, unsigned int dwSize, void* pData);
+void            Yamato_DumpSetMemory(unsigned int dwAddress, unsigned int dwSize, unsigned int pData);
+void            Yamato_DumpFbStart(gsl_device_t *device);
+void            Yamato_DumpRegSpace(gsl_device_t *device);
+#ifdef _WIN32
+void            Yamato_DumpWindow(unsigned int addr, unsigned int width, unsigned int height);
+#endif
+#endif
+#ifdef _DEBUG
+int             kgsl_dumpx_parse_ibs(gpuaddr_t gpuaddr, int sizedwords);
+#endif //_DEBUG
+#endif // __GSL_DRIVER_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_device.h b/drivers/mxc/amd-gpu/include/gsl_device.h
new file mode 100644
index 000000000000..433dc6963dfd
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_device.h
@@ -0,0 +1,142 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DEVICE_H
+#define __GSL_DEVICE_H
+
+#ifdef _LINUX
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// --------------
+// function table
+// --------------
+typedef struct _gsl_functable_t {
+    int (*device_init)            (gsl_device_t *device);
+    int (*device_close)           (gsl_device_t *device);
+    int (*device_destroy)         (gsl_device_t *device);
+    int (*device_start)           (gsl_device_t *device, gsl_flags_t flags);
+    int (*device_stop)            (gsl_device_t *device);
+    int (*device_getproperty)     (gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes);
+    int (*device_setproperty)     (gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes);
+    int (*device_idle)            (gsl_device_t *device, unsigned int timeout);
+    int (*device_regread)         (gsl_device_t *device, unsigned int offsetwords, unsigned int *value);
+    int (*device_regwrite)        (gsl_device_t *device, unsigned int offsetwords, unsigned int value);
+    int (*device_waitirq)         (gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout);
+	int (*device_waittimestamp)   (gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout);
+    int (*device_runpending)      (gsl_device_t *device);
+    int (*device_addtimestamp)    (gsl_device_t *device_id, gsl_timestamp_t *timestamp);
+    int (*intr_isr)               (gsl_device_t *device);
+	int (*mmu_tlbinvalidate)      (gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid);
+	int (*mmu_setpagetable)       (gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid);
+    int (*cmdstream_issueibcmds)  (gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags);
+    int (*context_create)         (gsl_device_t *device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags);
+    int (*context_destroy)        (gsl_device_t *device_id, unsigned int drawctxt_id);
+} gsl_functable_t;
+
+// -------------
+// device object 
+// -------------
+struct _gsl_device_t {
+
+    unsigned int      refcnt;
+    unsigned int      callerprocess[GSL_CALLER_PROCESS_MAX];    // caller process table
+    gsl_functable_t   ftbl;
+    gsl_flags_t       flags;
+    gsl_deviceid_t    id;
+    unsigned int      chip_id;
+    gsl_memregion_t   regspace;
+    gsl_intr_t        intr;
+    gsl_memdesc_t     memstore;
+    gsl_memqueue_t    memqueue; // queue of memfrees pending timestamp elapse 
+
+#ifdef  GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+    unsigned int      memstoreshadow[GSL_CALLER_PROCESS_MAX];
+#endif // GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+
+#ifndef GSL_NO_MMU
+    gsl_mmu_t         mmu;
+#endif // GSL_NO_MMU
+
+#ifdef GSL_BLD_YAMATO
+    gsl_memregion_t   gmemspace;
+    gsl_ringbuffer_t  ringbuffer;
+    unsigned int      drawctxt_count;
+    gsl_drawctxt_t    *drawctxt_active;
+    gsl_drawctxt_t    drawctxt[GSL_CONTEXT_MAX];
+#endif // GSL_BLD_YAMATO
+
+#ifdef GSL_BLD_G12
+    unsigned int      intrcnt[GSL_G12_INTR_COUNT];
+    gsl_timestamp_t   current_timestamp;
+    gsl_timestamp_t   timestamp;
+#ifndef _LINUX	
+    unsigned int      irq_thread;
+    oshandle_t        irq_thread_handle;
+#endif
+#ifdef IRQTHREAD_POLL
+    oshandle_t        irqthread_event;
+#endif
+#endif // GSL_BLD_G12
+#ifndef _LINUX	
+    oshandle_t        timestamp_event;
+#else
+	wait_queue_head_t timestamp_waitq;
+	struct workqueue_struct	*irq_workq;
+	struct work_struct irq_work;	
+#endif
+    void              *autogate;
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int     kgsl_device_init(gsl_device_t *device, gsl_deviceid_t device_id);
+int     kgsl_device_close(gsl_device_t *device);
+int     kgsl_device_destroy(gsl_device_t *device);
+int     kgsl_device_attachcallback(gsl_device_t *device, unsigned int pid);
+int     kgsl_device_detachcallback(gsl_device_t *device, unsigned int pid);
+int     kgsl_device_runpending(gsl_device_t *device);
+
+int     kgsl_yamato_getfunctable(gsl_functable_t *ftbl);
+int     kgsl_g12_getfunctable(gsl_functable_t *ftbl);
+
+int kgsl_clock(gsl_deviceid_t dev, int enable);
+int kgsl_device_active(gsl_device_t *dev);
+int kgsl_device_clock(gsl_deviceid_t id, int enable);
+int kgsl_device_autogate_init(gsl_device_t *dev);
+void kgsl_device_autogate_exit(gsl_device_t *dev);
+
+
+#endif  // __GSL_DEVICE_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_display.h b/drivers/mxc/amd-gpu/include/gsl_display.h
new file mode 100644
index 000000000000..82300647b3ef
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_display.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DISPLAY_H
+#define __GSL_DISPLAY_H
+
+#define __GSLDISPLAY_EXPORTS
+
+#include "gsl_libapi.h"
+#include "gsl_klibapi.h"    // hack to enable direct reg write
+#include "gsl_displayapi.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_LIB_MAXDISPLAYS     1
+#define GSL_LIB_MAXSURFACES     3
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+typedef struct _gsl_display_t {
+    int                   numdisplays;
+    gsl_displaymode_t     mode[GSL_LIB_MAXDISPLAYS];
+    gsl_devhandle_t       devhandle;
+} gsl_display_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int     gsl_display_hitachi_240x320_tft_init(int display_id);
+int     gsl_display_toshiba_640x480_tft_init(int display_id);
+
+#endif // __GSL_DISPLAY_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_drawctxt.h b/drivers/mxc/amd-gpu/include/gsl_drawctxt.h
new file mode 100644
index 000000000000..15b8097828af
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_drawctxt.h
@@ -0,0 +1,110 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DRAWCTXT_H
+#define __GSL_DRAWCTXT_H
+
+//////////////////////////////////////////////////////////////////////////////
+// Flags
+//////////////////////////////////////////////////////////////////////////////
+
+#define CTXT_FLAGS_NOT_IN_USE       0x00000000
+#define CTXT_FLAGS_IN_USE           0x00000001
+
+#define CTXT_FLAGS_STATE_SHADOW     0x00000010  // state shadow memory allocated
+
+#define CTXT_FLAGS_GMEM_SHADOW      0x00000100  // gmem shadow memory allocated
+#define CTXT_FLAGS_GMEM_SAVE        0x00000200  // gmem must be copied to shadow
+#define CTXT_FLAGS_GMEM_RESTORE     0x00000400  // gmem can be restored from shadow
+
+#define CTXT_FLAGS_SHADER_SAVE      0x00002000  // shader must be copied to shadow
+#define CTXT_FLAGS_SHADER_RESTORE   0x00004000  // shader can be restored from shadow
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// ------------
+// draw context
+// ------------
+
+typedef struct _gmem_shadow_t
+{
+    gsl_memdesc_t   gmemshadow;     // Shadow buffer address
+
+    // 256 KB GMEM surface = 4 bytes-per-pixel x 256 pixels/row x 256 rows.
+    // width & height must be a multiples of 32, in case tiled textures are used.
+    unsigned int    size;       // Size of surface used to store GMEM
+    unsigned int    width;          // Width of surface used to store GMEM
+    unsigned int    height;         // Height of surface used to store GMEM
+    unsigned int    pitch;          // Pitch of surface used to store GMEM
+    int             offset;
+    unsigned int    offset_x;
+    unsigned int    offset_y;
+    unsigned int    gmem_offset_x;
+    unsigned int    gmem_offset_y;
+
+    unsigned int*   gmem_save_commands;
+    unsigned int*   gmem_restore_commands;
+    unsigned int    gmem_save[3];
+    unsigned int    gmem_restore[3];
+
+    gsl_memdesc_t   quad_vertices;
+    gsl_memdesc_t   quad_texcoords;
+} gmem_shadow_t;
+
+#define GSL_MAX_GMEM_SHADOW_BUFFERS 2
+
+typedef struct _gsl_drawctxt_t {
+	unsigned int        pid;
+    gsl_flags_t         flags;
+    gsl_context_type_t  type;
+    gsl_memdesc_t       gpustate;
+    
+    unsigned int        reg_save[3];
+    unsigned int        reg_restore[3];
+    unsigned int        shader_save[3];
+    unsigned int        shader_fixup[3];
+    unsigned int        shader_restore[3];
+    unsigned int        chicken_restore[3];
+    gmem_shadow_t       context_gmem_shadow;    // Information of the GMEM shadow that is created in context create
+    gmem_shadow_t       user_gmem_shadow[GSL_MAX_GMEM_SHADOW_BUFFERS]; // User defined GMEM shadow buffers
+} gsl_drawctxt_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int     kgsl_drawctxt_init(gsl_device_t *device);
+int     kgsl_drawctxt_close(gsl_device_t *device);
+int     kgsl_drawctxt_destroyall(gsl_device_t *device);
+void    kgsl_drawctxt_switch(gsl_device_t *device, gsl_drawctxt_t *drawctxt, gsl_flags_t flags);
+int     kgsl_drawctxt_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags);
+int     kgsl_drawctxt_destroy(gsl_device_t* device, unsigned int drawctxt_id);
+
+#endif  // __GSL_DRAWCTXT_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_driver.h b/drivers/mxc/amd-gpu/include/gsl_driver.h
new file mode 100644
index 000000000000..1e1d43da431d
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_driver.h
@@ -0,0 +1,105 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DRIVER_H
+#define __GSL_DRIVER_H
+
+
+/////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#ifdef GSL_DEDICATED_PROCESS
+#define GSL_CALLER_PROCESSID_GET()      kos_callerprocess_getid()
+#else
+#define GSL_CALLER_PROCESSID_GET()      kos_process_getid()
+#endif // GSL_DEDICATED_PROCESS
+
+#ifdef GSL_LOCKING_COURSEGRAIN
+#define GSL_API_MUTEX_CREATE()          gsl_driver.mutex = kos_mutex_create("gsl_global"); \
+                                        if (!gsl_driver.mutex) {return (GSL_FAILURE);}
+#define GSL_API_MUTEX_LOCK()            kos_mutex_lock(gsl_driver.mutex)
+#define GSL_API_MUTEX_UNLOCK()          kos_mutex_unlock(gsl_driver.mutex)
+#define GSL_API_MUTEX_FREE()            kos_mutex_free(gsl_driver.mutex); gsl_driver.mutex = 0;
+#else
+#define GSL_API_MUTEX_CREATE()
+#define GSL_API_MUTEX_LOCK()        
+#define GSL_API_MUTEX_UNLOCK()      
+#define GSL_API_MUTEX_FREE()
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+// -------------
+// driver object 
+// -------------
+typedef struct _gsl_driver_t {
+    gsl_flags_t      flags_debug;
+    int              refcnt;
+    unsigned int     callerprocess[GSL_CALLER_PROCESS_MAX]; // caller process table
+    oshandle_t       mutex;                                 // global API mutex
+    void             *hal;
+    gsl_sharedmem_t  shmem;
+    gsl_device_t     device[GSL_DEVICE_MAX];
+    int              dmi_state;     //  OS_TRUE = enabled, OS_FALSE otherwise
+    gsl_flags_t      dmi_mode;      //  single, double, or triple buffering
+    int              dmi_frame;     //  set to -1 when DMI is enabled
+    int              dmi_max_frame; //  indicates the maximum frame # that we will support
+} gsl_driver_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+// external variable declarations
+//////////////////////////////////////////////////////////////////////////////
+extern gsl_driver_t  gsl_driver;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  inline functions
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE int
+kgsl_driver_getcallerprocessindex(unsigned int pid, int *index)
+{
+    int  i;
+
+    // obtain index in caller process table
+    for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++)
+    {
+        if (gsl_driver.callerprocess[i] == pid)
+        {
+            *index = i;            
+            return (GSL_SUCCESS);
+        }
+    }
+
+    return (GSL_FAILURE);
+}
+
+#endif // __GSL_DRIVER_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_hal.h b/drivers/mxc/amd-gpu/include/gsl_hal.h
new file mode 100644
index 000000000000..8a8a10cfb862
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_hal.h
@@ -0,0 +1,143 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_HALAPI_H
+#define __GSL_HALAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+/*
+#include "gsl_buildconfig.h"
+#include "kos_libapi.h"
+#include "gsl_klibapi.h"
+#ifdef GSL_BLD_YAMATO
+#include <reg/yamato.h>
+#endif
+#ifdef GSL_BLD_G12
+#include <reg/g12_reg.h>
+#endif
+#include "gsl_hwaccess.h"
+*/
+
+#include "gsl.h"
+#include "gsl_hwaccess.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+// linkage
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __KGSLHAL_EXPORTS
+#define KGSLHAL_API                 OS_DLLEXPORT
+#else
+#define KGSLHAL_API
+#endif // __KGSLLIB_EXPORTS
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  version control                    
+//////////////////////////////////////////////////////////////////////////////
+#define KGSLHAL_NAME            "AMD GSL Kernel HAL"
+#define KGSLHAL_VERSION         "0.1"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_HAL_REG_READ(device_id, gpubase, offsetwords, value)    kgsl_hwaccess_regread(device_id, gpubase, (offsetwords), (value))
+#define GSL_HAL_REG_WRITE(device_id, gpubase, offsetwords, value)   kgsl_hwaccess_regwrite(device_id, gpubase, (offsetwords), (value))
+
+#define GSL_HAL_MEM_READ(dst, gpubase, gpuoffset, sizebytes, touserspace)        kgsl_hwaccess_memread(dst, gpubase, (gpuoffset), (sizebytes), touserspace)
+#define GSL_HAL_MEM_WRITE(gpubase, gpuoffset, src, sizebytes, fromuserspace)     kgsl_hwaccess_memwrite(gpubase, (gpuoffset), src, (sizebytes), fromuserspace)
+#define GSL_HAL_MEM_SET(gpubase, gpuoffset, value, sizebytes)                    kgsl_hwaccess_memset(gpubase, (gpuoffset), (value), (sizebytes))
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// -------------
+// device config
+// -------------
+typedef struct _gsl_devconfig_t {
+
+    gsl_memregion_t  regspace;
+
+    unsigned int     mmu_config;
+    gpuaddr_t        mpu_base;
+    int              mpu_range;
+    gpuaddr_t        va_base;
+    unsigned int     va_range;
+
+#ifdef GSL_BLD_YAMATO
+    gsl_memregion_t  gmemspace;
+#endif // GSL_BLD_YAMATO
+
+} gsl_devconfig_t;
+
+// ----------------------
+// memory aperture config
+// ----------------------
+typedef struct _gsl_apertureconfig_t
+{
+    gsl_apertureid_t  id;
+    gsl_channelid_t   channel;
+    unsigned int      hostbase;
+    unsigned int      gpubase;
+    unsigned int      sizebytes;
+} gsl_apertureconfig_t;
+
+// --------------------
+// shared memory config
+// --------------------
+typedef struct _gsl_shmemconfig_t 
+{
+    int                   numapertures;
+    gsl_apertureconfig_t  apertures[GSL_SHMEM_MAX_APERTURES];
+} gsl_shmemconfig_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  HAL API
+//////////////////////////////////////////////////////////////////////////////
+KGSLHAL_API int             kgsl_hal_init(void);
+KGSLHAL_API int             kgsl_hal_close(void);
+KGSLHAL_API int             kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config);
+KGSLHAL_API int             kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config);
+KGSLHAL_API int             kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value);
+KGSLHAL_API gsl_chipid_t    kgsl_hal_getchipid(gsl_deviceid_t device_id);
+KGSLHAL_API int             kgsl_hal_getplatformtype(char *platform);
+KGSLHAL_API int             kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]);
+KGSLHAL_API int             kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif  // __GSL_HALAPI_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_intrmgr.h b/drivers/mxc/amd-gpu/include/gsl_intrmgr.h
new file mode 100644
index 000000000000..f46f6d8e6a86
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_intrmgr.h
@@ -0,0 +1,104 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_INTRMGR_H
+#define __GSL_INTRMGR_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// -------------------------------------
+// block which can generate an interrupt
+// -------------------------------------
+typedef enum _gsl_intrblock_t
+{
+    GSL_INTR_BLOCK_YDX_MH = 0,
+    GSL_INTR_BLOCK_YDX_CP,
+    GSL_INTR_BLOCK_YDX_RBBM,
+    GSL_INTR_BLOCK_YDX_SQ,
+    GSL_INTR_BLOCK_G12,
+    GSL_INTR_BLOCK_G12_MH,
+
+    GSL_INTR_BLOCK_COUNT,
+} gsl_intrblock_t;
+
+// ------------------------
+// interrupt block register
+// ------------------------
+typedef struct _gsl_intrblock_reg_t
+{
+    gsl_intrblock_t  id;
+    gsl_intrid_t     first_id;
+    gsl_intrid_t     last_id;
+    unsigned int     status_reg;
+    unsigned int     clear_reg;
+    unsigned int     mask_reg;
+} gsl_intrblock_reg_t;
+
+// --------
+// callback
+// --------
+typedef void (*gsl_intr_callback_t)(gsl_intrid_t id, void *cookie);
+
+// -----------------
+// interrupt routine
+// -----------------
+typedef struct _gsl_intr_handler_t
+{
+    gsl_intr_callback_t callback;
+    void *              cookie;
+} gsl_intr_handler_t;
+
+// -----------------
+// interrupt manager
+// -----------------
+typedef struct _gsl_intr_t
+{
+    gsl_flags_t         flags;
+    gsl_device_t        *device;
+    unsigned int        enabled[GSL_INTR_BLOCK_COUNT];
+    gsl_intr_handler_t  handler[GSL_INTR_COUNT];
+    oshandle_t          evnt[GSL_INTR_COUNT];
+} gsl_intr_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int             kgsl_intr_init(gsl_device_t *device);
+int             kgsl_intr_close(gsl_device_t *device);
+int             kgsl_intr_attach(gsl_intr_t *intr, gsl_intrid_t id, gsl_intr_callback_t callback, void *cookie);
+int             kgsl_intr_detach(gsl_intr_t *intr, gsl_intrid_t id);
+int             kgsl_intr_enable(gsl_intr_t *intr, gsl_intrid_t id);
+int             kgsl_intr_disable(gsl_intr_t *intr, gsl_intrid_t id);
+int             kgsl_intr_isenabled(gsl_intr_t *intr, gsl_intrid_t id);
+void            kgsl_intr_decode(gsl_device_t *device, gsl_intrblock_t block_id);
+
+#endif  // __GSL_INTMGR_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_ioctl.h b/drivers/mxc/amd-gpu/include/gsl_ioctl.h
new file mode 100644
index 000000000000..0f1983e4c770
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_ioctl.h
@@ -0,0 +1,238 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _GSL_IOCTL_H
+#define _GSL_IOCTL_H
+
+#include "gsl_types.h"
+#include "gsl_properties.h"
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+typedef struct _kgsl_device_start_t {
+    gsl_deviceid_t  device_id;
+    gsl_flags_t flags;
+} kgsl_device_start_t;
+
+typedef struct _kgsl_device_stop_t {
+    gsl_deviceid_t  device_id;
+} kgsl_device_stop_t;
+
+typedef struct _kgsl_device_idle_t {
+    gsl_deviceid_t  device_id;
+    unsigned int    timeout;
+} kgsl_device_idle_t;
+
+typedef struct _kgsl_device_getproperty_t {
+    gsl_deviceid_t  device_id;
+    gsl_property_type_t type;
+    unsigned int    *value;
+    unsigned int    sizebytes;
+} kgsl_device_getproperty_t;
+
+typedef struct _kgsl_device_setproperty_t {
+    gsl_deviceid_t  device_id;
+    gsl_property_type_t type;
+    void        *value;
+    unsigned int    sizebytes;
+} kgsl_device_setproperty_t;
+
+typedef struct _kgsl_device_regread_t {
+    gsl_deviceid_t  device_id;
+    unsigned int    offsetwords;
+    unsigned int    *value;
+} kgsl_device_regread_t;
+
+typedef struct _kgsl_device_regwrite_t {
+    gsl_deviceid_t  device_id;
+    unsigned int    offsetwords;
+    unsigned int    value;
+} kgsl_device_regwrite_t;
+
+typedef struct _kgsl_device_waitirq_t {
+    gsl_deviceid_t  device_id;
+    gsl_intrid_t    intr_id;
+    unsigned int    *count;
+    unsigned int    timeout;
+} kgsl_device_waitirq_t;
+
+typedef struct _kgsl_cmdstream_issueibcmds_t {
+    gsl_deviceid_t  device_id;
+    int     drawctxt_index;
+    gpuaddr_t   ibaddr;
+    int     sizedwords;
+    gsl_timestamp_t *timestamp;
+    gsl_flags_t flags;
+} kgsl_cmdstream_issueibcmds_t;
+
+typedef struct _kgsl_cmdstream_readtimestamp_t {
+    gsl_deviceid_t  device_id;
+    gsl_timestamp_type_t    type;
+    gsl_timestamp_t *timestamp;
+} kgsl_cmdstream_readtimestamp_t;
+
+typedef struct _kgsl_cmdstream_freememontimestamp_t {
+    gsl_deviceid_t  device_id;
+    gsl_memdesc_t   *memdesc;
+    gsl_timestamp_t timestamp;
+    gsl_timestamp_type_t    type;
+} kgsl_cmdstream_freememontimestamp_t;
+
+typedef struct _kgsl_cmdstream_waittimestamp_t {
+    gsl_deviceid_t  device_id;
+	gsl_timestamp_t timestamp;
+    unsigned int    timeout;
+} kgsl_cmdstream_waittimestamp_t;
+
+typedef struct _kgsl_cmdwindow_write_t {
+    gsl_deviceid_t  device_id;
+    gsl_cmdwindow_t target;
+    unsigned int    addr;
+    unsigned int    data;
+} kgsl_cmdwindow_write_t;
+
+typedef struct _kgsl_context_create_t {
+    gsl_deviceid_t  device_id;
+    gsl_context_type_t  type;
+    unsigned int    *drawctxt_id;
+    gsl_flags_t flags;
+} kgsl_context_create_t;
+
+typedef struct _kgsl_context_destroy_t {
+    gsl_deviceid_t  device_id;
+    unsigned int    drawctxt_id;
+} kgsl_context_destroy_t;
+
+typedef struct _kgsl_drawctxt_bind_gmem_shadow_t {
+    gsl_deviceid_t device_id;
+    unsigned int drawctxt_id;
+    const gsl_rect_t* gmem_rect;
+    unsigned int shadow_x;
+    unsigned int shadow_y;
+    const gsl_buffer_desc_t* shadow_buffer;
+    unsigned int buffer_id;
+} kgsl_drawctxt_bind_gmem_shadow_t;
+
+typedef struct _kgsl_sharedmem_alloc_t {
+    gsl_deviceid_t  device_id;
+    gsl_flags_t flags;
+    int     sizebytes;
+    gsl_memdesc_t   *memdesc;
+} kgsl_sharedmem_alloc_t;
+
+typedef struct _kgsl_sharedmem_free_t {
+    gsl_memdesc_t   *memdesc;
+} kgsl_sharedmem_free_t;
+
+typedef struct _kgsl_sharedmem_read_t {
+    const gsl_memdesc_t *memdesc;
+    unsigned int    *dst;
+    unsigned int    offsetbytes;
+    unsigned int    sizebytes;
+} kgsl_sharedmem_read_t;
+
+typedef struct _kgsl_sharedmem_write_t {
+    const gsl_memdesc_t *memdesc;
+    unsigned int    offsetbytes;
+    unsigned int    *src;
+    unsigned int    sizebytes;
+} kgsl_sharedmem_write_t;
+
+typedef struct _kgsl_sharedmem_set_t {
+    const gsl_memdesc_t *memdesc;
+    unsigned int    offsetbytes;
+    unsigned int    value;
+    unsigned int    sizebytes;
+} kgsl_sharedmem_set_t;
+
+typedef struct _kgsl_sharedmem_largestfreeblock_t {
+    gsl_deviceid_t  device_id;
+    gsl_flags_t flags;
+    unsigned int    *largestfreeblock;
+} kgsl_sharedmem_largestfreeblock_t;
+
+typedef struct _kgsl_sharedmem_cacheoperation_t {
+    const gsl_memdesc_t *memdesc;
+    unsigned int    offsetbytes;
+    unsigned int    sizebytes;
+    unsigned int    operation;
+} kgsl_sharedmem_cacheoperation_t;
+
+typedef struct _kgsl_sharedmem_fromhostpointer_t {
+    gsl_deviceid_t  device_id;
+    gsl_memdesc_t   *memdesc;
+    void        *hostptr;
+} kgsl_sharedmem_fromhostpointer_t;
+
+typedef struct _kgsl_add_timestamp_t {
+    gsl_deviceid_t device_id;
+    gsl_timestamp_t *timestamp;
+} kgsl_add_timestamp_t;
+
+typedef struct _kgsl_device_clock_t {
+    gsl_deviceid_t device; /* GSL_DEVICE_YAMATO = 1, GSL_DEVICE_G12 = 2 */
+    int enable; /* 0: disable, 1: enable */
+} kgsl_device_clock_t;
+
+//////////////////////////////////////////////////////////////////////////////
+// ioctl numbers
+//////////////////////////////////////////////////////////////////////////////
+
+#define GSL_MAGIC                               0xF9
+#define IOCTL_KGSL_DEVICE_START                 _IOW(GSL_MAGIC, 0x20, struct _kgsl_device_start_t)
+#define IOCTL_KGSL_DEVICE_STOP                  _IOW(GSL_MAGIC, 0x21, struct _kgsl_device_stop_t)
+#define IOCTL_KGSL_DEVICE_IDLE                  _IOW(GSL_MAGIC, 0x22, struct _kgsl_device_idle_t)
+#define IOCTL_KGSL_DEVICE_GETPROPERTY           _IOWR(GSL_MAGIC, 0x23, struct _kgsl_device_getproperty_t)
+#define IOCTL_KGSL_DEVICE_SETPROPERTY           _IOW(GSL_MAGIC, 0x24, struct _kgsl_device_setproperty_t)
+#define IOCTL_KGSL_DEVICE_REGREAD               _IOWR(GSL_MAGIC, 0x25, struct _kgsl_device_regread_t)
+#define IOCTL_KGSL_DEVICE_REGWRITE              _IOW(GSL_MAGIC, 0x26, struct _kgsl_device_regwrite_t)
+#define IOCTL_KGSL_DEVICE_WAITIRQ               _IOWR(GSL_MAGIC, 0x27, struct _kgsl_device_waitirq_t)
+#define IOCTL_KGSL_CMDSTREAM_ISSUEIBCMDS        _IOWR(GSL_MAGIC, 0x28, struct _kgsl_cmdstream_issueibcmds_t)
+#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP      _IOWR(GSL_MAGIC, 0x29, struct _kgsl_cmdstream_readtimestamp_t)
+#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP _IOW(GSL_MAGIC, 0x2A, struct _kgsl_cmdstream_freememontimestamp_t)
+#define IOCTL_KGSL_CMDSTREAM_WAITTIMESTAMP      _IOW(GSL_MAGIC, 0x2B, struct _kgsl_cmdstream_waittimestamp_t)
+#define IOCTL_KGSL_CMDWINDOW_WRITE              _IOW(GSL_MAGIC, 0x2C, struct _kgsl_cmdwindow_write_t)
+#define IOCTL_KGSL_CONTEXT_CREATE               _IOWR(GSL_MAGIC, 0x2D, struct _kgsl_context_create_t)
+#define IOCTL_KGSL_CONTEXT_DESTROY              _IOW(GSL_MAGIC, 0x2E, struct _kgsl_context_destroy_t)
+#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW    _IOW(GSL_MAGIC, 0x2F, struct _kgsl_drawctxt_bind_gmem_shadow_t)
+#define IOCTL_KGSL_SHAREDMEM_ALLOC              _IOWR(GSL_MAGIC, 0x30, struct _kgsl_sharedmem_alloc_t)
+#define IOCTL_KGSL_SHAREDMEM_FREE               _IOW(GSL_MAGIC, 0x31, struct _kgsl_sharedmem_free_t)
+#define IOCTL_KGSL_SHAREDMEM_READ               _IOWR(GSL_MAGIC, 0x32, struct _kgsl_sharedmem_read_t)
+#define IOCTL_KGSL_SHAREDMEM_WRITE              _IOW(GSL_MAGIC, 0x33, struct _kgsl_sharedmem_write_t)
+#define IOCTL_KGSL_SHAREDMEM_SET                _IOW(GSL_MAGIC, 0x34, struct _kgsl_sharedmem_set_t)
+#define IOCTL_KGSL_SHAREDMEM_LARGESTFREEBLOCK   _IOWR(GSL_MAGIC, 0x35, struct _kgsl_sharedmem_largestfreeblock_t)
+#define IOCTL_KGSL_SHAREDMEM_CACHEOPERATION     _IOW(GSL_MAGIC, 0x36, struct _kgsl_sharedmem_cacheoperation_t)
+#define IOCTL_KGSL_SHAREDMEM_FROMHOSTPOINTER    _IOW(GSL_MAGIC, 0x37, struct _kgsl_sharedmem_fromhostpointer_t)
+#define IOCTL_KGSL_ADD_TIMESTAMP                _IOWR(GSL_MAGIC, 0x38, struct _kgsl_add_timestamp_t)
+#define IOCTL_KGSL_DRIVER_EXIT		        _IOWR(GSL_MAGIC, 0x39, NULL)
+#define IOCTL_KGSL_DEVICE_CLOCK			_IOWR(GSL_MAGIC, 0x60, struct _kgsl_device_clock_t)
+
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/gsl_log.h b/drivers/mxc/amd-gpu/include/gsl_log.h
new file mode 100644
index 000000000000..dbb7e4c6ef96
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_log.h
@@ -0,0 +1,74 @@
+/* Copyright (c) 2002,2008-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_LOG_H
+#define __GSL_LOG_H
+
+#define KGSL_LOG_GROUP_DRIVER       0x00000001
+#define KGSL_LOG_GROUP_DEVICE       0x00000002
+#define KGSL_LOG_GROUP_COMMAND      0x00000004
+#define KGSL_LOG_GROUP_CONTEXT      0x00000008
+#define KGSL_LOG_GROUP_MEMORY       0x00000010
+#define KGSL_LOG_GROUP_ALL          0x000000ff
+
+#define KGSL_LOG_LEVEL_ALL          0x0000ff00
+#define KGSL_LOG_LEVEL_TRACE        0x00003f00
+#define KGSL_LOG_LEVEL_DEBUG        0x00001f00
+#define KGSL_LOG_LEVEL_INFO         0x00000f00
+#define KGSL_LOG_LEVEL_WARN         0x00000700
+#define KGSL_LOG_LEVEL_ERROR        0x00000300
+#define KGSL_LOG_LEVEL_FATAL        0x00000100
+
+#define KGSL_LOG_TIMESTAMP          0x00010000
+#define KGSL_LOG_THREAD_ID          0x00020000
+#define KGSL_LOG_PROCESS_ID         0x00040000
+
+#ifdef GSL_LOG
+
+int kgsl_log_init(void);
+int kgsl_log_close(void);
+int kgsl_log_open_stdout( unsigned int log_flags );
+int kgsl_log_write( unsigned int log_flags, char* format, ... );
+int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags );
+int kgsl_log_open_file( char* filename, unsigned int log_flags );
+int kgsl_log_flush_membuf( char* filename, int memBufId );
+
+#else
+
+// Empty function definitions
+OSINLINE int kgsl_log_init(void) { return GSL_SUCCESS; }
+OSINLINE int kgsl_log_close(void) { return GSL_SUCCESS; }
+OSINLINE int kgsl_log_open_stdout( unsigned int log_flags ) { (void)log_flags; return GSL_SUCCESS; }
+OSINLINE int kgsl_log_write( unsigned int log_flags, char* format, ... ) { (void)log_flags; (void)format; return GSL_SUCCESS; }
+OSINLINE int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags ) { (void)memBufId; (void)log_flags; return GSL_SUCCESS; }
+OSINLINE int kgsl_log_open_file( char* filename, unsigned int log_flags ) { (void)filename; (void)log_flags; return GSL_SUCCESS; }
+OSINLINE int kgsl_log_flush_membuf( char* filename, int memBufId ) { (void) filename; (void) memBufId; return GSL_SUCCESS; }
+
+#endif
+
+#endif // __GSL_LOG_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_memmgr.h b/drivers/mxc/amd-gpu/include/gsl_memmgr.h
new file mode 100644
index 000000000000..ef9ad93ea96e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_memmgr.h
@@ -0,0 +1,122 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_MEMMGR_H
+#define __GSL_MEMMGR_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// defines
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMARENA_NODE_POOL_MAX      32                              // max is 32
+
+#define GSL_MEMARENA_PAGE_DIST_MAX      12                              // 4MB
+
+//#define GSL_MEMARENA_NODE_POOL_ENABLED
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// ------------------
+// memory arena stats
+// ------------------
+typedef struct _gsl_memarena_stats_t {
+    __int64  bytes_read;
+    __int64  bytes_written;
+    __int64  allocs_success;
+    __int64  allocs_fail;
+    __int64  frees;
+    __int64  allocs_pagedistribution[GSL_MEMARENA_PAGE_DIST_MAX]; // 0=0--(4K-1), 1=4--(8K-1), 2=8--(16K-1),... max-1=(GSL_PAGESIZE<<(max-1))--infinity
+    __int64  frees_pagedistribution[GSL_MEMARENA_PAGE_DIST_MAX];
+} gsl_memarena_stats_t;
+
+// ------------
+// memory block
+// ------------
+typedef struct _memblk_t {
+    unsigned int      blkaddr;
+    unsigned int      blksize;
+    struct _memblk_t  *next;
+    struct _memblk_t  *prev;
+    int               nodepoolindex;
+} memblk_t;
+
+// ----------------------
+// memory block free list
+// ----------------------
+typedef struct _gsl_freelist_t {
+    memblk_t  *head;
+    memblk_t  *allocrover;
+    memblk_t  *freerover;
+} gsl_freelist_t;
+
+// ----------------------
+// memory block node pool
+// ----------------------
+typedef struct _gsl_nodepool_t {
+    unsigned int            priv;
+    memblk_t                memblk[GSL_MEMARENA_NODE_POOL_MAX];
+    struct _gsl_nodepool_t  *next;
+    struct _gsl_nodepool_t  *prev;
+} gsl_nodepool_t;
+
+// -------------------
+// memory arena object
+// -------------------
+typedef struct _gsl_memarena_t {
+    oshandle_t      mutex;
+    unsigned int    gpubaseaddr;
+    unsigned int    hostbaseaddr;
+    unsigned int    sizebytes;
+    gsl_nodepool_t  *nodepool;
+    gsl_freelist_t  freelist;
+    unsigned int    priv;
+
+#ifdef GSL_STATS_MEM
+    gsl_memarena_stats_t  stats;
+#endif // GSL_STATS_MEM
+
+} gsl_memarena_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+gsl_memarena_t* kgsl_memarena_create(int aperture_id, int mmu_virtualized, unsigned int hostbaseaddr, gpuaddr_t gpubaseaddr, int sizebytes);
+int             kgsl_memarena_destroy(gsl_memarena_t *memarena);
+int             kgsl_memarena_isvirtualized(gsl_memarena_t *memarena);
+int             kgsl_memarena_querystats(gsl_memarena_t *memarena, gsl_memarena_stats_t *stats);
+int             kgsl_memarena_alloc(gsl_memarena_t *memarena, gsl_flags_t flags, int size, gsl_memdesc_t *memdesc);
+void            kgsl_memarena_free(gsl_memarena_t *memarena, gsl_memdesc_t *memdesc);
+void*           kgsl_memarena_gethostptr(gsl_memarena_t *memarena, gpuaddr_t gpuaddr);
+unsigned int    kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena, void *hostptr);
+unsigned int    kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena, gsl_flags_t flags);
+
+#endif  // __GSL_MEMMGR_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_mmu.h b/drivers/mxc/amd-gpu/include/gsl_mmu.h
new file mode 100644
index 000000000000..868c5156f290
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_mmu.h
@@ -0,0 +1,183 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_MMU_H
+#define __GSL_MMU_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// defines
+//////////////////////////////////////////////////////////////////////////////
+#ifdef GSL_STATS_MMU
+#define GSL_MMU_STATS(x) x
+#else
+#define GSL_MMU_STATS(x)
+#endif // GSL_STATS_MMU
+
+#ifdef GSL_MMU_PAGETABLE_PERPROCESS
+#define GSL_MMU_PAGETABLE_MAX               GSL_CALLER_PROCESS_MAX      // all device mmu's share a single page table per process
+#else
+#define GSL_MMU_PAGETABLE_MAX               1                           // all device mmu's share a single global page table
+#endif // GSL_MMU_PAGETABLE_PERPROCESS
+
+#define GSL_PT_SUPER_PTE                    8
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+#ifdef _DEBUG
+// ---------
+// mmu debug
+// ---------
+typedef struct _gsl_mmu_debug_t {
+    unsigned int  config;
+    unsigned int  mpu_base;
+    unsigned int  mpu_end;
+    unsigned int  va_range;
+    unsigned int  pt_base;
+    unsigned int  page_fault;
+    unsigned int  trans_error;
+    unsigned int  invalidate;
+} gsl_mmu_debug_t;
+#endif // _DEBUG
+
+// ------------
+// mmu register
+// ------------
+typedef struct _gsl_mmu_reg_t
+{
+    unsigned int  CONFIG;
+    unsigned int  MPU_BASE;
+    unsigned int  MPU_END;
+    unsigned int  VA_RANGE;
+    unsigned int  PT_BASE;
+    unsigned int  PAGE_FAULT;
+    unsigned int  TRAN_ERROR;
+    unsigned int  INVALIDATE;
+} gsl_mmu_reg_t;
+
+// ------------
+// mh interrupt
+// ------------
+typedef struct _gsl_mh_intr_t
+{
+    gsl_intrid_t  AXI_READ_ERROR;
+    gsl_intrid_t  AXI_WRITE_ERROR;
+    gsl_intrid_t  MMU_PAGE_FAULT;
+} gsl_mh_intr_t;
+
+// ----------------
+// page table stats
+// ----------------
+typedef struct _gsl_ptstats_t {
+    __int64  maps;
+    __int64  unmaps;
+	__int64  switches;
+} gsl_ptstats_t;
+
+// ---------
+// mmu stats
+// ---------
+typedef struct _gsl_mmustats_t {
+	gsl_ptstats_t  pt;
+	__int64        tlbflushes;
+} gsl_mmustats_t;
+
+// -----------------
+// page table object
+// -----------------
+typedef struct _gsl_pagetable_t {
+	unsigned int   pid;
+    unsigned int   refcnt;
+    gsl_memdesc_t  base;
+    gpuaddr_t      va_base;
+    unsigned int   va_range;
+    unsigned int   last_superpte;
+    unsigned int   max_entries;
+} gsl_pagetable_t;
+
+// -------------------------
+// tlb flush filter object
+// -------------------------
+typedef struct _gsl_tlbflushfilter_t {
+    unsigned int  *base;
+    unsigned int  size;
+} gsl_tlbflushfilter_t;
+
+// ----------
+// mmu object
+// ----------
+typedef struct _gsl_mmu_t {
+    unsigned int          refcnt;
+    gsl_flags_t           flags;
+    gsl_device_t          *device;
+    unsigned int          config;
+    gpuaddr_t             mpu_base;
+    int                   mpu_range;
+    gpuaddr_t             va_base;
+    unsigned int          va_range;
+    gsl_memdesc_t         dummyspace;
+    gsl_tlbflushfilter_t  tlbflushfilter;
+    gsl_pagetable_t       *hwpagetable;                     // current page table object being used by device mmu
+    gsl_pagetable_t       *pagetable[GSL_MMU_PAGETABLE_MAX];    // page table object table
+#ifdef GSL_STATS_MMU
+	gsl_mmustats_t        stats;
+#endif  // GSL_STATS_MMU
+} gsl_mmu_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  inline functions
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE int
+kgsl_mmu_isenabled(gsl_mmu_t *mmu)
+{
+    // address translation enabled
+    int enabled = ((mmu)->flags & GSL_FLAGS_STARTED) ? 1 : 0;
+
+    return (enabled);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int    kgsl_mmu_init(gsl_device_t *device);
+int    kgsl_mmu_close(gsl_device_t *device);
+int    kgsl_mmu_attachcallback(gsl_mmu_t *mmu, unsigned int pid);
+int    kgsl_mmu_detachcallback(gsl_mmu_t *mmu, unsigned int pid);
+int    kgsl_mmu_setpagetable(gsl_device_t *device, unsigned int pid);
+int    kgsl_mmu_map(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, const gsl_scatterlist_t *scatterlist, gsl_flags_t flags, unsigned int pid);
+int    kgsl_mmu_unmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, unsigned int pid);
+int    kgsl_mmu_getmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, gsl_scatterlist_t *scatterlist, unsigned int pid);
+int    kgsl_mmu_querystats(gsl_mmu_t *mmu, gsl_mmustats_t *stats);
+int    kgsl_mmu_bist(gsl_mmu_t *mmu);
+
+#endif // __GSL_MMU_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h b/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h
new file mode 100644
index 000000000000..6081c396f6e4
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h
@@ -0,0 +1,235 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_RINGBUFFER_H
+#define __GSL_RINGBUFFER_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+
+// ringbuffer sizes log2quadword
+#define     GSL_RB_SIZE_8                        0
+#define     GSL_RB_SIZE_16                       1
+#define     GSL_RB_SIZE_32                       2
+#define     GSL_RB_SIZE_64                       3
+#define     GSL_RB_SIZE_128                      4
+#define     GSL_RB_SIZE_256                      5
+#define     GSL_RB_SIZE_512                      6
+#define     GSL_RB_SIZE_1K                       7
+#define     GSL_RB_SIZE_2K                       8
+#define     GSL_RB_SIZE_4K                       9
+#define     GSL_RB_SIZE_8K                      10
+#define     GSL_RB_SIZE_16K                     11
+#define     GSL_RB_SIZE_32K                     12
+#define     GSL_RB_SIZE_64K                     13
+#define     GSL_RB_SIZE_128K                    14
+#define     GSL_RB_SIZE_256K                    15
+#define     GSL_RB_SIZE_512K                    16
+#define     GSL_RB_SIZE_1M                      17
+#define     GSL_RB_SIZE_2M                      18
+#define     GSL_RB_SIZE_4M                      19
+
+// offsets into memptrs
+#define GSL_RB_MEMPTRS_RPTR_OFFSET              0
+#define GSL_RB_MEMPTRS_WPTRPOLL_OFFSET          (GSL_RB_MEMPTRS_RPTR_OFFSET + sizeof(unsigned int))
+
+// dword base address of the GFX decode space
+#define GSL_HAL_SUBBLOCK_OFFSET(reg)            ((unsigned int)((reg) - (0x2000)))
+
+// CP timestamp register
+#define mmCP_TIMESTAMP                          mmSCRATCH_REG0
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+#ifdef _DEBUG
+// ----------------
+// ringbuffer debug
+// ----------------
+typedef struct _gsl_rb_debug_t {
+    unsigned int        pm4_ucode_rel;
+    unsigned int        pfp_ucode_rel;
+    unsigned int        cp_rb_base;
+    cp_rb_cntl_u        cp_rb_cntl;
+    unsigned int        cp_rb_rptr_addr;
+    unsigned int        cp_rb_rptr;
+    unsigned int        cp_rb_wptr;
+    unsigned int        cp_rb_wptr_base;
+    scratch_umsk_u      scratch_umsk;
+    unsigned int        scratch_addr;
+    cp_me_cntl_u        cp_me_cntl;
+    cp_me_status_u      cp_me_status;
+    cp_debug_u          cp_debug;
+    cp_stat_u           cp_stat;
+    rbbm_status_u       rbbm_status;
+    unsigned int        sop_timestamp;
+    unsigned int        eop_timestamp;
+} gsl_rb_debug_t;
+#endif // _DEBUG
+
+// -------------------
+// ringbuffer watchdog
+// -------------------
+typedef struct _gsl_rbwatchdog_t {
+    gsl_flags_t   flags;
+    unsigned int  rptr_sample;
+} gsl_rbwatchdog_t;
+
+// ------------------
+// memory ptr objects
+// ------------------
+#ifdef __GNUC__
+#pragma pack(push, 1)
+#else
+#pragma pack(push)
+#pragma pack(1)
+#endif
+typedef struct _gsl_rbmemptrs_t {
+    volatile int  rptr;
+    int           wptr_poll;
+} gsl_rbmemptrs_t;
+#pragma pack(pop)
+
+// -----
+// stats
+// -----
+typedef struct _gsl_rbstats_t {
+    __int64  wraps;
+    __int64  issues;
+    __int64  wordstotal;
+} gsl_rbstats_t;
+
+
+// -----------------
+// ringbuffer object
+// -----------------
+typedef struct _gsl_ringbuffer_t {
+
+    gsl_device_t      *device;
+    gsl_flags_t       flags;
+
+    gsl_memdesc_t     buffer_desc;              // allocated memory descriptor
+    gsl_memdesc_t     memptrs_desc;
+
+    gsl_rbmemptrs_t   *memptrs;
+
+    unsigned int      sizedwords;               // ring buffer size dwords
+    unsigned int      blksizequadwords;
+
+    unsigned int      wptr;                     // write pointer offset in dwords from baseaddr
+    unsigned int      rptr;                     // read pointer  offset in dwords from baseaddr
+    gsl_timestamp_t   timestamp;
+
+
+    gsl_rbwatchdog_t  watchdog;
+
+#ifdef GSL_STATS_RINGBUFFER
+    gsl_rbstats_t     stats;
+#endif // GSL_STATS_RINGBUFFER
+
+} gsl_ringbuffer_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+
+// ----------
+// ring write
+// ----------
+#define GSL_RB_WRITE(ring, data)        \
+      KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RINGBUF_WRT, (unsigned int)ring, data, 0, "GSL_RB_WRITE")); \
+      *(unsigned int *)(ring)++ = (unsigned int)(data);
+
+// ---------
+// timestamp
+// ---------
+#ifdef GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+#define GSL_RB_USE_MEM_TIMESTAMP
+#endif //GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+
+#ifdef  GSL_RB_USE_MEM_TIMESTAMP
+#define GSL_RB_MEMPTRS_SCRATCH_MASK         0x1     // enable timestamp (...scratch0) memory shadowing
+#define GSL_RB_INIT_TIMESTAMP(rb)
+
+#else
+#define GSL_RB_MEMPTRS_SCRATCH_MASK         0x0     // disable
+#define GSL_RB_INIT_TIMESTAMP(rb)           kgsl_device_regwrite((rb)->device->id, mmCP_TIMESTAMP, 0);
+#endif // GSL_RB_USE_MEMTIMESTAMP
+
+// --------
+// mem rptr
+// --------
+#ifdef  GSL_RB_USE_MEM_RPTR
+#define GSL_RB_CNTL_NO_UPDATE               0x0     // enable
+#define GSL_RB_GET_READPTR(rb, data)        kgsl_sharedmem_read0(&(rb)->memptrs_desc, (data), GSL_RB_MEMPTRS_RPTR_OFFSET, 4, false)
+#else
+#define GSL_RB_CNTL_NO_UPDATE               0x1     // disable
+#define GSL_RB_GET_READPTR(rb, data)        (rb)->device->fbtl.device_regread((rb)->device, mmCP_RB_RPTR,(data))
+#endif // GSL_RB_USE_MEMRPTR
+
+// ------------
+// wptr polling
+// ------------
+#ifdef  GSL_RB_USE_WPTR_POLLING
+#define GSL_RB_CNTL_POLL_EN                 0x1     // enable
+#define GSL_RB_UPDATE_WPTR_POLLING(rb)      (rb)->memptrs->wptr_poll = (rb)->wptr
+#else
+#define GSL_RB_CNTL_POLL_EN                 0x0     // disable
+#define GSL_RB_UPDATE_WPTR_POLLING(rb)
+#endif  // GSL_RB_USE_WPTR_POLLING
+
+// -----
+// stats
+// -----
+#ifdef GSL_STATS_RINGBUFFER
+#define GSL_RB_STATS(x) x
+#else
+#define GSL_RB_STATS(x)
+#endif // GSL_STATS_RINGBUFFER
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int             kgsl_ringbuffer_init(gsl_device_t *device);
+int             kgsl_ringbuffer_close(gsl_ringbuffer_t *rb);
+int             kgsl_ringbuffer_start(gsl_ringbuffer_t *rb);
+int             kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb);
+gsl_timestamp_t	kgsl_ringbuffer_issuecmds(gsl_device_t *device, int pmodeoff, unsigned int *cmdaddr, int sizedwords, unsigned int pid);
+int             kgsl_ringbuffer_issueibcmds(gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags);
+void            kgsl_ringbuffer_watchdog(void);
+
+int             kgsl_ringbuffer_querystats(gsl_ringbuffer_t *rb, gsl_rbstats_t *stats);
+int             kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb);
+
+#endif  // __GSL_RINGBUFFER_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_sharedmem.h b/drivers/mxc/amd-gpu/include/gsl_sharedmem.h
new file mode 100644
index 000000000000..bb9692cc1e44
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_sharedmem.h
@@ -0,0 +1,110 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_SHAREDMEM_H
+#define __GSL_SHAREDMEM_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+
+#define GSL_APERTURE_MASK                   0x000000FF
+#define GSL_DEVICEID_MASK                   0x0000FF00
+#define GSL_EXTALLOC_MASK                   0x000F0000
+
+#define GSL_APERTURE_SHIFT                  0
+#define GSL_DEVICEID_SHIFT                  8
+#define GSL_EXTALLOC_SHIFT                  16
+
+#define GSL_APERTURE_GETGPUADDR(shmem, aperture_index)  \
+    shmem.apertures[aperture_index].memarena->gpubaseaddr;
+
+#define GSL_APERTURE_GETHOSTADDR(shmem, aperture_index) \
+    shmem.apertures[aperture_index].memarena->hostbaseaddr;
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// ---------------------
+// memory aperture stats
+// ---------------------
+typedef struct _gsl_aperture_stats_t
+{
+    gsl_apertureid_t      id;
+    gsl_channelid_t       channel;
+    gsl_memarena_stats_t  memarena;
+} gsl_aperture_stats_t;
+
+// -------------------
+// shared memory stats
+// -------------------
+typedef struct _gsl_sharedmem_stats_t
+{
+    gsl_aperture_stats_t  apertures[GSL_SHMEM_MAX_APERTURES];
+} gsl_sharedmem_stats_t;
+
+// ---------------
+// memory aperture
+// ---------------
+typedef struct _gsl_aperture_t
+{
+    gsl_apertureid_t  id;
+    gsl_channelid_t   channel;
+    int               numbanks;
+    gsl_memarena_t    *memarena;
+} gsl_aperture_t;
+
+// --------------------
+// shared memory object
+// --------------------
+typedef struct _gsl_sharedmem_t
+{
+    gsl_flags_t     flags;
+    unsigned int    priv;
+    int             numapertures;
+    gsl_aperture_t  apertures[GSL_SHMEM_MAX_APERTURES]; 
+    int             aperturelookup[GSL_APERTURE_MAX][GSL_CHANNEL_MAX];
+} gsl_sharedmem_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int             kgsl_sharedmem_init(gsl_sharedmem_t *shmem);
+int             kgsl_sharedmem_close(gsl_sharedmem_t *shmem);
+int             kgsl_sharedmem_alloc0(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc);
+int             kgsl_sharedmem_free0(gsl_memdesc_t *memdesc, unsigned int pid);
+int             kgsl_sharedmem_read0(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace);
+int             kgsl_sharedmem_write0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace);
+int             kgsl_sharedmem_set0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes);
+int             kgsl_sharedmem_querystats(gsl_sharedmem_t *shmem, gsl_sharedmem_stats_t *stats);
+unsigned int    kgsl_sharedmem_convertaddr(unsigned int addr, int type);
+
+#endif // __GSL_SHAREDMEM_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_tbdump.h b/drivers/mxc/amd-gpu/include/gsl_tbdump.h
new file mode 100644
index 000000000000..53b30a8442e7
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_tbdump.h
@@ -0,0 +1,38 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_TBDUMP_H
+#define __GSL_TBDUMP_H
+
+void tbdump_open(char* filename);
+void tbdump_close();
+void tbdump_syncmem(unsigned int addr, unsigned int src, unsigned int sizebytes);
+void tbdump_setmem(unsigned int addr, unsigned int value, unsigned int sizebytes);
+void tbdump_slavewrite(unsigned int addr, unsigned int value);
+
+#endif // __GSL_TBDUMP_H
diff --git a/drivers/mxc/amd-gpu/include/reg/g12_reg.h b/drivers/mxc/amd-gpu/include/reg/g12_reg.h
new file mode 100644
index 000000000000..d12d419822a2
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/g12_reg.h
@@ -0,0 +1,41 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _G12_H
+#define _G12_H
+
+#ifdef _Z180
+#include "vgc/vgregs_z180.h"
+#include "vgc/vgenums_z180.h"
+#else
+#include "vgc/vgregs_z160.h"
+#include "vgc/vgenums_z160.h"
+#endif
+
+#endif // _G12_H
diff --git a/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h b/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h
new file mode 100644
index 000000000000..911c22fbbba6
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h
@@ -0,0 +1,291 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __REGS_ENUMS_H
+#define __REGS_ENUMS_H
+
+typedef enum _BB_CULL {
+    BB_CULL_NONE                     = 0,
+    BB_CULL_CW                       = 1,
+    BB_CULL_CCW                      = 2,
+} BB_CULL;
+
+typedef enum _BB_TEXTUREADDRESS {
+    BB_TADDRESS_WRAP                 = 0,
+    BB_TADDRESS_CLAMP                = 1,
+    BB_TADDRESS_BORDER               = 2,
+    BB_TADDRESS_MIRROR               = 4,
+    BB_TADDRESS_MIRRORCLAMP          = 5,   // Not supported on G3x cores
+    BB_TADDRESS_MIRRORBORDER         = 6,   // Not supported on G3x cores
+} BB_TEXTUREADDRESS;
+
+typedef enum _BB_TEXTYPE {
+    BB_TEXTYPE_4444                  = 0,
+    BB_TEXTYPE_1555                  = 1,
+    BB_TEXTYPE_5551                  = 2,
+    BB_TEXTYPE_565                   = 3,
+    BB_TEXTYPE_8888                  = 4,
+    BB_TEXTYPE_8                     = 5,
+    BB_TEXTYPE_88                    = 6,
+    BB_TEXTYPE_4                     = 7,
+    BB_TEXTYPE_44                    = 8,
+    BB_TEXTYPE_UYVY                  = 9,
+    BB_TEXTYPE_YUY2                  = 10,
+    BB_TEXTYPE_YVYU                  = 11,
+    BB_TEXTYPE_DXT1                  = 12,
+    BB_TEXTYPE_PACKMAN               = 13,
+    BB_TEXTYPE_PACKMAN_ALPHA4        = 14,
+    BB_TEXTYPE_1F16                  = 15,
+    BB_TEXTYPE_2F16                  = 16,
+    BB_TEXTYPE_4F16                  = 17,
+    BB_TEXTYPE_IPACKMAN_RGB          = 18,
+    BB_TEXTYPE_IPACKMAN_RGBA         = 19,
+} BB_TEXTYPE;
+
+typedef enum _BB_CMPFUNC {
+    BB_CMP_NEVER                     = 0,
+    BB_CMP_LESS                      = 1,
+    BB_CMP_EQUAL                     = 2,
+    BB_CMP_LESSEQUAL                 = 3,
+    BB_CMP_GREATER                   = 4,
+    BB_CMP_NOTEQUAL                  = 5,
+    BB_CMP_GREATEREQUAL              = 6,
+    BB_CMP_ALWAYS                    = 7,
+} BB_CMPFUNC;
+
+typedef enum _BB_STENCILOP {
+    BB_STENCILOP_KEEP                = 0,
+    BB_STENCILOP_ZERO                = 1,
+    BB_STENCILOP_REPLACE             = 2,
+    BB_STENCILOP_INCRSAT             = 3,
+    BB_STENCILOP_DECRSAT             = 4,
+    BB_STENCILOP_INVERT              = 5,
+    BB_STENCILOP_INCR                = 6,
+    BB_STENCILOP_DECR                = 7,
+} BB_STENCILOP;
+
+typedef enum _BB_PRIMITIVETYPE {
+    BB_PT_POINTLIST                  = 0,
+    BB_PT_LINELIST                   = 1,
+    BB_PT_LINESTRIP                  = 2,
+    BB_PT_TRIANGLELIST               = 3,
+    BB_PT_TRIANGLESTRIP              = 4,
+    BB_PT_TRIANGLEFAN                = 5,
+} BB_PRIMITIVETYPE;
+
+typedef enum _BB_TEXTUREFILTERTYPE {
+    BB_TEXF_NONE                     = 0,   // filtering disabled (valid for mip filter only)
+    BB_TEXF_POINT                    = 1,   // nearest
+    BB_TEXF_LINEAR                   = 2,   // linear interpolation
+} BB_TEXTUREFILTERTYPE;
+
+typedef enum _BB_BUFFER {
+    BB_BUFFER_PPCODE                 = 0,   // Pixel processor code
+    BB_BUFFER_UNUSED                 = 1,   // Unused
+    BB_BUFFER_CBUF                   = 2,   // Color buffer
+    BB_BUFFER_ZBUF                   = 3,   // Z buffer
+    BB_BUFFER_AUXBUF0                = 4,   // AUX0 buffer
+    BB_BUFFER_AUXBUF1                = 5,   // AUX1 buffer
+    BB_BUFFER_AUXBUF2                = 6,   // AUX2 buffer
+    BB_BUFFER_AUXBUF3                = 7,   // AUX3 buffer
+} BB_BUFFER;
+
+typedef enum _BB_COLORFORMAT {
+    BB_COLOR_ARGB4444                = 0,
+    BB_COLOR_ARGB0565                = 1,
+    BB_COLOR_ARGB1555                = 2,
+    BB_COLOR_RGBA5551                = 3,
+    BB_COLOR_ARGB8888                = 4,
+    BB_COLOR_R16                     = 5,
+    BB_COLOR_RG1616                  = 6,
+    BB_COLOR_ARGB16161616            = 7,
+    BB_COLOR_D16                     = 8,
+    BB_COLOR_S4D12                   = 9,
+    BB_COLOR_S1D15                   = 10,
+    BB_COLOR_X8D24                   = 11,
+    BB_COLOR_S8D24                   = 12,
+    BB_COLOR_X2D30                   = 13,
+} BB_COLORFORMAT;
+
+typedef enum _BB_PP_REGCONFIG {
+    BB_PP_REGCONFIG_1                = 0,
+    BB_PP_REGCONFIG_2                = 1,
+    BB_PP_REGCONFIG_3                = 8,
+    BB_PP_REGCONFIG_4                = 2,
+    BB_PP_REGCONFIG_6                = 9,
+    BB_PP_REGCONFIG_8                = 3,
+    BB_PP_REGCONFIG_12               = 10,
+    BB_PP_REGCONFIG_16               = 4,
+    BB_PP_REGCONFIG_24               = 11,
+    BB_PP_REGCONFIG_32               = 5,
+} BB_PP_REGCONFIG;
+
+typedef enum _G2D_read_t {
+    G2D_READ_DST                     = 0,
+    G2D_READ_SRC1                    = 1,
+    G2D_READ_SRC2                    = 2,
+    G2D_READ_SRC3                    = 3,
+} G2D_read_t;
+
+typedef enum _G2D_format_t {
+    G2D_1                            = 0,   // foreground & background
+    G2D_1BW                          = 1,   // black & white
+    G2D_4                            = 2,
+    G2D_8                            = 3,   // alpha
+    G2D_4444                         = 4,
+    G2D_1555                         = 5,
+    G2D_0565                         = 6,
+    G2D_8888                         = 7,
+    G2D_YUY2                         = 8,
+    G2D_UYVY                         = 9,
+    G2D_YVYU                         = 10,
+    G2D_4444_RGBA                    = 11,
+    G2D_5551_RGBA                    = 12,
+    G2D_8888_RGBA                    = 13,
+    G2D_A8                           = 14,  // for alpha texture only
+} G2D_format_t;
+
+typedef enum _G2D_wrap_t {
+    G2D_WRAP_CLAMP                   = 0,
+    G2D_WRAP_REPEAT                  = 1,
+    G2D_WRAP_MIRROR                  = 2,
+    G2D_WRAP_BORDER                  = 3,
+} G2D_wrap_t;
+
+typedef enum _G2D_BLEND_OP {
+    G2D_BLENDOP_ADD                  = 0,
+    G2D_BLENDOP_SUB                  = 1,
+    G2D_BLENDOP_MIN                  = 2,
+    G2D_BLENDOP_MAX                  = 3,
+} G2D_BLEND_OP;
+
+typedef enum _G2D_GRAD_OP {
+    G2D_GRADOP_DOT                   = 0,
+    G2D_GRADOP_RCP                   = 1,
+    G2D_GRADOP_SQRTMUL               = 2,
+    G2D_GRADOP_SQRTADD               = 3,
+} G2D_GRAD_OP;
+
+typedef enum _G2D_BLEND_SRC {
+    G2D_BLENDSRC_ZERO                = 0,   // One with invert
+    G2D_BLENDSRC_SOURCE              = 1,   // Paint with coverage alpha applied
+    G2D_BLENDSRC_DESTINATION         = 2,
+    G2D_BLENDSRC_IMAGE               = 3,   // Second texture
+    G2D_BLENDSRC_TEMP0               = 4,
+    G2D_BLENDSRC_TEMP1               = 5,
+    G2D_BLENDSRC_TEMP2               = 6,
+} G2D_BLEND_SRC;
+
+typedef enum _G2D_BLEND_DST {
+    G2D_BLENDDST_IGNORE              = 0,   // Ignore destination
+    G2D_BLENDDST_TEMP0               = 1,
+    G2D_BLENDDST_TEMP1               = 2,
+    G2D_BLENDDST_TEMP2               = 3,
+} G2D_BLEND_DST;
+
+typedef enum _G2D_BLEND_CONST {
+    G2D_BLENDSRC_CONST0              = 0,
+    G2D_BLENDSRC_CONST1              = 1,
+    G2D_BLENDSRC_CONST2              = 2,
+    G2D_BLENDSRC_CONST3              = 3,
+    G2D_BLENDSRC_CONST4              = 4,
+    G2D_BLENDSRC_CONST5              = 5,
+    G2D_BLENDSRC_CONST6              = 6,
+    G2D_BLENDSRC_CONST7              = 7,
+} G2D_BLEND_CONST;
+
+typedef enum _V3_NEXTCMD {
+    VGV3_NEXTCMD_CONTINUE            = 0,   // Continue reading at current address, COUNT gives size of next packet.
+    VGV3_NEXTCMD_JUMP                = 1,   // Jump to CALLADDR, COUNT gives size of next packet.
+    VGV3_NEXTCMD_CALL                = 2,   // First call a sub-stream at CALLADDR for CALLCOUNT dwords. Then perform a continue.
+    VGV3_NEXTCMD_CALLV2TRUE          = 3,   // Not supported.
+    VGV3_NEXTCMD_CALLV2FALSE         = 4,   // Not supported.
+    VGV3_NEXTCMD_ABORT               = 5,   // Abort reading. This ends the stream. Normally stream can just be paused (or automatically pauses at the end) which avoids any data being lost.
+} V3_NEXTCMD;
+
+typedef enum _V3_FORMAT {
+    VGV3_FORMAT_S8                   = 0,   // Signed 8 bit data (4 writes per data dword) => VGV2-float
+    VGV3_FORMAT_S16                  = 1,   // Signed 16 bit data (2 writes per data dword) => VGV2-float
+    VGV3_FORMAT_S32                  = 2,   // Signed 32 bit data => VGV2-float
+    VGV3_FORMAT_F32                  = 3,   // IEEE 32-bit floating point => VGV2-float
+    VGV3_FORMAT_RAW                  = 4,   // No conversion
+} V3_FORMAT;
+
+typedef enum _V2_ACTION {
+    VGV2_ACTION_END                  = 0,   // end previous path
+    VGV2_ACTION_MOVETOOPEN           = 1,   // end previous path, C1=C4, start new open subpath
+    VGV2_ACTION_MOVETOCLOSED         = 2,   // end previous path, C1=C4, start new closed subpath
+    VGV2_ACTION_LINETO               = 3,   // line C1,C4
+    VGV2_ACTION_CUBICTO              = 4,   // cubic C1,C2,C3,C4.
+    VGV2_ACTION_QUADTO               = 5,   // quadratic C1,C3,C4.
+    VGV2_ACTION_SCUBICTO             = 6,   // smooth cubic C1,C4.
+    VGV2_ACTION_SQUADTO              = 7,   // smooth quadratic C1,C3,C4.
+    VGV2_ACTION_VERTEXTO             = 8,   // half lineto C4=pos, C3=normal.
+    VGV2_ACTION_VERTEXTOOPEN         = 9,   // moveto open + half lineto C4=pos, C3=normal.
+    VGV2_ACTION_VERTEXTOCLOSED       = 10,  // moveto closed + half lineto C4=pos, C3=normal.
+    VGV2_ACTION_MOVETOMOVE           = 11,  // end previous path, C1=C4, move but do not start a subpath
+    VGV2_ACTION_FLUSH                = 15,  // end previous path and block following regwrites until all lines sent
+} V2_ACTION;
+
+typedef enum _V2_CAP {
+    VGV2_CAP_BUTT                    = 0,   // butt caps (straight line overlappin starting point
+    VGV2_CAP_ROUND                   = 1,   // round caps (smoothness depends on ARCSIN/ARCCOS registers)
+    VGV2_CAP_SQUARE                  = 2,   // square caps (square centered on starting point)
+} V2_CAP;
+
+typedef enum _V2_JOIN {
+    VGV2_JOIN_MITER                  = 0,   // miter joins (both sides extended towards intersection. If angle is too small (compared to STMITER register) the miter is converted into a BEVEL.
+    VGV2_JOIN_ROUND                  = 1,   // round joins (smoothness depends on ARCSIN/ARCCOS registers)
+    VGV2_JOIN_BEVEL                  = 2,   // bevel joins (ends of both sides are connected with a single line)
+} V2_JOIN;
+
+enum
+{
+    G2D_GRADREG_X        = 0,  // also usable as temp
+    G2D_GRADREG_Y        = 1,  // also usable as temp
+    G2D_GRADREG_OUTX     = 8,
+    G2D_GRADREG_OUTY     = 9,
+    G2D_GRADREG_C0       = 16,
+    G2D_GRADREG_C1       = 17,
+    G2D_GRADREG_C2       = 18,
+    G2D_GRADREG_C3       = 19,
+    G2D_GRADREG_C4       = 20,
+    G2D_GRADREG_C5       = 21,
+    G2D_GRADREG_C6       = 22,
+    G2D_GRADREG_C7       = 23,
+    G2D_GRADREG_C8       = 24,
+    G2D_GRADREG_C9       = 25,
+    G2D_GRADREG_C10      = 26,
+    G2D_GRADREG_C11      = 27,
+    G2D_GRADREG_ZERO     = 28,
+    G2D_GRADREG_ONE      = 29,
+    G2D_GRADREG_MINUSONE = 30,
+};
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h b/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h
new file mode 100644
index 000000000000..1660bc1c12a9
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h
@@ -0,0 +1,3775 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __REGS_G4X_DRIVER_H
+#define __REGS_G4X_DRIVER_H
+
+#ifndef _LINUX
+#include <assert.h>
+#else
+#ifndef assert
+#define assert(expr)
+#endif
+#endif
+
+//-----------------------------------------------------
+// REGISTER ADDRESSES
+//-----------------------------------------------------
+
+#define ADDR_FBC_BASE                    0x84
+#define ADDR_FBC_DATA                    0x86
+#define ADDR_FBC_HEIGHT                  0x8a
+#define ADDR_FBC_START                   0x8e
+#define ADDR_FBC_STRIDE                  0x8c
+#define ADDR_FBC_WIDTH                   0x88
+#define ADDR_VGC_CLOCKEN                 0x508
+#define ADDR_VGC_COMMANDSTREAM           0x0
+#define ADDR_VGC_FIFOFREE                0x7c0
+#define ADDR_VGC_IRQENABLE               0x438
+#define ADDR_VGC_IRQSTATUS               0x418
+#define ADDR_VGC_IRQ_ACTIVE_CNT          0x4e0
+#define ADDR_VGC_MMUCOMMANDSTREAM        0x3fc
+#define ADDR_VGC_REVISION                0x400
+#define ADDR_VGC_SYSSTATUS               0x410
+#define ADDR_G2D_ALPHABLEND              0xc
+#define ADDR_G2D_BACKGROUND              0xb
+#define ADDR_G2D_BASE0                   0x0
+#define ADDR_G2D_BASE1                   0x2
+#define ADDR_G2D_BASE2                   0x4
+#define ADDR_G2D_BASE3                   0x6
+#define ADDR_G2D_BLENDERCFG              0x11
+#define ADDR_G2D_BLEND_A0                0x14
+#define ADDR_G2D_BLEND_A1                0x15
+#define ADDR_G2D_BLEND_A2                0x16
+#define ADDR_G2D_BLEND_A3                0x17
+#define ADDR_G2D_BLEND_C0                0x18
+#define ADDR_G2D_BLEND_C1                0x19
+#define ADDR_G2D_BLEND_C2                0x1a
+#define ADDR_G2D_BLEND_C3                0x1b
+#define ADDR_G2D_BLEND_C4                0x1c
+#define ADDR_G2D_BLEND_C5                0x1d
+#define ADDR_G2D_BLEND_C6                0x1e
+#define ADDR_G2D_BLEND_C7                0x1f
+#define ADDR_G2D_CFG0                    0x1
+#define ADDR_G2D_CFG1                    0x3
+#define ADDR_G2D_CFG2                    0x5
+#define ADDR_G2D_CFG3                    0x7
+#define ADDR_G2D_COLOR                   0xff
+#define ADDR_G2D_CONFIG                  0xe
+#define ADDR_G2D_CONST0                  0xb0
+#define ADDR_G2D_CONST1                  0xb1
+#define ADDR_G2D_CONST2                  0xb2
+#define ADDR_G2D_CONST3                  0xb3
+#define ADDR_G2D_CONST4                  0xb4
+#define ADDR_G2D_CONST5                  0xb5
+#define ADDR_G2D_CONST6                  0xb6
+#define ADDR_G2D_CONST7                  0xb7
+#define ADDR_G2D_FOREGROUND              0xa
+#define ADDR_G2D_GRADIENT                0xd0
+#define ADDR_G2D_IDLE                    0xfe
+#define ADDR_G2D_INPUT                   0xf
+#define ADDR_G2D_MASK                    0x10
+#define ADDR_G2D_ROP                     0xd
+#define ADDR_G2D_SCISSORX                0x8
+#define ADDR_G2D_SCISSORY                0x9
+#define ADDR_G2D_SXY                     0xf2
+#define ADDR_G2D_SXY2                    0xf3
+#define ADDR_G2D_VGSPAN                  0xf4
+#define ADDR_G2D_WIDTHHEIGHT             0xf1
+#define ADDR_G2D_XY                      0xf0
+#define ADDR_GRADW_BORDERCOLOR           0xd4
+#define ADDR_GRADW_CONST0                0xc0
+#define ADDR_GRADW_CONST1                0xc1
+#define ADDR_GRADW_CONST2                0xc2
+#define ADDR_GRADW_CONST3                0xc3
+#define ADDR_GRADW_CONST4                0xc4
+#define ADDR_GRADW_CONST5                0xc5
+#define ADDR_GRADW_CONST6                0xc6
+#define ADDR_GRADW_CONST7                0xc7
+#define ADDR_GRADW_CONST8                0xc8
+#define ADDR_GRADW_CONST9                0xc9
+#define ADDR_GRADW_CONSTA                0xca
+#define ADDR_GRADW_CONSTB                0xcb
+#define ADDR_GRADW_INST0                 0xe0
+#define ADDR_GRADW_INST1                 0xe1
+#define ADDR_GRADW_INST2                 0xe2
+#define ADDR_GRADW_INST3                 0xe3
+#define ADDR_GRADW_INST4                 0xe4
+#define ADDR_GRADW_INST5                 0xe5
+#define ADDR_GRADW_INST6                 0xe6
+#define ADDR_GRADW_INST7                 0xe7
+#define ADDR_GRADW_TEXBASE               0xd3
+#define ADDR_GRADW_TEXCFG                0xd1
+#define ADDR_GRADW_TEXSIZE               0xd2
+#define ADDR_MH_ARBITER_CONFIG           0xa40
+#define ADDR_MH_AXI_ERROR                0xa45
+#define ADDR_MH_AXI_HALT_CONTROL         0xa50
+#define ADDR_MH_CLNT_AXI_ID_REUSE        0xa41
+#define ADDR_MH_DEBUG_CTRL               0xa4e
+#define ADDR_MH_DEBUG_DATA               0xa4f
+#define ADDR_MH_INTERRUPT_CLEAR          0xa44
+#define ADDR_MH_INTERRUPT_MASK           0xa42
+#define ADDR_MH_INTERRUPT_STATUS         0xa43
+#define ADDR_MH_MMU_CONFIG               0x40
+#define ADDR_MH_MMU_INVALIDATE           0x45
+#define ADDR_MH_MMU_MPU_BASE             0x46
+#define ADDR_MH_MMU_MPU_END              0x47
+#define ADDR_MH_MMU_PAGE_FAULT           0x43
+#define ADDR_MH_MMU_PT_BASE              0x42
+#define ADDR_MH_MMU_TRAN_ERROR           0x44
+#define ADDR_MH_MMU_VA_RANGE             0x41
+#define ADDR_MH_PERFCOUNTER0_CONFIG      0xa47
+#define ADDR_MH_PERFCOUNTER0_HI          0xa49
+#define ADDR_MH_PERFCOUNTER0_LOW         0xa48
+#define ADDR_MH_PERFCOUNTER0_SELECT      0xa46
+#define ADDR_MH_PERFCOUNTER1_CONFIG      0xa4b
+#define ADDR_MH_PERFCOUNTER1_HI          0xa4d
+#define ADDR_MH_PERFCOUNTER1_LOW         0xa4c
+#define ADDR_MH_PERFCOUNTER1_SELECT      0xa4a
+#define ADDR_MMU_READ_ADDR               0x510
+#define ADDR_MMU_READ_DATA               0x518
+#define ADDR_VGV1_CBASE1                 0x2a
+#define ADDR_VGV1_CFG1                   0x27
+#define ADDR_VGV1_CFG2                   0x28
+#define ADDR_VGV1_DIRTYBASE              0x29
+#define ADDR_VGV1_FILL                   0x23
+#define ADDR_VGV1_SCISSORX               0x24
+#define ADDR_VGV1_SCISSORY               0x25
+#define ADDR_VGV1_TILEOFS                0x22
+#define ADDR_VGV1_UBASE2                 0x2b
+#define ADDR_VGV1_VTX0                   0x20
+#define ADDR_VGV1_VTX1                   0x21
+#define ADDR_VGV2_ACCURACY               0x60
+#define ADDR_VGV2_ACTION                 0x6f
+#define ADDR_VGV2_ARCCOS                 0x62
+#define ADDR_VGV2_ARCSIN                 0x63
+#define ADDR_VGV2_ARCTAN                 0x64
+#define ADDR_VGV2_BBOXMAXX               0x5c
+#define ADDR_VGV2_BBOXMAXY               0x5d
+#define ADDR_VGV2_BBOXMINX               0x5a
+#define ADDR_VGV2_BBOXMINY               0x5b
+#define ADDR_VGV2_BIAS                   0x5f
+#define ADDR_VGV2_C1X                    0x40
+#define ADDR_VGV2_C1XREL                 0x48
+#define ADDR_VGV2_C1Y                    0x41
+#define ADDR_VGV2_C1YREL                 0x49
+#define ADDR_VGV2_C2X                    0x42
+#define ADDR_VGV2_C2XREL                 0x4a
+#define ADDR_VGV2_C2Y                    0x43
+#define ADDR_VGV2_C2YREL                 0x4b
+#define ADDR_VGV2_C3X                    0x44
+#define ADDR_VGV2_C3XREL                 0x4c
+#define ADDR_VGV2_C3Y                    0x45
+#define ADDR_VGV2_C3YREL                 0x4d
+#define ADDR_VGV2_C4X                    0x46
+#define ADDR_VGV2_C4XREL                 0x4e
+#define ADDR_VGV2_C4Y                    0x47
+#define ADDR_VGV2_C4YREL                 0x4f
+#define ADDR_VGV2_CLIP                   0x68
+#define ADDR_VGV2_FIRST                  0x40
+#define ADDR_VGV2_LAST                   0x6f
+#define ADDR_VGV2_MITER                  0x66
+#define ADDR_VGV2_MODE                   0x6e
+#define ADDR_VGV2_RADIUS                 0x65
+#define ADDR_VGV2_SCALE                  0x5e
+#define ADDR_VGV2_THINRADIUS             0x61
+#define ADDR_VGV2_XFSTXX                 0x56
+#define ADDR_VGV2_XFSTXY                 0x58
+#define ADDR_VGV2_XFSTYX                 0x57
+#define ADDR_VGV2_XFSTYY                 0x59
+#define ADDR_VGV2_XFXA                   0x54
+#define ADDR_VGV2_XFXX                   0x50
+#define ADDR_VGV2_XFXY                   0x52
+#define ADDR_VGV2_XFYA                   0x55
+#define ADDR_VGV2_XFYX                   0x51
+#define ADDR_VGV2_XFYY                   0x53
+#define ADDR_VGV3_CONTROL                0x70
+#define ADDR_VGV3_FIRST                  0x70
+#define ADDR_VGV3_LAST                   0x7f
+#define ADDR_VGV3_MODE                   0x71
+#define ADDR_VGV3_NEXTADDR               0x75
+#define ADDR_VGV3_NEXTCMD                0x76
+#define ADDR_VGV3_VGBYPASS               0x77
+#define ADDR_VGV3_WRITE                  0x73
+#define ADDR_VGV3_WRITEADDR              0x72
+#define ADDR_VGV3_WRITEDMI               0x7d
+#define ADDR_VGV3_WRITEF32               0x7b
+#define ADDR_VGV3_WRITEIFPAUSED          0x74
+#define ADDR_VGV3_WRITERAW               0x7c
+#define ADDR_VGV3_WRITES16               0x79
+#define ADDR_VGV3_WRITES32               0x7a
+#define ADDR_VGV3_WRITES8                0x78
+
+// FBC_BASE
+typedef struct _REG_FBC_BASE {
+    unsigned BASE                : 32;
+} REG_FBC_BASE;
+
+// FBC_DATA
+typedef struct _REG_FBC_DATA {
+    unsigned DATA                : 32;
+} REG_FBC_DATA;
+
+// FBC_HEIGHT
+typedef struct _REG_FBC_HEIGHT {
+    unsigned HEIGHT              : 11;
+} REG_FBC_HEIGHT;
+
+// FBC_START
+typedef struct _REG_FBC_START {
+    unsigned DUMMY               : 1;
+} REG_FBC_START;
+
+// FBC_STRIDE
+typedef struct _REG_FBC_STRIDE {
+    unsigned STRIDE              : 11;
+} REG_FBC_STRIDE;
+
+// FBC_WIDTH
+typedef struct _REG_FBC_WIDTH {
+    unsigned WIDTH               : 11;
+} REG_FBC_WIDTH;
+
+// VGC_CLOCKEN
+typedef struct _REG_VGC_CLOCKEN {
+    unsigned BCACHE              : 1;
+    unsigned G2D_VGL3            : 1;
+    unsigned VG_L1L2             : 1;
+    unsigned RESERVED            : 3;
+} REG_VGC_CLOCKEN;
+
+// VGC_COMMANDSTREAM
+typedef struct _REG_VGC_COMMANDSTREAM {
+    unsigned DATA                : 32;
+} REG_VGC_COMMANDSTREAM;
+
+// VGC_FIFOFREE
+typedef struct _REG_VGC_FIFOFREE {
+    unsigned FREE                : 1;
+} REG_VGC_FIFOFREE;
+
+// VGC_IRQENABLE
+typedef struct _REG_VGC_IRQENABLE {
+    unsigned MH                  : 1;
+    unsigned G2D                 : 1;
+    unsigned FIFO                : 1;
+    unsigned FBC                 : 1;
+} REG_VGC_IRQENABLE;
+
+// VGC_IRQSTATUS
+typedef struct _REG_VGC_IRQSTATUS {
+    unsigned MH                  : 1;
+    unsigned G2D                 : 1;
+    unsigned FIFO                : 1;
+    unsigned FBC                 : 1;
+} REG_VGC_IRQSTATUS;
+
+// VGC_IRQ_ACTIVE_CNT
+typedef struct _REG_VGC_IRQ_ACTIVE_CNT {
+    unsigned MH                  : 8;
+    unsigned G2D                 : 8;
+    unsigned ERRORS              : 8;
+    unsigned FBC                 : 8;
+} REG_VGC_IRQ_ACTIVE_CNT;
+
+// VGC_MMUCOMMANDSTREAM
+typedef struct _REG_VGC_MMUCOMMANDSTREAM {
+    unsigned DATA                : 32;
+} REG_VGC_MMUCOMMANDSTREAM;
+
+// VGC_REVISION
+typedef struct _REG_VGC_REVISION {
+    unsigned MINOR_REVISION      : 4;
+    unsigned MAJOR_REVISION      : 4;
+} REG_VGC_REVISION;
+
+// VGC_SYSSTATUS
+typedef struct _REG_VGC_SYSSTATUS {
+    unsigned RESET               : 1;
+} REG_VGC_SYSSTATUS;
+
+// G2D_ALPHABLEND
+typedef struct _REG_G2D_ALPHABLEND {
+    unsigned ALPHA               : 8;
+    unsigned OBS_ENABLE          : 1;
+    unsigned CONSTANT            : 1;
+    unsigned INVERT              : 1;
+    unsigned OPTIMIZE            : 1;
+    unsigned MODULATE            : 1;
+    unsigned INVERTMASK          : 1;
+    unsigned PREMULTIPLYDST      : 1;
+    unsigned MASKTOALPHA         : 1;
+} REG_G2D_ALPHABLEND;
+
+// G2D_BACKGROUND
+typedef struct _REG_G2D_BACKGROUND {
+    unsigned COLOR               : 32;
+} REG_G2D_BACKGROUND;
+
+// G2D_BASE0
+typedef struct _REG_G2D_BASE0 {
+    unsigned ADDR                : 32;
+} REG_G2D_BASE0;
+
+// G2D_BASE1
+typedef struct _REG_G2D_BASE1 {
+    unsigned ADDR                : 32;
+} REG_G2D_BASE1;
+
+// G2D_BASE2
+typedef struct _REG_G2D_BASE2 {
+    unsigned ADDR                : 32;
+} REG_G2D_BASE2;
+
+// G2D_BASE3
+typedef struct _REG_G2D_BASE3 {
+    unsigned ADDR                : 32;
+} REG_G2D_BASE3;
+
+// G2D_BLENDERCFG
+typedef struct _REG_G2D_BLENDERCFG {
+    unsigned PASSES              : 3;
+    unsigned ALPHAPASSES         : 2;
+    unsigned ENABLE              : 1;
+    unsigned OOALPHA             : 1;
+    unsigned OBS_DIVALPHA        : 1;
+    unsigned NOMASK              : 1;
+} REG_G2D_BLENDERCFG;
+
+// G2D_BLEND_A0
+typedef struct _REG_G2D_BLEND_A0 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_A0;
+
+// G2D_BLEND_A1
+typedef struct _REG_G2D_BLEND_A1 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_A1;
+
+// G2D_BLEND_A2
+typedef struct _REG_G2D_BLEND_A2 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_A2;
+
+// G2D_BLEND_A3
+typedef struct _REG_G2D_BLEND_A3 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_A3;
+
+// G2D_BLEND_C0
+typedef struct _REG_G2D_BLEND_C0 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C0;
+
+// G2D_BLEND_C1
+typedef struct _REG_G2D_BLEND_C1 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C1;
+
+// G2D_BLEND_C2
+typedef struct _REG_G2D_BLEND_C2 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C2;
+
+// G2D_BLEND_C3
+typedef struct _REG_G2D_BLEND_C3 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C3;
+
+// G2D_BLEND_C4
+typedef struct _REG_G2D_BLEND_C4 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C4;
+
+// G2D_BLEND_C5
+typedef struct _REG_G2D_BLEND_C5 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C5;
+
+// G2D_BLEND_C6
+typedef struct _REG_G2D_BLEND_C6 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C6;
+
+// G2D_BLEND_C7
+typedef struct _REG_G2D_BLEND_C7 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C7;
+
+// G2D_CFG0
+typedef struct _REG_G2D_CFG0 {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned SRGB                : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned SWAPBITS            : 1;
+    unsigned STRIDESIGN          : 1;
+} REG_G2D_CFG0;
+
+// G2D_CFG1
+typedef struct _REG_G2D_CFG1 {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned SRGB                : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned SWAPBITS            : 1;
+    unsigned STRIDESIGN          : 1;
+} REG_G2D_CFG1;
+
+// G2D_CFG2
+typedef struct _REG_G2D_CFG2 {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned SRGB                : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned SWAPBITS            : 1;
+    unsigned STRIDESIGN          : 1;
+} REG_G2D_CFG2;
+
+// G2D_CFG3
+typedef struct _REG_G2D_CFG3 {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned SRGB                : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned SWAPBITS            : 1;
+    unsigned STRIDESIGN          : 1;
+} REG_G2D_CFG3;
+
+// G2D_COLOR
+typedef struct _REG_G2D_COLOR {
+    unsigned ARGB                : 32;
+} REG_G2D_COLOR;
+
+// G2D_CONFIG
+typedef struct _REG_G2D_CONFIG {
+    unsigned DST                 : 1;
+    unsigned SRC1                : 1;
+    unsigned SRC2                : 1;
+    unsigned SRC3                : 1;
+    unsigned SRCCK               : 1;
+    unsigned DSTCK               : 1;
+    unsigned ROTATE              : 2;
+    unsigned OBS_GAMMA           : 1;
+    unsigned IGNORECKALPHA       : 1;
+    unsigned DITHER              : 1;
+    unsigned WRITESRGB           : 1;
+    unsigned ARGBMASK            : 4;
+    unsigned ALPHATEX            : 1;
+    unsigned PALMLINES           : 1;
+    unsigned NOLASTPIXEL         : 1;
+    unsigned NOPROTECT           : 1;
+} REG_G2D_CONFIG;
+
+// G2D_CONST0
+typedef struct _REG_G2D_CONST0 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST0;
+
+// G2D_CONST1
+typedef struct _REG_G2D_CONST1 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST1;
+
+// G2D_CONST2
+typedef struct _REG_G2D_CONST2 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST2;
+
+// G2D_CONST3
+typedef struct _REG_G2D_CONST3 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST3;
+
+// G2D_CONST4
+typedef struct _REG_G2D_CONST4 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST4;
+
+// G2D_CONST5
+typedef struct _REG_G2D_CONST5 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST5;
+
+// G2D_CONST6
+typedef struct _REG_G2D_CONST6 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST6;
+
+// G2D_CONST7
+typedef struct _REG_G2D_CONST7 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST7;
+
+// G2D_FOREGROUND
+typedef struct _REG_G2D_FOREGROUND {
+    unsigned COLOR               : 32;
+} REG_G2D_FOREGROUND;
+
+// G2D_GRADIENT
+typedef struct _REG_G2D_GRADIENT {
+    unsigned INSTRUCTIONS        : 3;
+    unsigned INSTRUCTIONS2       : 3;
+    unsigned ENABLE              : 1;
+    unsigned ENABLE2             : 1;
+    unsigned SEL                 : 1;
+} REG_G2D_GRADIENT;
+
+// G2D_IDLE
+typedef struct _REG_G2D_IDLE {
+    unsigned IRQ                 : 1;
+    unsigned BCFLUSH             : 1;
+    unsigned V3                  : 1;
+} REG_G2D_IDLE;
+
+// G2D_INPUT
+typedef struct _REG_G2D_INPUT {
+    unsigned COLOR               : 1;
+    unsigned SCOORD1             : 1;
+    unsigned SCOORD2             : 1;
+    unsigned COPYCOORD           : 1;
+    unsigned VGMODE              : 1;
+    unsigned LINEMODE            : 1;
+} REG_G2D_INPUT;
+
+// G2D_MASK
+typedef struct _REG_G2D_MASK {
+    unsigned YMASK               : 12;
+    unsigned XMASK               : 12;
+} REG_G2D_MASK;
+
+// G2D_ROP
+typedef struct _REG_G2D_ROP {
+    unsigned ROP                 : 16;
+} REG_G2D_ROP;
+
+// G2D_SCISSORX
+typedef struct _REG_G2D_SCISSORX {
+    unsigned LEFT                : 11;
+    unsigned RIGHT               : 11;
+} REG_G2D_SCISSORX;
+
+// G2D_SCISSORY
+typedef struct _REG_G2D_SCISSORY {
+    unsigned TOP                 : 11;
+    unsigned BOTTOM              : 11;
+} REG_G2D_SCISSORY;
+
+// G2D_SXY
+typedef struct _REG_G2D_SXY {
+    unsigned Y                   : 11;
+    unsigned PAD                 : 5;
+    unsigned X                   : 11;
+} REG_G2D_SXY;
+
+// G2D_SXY2
+typedef struct _REG_G2D_SXY2 {
+    unsigned Y                   : 11;
+    unsigned PAD                 : 5;
+    unsigned X                   : 11;
+} REG_G2D_SXY2;
+
+// G2D_VGSPAN
+typedef struct _REG_G2D_VGSPAN {
+    int WIDTH               : 12;
+    unsigned PAD                 : 4;
+    unsigned COVERAGE            : 4;
+} REG_G2D_VGSPAN;
+
+// G2D_WIDTHHEIGHT
+typedef struct _REG_G2D_WIDTHHEIGHT {
+    int HEIGHT              : 12;
+    unsigned PAD                 : 4;
+    int WIDTH               : 12;
+} REG_G2D_WIDTHHEIGHT;
+
+// G2D_XY
+typedef struct _REG_G2D_XY {
+    int Y                   : 12;
+    unsigned PAD                 : 4;
+    int X                   : 12;
+} REG_G2D_XY;
+
+// GRADW_BORDERCOLOR
+typedef struct _REG_GRADW_BORDERCOLOR {
+    unsigned COLOR               : 32;
+} REG_GRADW_BORDERCOLOR;
+
+// GRADW_CONST0
+typedef struct _REG_GRADW_CONST0 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST0;
+
+// GRADW_CONST1
+typedef struct _REG_GRADW_CONST1 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST1;
+
+// GRADW_CONST2
+typedef struct _REG_GRADW_CONST2 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST2;
+
+// GRADW_CONST3
+typedef struct _REG_GRADW_CONST3 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST3;
+
+// GRADW_CONST4
+typedef struct _REG_GRADW_CONST4 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST4;
+
+// GRADW_CONST5
+typedef struct _REG_GRADW_CONST5 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST5;
+
+// GRADW_CONST6
+typedef struct _REG_GRADW_CONST6 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST6;
+
+// GRADW_CONST7
+typedef struct _REG_GRADW_CONST7 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST7;
+
+// GRADW_CONST8
+typedef struct _REG_GRADW_CONST8 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST8;
+
+// GRADW_CONST9
+typedef struct _REG_GRADW_CONST9 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST9;
+
+// GRADW_CONSTA
+typedef struct _REG_GRADW_CONSTA {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONSTA;
+
+// GRADW_CONSTB
+typedef struct _REG_GRADW_CONSTB {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONSTB;
+
+// GRADW_INST0
+typedef struct _REG_GRADW_INST0 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST0;
+
+// GRADW_INST1
+typedef struct _REG_GRADW_INST1 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST1;
+
+// GRADW_INST2
+typedef struct _REG_GRADW_INST2 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST2;
+
+// GRADW_INST3
+typedef struct _REG_GRADW_INST3 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST3;
+
+// GRADW_INST4
+typedef struct _REG_GRADW_INST4 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST4;
+
+// GRADW_INST5
+typedef struct _REG_GRADW_INST5 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST5;
+
+// GRADW_INST6
+typedef struct _REG_GRADW_INST6 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST6;
+
+// GRADW_INST7
+typedef struct _REG_GRADW_INST7 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST7;
+
+// GRADW_TEXBASE
+typedef struct _REG_GRADW_TEXBASE {
+    unsigned ADDR                : 32;
+} REG_GRADW_TEXBASE;
+
+// GRADW_TEXCFG
+typedef struct _REG_GRADW_TEXCFG {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned WRAPU               : 2;
+    unsigned WRAPV               : 2;
+    unsigned BILIN               : 1;
+    unsigned SRGB                : 1;
+    unsigned PREMULTIPLY         : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned TEX2D               : 1;
+    unsigned SWAPBITS            : 1;
+} REG_GRADW_TEXCFG;
+
+// GRADW_TEXSIZE
+typedef struct _REG_GRADW_TEXSIZE {
+    unsigned WIDTH               : 11;
+    unsigned HEIGHT              : 11;
+} REG_GRADW_TEXSIZE;
+
+// MH_ARBITER_CONFIG
+typedef struct _REG_MH_ARBITER_CONFIG {
+    unsigned SAME_PAGE_LIMIT     : 6;
+    unsigned SAME_PAGE_GRANULARITY : 1;
+    unsigned L1_ARB_ENABLE       : 1;
+    unsigned L1_ARB_HOLD_ENABLE  : 1;
+    unsigned L2_ARB_CONTROL      : 1;
+    unsigned PAGE_SIZE           : 3;
+    unsigned TC_REORDER_ENABLE   : 1;
+    unsigned TC_ARB_HOLD_ENABLE  : 1;
+    unsigned IN_FLIGHT_LIMIT_ENABLE : 1;
+    unsigned IN_FLIGHT_LIMIT     : 6;
+    unsigned CP_CLNT_ENABLE      : 1;
+    unsigned VGT_CLNT_ENABLE     : 1;
+    unsigned TC_CLNT_ENABLE      : 1;
+    unsigned RB_CLNT_ENABLE      : 1;
+    unsigned PA_CLNT_ENABLE      : 1;
+} REG_MH_ARBITER_CONFIG;
+
+// MH_AXI_ERROR
+typedef struct _REG_MH_AXI_ERROR {
+    unsigned AXI_READ_ID         : 3;
+    unsigned AXI_READ_ERROR      : 1;
+    unsigned AXI_WRITE_ID        : 3;
+    unsigned AXI_WRITE_ERROR     : 1;
+} REG_MH_AXI_ERROR;
+
+// MH_AXI_HALT_CONTROL
+typedef struct _REG_MH_AXI_HALT_CONTROL {
+    unsigned AXI_HALT            : 1;
+} REG_MH_AXI_HALT_CONTROL;
+
+// MH_CLNT_AXI_ID_REUSE
+typedef struct _REG_MH_CLNT_AXI_ID_REUSE {
+    unsigned CPW_ID              : 3;
+    unsigned PAD                 : 1;
+    unsigned RBW_ID              : 3;
+    unsigned PAD2                : 1;
+    unsigned MMUR_ID             : 3;
+    unsigned PAD3                : 1;
+    unsigned PAW_ID              : 3;
+} REG_MH_CLNT_AXI_ID_REUSE;
+
+// MH_DEBUG_CTRL
+typedef struct _REG_MH_DEBUG_CTRL {
+    unsigned INDEX               : 6;
+} REG_MH_DEBUG_CTRL;
+
+// MH_DEBUG_DATA
+typedef struct _REG_MH_DEBUG_DATA {
+    unsigned DATA                : 32;
+} REG_MH_DEBUG_DATA;
+
+// MH_INTERRUPT_CLEAR
+typedef struct _REG_MH_INTERRUPT_CLEAR {
+    unsigned AXI_READ_ERROR      : 1;
+    unsigned AXI_WRITE_ERROR     : 1;
+    unsigned MMU_PAGE_FAULT      : 1;
+} REG_MH_INTERRUPT_CLEAR;
+
+// MH_INTERRUPT_MASK
+typedef struct _REG_MH_INTERRUPT_MASK {
+    unsigned AXI_READ_ERROR      : 1;
+    unsigned AXI_WRITE_ERROR     : 1;
+    unsigned MMU_PAGE_FAULT      : 1;
+} REG_MH_INTERRUPT_MASK;
+
+// MH_INTERRUPT_STATUS
+typedef struct _REG_MH_INTERRUPT_STATUS {
+    unsigned AXI_READ_ERROR      : 1;
+    unsigned AXI_WRITE_ERROR     : 1;
+    unsigned MMU_PAGE_FAULT      : 1;
+} REG_MH_INTERRUPT_STATUS;
+
+// MH_MMU_CONFIG
+typedef struct _REG_MH_MMU_CONFIG {
+    unsigned MMU_ENABLE          : 1;
+    unsigned SPLIT_MODE_ENABLE   : 1;
+    unsigned PAD                 : 2;
+    unsigned RB_W_CLNT_BEHAVIOR  : 2;
+    unsigned CP_W_CLNT_BEHAVIOR  : 2;
+    unsigned CP_R0_CLNT_BEHAVIOR : 2;
+    unsigned CP_R1_CLNT_BEHAVIOR : 2;
+    unsigned CP_R2_CLNT_BEHAVIOR : 2;
+    unsigned CP_R3_CLNT_BEHAVIOR : 2;
+    unsigned CP_R4_CLNT_BEHAVIOR : 2;
+    unsigned VGT_R0_CLNT_BEHAVIOR : 2;
+    unsigned VGT_R1_CLNT_BEHAVIOR : 2;
+    unsigned TC_R_CLNT_BEHAVIOR  : 2;
+    unsigned PA_W_CLNT_BEHAVIOR  : 2;
+} REG_MH_MMU_CONFIG;
+
+// MH_MMU_INVALIDATE
+typedef struct _REG_MH_MMU_INVALIDATE {
+    unsigned INVALIDATE_ALL      : 1;
+    unsigned INVALIDATE_TC       : 1;
+} REG_MH_MMU_INVALIDATE;
+
+// MH_MMU_MPU_BASE
+typedef struct _REG_MH_MMU_MPU_BASE {
+    unsigned ZERO                : 12;
+    unsigned MPU_BASE            : 20;
+} REG_MH_MMU_MPU_BASE;
+
+// MH_MMU_MPU_END
+typedef struct _REG_MH_MMU_MPU_END {
+    unsigned ZERO                : 12;
+    unsigned MPU_END             : 20;
+} REG_MH_MMU_MPU_END;
+
+// MH_MMU_PAGE_FAULT
+typedef struct _REG_MH_MMU_PAGE_FAULT {
+    unsigned PAGE_FAULT          : 1;
+    unsigned OP_TYPE             : 1;
+    unsigned CLNT_BEHAVIOR       : 2;
+    unsigned AXI_ID              : 3;
+    unsigned PAD                 : 1;
+    unsigned MPU_ADDRESS_OUT_OF_RANGE : 1;
+    unsigned ADDRESS_OUT_OF_RANGE : 1;
+    unsigned READ_PROTECTION_ERROR : 1;
+    unsigned WRITE_PROTECTION_ERROR : 1;
+    unsigned REQ_VA              : 20;
+} REG_MH_MMU_PAGE_FAULT;
+
+// MH_MMU_PT_BASE
+typedef struct _REG_MH_MMU_PT_BASE {
+    unsigned ZERO                : 12;
+    unsigned PT_BASE             : 20;
+} REG_MH_MMU_PT_BASE;
+
+// MH_MMU_TRAN_ERROR
+typedef struct _REG_MH_MMU_TRAN_ERROR {
+    unsigned ZERO                : 5;
+    unsigned TRAN_ERROR          : 27;
+} REG_MH_MMU_TRAN_ERROR;
+
+// MH_MMU_VA_RANGE
+typedef struct _REG_MH_MMU_VA_RANGE {
+    unsigned NUM_64KB_REGIONS    : 12;
+    unsigned VA_BASE             : 20;
+} REG_MH_MMU_VA_RANGE;
+
+// MH_PERFCOUNTER0_CONFIG
+typedef struct _REG_MH_PERFCOUNTER0_CONFIG {
+    unsigned N_VALUE             : 8;
+} REG_MH_PERFCOUNTER0_CONFIG;
+
+// MH_PERFCOUNTER0_HI
+typedef struct _REG_MH_PERFCOUNTER0_HI {
+    unsigned PERF_COUNTER_HI     : 16;
+} REG_MH_PERFCOUNTER0_HI;
+
+// MH_PERFCOUNTER0_LOW
+typedef struct _REG_MH_PERFCOUNTER0_LOW {
+    unsigned PERF_COUNTER_LOW    : 32;
+} REG_MH_PERFCOUNTER0_LOW;
+
+// MH_PERFCOUNTER0_SELECT
+typedef struct _REG_MH_PERFCOUNTER0_SELECT {
+    unsigned PERF_SEL            : 8;
+} REG_MH_PERFCOUNTER0_SELECT;
+
+// MH_PERFCOUNTER1_CONFIG
+typedef struct _REG_MH_PERFCOUNTER1_CONFIG {
+    unsigned N_VALUE             : 8;
+} REG_MH_PERFCOUNTER1_CONFIG;
+
+// MH_PERFCOUNTER1_HI
+typedef struct _REG_MH_PERFCOUNTER1_HI {
+    unsigned PERF_COUNTER_HI     : 16;
+} REG_MH_PERFCOUNTER1_HI;
+
+// MH_PERFCOUNTER1_LOW
+typedef struct _REG_MH_PERFCOUNTER1_LOW {
+    unsigned PERF_COUNTER_LOW    : 32;
+} REG_MH_PERFCOUNTER1_LOW;
+
+// MH_PERFCOUNTER1_SELECT
+typedef struct _REG_MH_PERFCOUNTER1_SELECT {
+    unsigned PERF_SEL            : 8;
+} REG_MH_PERFCOUNTER1_SELECT;
+
+// MMU_READ_ADDR
+typedef struct _REG_MMU_READ_ADDR {
+    unsigned ADDR                : 15;
+} REG_MMU_READ_ADDR;
+
+// MMU_READ_DATA
+typedef struct _REG_MMU_READ_DATA {
+    unsigned DATA                : 32;
+} REG_MMU_READ_DATA;
+
+// VGV1_CBASE1
+typedef struct _REG_VGV1_CBASE1 {
+    unsigned ADDR                : 32;
+} REG_VGV1_CBASE1;
+
+// VGV1_CFG1
+typedef struct _REG_VGV1_CFG1 {
+    unsigned WINDRULE            : 1;
+} REG_VGV1_CFG1;
+
+// VGV1_CFG2
+typedef struct _REG_VGV1_CFG2 {
+    unsigned AAMODE              : 2;
+} REG_VGV1_CFG2;
+
+// VGV1_DIRTYBASE
+typedef struct _REG_VGV1_DIRTYBASE {
+    unsigned ADDR                : 32;
+} REG_VGV1_DIRTYBASE;
+
+// VGV1_FILL
+typedef struct _REG_VGV1_FILL {
+    unsigned INHERIT             : 1;
+} REG_VGV1_FILL;
+
+// VGV1_SCISSORX
+typedef struct _REG_VGV1_SCISSORX {
+    unsigned LEFT                : 11;
+    unsigned PAD                 : 5;
+    unsigned RIGHT               : 11;
+} REG_VGV1_SCISSORX;
+
+// VGV1_SCISSORY
+typedef struct _REG_VGV1_SCISSORY {
+    unsigned TOP                 : 11;
+    unsigned PAD                 : 5;
+    unsigned BOTTOM              : 11;
+} REG_VGV1_SCISSORY;
+
+// VGV1_TILEOFS
+typedef struct _REG_VGV1_TILEOFS {
+    unsigned X                   : 12;
+    unsigned Y                   : 12;
+    unsigned LEFTMOST            : 1;
+} REG_VGV1_TILEOFS;
+
+// VGV1_UBASE2
+typedef struct _REG_VGV1_UBASE2 {
+    unsigned ADDR                : 32;
+} REG_VGV1_UBASE2;
+
+// VGV1_VTX0
+typedef struct _REG_VGV1_VTX0 {
+    int X                   : 16;
+    int Y                   : 16;
+} REG_VGV1_VTX0;
+
+// VGV1_VTX1
+typedef struct _REG_VGV1_VTX1 {
+    int X                   : 16;
+    int Y                   : 16;
+} REG_VGV1_VTX1;
+
+// VGV2_ACCURACY
+typedef struct _REG_VGV2_ACCURACY {
+    unsigned F                   : 24;
+} REG_VGV2_ACCURACY;
+
+// VGV2_ACTION
+typedef struct _REG_VGV2_ACTION {
+    unsigned ACTION              : 4;
+} REG_VGV2_ACTION;
+
+// VGV2_ARCCOS
+typedef struct _REG_VGV2_ARCCOS {
+    unsigned F                   : 24;
+} REG_VGV2_ARCCOS;
+
+// VGV2_ARCSIN
+typedef struct _REG_VGV2_ARCSIN {
+    unsigned F                   : 24;
+} REG_VGV2_ARCSIN;
+
+// VGV2_ARCTAN
+typedef struct _REG_VGV2_ARCTAN {
+    unsigned F                   : 24;
+} REG_VGV2_ARCTAN;
+
+// VGV2_BBOXMAXX
+typedef struct _REG_VGV2_BBOXMAXX {
+    unsigned F                   : 24;
+} REG_VGV2_BBOXMAXX;
+
+// VGV2_BBOXMAXY
+typedef struct _REG_VGV2_BBOXMAXY {
+    unsigned F                   : 24;
+} REG_VGV2_BBOXMAXY;
+
+// VGV2_BBOXMINX
+typedef struct _REG_VGV2_BBOXMINX {
+    unsigned F                   : 24;
+} REG_VGV2_BBOXMINX;
+
+// VGV2_BBOXMINY
+typedef struct _REG_VGV2_BBOXMINY {
+    unsigned F                   : 24;
+} REG_VGV2_BBOXMINY;
+
+// VGV2_BIAS
+typedef struct _REG_VGV2_BIAS {
+    unsigned F                   : 24;
+} REG_VGV2_BIAS;
+
+// VGV2_C1X
+typedef struct _REG_VGV2_C1X {
+    unsigned F                   : 24;
+} REG_VGV2_C1X;
+
+// VGV2_C1XREL
+typedef struct _REG_VGV2_C1XREL {
+    unsigned F                   : 24;
+} REG_VGV2_C1XREL;
+
+// VGV2_C1Y
+typedef struct _REG_VGV2_C1Y {
+    unsigned F                   : 24;
+} REG_VGV2_C1Y;
+
+// VGV2_C1YREL
+typedef struct _REG_VGV2_C1YREL {
+    unsigned F                   : 24;
+} REG_VGV2_C1YREL;
+
+// VGV2_C2X
+typedef struct _REG_VGV2_C2X {
+    unsigned F                   : 24;
+} REG_VGV2_C2X;
+
+// VGV2_C2XREL
+typedef struct _REG_VGV2_C2XREL {
+    unsigned F                   : 24;
+} REG_VGV2_C2XREL;
+
+// VGV2_C2Y
+typedef struct _REG_VGV2_C2Y {
+    unsigned F                   : 24;
+} REG_VGV2_C2Y;
+
+// VGV2_C2YREL
+typedef struct _REG_VGV2_C2YREL {
+    unsigned F                   : 24;
+} REG_VGV2_C2YREL;
+
+// VGV2_C3X
+typedef struct _REG_VGV2_C3X {
+    unsigned F                   : 24;
+} REG_VGV2_C3X;
+
+// VGV2_C3XREL
+typedef struct _REG_VGV2_C3XREL {
+    unsigned F                   : 24;
+} REG_VGV2_C3XREL;
+
+// VGV2_C3Y
+typedef struct _REG_VGV2_C3Y {
+    unsigned F                   : 24;
+} REG_VGV2_C3Y;
+
+// VGV2_C3YREL
+typedef struct _REG_VGV2_C3YREL {
+    unsigned F                   : 24;
+} REG_VGV2_C3YREL;
+
+// VGV2_C4X
+typedef struct _REG_VGV2_C4X {
+    unsigned F                   : 24;
+} REG_VGV2_C4X;
+
+// VGV2_C4XREL
+typedef struct _REG_VGV2_C4XREL {
+    unsigned F                   : 24;
+} REG_VGV2_C4XREL;
+
+// VGV2_C4Y
+typedef struct _REG_VGV2_C4Y {
+    unsigned F                   : 24;
+} REG_VGV2_C4Y;
+
+// VGV2_C4YREL
+typedef struct _REG_VGV2_C4YREL {
+    unsigned F                   : 24;
+} REG_VGV2_C4YREL;
+
+// VGV2_CLIP
+typedef struct _REG_VGV2_CLIP {
+    unsigned F                   : 24;
+} REG_VGV2_CLIP;
+
+// VGV2_FIRST
+typedef struct _REG_VGV2_FIRST {
+    unsigned DUMMY               : 1;
+} REG_VGV2_FIRST;
+
+// VGV2_LAST
+typedef struct _REG_VGV2_LAST {
+    unsigned DUMMY               : 1;
+} REG_VGV2_LAST;
+
+// VGV2_MITER
+typedef struct _REG_VGV2_MITER {
+    unsigned F                   : 24;
+} REG_VGV2_MITER;
+
+// VGV2_MODE
+typedef struct _REG_VGV2_MODE {
+    unsigned MAXSPLIT            : 4;
+    unsigned CAP                 : 2;
+    unsigned JOIN                : 2;
+    unsigned STROKE              : 1;
+    unsigned STROKESPLIT         : 1;
+    unsigned FULLSPLIT           : 1;
+    unsigned NODOTS              : 1;
+    unsigned OPENFILL            : 1;
+    unsigned DROPLEFT            : 1;
+    unsigned DROPOTHER           : 1;
+    unsigned SYMMETRICJOINS      : 1;
+    unsigned SIMPLESTROKE        : 1;
+    unsigned SIMPLECLIP          : 1;
+    int EXPONENTADD         : 6;
+} REG_VGV2_MODE;
+
+// VGV2_RADIUS
+typedef struct _REG_VGV2_RADIUS {
+    unsigned F                   : 24;
+} REG_VGV2_RADIUS;
+
+// VGV2_SCALE
+typedef struct _REG_VGV2_SCALE {
+    unsigned F                   : 24;
+} REG_VGV2_SCALE;
+
+// VGV2_THINRADIUS
+typedef struct _REG_VGV2_THINRADIUS {
+    unsigned F                   : 24;
+} REG_VGV2_THINRADIUS;
+
+// VGV2_XFSTXX
+typedef struct _REG_VGV2_XFSTXX {
+    unsigned F                   : 24;
+} REG_VGV2_XFSTXX;
+
+// VGV2_XFSTXY
+typedef struct _REG_VGV2_XFSTXY {
+    unsigned F                   : 24;
+} REG_VGV2_XFSTXY;
+
+// VGV2_XFSTYX
+typedef struct _REG_VGV2_XFSTYX {
+    unsigned F                   : 24;
+} REG_VGV2_XFSTYX;
+
+// VGV2_XFSTYY
+typedef struct _REG_VGV2_XFSTYY {
+    unsigned F                   : 24;
+} REG_VGV2_XFSTYY;
+
+// VGV2_XFXA
+typedef struct _REG_VGV2_XFXA {
+    unsigned F                   : 24;
+} REG_VGV2_XFXA;
+
+// VGV2_XFXX
+typedef struct _REG_VGV2_XFXX {
+    unsigned F                   : 24;
+} REG_VGV2_XFXX;
+
+// VGV2_XFXY
+typedef struct _REG_VGV2_XFXY {
+    unsigned F                   : 24;
+} REG_VGV2_XFXY;
+
+// VGV2_XFYA
+typedef struct _REG_VGV2_XFYA {
+    unsigned F                   : 24;
+} REG_VGV2_XFYA;
+
+// VGV2_XFYX
+typedef struct _REG_VGV2_XFYX {
+    unsigned F                   : 24;
+} REG_VGV2_XFYX;
+
+// VGV2_XFYY
+typedef struct _REG_VGV2_XFYY {
+    unsigned F                   : 24;
+} REG_VGV2_XFYY;
+
+// VGV3_CONTROL
+typedef struct _REG_VGV3_CONTROL {
+    unsigned MARKADD             : 12;
+    unsigned DMIWAITCHMASK       : 4;
+    unsigned PAUSE               : 1;
+    unsigned ABORT               : 1;
+    unsigned WRITE               : 1;
+    unsigned BCFLUSH             : 1;
+    unsigned V0SYNC              : 1;
+    unsigned DMIWAITBUF          : 3;
+} REG_VGV3_CONTROL;
+
+// VGV3_FIRST
+typedef struct _REG_VGV3_FIRST {
+    unsigned DUMMY               : 1;
+} REG_VGV3_FIRST;
+
+// VGV3_LAST
+typedef struct _REG_VGV3_LAST {
+    unsigned DUMMY               : 1;
+} REG_VGV3_LAST;
+
+// VGV3_MODE
+typedef struct _REG_VGV3_MODE {
+    unsigned FLIPENDIAN          : 1;
+    unsigned UNUSED              : 1;
+    unsigned WRITEFLUSH          : 1;
+    unsigned DMIPAUSETYPE        : 1;
+    unsigned DMIRESET            : 1;
+} REG_VGV3_MODE;
+
+// VGV3_NEXTADDR
+typedef struct _REG_VGV3_NEXTADDR {
+    unsigned CALLADDR            : 32;
+} REG_VGV3_NEXTADDR;
+
+// VGV3_NEXTCMD
+typedef struct _REG_VGV3_NEXTCMD {
+    unsigned COUNT               : 12;
+    unsigned NEXTCMD             : 3;
+    unsigned MARK                : 1;
+    unsigned CALLCOUNT           : 12;
+} REG_VGV3_NEXTCMD;
+
+// VGV3_VGBYPASS
+typedef struct _REG_VGV3_VGBYPASS {
+    unsigned BYPASS              : 1;
+} REG_VGV3_VGBYPASS;
+
+// VGV3_WRITE
+typedef struct _REG_VGV3_WRITE {
+    unsigned VALUE               : 32;
+} REG_VGV3_WRITE;
+
+// VGV3_WRITEADDR
+typedef struct _REG_VGV3_WRITEADDR {
+    unsigned ADDR                : 32;
+} REG_VGV3_WRITEADDR;
+
+// VGV3_WRITEDMI
+typedef struct _REG_VGV3_WRITEDMI {
+    unsigned CHANMASK            : 4;
+    unsigned BUFFER              : 3;
+} REG_VGV3_WRITEDMI;
+
+// VGV3_WRITEF32
+typedef struct _REG_VGV3_WRITEF32 {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITEF32;
+
+// VGV3_WRITEIFPAUSED
+typedef struct _REG_VGV3_WRITEIFPAUSED {
+    unsigned VALUE               : 32;
+} REG_VGV3_WRITEIFPAUSED;
+
+// VGV3_WRITERAW
+typedef struct _REG_VGV3_WRITERAW {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITERAW;
+
+// VGV3_WRITES16
+typedef struct _REG_VGV3_WRITES16 {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITES16;
+
+// VGV3_WRITES32
+typedef struct _REG_VGV3_WRITES32 {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITES32;
+
+// VGV3_WRITES8
+typedef struct _REG_VGV3_WRITES8 {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITES8;
+
+// Register address, down shift, AND mask
+#define FBC_BASE_BASE_FADDR ADDR_FBC_BASE
+#define FBC_BASE_BASE_FSHIFT 0
+#define FBC_BASE_BASE_FMASK 0xffffffff
+#define FBC_DATA_DATA_FADDR ADDR_FBC_DATA
+#define FBC_DATA_DATA_FSHIFT 0
+#define FBC_DATA_DATA_FMASK 0xffffffff
+#define FBC_HEIGHT_HEIGHT_FADDR ADDR_FBC_HEIGHT
+#define FBC_HEIGHT_HEIGHT_FSHIFT 0
+#define FBC_HEIGHT_HEIGHT_FMASK 0x7ff
+#define FBC_START_DUMMY_FADDR ADDR_FBC_START
+#define FBC_START_DUMMY_FSHIFT 0
+#define FBC_START_DUMMY_FMASK 0x1
+#define FBC_STRIDE_STRIDE_FADDR ADDR_FBC_STRIDE
+#define FBC_STRIDE_STRIDE_FSHIFT 0
+#define FBC_STRIDE_STRIDE_FMASK 0x7ff
+#define FBC_WIDTH_WIDTH_FADDR ADDR_FBC_WIDTH
+#define FBC_WIDTH_WIDTH_FSHIFT 0
+#define FBC_WIDTH_WIDTH_FMASK 0x7ff
+#define VGC_CLOCKEN_BCACHE_FADDR ADDR_VGC_CLOCKEN
+#define VGC_CLOCKEN_BCACHE_FSHIFT 0
+#define VGC_CLOCKEN_BCACHE_FMASK 0x1
+#define VGC_CLOCKEN_G2D_VGL3_FADDR ADDR_VGC_CLOCKEN
+#define VGC_CLOCKEN_G2D_VGL3_FSHIFT 1
+#define VGC_CLOCKEN_G2D_VGL3_FMASK 0x1
+#define VGC_CLOCKEN_VG_L1L2_FADDR ADDR_VGC_CLOCKEN
+#define VGC_CLOCKEN_VG_L1L2_FSHIFT 2
+#define VGC_CLOCKEN_VG_L1L2_FMASK 0x1
+#define VGC_CLOCKEN_RESERVED_FADDR ADDR_VGC_CLOCKEN
+#define VGC_CLOCKEN_RESERVED_FSHIFT 3
+#define VGC_CLOCKEN_RESERVED_FMASK 0x7
+#define VGC_COMMANDSTREAM_DATA_FADDR ADDR_VGC_COMMANDSTREAM
+#define VGC_COMMANDSTREAM_DATA_FSHIFT 0
+#define VGC_COMMANDSTREAM_DATA_FMASK 0xffffffff
+#define VGC_FIFOFREE_FREE_FADDR ADDR_VGC_FIFOFREE
+#define VGC_FIFOFREE_FREE_FSHIFT 0
+#define VGC_FIFOFREE_FREE_FMASK 0x1
+#define VGC_IRQENABLE_MH_FADDR ADDR_VGC_IRQENABLE
+#define VGC_IRQENABLE_MH_FSHIFT 0
+#define VGC_IRQENABLE_MH_FMASK 0x1
+#define VGC_IRQENABLE_G2D_FADDR ADDR_VGC_IRQENABLE
+#define VGC_IRQENABLE_G2D_FSHIFT 1
+#define VGC_IRQENABLE_G2D_FMASK 0x1
+#define VGC_IRQENABLE_FIFO_FADDR ADDR_VGC_IRQENABLE
+#define VGC_IRQENABLE_FIFO_FSHIFT 2
+#define VGC_IRQENABLE_FIFO_FMASK 0x1
+#define VGC_IRQENABLE_FBC_FADDR ADDR_VGC_IRQENABLE
+#define VGC_IRQENABLE_FBC_FSHIFT 3
+#define VGC_IRQENABLE_FBC_FMASK 0x1
+#define VGC_IRQSTATUS_MH_FADDR ADDR_VGC_IRQSTATUS
+#define VGC_IRQSTATUS_MH_FSHIFT 0
+#define VGC_IRQSTATUS_MH_FMASK 0x1
+#define VGC_IRQSTATUS_G2D_FADDR ADDR_VGC_IRQSTATUS
+#define VGC_IRQSTATUS_G2D_FSHIFT 1
+#define VGC_IRQSTATUS_G2D_FMASK 0x1
+#define VGC_IRQSTATUS_FIFO_FADDR ADDR_VGC_IRQSTATUS
+#define VGC_IRQSTATUS_FIFO_FSHIFT 2
+#define VGC_IRQSTATUS_FIFO_FMASK 0x1
+#define VGC_IRQSTATUS_FBC_FADDR ADDR_VGC_IRQSTATUS
+#define VGC_IRQSTATUS_FBC_FSHIFT 3
+#define VGC_IRQSTATUS_FBC_FMASK 0x1
+#define VGC_IRQ_ACTIVE_CNT_MH_FADDR ADDR_VGC_IRQ_ACTIVE_CNT
+#define VGC_IRQ_ACTIVE_CNT_MH_FSHIFT 0
+#define VGC_IRQ_ACTIVE_CNT_MH_FMASK 0xff
+#define VGC_IRQ_ACTIVE_CNT_G2D_FADDR ADDR_VGC_IRQ_ACTIVE_CNT
+#define VGC_IRQ_ACTIVE_CNT_G2D_FSHIFT 8
+#define VGC_IRQ_ACTIVE_CNT_G2D_FMASK 0xff
+#define VGC_IRQ_ACTIVE_CNT_ERRORS_FADDR ADDR_VGC_IRQ_ACTIVE_CNT
+#define VGC_IRQ_ACTIVE_CNT_ERRORS_FSHIFT 16
+#define VGC_IRQ_ACTIVE_CNT_ERRORS_FMASK 0xff
+#define VGC_IRQ_ACTIVE_CNT_FBC_FADDR ADDR_VGC_IRQ_ACTIVE_CNT
+#define VGC_IRQ_ACTIVE_CNT_FBC_FSHIFT 24
+#define VGC_IRQ_ACTIVE_CNT_FBC_FMASK 0xff
+#define VGC_MMUCOMMANDSTREAM_DATA_FADDR ADDR_VGC_MMUCOMMANDSTREAM
+#define VGC_MMUCOMMANDSTREAM_DATA_FSHIFT 0
+#define VGC_MMUCOMMANDSTREAM_DATA_FMASK 0xffffffff
+#define VGC_REVISION_MINOR_REVISION_FADDR ADDR_VGC_REVISION
+#define VGC_REVISION_MINOR_REVISION_FSHIFT 0
+#define VGC_REVISION_MINOR_REVISION_FMASK 0xf
+#define VGC_REVISION_MAJOR_REVISION_FADDR ADDR_VGC_REVISION
+#define VGC_REVISION_MAJOR_REVISION_FSHIFT 4
+#define VGC_REVISION_MAJOR_REVISION_FMASK 0xf
+#define VGC_SYSSTATUS_RESET_FADDR ADDR_VGC_SYSSTATUS
+#define VGC_SYSSTATUS_RESET_FSHIFT 0
+#define VGC_SYSSTATUS_RESET_FMASK 0x1
+#define G2D_ALPHABLEND_ALPHA_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_ALPHA_FSHIFT 0
+#define G2D_ALPHABLEND_ALPHA_FMASK 0xff
+#define G2D_ALPHABLEND_OBS_ENABLE_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_OBS_ENABLE_FSHIFT 8
+#define G2D_ALPHABLEND_OBS_ENABLE_FMASK 0x1
+#define G2D_ALPHABLEND_CONSTANT_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_CONSTANT_FSHIFT 9
+#define G2D_ALPHABLEND_CONSTANT_FMASK 0x1
+#define G2D_ALPHABLEND_INVERT_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_INVERT_FSHIFT 10
+#define G2D_ALPHABLEND_INVERT_FMASK 0x1
+#define G2D_ALPHABLEND_OPTIMIZE_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_OPTIMIZE_FSHIFT 11
+#define G2D_ALPHABLEND_OPTIMIZE_FMASK 0x1
+#define G2D_ALPHABLEND_MODULATE_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_MODULATE_FSHIFT 12
+#define G2D_ALPHABLEND_MODULATE_FMASK 0x1
+#define G2D_ALPHABLEND_INVERTMASK_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_INVERTMASK_FSHIFT 13
+#define G2D_ALPHABLEND_INVERTMASK_FMASK 0x1
+#define G2D_ALPHABLEND_PREMULTIPLYDST_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_PREMULTIPLYDST_FSHIFT 14
+#define G2D_ALPHABLEND_PREMULTIPLYDST_FMASK 0x1
+#define G2D_ALPHABLEND_MASKTOALPHA_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_MASKTOALPHA_FSHIFT 15
+#define G2D_ALPHABLEND_MASKTOALPHA_FMASK 0x1
+#define G2D_BACKGROUND_COLOR_FADDR ADDR_G2D_BACKGROUND
+#define G2D_BACKGROUND_COLOR_FSHIFT 0
+#define G2D_BACKGROUND_COLOR_FMASK 0xffffffff
+#define G2D_BASE0_ADDR_FADDR ADDR_G2D_BASE0
+#define G2D_BASE0_ADDR_FSHIFT 0
+#define G2D_BASE0_ADDR_FMASK 0xffffffff
+#define G2D_BASE1_ADDR_FADDR ADDR_G2D_BASE1
+#define G2D_BASE1_ADDR_FSHIFT 0
+#define G2D_BASE1_ADDR_FMASK 0xffffffff
+#define G2D_BASE2_ADDR_FADDR ADDR_G2D_BASE2
+#define G2D_BASE2_ADDR_FSHIFT 0
+#define G2D_BASE2_ADDR_FMASK 0xffffffff
+#define G2D_BASE3_ADDR_FADDR ADDR_G2D_BASE3
+#define G2D_BASE3_ADDR_FSHIFT 0
+#define G2D_BASE3_ADDR_FMASK 0xffffffff
+#define G2D_BLENDERCFG_PASSES_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_PASSES_FSHIFT 0
+#define G2D_BLENDERCFG_PASSES_FMASK 0x7
+#define G2D_BLENDERCFG_ALPHAPASSES_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_ALPHAPASSES_FSHIFT 3
+#define G2D_BLENDERCFG_ALPHAPASSES_FMASK 0x3
+#define G2D_BLENDERCFG_ENABLE_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_ENABLE_FSHIFT 5
+#define G2D_BLENDERCFG_ENABLE_FMASK 0x1
+#define G2D_BLENDERCFG_OOALPHA_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_OOALPHA_FSHIFT 6
+#define G2D_BLENDERCFG_OOALPHA_FMASK 0x1
+#define G2D_BLENDERCFG_OBS_DIVALPHA_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_OBS_DIVALPHA_FSHIFT 7
+#define G2D_BLENDERCFG_OBS_DIVALPHA_FMASK 0x1
+#define G2D_BLENDERCFG_NOMASK_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_NOMASK_FSHIFT 8
+#define G2D_BLENDERCFG_NOMASK_FMASK 0x1
+#define G2D_BLEND_A0_OPERATION_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_OPERATION_FSHIFT 0
+#define G2D_BLEND_A0_OPERATION_FMASK 0x3
+#define G2D_BLEND_A0_DST_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_DST_A_FSHIFT 2
+#define G2D_BLEND_A0_DST_A_FMASK 0x3
+#define G2D_BLEND_A0_DST_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_DST_B_FSHIFT 4
+#define G2D_BLEND_A0_DST_B_FMASK 0x3
+#define G2D_BLEND_A0_DST_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_DST_C_FSHIFT 6
+#define G2D_BLEND_A0_DST_C_FMASK 0x3
+#define G2D_BLEND_A0_AR_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_AR_A_FSHIFT 8
+#define G2D_BLEND_A0_AR_A_FMASK 0x1
+#define G2D_BLEND_A0_AR_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_AR_B_FSHIFT 9
+#define G2D_BLEND_A0_AR_B_FMASK 0x1
+#define G2D_BLEND_A0_AR_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_AR_C_FSHIFT 10
+#define G2D_BLEND_A0_AR_C_FMASK 0x1
+#define G2D_BLEND_A0_AR_D_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_AR_D_FSHIFT 11
+#define G2D_BLEND_A0_AR_D_FMASK 0x1
+#define G2D_BLEND_A0_INV_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_INV_A_FSHIFT 12
+#define G2D_BLEND_A0_INV_A_FMASK 0x1
+#define G2D_BLEND_A0_INV_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_INV_B_FSHIFT 13
+#define G2D_BLEND_A0_INV_B_FMASK 0x1
+#define G2D_BLEND_A0_INV_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_INV_C_FSHIFT 14
+#define G2D_BLEND_A0_INV_C_FMASK 0x1
+#define G2D_BLEND_A0_INV_D_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_INV_D_FSHIFT 15
+#define G2D_BLEND_A0_INV_D_FMASK 0x1
+#define G2D_BLEND_A0_SRC_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_SRC_A_FSHIFT 16
+#define G2D_BLEND_A0_SRC_A_FMASK 0x7
+#define G2D_BLEND_A0_SRC_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_SRC_B_FSHIFT 19
+#define G2D_BLEND_A0_SRC_B_FMASK 0x7
+#define G2D_BLEND_A0_SRC_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_SRC_C_FSHIFT 22
+#define G2D_BLEND_A0_SRC_C_FMASK 0x7
+#define G2D_BLEND_A0_SRC_D_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_SRC_D_FSHIFT 25
+#define G2D_BLEND_A0_SRC_D_FMASK 0x7
+#define G2D_BLEND_A0_CONST_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_CONST_A_FSHIFT 28
+#define G2D_BLEND_A0_CONST_A_FMASK 0x1
+#define G2D_BLEND_A0_CONST_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_CONST_B_FSHIFT 29
+#define G2D_BLEND_A0_CONST_B_FMASK 0x1
+#define G2D_BLEND_A0_CONST_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_CONST_C_FSHIFT 30
+#define G2D_BLEND_A0_CONST_C_FMASK 0x1
+#define G2D_BLEND_A0_CONST_D_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_CONST_D_FSHIFT 31
+#define G2D_BLEND_A0_CONST_D_FMASK 0x1
+#define G2D_BLEND_A1_OPERATION_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_OPERATION_FSHIFT 0
+#define G2D_BLEND_A1_OPERATION_FMASK 0x3
+#define G2D_BLEND_A1_DST_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_DST_A_FSHIFT 2
+#define G2D_BLEND_A1_DST_A_FMASK 0x3
+#define G2D_BLEND_A1_DST_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_DST_B_FSHIFT 4
+#define G2D_BLEND_A1_DST_B_FMASK 0x3
+#define G2D_BLEND_A1_DST_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_DST_C_FSHIFT 6
+#define G2D_BLEND_A1_DST_C_FMASK 0x3
+#define G2D_BLEND_A1_AR_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_AR_A_FSHIFT 8
+#define G2D_BLEND_A1_AR_A_FMASK 0x1
+#define G2D_BLEND_A1_AR_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_AR_B_FSHIFT 9
+#define G2D_BLEND_A1_AR_B_FMASK 0x1
+#define G2D_BLEND_A1_AR_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_AR_C_FSHIFT 10
+#define G2D_BLEND_A1_AR_C_FMASK 0x1
+#define G2D_BLEND_A1_AR_D_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_AR_D_FSHIFT 11
+#define G2D_BLEND_A1_AR_D_FMASK 0x1
+#define G2D_BLEND_A1_INV_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_INV_A_FSHIFT 12
+#define G2D_BLEND_A1_INV_A_FMASK 0x1
+#define G2D_BLEND_A1_INV_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_INV_B_FSHIFT 13
+#define G2D_BLEND_A1_INV_B_FMASK 0x1
+#define G2D_BLEND_A1_INV_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_INV_C_FSHIFT 14
+#define G2D_BLEND_A1_INV_C_FMASK 0x1
+#define G2D_BLEND_A1_INV_D_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_INV_D_FSHIFT 15
+#define G2D_BLEND_A1_INV_D_FMASK 0x1
+#define G2D_BLEND_A1_SRC_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_SRC_A_FSHIFT 16
+#define G2D_BLEND_A1_SRC_A_FMASK 0x7
+#define G2D_BLEND_A1_SRC_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_SRC_B_FSHIFT 19
+#define G2D_BLEND_A1_SRC_B_FMASK 0x7
+#define G2D_BLEND_A1_SRC_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_SRC_C_FSHIFT 22
+#define G2D_BLEND_A1_SRC_C_FMASK 0x7
+#define G2D_BLEND_A1_SRC_D_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_SRC_D_FSHIFT 25
+#define G2D_BLEND_A1_SRC_D_FMASK 0x7
+#define G2D_BLEND_A1_CONST_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_CONST_A_FSHIFT 28
+#define G2D_BLEND_A1_CONST_A_FMASK 0x1
+#define G2D_BLEND_A1_CONST_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_CONST_B_FSHIFT 29
+#define G2D_BLEND_A1_CONST_B_FMASK 0x1
+#define G2D_BLEND_A1_CONST_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_CONST_C_FSHIFT 30
+#define G2D_BLEND_A1_CONST_C_FMASK 0x1
+#define G2D_BLEND_A1_CONST_D_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_CONST_D_FSHIFT 31
+#define G2D_BLEND_A1_CONST_D_FMASK 0x1
+#define G2D_BLEND_A2_OPERATION_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_OPERATION_FSHIFT 0
+#define G2D_BLEND_A2_OPERATION_FMASK 0x3
+#define G2D_BLEND_A2_DST_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_DST_A_FSHIFT 2
+#define G2D_BLEND_A2_DST_A_FMASK 0x3
+#define G2D_BLEND_A2_DST_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_DST_B_FSHIFT 4
+#define G2D_BLEND_A2_DST_B_FMASK 0x3
+#define G2D_BLEND_A2_DST_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_DST_C_FSHIFT 6
+#define G2D_BLEND_A2_DST_C_FMASK 0x3
+#define G2D_BLEND_A2_AR_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_AR_A_FSHIFT 8
+#define G2D_BLEND_A2_AR_A_FMASK 0x1
+#define G2D_BLEND_A2_AR_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_AR_B_FSHIFT 9
+#define G2D_BLEND_A2_AR_B_FMASK 0x1
+#define G2D_BLEND_A2_AR_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_AR_C_FSHIFT 10
+#define G2D_BLEND_A2_AR_C_FMASK 0x1
+#define G2D_BLEND_A2_AR_D_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_AR_D_FSHIFT 11
+#define G2D_BLEND_A2_AR_D_FMASK 0x1
+#define G2D_BLEND_A2_INV_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_INV_A_FSHIFT 12
+#define G2D_BLEND_A2_INV_A_FMASK 0x1
+#define G2D_BLEND_A2_INV_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_INV_B_FSHIFT 13
+#define G2D_BLEND_A2_INV_B_FMASK 0x1
+#define G2D_BLEND_A2_INV_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_INV_C_FSHIFT 14
+#define G2D_BLEND_A2_INV_C_FMASK 0x1
+#define G2D_BLEND_A2_INV_D_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_INV_D_FSHIFT 15
+#define G2D_BLEND_A2_INV_D_FMASK 0x1
+#define G2D_BLEND_A2_SRC_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_SRC_A_FSHIFT 16
+#define G2D_BLEND_A2_SRC_A_FMASK 0x7
+#define G2D_BLEND_A2_SRC_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_SRC_B_FSHIFT 19
+#define G2D_BLEND_A2_SRC_B_FMASK 0x7
+#define G2D_BLEND_A2_SRC_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_SRC_C_FSHIFT 22
+#define G2D_BLEND_A2_SRC_C_FMASK 0x7
+#define G2D_BLEND_A2_SRC_D_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_SRC_D_FSHIFT 25
+#define G2D_BLEND_A2_SRC_D_FMASK 0x7
+#define G2D_BLEND_A2_CONST_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_CONST_A_FSHIFT 28
+#define G2D_BLEND_A2_CONST_A_FMASK 0x1
+#define G2D_BLEND_A2_CONST_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_CONST_B_FSHIFT 29
+#define G2D_BLEND_A2_CONST_B_FMASK 0x1
+#define G2D_BLEND_A2_CONST_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_CONST_C_FSHIFT 30
+#define G2D_BLEND_A2_CONST_C_FMASK 0x1
+#define G2D_BLEND_A2_CONST_D_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_CONST_D_FSHIFT 31
+#define G2D_BLEND_A2_CONST_D_FMASK 0x1
+#define G2D_BLEND_A3_OPERATION_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_OPERATION_FSHIFT 0
+#define G2D_BLEND_A3_OPERATION_FMASK 0x3
+#define G2D_BLEND_A3_DST_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_DST_A_FSHIFT 2
+#define G2D_BLEND_A3_DST_A_FMASK 0x3
+#define G2D_BLEND_A3_DST_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_DST_B_FSHIFT 4
+#define G2D_BLEND_A3_DST_B_FMASK 0x3
+#define G2D_BLEND_A3_DST_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_DST_C_FSHIFT 6
+#define G2D_BLEND_A3_DST_C_FMASK 0x3
+#define G2D_BLEND_A3_AR_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_AR_A_FSHIFT 8
+#define G2D_BLEND_A3_AR_A_FMASK 0x1
+#define G2D_BLEND_A3_AR_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_AR_B_FSHIFT 9
+#define G2D_BLEND_A3_AR_B_FMASK 0x1
+#define G2D_BLEND_A3_AR_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_AR_C_FSHIFT 10
+#define G2D_BLEND_A3_AR_C_FMASK 0x1
+#define G2D_BLEND_A3_AR_D_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_AR_D_FSHIFT 11
+#define G2D_BLEND_A3_AR_D_FMASK 0x1
+#define G2D_BLEND_A3_INV_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_INV_A_FSHIFT 12
+#define G2D_BLEND_A3_INV_A_FMASK 0x1
+#define G2D_BLEND_A3_INV_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_INV_B_FSHIFT 13
+#define G2D_BLEND_A3_INV_B_FMASK 0x1
+#define G2D_BLEND_A3_INV_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_INV_C_FSHIFT 14
+#define G2D_BLEND_A3_INV_C_FMASK 0x1
+#define G2D_BLEND_A3_INV_D_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_INV_D_FSHIFT 15
+#define G2D_BLEND_A3_INV_D_FMASK 0x1
+#define G2D_BLEND_A3_SRC_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_SRC_A_FSHIFT 16
+#define G2D_BLEND_A3_SRC_A_FMASK 0x7
+#define G2D_BLEND_A3_SRC_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_SRC_B_FSHIFT 19
+#define G2D_BLEND_A3_SRC_B_FMASK 0x7
+#define G2D_BLEND_A3_SRC_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_SRC_C_FSHIFT 22
+#define G2D_BLEND_A3_SRC_C_FMASK 0x7
+#define G2D_BLEND_A3_SRC_D_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_SRC_D_FSHIFT 25
+#define G2D_BLEND_A3_SRC_D_FMASK 0x7
+#define G2D_BLEND_A3_CONST_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_CONST_A_FSHIFT 28
+#define G2D_BLEND_A3_CONST_A_FMASK 0x1
+#define G2D_BLEND_A3_CONST_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_CONST_B_FSHIFT 29
+#define G2D_BLEND_A3_CONST_B_FMASK 0x1
+#define G2D_BLEND_A3_CONST_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_CONST_C_FSHIFT 30
+#define G2D_BLEND_A3_CONST_C_FMASK 0x1
+#define G2D_BLEND_A3_CONST_D_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_CONST_D_FSHIFT 31
+#define G2D_BLEND_A3_CONST_D_FMASK 0x1
+#define G2D_BLEND_C0_OPERATION_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_OPERATION_FSHIFT 0
+#define G2D_BLEND_C0_OPERATION_FMASK 0x3
+#define G2D_BLEND_C0_DST_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_DST_A_FSHIFT 2
+#define G2D_BLEND_C0_DST_A_FMASK 0x3
+#define G2D_BLEND_C0_DST_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_DST_B_FSHIFT 4
+#define G2D_BLEND_C0_DST_B_FMASK 0x3
+#define G2D_BLEND_C0_DST_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_DST_C_FSHIFT 6
+#define G2D_BLEND_C0_DST_C_FMASK 0x3
+#define G2D_BLEND_C0_AR_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_AR_A_FSHIFT 8
+#define G2D_BLEND_C0_AR_A_FMASK 0x1
+#define G2D_BLEND_C0_AR_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_AR_B_FSHIFT 9
+#define G2D_BLEND_C0_AR_B_FMASK 0x1
+#define G2D_BLEND_C0_AR_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_AR_C_FSHIFT 10
+#define G2D_BLEND_C0_AR_C_FMASK 0x1
+#define G2D_BLEND_C0_AR_D_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_AR_D_FSHIFT 11
+#define G2D_BLEND_C0_AR_D_FMASK 0x1
+#define G2D_BLEND_C0_INV_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_INV_A_FSHIFT 12
+#define G2D_BLEND_C0_INV_A_FMASK 0x1
+#define G2D_BLEND_C0_INV_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_INV_B_FSHIFT 13
+#define G2D_BLEND_C0_INV_B_FMASK 0x1
+#define G2D_BLEND_C0_INV_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_INV_C_FSHIFT 14
+#define G2D_BLEND_C0_INV_C_FMASK 0x1
+#define G2D_BLEND_C0_INV_D_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_INV_D_FSHIFT 15
+#define G2D_BLEND_C0_INV_D_FMASK 0x1
+#define G2D_BLEND_C0_SRC_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_SRC_A_FSHIFT 16
+#define G2D_BLEND_C0_SRC_A_FMASK 0x7
+#define G2D_BLEND_C0_SRC_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_SRC_B_FSHIFT 19
+#define G2D_BLEND_C0_SRC_B_FMASK 0x7
+#define G2D_BLEND_C0_SRC_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_SRC_C_FSHIFT 22
+#define G2D_BLEND_C0_SRC_C_FMASK 0x7
+#define G2D_BLEND_C0_SRC_D_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_SRC_D_FSHIFT 25
+#define G2D_BLEND_C0_SRC_D_FMASK 0x7
+#define G2D_BLEND_C0_CONST_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_CONST_A_FSHIFT 28
+#define G2D_BLEND_C0_CONST_A_FMASK 0x1
+#define G2D_BLEND_C0_CONST_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_CONST_B_FSHIFT 29
+#define G2D_BLEND_C0_CONST_B_FMASK 0x1
+#define G2D_BLEND_C0_CONST_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_CONST_C_FSHIFT 30
+#define G2D_BLEND_C0_CONST_C_FMASK 0x1
+#define G2D_BLEND_C0_CONST_D_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_CONST_D_FSHIFT 31
+#define G2D_BLEND_C0_CONST_D_FMASK 0x1
+#define G2D_BLEND_C1_OPERATION_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_OPERATION_FSHIFT 0
+#define G2D_BLEND_C1_OPERATION_FMASK 0x3
+#define G2D_BLEND_C1_DST_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_DST_A_FSHIFT 2
+#define G2D_BLEND_C1_DST_A_FMASK 0x3
+#define G2D_BLEND_C1_DST_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_DST_B_FSHIFT 4
+#define G2D_BLEND_C1_DST_B_FMASK 0x3
+#define G2D_BLEND_C1_DST_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_DST_C_FSHIFT 6
+#define G2D_BLEND_C1_DST_C_FMASK 0x3
+#define G2D_BLEND_C1_AR_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_AR_A_FSHIFT 8
+#define G2D_BLEND_C1_AR_A_FMASK 0x1
+#define G2D_BLEND_C1_AR_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_AR_B_FSHIFT 9
+#define G2D_BLEND_C1_AR_B_FMASK 0x1
+#define G2D_BLEND_C1_AR_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_AR_C_FSHIFT 10
+#define G2D_BLEND_C1_AR_C_FMASK 0x1
+#define G2D_BLEND_C1_AR_D_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_AR_D_FSHIFT 11
+#define G2D_BLEND_C1_AR_D_FMASK 0x1
+#define G2D_BLEND_C1_INV_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_INV_A_FSHIFT 12
+#define G2D_BLEND_C1_INV_A_FMASK 0x1
+#define G2D_BLEND_C1_INV_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_INV_B_FSHIFT 13
+#define G2D_BLEND_C1_INV_B_FMASK 0x1
+#define G2D_BLEND_C1_INV_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_INV_C_FSHIFT 14
+#define G2D_BLEND_C1_INV_C_FMASK 0x1
+#define G2D_BLEND_C1_INV_D_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_INV_D_FSHIFT 15
+#define G2D_BLEND_C1_INV_D_FMASK 0x1
+#define G2D_BLEND_C1_SRC_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_SRC_A_FSHIFT 16
+#define G2D_BLEND_C1_SRC_A_FMASK 0x7
+#define G2D_BLEND_C1_SRC_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_SRC_B_FSHIFT 19
+#define G2D_BLEND_C1_SRC_B_FMASK 0x7
+#define G2D_BLEND_C1_SRC_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_SRC_C_FSHIFT 22
+#define G2D_BLEND_C1_SRC_C_FMASK 0x7
+#define G2D_BLEND_C1_SRC_D_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_SRC_D_FSHIFT 25
+#define G2D_BLEND_C1_SRC_D_FMASK 0x7
+#define G2D_BLEND_C1_CONST_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_CONST_A_FSHIFT 28
+#define G2D_BLEND_C1_CONST_A_FMASK 0x1
+#define G2D_BLEND_C1_CONST_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_CONST_B_FSHIFT 29
+#define G2D_BLEND_C1_CONST_B_FMASK 0x1
+#define G2D_BLEND_C1_CONST_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_CONST_C_FSHIFT 30
+#define G2D_BLEND_C1_CONST_C_FMASK 0x1
+#define G2D_BLEND_C1_CONST_D_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_CONST_D_FSHIFT 31
+#define G2D_BLEND_C1_CONST_D_FMASK 0x1
+#define G2D_BLEND_C2_OPERATION_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_OPERATION_FSHIFT 0
+#define G2D_BLEND_C2_OPERATION_FMASK 0x3
+#define G2D_BLEND_C2_DST_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_DST_A_FSHIFT 2
+#define G2D_BLEND_C2_DST_A_FMASK 0x3
+#define G2D_BLEND_C2_DST_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_DST_B_FSHIFT 4
+#define G2D_BLEND_C2_DST_B_FMASK 0x3
+#define G2D_BLEND_C2_DST_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_DST_C_FSHIFT 6
+#define G2D_BLEND_C2_DST_C_FMASK 0x3
+#define G2D_BLEND_C2_AR_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_AR_A_FSHIFT 8
+#define G2D_BLEND_C2_AR_A_FMASK 0x1
+#define G2D_BLEND_C2_AR_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_AR_B_FSHIFT 9
+#define G2D_BLEND_C2_AR_B_FMASK 0x1
+#define G2D_BLEND_C2_AR_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_AR_C_FSHIFT 10
+#define G2D_BLEND_C2_AR_C_FMASK 0x1
+#define G2D_BLEND_C2_AR_D_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_AR_D_FSHIFT 11
+#define G2D_BLEND_C2_AR_D_FMASK 0x1
+#define G2D_BLEND_C2_INV_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_INV_A_FSHIFT 12
+#define G2D_BLEND_C2_INV_A_FMASK 0x1
+#define G2D_BLEND_C2_INV_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_INV_B_FSHIFT 13
+#define G2D_BLEND_C2_INV_B_FMASK 0x1
+#define G2D_BLEND_C2_INV_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_INV_C_FSHIFT 14
+#define G2D_BLEND_C2_INV_C_FMASK 0x1
+#define G2D_BLEND_C2_INV_D_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_INV_D_FSHIFT 15
+#define G2D_BLEND_C2_INV_D_FMASK 0x1
+#define G2D_BLEND_C2_SRC_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_SRC_A_FSHIFT 16
+#define G2D_BLEND_C2_SRC_A_FMASK 0x7
+#define G2D_BLEND_C2_SRC_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_SRC_B_FSHIFT 19
+#define G2D_BLEND_C2_SRC_B_FMASK 0x7
+#define G2D_BLEND_C2_SRC_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_SRC_C_FSHIFT 22
+#define G2D_BLEND_C2_SRC_C_FMASK 0x7
+#define G2D_BLEND_C2_SRC_D_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_SRC_D_FSHIFT 25
+#define G2D_BLEND_C2_SRC_D_FMASK 0x7
+#define G2D_BLEND_C2_CONST_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_CONST_A_FSHIFT 28
+#define G2D_BLEND_C2_CONST_A_FMASK 0x1
+#define G2D_BLEND_C2_CONST_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_CONST_B_FSHIFT 29
+#define G2D_BLEND_C2_CONST_B_FMASK 0x1
+#define G2D_BLEND_C2_CONST_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_CONST_C_FSHIFT 30
+#define G2D_BLEND_C2_CONST_C_FMASK 0x1
+#define G2D_BLEND_C2_CONST_D_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_CONST_D_FSHIFT 31
+#define G2D_BLEND_C2_CONST_D_FMASK 0x1
+#define G2D_BLEND_C3_OPERATION_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_OPERATION_FSHIFT 0
+#define G2D_BLEND_C3_OPERATION_FMASK 0x3
+#define G2D_BLEND_C3_DST_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_DST_A_FSHIFT 2
+#define G2D_BLEND_C3_DST_A_FMASK 0x3
+#define G2D_BLEND_C3_DST_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_DST_B_FSHIFT 4
+#define G2D_BLEND_C3_DST_B_FMASK 0x3
+#define G2D_BLEND_C3_DST_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_DST_C_FSHIFT 6
+#define G2D_BLEND_C3_DST_C_FMASK 0x3
+#define G2D_BLEND_C3_AR_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_AR_A_FSHIFT 8
+#define G2D_BLEND_C3_AR_A_FMASK 0x1
+#define G2D_BLEND_C3_AR_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_AR_B_FSHIFT 9
+#define G2D_BLEND_C3_AR_B_FMASK 0x1
+#define G2D_BLEND_C3_AR_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_AR_C_FSHIFT 10
+#define G2D_BLEND_C3_AR_C_FMASK 0x1
+#define G2D_BLEND_C3_AR_D_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_AR_D_FSHIFT 11
+#define G2D_BLEND_C3_AR_D_FMASK 0x1
+#define G2D_BLEND_C3_INV_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_INV_A_FSHIFT 12
+#define G2D_BLEND_C3_INV_A_FMASK 0x1
+#define G2D_BLEND_C3_INV_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_INV_B_FSHIFT 13
+#define G2D_BLEND_C3_INV_B_FMASK 0x1
+#define G2D_BLEND_C3_INV_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_INV_C_FSHIFT 14
+#define G2D_BLEND_C3_INV_C_FMASK 0x1
+#define G2D_BLEND_C3_INV_D_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_INV_D_FSHIFT 15
+#define G2D_BLEND_C3_INV_D_FMASK 0x1
+#define G2D_BLEND_C3_SRC_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_SRC_A_FSHIFT 16
+#define G2D_BLEND_C3_SRC_A_FMASK 0x7
+#define G2D_BLEND_C3_SRC_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_SRC_B_FSHIFT 19
+#define G2D_BLEND_C3_SRC_B_FMASK 0x7
+#define G2D_BLEND_C3_SRC_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_SRC_C_FSHIFT 22
+#define G2D_BLEND_C3_SRC_C_FMASK 0x7
+#define G2D_BLEND_C3_SRC_D_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_SRC_D_FSHIFT 25
+#define G2D_BLEND_C3_SRC_D_FMASK 0x7
+#define G2D_BLEND_C3_CONST_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_CONST_A_FSHIFT 28
+#define G2D_BLEND_C3_CONST_A_FMASK 0x1
+#define G2D_BLEND_C3_CONST_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_CONST_B_FSHIFT 29
+#define G2D_BLEND_C3_CONST_B_FMASK 0x1
+#define G2D_BLEND_C3_CONST_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_CONST_C_FSHIFT 30
+#define G2D_BLEND_C3_CONST_C_FMASK 0x1
+#define G2D_BLEND_C3_CONST_D_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_CONST_D_FSHIFT 31
+#define G2D_BLEND_C3_CONST_D_FMASK 0x1
+#define G2D_BLEND_C4_OPERATION_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_OPERATION_FSHIFT 0
+#define G2D_BLEND_C4_OPERATION_FMASK 0x3
+#define G2D_BLEND_C4_DST_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_DST_A_FSHIFT 2
+#define G2D_BLEND_C4_DST_A_FMASK 0x3
+#define G2D_BLEND_C4_DST_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_DST_B_FSHIFT 4
+#define G2D_BLEND_C4_DST_B_FMASK 0x3
+#define G2D_BLEND_C4_DST_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_DST_C_FSHIFT 6
+#define G2D_BLEND_C4_DST_C_FMASK 0x3
+#define G2D_BLEND_C4_AR_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_AR_A_FSHIFT 8
+#define G2D_BLEND_C4_AR_A_FMASK 0x1
+#define G2D_BLEND_C4_AR_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_AR_B_FSHIFT 9
+#define G2D_BLEND_C4_AR_B_FMASK 0x1
+#define G2D_BLEND_C4_AR_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_AR_C_FSHIFT 10
+#define G2D_BLEND_C4_AR_C_FMASK 0x1
+#define G2D_BLEND_C4_AR_D_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_AR_D_FSHIFT 11
+#define G2D_BLEND_C4_AR_D_FMASK 0x1
+#define G2D_BLEND_C4_INV_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_INV_A_FSHIFT 12
+#define G2D_BLEND_C4_INV_A_FMASK 0x1
+#define G2D_BLEND_C4_INV_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_INV_B_FSHIFT 13
+#define G2D_BLEND_C4_INV_B_FMASK 0x1
+#define G2D_BLEND_C4_INV_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_INV_C_FSHIFT 14
+#define G2D_BLEND_C4_INV_C_FMASK 0x1
+#define G2D_BLEND_C4_INV_D_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_INV_D_FSHIFT 15
+#define G2D_BLEND_C4_INV_D_FMASK 0x1
+#define G2D_BLEND_C4_SRC_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_SRC_A_FSHIFT 16
+#define G2D_BLEND_C4_SRC_A_FMASK 0x7
+#define G2D_BLEND_C4_SRC_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_SRC_B_FSHIFT 19
+#define G2D_BLEND_C4_SRC_B_FMASK 0x7
+#define G2D_BLEND_C4_SRC_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_SRC_C_FSHIFT 22
+#define G2D_BLEND_C4_SRC_C_FMASK 0x7
+#define G2D_BLEND_C4_SRC_D_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_SRC_D_FSHIFT 25
+#define G2D_BLEND_C4_SRC_D_FMASK 0x7
+#define G2D_BLEND_C4_CONST_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_CONST_A_FSHIFT 28
+#define G2D_BLEND_C4_CONST_A_FMASK 0x1
+#define G2D_BLEND_C4_CONST_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_CONST_B_FSHIFT 29
+#define G2D_BLEND_C4_CONST_B_FMASK 0x1
+#define G2D_BLEND_C4_CONST_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_CONST_C_FSHIFT 30
+#define G2D_BLEND_C4_CONST_C_FMASK 0x1
+#define G2D_BLEND_C4_CONST_D_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_CONST_D_FSHIFT 31
+#define G2D_BLEND_C4_CONST_D_FMASK 0x1
+#define G2D_BLEND_C5_OPERATION_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_OPERATION_FSHIFT 0
+#define G2D_BLEND_C5_OPERATION_FMASK 0x3
+#define G2D_BLEND_C5_DST_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_DST_A_FSHIFT 2
+#define G2D_BLEND_C5_DST_A_FMASK 0x3
+#define G2D_BLEND_C5_DST_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_DST_B_FSHIFT 4
+#define G2D_BLEND_C5_DST_B_FMASK 0x3
+#define G2D_BLEND_C5_DST_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_DST_C_FSHIFT 6
+#define G2D_BLEND_C5_DST_C_FMASK 0x3
+#define G2D_BLEND_C5_AR_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_AR_A_FSHIFT 8
+#define G2D_BLEND_C5_AR_A_FMASK 0x1
+#define G2D_BLEND_C5_AR_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_AR_B_FSHIFT 9
+#define G2D_BLEND_C5_AR_B_FMASK 0x1
+#define G2D_BLEND_C5_AR_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_AR_C_FSHIFT 10
+#define G2D_BLEND_C5_AR_C_FMASK 0x1
+#define G2D_BLEND_C5_AR_D_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_AR_D_FSHIFT 11
+#define G2D_BLEND_C5_AR_D_FMASK 0x1
+#define G2D_BLEND_C5_INV_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_INV_A_FSHIFT 12
+#define G2D_BLEND_C5_INV_A_FMASK 0x1
+#define G2D_BLEND_C5_INV_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_INV_B_FSHIFT 13
+#define G2D_BLEND_C5_INV_B_FMASK 0x1
+#define G2D_BLEND_C5_INV_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_INV_C_FSHIFT 14
+#define G2D_BLEND_C5_INV_C_FMASK 0x1
+#define G2D_BLEND_C5_INV_D_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_INV_D_FSHIFT 15
+#define G2D_BLEND_C5_INV_D_FMASK 0x1
+#define G2D_BLEND_C5_SRC_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_SRC_A_FSHIFT 16
+#define G2D_BLEND_C5_SRC_A_FMASK 0x7
+#define G2D_BLEND_C5_SRC_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_SRC_B_FSHIFT 19
+#define G2D_BLEND_C5_SRC_B_FMASK 0x7
+#define G2D_BLEND_C5_SRC_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_SRC_C_FSHIFT 22
+#define G2D_BLEND_C5_SRC_C_FMASK 0x7
+#define G2D_BLEND_C5_SRC_D_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_SRC_D_FSHIFT 25
+#define G2D_BLEND_C5_SRC_D_FMASK 0x7
+#define G2D_BLEND_C5_CONST_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_CONST_A_FSHIFT 28
+#define G2D_BLEND_C5_CONST_A_FMASK 0x1
+#define G2D_BLEND_C5_CONST_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_CONST_B_FSHIFT 29
+#define G2D_BLEND_C5_CONST_B_FMASK 0x1
+#define G2D_BLEND_C5_CONST_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_CONST_C_FSHIFT 30
+#define G2D_BLEND_C5_CONST_C_FMASK 0x1
+#define G2D_BLEND_C5_CONST_D_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_CONST_D_FSHIFT 31
+#define G2D_BLEND_C5_CONST_D_FMASK 0x1
+#define G2D_BLEND_C6_OPERATION_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_OPERATION_FSHIFT 0
+#define G2D_BLEND_C6_OPERATION_FMASK 0x3
+#define G2D_BLEND_C6_DST_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_DST_A_FSHIFT 2
+#define G2D_BLEND_C6_DST_A_FMASK 0x3
+#define G2D_BLEND_C6_DST_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_DST_B_FSHIFT 4
+#define G2D_BLEND_C6_DST_B_FMASK 0x3
+#define G2D_BLEND_C6_DST_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_DST_C_FSHIFT 6
+#define G2D_BLEND_C6_DST_C_FMASK 0x3
+#define G2D_BLEND_C6_AR_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_AR_A_FSHIFT 8
+#define G2D_BLEND_C6_AR_A_FMASK 0x1
+#define G2D_BLEND_C6_AR_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_AR_B_FSHIFT 9
+#define G2D_BLEND_C6_AR_B_FMASK 0x1
+#define G2D_BLEND_C6_AR_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_AR_C_FSHIFT 10
+#define G2D_BLEND_C6_AR_C_FMASK 0x1
+#define G2D_BLEND_C6_AR_D_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_AR_D_FSHIFT 11
+#define G2D_BLEND_C6_AR_D_FMASK 0x1
+#define G2D_BLEND_C6_INV_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_INV_A_FSHIFT 12
+#define G2D_BLEND_C6_INV_A_FMASK 0x1
+#define G2D_BLEND_C6_INV_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_INV_B_FSHIFT 13
+#define G2D_BLEND_C6_INV_B_FMASK 0x1
+#define G2D_BLEND_C6_INV_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_INV_C_FSHIFT 14
+#define G2D_BLEND_C6_INV_C_FMASK 0x1
+#define G2D_BLEND_C6_INV_D_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_INV_D_FSHIFT 15
+#define G2D_BLEND_C6_INV_D_FMASK 0x1
+#define G2D_BLEND_C6_SRC_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_SRC_A_FSHIFT 16
+#define G2D_BLEND_C6_SRC_A_FMASK 0x7
+#define G2D_BLEND_C6_SRC_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_SRC_B_FSHIFT 19
+#define G2D_BLEND_C6_SRC_B_FMASK 0x7
+#define G2D_BLEND_C6_SRC_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_SRC_C_FSHIFT 22
+#define G2D_BLEND_C6_SRC_C_FMASK 0x7
+#define G2D_BLEND_C6_SRC_D_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_SRC_D_FSHIFT 25
+#define G2D_BLEND_C6_SRC_D_FMASK 0x7
+#define G2D_BLEND_C6_CONST_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_CONST_A_FSHIFT 28
+#define G2D_BLEND_C6_CONST_A_FMASK 0x1
+#define G2D_BLEND_C6_CONST_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_CONST_B_FSHIFT 29
+#define G2D_BLEND_C6_CONST_B_FMASK 0x1
+#define G2D_BLEND_C6_CONST_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_CONST_C_FSHIFT 30
+#define G2D_BLEND_C6_CONST_C_FMASK 0x1
+#define G2D_BLEND_C6_CONST_D_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_CONST_D_FSHIFT 31
+#define G2D_BLEND_C6_CONST_D_FMASK 0x1
+#define G2D_BLEND_C7_OPERATION_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_OPERATION_FSHIFT 0
+#define G2D_BLEND_C7_OPERATION_FMASK 0x3
+#define G2D_BLEND_C7_DST_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_DST_A_FSHIFT 2
+#define G2D_BLEND_C7_DST_A_FMASK 0x3
+#define G2D_BLEND_C7_DST_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_DST_B_FSHIFT 4
+#define G2D_BLEND_C7_DST_B_FMASK 0x3
+#define G2D_BLEND_C7_DST_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_DST_C_FSHIFT 6
+#define G2D_BLEND_C7_DST_C_FMASK 0x3
+#define G2D_BLEND_C7_AR_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_AR_A_FSHIFT 8
+#define G2D_BLEND_C7_AR_A_FMASK 0x1
+#define G2D_BLEND_C7_AR_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_AR_B_FSHIFT 9
+#define G2D_BLEND_C7_AR_B_FMASK 0x1
+#define G2D_BLEND_C7_AR_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_AR_C_FSHIFT 10
+#define G2D_BLEND_C7_AR_C_FMASK 0x1
+#define G2D_BLEND_C7_AR_D_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_AR_D_FSHIFT 11
+#define G2D_BLEND_C7_AR_D_FMASK 0x1
+#define G2D_BLEND_C7_INV_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_INV_A_FSHIFT 12
+#define G2D_BLEND_C7_INV_A_FMASK 0x1
+#define G2D_BLEND_C7_INV_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_INV_B_FSHIFT 13
+#define G2D_BLEND_C7_INV_B_FMASK 0x1
+#define G2D_BLEND_C7_INV_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_INV_C_FSHIFT 14
+#define G2D_BLEND_C7_INV_C_FMASK 0x1
+#define G2D_BLEND_C7_INV_D_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_INV_D_FSHIFT 15
+#define G2D_BLEND_C7_INV_D_FMASK 0x1
+#define G2D_BLEND_C7_SRC_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_SRC_A_FSHIFT 16
+#define G2D_BLEND_C7_SRC_A_FMASK 0x7
+#define G2D_BLEND_C7_SRC_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_SRC_B_FSHIFT 19
+#define G2D_BLEND_C7_SRC_B_FMASK 0x7
+#define G2D_BLEND_C7_SRC_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_SRC_C_FSHIFT 22
+#define G2D_BLEND_C7_SRC_C_FMASK 0x7
+#define G2D_BLEND_C7_SRC_D_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_SRC_D_FSHIFT 25
+#define G2D_BLEND_C7_SRC_D_FMASK 0x7
+#define G2D_BLEND_C7_CONST_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_CONST_A_FSHIFT 28
+#define G2D_BLEND_C7_CONST_A_FMASK 0x1
+#define G2D_BLEND_C7_CONST_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_CONST_B_FSHIFT 29
+#define G2D_BLEND_C7_CONST_B_FMASK 0x1
+#define G2D_BLEND_C7_CONST_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_CONST_C_FSHIFT 30
+#define G2D_BLEND_C7_CONST_C_FMASK 0x1
+#define G2D_BLEND_C7_CONST_D_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_CONST_D_FSHIFT 31
+#define G2D_BLEND_C7_CONST_D_FMASK 0x1
+#define G2D_CFG0_STRIDE_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_STRIDE_FSHIFT 0
+#define G2D_CFG0_STRIDE_FMASK 0xfff
+#define G2D_CFG0_FORMAT_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_FORMAT_FSHIFT 12
+#define G2D_CFG0_FORMAT_FMASK 0xf
+#define G2D_CFG0_TILED_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_TILED_FSHIFT 16
+#define G2D_CFG0_TILED_FMASK 0x1
+#define G2D_CFG0_SRGB_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SRGB_FSHIFT 17
+#define G2D_CFG0_SRGB_FMASK 0x1
+#define G2D_CFG0_SWAPWORDS_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPWORDS_FSHIFT 18
+#define G2D_CFG0_SWAPWORDS_FMASK 0x1
+#define G2D_CFG0_SWAPBYTES_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPBYTES_FSHIFT 19
+#define G2D_CFG0_SWAPBYTES_FMASK 0x1
+#define G2D_CFG0_SWAPALL_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPALL_FSHIFT 20
+#define G2D_CFG0_SWAPALL_FMASK 0x1
+#define G2D_CFG0_SWAPRB_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPRB_FSHIFT 21
+#define G2D_CFG0_SWAPRB_FMASK 0x1
+#define G2D_CFG0_SWAPBITS_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPBITS_FSHIFT 22
+#define G2D_CFG0_SWAPBITS_FMASK 0x1
+#define G2D_CFG0_STRIDESIGN_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_STRIDESIGN_FSHIFT 23
+#define G2D_CFG0_STRIDESIGN_FMASK 0x1
+#define G2D_CFG1_STRIDE_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_STRIDE_FSHIFT 0
+#define G2D_CFG1_STRIDE_FMASK 0xfff
+#define G2D_CFG1_FORMAT_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_FORMAT_FSHIFT 12
+#define G2D_CFG1_FORMAT_FMASK 0xf
+#define G2D_CFG1_TILED_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_TILED_FSHIFT 16
+#define G2D_CFG1_TILED_FMASK 0x1
+#define G2D_CFG1_SRGB_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SRGB_FSHIFT 17
+#define G2D_CFG1_SRGB_FMASK 0x1
+#define G2D_CFG1_SWAPWORDS_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPWORDS_FSHIFT 18
+#define G2D_CFG1_SWAPWORDS_FMASK 0x1
+#define G2D_CFG1_SWAPBYTES_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPBYTES_FSHIFT 19
+#define G2D_CFG1_SWAPBYTES_FMASK 0x1
+#define G2D_CFG1_SWAPALL_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPALL_FSHIFT 20
+#define G2D_CFG1_SWAPALL_FMASK 0x1
+#define G2D_CFG1_SWAPRB_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPRB_FSHIFT 21
+#define G2D_CFG1_SWAPRB_FMASK 0x1
+#define G2D_CFG1_SWAPBITS_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPBITS_FSHIFT 22
+#define G2D_CFG1_SWAPBITS_FMASK 0x1
+#define G2D_CFG1_STRIDESIGN_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_STRIDESIGN_FSHIFT 23
+#define G2D_CFG1_STRIDESIGN_FMASK 0x1
+#define G2D_CFG2_STRIDE_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_STRIDE_FSHIFT 0
+#define G2D_CFG2_STRIDE_FMASK 0xfff
+#define G2D_CFG2_FORMAT_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_FORMAT_FSHIFT 12
+#define G2D_CFG2_FORMAT_FMASK 0xf
+#define G2D_CFG2_TILED_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_TILED_FSHIFT 16
+#define G2D_CFG2_TILED_FMASK 0x1
+#define G2D_CFG2_SRGB_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SRGB_FSHIFT 17
+#define G2D_CFG2_SRGB_FMASK 0x1
+#define G2D_CFG2_SWAPWORDS_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPWORDS_FSHIFT 18
+#define G2D_CFG2_SWAPWORDS_FMASK 0x1
+#define G2D_CFG2_SWAPBYTES_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPBYTES_FSHIFT 19
+#define G2D_CFG2_SWAPBYTES_FMASK 0x1
+#define G2D_CFG2_SWAPALL_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPALL_FSHIFT 20
+#define G2D_CFG2_SWAPALL_FMASK 0x1
+#define G2D_CFG2_SWAPRB_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPRB_FSHIFT 21
+#define G2D_CFG2_SWAPRB_FMASK 0x1
+#define G2D_CFG2_SWAPBITS_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPBITS_FSHIFT 22
+#define G2D_CFG2_SWAPBITS_FMASK 0x1
+#define G2D_CFG2_STRIDESIGN_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_STRIDESIGN_FSHIFT 23
+#define G2D_CFG2_STRIDESIGN_FMASK 0x1
+#define G2D_CFG3_STRIDE_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_STRIDE_FSHIFT 0
+#define G2D_CFG3_STRIDE_FMASK 0xfff
+#define G2D_CFG3_FORMAT_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_FORMAT_FSHIFT 12
+#define G2D_CFG3_FORMAT_FMASK 0xf
+#define G2D_CFG3_TILED_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_TILED_FSHIFT 16
+#define G2D_CFG3_TILED_FMASK 0x1
+#define G2D_CFG3_SRGB_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SRGB_FSHIFT 17
+#define G2D_CFG3_SRGB_FMASK 0x1
+#define G2D_CFG3_SWAPWORDS_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPWORDS_FSHIFT 18
+#define G2D_CFG3_SWAPWORDS_FMASK 0x1
+#define G2D_CFG3_SWAPBYTES_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPBYTES_FSHIFT 19
+#define G2D_CFG3_SWAPBYTES_FMASK 0x1
+#define G2D_CFG3_SWAPALL_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPALL_FSHIFT 20
+#define G2D_CFG3_SWAPALL_FMASK 0x1
+#define G2D_CFG3_SWAPRB_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPRB_FSHIFT 21
+#define G2D_CFG3_SWAPRB_FMASK 0x1
+#define G2D_CFG3_SWAPBITS_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPBITS_FSHIFT 22
+#define G2D_CFG3_SWAPBITS_FMASK 0x1
+#define G2D_CFG3_STRIDESIGN_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_STRIDESIGN_FSHIFT 23
+#define G2D_CFG3_STRIDESIGN_FMASK 0x1
+#define G2D_COLOR_ARGB_FADDR ADDR_G2D_COLOR
+#define G2D_COLOR_ARGB_FSHIFT 0
+#define G2D_COLOR_ARGB_FMASK 0xffffffff
+#define G2D_CONFIG_DST_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_DST_FSHIFT 0
+#define G2D_CONFIG_DST_FMASK 0x1
+#define G2D_CONFIG_SRC1_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_SRC1_FSHIFT 1
+#define G2D_CONFIG_SRC1_FMASK 0x1
+#define G2D_CONFIG_SRC2_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_SRC2_FSHIFT 2
+#define G2D_CONFIG_SRC2_FMASK 0x1
+#define G2D_CONFIG_SRC3_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_SRC3_FSHIFT 3
+#define G2D_CONFIG_SRC3_FMASK 0x1
+#define G2D_CONFIG_SRCCK_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_SRCCK_FSHIFT 4
+#define G2D_CONFIG_SRCCK_FMASK 0x1
+#define G2D_CONFIG_DSTCK_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_DSTCK_FSHIFT 5
+#define G2D_CONFIG_DSTCK_FMASK 0x1
+#define G2D_CONFIG_ROTATE_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_ROTATE_FSHIFT 6
+#define G2D_CONFIG_ROTATE_FMASK 0x3
+#define G2D_CONFIG_OBS_GAMMA_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_OBS_GAMMA_FSHIFT 8
+#define G2D_CONFIG_OBS_GAMMA_FMASK 0x1
+#define G2D_CONFIG_IGNORECKALPHA_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_IGNORECKALPHA_FSHIFT 9
+#define G2D_CONFIG_IGNORECKALPHA_FMASK 0x1
+#define G2D_CONFIG_DITHER_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_DITHER_FSHIFT 10
+#define G2D_CONFIG_DITHER_FMASK 0x1
+#define G2D_CONFIG_WRITESRGB_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_WRITESRGB_FSHIFT 11
+#define G2D_CONFIG_WRITESRGB_FMASK 0x1
+#define G2D_CONFIG_ARGBMASK_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_ARGBMASK_FSHIFT 12
+#define G2D_CONFIG_ARGBMASK_FMASK 0xf
+#define G2D_CONFIG_ALPHATEX_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_ALPHATEX_FSHIFT 16
+#define G2D_CONFIG_ALPHATEX_FMASK 0x1
+#define G2D_CONFIG_PALMLINES_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_PALMLINES_FSHIFT 17
+#define G2D_CONFIG_PALMLINES_FMASK 0x1
+#define G2D_CONFIG_NOLASTPIXEL_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_NOLASTPIXEL_FSHIFT 18
+#define G2D_CONFIG_NOLASTPIXEL_FMASK 0x1
+#define G2D_CONFIG_NOPROTECT_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_NOPROTECT_FSHIFT 19
+#define G2D_CONFIG_NOPROTECT_FMASK 0x1
+#define G2D_CONST0_ARGB_FADDR ADDR_G2D_CONST0
+#define G2D_CONST0_ARGB_FSHIFT 0
+#define G2D_CONST0_ARGB_FMASK 0xffffffff
+#define G2D_CONST1_ARGB_FADDR ADDR_G2D_CONST1
+#define G2D_CONST1_ARGB_FSHIFT 0
+#define G2D_CONST1_ARGB_FMASK 0xffffffff
+#define G2D_CONST2_ARGB_FADDR ADDR_G2D_CONST2
+#define G2D_CONST2_ARGB_FSHIFT 0
+#define G2D_CONST2_ARGB_FMASK 0xffffffff
+#define G2D_CONST3_ARGB_FADDR ADDR_G2D_CONST3
+#define G2D_CONST3_ARGB_FSHIFT 0
+#define G2D_CONST3_ARGB_FMASK 0xffffffff
+#define G2D_CONST4_ARGB_FADDR ADDR_G2D_CONST4
+#define G2D_CONST4_ARGB_FSHIFT 0
+#define G2D_CONST4_ARGB_FMASK 0xffffffff
+#define G2D_CONST5_ARGB_FADDR ADDR_G2D_CONST5
+#define G2D_CONST5_ARGB_FSHIFT 0
+#define G2D_CONST5_ARGB_FMASK 0xffffffff
+#define G2D_CONST6_ARGB_FADDR ADDR_G2D_CONST6
+#define G2D_CONST6_ARGB_FSHIFT 0
+#define G2D_CONST6_ARGB_FMASK 0xffffffff
+#define G2D_CONST7_ARGB_FADDR ADDR_G2D_CONST7
+#define G2D_CONST7_ARGB_FSHIFT 0
+#define G2D_CONST7_ARGB_FMASK 0xffffffff
+#define G2D_FOREGROUND_COLOR_FADDR ADDR_G2D_FOREGROUND
+#define G2D_FOREGROUND_COLOR_FSHIFT 0
+#define G2D_FOREGROUND_COLOR_FMASK 0xffffffff
+#define G2D_GRADIENT_INSTRUCTIONS_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_INSTRUCTIONS_FSHIFT 0
+#define G2D_GRADIENT_INSTRUCTIONS_FMASK 0x7
+#define G2D_GRADIENT_INSTRUCTIONS2_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_INSTRUCTIONS2_FSHIFT 3
+#define G2D_GRADIENT_INSTRUCTIONS2_FMASK 0x7
+#define G2D_GRADIENT_ENABLE_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_ENABLE_FSHIFT 6
+#define G2D_GRADIENT_ENABLE_FMASK 0x1
+#define G2D_GRADIENT_ENABLE2_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_ENABLE2_FSHIFT 7
+#define G2D_GRADIENT_ENABLE2_FMASK 0x1
+#define G2D_GRADIENT_SEL_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_SEL_FSHIFT 8
+#define G2D_GRADIENT_SEL_FMASK 0x1
+#define G2D_IDLE_IRQ_FADDR ADDR_G2D_IDLE
+#define G2D_IDLE_IRQ_FSHIFT 0
+#define G2D_IDLE_IRQ_FMASK 0x1
+#define G2D_IDLE_BCFLUSH_FADDR ADDR_G2D_IDLE
+#define G2D_IDLE_BCFLUSH_FSHIFT 1
+#define G2D_IDLE_BCFLUSH_FMASK 0x1
+#define G2D_IDLE_V3_FADDR ADDR_G2D_IDLE
+#define G2D_IDLE_V3_FSHIFT 2
+#define G2D_IDLE_V3_FMASK 0x1
+#define G2D_INPUT_COLOR_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_COLOR_FSHIFT 0
+#define G2D_INPUT_COLOR_FMASK 0x1
+#define G2D_INPUT_SCOORD1_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_SCOORD1_FSHIFT 1
+#define G2D_INPUT_SCOORD1_FMASK 0x1
+#define G2D_INPUT_SCOORD2_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_SCOORD2_FSHIFT 2
+#define G2D_INPUT_SCOORD2_FMASK 0x1
+#define G2D_INPUT_COPYCOORD_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_COPYCOORD_FSHIFT 3
+#define G2D_INPUT_COPYCOORD_FMASK 0x1
+#define G2D_INPUT_VGMODE_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_VGMODE_FSHIFT 4
+#define G2D_INPUT_VGMODE_FMASK 0x1
+#define G2D_INPUT_LINEMODE_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_LINEMODE_FSHIFT 5
+#define G2D_INPUT_LINEMODE_FMASK 0x1
+#define G2D_MASK_YMASK_FADDR ADDR_G2D_MASK
+#define G2D_MASK_YMASK_FSHIFT 0
+#define G2D_MASK_YMASK_FMASK 0xfff
+#define G2D_MASK_XMASK_FADDR ADDR_G2D_MASK
+#define G2D_MASK_XMASK_FSHIFT 12
+#define G2D_MASK_XMASK_FMASK 0xfff
+#define G2D_ROP_ROP_FADDR ADDR_G2D_ROP
+#define G2D_ROP_ROP_FSHIFT 0
+#define G2D_ROP_ROP_FMASK 0xffff
+#define G2D_SCISSORX_LEFT_FADDR ADDR_G2D_SCISSORX
+#define G2D_SCISSORX_LEFT_FSHIFT 0
+#define G2D_SCISSORX_LEFT_FMASK 0x7ff
+#define G2D_SCISSORX_RIGHT_FADDR ADDR_G2D_SCISSORX
+#define G2D_SCISSORX_RIGHT_FSHIFT 11
+#define G2D_SCISSORX_RIGHT_FMASK 0x7ff
+#define G2D_SCISSORY_TOP_FADDR ADDR_G2D_SCISSORY
+#define G2D_SCISSORY_TOP_FSHIFT 0
+#define G2D_SCISSORY_TOP_FMASK 0x7ff
+#define G2D_SCISSORY_BOTTOM_FADDR ADDR_G2D_SCISSORY
+#define G2D_SCISSORY_BOTTOM_FSHIFT 11
+#define G2D_SCISSORY_BOTTOM_FMASK 0x7ff
+#define G2D_SXY_Y_FADDR ADDR_G2D_SXY
+#define G2D_SXY_Y_FSHIFT 0
+#define G2D_SXY_Y_FMASK 0x7ff
+#define G2D_SXY_PAD_FADDR ADDR_G2D_SXY
+#define G2D_SXY_PAD_FSHIFT 11
+#define G2D_SXY_PAD_FMASK 0x1f
+#define G2D_SXY_X_FADDR ADDR_G2D_SXY
+#define G2D_SXY_X_FSHIFT 16
+#define G2D_SXY_X_FMASK 0x7ff
+#define G2D_SXY2_Y_FADDR ADDR_G2D_SXY2
+#define G2D_SXY2_Y_FSHIFT 0
+#define G2D_SXY2_Y_FMASK 0x7ff
+#define G2D_SXY2_PAD_FADDR ADDR_G2D_SXY2
+#define G2D_SXY2_PAD_FSHIFT 11
+#define G2D_SXY2_PAD_FMASK 0x1f
+#define G2D_SXY2_X_FADDR ADDR_G2D_SXY2
+#define G2D_SXY2_X_FSHIFT 16
+#define G2D_SXY2_X_FMASK 0x7ff
+#define G2D_VGSPAN_WIDTH_FADDR ADDR_G2D_VGSPAN
+#define G2D_VGSPAN_WIDTH_FSHIFT 0
+#define G2D_VGSPAN_WIDTH_FMASK 0xfff
+#define G2D_VGSPAN_PAD_FADDR ADDR_G2D_VGSPAN
+#define G2D_VGSPAN_PAD_FSHIFT 12
+#define G2D_VGSPAN_PAD_FMASK 0xf
+#define G2D_VGSPAN_COVERAGE_FADDR ADDR_G2D_VGSPAN
+#define G2D_VGSPAN_COVERAGE_FSHIFT 16
+#define G2D_VGSPAN_COVERAGE_FMASK 0xf
+#define G2D_WIDTHHEIGHT_HEIGHT_FADDR ADDR_G2D_WIDTHHEIGHT
+#define G2D_WIDTHHEIGHT_HEIGHT_FSHIFT 0
+#define G2D_WIDTHHEIGHT_HEIGHT_FMASK 0xfff
+#define G2D_WIDTHHEIGHT_PAD_FADDR ADDR_G2D_WIDTHHEIGHT
+#define G2D_WIDTHHEIGHT_PAD_FSHIFT 12
+#define G2D_WIDTHHEIGHT_PAD_FMASK 0xf
+#define G2D_WIDTHHEIGHT_WIDTH_FADDR ADDR_G2D_WIDTHHEIGHT
+#define G2D_WIDTHHEIGHT_WIDTH_FSHIFT 16
+#define G2D_WIDTHHEIGHT_WIDTH_FMASK 0xfff
+#define G2D_XY_Y_FADDR ADDR_G2D_XY
+#define G2D_XY_Y_FSHIFT 0
+#define G2D_XY_Y_FMASK 0xfff
+#define G2D_XY_PAD_FADDR ADDR_G2D_XY
+#define G2D_XY_PAD_FSHIFT 12
+#define G2D_XY_PAD_FMASK 0xf
+#define G2D_XY_X_FADDR ADDR_G2D_XY
+#define G2D_XY_X_FSHIFT 16
+#define G2D_XY_X_FMASK 0xfff
+#define GRADW_BORDERCOLOR_COLOR_FADDR ADDR_GRADW_BORDERCOLOR
+#define GRADW_BORDERCOLOR_COLOR_FSHIFT 0
+#define GRADW_BORDERCOLOR_COLOR_FMASK 0xffffffff
+#define GRADW_CONST0_VALUE_FADDR ADDR_GRADW_CONST0
+#define GRADW_CONST0_VALUE_FSHIFT 0
+#define GRADW_CONST0_VALUE_FMASK 0xffff
+#define GRADW_CONST1_VALUE_FADDR ADDR_GRADW_CONST1
+#define GRADW_CONST1_VALUE_FSHIFT 0
+#define GRADW_CONST1_VALUE_FMASK 0xffff
+#define GRADW_CONST2_VALUE_FADDR ADDR_GRADW_CONST2
+#define GRADW_CONST2_VALUE_FSHIFT 0
+#define GRADW_CONST2_VALUE_FMASK 0xffff
+#define GRADW_CONST3_VALUE_FADDR ADDR_GRADW_CONST3
+#define GRADW_CONST3_VALUE_FSHIFT 0
+#define GRADW_CONST3_VALUE_FMASK 0xffff
+#define GRADW_CONST4_VALUE_FADDR ADDR_GRADW_CONST4
+#define GRADW_CONST4_VALUE_FSHIFT 0
+#define GRADW_CONST4_VALUE_FMASK 0xffff
+#define GRADW_CONST5_VALUE_FADDR ADDR_GRADW_CONST5
+#define GRADW_CONST5_VALUE_FSHIFT 0
+#define GRADW_CONST5_VALUE_FMASK 0xffff
+#define GRADW_CONST6_VALUE_FADDR ADDR_GRADW_CONST6
+#define GRADW_CONST6_VALUE_FSHIFT 0
+#define GRADW_CONST6_VALUE_FMASK 0xffff
+#define GRADW_CONST7_VALUE_FADDR ADDR_GRADW_CONST7
+#define GRADW_CONST7_VALUE_FSHIFT 0
+#define GRADW_CONST7_VALUE_FMASK 0xffff
+#define GRADW_CONST8_VALUE_FADDR ADDR_GRADW_CONST8
+#define GRADW_CONST8_VALUE_FSHIFT 0
+#define GRADW_CONST8_VALUE_FMASK 0xffff
+#define GRADW_CONST9_VALUE_FADDR ADDR_GRADW_CONST9
+#define GRADW_CONST9_VALUE_FSHIFT 0
+#define GRADW_CONST9_VALUE_FMASK 0xffff
+#define GRADW_CONSTA_VALUE_FADDR ADDR_GRADW_CONSTA
+#define GRADW_CONSTA_VALUE_FSHIFT 0
+#define GRADW_CONSTA_VALUE_FMASK 0xffff
+#define GRADW_CONSTB_VALUE_FADDR ADDR_GRADW_CONSTB
+#define GRADW_CONSTB_VALUE_FSHIFT 0
+#define GRADW_CONSTB_VALUE_FMASK 0xffff
+#define GRADW_INST0_SRC_E_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_E_FSHIFT 0
+#define GRADW_INST0_SRC_E_FMASK 0x1f
+#define GRADW_INST0_SRC_D_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_D_FSHIFT 5
+#define GRADW_INST0_SRC_D_FMASK 0x1f
+#define GRADW_INST0_SRC_C_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_C_FSHIFT 10
+#define GRADW_INST0_SRC_C_FMASK 0x1f
+#define GRADW_INST0_SRC_B_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_B_FSHIFT 15
+#define GRADW_INST0_SRC_B_FMASK 0x1f
+#define GRADW_INST0_SRC_A_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_A_FSHIFT 20
+#define GRADW_INST0_SRC_A_FMASK 0x1f
+#define GRADW_INST0_DST_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_DST_FSHIFT 25
+#define GRADW_INST0_DST_FMASK 0xf
+#define GRADW_INST0_OPCODE_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_OPCODE_FSHIFT 29
+#define GRADW_INST0_OPCODE_FMASK 0x3
+#define GRADW_INST1_SRC_E_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_E_FSHIFT 0
+#define GRADW_INST1_SRC_E_FMASK 0x1f
+#define GRADW_INST1_SRC_D_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_D_FSHIFT 5
+#define GRADW_INST1_SRC_D_FMASK 0x1f
+#define GRADW_INST1_SRC_C_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_C_FSHIFT 10
+#define GRADW_INST1_SRC_C_FMASK 0x1f
+#define GRADW_INST1_SRC_B_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_B_FSHIFT 15
+#define GRADW_INST1_SRC_B_FMASK 0x1f
+#define GRADW_INST1_SRC_A_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_A_FSHIFT 20
+#define GRADW_INST1_SRC_A_FMASK 0x1f
+#define GRADW_INST1_DST_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_DST_FSHIFT 25
+#define GRADW_INST1_DST_FMASK 0xf
+#define GRADW_INST1_OPCODE_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_OPCODE_FSHIFT 29
+#define GRADW_INST1_OPCODE_FMASK 0x3
+#define GRADW_INST2_SRC_E_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_E_FSHIFT 0
+#define GRADW_INST2_SRC_E_FMASK 0x1f
+#define GRADW_INST2_SRC_D_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_D_FSHIFT 5
+#define GRADW_INST2_SRC_D_FMASK 0x1f
+#define GRADW_INST2_SRC_C_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_C_FSHIFT 10
+#define GRADW_INST2_SRC_C_FMASK 0x1f
+#define GRADW_INST2_SRC_B_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_B_FSHIFT 15
+#define GRADW_INST2_SRC_B_FMASK 0x1f
+#define GRADW_INST2_SRC_A_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_A_FSHIFT 20
+#define GRADW_INST2_SRC_A_FMASK 0x1f
+#define GRADW_INST2_DST_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_DST_FSHIFT 25
+#define GRADW_INST2_DST_FMASK 0xf
+#define GRADW_INST2_OPCODE_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_OPCODE_FSHIFT 29
+#define GRADW_INST2_OPCODE_FMASK 0x3
+#define GRADW_INST3_SRC_E_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_E_FSHIFT 0
+#define GRADW_INST3_SRC_E_FMASK 0x1f
+#define GRADW_INST3_SRC_D_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_D_FSHIFT 5
+#define GRADW_INST3_SRC_D_FMASK 0x1f
+#define GRADW_INST3_SRC_C_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_C_FSHIFT 10
+#define GRADW_INST3_SRC_C_FMASK 0x1f
+#define GRADW_INST3_SRC_B_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_B_FSHIFT 15
+#define GRADW_INST3_SRC_B_FMASK 0x1f
+#define GRADW_INST3_SRC_A_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_A_FSHIFT 20
+#define GRADW_INST3_SRC_A_FMASK 0x1f
+#define GRADW_INST3_DST_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_DST_FSHIFT 25
+#define GRADW_INST3_DST_FMASK 0xf
+#define GRADW_INST3_OPCODE_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_OPCODE_FSHIFT 29
+#define GRADW_INST3_OPCODE_FMASK 0x3
+#define GRADW_INST4_SRC_E_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_E_FSHIFT 0
+#define GRADW_INST4_SRC_E_FMASK 0x1f
+#define GRADW_INST4_SRC_D_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_D_FSHIFT 5
+#define GRADW_INST4_SRC_D_FMASK 0x1f
+#define GRADW_INST4_SRC_C_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_C_FSHIFT 10
+#define GRADW_INST4_SRC_C_FMASK 0x1f
+#define GRADW_INST4_SRC_B_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_B_FSHIFT 15
+#define GRADW_INST4_SRC_B_FMASK 0x1f
+#define GRADW_INST4_SRC_A_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_A_FSHIFT 20
+#define GRADW_INST4_SRC_A_FMASK 0x1f
+#define GRADW_INST4_DST_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_DST_FSHIFT 25
+#define GRADW_INST4_DST_FMASK 0xf
+#define GRADW_INST4_OPCODE_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_OPCODE_FSHIFT 29
+#define GRADW_INST4_OPCODE_FMASK 0x3
+#define GRADW_INST5_SRC_E_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_E_FSHIFT 0
+#define GRADW_INST5_SRC_E_FMASK 0x1f
+#define GRADW_INST5_SRC_D_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_D_FSHIFT 5
+#define GRADW_INST5_SRC_D_FMASK 0x1f
+#define GRADW_INST5_SRC_C_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_C_FSHIFT 10
+#define GRADW_INST5_SRC_C_FMASK 0x1f
+#define GRADW_INST5_SRC_B_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_B_FSHIFT 15
+#define GRADW_INST5_SRC_B_FMASK 0x1f
+#define GRADW_INST5_SRC_A_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_A_FSHIFT 20
+#define GRADW_INST5_SRC_A_FMASK 0x1f
+#define GRADW_INST5_DST_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_DST_FSHIFT 25
+#define GRADW_INST5_DST_FMASK 0xf
+#define GRADW_INST5_OPCODE_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_OPCODE_FSHIFT 29
+#define GRADW_INST5_OPCODE_FMASK 0x3
+#define GRADW_INST6_SRC_E_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_E_FSHIFT 0
+#define GRADW_INST6_SRC_E_FMASK 0x1f
+#define GRADW_INST6_SRC_D_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_D_FSHIFT 5
+#define GRADW_INST6_SRC_D_FMASK 0x1f
+#define GRADW_INST6_SRC_C_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_C_FSHIFT 10
+#define GRADW_INST6_SRC_C_FMASK 0x1f
+#define GRADW_INST6_SRC_B_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_B_FSHIFT 15
+#define GRADW_INST6_SRC_B_FMASK 0x1f
+#define GRADW_INST6_SRC_A_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_A_FSHIFT 20
+#define GRADW_INST6_SRC_A_FMASK 0x1f
+#define GRADW_INST6_DST_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_DST_FSHIFT 25
+#define GRADW_INST6_DST_FMASK 0xf
+#define GRADW_INST6_OPCODE_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_OPCODE_FSHIFT 29
+#define GRADW_INST6_OPCODE_FMASK 0x3
+#define GRADW_INST7_SRC_E_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_E_FSHIFT 0
+#define GRADW_INST7_SRC_E_FMASK 0x1f
+#define GRADW_INST7_SRC_D_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_D_FSHIFT 5
+#define GRADW_INST7_SRC_D_FMASK 0x1f
+#define GRADW_INST7_SRC_C_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_C_FSHIFT 10
+#define GRADW_INST7_SRC_C_FMASK 0x1f
+#define GRADW_INST7_SRC_B_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_B_FSHIFT 15
+#define GRADW_INST7_SRC_B_FMASK 0x1f
+#define GRADW_INST7_SRC_A_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_A_FSHIFT 20
+#define GRADW_INST7_SRC_A_FMASK 0x1f
+#define GRADW_INST7_DST_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_DST_FSHIFT 25
+#define GRADW_INST7_DST_FMASK 0xf
+#define GRADW_INST7_OPCODE_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_OPCODE_FSHIFT 29
+#define GRADW_INST7_OPCODE_FMASK 0x3
+#define GRADW_TEXBASE_ADDR_FADDR ADDR_GRADW_TEXBASE
+#define GRADW_TEXBASE_ADDR_FSHIFT 0
+#define GRADW_TEXBASE_ADDR_FMASK 0xffffffff
+#define GRADW_TEXCFG_STRIDE_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_STRIDE_FSHIFT 0
+#define GRADW_TEXCFG_STRIDE_FMASK 0xfff
+#define GRADW_TEXCFG_FORMAT_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_FORMAT_FSHIFT 12
+#define GRADW_TEXCFG_FORMAT_FMASK 0xf
+#define GRADW_TEXCFG_TILED_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_TILED_FSHIFT 16
+#define GRADW_TEXCFG_TILED_FMASK 0x1
+#define GRADW_TEXCFG_WRAPU_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_WRAPU_FSHIFT 17
+#define GRADW_TEXCFG_WRAPU_FMASK 0x3
+#define GRADW_TEXCFG_WRAPV_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_WRAPV_FSHIFT 19
+#define GRADW_TEXCFG_WRAPV_FMASK 0x3
+#define GRADW_TEXCFG_BILIN_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_BILIN_FSHIFT 21
+#define GRADW_TEXCFG_BILIN_FMASK 0x1
+#define GRADW_TEXCFG_SRGB_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SRGB_FSHIFT 22
+#define GRADW_TEXCFG_SRGB_FMASK 0x1
+#define GRADW_TEXCFG_PREMULTIPLY_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_PREMULTIPLY_FSHIFT 23
+#define GRADW_TEXCFG_PREMULTIPLY_FMASK 0x1
+#define GRADW_TEXCFG_SWAPWORDS_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPWORDS_FSHIFT 24
+#define GRADW_TEXCFG_SWAPWORDS_FMASK 0x1
+#define GRADW_TEXCFG_SWAPBYTES_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPBYTES_FSHIFT 25
+#define GRADW_TEXCFG_SWAPBYTES_FMASK 0x1
+#define GRADW_TEXCFG_SWAPALL_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPALL_FSHIFT 26
+#define GRADW_TEXCFG_SWAPALL_FMASK 0x1
+#define GRADW_TEXCFG_SWAPRB_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPRB_FSHIFT 27
+#define GRADW_TEXCFG_SWAPRB_FMASK 0x1
+#define GRADW_TEXCFG_TEX2D_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_TEX2D_FSHIFT 28
+#define GRADW_TEXCFG_TEX2D_FMASK 0x1
+#define GRADW_TEXCFG_SWAPBITS_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPBITS_FSHIFT 29
+#define GRADW_TEXCFG_SWAPBITS_FMASK 0x1
+#define GRADW_TEXSIZE_WIDTH_FADDR ADDR_GRADW_TEXSIZE
+#define GRADW_TEXSIZE_WIDTH_FSHIFT 0
+#define GRADW_TEXSIZE_WIDTH_FMASK 0x7ff
+#define GRADW_TEXSIZE_HEIGHT_FADDR ADDR_GRADW_TEXSIZE
+#define GRADW_TEXSIZE_HEIGHT_FSHIFT 11
+#define GRADW_TEXSIZE_HEIGHT_FMASK 0x7ff
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FSHIFT 0
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FMASK 0x3f
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FSHIFT 6
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FMASK 0x1
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FSHIFT 7
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FSHIFT 8
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FSHIFT 9
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FMASK 0x1
+#define MH_ARBITER_CONFIG_PAGE_SIZE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_PAGE_SIZE_FSHIFT 10
+#define MH_ARBITER_CONFIG_PAGE_SIZE_FMASK 0x7
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FSHIFT 13
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FSHIFT 14
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FSHIFT 15
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FSHIFT 16
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FMASK 0x3f
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FSHIFT 22
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FSHIFT 23
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FSHIFT 24
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FSHIFT 25
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FSHIFT 26
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FMASK 0x1
+#define MH_AXI_ERROR_AXI_READ_ID_FADDR ADDR_MH_AXI_ERROR
+#define MH_AXI_ERROR_AXI_READ_ID_FSHIFT 0
+#define MH_AXI_ERROR_AXI_READ_ID_FMASK 0x7
+#define MH_AXI_ERROR_AXI_READ_ERROR_FADDR ADDR_MH_AXI_ERROR
+#define MH_AXI_ERROR_AXI_READ_ERROR_FSHIFT 3
+#define MH_AXI_ERROR_AXI_READ_ERROR_FMASK 0x1
+#define MH_AXI_ERROR_AXI_WRITE_ID_FADDR ADDR_MH_AXI_ERROR
+#define MH_AXI_ERROR_AXI_WRITE_ID_FSHIFT 4
+#define MH_AXI_ERROR_AXI_WRITE_ID_FMASK 0x7
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_FADDR ADDR_MH_AXI_ERROR
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_FSHIFT 7
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_FMASK 0x1
+#define MH_AXI_HALT_CONTROL_AXI_HALT_FADDR ADDR_MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL_AXI_HALT_FSHIFT 0
+#define MH_AXI_HALT_CONTROL_AXI_HALT_FMASK 0x1
+#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FSHIFT 0
+#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FMASK 0x7
+#define MH_CLNT_AXI_ID_REUSE_PAD_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_PAD_FSHIFT 3
+#define MH_CLNT_AXI_ID_REUSE_PAD_FMASK 0x1
+#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FSHIFT 4
+#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FMASK 0x7
+#define MH_CLNT_AXI_ID_REUSE_PAD2_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_PAD2_FSHIFT 7
+#define MH_CLNT_AXI_ID_REUSE_PAD2_FMASK 0x1
+#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FSHIFT 8
+#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FMASK 0x7
+#define MH_CLNT_AXI_ID_REUSE_PAD3_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_PAD3_FSHIFT 11
+#define MH_CLNT_AXI_ID_REUSE_PAD3_FMASK 0x1
+#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FSHIFT 12
+#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FMASK 0x7
+#define MH_DEBUG_CTRL_INDEX_FADDR ADDR_MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL_INDEX_FSHIFT 0
+#define MH_DEBUG_CTRL_INDEX_FMASK 0x3f
+#define MH_DEBUG_DATA_DATA_FADDR ADDR_MH_DEBUG_DATA
+#define MH_DEBUG_DATA_DATA_FSHIFT 0
+#define MH_DEBUG_DATA_DATA_FMASK 0xffffffff
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FSHIFT 0
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FMASK 0x1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FSHIFT 1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FMASK 0x1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FSHIFT 2
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FMASK 0x1
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FSHIFT 0
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FMASK 0x1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FSHIFT 1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FMASK 0x1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FSHIFT 2
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FMASK 0x1
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FSHIFT 0
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FMASK 0x1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FSHIFT 1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FMASK 0x1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FSHIFT 2
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FMASK 0x1
+#define MH_MMU_CONFIG_MMU_ENABLE_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_MMU_ENABLE_FSHIFT 0
+#define MH_MMU_CONFIG_MMU_ENABLE_FMASK 0x1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FSHIFT 1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FMASK 0x1
+#define MH_MMU_CONFIG_PAD_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_PAD_FSHIFT 2
+#define MH_MMU_CONFIG_PAD_FMASK 0x3
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FSHIFT 4
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FSHIFT 6
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FSHIFT 8
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FSHIFT 10
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FSHIFT 12
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FSHIFT 14
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FSHIFT 16
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FSHIFT 18
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FSHIFT 20
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FSHIFT 22
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FSHIFT 24
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FADDR ADDR_MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FSHIFT 0
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FMASK 0x1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_FADDR ADDR_MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_FSHIFT 1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_FMASK 0x1
+#define MH_MMU_MPU_BASE_ZERO_FADDR ADDR_MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE_ZERO_FSHIFT 0
+#define MH_MMU_MPU_BASE_ZERO_FMASK 0xfff
+#define MH_MMU_MPU_BASE_MPU_BASE_FADDR ADDR_MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE_MPU_BASE_FSHIFT 12
+#define MH_MMU_MPU_BASE_MPU_BASE_FMASK 0xfffff
+#define MH_MMU_MPU_END_ZERO_FADDR ADDR_MH_MMU_MPU_END
+#define MH_MMU_MPU_END_ZERO_FSHIFT 0
+#define MH_MMU_MPU_END_ZERO_FMASK 0xfff
+#define MH_MMU_MPU_END_MPU_END_FADDR ADDR_MH_MMU_MPU_END
+#define MH_MMU_MPU_END_MPU_END_FSHIFT 12
+#define MH_MMU_MPU_END_MPU_END_FMASK 0xfffff
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FSHIFT 0
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_OP_TYPE_FSHIFT 1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FSHIFT 2
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_PAGE_FAULT_AXI_ID_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_AXI_ID_FSHIFT 4
+#define MH_MMU_PAGE_FAULT_AXI_ID_FMASK 0x7
+#define MH_MMU_PAGE_FAULT_PAD_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_PAD_FSHIFT 7
+#define MH_MMU_PAGE_FAULT_PAD_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FSHIFT 8
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FSHIFT 9
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FSHIFT 10
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FSHIFT 11
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_REQ_VA_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_REQ_VA_FSHIFT 12
+#define MH_MMU_PAGE_FAULT_REQ_VA_FMASK 0xfffff
+#define MH_MMU_PT_BASE_ZERO_FADDR ADDR_MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE_ZERO_FSHIFT 0
+#define MH_MMU_PT_BASE_ZERO_FMASK 0xfff
+#define MH_MMU_PT_BASE_PT_BASE_FADDR ADDR_MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE_PT_BASE_FSHIFT 12
+#define MH_MMU_PT_BASE_PT_BASE_FMASK 0xfffff
+#define MH_MMU_TRAN_ERROR_ZERO_FADDR ADDR_MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR_ZERO_FSHIFT 0
+#define MH_MMU_TRAN_ERROR_ZERO_FMASK 0x1f
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FADDR ADDR_MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FSHIFT 5
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FMASK 0x7ffffff
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FADDR ADDR_MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FSHIFT 0
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FMASK 0xfff
+#define MH_MMU_VA_RANGE_VA_BASE_FADDR ADDR_MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE_VA_BASE_FSHIFT 12
+#define MH_MMU_VA_RANGE_VA_BASE_FMASK 0xfffff
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FADDR ADDR_MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FSHIFT 0
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FMASK 0xff
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FADDR ADDR_MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FSHIFT 0
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FMASK 0xffff
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FADDR ADDR_MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FSHIFT 0
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FMASK 0xffffffff
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FADDR ADDR_MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FSHIFT 0
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FMASK 0xff
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FADDR ADDR_MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FSHIFT 0
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FMASK 0xff
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FADDR ADDR_MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FSHIFT 0
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FMASK 0xffff
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FADDR ADDR_MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FSHIFT 0
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FMASK 0xffffffff
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FADDR ADDR_MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FSHIFT 0
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FMASK 0xff
+#define MMU_READ_ADDR_ADDR_FADDR ADDR_MMU_READ_ADDR
+#define MMU_READ_ADDR_ADDR_FSHIFT 0
+#define MMU_READ_ADDR_ADDR_FMASK 0x7fff
+#define MMU_READ_DATA_DATA_FADDR ADDR_MMU_READ_DATA
+#define MMU_READ_DATA_DATA_FSHIFT 0
+#define MMU_READ_DATA_DATA_FMASK 0xffffffff
+#define VGV1_CBASE1_ADDR_FADDR ADDR_VGV1_CBASE1
+#define VGV1_CBASE1_ADDR_FSHIFT 0
+#define VGV1_CBASE1_ADDR_FMASK 0xffffffff
+#define VGV1_CFG1_WINDRULE_FADDR ADDR_VGV1_CFG1
+#define VGV1_CFG1_WINDRULE_FSHIFT 0
+#define VGV1_CFG1_WINDRULE_FMASK 0x1
+#define VGV1_CFG2_AAMODE_FADDR ADDR_VGV1_CFG2
+#define VGV1_CFG2_AAMODE_FSHIFT 0
+#define VGV1_CFG2_AAMODE_FMASK 0x3
+#define VGV1_DIRTYBASE_ADDR_FADDR ADDR_VGV1_DIRTYBASE
+#define VGV1_DIRTYBASE_ADDR_FSHIFT 0
+#define VGV1_DIRTYBASE_ADDR_FMASK 0xffffffff
+#define VGV1_FILL_INHERIT_FADDR ADDR_VGV1_FILL
+#define VGV1_FILL_INHERIT_FSHIFT 0
+#define VGV1_FILL_INHERIT_FMASK 0x1
+#define VGV1_SCISSORX_LEFT_FADDR ADDR_VGV1_SCISSORX
+#define VGV1_SCISSORX_LEFT_FSHIFT 0
+#define VGV1_SCISSORX_LEFT_FMASK 0x7ff
+#define VGV1_SCISSORX_PAD_FADDR ADDR_VGV1_SCISSORX
+#define VGV1_SCISSORX_PAD_FSHIFT 11
+#define VGV1_SCISSORX_PAD_FMASK 0x1f
+#define VGV1_SCISSORX_RIGHT_FADDR ADDR_VGV1_SCISSORX
+#define VGV1_SCISSORX_RIGHT_FSHIFT 16
+#define VGV1_SCISSORX_RIGHT_FMASK 0x7ff
+#define VGV1_SCISSORY_TOP_FADDR ADDR_VGV1_SCISSORY
+#define VGV1_SCISSORY_TOP_FSHIFT 0
+#define VGV1_SCISSORY_TOP_FMASK 0x7ff
+#define VGV1_SCISSORY_PAD_FADDR ADDR_VGV1_SCISSORY
+#define VGV1_SCISSORY_PAD_FSHIFT 11
+#define VGV1_SCISSORY_PAD_FMASK 0x1f
+#define VGV1_SCISSORY_BOTTOM_FADDR ADDR_VGV1_SCISSORY
+#define VGV1_SCISSORY_BOTTOM_FSHIFT 16
+#define VGV1_SCISSORY_BOTTOM_FMASK 0x7ff
+#define VGV1_TILEOFS_X_FADDR ADDR_VGV1_TILEOFS
+#define VGV1_TILEOFS_X_FSHIFT 0
+#define VGV1_TILEOFS_X_FMASK 0xfff
+#define VGV1_TILEOFS_Y_FADDR ADDR_VGV1_TILEOFS
+#define VGV1_TILEOFS_Y_FSHIFT 12
+#define VGV1_TILEOFS_Y_FMASK 0xfff
+#define VGV1_TILEOFS_LEFTMOST_FADDR ADDR_VGV1_TILEOFS
+#define VGV1_TILEOFS_LEFTMOST_FSHIFT 24
+#define VGV1_TILEOFS_LEFTMOST_FMASK 0x1
+#define VGV1_UBASE2_ADDR_FADDR ADDR_VGV1_UBASE2
+#define VGV1_UBASE2_ADDR_FSHIFT 0
+#define VGV1_UBASE2_ADDR_FMASK 0xffffffff
+#define VGV1_VTX0_X_FADDR ADDR_VGV1_VTX0
+#define VGV1_VTX0_X_FSHIFT 0
+#define VGV1_VTX0_X_FMASK 0xffff
+#define VGV1_VTX0_Y_FADDR ADDR_VGV1_VTX0
+#define VGV1_VTX0_Y_FSHIFT 16
+#define VGV1_VTX0_Y_FMASK 0xffff
+#define VGV1_VTX1_X_FADDR ADDR_VGV1_VTX1
+#define VGV1_VTX1_X_FSHIFT 0
+#define VGV1_VTX1_X_FMASK 0xffff
+#define VGV1_VTX1_Y_FADDR ADDR_VGV1_VTX1
+#define VGV1_VTX1_Y_FSHIFT 16
+#define VGV1_VTX1_Y_FMASK 0xffff
+#define VGV2_ACCURACY_F_FADDR ADDR_VGV2_ACCURACY
+#define VGV2_ACCURACY_F_FSHIFT 0
+#define VGV2_ACCURACY_F_FMASK 0xffffff
+#define VGV2_ACTION_ACTION_FADDR ADDR_VGV2_ACTION
+#define VGV2_ACTION_ACTION_FSHIFT 0
+#define VGV2_ACTION_ACTION_FMASK 0xf
+#define VGV2_ARCCOS_F_FADDR ADDR_VGV2_ARCCOS
+#define VGV2_ARCCOS_F_FSHIFT 0
+#define VGV2_ARCCOS_F_FMASK 0xffffff
+#define VGV2_ARCSIN_F_FADDR ADDR_VGV2_ARCSIN
+#define VGV2_ARCSIN_F_FSHIFT 0
+#define VGV2_ARCSIN_F_FMASK 0xffffff
+#define VGV2_ARCTAN_F_FADDR ADDR_VGV2_ARCTAN
+#define VGV2_ARCTAN_F_FSHIFT 0
+#define VGV2_ARCTAN_F_FMASK 0xffffff
+#define VGV2_BBOXMAXX_F_FADDR ADDR_VGV2_BBOXMAXX
+#define VGV2_BBOXMAXX_F_FSHIFT 0
+#define VGV2_BBOXMAXX_F_FMASK 0xffffff
+#define VGV2_BBOXMAXY_F_FADDR ADDR_VGV2_BBOXMAXY
+#define VGV2_BBOXMAXY_F_FSHIFT 0
+#define VGV2_BBOXMAXY_F_FMASK 0xffffff
+#define VGV2_BBOXMINX_F_FADDR ADDR_VGV2_BBOXMINX
+#define VGV2_BBOXMINX_F_FSHIFT 0
+#define VGV2_BBOXMINX_F_FMASK 0xffffff
+#define VGV2_BBOXMINY_F_FADDR ADDR_VGV2_BBOXMINY
+#define VGV2_BBOXMINY_F_FSHIFT 0
+#define VGV2_BBOXMINY_F_FMASK 0xffffff
+#define VGV2_BIAS_F_FADDR ADDR_VGV2_BIAS
+#define VGV2_BIAS_F_FSHIFT 0
+#define VGV2_BIAS_F_FMASK 0xffffff
+#define VGV2_C1X_F_FADDR ADDR_VGV2_C1X
+#define VGV2_C1X_F_FSHIFT 0
+#define VGV2_C1X_F_FMASK 0xffffff
+#define VGV2_C1XREL_F_FADDR ADDR_VGV2_C1XREL
+#define VGV2_C1XREL_F_FSHIFT 0
+#define VGV2_C1XREL_F_FMASK 0xffffff
+#define VGV2_C1Y_F_FADDR ADDR_VGV2_C1Y
+#define VGV2_C1Y_F_FSHIFT 0
+#define VGV2_C1Y_F_FMASK 0xffffff
+#define VGV2_C1YREL_F_FADDR ADDR_VGV2_C1YREL
+#define VGV2_C1YREL_F_FSHIFT 0
+#define VGV2_C1YREL_F_FMASK 0xffffff
+#define VGV2_C2X_F_FADDR ADDR_VGV2_C2X
+#define VGV2_C2X_F_FSHIFT 0
+#define VGV2_C2X_F_FMASK 0xffffff
+#define VGV2_C2XREL_F_FADDR ADDR_VGV2_C2XREL
+#define VGV2_C2XREL_F_FSHIFT 0
+#define VGV2_C2XREL_F_FMASK 0xffffff
+#define VGV2_C2Y_F_FADDR ADDR_VGV2_C2Y
+#define VGV2_C2Y_F_FSHIFT 0
+#define VGV2_C2Y_F_FMASK 0xffffff
+#define VGV2_C2YREL_F_FADDR ADDR_VGV2_C2YREL
+#define VGV2_C2YREL_F_FSHIFT 0
+#define VGV2_C2YREL_F_FMASK 0xffffff
+#define VGV2_C3X_F_FADDR ADDR_VGV2_C3X
+#define VGV2_C3X_F_FSHIFT 0
+#define VGV2_C3X_F_FMASK 0xffffff
+#define VGV2_C3XREL_F_FADDR ADDR_VGV2_C3XREL
+#define VGV2_C3XREL_F_FSHIFT 0
+#define VGV2_C3XREL_F_FMASK 0xffffff
+#define VGV2_C3Y_F_FADDR ADDR_VGV2_C3Y
+#define VGV2_C3Y_F_FSHIFT 0
+#define VGV2_C3Y_F_FMASK 0xffffff
+#define VGV2_C3YREL_F_FADDR ADDR_VGV2_C3YREL
+#define VGV2_C3YREL_F_FSHIFT 0
+#define VGV2_C3YREL_F_FMASK 0xffffff
+#define VGV2_C4X_F_FADDR ADDR_VGV2_C4X
+#define VGV2_C4X_F_FSHIFT 0
+#define VGV2_C4X_F_FMASK 0xffffff
+#define VGV2_C4XREL_F_FADDR ADDR_VGV2_C4XREL
+#define VGV2_C4XREL_F_FSHIFT 0
+#define VGV2_C4XREL_F_FMASK 0xffffff
+#define VGV2_C4Y_F_FADDR ADDR_VGV2_C4Y
+#define VGV2_C4Y_F_FSHIFT 0
+#define VGV2_C4Y_F_FMASK 0xffffff
+#define VGV2_C4YREL_F_FADDR ADDR_VGV2_C4YREL
+#define VGV2_C4YREL_F_FSHIFT 0
+#define VGV2_C4YREL_F_FMASK 0xffffff
+#define VGV2_CLIP_F_FADDR ADDR_VGV2_CLIP
+#define VGV2_CLIP_F_FSHIFT 0
+#define VGV2_CLIP_F_FMASK 0xffffff
+#define VGV2_FIRST_DUMMY_FADDR ADDR_VGV2_FIRST
+#define VGV2_FIRST_DUMMY_FSHIFT 0
+#define VGV2_FIRST_DUMMY_FMASK 0x1
+#define VGV2_LAST_DUMMY_FADDR ADDR_VGV2_LAST
+#define VGV2_LAST_DUMMY_FSHIFT 0
+#define VGV2_LAST_DUMMY_FMASK 0x1
+#define VGV2_MITER_F_FADDR ADDR_VGV2_MITER
+#define VGV2_MITER_F_FSHIFT 0
+#define VGV2_MITER_F_FMASK 0xffffff
+#define VGV2_MODE_MAXSPLIT_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_MAXSPLIT_FSHIFT 0
+#define VGV2_MODE_MAXSPLIT_FMASK 0xf
+#define VGV2_MODE_CAP_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_CAP_FSHIFT 4
+#define VGV2_MODE_CAP_FMASK 0x3
+#define VGV2_MODE_JOIN_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_JOIN_FSHIFT 6
+#define VGV2_MODE_JOIN_FMASK 0x3
+#define VGV2_MODE_STROKE_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_STROKE_FSHIFT 8
+#define VGV2_MODE_STROKE_FMASK 0x1
+#define VGV2_MODE_STROKESPLIT_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_STROKESPLIT_FSHIFT 9
+#define VGV2_MODE_STROKESPLIT_FMASK 0x1
+#define VGV2_MODE_FULLSPLIT_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_FULLSPLIT_FSHIFT 10
+#define VGV2_MODE_FULLSPLIT_FMASK 0x1
+#define VGV2_MODE_NODOTS_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_NODOTS_FSHIFT 11
+#define VGV2_MODE_NODOTS_FMASK 0x1
+#define VGV2_MODE_OPENFILL_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_OPENFILL_FSHIFT 12
+#define VGV2_MODE_OPENFILL_FMASK 0x1
+#define VGV2_MODE_DROPLEFT_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_DROPLEFT_FSHIFT 13
+#define VGV2_MODE_DROPLEFT_FMASK 0x1
+#define VGV2_MODE_DROPOTHER_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_DROPOTHER_FSHIFT 14
+#define VGV2_MODE_DROPOTHER_FMASK 0x1
+#define VGV2_MODE_SYMMETRICJOINS_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_SYMMETRICJOINS_FSHIFT 15
+#define VGV2_MODE_SYMMETRICJOINS_FMASK 0x1
+#define VGV2_MODE_SIMPLESTROKE_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_SIMPLESTROKE_FSHIFT 16
+#define VGV2_MODE_SIMPLESTROKE_FMASK 0x1
+#define VGV2_MODE_SIMPLECLIP_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_SIMPLECLIP_FSHIFT 17
+#define VGV2_MODE_SIMPLECLIP_FMASK 0x1
+#define VGV2_MODE_EXPONENTADD_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_EXPONENTADD_FSHIFT 18
+#define VGV2_MODE_EXPONENTADD_FMASK 0x3f
+#define VGV2_RADIUS_F_FADDR ADDR_VGV2_RADIUS
+#define VGV2_RADIUS_F_FSHIFT 0
+#define VGV2_RADIUS_F_FMASK 0xffffff
+#define VGV2_SCALE_F_FADDR ADDR_VGV2_SCALE
+#define VGV2_SCALE_F_FSHIFT 0
+#define VGV2_SCALE_F_FMASK 0xffffff
+#define VGV2_THINRADIUS_F_FADDR ADDR_VGV2_THINRADIUS
+#define VGV2_THINRADIUS_F_FSHIFT 0
+#define VGV2_THINRADIUS_F_FMASK 0xffffff
+#define VGV2_XFSTXX_F_FADDR ADDR_VGV2_XFSTXX
+#define VGV2_XFSTXX_F_FSHIFT 0
+#define VGV2_XFSTXX_F_FMASK 0xffffff
+#define VGV2_XFSTXY_F_FADDR ADDR_VGV2_XFSTXY
+#define VGV2_XFSTXY_F_FSHIFT 0
+#define VGV2_XFSTXY_F_FMASK 0xffffff
+#define VGV2_XFSTYX_F_FADDR ADDR_VGV2_XFSTYX
+#define VGV2_XFSTYX_F_FSHIFT 0
+#define VGV2_XFSTYX_F_FMASK 0xffffff
+#define VGV2_XFSTYY_F_FADDR ADDR_VGV2_XFSTYY
+#define VGV2_XFSTYY_F_FSHIFT 0
+#define VGV2_XFSTYY_F_FMASK 0xffffff
+#define VGV2_XFXA_F_FADDR ADDR_VGV2_XFXA
+#define VGV2_XFXA_F_FSHIFT 0
+#define VGV2_XFXA_F_FMASK 0xffffff
+#define VGV2_XFXX_F_FADDR ADDR_VGV2_XFXX
+#define VGV2_XFXX_F_FSHIFT 0
+#define VGV2_XFXX_F_FMASK 0xffffff
+#define VGV2_XFXY_F_FADDR ADDR_VGV2_XFXY
+#define VGV2_XFXY_F_FSHIFT 0
+#define VGV2_XFXY_F_FMASK 0xffffff
+#define VGV2_XFYA_F_FADDR ADDR_VGV2_XFYA
+#define VGV2_XFYA_F_FSHIFT 0
+#define VGV2_XFYA_F_FMASK 0xffffff
+#define VGV2_XFYX_F_FADDR ADDR_VGV2_XFYX
+#define VGV2_XFYX_F_FSHIFT 0
+#define VGV2_XFYX_F_FMASK 0xffffff
+#define VGV2_XFYY_F_FADDR ADDR_VGV2_XFYY
+#define VGV2_XFYY_F_FSHIFT 0
+#define VGV2_XFYY_F_FMASK 0xffffff
+#define VGV3_CONTROL_MARKADD_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_MARKADD_FSHIFT 0
+#define VGV3_CONTROL_MARKADD_FMASK 0xfff
+#define VGV3_CONTROL_DMIWAITCHMASK_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_DMIWAITCHMASK_FSHIFT 12
+#define VGV3_CONTROL_DMIWAITCHMASK_FMASK 0xf
+#define VGV3_CONTROL_PAUSE_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_PAUSE_FSHIFT 16
+#define VGV3_CONTROL_PAUSE_FMASK 0x1
+#define VGV3_CONTROL_ABORT_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_ABORT_FSHIFT 17
+#define VGV3_CONTROL_ABORT_FMASK 0x1
+#define VGV3_CONTROL_WRITE_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_WRITE_FSHIFT 18
+#define VGV3_CONTROL_WRITE_FMASK 0x1
+#define VGV3_CONTROL_BCFLUSH_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_BCFLUSH_FSHIFT 19
+#define VGV3_CONTROL_BCFLUSH_FMASK 0x1
+#define VGV3_CONTROL_V0SYNC_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_V0SYNC_FSHIFT 20
+#define VGV3_CONTROL_V0SYNC_FMASK 0x1
+#define VGV3_CONTROL_DMIWAITBUF_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_DMIWAITBUF_FSHIFT 21
+#define VGV3_CONTROL_DMIWAITBUF_FMASK 0x7
+#define VGV3_FIRST_DUMMY_FADDR ADDR_VGV3_FIRST
+#define VGV3_FIRST_DUMMY_FSHIFT 0
+#define VGV3_FIRST_DUMMY_FMASK 0x1
+#define VGV3_LAST_DUMMY_FADDR ADDR_VGV3_LAST
+#define VGV3_LAST_DUMMY_FSHIFT 0
+#define VGV3_LAST_DUMMY_FMASK 0x1
+#define VGV3_MODE_FLIPENDIAN_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_FLIPENDIAN_FSHIFT 0
+#define VGV3_MODE_FLIPENDIAN_FMASK 0x1
+#define VGV3_MODE_UNUSED_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_UNUSED_FSHIFT 1
+#define VGV3_MODE_UNUSED_FMASK 0x1
+#define VGV3_MODE_WRITEFLUSH_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_WRITEFLUSH_FSHIFT 2
+#define VGV3_MODE_WRITEFLUSH_FMASK 0x1
+#define VGV3_MODE_DMIPAUSETYPE_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_DMIPAUSETYPE_FSHIFT 3
+#define VGV3_MODE_DMIPAUSETYPE_FMASK 0x1
+#define VGV3_MODE_DMIRESET_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_DMIRESET_FSHIFT 4
+#define VGV3_MODE_DMIRESET_FMASK 0x1
+#define VGV3_NEXTADDR_CALLADDR_FADDR ADDR_VGV3_NEXTADDR
+#define VGV3_NEXTADDR_CALLADDR_FSHIFT 0
+#define VGV3_NEXTADDR_CALLADDR_FMASK 0xffffffff
+#define VGV3_NEXTCMD_COUNT_FADDR ADDR_VGV3_NEXTCMD
+#define VGV3_NEXTCMD_COUNT_FSHIFT 0
+#define VGV3_NEXTCMD_COUNT_FMASK 0xfff
+#define VGV3_NEXTCMD_NEXTCMD_FADDR ADDR_VGV3_NEXTCMD
+#define VGV3_NEXTCMD_NEXTCMD_FSHIFT 12
+#define VGV3_NEXTCMD_NEXTCMD_FMASK 0x7
+#define VGV3_NEXTCMD_MARK_FADDR ADDR_VGV3_NEXTCMD
+#define VGV3_NEXTCMD_MARK_FSHIFT 15
+#define VGV3_NEXTCMD_MARK_FMASK 0x1
+#define VGV3_NEXTCMD_CALLCOUNT_FADDR ADDR_VGV3_NEXTCMD
+#define VGV3_NEXTCMD_CALLCOUNT_FSHIFT 16
+#define VGV3_NEXTCMD_CALLCOUNT_FMASK 0xfff
+#define VGV3_VGBYPASS_BYPASS_FADDR ADDR_VGV3_VGBYPASS
+#define VGV3_VGBYPASS_BYPASS_FSHIFT 0
+#define VGV3_VGBYPASS_BYPASS_FMASK 0x1
+#define VGV3_WRITE_VALUE_FADDR ADDR_VGV3_WRITE
+#define VGV3_WRITE_VALUE_FSHIFT 0
+#define VGV3_WRITE_VALUE_FMASK 0xffffffff
+#define VGV3_WRITEADDR_ADDR_FADDR ADDR_VGV3_WRITEADDR
+#define VGV3_WRITEADDR_ADDR_FSHIFT 0
+#define VGV3_WRITEADDR_ADDR_FMASK 0xffffffff
+#define VGV3_WRITEDMI_CHANMASK_FADDR ADDR_VGV3_WRITEDMI
+#define VGV3_WRITEDMI_CHANMASK_FSHIFT 0
+#define VGV3_WRITEDMI_CHANMASK_FMASK 0xf
+#define VGV3_WRITEDMI_BUFFER_FADDR ADDR_VGV3_WRITEDMI
+#define VGV3_WRITEDMI_BUFFER_FSHIFT 4
+#define VGV3_WRITEDMI_BUFFER_FMASK 0x7
+#define VGV3_WRITEF32_ADDR_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_ADDR_FSHIFT 0
+#define VGV3_WRITEF32_ADDR_FMASK 0xff
+#define VGV3_WRITEF32_COUNT_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_COUNT_FSHIFT 8
+#define VGV3_WRITEF32_COUNT_FMASK 0xff
+#define VGV3_WRITEF32_LOOP_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_LOOP_FSHIFT 16
+#define VGV3_WRITEF32_LOOP_FMASK 0xf
+#define VGV3_WRITEF32_ACTION_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_ACTION_FSHIFT 20
+#define VGV3_WRITEF32_ACTION_FMASK 0xf
+#define VGV3_WRITEF32_FORMAT_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_FORMAT_FSHIFT 24
+#define VGV3_WRITEF32_FORMAT_FMASK 0x7
+#define VGV3_WRITEIFPAUSED_VALUE_FADDR ADDR_VGV3_WRITEIFPAUSED
+#define VGV3_WRITEIFPAUSED_VALUE_FSHIFT 0
+#define VGV3_WRITEIFPAUSED_VALUE_FMASK 0xffffffff
+#define VGV3_WRITERAW_ADDR_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_ADDR_FSHIFT 0
+#define VGV3_WRITERAW_ADDR_FMASK 0xff
+#define VGV3_WRITERAW_COUNT_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_COUNT_FSHIFT 8
+#define VGV3_WRITERAW_COUNT_FMASK 0xff
+#define VGV3_WRITERAW_LOOP_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_LOOP_FSHIFT 16
+#define VGV3_WRITERAW_LOOP_FMASK 0xf
+#define VGV3_WRITERAW_ACTION_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_ACTION_FSHIFT 20
+#define VGV3_WRITERAW_ACTION_FMASK 0xf
+#define VGV3_WRITERAW_FORMAT_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_FORMAT_FSHIFT 24
+#define VGV3_WRITERAW_FORMAT_FMASK 0x7
+#define VGV3_WRITES16_ADDR_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_ADDR_FSHIFT 0
+#define VGV3_WRITES16_ADDR_FMASK 0xff
+#define VGV3_WRITES16_COUNT_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_COUNT_FSHIFT 8
+#define VGV3_WRITES16_COUNT_FMASK 0xff
+#define VGV3_WRITES16_LOOP_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_LOOP_FSHIFT 16
+#define VGV3_WRITES16_LOOP_FMASK 0xf
+#define VGV3_WRITES16_ACTION_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_ACTION_FSHIFT 20
+#define VGV3_WRITES16_ACTION_FMASK 0xf
+#define VGV3_WRITES16_FORMAT_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_FORMAT_FSHIFT 24
+#define VGV3_WRITES16_FORMAT_FMASK 0x7
+#define VGV3_WRITES32_ADDR_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_ADDR_FSHIFT 0
+#define VGV3_WRITES32_ADDR_FMASK 0xff
+#define VGV3_WRITES32_COUNT_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_COUNT_FSHIFT 8
+#define VGV3_WRITES32_COUNT_FMASK 0xff
+#define VGV3_WRITES32_LOOP_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_LOOP_FSHIFT 16
+#define VGV3_WRITES32_LOOP_FMASK 0xf
+#define VGV3_WRITES32_ACTION_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_ACTION_FSHIFT 20
+#define VGV3_WRITES32_ACTION_FMASK 0xf
+#define VGV3_WRITES32_FORMAT_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_FORMAT_FSHIFT 24
+#define VGV3_WRITES32_FORMAT_FMASK 0x7
+#define VGV3_WRITES8_ADDR_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_ADDR_FSHIFT 0
+#define VGV3_WRITES8_ADDR_FMASK 0xff
+#define VGV3_WRITES8_COUNT_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_COUNT_FSHIFT 8
+#define VGV3_WRITES8_COUNT_FMASK 0xff
+#define VGV3_WRITES8_LOOP_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_LOOP_FSHIFT 16
+#define VGV3_WRITES8_LOOP_FMASK 0xf
+#define VGV3_WRITES8_ACTION_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_ACTION_FSHIFT 20
+#define VGV3_WRITES8_ACTION_FMASK 0xf
+#define VGV3_WRITES8_FORMAT_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_FORMAT_FSHIFT 24
+#define VGV3_WRITES8_FORMAT_FMASK 0x7
+typedef struct {
+    unsigned RS[256];
+    unsigned GRADW[2][40];
+} regstate_t;
+
+#define GRADW_WINDOW_START 0xc0
+#define GRADW_WINDOW_LEN 0x28
+#define GRADW_WINDOW_NUM 0x2
+
+static unsigned __inline __getwrs__(regstate_t* RS, unsigned win, unsigned addr, unsigned shift, unsigned mask) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        assert( win < 2 );
+        return (RS->GRADW[win][addr-0xc0] >>
+                shift) & mask;
+    }
+    return ((RS->RS[addr] >> shift) & mask);
+}
+
+static void __inline __setwrs__(regstate_t* RS, unsigned win, unsigned addr, unsigned shift, unsigned mask, unsigned data) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        assert( win < 2 );
+        RS->GRADW[win][addr-0xc0] = (RS->GRADW[win][addr-0xc0] & 
+                   ~(mask << shift)) | 
+                   ((mask & data) << shift);
+    }
+    RS->RS[addr] = (RS->RS[addr] & ~(mask << shift)) | ((mask & data) << shift);
+}
+
+static void __inline __setwreg__(regstate_t* RS, unsigned win, unsigned addr, unsigned data) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        assert( win < 2 );
+        RS->GRADW[win][addr-0xc0] = data;
+    }
+    RS->RS[addr] = data;
+}
+
+static unsigned __inline __getrs__(regstate_t* RS, unsigned addr, unsigned shift, unsigned mask) {
+    return ((RS->RS[addr] >> shift) & mask);
+}
+
+static void __inline __setrs__(regstate_t* RS, unsigned addr, unsigned shift, unsigned mask, unsigned data) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        unsigned win = __getrs__(RS, G2D_GRADIENT_SEL_FADDR, G2D_GRADIENT_SEL_FSHIFT, G2D_GRADIENT_SEL_FMASK);
+        assert( win < 2 );
+        RS->GRADW[win][addr-0xc0] = (RS->GRADW[win][addr-0xc0] & 
+                   ~(mask << shift)) | ((mask & data) << shift);
+    }
+    RS->RS[addr] = (RS->RS[addr] & ~(mask << shift)) | ((mask & data) << shift);
+}
+
+static void __inline __setreg__(regstate_t* RS, unsigned addr, unsigned data) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        unsigned win = __getrs__(RS, G2D_GRADIENT_SEL_FADDR, G2D_GRADIENT_SEL_FSHIFT, G2D_GRADIENT_SEL_FMASK);
+        assert( win < 2 );
+        RS->GRADW[win][addr-0xc0] = data;
+    }
+    RS->RS[addr] = data;
+}
+
+#define SETWRS(win, id, value) __setwrs__(&RS, win, id##_FADDR, id##_FSHIFT, id##_FMASK, value)
+#define GETWRS(win, id) __getwrs__(&RS, win, id##_FADDR, id##_FSHIFT, id##_FMASK)
+#define SETWREG(win, reg, data) __setwreg__(&RS, win, reg, data)
+#define SETRS(id, value) __setrs__(&RS, id##_FADDR, id##_FSHIFT, id##_FMASK, value)
+#define GETRS(id) __getrs__(&RS, id##_FADDR, id##_FSHIFT, id##_FMASK)
+#define SETREG(reg, data) __setreg__(&RS, reg, data)
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato.h b/drivers/mxc/amd-gpu/include/reg/yamato.h
new file mode 100644
index 000000000000..05cae6c46403
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _YAMATO_H
+#define _YAMATO_H
+
+#ifndef qLittleEndian
+#define qLittleEndian
+#endif
+
+#if defined(_YDX14)
+#if defined(_WIN32) && !defined(__SYMBIAN32__)
+#pragma message("YDX 14 header files\r\n")
+#endif
+#include "yamato/14/yamato_enum.h"
+#include "yamato/14/yamato_ipt.h"
+#include "yamato/14/yamato_mask.h"
+#include "yamato/14/yamato_offset.h"
+#include "yamato/14/yamato_registers.h"
+#include "yamato/14/yamato_shift.h"
+#include "yamato/14/yamato_struct.h"
+#include "yamato/14/yamato_typedef.h"
+#define _YAMATO_GENENUM_H           "reg/yamato/14/yamato_genenum.h"
+#define _YAMATO_GENREG_H            "reg/yamato/14/yamato_genreg.h"
+#else
+#if defined(_WIN32) && !defined(__SYMBIAN32__)
+#pragma message("YDX 22 header files\r\n")
+#endif
+#include "yamato/22/yamato_enum.h"
+#include "yamato/22/yamato_ipt.h"
+#include "yamato/22/yamato_mask.h"
+#include "yamato/22/yamato_offset.h"
+#include "yamato/22/yamato_registers.h"
+#include "yamato/22/yamato_shift.h"
+#include "yamato/22/yamato_struct.h"
+#include "yamato/22/yamato_typedef.h"
+#define _YAMATO_GENENUM_H           "reg/yamato/22/yamato_genenum.h"
+#define _YAMATO_GENREG_H            "reg/yamato/22/yamato_genreg.h"
+#endif
+
+#endif // _YAMATO_H
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h
new file mode 100644
index 000000000000..144e9151fd8a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h
@@ -0,0 +1,1895 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_ENUM_HEADER)
+#define _yamato_ENUM_HEADER
+
+#ifndef _DRIVER_BUILD
+#ifndef GL_ZERO
+#define GL__ZERO                      BLEND_ZERO
+#define GL__ONE                       BLEND_ONE
+#define GL__SRC_COLOR                 BLEND_SRC_COLOR
+#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
+#define GL__DST_COLOR                 BLEND_DST_COLOR
+#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
+#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
+#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
+#define GL__DST_ALPHA                 BLEND_DST_ALPHA
+#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
+#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
+#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
+#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
+#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
+#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
+#endif
+#endif
+
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+#ifndef ENUMS_SU_PERFCNT_SELECT_H
+#define ENUMS_SU_PERFCNT_SELECT_H
+typedef enum SU_PERFCNT_SELECT {
+ PERF_PAPC_PASX_REQ = 0,
+ UNUSED1 = 1,
+ PERF_PAPC_PASX_FIRST_VECTOR = 2,
+ PERF_PAPC_PASX_SECOND_VECTOR = 3,
+ PERF_PAPC_PASX_FIRST_DEAD = 4,
+ PERF_PAPC_PASX_SECOND_DEAD = 5,
+ PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
+ PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
+ PERF_PAPC_PA_INPUT_PRIM = 8,
+ PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
+ PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
+ PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
+ PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
+ PERF_PAPC_CLPR_CULL_PRIM = 13,
+ UNUSED2 = 14,
+ PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
+ UNUSED3 = 16,
+ PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
+ PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
+ PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
+ UNUSED4 = 20,
+ PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
+ UNUSED5 = 22,
+ PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
+ PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
+ PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
+ PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
+ PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
+ PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
+ PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
+ PERF_PAPC_CLSM_NULL_PRIM = 36,
+ PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
+ PERF_PAPC_CLSM_CLIP_PRIM = 38,
+ PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
+ PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
+ PERF_PAPC_SU_INPUT_PRIM = 47,
+ PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
+ PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
+ PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
+ PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
+ PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
+ PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
+ PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
+ PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
+ PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
+ PERF_PAPC_SU_OUTPUT_PRIM = 57,
+ PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
+ PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
+ PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
+ PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
+ PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
+ PERF_PAPC_PASX_REQ_IDLE = 69,
+ PERF_PAPC_PASX_REQ_BUSY = 70,
+ PERF_PAPC_PASX_REQ_STALLED = 71,
+ PERF_PAPC_PASX_REC_IDLE = 72,
+ PERF_PAPC_PASX_REC_BUSY = 73,
+ PERF_PAPC_PASX_REC_STARVED_SX = 74,
+ PERF_PAPC_PASX_REC_STALLED = 75,
+ PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
+ PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
+ PERF_PAPC_CCGSM_IDLE = 78,
+ PERF_PAPC_CCGSM_BUSY = 79,
+ PERF_PAPC_CCGSM_STALLED = 80,
+ PERF_PAPC_CLPRIM_IDLE = 81,
+ PERF_PAPC_CLPRIM_BUSY = 82,
+ PERF_PAPC_CLPRIM_STALLED = 83,
+ PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
+ PERF_PAPC_CLIPSM_IDLE = 85,
+ PERF_PAPC_CLIPSM_BUSY = 86,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
+ PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
+ PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
+ PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
+ PERF_PAPC_CLIPGA_IDLE = 92,
+ PERF_PAPC_CLIPGA_BUSY = 93,
+ PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
+ PERF_PAPC_CLIPGA_STALLED = 95,
+ PERF_PAPC_CLIP_IDLE = 96,
+ PERF_PAPC_CLIP_BUSY = 97,
+ PERF_PAPC_SU_IDLE = 98,
+ PERF_PAPC_SU_BUSY = 99,
+ PERF_PAPC_SU_STARVED_CLIP = 100,
+ PERF_PAPC_SU_STALLED_SC = 101,
+ PERF_PAPC_SU_FACENESS_CULL = 102,
+} SU_PERFCNT_SELECT;
+#endif /*ENUMS_SU_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SC_PERFCNT_SELECT_H
+#define ENUMS_SC_PERFCNT_SELECT_H
+typedef enum SC_PERFCNT_SELECT {
+ SC_SR_WINDOW_VALID = 0,
+ SC_CW_WINDOW_VALID = 1,
+ SC_QM_WINDOW_VALID = 2,
+ SC_FW_WINDOW_VALID = 3,
+ SC_EZ_WINDOW_VALID = 4,
+ SC_IT_WINDOW_VALID = 5,
+ SC_STARVED_BY_PA = 6,
+ SC_STALLED_BY_RB_TILE = 7,
+ SC_STALLED_BY_RB_SAMP = 8,
+ SC_STARVED_BY_RB_EZ = 9,
+ SC_STALLED_BY_SAMPLE_FF = 10,
+ SC_STALLED_BY_SQ = 11,
+ SC_STALLED_BY_SP = 12,
+ SC_TOTAL_NO_PRIMS = 13,
+ SC_NON_EMPTY_PRIMS = 14,
+ SC_NO_TILES_PASSING_QM = 15,
+ SC_NO_PIXELS_PRE_EZ = 16,
+ SC_NO_PIXELS_POST_EZ = 17,
+} SC_PERFCNT_SELECT;
+#endif /*ENUMS_SC_PERFCNT_SELECT_H*/
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+#ifndef ENUMS_VGT_DI_PRIM_TYPE_H
+#define ENUMS_VGT_DI_PRIM_TYPE_H
+typedef enum VGT_DI_PRIM_TYPE {
+ DI_PT_NONE = 0,
+ DI_PT_POINTLIST = 1,
+ DI_PT_LINELIST = 2,
+ DI_PT_LINESTRIP = 3,
+ DI_PT_TRILIST = 4,
+ DI_PT_TRIFAN = 5,
+ DI_PT_TRISTRIP = 6,
+ DI_PT_UNUSED_1 = 7,
+ DI_PT_RECTLIST = 8,
+ DI_PT_UNUSED_2 = 9,
+ DI_PT_UNUSED_3 = 10,
+ DI_PT_UNUSED_4 = 11,
+ DI_PT_UNUSED_5 = 12,
+ DI_PT_QUADLIST = 13,
+ DI_PT_QUADSTRIP = 14,
+ DI_PT_POLYGON = 15,
+ DI_PT_2D_COPY_RECT_LIST_V0 = 16,
+ DI_PT_2D_COPY_RECT_LIST_V1 = 17,
+ DI_PT_2D_COPY_RECT_LIST_V2 = 18,
+ DI_PT_2D_COPY_RECT_LIST_V3 = 19,
+ DI_PT_2D_FILL_RECT_LIST = 20,
+ DI_PT_2D_LINE_STRIP = 21,
+ DI_PT_2D_TRI_STRIP = 22,
+} VGT_DI_PRIM_TYPE;
+#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/
+
+#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H
+#define ENUMS_VGT_DI_SOURCE_SELECT_H
+typedef enum VGT_DI_SOURCE_SELECT {
+ DI_SRC_SEL_DMA = 0,
+ DI_SRC_SEL_IMMEDIATE = 1,
+ DI_SRC_SEL_AUTO_INDEX = 2,
+ DI_SRC_SEL_RESERVED = 3
+} VGT_DI_SOURCE_SELECT;
+#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_FACENESS_CULL_SELECT_H
+#define ENUMS_VGT_DI_FACENESS_CULL_SELECT_H
+typedef enum VGT_DI_FACENESS_CULL_SELECT {
+ DI_FACE_CULL_NONE = 0,
+ DI_FACE_CULL_FETCH = 1,
+ DI_FACE_BACKFACE_CULL = 2,
+ DI_FACE_FRONTFACE_CULL = 3
+} VGT_DI_FACENESS_CULL_SELECT;
+#endif /*ENUMS_VGT_DI_FACENESS_CULL_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_INDEX_SIZE_H
+#define ENUMS_VGT_DI_INDEX_SIZE_H
+typedef enum VGT_DI_INDEX_SIZE {
+ DI_INDEX_SIZE_16_BIT = 0,
+ DI_INDEX_SIZE_32_BIT = 1
+} VGT_DI_INDEX_SIZE;
+#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/
+
+#ifndef ENUMS_VGT_DI_SMALL_INDEX_H
+#define ENUMS_VGT_DI_SMALL_INDEX_H
+typedef enum VGT_DI_SMALL_INDEX {
+ DI_USE_INDEX_SIZE = 0,
+ DI_INDEX_SIZE_8_BIT = 1
+} VGT_DI_SMALL_INDEX;
+#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/
+
+#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE {
+ DISABLE_PRE_FETCH_CULL_ENABLE = 0,
+ PRE_FETCH_CULL_ENABLE = 1
+} VGT_DI_PRE_FETCH_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+typedef enum VGT_DI_GRP_CULL_ENABLE {
+ DISABLE_GRP_CULL_ENABLE = 0,
+ GRP_CULL_ENABLE = 1
+} VGT_DI_GRP_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_EVENT_TYPE_H
+#define ENUMS_VGT_EVENT_TYPE_H
+typedef enum VGT_EVENT_TYPE {
+ VS_DEALLOC = 0,
+ PS_DEALLOC = 1,
+ VS_DONE_TS = 2,
+ PS_DONE_TS = 3,
+ CACHE_FLUSH_TS = 4,
+ CONTEXT_DONE = 5,
+ CACHE_FLUSH = 6,
+ VIZQUERY_START = 7,
+ VIZQUERY_END = 8,
+ SC_WAIT_WC = 9,
+ RST_PIX_CNT = 13,
+ RST_VTX_CNT = 14,
+ TILE_FLUSH = 15,
+ CACHE_FLUSH_AND_INV_TS_EVENT = 20,
+ ZPASS_DONE = 21,
+ CACHE_FLUSH_AND_INV_EVENT = 22,
+ PERFCOUNTER_START = 23,
+ PERFCOUNTER_STOP = 24,
+ VS_FETCH_DONE = 27,
+ FACENESS_FLUSH = 28,
+} VGT_EVENT_TYPE;
+#endif /*ENUMS_VGT_EVENT_TYPE_H*/
+
+#ifndef ENUMS_VGT_DMA_SWAP_MODE_H
+#define ENUMS_VGT_DMA_SWAP_MODE_H
+typedef enum VGT_DMA_SWAP_MODE {
+ VGT_DMA_SWAP_NONE = 0,
+ VGT_DMA_SWAP_16_BIT = 1,
+ VGT_DMA_SWAP_32_BIT = 2,
+ VGT_DMA_SWAP_WORD = 3
+} VGT_DMA_SWAP_MODE;
+#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/
+
+#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H
+#define ENUMS_VGT_PERFCOUNT_SELECT_H
+typedef enum VGT_PERFCOUNT_SELECT {
+ VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
+ VGT_SQ_SEND = 1,
+ VGT_SQ_STALLED = 2,
+ VGT_SQ_STARVED_BUSY = 3,
+ VGT_SQ_STARVED_IDLE = 4,
+ VGT_SQ_STATIC = 5,
+ VGT_PA_EVENT_WINDOW_ACTIVE = 6,
+ VGT_PA_CLIP_V_SEND = 7,
+ VGT_PA_CLIP_V_STALLED = 8,
+ VGT_PA_CLIP_V_STARVED_BUSY = 9,
+ VGT_PA_CLIP_V_STARVED_IDLE = 10,
+ VGT_PA_CLIP_V_STATIC = 11,
+ VGT_PA_CLIP_P_SEND = 12,
+ VGT_PA_CLIP_P_STALLED = 13,
+ VGT_PA_CLIP_P_STARVED_BUSY = 14,
+ VGT_PA_CLIP_P_STARVED_IDLE = 15,
+ VGT_PA_CLIP_P_STATIC = 16,
+ VGT_PA_CLIP_S_SEND = 17,
+ VGT_PA_CLIP_S_STALLED = 18,
+ VGT_PA_CLIP_S_STARVED_BUSY = 19,
+ VGT_PA_CLIP_S_STARVED_IDLE = 20,
+ VGT_PA_CLIP_S_STATIC = 21,
+ RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
+ RBIU_IMMED_DATA_FIFO_STARVED = 23,
+ RBIU_IMMED_DATA_FIFO_STALLED = 24,
+ RBIU_DMA_REQUEST_FIFO_STARVED = 25,
+ RBIU_DMA_REQUEST_FIFO_STALLED = 26,
+ RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
+ RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
+ BIN_PRIM_NEAR_CULL = 29,
+ BIN_PRIM_ZERO_CULL = 30,
+ BIN_PRIM_FAR_CULL = 31,
+ BIN_PRIM_BIN_CULL = 32,
+ BIN_PRIM_FACE_CULL = 33,
+ SPARE34 = 34,
+ SPARE35 = 35,
+ SPARE36 = 36,
+ SPARE37 = 37,
+ SPARE38 = 38,
+ SPARE39 = 39,
+ TE_SU_IN_VALID = 40,
+ TE_SU_IN_READ = 41,
+ TE_SU_IN_PRIM = 42,
+ TE_SU_IN_EOP = 43,
+ TE_SU_IN_NULL_PRIM = 44,
+ TE_WK_IN_VALID = 45,
+ TE_WK_IN_READ = 46,
+ TE_OUT_PRIM_VALID = 47,
+ TE_OUT_PRIM_READ = 48,
+} VGT_PERFCOUNT_SELECT;
+#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H
+#define ENUMS_TCR_PERFCOUNT_SELECT_H
+typedef enum TCR_PERFCOUNT_SELECT {
+ DGMMPD_IPMUX0_STALL = 0,
+ reserved_46 = 1,
+ reserved_47 = 2,
+ reserved_48 = 3,
+ DGMMPD_IPMUX_ALL_STALL = 4,
+ OPMUX0_L2_WRITES = 5,
+ reserved_49 = 6,
+ reserved_50 = 7,
+ reserved_51 = 8,
+} TCR_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TP_PERFCOUNT_SELECT_H
+#define ENUMS_TP_PERFCOUNT_SELECT_H
+typedef enum TP_PERFCOUNT_SELECT {
+ POINT_QUADS = 0,
+ BILIN_QUADS = 1,
+ ANISO_QUADS = 2,
+ MIP_QUADS = 3,
+ VOL_QUADS = 4,
+ MIP_VOL_QUADS = 5,
+ MIP_ANISO_QUADS = 6,
+ VOL_ANISO_QUADS = 7,
+ ANISO_2_1_QUADS = 8,
+ ANISO_4_1_QUADS = 9,
+ ANISO_6_1_QUADS = 10,
+ ANISO_8_1_QUADS = 11,
+ ANISO_10_1_QUADS = 12,
+ ANISO_12_1_QUADS = 13,
+ ANISO_14_1_QUADS = 14,
+ ANISO_16_1_QUADS = 15,
+ MIP_VOL_ANISO_QUADS = 16,
+ ALIGN_2_QUADS = 17,
+ ALIGN_4_QUADS = 18,
+ PIX_0_QUAD = 19,
+ PIX_1_QUAD = 20,
+ PIX_2_QUAD = 21,
+ PIX_3_QUAD = 22,
+ PIX_4_QUAD = 23,
+ TP_MIPMAP_LOD0 = 24,
+ TP_MIPMAP_LOD1 = 25,
+ TP_MIPMAP_LOD2 = 26,
+ TP_MIPMAP_LOD3 = 27,
+ TP_MIPMAP_LOD4 = 28,
+ TP_MIPMAP_LOD5 = 29,
+ TP_MIPMAP_LOD6 = 30,
+ TP_MIPMAP_LOD7 = 31,
+ TP_MIPMAP_LOD8 = 32,
+ TP_MIPMAP_LOD9 = 33,
+ TP_MIPMAP_LOD10 = 34,
+ TP_MIPMAP_LOD11 = 35,
+ TP_MIPMAP_LOD12 = 36,
+ TP_MIPMAP_LOD13 = 37,
+ TP_MIPMAP_LOD14 = 38,
+} TP_PERFCOUNT_SELECT;
+#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H
+#define ENUMS_TCM_PERFCOUNT_SELECT_H
+typedef enum TCM_PERFCOUNT_SELECT {
+ QUAD0_RD_LAT_FIFO_EMPTY = 0,
+ reserved_01 = 1,
+ reserved_02 = 2,
+ QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
+ QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
+ QUAD0_RD_LAT_FIFO_FULL = 5,
+ QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
+ reserved_07 = 7,
+ reserved_08 = 8,
+ reserved_09 = 9,
+ reserved_10 = 10,
+ reserved_11 = 11,
+ reserved_12 = 12,
+ reserved_13 = 13,
+ reserved_14 = 14,
+ reserved_15 = 15,
+ reserved_16 = 16,
+ reserved_17 = 17,
+ reserved_18 = 18,
+ reserved_19 = 19,
+ reserved_20 = 20,
+ reserved_21 = 21,
+ reserved_22 = 22,
+ reserved_23 = 23,
+ reserved_24 = 24,
+ reserved_25 = 25,
+ reserved_26 = 26,
+ reserved_27 = 27,
+ READ_STARVED_QUAD0 = 28,
+ reserved_29 = 29,
+ reserved_30 = 30,
+ reserved_31 = 31,
+ READ_STARVED = 32,
+ READ_STALLED_QUAD0 = 33,
+ reserved_34 = 34,
+ reserved_35 = 35,
+ reserved_36 = 36,
+ READ_STALLED = 37,
+ VALID_READ_QUAD0 = 38,
+ reserved_39 = 39,
+ reserved_40 = 40,
+ reserved_41 = 41,
+ TC_TP_STARVED_QUAD0 = 42,
+ reserved_43 = 43,
+ reserved_44 = 44,
+ reserved_45 = 45,
+ TC_TP_STARVED = 46,
+} TCM_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H
+#define ENUMS_TCF_PERFCOUNT_SELECT_H
+typedef enum TCF_PERFCOUNT_SELECT {
+ VALID_CYCLES = 0,
+ SINGLE_PHASES = 1,
+ ANISO_PHASES = 2,
+ MIP_PHASES = 3,
+ VOL_PHASES = 4,
+ MIP_VOL_PHASES = 5,
+ MIP_ANISO_PHASES = 6,
+ VOL_ANISO_PHASES = 7,
+ ANISO_2_1_PHASES = 8,
+ ANISO_4_1_PHASES = 9,
+ ANISO_6_1_PHASES = 10,
+ ANISO_8_1_PHASES = 11,
+ ANISO_10_1_PHASES = 12,
+ ANISO_12_1_PHASES = 13,
+ ANISO_14_1_PHASES = 14,
+ ANISO_16_1_PHASES = 15,
+ MIP_VOL_ANISO_PHASES = 16,
+ ALIGN_2_PHASES = 17,
+ ALIGN_4_PHASES = 18,
+ TPC_BUSY = 19,
+ TPC_STALLED = 20,
+ TPC_STARVED = 21,
+ TPC_WORKING = 22,
+ TPC_WALKER_BUSY = 23,
+ TPC_WALKER_STALLED = 24,
+ TPC_WALKER_WORKING = 25,
+ TPC_ALIGNER_BUSY = 26,
+ TPC_ALIGNER_STALLED = 27,
+ TPC_ALIGNER_STALLED_BY_BLEND = 28,
+ TPC_ALIGNER_STALLED_BY_CACHE = 29,
+ TPC_ALIGNER_WORKING = 30,
+ TPC_BLEND_BUSY = 31,
+ TPC_BLEND_SYNC = 32,
+ TPC_BLEND_STARVED = 33,
+ TPC_BLEND_WORKING = 34,
+ OPCODE_0x00 = 35,
+ OPCODE_0x01 = 36,
+ OPCODE_0x04 = 37,
+ OPCODE_0x10 = 38,
+ OPCODE_0x11 = 39,
+ OPCODE_0x12 = 40,
+ OPCODE_0x13 = 41,
+ OPCODE_0x18 = 42,
+ OPCODE_0x19 = 43,
+ OPCODE_0x1A = 44,
+ OPCODE_OTHER = 45,
+ IN_FIFO_0_EMPTY = 56,
+ IN_FIFO_0_LT_HALF_FULL = 57,
+ IN_FIFO_0_HALF_FULL = 58,
+ IN_FIFO_0_FULL = 59,
+ IN_FIFO_TPC_EMPTY = 72,
+ IN_FIFO_TPC_LT_HALF_FULL = 73,
+ IN_FIFO_TPC_HALF_FULL = 74,
+ IN_FIFO_TPC_FULL = 75,
+ TPC_TC_XFC = 76,
+ TPC_TC_STATE = 77,
+ TC_STALL = 78,
+ QUAD0_TAPS = 79,
+ QUADS = 83,
+ TCA_SYNC_STALL = 84,
+ TAG_STALL = 85,
+ TCB_SYNC_STALL = 88,
+ TCA_VALID = 89,
+ PROBES_VALID = 90,
+ MISS_STALL = 91,
+ FETCH_FIFO_STALL = 92,
+ TCO_STALL = 93,
+ ANY_STALL = 94,
+ TAG_MISSES = 95,
+ TAG_HITS = 96,
+ SUB_TAG_MISSES = 97,
+ SET0_INVALIDATES = 98,
+ SET1_INVALIDATES = 99,
+ SET2_INVALIDATES = 100,
+ SET3_INVALIDATES = 101,
+ SET0_TAG_MISSES = 102,
+ SET1_TAG_MISSES = 103,
+ SET2_TAG_MISSES = 104,
+ SET3_TAG_MISSES = 105,
+ SET0_TAG_HITS = 106,
+ SET1_TAG_HITS = 107,
+ SET2_TAG_HITS = 108,
+ SET3_TAG_HITS = 109,
+ SET0_SUB_TAG_MISSES = 110,
+ SET1_SUB_TAG_MISSES = 111,
+ SET2_SUB_TAG_MISSES = 112,
+ SET3_SUB_TAG_MISSES = 113,
+ SET0_EVICT1 = 114,
+ SET0_EVICT2 = 115,
+ SET0_EVICT3 = 116,
+ SET0_EVICT4 = 117,
+ SET0_EVICT5 = 118,
+ SET0_EVICT6 = 119,
+ SET0_EVICT7 = 120,
+ SET0_EVICT8 = 121,
+ SET1_EVICT1 = 130,
+ SET1_EVICT2 = 131,
+ SET1_EVICT3 = 132,
+ SET1_EVICT4 = 133,
+ SET1_EVICT5 = 134,
+ SET1_EVICT6 = 135,
+ SET1_EVICT7 = 136,
+ SET1_EVICT8 = 137,
+ SET2_EVICT1 = 146,
+ SET2_EVICT2 = 147,
+ SET2_EVICT3 = 148,
+ SET2_EVICT4 = 149,
+ SET2_EVICT5 = 150,
+ SET2_EVICT6 = 151,
+ SET2_EVICT7 = 152,
+ SET2_EVICT8 = 153,
+ SET3_EVICT1 = 162,
+ SET3_EVICT2 = 163,
+ SET3_EVICT3 = 164,
+ SET3_EVICT4 = 165,
+ SET3_EVICT5 = 166,
+ SET3_EVICT6 = 167,
+ SET3_EVICT7 = 168,
+ SET3_EVICT8 = 169,
+ FF_EMPTY = 178,
+ FF_LT_HALF_FULL = 179,
+ FF_HALF_FULL = 180,
+ FF_FULL = 181,
+ FF_XFC = 182,
+ FF_STALLED = 183,
+ FG_MASKS = 184,
+ FG_LEFT_MASKS = 185,
+ FG_LEFT_MASK_STALLED = 186,
+ FG_LEFT_NOT_DONE_STALL = 187,
+ FG_LEFT_FG_STALL = 188,
+ FG_LEFT_SECTORS = 189,
+ FG0_REQUESTS = 195,
+ FG0_STALLED = 196,
+ MEM_REQ512 = 199,
+ MEM_REQ_SENT = 200,
+ MEM_LOCAL_READ_REQ = 202,
+ TC0_MH_STALLED = 203,
+} TCF_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+#ifndef ENUMS_SQ_PERFCNT_SELECT_H
+#define ENUMS_SQ_PERFCNT_SELECT_H
+typedef enum SQ_PERFCNT_SELECT {
+ SQ_PIXEL_VECTORS_SUB = 0,
+ SQ_VERTEX_VECTORS_SUB = 1,
+ SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
+ SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
+ SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
+ SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
+ SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
+ SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
+ SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
+ SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
+ SQ_EXPORT_CYCLES = 10,
+ SQ_ALU_CST_WRITTEN = 11,
+ SQ_TEX_CST_WRITTEN = 12,
+ SQ_ALU_CST_STALL = 13,
+ SQ_ALU_TEX_STALL = 14,
+ SQ_INST_WRITTEN = 15,
+ SQ_BOOLEAN_WRITTEN = 16,
+ SQ_LOOPS_WRITTEN = 17,
+ SQ_PIXEL_SWAP_IN = 18,
+ SQ_PIXEL_SWAP_OUT = 19,
+ SQ_VERTEX_SWAP_IN = 20,
+ SQ_VERTEX_SWAP_OUT = 21,
+ SQ_ALU_VTX_INST_ISSUED = 22,
+ SQ_TEX_VTX_INST_ISSUED = 23,
+ SQ_VC_VTX_INST_ISSUED = 24,
+ SQ_CF_VTX_INST_ISSUED = 25,
+ SQ_ALU_PIX_INST_ISSUED = 26,
+ SQ_TEX_PIX_INST_ISSUED = 27,
+ SQ_VC_PIX_INST_ISSUED = 28,
+ SQ_CF_PIX_INST_ISSUED = 29,
+ SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
+ SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
+ SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
+ SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
+ SQ_ALU_NOPS = 34,
+ SQ_PRED_SKIP = 35,
+ SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
+ SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
+ SQ_SYNC_TEX_STALL_VTX = 38,
+ SQ_SYNC_VC_STALL_VTX = 39,
+ SQ_CONSTANTS_USED_SIMD0 = 40,
+ SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
+ SQ_GPR_STALL_VTX = 42,
+ SQ_GPR_STALL_PIX = 43,
+ SQ_VTX_RS_STALL = 44,
+ SQ_PIX_RS_STALL = 45,
+ SQ_SX_PC_FULL   = 46,
+ SQ_SX_EXP_BUFF_FULL = 47,
+ SQ_SX_POS_BUFF_FULL = 48,
+ SQ_INTERP_QUADS = 49,
+ SQ_INTERP_ACTIVE = 50,
+ SQ_IN_PIXEL_STALL = 51,
+ SQ_IN_VTX_STALL = 52,
+ SQ_VTX_CNT = 53,
+ SQ_VTX_VECTOR2 = 54,
+ SQ_VTX_VECTOR3 = 55,
+ SQ_VTX_VECTOR4 = 56,
+ SQ_PIXEL_VECTOR1 = 57,
+ SQ_PIXEL_VECTOR23 = 58,
+ SQ_PIXEL_VECTOR4 = 59,
+ SQ_CONSTANTS_USED_SIMD1 = 60,
+ SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
+ SQ_SX_MEM_EXP_FULL = 62,
+ SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
+ SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
+ SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
+ SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
+ SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
+ SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68,
+ SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
+ SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70,
+ SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
+ SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
+ SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
+ SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
+ SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
+ SQ_PERFCOUNT_VTX_POP_THREAD = 76,
+ SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
+ SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
+ SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
+ SQ_PERFCOUNT_PIX_POP_THREAD = 80,
+ SQ_SYNC_TEX_STALL_PIX = 81,
+ SQ_SYNC_VC_STALL_PIX = 82,
+ SQ_CONSTANTS_USED_SIMD2 = 83,
+ SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
+ SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85,
+ SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86,
+ SQ_ALU0_FIFO_FULL_SIMD0 = 87,
+ SQ_ALU1_FIFO_FULL_SIMD0 = 88,
+ SQ_ALU0_FIFO_FULL_SIMD1 = 89,
+ SQ_ALU1_FIFO_FULL_SIMD1 = 90,
+ SQ_ALU0_FIFO_FULL_SIMD2 = 91,
+ SQ_ALU1_FIFO_FULL_SIMD2 = 92,
+ SQ_ALU0_FIFO_FULL_SIMD3 = 93,
+ SQ_ALU1_FIFO_FULL_SIMD3 = 94,
+ VC_PERF_STATIC = 95,
+ VC_PERF_STALLED = 96,
+ VC_PERF_STARVED = 97,
+ VC_PERF_SEND = 98,
+ VC_PERF_ACTUAL_STARVED = 99,
+ PIXEL_THREAD_0_ACTIVE   = 100,
+ VERTEX_THREAD_0_ACTIVE  = 101,
+ PIXEL_THREAD_0_NUMBER   = 102,
+ VERTEX_THREAD_0_NUMBER  = 103,
+ VERTEX_EVENT_NUMBER     = 104,
+ PIXEL_EVENT_NUMBER  = 105,
+ PTRBUFF_EF_PUSH = 106,
+ PTRBUFF_EF_POP_EVENT = 107,
+ PTRBUFF_EF_POP_NEW_VTX = 108,
+ PTRBUFF_EF_POP_DEALLOC = 109,
+ PTRBUFF_EF_POP_PVECTOR = 110,
+ PTRBUFF_EF_POP_PVECTOR_X = 111,
+ PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
+ PTRBUFF_PB_DEALLOC = 113,
+ PTRBUFF_PI_STATE_PPB_POP = 114,
+ PTRBUFF_PI_RTR = 115,
+ PTRBUFF_PI_READ_EN = 116,
+ PTRBUFF_PI_BUFF_SWAP = 117,
+ PTRBUFF_SQ_FREE_BUFF = 118,
+ PTRBUFF_SQ_DEC = 119,
+ PTRBUFF_SC_VALID_CNTL_EVENT = 120,
+ PTRBUFF_SC_VALID_IJ_XFER = 121,
+ PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
+ PTRBUFF_QUAL_NEW_VECTOR = 123,
+ PTRBUFF_QUAL_EVENT = 124,
+ PTRBUFF_END_BUFFER = 125,
+ PTRBUFF_FILL_QUAD = 126,
+ VERTS_WRITTEN_SPI = 127,
+ TP_FETCH_INSTR_EXEC = 128,
+ TP_FETCH_INSTR_REQ = 129,
+ TP_DATA_RETURN = 130,
+ SPI_WRITE_CYCLES_SP = 131,
+ SPI_WRITES_SP = 132,
+ SP_ALU_INSTR_EXEC = 133,
+ SP_CONST_ADDR_TO_SQ = 134,
+ SP_PRED_KILLS_TO_SQ = 135,
+ SP_EXPORT_CYCLES_TO_SX = 136,
+ SP_EXPORTS_TO_SX = 137,
+ SQ_CYCLES_ELAPSED = 138,
+ SQ_TCFS_OPT_ALLOC_EXEC = 139,
+ SQ_TCFS_NO_OPT_ALLOC = 140,
+ SQ_ALU0_NO_OPT_ALLOC = 141,
+ SQ_ALU1_NO_OPT_ALLOC = 142,
+ SQ_TCFS_ARB_XFC_CNT = 143,
+ SQ_ALU0_ARB_XFC_CNT = 144,
+ SQ_ALU1_ARB_XFC_CNT = 145,
+ SQ_TCFS_CFS_UPDATE_CNT = 146,
+ SQ_ALU0_CFS_UPDATE_CNT = 147,
+ SQ_ALU1_CFS_UPDATE_CNT = 148,
+ SQ_VTX_PUSH_THREAD_CNT = 149,
+ SQ_VTX_POP_THREAD_CNT = 150,
+ SQ_PIX_PUSH_THREAD_CNT = 151,
+ SQ_PIX_POP_THREAD_CNT = 152,
+ SQ_PIX_TOTAL = 153,
+ SQ_PIX_KILLED = 154,
+} SQ_PERFCNT_SELECT;
+#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SX_PERFCNT_SELECT_H
+#define ENUMS_SX_PERFCNT_SELECT_H
+typedef enum SX_PERFCNT_SELECT {
+ SX_EXPORT_VECTORS = 0,
+ SX_DUMMY_QUADS  = 1,
+ SX_ALPHA_FAIL = 2,
+ SX_RB_QUAD_BUSY = 3,
+ SX_RB_COLOR_BUSY = 4,
+ SX_RB_QUAD_STALL = 5,
+ SX_RB_COLOR_STALL = 6,
+} SX_PERFCNT_SELECT;
+#endif /*ENUMS_SX_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_Abs_modifier_H
+#define ENUMS_Abs_modifier_H
+typedef enum Abs_modifier {
+ NO_ABS_MOD = 0,
+ ABS_MOD = 1
+} Abs_modifier;
+#endif /*ENUMS_Abs_modifier_H*/
+
+#ifndef ENUMS_Exporting_H
+#define ENUMS_Exporting_H
+typedef enum Exporting {
+ NOT_EXPORTING = 0,
+ EXPORTING = 1
+} Exporting;
+#endif /*ENUMS_Exporting_H*/
+
+#ifndef ENUMS_ScalarOpcode_H
+#define ENUMS_ScalarOpcode_H
+typedef enum ScalarOpcode {
+ ADDs = 0,
+ ADD_PREVs = 1,
+ MULs = 2,
+ MUL_PREVs = 3,
+ MUL_PREV2s = 4,
+ MAXs = 5,
+ MINs = 6,
+ SETEs = 7,
+ SETGTs = 8,
+ SETGTEs = 9,
+ SETNEs = 10,
+ FRACs = 11,
+ TRUNCs = 12,
+ FLOORs = 13,
+ EXP_IEEE = 14,
+ LOG_CLAMP = 15,
+ LOG_IEEE = 16,
+ RECIP_CLAMP = 17,
+ RECIP_FF = 18,
+ RECIP_IEEE = 19,
+ RECIPSQ_CLAMP = 20,
+ RECIPSQ_FF = 21,
+ RECIPSQ_IEEE = 22,
+ MOVAs = 23,
+ MOVA_FLOORs = 24,
+ SUBs = 25,
+ SUB_PREVs = 26,
+ PRED_SETEs = 27,
+ PRED_SETNEs = 28,
+ PRED_SETGTs = 29,
+ PRED_SETGTEs = 30,
+ PRED_SET_INVs = 31,
+ PRED_SET_POPs = 32,
+ PRED_SET_CLRs = 33,
+ PRED_SET_RESTOREs = 34,
+ KILLEs = 35,
+ KILLGTs = 36,
+ KILLGTEs = 37,
+ KILLNEs = 38,
+ KILLONEs = 39,
+ SQRT_IEEE = 40,
+ MUL_CONST_0 = 42,
+ MUL_CONST_1 = 43,
+ ADD_CONST_0 = 44,
+ ADD_CONST_1 = 45,
+ SUB_CONST_0 = 46,
+ SUB_CONST_1 = 47,
+ SIN = 48,
+ COS = 49,
+ RETAIN_PREV = 50,
+} ScalarOpcode;
+#endif /*ENUMS_ScalarOpcode_H*/
+
+#ifndef ENUMS_SwizzleType_H
+#define ENUMS_SwizzleType_H
+typedef enum SwizzleType {
+ NO_SWIZZLE = 0,
+ SHIFT_RIGHT_1 = 1,
+ SHIFT_RIGHT_2 = 2,
+ SHIFT_RIGHT_3 = 3
+} SwizzleType;
+#endif /*ENUMS_SwizzleType_H*/
+
+#ifndef ENUMS_InputModifier_H
+#define ENUMS_InputModifier_H
+typedef enum InputModifier {
+ NIL = 0,
+ NEGATE = 1
+} InputModifier;
+#endif /*ENUMS_InputModifier_H*/
+
+#ifndef ENUMS_PredicateSelect_H
+#define ENUMS_PredicateSelect_H
+typedef enum PredicateSelect {
+ NO_PREDICATION = 0,
+ PREDICATE_QUAD = 1,
+ PREDICATED_2 = 2,
+ PREDICATED_3 = 3
+} PredicateSelect;
+#endif /*ENUMS_PredicateSelect_H*/
+
+#ifndef ENUMS_OperandSelect1_H
+#define ENUMS_OperandSelect1_H
+typedef enum OperandSelect1 {
+ ABSOLUTE_REG = 0,
+ RELATIVE_REG = 1
+} OperandSelect1;
+#endif /*ENUMS_OperandSelect1_H*/
+
+#ifndef ENUMS_VectorOpcode_H
+#define ENUMS_VectorOpcode_H
+typedef enum VectorOpcode {
+ ADDv = 0,
+ MULv = 1,
+ MAXv = 2,
+ MINv = 3,
+ SETEv = 4,
+ SETGTv = 5,
+ SETGTEv = 6,
+ SETNEv = 7,
+ FRACv = 8,
+ TRUNCv = 9,
+ FLOORv = 10,
+ MULADDv = 11,
+ CNDEv = 12,
+ CNDGTEv = 13,
+ CNDGTv = 14,
+ DOT4v = 15,
+ DOT3v = 16,
+ DOT2ADDv = 17,
+ CUBEv = 18,
+ MAX4v = 19,
+ PRED_SETE_PUSHv = 20,
+ PRED_SETNE_PUSHv = 21,
+ PRED_SETGT_PUSHv = 22,
+ PRED_SETGTE_PUSHv = 23,
+ KILLEv = 24,
+ KILLGTv = 25,
+ KILLGTEv = 26,
+ KILLNEv = 27,
+ DSTv = 28,
+ MOVAv = 29,
+} VectorOpcode;
+#endif /*ENUMS_VectorOpcode_H*/
+
+#ifndef ENUMS_OperandSelect0_H
+#define ENUMS_OperandSelect0_H
+typedef enum OperandSelect0 {
+ CONSTANT = 0,
+ NON_CONSTANT = 1
+} OperandSelect0;
+#endif /*ENUMS_OperandSelect0_H*/
+
+#ifndef ENUMS_Ressource_type_H
+#define ENUMS_Ressource_type_H
+typedef enum Ressource_type {
+ ALU = 0,
+ TEXTURE = 1
+} Ressource_type;
+#endif /*ENUMS_Ressource_type_H*/
+
+#ifndef ENUMS_Instruction_serial_H
+#define ENUMS_Instruction_serial_H
+typedef enum Instruction_serial {
+ NOT_SERIAL = 0,
+ SERIAL = 1
+} Instruction_serial;
+#endif /*ENUMS_Instruction_serial_H*/
+
+#ifndef ENUMS_VC_type_H
+#define ENUMS_VC_type_H
+typedef enum VC_type {
+ ALU_TP_REQUEST = 0,
+ VC_REQUEST = 1
+} VC_type;
+#endif /*ENUMS_VC_type_H*/
+
+#ifndef ENUMS_Addressing_H
+#define ENUMS_Addressing_H
+typedef enum Addressing {
+ RELATIVE_ADDR = 0,
+ ABSOLUTE_ADDR = 1
+} Addressing;
+#endif /*ENUMS_Addressing_H*/
+
+#ifndef ENUMS_CFOpcode_H
+#define ENUMS_CFOpcode_H
+typedef enum CFOpcode {
+ NOP = 0,
+ EXECUTE = 1,
+ EXECUTE_END = 2,
+ COND_EXECUTE = 3,
+ COND_EXECUTE_END = 4,
+ COND_PRED_EXECUTE = 5,
+ COND_PRED_EXECUTE_END = 6,
+ LOOP_START = 7,
+ LOOP_END = 8,
+ COND_CALL = 9,
+ RETURN = 10,
+ COND_JMP = 11,
+ ALLOCATE = 12,
+ COND_EXECUTE_PRED_CLEAN = 13,
+ COND_EXECUTE_PRED_CLEAN_END = 14,
+ MARK_VS_FETCH_DONE = 15
+} CFOpcode;
+#endif /*ENUMS_CFOpcode_H*/
+
+#ifndef ENUMS_Allocation_type_H
+#define ENUMS_Allocation_type_H
+typedef enum Allocation_type {
+ SQ_NO_ALLOC = 0,
+ SQ_POSITION = 1,
+ SQ_PARAMETER_PIXEL = 2,
+ SQ_MEMORY = 3
+} Allocation_type;
+#endif /*ENUMS_Allocation_type_H*/
+
+#ifndef ENUMS_TexInstOpcode_H
+#define ENUMS_TexInstOpcode_H
+typedef enum TexInstOpcode {
+ TEX_INST_FETCH = 1,
+ TEX_INST_RESERVED_1 = 2,
+ TEX_INST_RESERVED_2 = 3,
+ TEX_INST_RESERVED_3 = 4,
+ TEX_INST_GET_BORDER_COLOR_FRAC = 16,
+ TEX_INST_GET_COMP_TEX_LOD = 17,
+ TEX_INST_GET_GRADIENTS = 18,
+ TEX_INST_GET_WEIGHTS = 19,
+ TEX_INST_SET_TEX_LOD = 24,
+ TEX_INST_SET_GRADIENTS_H = 25,
+ TEX_INST_SET_GRADIENTS_V = 26,
+ TEX_INST_RESERVED_4 = 27,
+} TexInstOpcode;
+#endif /*ENUMS_TexInstOpcode_H*/
+
+#ifndef ENUMS_Addressmode_H
+#define ENUMS_Addressmode_H
+typedef enum Addressmode {
+ LOGICAL = 0,
+ LOOP_RELATIVE = 1
+} Addressmode;
+#endif /*ENUMS_Addressmode_H*/
+
+#ifndef ENUMS_TexCoordDenorm_H
+#define ENUMS_TexCoordDenorm_H
+typedef enum TexCoordDenorm {
+ TEX_COORD_NORMALIZED = 0,
+ TEX_COORD_UNNORMALIZED = 1
+} TexCoordDenorm;
+#endif /*ENUMS_TexCoordDenorm_H*/
+
+#ifndef ENUMS_SrcSel_H
+#define ENUMS_SrcSel_H
+typedef enum SrcSel {
+ SRC_SEL_X = 0,
+ SRC_SEL_Y = 1,
+ SRC_SEL_Z = 2,
+ SRC_SEL_W = 3
+} SrcSel;
+#endif /*ENUMS_SrcSel_H*/
+
+#ifndef ENUMS_DstSel_H
+#define ENUMS_DstSel_H
+typedef enum DstSel {
+ DST_SEL_X = 0,
+ DST_SEL_Y = 1,
+ DST_SEL_Z = 2,
+ DST_SEL_W = 3,
+ DST_SEL_0 = 4,
+ DST_SEL_1 = 5,
+ DST_SEL_RSVD = 6,
+ DST_SEL_MASK = 7
+} DstSel;
+#endif /*ENUMS_DstSel_H*/
+
+#ifndef ENUMS_MagFilter_H
+#define ENUMS_MagFilter_H
+typedef enum MagFilter {
+ MAG_FILTER_POINT = 0,
+ MAG_FILTER_LINEAR = 1,
+ MAG_FILTER_RESERVED_0 = 2,
+ MAG_FILTER_USE_FETCH_CONST = 3
+} MagFilter;
+#endif /*ENUMS_MagFilter_H*/
+
+#ifndef ENUMS_MinFilter_H
+#define ENUMS_MinFilter_H
+typedef enum MinFilter {
+ MIN_FILTER_POINT = 0,
+ MIN_FILTER_LINEAR = 1,
+ MIN_FILTER_RESERVED_0 = 2,
+ MIN_FILTER_USE_FETCH_CONST = 3
+} MinFilter;
+#endif /*ENUMS_MinFilter_H*/
+
+#ifndef ENUMS_MipFilter_H
+#define ENUMS_MipFilter_H
+typedef enum MipFilter {
+ MIP_FILTER_POINT = 0,
+ MIP_FILTER_LINEAR = 1,
+ MIP_FILTER_BASEMAP = 2,
+ MIP_FILTER_USE_FETCH_CONST = 3
+} MipFilter;
+#endif /*ENUMS_MipFilter_H*/
+
+#ifndef ENUMS_AnisoFilter_H
+#define ENUMS_AnisoFilter_H
+typedef enum AnisoFilter {
+ ANISO_FILTER_DISABLED = 0,
+ ANISO_FILTER_MAX_1_1 = 1,
+ ANISO_FILTER_MAX_2_1 = 2,
+ ANISO_FILTER_MAX_4_1 = 3,
+ ANISO_FILTER_MAX_8_1 = 4,
+ ANISO_FILTER_MAX_16_1 = 5,
+ ANISO_FILTER_USE_FETCH_CONST = 7
+} AnisoFilter;
+#endif /*ENUMS_AnisoFilter_H*/
+
+#ifndef ENUMS_ArbitraryFilter_H
+#define ENUMS_ArbitraryFilter_H
+typedef enum ArbitraryFilter {
+ ARBITRARY_FILTER_2X4_SYM = 0,
+ ARBITRARY_FILTER_2X4_ASYM = 1,
+ ARBITRARY_FILTER_4X2_SYM = 2,
+ ARBITRARY_FILTER_4X2_ASYM = 3,
+ ARBITRARY_FILTER_4X4_SYM = 4,
+ ARBITRARY_FILTER_4X4_ASYM = 5,
+ ARBITRARY_FILTER_USE_FETCH_CONST = 7
+} ArbitraryFilter;
+#endif /*ENUMS_ArbitraryFilter_H*/
+
+#ifndef ENUMS_VolMagFilter_H
+#define ENUMS_VolMagFilter_H
+typedef enum VolMagFilter {
+ VOL_MAG_FILTER_POINT = 0,
+ VOL_MAG_FILTER_LINEAR = 1,
+ VOL_MAG_FILTER_USE_FETCH_CONST = 3
+} VolMagFilter;
+#endif /*ENUMS_VolMagFilter_H*/
+
+#ifndef ENUMS_VolMinFilter_H
+#define ENUMS_VolMinFilter_H
+typedef enum VolMinFilter {
+ VOL_MIN_FILTER_POINT = 0,
+ VOL_MIN_FILTER_LINEAR = 1,
+ VOL_MIN_FILTER_USE_FETCH_CONST = 3
+} VolMinFilter;
+#endif /*ENUMS_VolMinFilter_H*/
+
+#ifndef ENUMS_PredSelect_H
+#define ENUMS_PredSelect_H
+typedef enum PredSelect {
+ NOT_PREDICATED = 0,
+ PREDICATED = 1
+} PredSelect;
+#endif /*ENUMS_PredSelect_H*/
+
+#ifndef ENUMS_SampleLocation_H
+#define ENUMS_SampleLocation_H
+typedef enum SampleLocation {
+ SAMPLE_CENTROID = 0,
+ SAMPLE_CENTER = 1
+} SampleLocation;
+#endif /*ENUMS_SampleLocation_H*/
+
+#ifndef ENUMS_VertexMode_H
+#define ENUMS_VertexMode_H
+typedef enum VertexMode {
+ POSITION_1_VECTOR = 0,
+ POSITION_2_VECTORS_UNUSED = 1,
+ POSITION_2_VECTORS_SPRITE = 2,
+ POSITION_2_VECTORS_EDGE = 3,
+ POSITION_2_VECTORS_KILL = 4,
+ POSITION_2_VECTORS_SPRITE_KILL = 5,
+ POSITION_2_VECTORS_EDGE_KILL = 6,
+ MULTIPASS = 7
+} VertexMode;
+#endif /*ENUMS_VertexMode_H*/
+
+#ifndef ENUMS_Sample_Cntl_H
+#define ENUMS_Sample_Cntl_H
+typedef enum Sample_Cntl {
+ CENTROIDS_ONLY = 0,
+ CENTERS_ONLY = 1,
+ CENTROIDS_AND_CENTERS = 2,
+ UNDEF = 3
+} Sample_Cntl;
+#endif /*ENUMS_Sample_Cntl_H*/
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+#ifndef ENUMS_MhPerfEncode_H
+#define ENUMS_MhPerfEncode_H
+typedef enum MhPerfEncode {
+ CP_R0_REQUESTS = 0,
+ CP_R1_REQUESTS = 1,
+ CP_R2_REQUESTS = 2,
+ CP_R3_REQUESTS = 3,
+ CP_R4_REQUESTS = 4,
+ CP_TOTAL_READ_REQUESTS = 5,
+ CP_TOTAL_WRITE_REQUESTS = 6,
+ CP_TOTAL_REQUESTS = 7,
+ CP_DATA_BYTES_WRITTEN = 8,
+ CP_WRITE_CLEAN_RESPONSES = 9,
+ CP_R0_READ_BURSTS_RECEIVED = 10,
+ CP_R1_READ_BURSTS_RECEIVED = 11,
+ CP_R2_READ_BURSTS_RECEIVED = 12,
+ CP_R3_READ_BURSTS_RECEIVED = 13,
+ CP_R4_READ_BURSTS_RECEIVED = 14,
+ CP_TOTAL_READ_BURSTS_RECEIVED = 15,
+ CP_R0_DATA_BEATS_READ = 16,
+ CP_R1_DATA_BEATS_READ = 17,
+ CP_R2_DATA_BEATS_READ = 18,
+ CP_R3_DATA_BEATS_READ = 19,
+ CP_R4_DATA_BEATS_READ = 20,
+ CP_TOTAL_DATA_BEATS_READ = 21,
+ VGT_R0_REQUESTS = 22,
+ VGT_R1_REQUESTS = 23,
+ VGT_TOTAL_REQUESTS = 24,
+ VGT_R0_READ_BURSTS_RECEIVED = 25,
+ VGT_R1_READ_BURSTS_RECEIVED = 26,
+ VGT_TOTAL_READ_BURSTS_RECEIVED = 27,
+ VGT_R0_DATA_BEATS_READ = 28,
+ VGT_R1_DATA_BEATS_READ = 29,
+ VGT_TOTAL_DATA_BEATS_READ = 30,
+ TC_TOTAL_REQUESTS = 31,
+ TC_ROQ_REQUESTS = 32,
+ TC_INFO_SENT = 33,
+ TC_READ_BURSTS_RECEIVED = 34,
+ TC_DATA_BEATS_READ = 35,
+ TCD_BURSTS_READ = 36,
+ RB_REQUESTS = 37,
+ RB_DATA_BYTES_WRITTEN = 38,
+ RB_WRITE_CLEAN_RESPONSES = 39,
+ AXI_READ_REQUESTS_ID_0 = 40,
+ AXI_READ_REQUESTS_ID_1 = 41,
+ AXI_READ_REQUESTS_ID_2 = 42,
+ AXI_READ_REQUESTS_ID_3 = 43,
+ AXI_READ_REQUESTS_ID_4 = 44,
+ AXI_READ_REQUESTS_ID_5 = 45,
+ AXI_READ_REQUESTS_ID_6 = 46,
+ AXI_READ_REQUESTS_ID_7 = 47,
+ AXI_TOTAL_READ_REQUESTS = 48,
+ AXI_WRITE_REQUESTS_ID_0 = 49,
+ AXI_WRITE_REQUESTS_ID_1 = 50,
+ AXI_WRITE_REQUESTS_ID_2 = 51,
+ AXI_WRITE_REQUESTS_ID_3 = 52,
+ AXI_WRITE_REQUESTS_ID_4 = 53,
+ AXI_WRITE_REQUESTS_ID_5 = 54,
+ AXI_WRITE_REQUESTS_ID_6 = 55,
+ AXI_WRITE_REQUESTS_ID_7 = 56,
+ AXI_TOTAL_WRITE_REQUESTS = 57,
+ AXI_TOTAL_REQUESTS_ID_0 = 58,
+ AXI_TOTAL_REQUESTS_ID_1 = 59,
+ AXI_TOTAL_REQUESTS_ID_2 = 60,
+ AXI_TOTAL_REQUESTS_ID_3 = 61,
+ AXI_TOTAL_REQUESTS_ID_4 = 62,
+ AXI_TOTAL_REQUESTS_ID_5 = 63,
+ AXI_TOTAL_REQUESTS_ID_6 = 64,
+ AXI_TOTAL_REQUESTS_ID_7 = 65,
+ AXI_TOTAL_REQUESTS = 66,
+ AXI_READ_CHANNEL_BURSTS_ID_0 = 67,
+ AXI_READ_CHANNEL_BURSTS_ID_1 = 68,
+ AXI_READ_CHANNEL_BURSTS_ID_2 = 69,
+ AXI_READ_CHANNEL_BURSTS_ID_3 = 70,
+ AXI_READ_CHANNEL_BURSTS_ID_4 = 71,
+ AXI_READ_CHANNEL_BURSTS_ID_5 = 72,
+ AXI_READ_CHANNEL_BURSTS_ID_6 = 73,
+ AXI_READ_CHANNEL_BURSTS_ID_7 = 74,
+ AXI_READ_CHANNEL_TOTAL_BURSTS = 75,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83,
+ AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84,
+ AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85,
+ AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86,
+ AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87,
+ AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88,
+ AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89,
+ AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90,
+ AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91,
+ AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92,
+ AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101,
+ AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110,
+ AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111,
+ TOTAL_MMU_MISSES = 112,
+ MMU_READ_MISSES = 113,
+ MMU_WRITE_MISSES = 114,
+ TOTAL_MMU_HITS = 115,
+ MMU_READ_HITS = 116,
+ MMU_WRITE_HITS = 117,
+ SPLIT_MODE_TC_HITS = 118,
+ SPLIT_MODE_TC_MISSES = 119,
+ SPLIT_MODE_NON_TC_HITS = 120,
+ SPLIT_MODE_NON_TC_MISSES = 121,
+ STALL_AWAITING_TLB_MISS_FETCH = 122,
+ MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123,
+ MMU_TLB_MISS_DATA_BEATS_READ = 124,
+ CP_CYCLES_HELD_OFF = 125,
+ VGT_CYCLES_HELD_OFF = 126,
+ TC_CYCLES_HELD_OFF = 127,
+ TC_ROQ_CYCLES_HELD_OFF = 128,
+ TC_CYCLES_HELD_OFF_TCD_FULL = 129,
+ RB_CYCLES_HELD_OFF = 130,
+ TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131,
+ TLB_MISS_CYCLES_HELD_OFF = 132,
+ AXI_READ_REQUEST_HELD_OFF = 133,
+ AXI_WRITE_REQUEST_HELD_OFF = 134,
+ AXI_REQUEST_HELD_OFF = 135,
+ AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136,
+ AXI_WRITE_DATA_HELD_OFF = 137,
+ CP_SAME_PAGE_BANK_REQUESTS = 138,
+ VGT_SAME_PAGE_BANK_REQUESTS = 139,
+ TC_SAME_PAGE_BANK_REQUESTS = 140,
+ TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141,
+ RB_SAME_PAGE_BANK_REQUESTS = 142,
+ TOTAL_SAME_PAGE_BANK_REQUESTS = 143,
+ CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144,
+ VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145,
+ TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146,
+ RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147,
+ TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148,
+ TOTAL_MH_READ_REQUESTS = 149,
+ TOTAL_MH_WRITE_REQUESTS = 150,
+ TOTAL_MH_REQUESTS = 151,
+ MH_BUSY = 152,
+ CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153,
+ VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154,
+ TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155,
+ RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156,
+ TC_ROQ_N_VALID_ENTRIES = 157,
+ ARQ_N_ENTRIES = 158,
+ WDB_N_ENTRIES = 159,
+ MH_READ_LATENCY_OUTST_REQ_SUM = 160,
+ MC_READ_LATENCY_OUTST_REQ_SUM = 161,
+ MC_TOTAL_READ_REQUESTS = 162,
+ ELAPSED_CYCLES_MH_GATED_CLK = 163,
+ ELAPSED_CLK_CYCLES = 164,
+ CP_W_16B_REQUESTS = 165,
+ CP_W_32B_REQUESTS = 166,
+ TC_16B_REQUESTS = 167,
+ TC_32B_REQUESTS = 168,
+ PA_REQUESTS = 169,
+ PA_DATA_BYTES_WRITTEN = 170,
+ PA_WRITE_CLEAN_RESPONSES = 171,
+ PA_CYCLES_HELD_OFF = 172,
+ AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173,
+ AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174,
+ AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175,
+ AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176,
+ AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177,
+ AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178,
+ AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179,
+ AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180,
+ AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181,
+} MhPerfEncode;
+#endif /*ENUMS_MhPerfEncode_H*/
+
+#ifndef ENUMS_MmuClntBeh_H
+#define ENUMS_MmuClntBeh_H
+typedef enum MmuClntBeh {
+ BEH_NEVR = 0,
+ BEH_TRAN_RNG = 1,
+ BEH_TRAN_FLT = 2,
+} MmuClntBeh;
+#endif /*ENUMS_MmuClntBeh_H*/
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H
+#define ENUMS_RBBM_PERFCOUNT1_SEL_H
+typedef enum RBBM_PERFCOUNT1_SEL {
+ RBBM1_COUNT = 0,
+ RBBM1_NRT_BUSY = 1,
+ RBBM1_RB_BUSY = 2,
+ RBBM1_SQ_CNTX0_BUSY = 3,
+ RBBM1_SQ_CNTX17_BUSY = 4,
+ RBBM1_VGT_BUSY = 5,
+ RBBM1_VGT_NODMA_BUSY = 6,
+ RBBM1_PA_BUSY = 7,
+ RBBM1_SC_CNTX_BUSY = 8,
+ RBBM1_TPC_BUSY = 9,
+ RBBM1_TC_BUSY = 10,
+ RBBM1_SX_BUSY = 11,
+ RBBM1_CP_COHER_BUSY = 12,
+ RBBM1_CP_NRT_BUSY = 13,
+ RBBM1_GFX_IDLE_STALL = 14,
+ RBBM1_INTERRUPT = 15,
+} RBBM_PERFCOUNT1_SEL;
+#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+#ifndef ENUMS_CP_PERFCOUNT_SEL_H
+#define ENUMS_CP_PERFCOUNT_SEL_H
+typedef enum CP_PERFCOUNT_SEL {
+ ALWAYS_COUNT = 0,
+ TRANS_FIFO_FULL = 1,
+ TRANS_FIFO_AF = 2,
+ RCIU_PFPTRANS_WAIT = 3,
+ Reserved_04 = 4,
+ Reserved_05 = 5,
+ RCIU_NRTTRANS_WAIT = 6,
+ Reserved_07 = 7,
+ CSF_NRT_READ_WAIT = 8,
+ CSF_I1_FIFO_FULL = 9,
+ CSF_I2_FIFO_FULL = 10,
+ CSF_ST_FIFO_FULL = 11,
+ Reserved_12 = 12,
+ CSF_RING_ROQ_FULL = 13,
+ CSF_I1_ROQ_FULL = 14,
+ CSF_I2_ROQ_FULL = 15,
+ CSF_ST_ROQ_FULL = 16,
+ Reserved_17 = 17,
+ MIU_TAG_MEM_FULL = 18,
+ MIU_WRITECLEAN = 19,
+ Reserved_20 = 20,
+ Reserved_21 = 21,
+ MIU_NRT_WRITE_STALLED = 22,
+ MIU_NRT_READ_STALLED = 23,
+ ME_WRITE_CONFIRM_FIFO_FULL = 24,
+ ME_VS_DEALLOC_FIFO_FULL = 25,
+ ME_PS_DEALLOC_FIFO_FULL = 26,
+ ME_REGS_VS_EVENT_FIFO_FULL = 27,
+ ME_REGS_PS_EVENT_FIFO_FULL = 28,
+ ME_REGS_CF_EVENT_FIFO_FULL = 29,
+ ME_MICRO_RB_STARVED = 30,
+ ME_MICRO_I1_STARVED = 31,
+ ME_MICRO_I2_STARVED = 32,
+ ME_MICRO_ST_STARVED = 33,
+ Reserved_34 = 34,
+ Reserved_35 = 35,
+ Reserved_36 = 36,
+ Reserved_37 = 37,
+ Reserved_38 = 38,
+ Reserved_39 = 39,
+ RCIU_RBBM_DWORD_SENT = 40,
+ ME_BUSY_CLOCKS = 41,
+ ME_WAIT_CONTEXT_AVAIL = 42,
+ PFP_TYPE0_PACKET = 43,
+ PFP_TYPE3_PACKET = 44,
+ CSF_RB_WPTR_NEQ_RPTR = 45,
+ CSF_I1_SIZE_NEQ_ZERO = 46,
+ CSF_I2_SIZE_NEQ_ZERO = 47,
+ CSF_RBI1I2_FETCHING = 48,
+ Reserved_49 = 49,
+ Reserved_50 = 50,
+ Reserved_51 = 51,
+ Reserved_52 = 52,
+ Reserved_53 = 53,
+ Reserved_54 = 54,
+ Reserved_55 = 55,
+ Reserved_56 = 56,
+ Reserved_57 = 57,
+ Reserved_58 = 58,
+ Reserved_59 = 59,
+ Reserved_60 = 60,
+ Reserved_61 = 61,
+ Reserved_62 = 62,
+ Reserved_63 = 63
+} CP_PERFCOUNT_SEL;
+#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+#ifndef ENUMS_ColorformatX_H
+#define ENUMS_ColorformatX_H
+typedef enum ColorformatX {
+ COLORX_4_4_4_4 = 0,
+ COLORX_1_5_5_5 = 1,
+ COLORX_5_6_5 = 2,
+ COLORX_8 = 3,
+ COLORX_8_8 = 4,
+ COLORX_8_8_8_8 = 5,
+ COLORX_S8_8_8_8 = 6,
+ COLORX_16_FLOAT = 7,
+ COLORX_16_16_FLOAT = 8,
+ COLORX_16_16_16_16_FLOAT = 9,
+ COLORX_32_FLOAT = 10,
+ COLORX_32_32_FLOAT = 11,
+ COLORX_32_32_32_32_FLOAT = 12,
+ COLORX_2_3_3 = 13,
+ COLORX_8_8_8 = 14,
+} ColorformatX;
+#endif /*ENUMS_ColorformatX_H*/
+
+#ifndef ENUMS_DepthformatX_H
+#define ENUMS_DepthformatX_H
+typedef enum DepthformatX {
+ DEPTHX_16 = 0,
+ DEPTHX_24_8 = 1
+} DepthformatX;
+#endif /*ENUMS_DepthformatX_H*/
+
+#ifndef ENUMS_CompareFrag_H
+#define ENUMS_CompareFrag_H
+typedef enum CompareFrag {
+ FRAG_NEVER = 0,
+ FRAG_LESS = 1,
+ FRAG_EQUAL = 2,
+ FRAG_LEQUAL = 3,
+ FRAG_GREATER = 4,
+ FRAG_NOTEQUAL = 5,
+ FRAG_GEQUAL = 6,
+ FRAG_ALWAYS = 7
+} CompareFrag;
+#endif /*ENUMS_CompareFrag_H*/
+
+#ifndef ENUMS_CompareRef_H
+#define ENUMS_CompareRef_H
+typedef enum CompareRef {
+ REF_NEVER = 0,
+ REF_LESS = 1,
+ REF_EQUAL = 2,
+ REF_LEQUAL = 3,
+ REF_GREATER = 4,
+ REF_NOTEQUAL = 5,
+ REF_GEQUAL = 6,
+ REF_ALWAYS = 7
+} CompareRef;
+#endif /*ENUMS_CompareRef_H*/
+
+#ifndef ENUMS_StencilOp_H
+#define ENUMS_StencilOp_H
+typedef enum StencilOp {
+ STENCIL_KEEP = 0,
+ STENCIL_ZERO = 1,
+ STENCIL_REPLACE = 2,
+ STENCIL_INCR_CLAMP = 3,
+ STENCIL_DECR_CLAMP = 4,
+ STENCIL_INVERT = 5,
+ STENCIL_INCR_WRAP = 6,
+ STENCIL_DECR_WRAP = 7
+} StencilOp;
+#endif /*ENUMS_StencilOp_H*/
+
+#ifndef ENUMS_BlendOpX_H
+#define ENUMS_BlendOpX_H
+typedef enum BlendOpX {
+ BLENDX_ZERO = 0,
+ BLENDX_ONE = 1,
+ BLENDX_SRC_COLOR = 4,
+ BLENDX_ONE_MINUS_SRC_COLOR = 5,
+ BLENDX_SRC_ALPHA = 6,
+ BLENDX_ONE_MINUS_SRC_ALPHA = 7,
+ BLENDX_DST_COLOR = 8,
+ BLENDX_ONE_MINUS_DST_COLOR = 9,
+ BLENDX_DST_ALPHA = 10,
+ BLENDX_ONE_MINUS_DST_ALPHA = 11,
+ BLENDX_CONSTANT_COLOR = 12,
+ BLENDX_ONE_MINUS_CONSTANT_COLOR = 13,
+ BLENDX_CONSTANT_ALPHA = 14,
+ BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15,
+ BLENDX_SRC_ALPHA_SATURATE = 16,
+} BlendOpX;
+#endif /*ENUMS_BlendOpX_H*/
+
+#ifndef ENUMS_CombFuncX_H
+#define ENUMS_CombFuncX_H
+typedef enum CombFuncX {
+ COMB_DST_PLUS_SRC = 0,
+ COMB_SRC_MINUS_DST = 1,
+ COMB_MIN_DST_SRC = 2,
+ COMB_MAX_DST_SRC = 3,
+ COMB_DST_MINUS_SRC = 4,
+ COMB_DST_PLUS_SRC_BIAS = 5,
+} CombFuncX;
+#endif /*ENUMS_CombFuncX_H*/
+
+#ifndef ENUMS_DitherModeX_H
+#define ENUMS_DitherModeX_H
+typedef enum DitherModeX {
+ DITHER_DISABLE = 0,
+ DITHER_ALWAYS = 1,
+ DITHER_IF_ALPHA_OFF = 2,
+} DitherModeX;
+#endif /*ENUMS_DitherModeX_H*/
+
+#ifndef ENUMS_DitherTypeX_H
+#define ENUMS_DitherTypeX_H
+typedef enum DitherTypeX {
+ DITHER_PIXEL = 0,
+ DITHER_SUBPIXEL = 1,
+} DitherTypeX;
+#endif /*ENUMS_DitherTypeX_H*/
+
+#ifndef ENUMS_EdramMode_H
+#define ENUMS_EdramMode_H
+typedef enum EdramMode {
+ EDRAM_NOP = 0,
+ COLOR_DEPTH = 4,
+ DEPTH_ONLY = 5,
+ EDRAM_COPY = 6,
+} EdramMode;
+#endif /*ENUMS_EdramMode_H*/
+
+#ifndef ENUMS_SurfaceEndian_H
+#define ENUMS_SurfaceEndian_H
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0,
+ ENDIAN_8IN16 = 1,
+ ENDIAN_8IN32 = 2,
+ ENDIAN_16IN32 = 3,
+ ENDIAN_8IN64 = 4,
+ ENDIAN_8IN128 = 5,
+} SurfaceEndian;
+#endif /*ENUMS_SurfaceEndian_H*/
+
+#ifndef ENUMS_EdramSizeX_H
+#define ENUMS_EdramSizeX_H
+typedef enum EdramSizeX {
+ EDRAMSIZE_16KB = 0,
+ EDRAMSIZE_32KB = 1,
+ EDRAMSIZE_64KB = 2,
+ EDRAMSIZE_128KB = 3,
+ EDRAMSIZE_256KB = 4,
+ EDRAMSIZE_512KB = 5,
+ EDRAMSIZE_1MB = 6,
+ EDRAMSIZE_2MB = 7,
+ EDRAMSIZE_4MB = 8,
+ EDRAMSIZE_8MB = 9,
+ EDRAMSIZE_16MB = 10,
+} EdramSizeX;
+#endif /*ENUMS_EdramSizeX_H*/
+
+#ifndef ENUMS_RB_PERFCNT_SELECT_H
+#define ENUMS_RB_PERFCNT_SELECT_H
+typedef enum RB_PERFCNT_SELECT {
+ RBPERF_CNTX_BUSY = 0,
+ RBPERF_CNTX_BUSY_MAX = 1,
+ RBPERF_SX_QUAD_STARVED = 2,
+ RBPERF_SX_QUAD_STARVED_MAX = 3,
+ RBPERF_GA_GC_CH0_SYS_REQ = 4,
+ RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
+ RBPERF_GA_GC_CH1_SYS_REQ = 6,
+ RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
+ RBPERF_MH_STARVED = 8,
+ RBPERF_MH_STARVED_MAX = 9,
+ RBPERF_AZ_BC_COLOR_BUSY = 10,
+ RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
+ RBPERF_AZ_BC_Z_BUSY = 12,
+ RBPERF_AZ_BC_Z_BUSY_MAX = 13,
+ RBPERF_RB_SC_TILE_RTR_N = 14,
+ RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
+ RBPERF_RB_SC_SAMP_RTR_N = 16,
+ RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
+ RBPERF_RB_SX_QUAD_RTR_N = 18,
+ RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
+ RBPERF_RB_SX_COLOR_RTR_N = 20,
+ RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
+ RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
+ RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
+ RBPERF_ZXP_STALL = 24,
+ RBPERF_ZXP_STALL_MAX = 25,
+ RBPERF_EVENT_PENDING = 26,
+ RBPERF_EVENT_PENDING_MAX = 27,
+ RBPERF_RB_MH_VALID = 28,
+ RBPERF_RB_MH_VALID_MAX = 29,
+ RBPERF_SX_RB_QUAD_SEND = 30,
+ RBPERF_SX_RB_COLOR_SEND = 31,
+ RBPERF_SC_RB_TILE_SEND = 32,
+ RBPERF_SC_RB_SAMPLE_SEND = 33,
+ RBPERF_SX_RB_MEM_EXPORT = 34,
+ RBPERF_SX_RB_QUAD_EVENT = 35,
+ RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
+ RBPERF_SC_RB_TILE_EVENT_ALL = 37,
+ RBPERF_RB_SC_EZ_SEND = 38,
+ RBPERF_RB_SX_INDEX_SEND = 39,
+ RBPERF_GMEM_INTFO_RD = 40,
+ RBPERF_GMEM_INTF1_RD = 41,
+ RBPERF_GMEM_INTFO_WR = 42,
+ RBPERF_GMEM_INTF1_WR = 43,
+ RBPERF_RB_CP_CONTEXT_DONE = 44,
+ RBPERF_RB_CP_CACHE_FLUSH = 45,
+ RBPERF_ZPASS_DONE = 46,
+ RBPERF_ZCMD_VALID = 47,
+ RBPERF_CCMD_VALID = 48,
+ RBPERF_ACCUM_GRANT = 49,
+ RBPERF_ACCUM_C0_GRANT = 50,
+ RBPERF_ACCUM_C1_GRANT = 51,
+ RBPERF_ACCUM_FULL_BE_WR = 52,
+ RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
+ RBPERF_ACCUM_TIMEOUT_PULSE = 54,
+ RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
+ RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
+} RB_PERFCNT_SELECT;
+#endif /*ENUMS_RB_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_DepthFormat_H
+#define ENUMS_DepthFormat_H
+typedef enum DepthFormat {
+ DEPTH_24_8 = 22,
+ DEPTH_24_8_FLOAT = 23,
+ DEPTH_16 = 24,
+} DepthFormat;
+#endif /*ENUMS_DepthFormat_H*/
+
+#ifndef ENUMS_SurfaceSwap_H
+#define ENUMS_SurfaceSwap_H
+typedef enum SurfaceSwap {
+ SWAP_LOWRED = 0,
+ SWAP_LOWBLUE = 1
+} SurfaceSwap;
+#endif /*ENUMS_SurfaceSwap_H*/
+
+#ifndef ENUMS_DepthArray_H
+#define ENUMS_DepthArray_H
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0,
+ ARRAY_2D_DEPTH = 1,
+} DepthArray;
+#endif /*ENUMS_DepthArray_H*/
+
+#ifndef ENUMS_ColorArray_H
+#define ENUMS_ColorArray_H
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0,
+ ARRAY_2D_COLOR = 1,
+ ARRAY_3D_SLICE_COLOR = 3
+} ColorArray;
+#endif /*ENUMS_ColorArray_H*/
+
+#ifndef ENUMS_ColorFormat_H
+#define ENUMS_ColorFormat_H
+typedef enum ColorFormat {
+ COLOR_8 = 2,
+ COLOR_1_5_5_5 = 3,
+ COLOR_5_6_5 = 4,
+ COLOR_6_5_5 = 5,
+ COLOR_8_8_8_8 = 6,
+ COLOR_2_10_10_10 = 7,
+ COLOR_8_A = 8,
+ COLOR_8_B = 9,
+ COLOR_8_8 = 10,
+ COLOR_8_8_8 = 11,
+ COLOR_8_8_8_8_A = 14,
+ COLOR_4_4_4_4 = 15,
+ COLOR_10_11_11 = 16,
+ COLOR_11_11_10 = 17,
+ COLOR_16 = 24,
+ COLOR_16_16 = 25,
+ COLOR_16_16_16_16 = 26,
+ COLOR_16_FLOAT = 30,
+ COLOR_16_16_FLOAT = 31,
+ COLOR_16_16_16_16_FLOAT = 32,
+ COLOR_32_FLOAT = 36,
+ COLOR_32_32_FLOAT = 37,
+ COLOR_32_32_32_32_FLOAT = 38,
+ COLOR_2_3_3 = 39,
+} ColorFormat;
+#endif /*ENUMS_ColorFormat_H*/
+
+#ifndef ENUMS_SurfaceNumber_H
+#define ENUMS_SurfaceNumber_H
+typedef enum SurfaceNumber {
+ NUMBER_UREPEAT = 0,
+ NUMBER_SREPEAT = 1,
+ NUMBER_UINTEGER = 2,
+ NUMBER_SINTEGER = 3,
+ NUMBER_GAMMA = 4,
+ NUMBER_FIXED = 5,
+ NUMBER_FLOAT = 7
+} SurfaceNumber;
+#endif /*ENUMS_SurfaceNumber_H*/
+
+#ifndef ENUMS_SurfaceFormat_H
+#define ENUMS_SurfaceFormat_H
+typedef enum SurfaceFormat {
+ FMT_1_REVERSE = 0,
+ FMT_1 = 1,
+ FMT_8 = 2,
+ FMT_1_5_5_5 = 3,
+ FMT_5_6_5 = 4,
+ FMT_6_5_5 = 5,
+ FMT_8_8_8_8 = 6,
+ FMT_2_10_10_10 = 7,
+ FMT_8_A = 8,
+ FMT_8_B = 9,
+ FMT_8_8 = 10,
+ FMT_Cr_Y1_Cb_Y0 = 11,
+ FMT_Y1_Cr_Y0_Cb = 12,
+ FMT_5_5_5_1 = 13,
+ FMT_8_8_8_8_A = 14,
+ FMT_4_4_4_4 = 15,
+ FMT_8_8_8 = 16,
+ FMT_DXT1 = 18,
+ FMT_DXT2_3 = 19,
+ FMT_DXT4_5 = 20,
+ FMT_10_10_10_2 = 21,
+ FMT_24_8 = 22,
+ FMT_16 = 24,
+ FMT_16_16 = 25,
+ FMT_16_16_16_16 = 26,
+ FMT_16_EXPAND = 27,
+ FMT_16_16_EXPAND = 28,
+ FMT_16_16_16_16_EXPAND = 29,
+ FMT_16_FLOAT = 30,
+ FMT_16_16_FLOAT = 31,
+ FMT_16_16_16_16_FLOAT = 32,
+ FMT_32 = 33,
+ FMT_32_32 = 34,
+ FMT_32_32_32_32 = 35,
+ FMT_32_FLOAT = 36,
+ FMT_32_32_FLOAT = 37,
+ FMT_32_32_32_32_FLOAT = 38,
+ FMT_ATI_TC_RGB = 39,
+ FMT_ATI_TC_RGBA = 40,
+ FMT_ATI_TC_555_565_RGB = 41,
+ FMT_ATI_TC_555_565_RGBA = 42,
+ FMT_ATI_TC_RGBA_INTERP = 43,
+ FMT_ATI_TC_555_565_RGBA_INTERP = 44,
+ FMT_ETC1_RGBA_INTERP = 46,
+ FMT_ETC1_RGB = 47,
+ FMT_ETC1_RGBA = 48,
+ FMT_DXN = 49,
+ FMT_2_3_3 = 51,
+ FMT_2_10_10_10_AS_16_16_16_16 = 54,
+ FMT_10_10_10_2_AS_16_16_16_16 = 55,
+ FMT_32_32_32_FLOAT = 57,
+ FMT_DXT3A = 58,
+ FMT_DXT5A = 59,
+ FMT_CTX1 = 60,
+} SurfaceFormat;
+#endif /*ENUMS_SurfaceFormat_H*/
+
+#ifndef ENUMS_SurfaceTiling_H
+#define ENUMS_SurfaceTiling_H
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0,
+ ARRAY_TILED = 1
+} SurfaceTiling;
+#endif /*ENUMS_SurfaceTiling_H*/
+
+#ifndef ENUMS_SurfaceArray_H
+#define ENUMS_SurfaceArray_H
+typedef enum SurfaceArray {
+ ARRAY_1D = 0,
+ ARRAY_2D = 1,
+ ARRAY_3D = 2,
+ ARRAY_3D_SLICE = 3
+} SurfaceArray;
+#endif /*ENUMS_SurfaceArray_H*/
+
+#ifndef ENUMS_SurfaceNumberX_H
+#define ENUMS_SurfaceNumberX_H
+typedef enum SurfaceNumberX {
+ NUMBERX_UREPEAT = 0,
+ NUMBERX_SREPEAT = 1,
+ NUMBERX_UINTEGER = 2,
+ NUMBERX_SINTEGER = 3,
+ NUMBERX_FLOAT = 7
+} SurfaceNumberX;
+#endif /*ENUMS_SurfaceNumberX_H*/
+
+#ifndef ENUMS_ColorArrayX_H
+#define ENUMS_ColorArrayX_H
+typedef enum ColorArrayX {
+ ARRAYX_2D_COLOR = 0,
+ ARRAYX_3D_SLICE_COLOR = 1,
+} ColorArrayX;
+#endif /*ENUMS_ColorArrayX_H*/
+
+#endif /*_yamato_ENUM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h
new file mode 100644
index 000000000000..87a454a1e38a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h
@@ -0,0 +1,1703 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_ENUMTYPE(SU_PERFCNT_SELECT)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0)
+    GENERATE_ENUM(UNUSED1, 1)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13)
+    GENERATE_ENUM(UNUSED2, 14)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15)
+    GENERATE_ENUM(UNUSED3, 16)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19)
+    GENERATE_ENUM(UNUSED4, 20)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21)
+    GENERATE_ENUM(UNUSED5, 22)
+    GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36)
+    GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49)
+    GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50)
+    GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51)
+    GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95)
+    GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96)
+    GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97)
+    GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98)
+    GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99)
+    GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100)
+    GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101)
+    GENERATE_ENUM(PERF_PAPC_SU_FACENESS_CULL, 102)
+END_ENUMTYPE(SU_PERFCNT_SELECT)
+
+START_ENUMTYPE(SC_PERFCNT_SELECT)
+    GENERATE_ENUM(SC_SR_WINDOW_VALID, 0)
+    GENERATE_ENUM(SC_CW_WINDOW_VALID, 1)
+    GENERATE_ENUM(SC_QM_WINDOW_VALID, 2)
+    GENERATE_ENUM(SC_FW_WINDOW_VALID, 3)
+    GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4)
+    GENERATE_ENUM(SC_IT_WINDOW_VALID, 5)
+    GENERATE_ENUM(SC_STARVED_BY_PA, 6)
+    GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7)
+    GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8)
+    GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9)
+    GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10)
+    GENERATE_ENUM(SC_STALLED_BY_SQ, 11)
+    GENERATE_ENUM(SC_STALLED_BY_SP, 12)
+    GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13)
+    GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14)
+    GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15)
+    GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16)
+    GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17)
+END_ENUMTYPE(SC_PERFCNT_SELECT)
+
+START_ENUMTYPE(VGT_DI_PRIM_TYPE)
+    GENERATE_ENUM(DI_PT_NONE, 0)
+    GENERATE_ENUM(DI_PT_POINTLIST, 1)
+    GENERATE_ENUM(DI_PT_LINELIST, 2)
+    GENERATE_ENUM(DI_PT_LINESTRIP, 3)
+    GENERATE_ENUM(DI_PT_TRILIST, 4)
+    GENERATE_ENUM(DI_PT_TRIFAN, 5)
+    GENERATE_ENUM(DI_PT_TRISTRIP, 6)
+    GENERATE_ENUM(DI_PT_UNUSED_1, 7)
+    GENERATE_ENUM(DI_PT_RECTLIST, 8)
+    GENERATE_ENUM(DI_PT_UNUSED_2, 9)
+    GENERATE_ENUM(DI_PT_UNUSED_3, 10)
+    GENERATE_ENUM(DI_PT_UNUSED_4, 11)
+    GENERATE_ENUM(DI_PT_UNUSED_5, 12)
+    GENERATE_ENUM(DI_PT_QUADLIST, 13)
+    GENERATE_ENUM(DI_PT_QUADSTRIP, 14)
+    GENERATE_ENUM(DI_PT_POLYGON, 15)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19)
+    GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20)
+    GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21)
+    GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22)
+END_ENUMTYPE(VGT_DI_PRIM_TYPE)
+
+START_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+    GENERATE_ENUM(DI_SRC_SEL_DMA, 0)
+    GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1)
+    GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2)
+    GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3)
+END_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+
+START_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT)
+    GENERATE_ENUM(DI_FACE_CULL_NONE, 0)
+    GENERATE_ENUM(DI_FACE_CULL_FETCH, 1)
+    GENERATE_ENUM(DI_FACE_BACKFACE_CULL, 2)
+    GENERATE_ENUM(DI_FACE_FRONTFACE_CULL, 3)
+END_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT)
+
+START_ENUMTYPE(VGT_DI_INDEX_SIZE)
+    GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1)
+END_ENUMTYPE(VGT_DI_INDEX_SIZE)
+
+START_ENUMTYPE(VGT_DI_SMALL_INDEX)
+    GENERATE_ENUM(DI_USE_INDEX_SIZE, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1)
+END_ENUMTYPE(VGT_DI_SMALL_INDEX)
+
+START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0)
+    GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0)
+    GENERATE_ENUM(GRP_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_EVENT_TYPE)
+    GENERATE_ENUM(VS_DEALLOC, 0)
+    GENERATE_ENUM(PS_DEALLOC, 1)
+    GENERATE_ENUM(VS_DONE_TS, 2)
+    GENERATE_ENUM(PS_DONE_TS, 3)
+    GENERATE_ENUM(CACHE_FLUSH_TS, 4)
+    GENERATE_ENUM(CONTEXT_DONE, 5)
+    GENERATE_ENUM(CACHE_FLUSH, 6)
+    GENERATE_ENUM(VIZQUERY_START, 7)
+    GENERATE_ENUM(VIZQUERY_END, 8)
+    GENERATE_ENUM(SC_WAIT_WC, 9)
+    GENERATE_ENUM(RST_PIX_CNT, 13)
+    GENERATE_ENUM(RST_VTX_CNT, 14)
+    GENERATE_ENUM(TILE_FLUSH, 15)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20)
+    GENERATE_ENUM(ZPASS_DONE, 21)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22)
+    GENERATE_ENUM(PERFCOUNTER_START, 23)
+    GENERATE_ENUM(PERFCOUNTER_STOP, 24)
+    GENERATE_ENUM(VS_FETCH_DONE, 27)
+    GENERATE_ENUM(FACENESS_FLUSH, 28)
+END_ENUMTYPE(VGT_EVENT_TYPE)
+
+START_ENUMTYPE(VGT_DMA_SWAP_MODE)
+    GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0)
+    GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1)
+    GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2)
+    GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3)
+END_ENUMTYPE(VGT_DMA_SWAP_MODE)
+
+START_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0)
+    GENERATE_ENUM(VGT_SQ_SEND, 1)
+    GENERATE_ENUM(VGT_SQ_STALLED, 2)
+    GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3)
+    GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4)
+    GENERATE_ENUM(VGT_SQ_STATIC, 5)
+    GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6)
+    GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11)
+    GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16)
+    GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21)
+    GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28)
+    GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29)
+    GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30)
+    GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31)
+    GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32)
+    GENERATE_ENUM(BIN_PRIM_FACE_CULL, 33)
+    GENERATE_ENUM(SPARE34, 34)
+    GENERATE_ENUM(SPARE35, 35)
+    GENERATE_ENUM(SPARE36, 36)
+    GENERATE_ENUM(SPARE37, 37)
+    GENERATE_ENUM(SPARE38, 38)
+    GENERATE_ENUM(SPARE39, 39)
+    GENERATE_ENUM(TE_SU_IN_VALID, 40)
+    GENERATE_ENUM(TE_SU_IN_READ, 41)
+    GENERATE_ENUM(TE_SU_IN_PRIM, 42)
+    GENERATE_ENUM(TE_SU_IN_EOP, 43)
+    GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44)
+    GENERATE_ENUM(TE_WK_IN_VALID, 45)
+    GENERATE_ENUM(TE_WK_IN_READ, 46)
+    GENERATE_ENUM(TE_OUT_PRIM_VALID, 47)
+    GENERATE_ENUM(TE_OUT_PRIM_READ, 48)
+END_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+    GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0)
+    GENERATE_ENUM(reserved_46, 1)
+    GENERATE_ENUM(reserved_47, 2)
+    GENERATE_ENUM(reserved_48, 3)
+    GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4)
+    GENERATE_ENUM(OPMUX0_L2_WRITES, 5)
+    GENERATE_ENUM(reserved_49, 6)
+    GENERATE_ENUM(reserved_50, 7)
+    GENERATE_ENUM(reserved_51, 8)
+END_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TP_PERFCOUNT_SELECT)
+    GENERATE_ENUM(POINT_QUADS, 0)
+    GENERATE_ENUM(BILIN_QUADS, 1)
+    GENERATE_ENUM(ANISO_QUADS, 2)
+    GENERATE_ENUM(MIP_QUADS, 3)
+    GENERATE_ENUM(VOL_QUADS, 4)
+    GENERATE_ENUM(MIP_VOL_QUADS, 5)
+    GENERATE_ENUM(MIP_ANISO_QUADS, 6)
+    GENERATE_ENUM(VOL_ANISO_QUADS, 7)
+    GENERATE_ENUM(ANISO_2_1_QUADS, 8)
+    GENERATE_ENUM(ANISO_4_1_QUADS, 9)
+    GENERATE_ENUM(ANISO_6_1_QUADS, 10)
+    GENERATE_ENUM(ANISO_8_1_QUADS, 11)
+    GENERATE_ENUM(ANISO_10_1_QUADS, 12)
+    GENERATE_ENUM(ANISO_12_1_QUADS, 13)
+    GENERATE_ENUM(ANISO_14_1_QUADS, 14)
+    GENERATE_ENUM(ANISO_16_1_QUADS, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16)
+    GENERATE_ENUM(ALIGN_2_QUADS, 17)
+    GENERATE_ENUM(ALIGN_4_QUADS, 18)
+    GENERATE_ENUM(PIX_0_QUAD, 19)
+    GENERATE_ENUM(PIX_1_QUAD, 20)
+    GENERATE_ENUM(PIX_2_QUAD, 21)
+    GENERATE_ENUM(PIX_3_QUAD, 22)
+    GENERATE_ENUM(PIX_4_QUAD, 23)
+    GENERATE_ENUM(TP_MIPMAP_LOD0, 24)
+    GENERATE_ENUM(TP_MIPMAP_LOD1, 25)
+    GENERATE_ENUM(TP_MIPMAP_LOD2, 26)
+    GENERATE_ENUM(TP_MIPMAP_LOD3, 27)
+    GENERATE_ENUM(TP_MIPMAP_LOD4, 28)
+    GENERATE_ENUM(TP_MIPMAP_LOD5, 29)
+    GENERATE_ENUM(TP_MIPMAP_LOD6, 30)
+    GENERATE_ENUM(TP_MIPMAP_LOD7, 31)
+    GENERATE_ENUM(TP_MIPMAP_LOD8, 32)
+    GENERATE_ENUM(TP_MIPMAP_LOD9, 33)
+    GENERATE_ENUM(TP_MIPMAP_LOD10, 34)
+    GENERATE_ENUM(TP_MIPMAP_LOD11, 35)
+    GENERATE_ENUM(TP_MIPMAP_LOD12, 36)
+    GENERATE_ENUM(TP_MIPMAP_LOD13, 37)
+    GENERATE_ENUM(TP_MIPMAP_LOD14, 38)
+END_ENUMTYPE(TP_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0)
+    GENERATE_ENUM(reserved_01, 1)
+    GENERATE_ENUM(reserved_02, 2)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6)
+    GENERATE_ENUM(reserved_07, 7)
+    GENERATE_ENUM(reserved_08, 8)
+    GENERATE_ENUM(reserved_09, 9)
+    GENERATE_ENUM(reserved_10, 10)
+    GENERATE_ENUM(reserved_11, 11)
+    GENERATE_ENUM(reserved_12, 12)
+    GENERATE_ENUM(reserved_13, 13)
+    GENERATE_ENUM(reserved_14, 14)
+    GENERATE_ENUM(reserved_15, 15)
+    GENERATE_ENUM(reserved_16, 16)
+    GENERATE_ENUM(reserved_17, 17)
+    GENERATE_ENUM(reserved_18, 18)
+    GENERATE_ENUM(reserved_19, 19)
+    GENERATE_ENUM(reserved_20, 20)
+    GENERATE_ENUM(reserved_21, 21)
+    GENERATE_ENUM(reserved_22, 22)
+    GENERATE_ENUM(reserved_23, 23)
+    GENERATE_ENUM(reserved_24, 24)
+    GENERATE_ENUM(reserved_25, 25)
+    GENERATE_ENUM(reserved_26, 26)
+    GENERATE_ENUM(reserved_27, 27)
+    GENERATE_ENUM(READ_STARVED_QUAD0, 28)
+    GENERATE_ENUM(reserved_29, 29)
+    GENERATE_ENUM(reserved_30, 30)
+    GENERATE_ENUM(reserved_31, 31)
+    GENERATE_ENUM(READ_STARVED, 32)
+    GENERATE_ENUM(READ_STALLED_QUAD0, 33)
+    GENERATE_ENUM(reserved_34, 34)
+    GENERATE_ENUM(reserved_35, 35)
+    GENERATE_ENUM(reserved_36, 36)
+    GENERATE_ENUM(READ_STALLED, 37)
+    GENERATE_ENUM(VALID_READ_QUAD0, 38)
+    GENERATE_ENUM(reserved_39, 39)
+    GENERATE_ENUM(reserved_40, 40)
+    GENERATE_ENUM(reserved_41, 41)
+    GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42)
+    GENERATE_ENUM(reserved_43, 43)
+    GENERATE_ENUM(reserved_44, 44)
+    GENERATE_ENUM(reserved_45, 45)
+    GENERATE_ENUM(TC_TP_STARVED, 46)
+END_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VALID_CYCLES, 0)
+    GENERATE_ENUM(SINGLE_PHASES, 1)
+    GENERATE_ENUM(ANISO_PHASES, 2)
+    GENERATE_ENUM(MIP_PHASES, 3)
+    GENERATE_ENUM(VOL_PHASES, 4)
+    GENERATE_ENUM(MIP_VOL_PHASES, 5)
+    GENERATE_ENUM(MIP_ANISO_PHASES, 6)
+    GENERATE_ENUM(VOL_ANISO_PHASES, 7)
+    GENERATE_ENUM(ANISO_2_1_PHASES, 8)
+    GENERATE_ENUM(ANISO_4_1_PHASES, 9)
+    GENERATE_ENUM(ANISO_6_1_PHASES, 10)
+    GENERATE_ENUM(ANISO_8_1_PHASES, 11)
+    GENERATE_ENUM(ANISO_10_1_PHASES, 12)
+    GENERATE_ENUM(ANISO_12_1_PHASES, 13)
+    GENERATE_ENUM(ANISO_14_1_PHASES, 14)
+    GENERATE_ENUM(ANISO_16_1_PHASES, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16)
+    GENERATE_ENUM(ALIGN_2_PHASES, 17)
+    GENERATE_ENUM(ALIGN_4_PHASES, 18)
+    GENERATE_ENUM(TPC_BUSY, 19)
+    GENERATE_ENUM(TPC_STALLED, 20)
+    GENERATE_ENUM(TPC_STARVED, 21)
+    GENERATE_ENUM(TPC_WORKING, 22)
+    GENERATE_ENUM(TPC_WALKER_BUSY, 23)
+    GENERATE_ENUM(TPC_WALKER_STALLED, 24)
+    GENERATE_ENUM(TPC_WALKER_WORKING, 25)
+    GENERATE_ENUM(TPC_ALIGNER_BUSY, 26)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED, 27)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29)
+    GENERATE_ENUM(TPC_ALIGNER_WORKING, 30)
+    GENERATE_ENUM(TPC_BLEND_BUSY, 31)
+    GENERATE_ENUM(TPC_BLEND_SYNC, 32)
+    GENERATE_ENUM(TPC_BLEND_STARVED, 33)
+    GENERATE_ENUM(TPC_BLEND_WORKING, 34)
+    GENERATE_ENUM(OPCODE_0x00, 35)
+    GENERATE_ENUM(OPCODE_0x01, 36)
+    GENERATE_ENUM(OPCODE_0x04, 37)
+    GENERATE_ENUM(OPCODE_0x10, 38)
+    GENERATE_ENUM(OPCODE_0x11, 39)
+    GENERATE_ENUM(OPCODE_0x12, 40)
+    GENERATE_ENUM(OPCODE_0x13, 41)
+    GENERATE_ENUM(OPCODE_0x18, 42)
+    GENERATE_ENUM(OPCODE_0x19, 43)
+    GENERATE_ENUM(OPCODE_0x1A, 44)
+    GENERATE_ENUM(OPCODE_OTHER, 45)
+    GENERATE_ENUM(IN_FIFO_0_EMPTY, 56)
+    GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57)
+    GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58)
+    GENERATE_ENUM(IN_FIFO_0_FULL, 59)
+    GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72)
+    GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73)
+    GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74)
+    GENERATE_ENUM(IN_FIFO_TPC_FULL, 75)
+    GENERATE_ENUM(TPC_TC_XFC, 76)
+    GENERATE_ENUM(TPC_TC_STATE, 77)
+    GENERATE_ENUM(TC_STALL, 78)
+    GENERATE_ENUM(QUAD0_TAPS, 79)
+    GENERATE_ENUM(QUADS, 83)
+    GENERATE_ENUM(TCA_SYNC_STALL, 84)
+    GENERATE_ENUM(TAG_STALL, 85)
+    GENERATE_ENUM(TCB_SYNC_STALL, 88)
+    GENERATE_ENUM(TCA_VALID, 89)
+    GENERATE_ENUM(PROBES_VALID, 90)
+    GENERATE_ENUM(MISS_STALL, 91)
+    GENERATE_ENUM(FETCH_FIFO_STALL, 92)
+    GENERATE_ENUM(TCO_STALL, 93)
+    GENERATE_ENUM(ANY_STALL, 94)
+    GENERATE_ENUM(TAG_MISSES, 95)
+    GENERATE_ENUM(TAG_HITS, 96)
+    GENERATE_ENUM(SUB_TAG_MISSES, 97)
+    GENERATE_ENUM(SET0_INVALIDATES, 98)
+    GENERATE_ENUM(SET1_INVALIDATES, 99)
+    GENERATE_ENUM(SET2_INVALIDATES, 100)
+    GENERATE_ENUM(SET3_INVALIDATES, 101)
+    GENERATE_ENUM(SET0_TAG_MISSES, 102)
+    GENERATE_ENUM(SET1_TAG_MISSES, 103)
+    GENERATE_ENUM(SET2_TAG_MISSES, 104)
+    GENERATE_ENUM(SET3_TAG_MISSES, 105)
+    GENERATE_ENUM(SET0_TAG_HITS, 106)
+    GENERATE_ENUM(SET1_TAG_HITS, 107)
+    GENERATE_ENUM(SET2_TAG_HITS, 108)
+    GENERATE_ENUM(SET3_TAG_HITS, 109)
+    GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110)
+    GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111)
+    GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112)
+    GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113)
+    GENERATE_ENUM(SET0_EVICT1, 114)
+    GENERATE_ENUM(SET0_EVICT2, 115)
+    GENERATE_ENUM(SET0_EVICT3, 116)
+    GENERATE_ENUM(SET0_EVICT4, 117)
+    GENERATE_ENUM(SET0_EVICT5, 118)
+    GENERATE_ENUM(SET0_EVICT6, 119)
+    GENERATE_ENUM(SET0_EVICT7, 120)
+    GENERATE_ENUM(SET0_EVICT8, 121)
+    GENERATE_ENUM(SET1_EVICT1, 130)
+    GENERATE_ENUM(SET1_EVICT2, 131)
+    GENERATE_ENUM(SET1_EVICT3, 132)
+    GENERATE_ENUM(SET1_EVICT4, 133)
+    GENERATE_ENUM(SET1_EVICT5, 134)
+    GENERATE_ENUM(SET1_EVICT6, 135)
+    GENERATE_ENUM(SET1_EVICT7, 136)
+    GENERATE_ENUM(SET1_EVICT8, 137)
+    GENERATE_ENUM(SET2_EVICT1, 146)
+    GENERATE_ENUM(SET2_EVICT2, 147)
+    GENERATE_ENUM(SET2_EVICT3, 148)
+    GENERATE_ENUM(SET2_EVICT4, 149)
+    GENERATE_ENUM(SET2_EVICT5, 150)
+    GENERATE_ENUM(SET2_EVICT6, 151)
+    GENERATE_ENUM(SET2_EVICT7, 152)
+    GENERATE_ENUM(SET2_EVICT8, 153)
+    GENERATE_ENUM(SET3_EVICT1, 162)
+    GENERATE_ENUM(SET3_EVICT2, 163)
+    GENERATE_ENUM(SET3_EVICT3, 164)
+    GENERATE_ENUM(SET3_EVICT4, 165)
+    GENERATE_ENUM(SET3_EVICT5, 166)
+    GENERATE_ENUM(SET3_EVICT6, 167)
+    GENERATE_ENUM(SET3_EVICT7, 168)
+    GENERATE_ENUM(SET3_EVICT8, 169)
+    GENERATE_ENUM(FF_EMPTY, 178)
+    GENERATE_ENUM(FF_LT_HALF_FULL, 179)
+    GENERATE_ENUM(FF_HALF_FULL, 180)
+    GENERATE_ENUM(FF_FULL, 181)
+    GENERATE_ENUM(FF_XFC, 182)
+    GENERATE_ENUM(FF_STALLED, 183)
+    GENERATE_ENUM(FG_MASKS, 184)
+    GENERATE_ENUM(FG_LEFT_MASKS, 185)
+    GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186)
+    GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187)
+    GENERATE_ENUM(FG_LEFT_FG_STALL, 188)
+    GENERATE_ENUM(FG_LEFT_SECTORS, 189)
+    GENERATE_ENUM(FG0_REQUESTS, 195)
+    GENERATE_ENUM(FG0_STALLED, 196)
+    GENERATE_ENUM(MEM_REQ512, 199)
+    GENERATE_ENUM(MEM_REQ_SENT, 200)
+    GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202)
+    GENERATE_ENUM(TC0_MH_STALLED, 203)
+END_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(SQ_PERFCNT_SELECT)
+    GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0)
+    GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9)
+    GENERATE_ENUM(SQ_EXPORT_CYCLES, 10)
+    GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11)
+    GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12)
+    GENERATE_ENUM(SQ_ALU_CST_STALL, 13)
+    GENERATE_ENUM(SQ_ALU_TEX_STALL, 14)
+    GENERATE_ENUM(SQ_INST_WRITTEN, 15)
+    GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16)
+    GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21)
+    GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22)
+    GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23)
+    GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24)
+    GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25)
+    GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26)
+    GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27)
+    GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28)
+    GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33)
+    GENERATE_ENUM(SQ_ALU_NOPS, 34)
+    GENERATE_ENUM(SQ_PRED_SKIP, 35)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41)
+    GENERATE_ENUM(SQ_GPR_STALL_VTX, 42)
+    GENERATE_ENUM(SQ_GPR_STALL_PIX, 43)
+    GENERATE_ENUM(SQ_VTX_RS_STALL, 44)
+    GENERATE_ENUM(SQ_PIX_RS_STALL, 45)
+    GENERATE_ENUM(SQ_SX_PC_FULL, 46)
+    GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47)
+    GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48)
+    GENERATE_ENUM(SQ_INTERP_QUADS, 49)
+    GENERATE_ENUM(SQ_INTERP_ACTIVE, 50)
+    GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51)
+    GENERATE_ENUM(SQ_IN_VTX_STALL, 52)
+    GENERATE_ENUM(SQ_VTX_CNT, 53)
+    GENERATE_ENUM(SQ_VTX_VECTOR2, 54)
+    GENERATE_ENUM(SQ_VTX_VECTOR3, 55)
+    GENERATE_ENUM(SQ_VTX_VECTOR4, 56)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61)
+    GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_QUAL_TP_DONE, 68)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_QUAL_TP_DONE, 70)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_POP_THREAD, 76)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_POP_THREAD, 80)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_DEALLOC_ACK, 85)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_DEALLOC_ACK, 86)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94)
+    GENERATE_ENUM(VC_PERF_STATIC, 95)
+    GENERATE_ENUM(VC_PERF_STALLED, 96)
+    GENERATE_ENUM(VC_PERF_STARVED, 97)
+    GENERATE_ENUM(VC_PERF_SEND, 98)
+    GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99)
+    GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100)
+    GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101)
+    GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102)
+    GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103)
+    GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104)
+    GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105)
+    GENERATE_ENUM(PTRBUFF_EF_PUSH, 106)
+    GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107)
+    GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108)
+    GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112)
+    GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113)
+    GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114)
+    GENERATE_ENUM(PTRBUFF_PI_RTR, 115)
+    GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116)
+    GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117)
+    GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118)
+    GENERATE_ENUM(PTRBUFF_SQ_DEC, 119)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121)
+    GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122)
+    GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123)
+    GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124)
+    GENERATE_ENUM(PTRBUFF_END_BUFFER, 125)
+    GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126)
+    GENERATE_ENUM(VERTS_WRITTEN_SPI, 127)
+    GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128)
+    GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129)
+    GENERATE_ENUM(TP_DATA_RETURN, 130)
+    GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131)
+    GENERATE_ENUM(SPI_WRITES_SP, 132)
+    GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133)
+    GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134)
+    GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135)
+    GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136)
+    GENERATE_ENUM(SP_EXPORTS_TO_SX, 137)
+    GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138)
+    GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139)
+    GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140)
+    GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141)
+    GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142)
+    GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143)
+    GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144)
+    GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145)
+    GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146)
+    GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147)
+    GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148)
+    GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149)
+    GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150)
+    GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151)
+    GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152)
+    GENERATE_ENUM(SQ_PIX_TOTAL, 153)
+    GENERATE_ENUM(SQ_PIX_KILLED, 154)
+END_ENUMTYPE(SQ_PERFCNT_SELECT)
+
+START_ENUMTYPE(SX_PERFCNT_SELECT)
+    GENERATE_ENUM(SX_EXPORT_VECTORS, 0)
+    GENERATE_ENUM(SX_DUMMY_QUADS, 1)
+    GENERATE_ENUM(SX_ALPHA_FAIL, 2)
+    GENERATE_ENUM(SX_RB_QUAD_BUSY, 3)
+    GENERATE_ENUM(SX_RB_COLOR_BUSY, 4)
+    GENERATE_ENUM(SX_RB_QUAD_STALL, 5)
+    GENERATE_ENUM(SX_RB_COLOR_STALL, 6)
+END_ENUMTYPE(SX_PERFCNT_SELECT)
+
+START_ENUMTYPE(Abs_modifier)
+    GENERATE_ENUM(NO_ABS_MOD, 0)
+    GENERATE_ENUM(ABS_MOD, 1)
+END_ENUMTYPE(Abs_modifier)
+
+START_ENUMTYPE(Exporting)
+    GENERATE_ENUM(NOT_EXPORTING, 0)
+    GENERATE_ENUM(EXPORTING, 1)
+END_ENUMTYPE(Exporting)
+
+START_ENUMTYPE(ScalarOpcode)
+    GENERATE_ENUM(ADDs, 0)
+    GENERATE_ENUM(ADD_PREVs, 1)
+    GENERATE_ENUM(MULs, 2)
+    GENERATE_ENUM(MUL_PREVs, 3)
+    GENERATE_ENUM(MUL_PREV2s, 4)
+    GENERATE_ENUM(MAXs, 5)
+    GENERATE_ENUM(MINs, 6)
+    GENERATE_ENUM(SETEs, 7)
+    GENERATE_ENUM(SETGTs, 8)
+    GENERATE_ENUM(SETGTEs, 9)
+    GENERATE_ENUM(SETNEs, 10)
+    GENERATE_ENUM(FRACs, 11)
+    GENERATE_ENUM(TRUNCs, 12)
+    GENERATE_ENUM(FLOORs, 13)
+    GENERATE_ENUM(EXP_IEEE, 14)
+    GENERATE_ENUM(LOG_CLAMP, 15)
+    GENERATE_ENUM(LOG_IEEE, 16)
+    GENERATE_ENUM(RECIP_CLAMP, 17)
+    GENERATE_ENUM(RECIP_FF, 18)
+    GENERATE_ENUM(RECIP_IEEE, 19)
+    GENERATE_ENUM(RECIPSQ_CLAMP, 20)
+    GENERATE_ENUM(RECIPSQ_FF, 21)
+    GENERATE_ENUM(RECIPSQ_IEEE, 22)
+    GENERATE_ENUM(MOVAs, 23)
+    GENERATE_ENUM(MOVA_FLOORs, 24)
+    GENERATE_ENUM(SUBs, 25)
+    GENERATE_ENUM(SUB_PREVs, 26)
+    GENERATE_ENUM(PRED_SETEs, 27)
+    GENERATE_ENUM(PRED_SETNEs, 28)
+    GENERATE_ENUM(PRED_SETGTs, 29)
+    GENERATE_ENUM(PRED_SETGTEs, 30)
+    GENERATE_ENUM(PRED_SET_INVs, 31)
+    GENERATE_ENUM(PRED_SET_POPs, 32)
+    GENERATE_ENUM(PRED_SET_CLRs, 33)
+    GENERATE_ENUM(PRED_SET_RESTOREs, 34)
+    GENERATE_ENUM(KILLEs, 35)
+    GENERATE_ENUM(KILLGTs, 36)
+    GENERATE_ENUM(KILLGTEs, 37)
+    GENERATE_ENUM(KILLNEs, 38)
+    GENERATE_ENUM(KILLONEs, 39)
+    GENERATE_ENUM(SQRT_IEEE, 40)
+    GENERATE_ENUM(MUL_CONST_0, 42)
+    GENERATE_ENUM(MUL_CONST_1, 43)
+    GENERATE_ENUM(ADD_CONST_0, 44)
+    GENERATE_ENUM(ADD_CONST_1, 45)
+    GENERATE_ENUM(SUB_CONST_0, 46)
+    GENERATE_ENUM(SUB_CONST_1, 47)
+    GENERATE_ENUM(SIN, 48)
+    GENERATE_ENUM(COS, 49)
+    GENERATE_ENUM(RETAIN_PREV, 50)
+END_ENUMTYPE(ScalarOpcode)
+
+START_ENUMTYPE(SwizzleType)
+    GENERATE_ENUM(NO_SWIZZLE, 0)
+    GENERATE_ENUM(SHIFT_RIGHT_1, 1)
+    GENERATE_ENUM(SHIFT_RIGHT_2, 2)
+    GENERATE_ENUM(SHIFT_RIGHT_3, 3)
+END_ENUMTYPE(SwizzleType)
+
+START_ENUMTYPE(InputModifier)
+    GENERATE_ENUM(NIL, 0)
+    GENERATE_ENUM(NEGATE, 1)
+END_ENUMTYPE(InputModifier)
+
+START_ENUMTYPE(PredicateSelect)
+    GENERATE_ENUM(NO_PREDICATION, 0)
+    GENERATE_ENUM(PREDICATE_QUAD, 1)
+    GENERATE_ENUM(PREDICATED_2, 2)
+    GENERATE_ENUM(PREDICATED_3, 3)
+END_ENUMTYPE(PredicateSelect)
+
+START_ENUMTYPE(OperandSelect1)
+    GENERATE_ENUM(ABSOLUTE_REG, 0)
+    GENERATE_ENUM(RELATIVE_REG, 1)
+END_ENUMTYPE(OperandSelect1)
+
+START_ENUMTYPE(VectorOpcode)
+    GENERATE_ENUM(ADDv, 0)
+    GENERATE_ENUM(MULv, 1)
+    GENERATE_ENUM(MAXv, 2)
+    GENERATE_ENUM(MINv, 3)
+    GENERATE_ENUM(SETEv, 4)
+    GENERATE_ENUM(SETGTv, 5)
+    GENERATE_ENUM(SETGTEv, 6)
+    GENERATE_ENUM(SETNEv, 7)
+    GENERATE_ENUM(FRACv, 8)
+    GENERATE_ENUM(TRUNCv, 9)
+    GENERATE_ENUM(FLOORv, 10)
+    GENERATE_ENUM(MULADDv, 11)
+    GENERATE_ENUM(CNDEv, 12)
+    GENERATE_ENUM(CNDGTEv, 13)
+    GENERATE_ENUM(CNDGTv, 14)
+    GENERATE_ENUM(DOT4v, 15)
+    GENERATE_ENUM(DOT3v, 16)
+    GENERATE_ENUM(DOT2ADDv, 17)
+    GENERATE_ENUM(CUBEv, 18)
+    GENERATE_ENUM(MAX4v, 19)
+    GENERATE_ENUM(PRED_SETE_PUSHv, 20)
+    GENERATE_ENUM(PRED_SETNE_PUSHv, 21)
+    GENERATE_ENUM(PRED_SETGT_PUSHv, 22)
+    GENERATE_ENUM(PRED_SETGTE_PUSHv, 23)
+    GENERATE_ENUM(KILLEv, 24)
+    GENERATE_ENUM(KILLGTv, 25)
+    GENERATE_ENUM(KILLGTEv, 26)
+    GENERATE_ENUM(KILLNEv, 27)
+    GENERATE_ENUM(DSTv, 28)
+    GENERATE_ENUM(MOVAv, 29)
+END_ENUMTYPE(VectorOpcode)
+
+START_ENUMTYPE(OperandSelect0)
+    GENERATE_ENUM(CONSTANT, 0)
+    GENERATE_ENUM(NON_CONSTANT, 1)
+END_ENUMTYPE(OperandSelect0)
+
+START_ENUMTYPE(Ressource_type)
+    GENERATE_ENUM(ALU, 0)
+    GENERATE_ENUM(TEXTURE, 1)
+END_ENUMTYPE(Ressource_type)
+
+START_ENUMTYPE(Instruction_serial)
+    GENERATE_ENUM(NOT_SERIAL, 0)
+    GENERATE_ENUM(SERIAL, 1)
+END_ENUMTYPE(Instruction_serial)
+
+START_ENUMTYPE(VC_type)
+    GENERATE_ENUM(ALU_TP_REQUEST, 0)
+    GENERATE_ENUM(VC_REQUEST, 1)
+END_ENUMTYPE(VC_type)
+
+START_ENUMTYPE(Addressing)
+    GENERATE_ENUM(RELATIVE_ADDR, 0)
+    GENERATE_ENUM(ABSOLUTE_ADDR, 1)
+END_ENUMTYPE(Addressing)
+
+START_ENUMTYPE(CFOpcode)
+    GENERATE_ENUM(NOP, 0)
+    GENERATE_ENUM(EXECUTE, 1)
+    GENERATE_ENUM(EXECUTE_END, 2)
+    GENERATE_ENUM(COND_EXECUTE, 3)
+    GENERATE_ENUM(COND_EXECUTE_END, 4)
+    GENERATE_ENUM(COND_PRED_EXECUTE, 5)
+    GENERATE_ENUM(COND_PRED_EXECUTE_END, 6)
+    GENERATE_ENUM(LOOP_START, 7)
+    GENERATE_ENUM(LOOP_END, 8)
+    GENERATE_ENUM(COND_CALL, 9)
+    GENERATE_ENUM(RETURN, 10)
+    GENERATE_ENUM(COND_JMP, 11)
+    GENERATE_ENUM(ALLOCATE, 12)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14)
+    GENERATE_ENUM(MARK_VS_FETCH_DONE, 15)
+END_ENUMTYPE(CFOpcode)
+
+START_ENUMTYPE(Allocation_type)
+    GENERATE_ENUM(SQ_NO_ALLOC, 0)
+    GENERATE_ENUM(SQ_POSITION, 1)
+    GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2)
+    GENERATE_ENUM(SQ_MEMORY, 3)
+END_ENUMTYPE(Allocation_type)
+
+START_ENUMTYPE(TexInstOpcode)
+    GENERATE_ENUM(TEX_INST_FETCH, 1)
+    GENERATE_ENUM(TEX_INST_RESERVED_1, 2)
+    GENERATE_ENUM(TEX_INST_RESERVED_2, 3)
+    GENERATE_ENUM(TEX_INST_RESERVED_3, 4)
+    GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16)
+    GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17)
+    GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18)
+    GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19)
+    GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26)
+    GENERATE_ENUM(TEX_INST_RESERVED_4, 27)
+END_ENUMTYPE(TexInstOpcode)
+
+START_ENUMTYPE(Addressmode)
+    GENERATE_ENUM(LOGICAL, 0)
+    GENERATE_ENUM(LOOP_RELATIVE, 1)
+END_ENUMTYPE(Addressmode)
+
+START_ENUMTYPE(TexCoordDenorm)
+    GENERATE_ENUM(TEX_COORD_NORMALIZED, 0)
+    GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1)
+END_ENUMTYPE(TexCoordDenorm)
+
+START_ENUMTYPE(SrcSel)
+    GENERATE_ENUM(SRC_SEL_X, 0)
+    GENERATE_ENUM(SRC_SEL_Y, 1)
+    GENERATE_ENUM(SRC_SEL_Z, 2)
+    GENERATE_ENUM(SRC_SEL_W, 3)
+END_ENUMTYPE(SrcSel)
+
+START_ENUMTYPE(DstSel)
+    GENERATE_ENUM(DST_SEL_X, 0)
+    GENERATE_ENUM(DST_SEL_Y, 1)
+    GENERATE_ENUM(DST_SEL_Z, 2)
+    GENERATE_ENUM(DST_SEL_W, 3)
+    GENERATE_ENUM(DST_SEL_0, 4)
+    GENERATE_ENUM(DST_SEL_1, 5)
+    GENERATE_ENUM(DST_SEL_RSVD, 6)
+    GENERATE_ENUM(DST_SEL_MASK, 7)
+END_ENUMTYPE(DstSel)
+
+START_ENUMTYPE(MagFilter)
+    GENERATE_ENUM(MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MagFilter)
+
+START_ENUMTYPE(MinFilter)
+    GENERATE_ENUM(MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MinFilter)
+
+START_ENUMTYPE(MipFilter)
+    GENERATE_ENUM(MIP_FILTER_POINT, 0)
+    GENERATE_ENUM(MIP_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIP_FILTER_BASEMAP, 2)
+    GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MipFilter)
+
+START_ENUMTYPE(AnisoFilter)
+    GENERATE_ENUM(ANISO_FILTER_DISABLED, 0)
+    GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1)
+    GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2)
+    GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3)
+    GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4)
+    GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5)
+    GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(AnisoFilter)
+
+START_ENUMTYPE(ArbitraryFilter)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5)
+    GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(ArbitraryFilter)
+
+START_ENUMTYPE(VolMagFilter)
+    GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMagFilter)
+
+START_ENUMTYPE(VolMinFilter)
+    GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMinFilter)
+
+START_ENUMTYPE(PredSelect)
+    GENERATE_ENUM(NOT_PREDICATED, 0)
+    GENERATE_ENUM(PREDICATED, 1)
+END_ENUMTYPE(PredSelect)
+
+START_ENUMTYPE(SampleLocation)
+    GENERATE_ENUM(SAMPLE_CENTROID, 0)
+    GENERATE_ENUM(SAMPLE_CENTER, 1)
+END_ENUMTYPE(SampleLocation)
+
+START_ENUMTYPE(VertexMode)
+    GENERATE_ENUM(POSITION_1_VECTOR, 0)
+    GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3)
+    GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6)
+    GENERATE_ENUM(MULTIPASS, 7)
+END_ENUMTYPE(VertexMode)
+
+START_ENUMTYPE(Sample_Cntl)
+    GENERATE_ENUM(CENTROIDS_ONLY, 0)
+    GENERATE_ENUM(CENTERS_ONLY, 1)
+    GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2)
+    GENERATE_ENUM(UNDEF, 3)
+END_ENUMTYPE(Sample_Cntl)
+
+START_ENUMTYPE(MhPerfEncode)
+    GENERATE_ENUM(CP_R0_REQUESTS, 0)
+    GENERATE_ENUM(CP_R1_REQUESTS, 1)
+    GENERATE_ENUM(CP_R2_REQUESTS, 2)
+    GENERATE_ENUM(CP_R3_REQUESTS, 3)
+    GENERATE_ENUM(CP_R4_REQUESTS, 4)
+    GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5)
+    GENERATE_ENUM(CP_TOTAL_WRITE_REQUESTS, 6)
+    GENERATE_ENUM(CP_TOTAL_REQUESTS, 7)
+    GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8)
+    GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9)
+    GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10)
+    GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11)
+    GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12)
+    GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13)
+    GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14)
+    GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15)
+    GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16)
+    GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17)
+    GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18)
+    GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19)
+    GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20)
+    GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21)
+    GENERATE_ENUM(VGT_R0_REQUESTS, 22)
+    GENERATE_ENUM(VGT_R1_REQUESTS, 23)
+    GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24)
+    GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25)
+    GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26)
+    GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27)
+    GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28)
+    GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29)
+    GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30)
+    GENERATE_ENUM(TC_TOTAL_REQUESTS, 31)
+    GENERATE_ENUM(TC_ROQ_REQUESTS, 32)
+    GENERATE_ENUM(TC_INFO_SENT, 33)
+    GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34)
+    GENERATE_ENUM(TC_DATA_BEATS_READ, 35)
+    GENERATE_ENUM(TCD_BURSTS_READ, 36)
+    GENERATE_ENUM(RB_REQUESTS, 37)
+    GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38)
+    GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56)
+    GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111)
+    GENERATE_ENUM(TOTAL_MMU_MISSES, 112)
+    GENERATE_ENUM(MMU_READ_MISSES, 113)
+    GENERATE_ENUM(MMU_WRITE_MISSES, 114)
+    GENERATE_ENUM(TOTAL_MMU_HITS, 115)
+    GENERATE_ENUM(MMU_READ_HITS, 116)
+    GENERATE_ENUM(MMU_WRITE_HITS, 117)
+    GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118)
+    GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121)
+    GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122)
+    GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123)
+    GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124)
+    GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125)
+    GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127)
+    GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129)
+    GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130)
+    GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131)
+    GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132)
+    GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133)
+    GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136)
+    GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140)
+    GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148)
+    GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149)
+    GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150)
+    GENERATE_ENUM(TOTAL_MH_REQUESTS, 151)
+    GENERATE_ENUM(MH_BUSY, 152)
+    GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153)
+    GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154)
+    GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155)
+    GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156)
+    GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157)
+    GENERATE_ENUM(ARQ_N_ENTRIES, 158)
+    GENERATE_ENUM(WDB_N_ENTRIES, 159)
+    GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160)
+    GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161)
+    GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162)
+    GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163)
+    GENERATE_ENUM(ELAPSED_CLK_CYCLES, 164)
+    GENERATE_ENUM(CP_W_16B_REQUESTS, 165)
+    GENERATE_ENUM(CP_W_32B_REQUESTS, 166)
+    GENERATE_ENUM(TC_16B_REQUESTS, 167)
+    GENERATE_ENUM(TC_32B_REQUESTS, 168)
+    GENERATE_ENUM(PA_REQUESTS, 169)
+    GENERATE_ENUM(PA_DATA_BYTES_WRITTEN, 170)
+    GENERATE_ENUM(PA_WRITE_CLEAN_RESPONSES, 171)
+    GENERATE_ENUM(PA_CYCLES_HELD_OFF, 172)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_0, 173)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_1, 174)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_2, 175)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_3, 176)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_4, 177)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_5, 178)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_6, 179)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_7, 180)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUEST_DATA_BEATS, 181)
+END_ENUMTYPE(MhPerfEncode)
+
+START_ENUMTYPE(MmuClntBeh)
+    GENERATE_ENUM(BEH_NEVR, 0)
+    GENERATE_ENUM(BEH_TRAN_RNG, 1)
+    GENERATE_ENUM(BEH_TRAN_FLT, 2)
+END_ENUMTYPE(MmuClntBeh)
+
+START_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+    GENERATE_ENUM(RBBM1_COUNT, 0)
+    GENERATE_ENUM(RBBM1_NRT_BUSY, 1)
+    GENERATE_ENUM(RBBM1_RB_BUSY, 2)
+    GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3)
+    GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4)
+    GENERATE_ENUM(RBBM1_VGT_BUSY, 5)
+    GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6)
+    GENERATE_ENUM(RBBM1_PA_BUSY, 7)
+    GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8)
+    GENERATE_ENUM(RBBM1_TPC_BUSY, 9)
+    GENERATE_ENUM(RBBM1_TC_BUSY, 10)
+    GENERATE_ENUM(RBBM1_SX_BUSY, 11)
+    GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12)
+    GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13)
+    GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14)
+    GENERATE_ENUM(RBBM1_INTERRUPT, 15)
+END_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+
+START_ENUMTYPE(CP_PERFCOUNT_SEL)
+    GENERATE_ENUM(ALWAYS_COUNT, 0)
+    GENERATE_ENUM(TRANS_FIFO_FULL, 1)
+    GENERATE_ENUM(TRANS_FIFO_AF, 2)
+    GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3)
+    GENERATE_ENUM(Reserved_04, 4)
+    GENERATE_ENUM(Reserved_05, 5)
+    GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6)
+    GENERATE_ENUM(Reserved_07, 7)
+    GENERATE_ENUM(CSF_NRT_READ_WAIT, 8)
+    GENERATE_ENUM(CSF_I1_FIFO_FULL, 9)
+    GENERATE_ENUM(CSF_I2_FIFO_FULL, 10)
+    GENERATE_ENUM(CSF_ST_FIFO_FULL, 11)
+    GENERATE_ENUM(Reserved_12, 12)
+    GENERATE_ENUM(CSF_RING_ROQ_FULL, 13)
+    GENERATE_ENUM(CSF_I1_ROQ_FULL, 14)
+    GENERATE_ENUM(CSF_I2_ROQ_FULL, 15)
+    GENERATE_ENUM(CSF_ST_ROQ_FULL, 16)
+    GENERATE_ENUM(Reserved_17, 17)
+    GENERATE_ENUM(MIU_TAG_MEM_FULL, 18)
+    GENERATE_ENUM(MIU_WRITECLEAN, 19)
+    GENERATE_ENUM(Reserved_20, 20)
+    GENERATE_ENUM(Reserved_21, 21)
+    GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22)
+    GENERATE_ENUM(MIU_NRT_READ_STALLED, 23)
+    GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24)
+    GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25)
+    GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26)
+    GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27)
+    GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28)
+    GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29)
+    GENERATE_ENUM(ME_MICRO_RB_STARVED, 30)
+    GENERATE_ENUM(ME_MICRO_I1_STARVED, 31)
+    GENERATE_ENUM(ME_MICRO_I2_STARVED, 32)
+    GENERATE_ENUM(ME_MICRO_ST_STARVED, 33)
+    GENERATE_ENUM(Reserved_34, 34)
+    GENERATE_ENUM(Reserved_35, 35)
+    GENERATE_ENUM(Reserved_36, 36)
+    GENERATE_ENUM(Reserved_37, 37)
+    GENERATE_ENUM(Reserved_38, 38)
+    GENERATE_ENUM(Reserved_39, 39)
+    GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40)
+    GENERATE_ENUM(ME_BUSY_CLOCKS, 41)
+    GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42)
+    GENERATE_ENUM(PFP_TYPE0_PACKET, 43)
+    GENERATE_ENUM(PFP_TYPE3_PACKET, 44)
+    GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45)
+    GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46)
+    GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47)
+    GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48)
+    GENERATE_ENUM(Reserved_49, 49)
+    GENERATE_ENUM(Reserved_50, 50)
+    GENERATE_ENUM(Reserved_51, 51)
+    GENERATE_ENUM(Reserved_52, 52)
+    GENERATE_ENUM(Reserved_53, 53)
+    GENERATE_ENUM(Reserved_54, 54)
+    GENERATE_ENUM(Reserved_55, 55)
+    GENERATE_ENUM(Reserved_56, 56)
+    GENERATE_ENUM(Reserved_57, 57)
+    GENERATE_ENUM(Reserved_58, 58)
+    GENERATE_ENUM(Reserved_59, 59)
+    GENERATE_ENUM(Reserved_60, 60)
+    GENERATE_ENUM(Reserved_61, 61)
+    GENERATE_ENUM(Reserved_62, 62)
+    GENERATE_ENUM(Reserved_63, 63)
+END_ENUMTYPE(CP_PERFCOUNT_SEL)
+
+START_ENUMTYPE(ColorformatX)
+    GENERATE_ENUM(COLORX_4_4_4_4, 0)
+    GENERATE_ENUM(COLORX_1_5_5_5, 1)
+    GENERATE_ENUM(COLORX_5_6_5, 2)
+    GENERATE_ENUM(COLORX_8, 3)
+    GENERATE_ENUM(COLORX_8_8, 4)
+    GENERATE_ENUM(COLORX_8_8_8_8, 5)
+    GENERATE_ENUM(COLORX_S8_8_8_8, 6)
+    GENERATE_ENUM(COLORX_16_FLOAT, 7)
+    GENERATE_ENUM(COLORX_16_16_FLOAT, 8)
+    GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9)
+    GENERATE_ENUM(COLORX_32_FLOAT, 10)
+    GENERATE_ENUM(COLORX_32_32_FLOAT, 11)
+    GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12)
+    GENERATE_ENUM(COLORX_2_3_3, 13)
+    GENERATE_ENUM(COLORX_8_8_8, 14)
+END_ENUMTYPE(ColorformatX)
+
+START_ENUMTYPE(DepthformatX)
+    GENERATE_ENUM(DEPTHX_16, 0)
+    GENERATE_ENUM(DEPTHX_24_8, 1)
+END_ENUMTYPE(DepthformatX)
+
+START_ENUMTYPE(CompareFrag)
+    GENERATE_ENUM(FRAG_NEVER, 0)
+    GENERATE_ENUM(FRAG_LESS, 1)
+    GENERATE_ENUM(FRAG_EQUAL, 2)
+    GENERATE_ENUM(FRAG_LEQUAL, 3)
+    GENERATE_ENUM(FRAG_GREATER, 4)
+    GENERATE_ENUM(FRAG_NOTEQUAL, 5)
+    GENERATE_ENUM(FRAG_GEQUAL, 6)
+    GENERATE_ENUM(FRAG_ALWAYS, 7)
+END_ENUMTYPE(CompareFrag)
+
+START_ENUMTYPE(CompareRef)
+    GENERATE_ENUM(REF_NEVER, 0)
+    GENERATE_ENUM(REF_LESS, 1)
+    GENERATE_ENUM(REF_EQUAL, 2)
+    GENERATE_ENUM(REF_LEQUAL, 3)
+    GENERATE_ENUM(REF_GREATER, 4)
+    GENERATE_ENUM(REF_NOTEQUAL, 5)
+    GENERATE_ENUM(REF_GEQUAL, 6)
+    GENERATE_ENUM(REF_ALWAYS, 7)
+END_ENUMTYPE(CompareRef)
+
+START_ENUMTYPE(StencilOp)
+    GENERATE_ENUM(STENCIL_KEEP, 0)
+    GENERATE_ENUM(STENCIL_ZERO, 1)
+    GENERATE_ENUM(STENCIL_REPLACE, 2)
+    GENERATE_ENUM(STENCIL_INCR_CLAMP, 3)
+    GENERATE_ENUM(STENCIL_DECR_CLAMP, 4)
+    GENERATE_ENUM(STENCIL_INVERT, 5)
+    GENERATE_ENUM(STENCIL_INCR_WRAP, 6)
+    GENERATE_ENUM(STENCIL_DECR_WRAP, 7)
+END_ENUMTYPE(StencilOp)
+
+START_ENUMTYPE(BlendOpX)
+    GENERATE_ENUM(BLENDX_ZERO, 0)
+    GENERATE_ENUM(BLENDX_ONE, 1)
+    GENERATE_ENUM(BLENDX_SRC_COLOR, 4)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA, 6)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7)
+    GENERATE_ENUM(BLENDX_DST_COLOR, 8)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9)
+    GENERATE_ENUM(BLENDX_DST_ALPHA, 10)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11)
+    GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13)
+    GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16)
+END_ENUMTYPE(BlendOpX)
+
+START_ENUMTYPE(CombFuncX)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC, 0)
+    GENERATE_ENUM(COMB_SRC_MINUS_DST, 1)
+    GENERATE_ENUM(COMB_MIN_DST_SRC, 2)
+    GENERATE_ENUM(COMB_MAX_DST_SRC, 3)
+    GENERATE_ENUM(COMB_DST_MINUS_SRC, 4)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5)
+END_ENUMTYPE(CombFuncX)
+
+START_ENUMTYPE(DitherModeX)
+    GENERATE_ENUM(DITHER_DISABLE, 0)
+    GENERATE_ENUM(DITHER_ALWAYS, 1)
+    GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2)
+END_ENUMTYPE(DitherModeX)
+
+START_ENUMTYPE(DitherTypeX)
+    GENERATE_ENUM(DITHER_PIXEL, 0)
+    GENERATE_ENUM(DITHER_SUBPIXEL, 1)
+END_ENUMTYPE(DitherTypeX)
+
+START_ENUMTYPE(EdramMode)
+    GENERATE_ENUM(EDRAM_NOP, 0)
+    GENERATE_ENUM(COLOR_DEPTH, 4)
+    GENERATE_ENUM(DEPTH_ONLY, 5)
+    GENERATE_ENUM(EDRAM_COPY, 6)
+END_ENUMTYPE(EdramMode)
+
+START_ENUMTYPE(SurfaceEndian)
+    GENERATE_ENUM(ENDIAN_NONE, 0)
+    GENERATE_ENUM(ENDIAN_8IN16, 1)
+    GENERATE_ENUM(ENDIAN_8IN32, 2)
+    GENERATE_ENUM(ENDIAN_16IN32, 3)
+    GENERATE_ENUM(ENDIAN_8IN64, 4)
+    GENERATE_ENUM(ENDIAN_8IN128, 5)
+END_ENUMTYPE(SurfaceEndian)
+
+START_ENUMTYPE(EdramSizeX)
+    GENERATE_ENUM(EDRAMSIZE_16KB, 0)
+    GENERATE_ENUM(EDRAMSIZE_32KB, 1)
+    GENERATE_ENUM(EDRAMSIZE_64KB, 2)
+    GENERATE_ENUM(EDRAMSIZE_128KB, 3)
+    GENERATE_ENUM(EDRAMSIZE_256KB, 4)
+    GENERATE_ENUM(EDRAMSIZE_512KB, 5)
+    GENERATE_ENUM(EDRAMSIZE_1MB, 6)
+    GENERATE_ENUM(EDRAMSIZE_2MB, 7)
+    GENERATE_ENUM(EDRAMSIZE_4MB, 8)
+    GENERATE_ENUM(EDRAMSIZE_8MB, 9)
+    GENERATE_ENUM(EDRAMSIZE_16MB, 10)
+END_ENUMTYPE(EdramSizeX)
+
+START_ENUMTYPE(RB_PERFCNT_SELECT)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY, 0)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7)
+    GENERATE_ENUM(RBPERF_MH_STARVED, 8)
+    GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23)
+    GENERATE_ENUM(RBPERF_ZXP_STALL, 24)
+    GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING, 26)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID, 28)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30)
+    GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32)
+    GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33)
+    GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37)
+    GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38)
+    GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43)
+    GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44)
+    GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45)
+    GENERATE_ENUM(RBPERF_ZPASS_DONE, 46)
+    GENERATE_ENUM(RBPERF_ZCMD_VALID, 47)
+    GENERATE_ENUM(RBPERF_CCMD_VALID, 48)
+    GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49)
+    GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50)
+    GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51)
+    GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52)
+    GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53)
+    GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54)
+    GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55)
+    GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56)
+END_ENUMTYPE(RB_PERFCNT_SELECT)
+
+START_ENUMTYPE(DepthFormat)
+    GENERATE_ENUM(DEPTH_24_8, 22)
+    GENERATE_ENUM(DEPTH_24_8_FLOAT, 23)
+    GENERATE_ENUM(DEPTH_16, 24)
+END_ENUMTYPE(DepthFormat)
+
+START_ENUMTYPE(SurfaceSwap)
+    GENERATE_ENUM(SWAP_LOWRED, 0)
+    GENERATE_ENUM(SWAP_LOWBLUE, 1)
+END_ENUMTYPE(SurfaceSwap)
+
+START_ENUMTYPE(DepthArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0)
+    GENERATE_ENUM(ARRAY_2D_DEPTH, 1)
+END_ENUMTYPE(DepthArray)
+
+START_ENUMTYPE(ColorArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0)
+    GENERATE_ENUM(ARRAY_2D_COLOR, 1)
+    GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3)
+END_ENUMTYPE(ColorArray)
+
+START_ENUMTYPE(ColorFormat)
+    GENERATE_ENUM(COLOR_8, 2)
+    GENERATE_ENUM(COLOR_1_5_5_5, 3)
+    GENERATE_ENUM(COLOR_5_6_5, 4)
+    GENERATE_ENUM(COLOR_6_5_5, 5)
+    GENERATE_ENUM(COLOR_8_8_8_8, 6)
+    GENERATE_ENUM(COLOR_2_10_10_10, 7)
+    GENERATE_ENUM(COLOR_8_A, 8)
+    GENERATE_ENUM(COLOR_8_B, 9)
+    GENERATE_ENUM(COLOR_8_8, 10)
+    GENERATE_ENUM(COLOR_8_8_8, 11)
+    GENERATE_ENUM(COLOR_8_8_8_8_A, 14)
+    GENERATE_ENUM(COLOR_4_4_4_4, 15)
+    GENERATE_ENUM(COLOR_10_11_11, 16)
+    GENERATE_ENUM(COLOR_11_11_10, 17)
+    GENERATE_ENUM(COLOR_16, 24)
+    GENERATE_ENUM(COLOR_16_16, 25)
+    GENERATE_ENUM(COLOR_16_16_16_16, 26)
+    GENERATE_ENUM(COLOR_16_FLOAT, 30)
+    GENERATE_ENUM(COLOR_16_16_FLOAT, 31)
+    GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(COLOR_32_FLOAT, 36)
+    GENERATE_ENUM(COLOR_32_32_FLOAT, 37)
+    GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(COLOR_2_3_3, 39)
+END_ENUMTYPE(ColorFormat)
+
+START_ENUMTYPE(SurfaceNumber)
+    GENERATE_ENUM(NUMBER_UREPEAT, 0)
+    GENERATE_ENUM(NUMBER_SREPEAT, 1)
+    GENERATE_ENUM(NUMBER_UINTEGER, 2)
+    GENERATE_ENUM(NUMBER_SINTEGER, 3)
+    GENERATE_ENUM(NUMBER_GAMMA, 4)
+    GENERATE_ENUM(NUMBER_FIXED, 5)
+    GENERATE_ENUM(NUMBER_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumber)
+
+START_ENUMTYPE(SurfaceFormat)
+    GENERATE_ENUM(FMT_1_REVERSE, 0)
+    GENERATE_ENUM(FMT_1, 1)
+    GENERATE_ENUM(FMT_8, 2)
+    GENERATE_ENUM(FMT_1_5_5_5, 3)
+    GENERATE_ENUM(FMT_5_6_5, 4)
+    GENERATE_ENUM(FMT_6_5_5, 5)
+    GENERATE_ENUM(FMT_8_8_8_8, 6)
+    GENERATE_ENUM(FMT_2_10_10_10, 7)
+    GENERATE_ENUM(FMT_8_A, 8)
+    GENERATE_ENUM(FMT_8_B, 9)
+    GENERATE_ENUM(FMT_8_8, 10)
+    GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11)
+    GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12)
+    GENERATE_ENUM(FMT_5_5_5_1, 13)
+    GENERATE_ENUM(FMT_8_8_8_8_A, 14)
+    GENERATE_ENUM(FMT_4_4_4_4, 15)
+    GENERATE_ENUM(FMT_8_8_8, 16)
+    GENERATE_ENUM(FMT_DXT1, 18)
+    GENERATE_ENUM(FMT_DXT2_3, 19)
+    GENERATE_ENUM(FMT_DXT4_5, 20)
+    GENERATE_ENUM(FMT_10_10_10_2, 21)
+    GENERATE_ENUM(FMT_24_8, 22)
+    GENERATE_ENUM(FMT_16, 24)
+    GENERATE_ENUM(FMT_16_16, 25)
+    GENERATE_ENUM(FMT_16_16_16_16, 26)
+    GENERATE_ENUM(FMT_16_EXPAND, 27)
+    GENERATE_ENUM(FMT_16_16_EXPAND, 28)
+    GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29)
+    GENERATE_ENUM(FMT_16_FLOAT, 30)
+    GENERATE_ENUM(FMT_16_16_FLOAT, 31)
+    GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(FMT_32, 33)
+    GENERATE_ENUM(FMT_32_32, 34)
+    GENERATE_ENUM(FMT_32_32_32_32, 35)
+    GENERATE_ENUM(FMT_32_FLOAT, 36)
+    GENERATE_ENUM(FMT_32_32_FLOAT, 37)
+    GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(FMT_ATI_TC_RGB, 39)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA, 40)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44)
+    GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46)
+    GENERATE_ENUM(FMT_ETC1_RGB, 47)
+    GENERATE_ENUM(FMT_ETC1_RGBA, 48)
+    GENERATE_ENUM(FMT_DXN, 49)
+    GENERATE_ENUM(FMT_2_3_3, 51)
+    GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54)
+    GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55)
+    GENERATE_ENUM(FMT_32_32_32_FLOAT, 57)
+    GENERATE_ENUM(FMT_DXT3A, 58)
+    GENERATE_ENUM(FMT_DXT5A, 59)
+    GENERATE_ENUM(FMT_CTX1, 60)
+END_ENUMTYPE(SurfaceFormat)
+
+START_ENUMTYPE(SurfaceTiling)
+    GENERATE_ENUM(ARRAY_LINEAR, 0)
+    GENERATE_ENUM(ARRAY_TILED, 1)
+END_ENUMTYPE(SurfaceTiling)
+
+START_ENUMTYPE(SurfaceArray)
+    GENERATE_ENUM(ARRAY_1D, 0)
+    GENERATE_ENUM(ARRAY_2D, 1)
+    GENERATE_ENUM(ARRAY_3D, 2)
+    GENERATE_ENUM(ARRAY_3D_SLICE, 3)
+END_ENUMTYPE(SurfaceArray)
+
+START_ENUMTYPE(SurfaceNumberX)
+    GENERATE_ENUM(NUMBERX_UREPEAT, 0)
+    GENERATE_ENUM(NUMBERX_SREPEAT, 1)
+    GENERATE_ENUM(NUMBERX_UINTEGER, 2)
+    GENERATE_ENUM(NUMBERX_SINTEGER, 3)
+    GENERATE_ENUM(NUMBERX_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumberX)
+
+START_ENUMTYPE(ColorArrayX)
+    GENERATE_ENUM(ARRAYX_2D_COLOR, 0)
+    GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1)
+END_ENUMTYPE(ColorArrayX)
+
+
+
+
+// **************************************************************************
+// These are ones that had to be added in addition to what's generated
+// by the autoreg (in CSIM)
+// **************************************************************************
+START_ENUMTYPE(DXClipSpaceDef)
+    GENERATE_ENUM(DXCLIP_OPENGL, 0)
+    GENERATE_ENUM(DXCLIP_DIRECTX, 1)
+END_ENUMTYPE(DXClipSpaceDef)
+
+START_ENUMTYPE(PixCenter)
+    GENERATE_ENUM(PIXCENTER_D3D, 0)
+    GENERATE_ENUM(PIXCENTER_OGL, 1)
+END_ENUMTYPE(PixCenter)
+
+START_ENUMTYPE(RoundMode)
+    GENERATE_ENUM(TRUNCATE,   0)
+    GENERATE_ENUM(ROUND,      1)
+    GENERATE_ENUM(ROUNDTOEVEN,    2)
+    GENERATE_ENUM(ROUNDTOODD,     3)
+END_ENUMTYPE(RoundMode)
+
+START_ENUMTYPE(QuantMode)
+    GENERATE_ENUM(ONE_SIXTEENTH,   0)
+    GENERATE_ENUM(ONE_EIGHTH,      1)
+    GENERATE_ENUM(ONE_QUARTER,     2)
+    GENERATE_ENUM(ONE_HALF,    3)
+    GENERATE_ENUM(ONE,         4)
+END_ENUMTYPE(QuantMode)
+
+START_ENUMTYPE(FrontFace)
+    GENERATE_ENUM(FRONT_CCW,        0)
+    GENERATE_ENUM(FRONT_CW,     1)
+END_ENUMTYPE(FrontFace)
+
+START_ENUMTYPE(PolyMode)
+    GENERATE_ENUM(DISABLED,    0)
+    GENERATE_ENUM(DUALMODE,    1)
+END_ENUMTYPE(PolyMode)
+
+START_ENUMTYPE(PType)
+    GENERATE_ENUM(DRAW_POINTS,      0)
+    GENERATE_ENUM(DRAW_LINES,       1)
+    GENERATE_ENUM(DRAW_TRIANGLES,   2)
+END_ENUMTYPE(PType)
+
+START_ENUMTYPE(MSAANumSamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     3)
+END_ENUMTYPE(MSAANumSamples)
+
+START_ENUMTYPE(PatternBitOrder)
+    GENERATE_ENUM(LITTLE,   0)
+    GENERATE_ENUM(BIG,      1)
+END_ENUMTYPE(PatternBitOrder)
+
+START_ENUMTYPE(AutoResetCntl)
+    GENERATE_ENUM(NEVER,        0)
+    GENERATE_ENUM(EACHPRIMITIVE,    1)
+    GENERATE_ENUM(EACHPACKET,       2)
+END_ENUMTYPE(AutoResetCntl)
+
+START_ENUMTYPE(ParamShade)
+    GENERATE_ENUM(FLAT,     0)
+    GENERATE_ENUM(GOURAUD,  1)
+END_ENUMTYPE(ParamShade)
+
+START_ENUMTYPE(SamplingPattern)
+    GENERATE_ENUM(CENTROID, 0)
+    GENERATE_ENUM(PIXCENTER, 1)
+END_ENUMTYPE(SamplingPattern)
+
+START_ENUMTYPE(MSAASamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     2)
+END_ENUMTYPE(MSAASamples)
+
+START_ENUMTYPE(CopySampleSelect)
+    GENERATE_ENUM(SAMPLE_0, 0)
+    GENERATE_ENUM(SAMPLE_1, 1)
+    GENERATE_ENUM(SAMPLE_2, 2)
+    GENERATE_ENUM(SAMPLE_3, 3)
+    GENERATE_ENUM(SAMPLE_01,    4)
+    GENERATE_ENUM(SAMPLE_23,    5)
+    GENERATE_ENUM(SAMPLE_0123,  6)
+END_ENUMTYPE(CopySampleSelect)
+
+
+#undef START_ENUMTYPE
+#undef GENERATE_ENUM
+#undef END_ENUMTYPE
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h
new file mode 100644
index 000000000000..f7efe31bc8a8
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h
@@ -0,0 +1,3404 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_REGISTER(PA_CL_VPORT_XSCALE)
+    GENERATE_FIELD(VPORT_XSCALE, float)
+END_REGISTER(PA_CL_VPORT_XSCALE)
+
+START_REGISTER(PA_CL_VPORT_XOFFSET)
+    GENERATE_FIELD(VPORT_XOFFSET, float)
+END_REGISTER(PA_CL_VPORT_XOFFSET)
+
+START_REGISTER(PA_CL_VPORT_YSCALE)
+    GENERATE_FIELD(VPORT_YSCALE, float)
+END_REGISTER(PA_CL_VPORT_YSCALE)
+
+START_REGISTER(PA_CL_VPORT_YOFFSET)
+    GENERATE_FIELD(VPORT_YOFFSET, float)
+END_REGISTER(PA_CL_VPORT_YOFFSET)
+
+START_REGISTER(PA_CL_VPORT_ZSCALE)
+    GENERATE_FIELD(VPORT_ZSCALE, float)
+END_REGISTER(PA_CL_VPORT_ZSCALE)
+
+START_REGISTER(PA_CL_VPORT_ZOFFSET)
+    GENERATE_FIELD(VPORT_ZOFFSET, float)
+END_REGISTER(PA_CL_VPORT_ZOFFSET)
+
+START_REGISTER(PA_CL_VTE_CNTL)
+    GENERATE_FIELD(PERFCOUNTER_REF, bool)
+    GENERATE_FIELD(VTX_W0_FMT, bool)
+    GENERATE_FIELD(VTX_Z_FMT, bool)
+    GENERATE_FIELD(VTX_XY_FMT, bool)
+    GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_X_SCALE_ENA, bool)
+END_REGISTER(PA_CL_VTE_CNTL)
+
+START_REGISTER(PA_CL_CLIP_CNTL)
+    GENERATE_FIELD(W_NAN_RETAIN, bool)
+    GENERATE_FIELD(Z_NAN_RETAIN, bool)
+    GENERATE_FIELD(XY_NAN_RETAIN, bool)
+    GENERATE_FIELD(VTX_KILL_OR, bool)
+    GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool)
+    GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef)
+    GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool)
+    GENERATE_FIELD(CLIP_DISABLE, bool)
+END_REGISTER(PA_CL_CLIP_CNTL)
+
+START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+
+START_REGISTER(PA_CL_ENHANCE)
+    GENERATE_FIELD(ECO_SPARE0, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool)
+END_REGISTER(PA_CL_ENHANCE)
+
+START_REGISTER(PA_SC_ENHANCE)
+    GENERATE_FIELD(ECO_SPARE0, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE3, int)
+END_REGISTER(PA_SC_ENHANCE)
+
+START_REGISTER(PA_SU_VTX_CNTL)
+    GENERATE_FIELD(QUANT_MODE, QuantMode)
+    GENERATE_FIELD(ROUND_MODE, RoundMode)
+    GENERATE_FIELD(PIX_CENTER, PixCenter)
+END_REGISTER(PA_SU_VTX_CNTL)
+
+START_REGISTER(PA_SU_POINT_SIZE)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+    GENERATE_FIELD(HEIGHT, fixed12_4)
+END_REGISTER(PA_SU_POINT_SIZE)
+
+START_REGISTER(PA_SU_POINT_MINMAX)
+    GENERATE_FIELD(MAX_SIZE, fixed12_4)
+    GENERATE_FIELD(MIN_SIZE, fixed12_4)
+END_REGISTER(PA_SU_POINT_MINMAX)
+
+START_REGISTER(PA_SU_LINE_CNTL)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_LINE_CNTL)
+
+START_REGISTER(PA_SU_FACE_DATA)
+    GENERATE_FIELD(BASE_ADDR, int)
+END_REGISTER(PA_SU_FACE_DATA)
+
+START_REGISTER(PA_SU_SC_MODE_CNTL)
+    GENERATE_FIELD(FACE_WRITE_ENABLE, bool)
+    GENERATE_FIELD(FACE_KILL_ENABLE, bool)
+    GENERATE_FIELD(ZERO_AREA_FACENESS, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool)
+    GENERATE_FIELD(QUAD_ORDER_ENABLE, bool)
+    GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool)
+    GENERATE_FIELD(PERSP_CORR_DIS, bool)
+    GENERATE_FIELD(PROVOKING_VTX_LAST, bool)
+    GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool)
+    GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool)
+    GENERATE_FIELD(MSAA_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool)
+    GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType)
+    GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType)
+    GENERATE_FIELD(POLY_MODE, PolyMode)
+    GENERATE_FIELD(FACE, FrontFace)
+    GENERATE_FIELD(CULL_BACK, bool)
+    GENERATE_FIELD(CULL_FRONT, bool)
+END_REGISTER(PA_SU_SC_MODE_CNTL)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT)
+END_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_HI)
+
+START_REGISTER(PA_SC_WINDOW_OFFSET)
+    GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15)
+    GENERATE_FIELD(WINDOW_X_OFFSET, signedint15)
+END_REGISTER(PA_SC_WINDOW_OFFSET)
+
+START_REGISTER(PA_SC_AA_CONFIG)
+    GENERATE_FIELD(MAX_SAMPLE_DIST, int)
+    GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples)
+END_REGISTER(PA_SC_AA_CONFIG)
+
+START_REGISTER(PA_SC_AA_MASK)
+    GENERATE_FIELD(AA_MASK, hex)
+END_REGISTER(PA_SC_AA_MASK)
+
+START_REGISTER(PA_SC_LINE_STIPPLE)
+    GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl)
+    GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder)
+    GENERATE_FIELD(REPEAT_COUNT, intMinusOne)
+    GENERATE_FIELD(LINE_PATTERN, hex)
+END_REGISTER(PA_SC_LINE_STIPPLE)
+
+START_REGISTER(PA_SC_LINE_CNTL)
+    GENERATE_FIELD(LAST_PIXEL, bool)
+    GENERATE_FIELD(EXPAND_LINE_WIDTH, bool)
+    GENERATE_FIELD(USE_BRES_CNTL, bool)
+    GENERATE_FIELD(BRES_CNTL, int)
+END_REGISTER(PA_SC_LINE_CNTL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+    GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool)
+    GENERATE_FIELD(TL_Y, int)
+    GENERATE_FIELD(TL_X, int)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+    GENERATE_FIELD(BR_Y, int)
+    GENERATE_FIELD(BR_X, int)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+    GENERATE_FIELD(TL_Y, int)
+    GENERATE_FIELD(TL_X, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+    GENERATE_FIELD(BR_Y, int)
+    GENERATE_FIELD(BR_X, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+
+START_REGISTER(PA_SC_VIZ_QUERY)
+    GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool)
+    GENERATE_FIELD(VIZ_QUERY_ID, int)
+    GENERATE_FIELD(VIZ_QUERY_ENA, bool)
+END_REGISTER(PA_SC_VIZ_QUERY)
+
+START_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+    GENERATE_FIELD(STATUS_BITS, hex)
+END_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+
+START_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+    GENERATE_FIELD(CURRENT_COUNT, int)
+    GENERATE_FIELD(CURRENT_PTR, int)
+END_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT)
+END_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_CL_CNTL_STATUS)
+    GENERATE_FIELD(CL_BUSY, int)
+END_REGISTER(PA_CL_CNTL_STATUS)
+
+START_REGISTER(PA_SU_CNTL_STATUS)
+    GENERATE_FIELD(SU_BUSY, int)
+END_REGISTER(PA_SU_CNTL_STATUS)
+
+START_REGISTER(PA_SC_CNTL_STATUS)
+    GENERATE_FIELD(SC_BUSY, int)
+END_REGISTER(PA_SC_CNTL_STATUS)
+
+START_REGISTER(PA_SU_DEBUG_CNTL)
+    GENERATE_FIELD(SU_DEBUG_INDX, int)
+END_REGISTER(PA_SU_DEBUG_CNTL)
+
+START_REGISTER(PA_SU_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(PA_SU_DEBUG_DATA)
+
+START_REGISTER(PA_SC_DEBUG_CNTL)
+    GENERATE_FIELD(SC_DEBUG_INDX, int)
+END_REGISTER(PA_SC_DEBUG_CNTL)
+
+START_REGISTER(PA_SC_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(PA_SC_DEBUG_DATA)
+
+START_REGISTER(GFX_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+END_REGISTER(GFX_COPY_STATE)
+
+START_REGISTER(VGT_DRAW_INITIATOR)
+    GENERATE_FIELD(NUM_INDICES, uint)
+    GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX)
+    GENERATE_FIELD(NOT_EOP, bool)
+    GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE)
+    GENERATE_FIELD(FACENESS_CULL_SELECT, VGT_DI_FACENESS_CULL_SELECT)
+    GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT)
+    GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE)
+END_REGISTER(VGT_DRAW_INITIATOR)
+
+START_REGISTER(VGT_EVENT_INITIATOR)
+    GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE)
+END_REGISTER(VGT_EVENT_INITIATOR)
+
+START_REGISTER(VGT_DMA_BASE)
+    GENERATE_FIELD(BASE_ADDR, uint)
+END_REGISTER(VGT_DMA_BASE)
+
+START_REGISTER(VGT_DMA_SIZE)
+    GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+END_REGISTER(VGT_DMA_SIZE)
+
+START_REGISTER(VGT_BIN_BASE)
+    GENERATE_FIELD(BIN_BASE_ADDR, uint)
+END_REGISTER(VGT_BIN_BASE)
+
+START_REGISTER(VGT_BIN_SIZE)
+    GENERATE_FIELD(FACENESS_RESET, int)
+    GENERATE_FIELD(FACENESS_FETCH, int)
+    GENERATE_FIELD(NUM_WORDS, uint)
+END_REGISTER(VGT_BIN_SIZE)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+    GENERATE_FIELD(GUARD_BAND, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(COLUMN, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+    GENERATE_FIELD(GUARD_BAND, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(COLUMN, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+
+START_REGISTER(VGT_IMMED_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_IMMED_DATA)
+
+START_REGISTER(VGT_MAX_VTX_INDX)
+    GENERATE_FIELD(MAX_INDX, int)
+END_REGISTER(VGT_MAX_VTX_INDX)
+
+START_REGISTER(VGT_MIN_VTX_INDX)
+    GENERATE_FIELD(MIN_INDX, int)
+END_REGISTER(VGT_MIN_VTX_INDX)
+
+START_REGISTER(VGT_INDX_OFFSET)
+    GENERATE_FIELD(INDX_OFFSET, int)
+END_REGISTER(VGT_INDX_OFFSET)
+
+START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+    GENERATE_FIELD(VTX_REUSE_DEPTH, int)
+END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+
+START_REGISTER(VGT_OUT_DEALLOC_CNTL)
+    GENERATE_FIELD(DEALLOC_DIST, int)
+END_REGISTER(VGT_OUT_DEALLOC_CNTL)
+
+START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+    GENERATE_FIELD(RESET_INDX, int)
+END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+
+START_REGISTER(VGT_ENHANCE)
+    GENERATE_FIELD(MISC, hex)
+END_REGISTER(VGT_ENHANCE)
+
+START_REGISTER(VGT_VTX_VECT_EJECT_REG)
+    GENERATE_FIELD(PRIM_COUNT, int)
+END_REGISTER(VGT_VTX_VECT_EJECT_REG)
+
+START_REGISTER(VGT_LAST_COPY_STATE)
+    GENERATE_FIELD(DST_STATE_ID, int)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+END_REGISTER(VGT_LAST_COPY_STATE)
+
+START_REGISTER(VGT_DEBUG_CNTL)
+    GENERATE_FIELD(VGT_DEBUG_INDX, int)
+END_REGISTER(VGT_DEBUG_CNTL)
+
+START_REGISTER(VGT_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_DEBUG_DATA)
+
+START_REGISTER(VGT_CNTL_STATUS)
+    GENERATE_FIELD(VGT_OUT_INDX_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_BUSY, int)
+    GENERATE_FIELD(VGT_PT_BUSY, int)
+    GENERATE_FIELD(VGT_BIN_BUSY, int)
+    GENERATE_FIELD(VGT_VR_BUSY, int)
+    GENERATE_FIELD(VGT_GRP_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_REQ_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY, int)
+END_REGISTER(VGT_CNTL_STATUS)
+
+START_REGISTER(VGT_CRC_SQ_DATA)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_DATA)
+
+START_REGISTER(VGT_CRC_SQ_CTRL)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_CTRL)
+
+START_REGISTER(VGT_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER0_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER1_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER2_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER3_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_HI)
+
+START_REGISTER(VGT_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_HI)
+
+START_REGISTER(VGT_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_HI)
+
+START_REGISTER(VGT_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_HI)
+
+START_REGISTER(TC_CNTL_STATUS)
+    GENERATE_FIELD(TC_BUSY, int)
+    GENERATE_FIELD(TC_L2_HIT_MISS, int)
+    GENERATE_FIELD(L2_INVALIDATE, int)
+END_REGISTER(TC_CNTL_STATUS)
+
+START_REGISTER(TCR_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCR_CHICKEN)
+
+START_REGISTER(TCF_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCF_CHICKEN)
+
+START_REGISTER(TCM_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+    GENERATE_FIELD(ETC_COLOR_ENDIAN, int)
+    GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int)
+END_REGISTER(TCM_CHICKEN)
+
+START_REGISTER(TCR_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER0_HI)
+
+START_REGISTER(TCR_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER1_HI)
+
+START_REGISTER(TCR_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCR_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER1_LOW)
+
+START_REGISTER(TP_TC_CLKGATE_CNTL)
+    GENERATE_FIELD(TC_BUSY_EXTEND, int)
+    GENERATE_FIELD(TP_BUSY_EXTEND, int)
+END_REGISTER(TP_TC_CLKGATE_CNTL)
+
+START_REGISTER(TPC_CNTL_STATUS)
+    GENERATE_FIELD(TPC_BUSY, int)
+    GENERATE_FIELD(TP_SQ_DEC, int)
+    GENERATE_FIELD(TA_TF_TC_FIFO_REN, int)
+    GENERATE_FIELD(TA_TF_RTS, int)
+    GENERATE_FIELD(TA_TB_RTR, int)
+    GENERATE_FIELD(TA_TB_TT_RTS, int)
+    GENERATE_FIELD(TA_TB_RTS, int)
+    GENERATE_FIELD(TW_TA_RTR, int)
+    GENERATE_FIELD(TW_TA_LAST_RTS, int)
+    GENERATE_FIELD(TW_TA_TT_RTS, int)
+    GENERATE_FIELD(TW_TA_RTS, int)
+    GENERATE_FIELD(TF_TW_RTR, int)
+    GENERATE_FIELD(TF_TW_STATE_RTS, int)
+    GENERATE_FIELD(TF_TW_RTS, int)
+    GENERATE_FIELD(TPC_BLEND_BUSY, int)
+    GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_BUSY, int)
+    GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_INPUT_BUSY, int)
+END_REGISTER(TPC_CNTL_STATUS)
+
+START_REGISTER(TPC_DEBUG0)
+    GENERATE_FIELD(SQ_TP_WAKEUP, int)
+    GENERATE_FIELD(TPC_CLK_EN, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(ALIGNER_STATE, int)
+    GENERATE_FIELD(WALKER_STATE, int)
+    GENERATE_FIELD(PREV_TC_STATE_VALID, int)
+    GENERATE_FIELD(ALIGNER_CNTL, int)
+    GENERATE_FIELD(WALKER_CNTL, int)
+    GENERATE_FIELD(IC_CTR, int)
+    GENERATE_FIELD(LOD_CNTL, int)
+END_REGISTER(TPC_DEBUG0)
+
+START_REGISTER(TPC_DEBUG1)
+    GENERATE_FIELD(UNUSED, int)
+END_REGISTER(TPC_DEBUG1)
+
+START_REGISTER(TPC_CHICKEN)
+    GENERATE_FIELD(SPARE, int)
+    GENERATE_FIELD(BLEND_PRECISION, int)
+END_REGISTER(TPC_CHICKEN)
+
+START_REGISTER(TP0_CNTL_STATUS)
+    GENERATE_FIELD(TP_BUSY, int)
+    GENERATE_FIELD(TB_TO_RTS, int)
+    GENERATE_FIELD(TB_TT_TT_RESET, int)
+    GENERATE_FIELD(TB_TT_RTS, int)
+    GENERATE_FIELD(TF_TB_TT_RTS, int)
+    GENERATE_FIELD(TF_TB_RTS, int)
+    GENERATE_FIELD(AL_TF_TT_RTS, int)
+    GENERATE_FIELD(AL_TF_RTS, int)
+    GENERATE_FIELD(FA_AL_TT_RTS, int)
+    GENERATE_FIELD(FA_AL_RTS, int)
+    GENERATE_FIELD(TA_FA_TT_RTS, int)
+    GENERATE_FIELD(TA_FA_RTS, int)
+    GENERATE_FIELD(FL_TA_RTS, int)
+    GENERATE_FIELD(LA_FL_RTS, int)
+    GENERATE_FIELD(LC_LA_RTS, int)
+    GENERATE_FIELD(IN_LC_RTS, int)
+    GENERATE_FIELD(TP_OUTPUT_BUSY, int)
+    GENERATE_FIELD(TP_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_HICOLOR_BUSY, int)
+    GENERATE_FIELD(TP_TT_BUSY, int)
+    GENERATE_FIELD(TP_CH_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_FETCH_BUSY, int)
+    GENERATE_FIELD(TP_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ADDR_BUSY, int)
+    GENERATE_FIELD(TP_LOD_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_LOD_BUSY, int)
+    GENERATE_FIELD(TP_INPUT_BUSY, int)
+END_REGISTER(TP0_CNTL_STATUS)
+
+START_REGISTER(TP0_DEBUG)
+    GENERATE_FIELD(Q_ALIGNER_CNTL, int)
+    GENERATE_FIELD(Q_WALKER_CNTL, int)
+    GENERATE_FIELD(TP_CLK_EN, int)
+    GENERATE_FIELD(PERF_CLK_EN, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int)
+    GENERATE_FIELD(Q_SQ_TP_WAKEUP, int)
+    GENERATE_FIELD(Q_LOD_CNTL, int)
+END_REGISTER(TP0_DEBUG)
+
+START_REGISTER(TP0_CHICKEN)
+    GENERATE_FIELD(SPARE, int)
+    GENERATE_FIELD(VFETCH_ADDRESS_MODE, int)
+    GENERATE_FIELD(TT_MODE, int)
+END_REGISTER(TP0_CHICKEN)
+
+START_REGISTER(TP0_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT)
+END_REGISTER(TP0_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER0_HI)
+
+START_REGISTER(TP0_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER0_LOW)
+
+START_REGISTER(TP0_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, int)
+END_REGISTER(TP0_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER1_HI)
+
+START_REGISTER(TP0_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER0_HI)
+
+START_REGISTER(TCM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER1_HI)
+
+START_REGISTER(TCM_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER2_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER3_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER4_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER4_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER5_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER5_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER6_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER6_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER7_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER7_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER8_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER8_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER9_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER9_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER10_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER10_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER11_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER11_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER0_HI)
+
+START_REGISTER(TCF_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER1_HI)
+
+START_REGISTER(TCF_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER2_HI)
+
+START_REGISTER(TCF_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER3_HI)
+
+START_REGISTER(TCF_PERFCOUNTER4_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER4_HI)
+
+START_REGISTER(TCF_PERFCOUNTER5_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER5_HI)
+
+START_REGISTER(TCF_PERFCOUNTER6_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER6_HI)
+
+START_REGISTER(TCF_PERFCOUNTER7_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER7_HI)
+
+START_REGISTER(TCF_PERFCOUNTER8_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER8_HI)
+
+START_REGISTER(TCF_PERFCOUNTER9_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER9_HI)
+
+START_REGISTER(TCF_PERFCOUNTER10_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER10_HI)
+
+START_REGISTER(TCF_PERFCOUNTER11_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER11_HI)
+
+START_REGISTER(TCF_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER2_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER3_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER4_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER4_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER5_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER5_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER6_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER6_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER7_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER7_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER8_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER8_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER9_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER9_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER10_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER10_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER11_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER11_LOW)
+
+START_REGISTER(TCF_DEBUG)
+    GENERATE_FIELD(tca_rts, int)
+    GENERATE_FIELD(tca_state_rts, int)
+    GENERATE_FIELD(not_TPC_rtr, int)
+    GENERATE_FIELD(TPC_full, int)
+    GENERATE_FIELD(TP0_full, int)
+    GENERATE_FIELD(PF0_stall, int)
+    GENERATE_FIELD(TCA_TCB_stall, int)
+    GENERATE_FIELD(TCB_miss_stall, int)
+    GENERATE_FIELD(TCB_ff_stall, int)
+    GENERATE_FIELD(not_TCB_TCO_rtr, int)
+    GENERATE_FIELD(not_FG0_rtr, int)
+    GENERATE_FIELD(TC_MH_send, int)
+    GENERATE_FIELD(not_MH_TC_rtr, int)
+END_REGISTER(TCF_DEBUG)
+
+START_REGISTER(TCA_FIFO_DEBUG)
+    GENERATE_FIELD(FW_tpc_rts, int)
+    GENERATE_FIELD(not_FW_tpc_rtr, int)
+    GENERATE_FIELD(FW_rts0, int)
+    GENERATE_FIELD(not_FW_rtr0, int)
+    GENERATE_FIELD(FW_full, int)
+    GENERATE_FIELD(load_tp_fifos, int)
+    GENERATE_FIELD(load_tpc_fifo, int)
+    GENERATE_FIELD(tpc_full, int)
+    GENERATE_FIELD(tp0_full, int)
+END_REGISTER(TCA_FIFO_DEBUG)
+
+START_REGISTER(TCA_PROBE_DEBUG)
+    GENERATE_FIELD(ProbeFilter_stall, int)
+END_REGISTER(TCA_PROBE_DEBUG)
+
+START_REGISTER(TCA_TPC_DEBUG)
+    GENERATE_FIELD(capture_tca_rts, int)
+    GENERATE_FIELD(captue_state_rts, int)
+END_REGISTER(TCA_TPC_DEBUG)
+
+START_REGISTER(TCB_CORE_DEBUG)
+    GENERATE_FIELD(sector_format512, int)
+    GENERATE_FIELD(sector_format, int)
+    GENERATE_FIELD(format, int)
+    GENERATE_FIELD(opcode, int)
+    GENERATE_FIELD(tiled, int)
+    GENERATE_FIELD(access512, int)
+END_REGISTER(TCB_CORE_DEBUG)
+
+START_REGISTER(TCB_TAG0_DEBUG)
+    GENERATE_FIELD(max_misses, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(mem_read_cycle, int)
+END_REGISTER(TCB_TAG0_DEBUG)
+
+START_REGISTER(TCB_TAG1_DEBUG)
+    GENERATE_FIELD(max_misses, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(mem_read_cycle, int)
+END_REGISTER(TCB_TAG1_DEBUG)
+
+START_REGISTER(TCB_TAG2_DEBUG)
+    GENERATE_FIELD(max_misses, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(mem_read_cycle, int)
+END_REGISTER(TCB_TAG2_DEBUG)
+
+START_REGISTER(TCB_TAG3_DEBUG)
+    GENERATE_FIELD(max_misses, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(mem_read_cycle, int)
+END_REGISTER(TCB_TAG3_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+    GENERATE_FIELD(valid_left_q, int)
+    GENERATE_FIELD(sector_mask_left_q, int)
+    GENERATE_FIELD(sector_mask_left_count_q, int)
+    GENERATE_FIELD(update_left, int)
+    GENERATE_FIELD(no_sectors_to_go, int)
+    GENERATE_FIELD(one_sector_to_go_left_q, int)
+    GENERATE_FIELD(fg0_sends_left, int)
+    GENERATE_FIELD(left_done, int)
+END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+    GENERATE_FIELD(setquads_to_send, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(ff_fg_type512, int)
+    GENERATE_FIELD(right_eq_left, int)
+    GENERATE_FIELD(set_sel_left, int)
+    GENERATE_FIELD(quad_sel_left, int)
+END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+    GENERATE_FIELD(arb_RTR, int)
+    GENERATE_FIELD(valid_q, int)
+    GENERATE_FIELD(mc_sel_q, int)
+    GENERATE_FIELD(ga_busy, int)
+    GENERATE_FIELD(fgo_busy, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(tc_arb_request_type, int)
+    GENERATE_FIELD(tc_arb_fmsopcode, int)
+    GENERATE_FIELD(tc_arb_format, int)
+    GENERATE_FIELD(ga_out_rts, int)
+    GENERATE_FIELD(tc0_arb_rts, int)
+END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+
+START_REGISTER(TCD_INPUT0_DEBUG)
+    GENERATE_FIELD(ipbuf_busy, int)
+    GENERATE_FIELD(ipbuf_dxt_send, int)
+    GENERATE_FIELD(ip_send, int)
+    GENERATE_FIELD(last_send_q1, int)
+    GENERATE_FIELD(cnt_q1, int)
+    GENERATE_FIELD(valid_q1, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(empty, int)
+END_REGISTER(TCD_INPUT0_DEBUG)
+
+START_REGISTER(TCD_DEGAMMA_DEBUG)
+    GENERATE_FIELD(dgmm_pstate, int)
+    GENERATE_FIELD(dgmm_stall, int)
+    GENERATE_FIELD(dgmm_ctrl_send, int)
+    GENERATE_FIELD(dgmm_ctrl_last_send, int)
+    GENERATE_FIELD(dgmm_ctrl_dgmm8, int)
+    GENERATE_FIELD(dgmm_ftfconv_dgmmen, int)
+END_REGISTER(TCD_DEGAMMA_DEBUG)
+
+START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+    GENERATE_FIELD(dcmp_mux_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_last_send, int)
+    GENERATE_FIELD(dxtc_sctrarb_send, int)
+    GENERATE_FIELD(sctrmx0_sctrarb_rts, int)
+    GENERATE_FIELD(sctrarb_multcyl_send, int)
+    GENERATE_FIELD(dxtc_rtr, int)
+    GENERATE_FIELD(sctrmx_rtr, int)
+    GENERATE_FIELD(pstate, int)
+END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+
+START_REGISTER(TCD_DXTC_ARB_DEBUG)
+    GENERATE_FIELD(n0_dxt2_4_types, int)
+    GENERATE_FIELD(arb_dcmp01_send, int)
+    GENERATE_FIELD(arb_dcmp01_format, int)
+    GENERATE_FIELD(arb_dcmp01_cacheline, int)
+    GENERATE_FIELD(arb_dcmp01_sector, int)
+    GENERATE_FIELD(arb_dcmp01_cnt, int)
+    GENERATE_FIELD(arb_dcmp01_last_send, int)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(n0_stall, int)
+END_REGISTER(TCD_DXTC_ARB_DEBUG)
+
+START_REGISTER(TCD_STALLS_DEBUG)
+    GENERATE_FIELD(not_incoming_rtr, int)
+    GENERATE_FIELD(not_mux_dcmp_rtr, int)
+    GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int)
+    GENERATE_FIELD(not_dcmp0_arb_rtr, int)
+    GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int)
+    GENERATE_FIELD(not_multcyl_sctrarb_rtr, int)
+END_REGISTER(TCD_STALLS_DEBUG)
+
+START_REGISTER(TCO_STALLS_DEBUG)
+    GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int)
+    GENERATE_FIELD(quad0_rl_sg_RTR, int)
+    GENERATE_FIELD(quad0_sg_crd_RTR, int)
+END_REGISTER(TCO_STALLS_DEBUG)
+
+START_REGISTER(TCO_QUAD0_DEBUG0)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(all_sectors_written_set0, int)
+    GENERATE_FIELD(all_sectors_written_set1, int)
+    GENERATE_FIELD(all_sectors_written_set2, int)
+    GENERATE_FIELD(all_sectors_written_set3, int)
+    GENERATE_FIELD(cache_read_RTR, int)
+    GENERATE_FIELD(read_cache_q, int)
+    GENERATE_FIELD(stageN1_valid_q, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_end_of_sample, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_end_of_sample, int)
+    GENERATE_FIELD(rl_sg_sector_format, int)
+END_REGISTER(TCO_QUAD0_DEBUG0)
+
+START_REGISTER(TCO_QUAD0_DEBUG1)
+    GENERATE_FIELD(TCO_TCB_read_xfc, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(TCB_TCO_xfc_q, int)
+    GENERATE_FIELD(TCB_TCO_rtr_d, int)
+    GENERATE_FIELD(tco_quad_pipe_busy, int)
+    GENERATE_FIELD(input_quad_busy, int)
+    GENERATE_FIELD(latency_fifo_busy, int)
+    GENERATE_FIELD(cache_read_busy, int)
+    GENERATE_FIELD(fifo_read_ptr, int)
+    GENERATE_FIELD(fifo_write_ptr, int)
+    GENERATE_FIELD(write_enable, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(fifo_busy, int)
+END_REGISTER(TCO_QUAD0_DEBUG1)
+
+START_REGISTER(SQ_GPR_MANAGEMENT)
+    GENERATE_FIELD(REG_SIZE_VTX, int)
+    GENERATE_FIELD(REG_SIZE_PIX, int)
+    GENERATE_FIELD(REG_DYNAMIC, int)
+END_REGISTER(SQ_GPR_MANAGEMENT)
+
+START_REGISTER(SQ_FLOW_CONTROL)
+    GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int)
+    GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int)
+    GENERATE_FIELD(POS_EXP_PRIORITY, int)
+    GENERATE_FIELD(NO_CFS_EJECT, int)
+    GENERATE_FIELD(NO_ARB_EJECT, int)
+    GENERATE_FIELD(ALU_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(VC_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int)
+    GENERATE_FIELD(NO_LOOP_EXIT, int)
+    GENERATE_FIELD(NO_PV_PS, int)
+    GENERATE_FIELD(CF_WR_BASE, hex)
+    GENERATE_FIELD(ONE_ALU, int)
+    GENERATE_FIELD(ONE_THREAD, int)
+    GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int)
+END_REGISTER(SQ_FLOW_CONTROL)
+
+START_REGISTER(SQ_INST_STORE_MANAGMENT)
+    GENERATE_FIELD(INST_BASE_VTX, int)
+    GENERATE_FIELD(INST_BASE_PIX, int)
+END_REGISTER(SQ_INST_STORE_MANAGMENT)
+
+START_REGISTER(SQ_RESOURCE_MANAGMENT)
+    GENERATE_FIELD(EXPORT_BUF_ENTRIES, int)
+    GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int)
+END_REGISTER(SQ_RESOURCE_MANAGMENT)
+
+START_REGISTER(SQ_EO_RT)
+    GENERATE_FIELD(EO_TSTATE_RT, int)
+    GENERATE_FIELD(EO_CONSTANTS_RT, int)
+END_REGISTER(SQ_EO_RT)
+
+START_REGISTER(SQ_DEBUG_MISC)
+    GENERATE_FIELD(DB_WEN_MEMORY_3, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_2, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_1, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_0, int)
+    GENERATE_FIELD(DB_READ_MEMORY, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DB_READ_CTX, int)
+    GENERATE_FIELD(DB_TSTATE_SIZE, int)
+    GENERATE_FIELD(DB_ALUCST_SIZE, int)
+END_REGISTER(SQ_DEBUG_MISC)
+
+START_REGISTER(SQ_ACTIVITY_METER_CNTL)
+    GENERATE_FIELD(SPARE, int)
+    GENERATE_FIELD(THRESHOLD_HIGH, int)
+    GENERATE_FIELD(THRESHOLD_LOW, int)
+    GENERATE_FIELD(TIMEBASE, int)
+END_REGISTER(SQ_ACTIVITY_METER_CNTL)
+
+START_REGISTER(SQ_ACTIVITY_METER_STATUS)
+    GENERATE_FIELD(PERCENT_BUSY, int)
+END_REGISTER(SQ_ACTIVITY_METER_STATUS)
+
+START_REGISTER(SQ_INPUT_ARB_PRIORITY)
+    GENERATE_FIELD(THRESHOLD, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+END_REGISTER(SQ_INPUT_ARB_PRIORITY)
+
+START_REGISTER(SQ_THREAD_ARB_PRIORITY)
+    GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int)
+    GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(THRESHOLD, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+END_REGISTER(SQ_THREAD_ARB_PRIORITY)
+
+START_REGISTER(SQ_VS_WATCHDOG_TIMER)
+    GENERATE_FIELD(TIMEOUT_COUNT, int)
+    GENERATE_FIELD(ENABLE, int)
+END_REGISTER(SQ_VS_WATCHDOG_TIMER)
+
+START_REGISTER(SQ_PS_WATCHDOG_TIMER)
+    GENERATE_FIELD(TIMEOUT_COUNT, int)
+    GENERATE_FIELD(ENABLE, int)
+END_REGISTER(SQ_PS_WATCHDOG_TIMER)
+
+START_REGISTER(SQ_INT_CNTL)
+    GENERATE_FIELD(VS_WATCHDOG_MASK, int)
+    GENERATE_FIELD(PS_WATCHDOG_MASK, int)
+END_REGISTER(SQ_INT_CNTL)
+
+START_REGISTER(SQ_INT_STATUS)
+    GENERATE_FIELD(VS_WATCHDOG_TIMEOUT, int)
+    GENERATE_FIELD(PS_WATCHDOG_TIMEOUT, int)
+END_REGISTER(SQ_INT_STATUS)
+
+START_REGISTER(SQ_INT_ACK)
+    GENERATE_FIELD(VS_WATCHDOG_ACK, int)
+    GENERATE_FIELD(PS_WATCHDOG_ACK, int)
+END_REGISTER(SQ_INT_ACK)
+
+START_REGISTER(SQ_DEBUG_INPUT_FSM)
+    GENERATE_FIELD(PC_GPR_SIZE, int)
+    GENERATE_FIELD(PC_INTERP_CNT, int)
+    GENERATE_FIELD(PC_AS, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PC_PISM, int)
+    GENERATE_FIELD(VC_GPR_LD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VC_VSR_LD, int)
+END_REGISTER(SQ_DEBUG_INPUT_FSM)
+
+START_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+    GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(TEX_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(ALU_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(ALU_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(TEX_CONST_EVENT_STATE, int)
+END_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+
+START_REGISTER(SQ_DEBUG_TP_FSM)
+    GENERATE_FIELD(ARB_TR_TP, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(FCS_TP, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(FCR_TP, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(GS_TP, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(TIS_TP, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(IF_TP, int)
+    GENERATE_FIELD(CF_TP, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(EX_TP, int)
+END_REGISTER(SQ_DEBUG_TP_FSM)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_0)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(EX_ALU_0, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_0)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_1)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(EX_ALU_0, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_1)
+
+START_REGISTER(SQ_DEBUG_EXP_ALLOC)
+    GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(EA_BUF_AVAIL, int)
+    GENERATE_FIELD(COLOR_BUF_AVAIL, int)
+    GENERATE_FIELD(POS_BUF_AVAIL, int)
+END_REGISTER(SQ_DEBUG_EXP_ALLOC)
+
+START_REGISTER(SQ_DEBUG_PTR_BUFF)
+    GENERATE_FIELD(VTX_SYNC_CNT, int)
+    GENERATE_FIELD(EF_EMPTY, int)
+    GENERATE_FIELD(PRIM_TYPE_POLYGON, int)
+    GENERATE_FIELD(QUAL_EVENT, int)
+    GENERATE_FIELD(SC_EVENT_ID, int)
+    GENERATE_FIELD(EVENT_CONTEXT_ID, int)
+    GENERATE_FIELD(QUAL_NEW_VECTOR, int)
+    GENERATE_FIELD(DEALLOC_CNT, int)
+    GENERATE_FIELD(END_OF_BUFFER, int)
+END_REGISTER(SQ_DEBUG_PTR_BUFF)
+
+START_REGISTER(SQ_DEBUG_GPR_VTX)
+    GENERATE_FIELD(VTX_FREE, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(VTX_MAX, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(VTX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VTX_TAIL_PTR, int)
+END_REGISTER(SQ_DEBUG_GPR_VTX)
+
+START_REGISTER(SQ_DEBUG_GPR_PIX)
+    GENERATE_FIELD(PIX_FREE, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(PIX_MAX, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(PIX_TAIL_PTR, int)
+END_REGISTER(SQ_DEBUG_GPR_PIX)
+
+START_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+    GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int)
+    GENERATE_FIELD(VC_THREAD_BUF_DLY, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int)
+END_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_0)
+    GENERATE_FIELD(BUSY_Q, int)
+    GENERATE_FIELD(SX_EVENT_FULL, int)
+    GENERATE_FIELD(NXT_PC_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_POS_ALLOC_CNT, int)
+    GENERATE_FIELD(FULL_CNT_Q, int)
+    GENERATE_FIELD(TAIL_PTR_Q, int)
+    GENERATE_FIELD(VTX_HEAD_PTR_Q, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_0)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_1)
+    GENERATE_FIELD(VS_DONE_PTR, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_1)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+    GENERATE_FIELD(VS_STATUS_REG, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+    GENERATE_FIELD(VS_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_0)
+    GENERATE_FIELD(BUSY, int)
+    GENERATE_FIELD(NXT_PIX_EXP_CNT, int)
+    GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int)
+    GENERATE_FIELD(FULL_CNT, int)
+    GENERATE_FIELD(TAIL_PTR, int)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_0, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_1, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_2, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_3, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+    GENERATE_FIELD(PIX_TB_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+
+START_REGISTER(SQ_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT)
+END_REGISTER(SQ_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER1_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER2_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER3_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_HI)
+
+START_REGISTER(SQ_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_HI)
+
+START_REGISTER(SQ_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_HI)
+
+START_REGISTER(SX_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT)
+END_REGISTER(SX_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SX_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_LOW)
+
+START_REGISTER(SX_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_0)
+    GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode)
+    GENERATE_FIELD(SCALAR_CLAMP, int)
+    GENERATE_FIELD(VECTOR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_WRT_MSK, int)
+    GENERATE_FIELD(VECTOR_WRT_MSK, int)
+    GENERATE_FIELD(EXPORT_DATA, Exporting)
+    GENERATE_FIELD(SCALAR_DST_REL, int)
+    GENERATE_FIELD(SCALAR_RESULT, int)
+    GENERATE_FIELD(LOW_PRECISION_16B_FP, int)
+    GENERATE_FIELD(VECTOR_DST_REL, Abs_modifier)
+    GENERATE_FIELD(VECTOR_RESULT, int)
+END_REGISTER(SQ_INSTRUCTION_ALU_0)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_1)
+    GENERATE_FIELD(CONST_0_REL_ABS, int)
+    GENERATE_FIELD(CONST_1_REL_ABS, int)
+    GENERATE_FIELD(RELATIVE_ADDR, int)
+    GENERATE_FIELD(PRED_SELECT, PredicateSelect)
+    GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType)
+END_REGISTER(SQ_INSTRUCTION_ALU_1)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_2)
+    GENERATE_FIELD(SRC_A_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_B_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_C_SEL, OperandSelect0)
+    GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode)
+    GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier)
+    GENERATE_FIELD(REG_SELECT_A, OperandSelect1)
+    GENERATE_FIELD(SRC_A_REG_PTR, int)
+    GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier)
+    GENERATE_FIELD(REG_SELECT_B, OperandSelect1)
+    GENERATE_FIELD(SRC_B_REG_PTR, int)
+    GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier)
+    GENERATE_FIELD(REG_SELECT_C, OperandSelect1)
+    GENERATE_FIELD(SRC_C_REG_PTR, int)
+END_REGISTER(SQ_INSTRUCTION_ALU_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(YIELD, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ADDRESS, int)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+    GENERATE_FIELD(YIELD, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(ADDRESS, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(RESERVED_0, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(LOOP_ID, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(PREDICATED_JMP, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(ADDRESS, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+    GENERATE_FIELD(RESERVED_2, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(RESERVED_0, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(RESERVED_0, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+    GENERATE_FIELD(SRC_SEL_Z, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Y, SrcSel)
+    GENERATE_FIELD(SRC_SEL_X, SrcSel)
+    GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(FETCH_VALID_ONLY, int)
+    GENERATE_FIELD(DST_GPR_AM, Addressmode)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, Addressmode)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(OPCODE, TexInstOpcode)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+    GENERATE_FIELD(PRED_SELECT, PredSelect)
+    GENERATE_FIELD(USE_REG_LOD, int)
+    GENERATE_FIELD(USE_COMP_LOD, int)
+    GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter)
+    GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter)
+    GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter)
+    GENERATE_FIELD(ANISO_FILTER, AnisoFilter)
+    GENERATE_FIELD(MIP_FILTER, MipFilter)
+    GENERATE_FIELD(MIN_FILTER, MinFilter)
+    GENERATE_FIELD(MAG_FILTER, MagFilter)
+    GENERATE_FIELD(DST_SEL_W, DstSel)
+    GENERATE_FIELD(DST_SEL_Z, DstSel)
+    GENERATE_FIELD(DST_SEL_Y, DstSel)
+    GENERATE_FIELD(DST_SEL_X, DstSel)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+    GENERATE_FIELD(PRED_CONDITION, int)
+    GENERATE_FIELD(OFFSET_Z, int)
+    GENERATE_FIELD(OFFSET_Y, int)
+    GENERATE_FIELD(OFFSET_X, int)
+    GENERATE_FIELD(UNUSED, int)
+    GENERATE_FIELD(LOD_BIAS, int)
+    GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation)
+    GENERATE_FIELD(USE_REG_GRADIENTS, int)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+    GENERATE_FIELD(SRC_SEL, int)
+    GENERATE_FIELD(CONST_INDEX_SEL, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(MUST_BE_ONE, int)
+    GENERATE_FIELD(DST_GPR_AM, int)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, int)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(OPCODE, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+    GENERATE_FIELD(PRED_SELECT, int)
+    GENERATE_FIELD(EXP_ADJUST_ALL, int)
+    GENERATE_FIELD(DATA_FORMAT, int)
+    GENERATE_FIELD(SIGNED_RF_MODE_ALL, int)
+    GENERATE_FIELD(NUM_FORMAT_ALL, int)
+    GENERATE_FIELD(FORMAT_COMP_ALL, int)
+    GENERATE_FIELD(DST_SEL_W, int)
+    GENERATE_FIELD(DST_SEL_Z, int)
+    GENERATE_FIELD(DST_SEL_Y, int)
+    GENERATE_FIELD(DST_SEL_X, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+    GENERATE_FIELD(PRED_CONDITION, int)
+    GENERATE_FIELD(OFFSET, int)
+    GENERATE_FIELD(STRIDE, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+
+START_REGISTER(SQ_CONSTANT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_0)
+
+START_REGISTER(SQ_CONSTANT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_1)
+
+START_REGISTER(SQ_CONSTANT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_2)
+
+START_REGISTER(SQ_CONSTANT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_3)
+
+START_REGISTER(SQ_FETCH_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_0)
+
+START_REGISTER(SQ_FETCH_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_1)
+
+START_REGISTER(SQ_FETCH_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_2)
+
+START_REGISTER(SQ_FETCH_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_3)
+
+START_REGISTER(SQ_FETCH_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_4)
+
+START_REGISTER(SQ_FETCH_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_5)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_0)
+    GENERATE_FIELD(BASE_ADDRESS, hex)
+    GENERATE_FIELD(STATE, int)
+    GENERATE_FIELD(TYPE, int)
+END_REGISTER(SQ_CONSTANT_VFETCH_0)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_1)
+    GENERATE_FIELD(LIMIT_ADDRESS, hex)
+    GENERATE_FIELD(ENDIAN_SWAP, int)
+END_REGISTER(SQ_CONSTANT_VFETCH_1)
+
+START_REGISTER(SQ_CONSTANT_T2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T2)
+
+START_REGISTER(SQ_CONSTANT_T3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T3)
+
+START_REGISTER(SQ_CF_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+END_REGISTER(SQ_CF_BOOLEANS)
+
+START_REGISTER(SQ_CF_LOOP)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+END_REGISTER(SQ_CF_LOOP)
+
+START_REGISTER(SQ_CONSTANT_RT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_RT_0)
+
+START_REGISTER(SQ_CONSTANT_RT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_RT_1)
+
+START_REGISTER(SQ_CONSTANT_RT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_RT_2)
+
+START_REGISTER(SQ_CONSTANT_RT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_0)
+
+START_REGISTER(SQ_FETCH_RT_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_1)
+
+START_REGISTER(SQ_FETCH_RT_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_2)
+
+START_REGISTER(SQ_FETCH_RT_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_4)
+
+START_REGISTER(SQ_FETCH_RT_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_5)
+
+START_REGISTER(SQ_CF_RT_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+END_REGISTER(SQ_CF_RT_BOOLEANS)
+
+START_REGISTER(SQ_CF_RT_LOOP)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+END_REGISTER(SQ_CF_RT_LOOP)
+
+START_REGISTER(SQ_VS_PROGRAM)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(SQ_VS_PROGRAM)
+
+START_REGISTER(SQ_PS_PROGRAM)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(SQ_PS_PROGRAM)
+
+START_REGISTER(SQ_CF_PROGRAM_SIZE)
+    GENERATE_FIELD(PS_CF_SIZE, int)
+    GENERATE_FIELD(VS_CF_SIZE, int)
+END_REGISTER(SQ_CF_PROGRAM_SIZE)
+
+START_REGISTER(SQ_INTERPOLATOR_CNTL)
+    GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern)
+    GENERATE_FIELD(PARAM_SHADE, ParamShade)
+END_REGISTER(SQ_INTERPOLATOR_CNTL)
+
+START_REGISTER(SQ_PROGRAM_CNTL)
+    GENERATE_FIELD(GEN_INDEX_VTX, int)
+    GENERATE_FIELD(PS_EXPORT_MODE, int)
+    GENERATE_FIELD(VS_EXPORT_MODE, VertexMode)
+    GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne)
+    GENERATE_FIELD(GEN_INDEX_PIX, int)
+    GENERATE_FIELD(PARAM_GEN, int)
+    GENERATE_FIELD(PS_RESOURCE, int)
+    GENERATE_FIELD(VS_RESOURCE, int)
+    GENERATE_FIELD(PS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(VS_NUM_REG, intMinusOne)
+END_REGISTER(SQ_PROGRAM_CNTL)
+
+START_REGISTER(SQ_WRAPPING_0)
+    GENERATE_FIELD(PARAM_WRAP_7, hex)
+    GENERATE_FIELD(PARAM_WRAP_6, hex)
+    GENERATE_FIELD(PARAM_WRAP_5, hex)
+    GENERATE_FIELD(PARAM_WRAP_4, hex)
+    GENERATE_FIELD(PARAM_WRAP_3, hex)
+    GENERATE_FIELD(PARAM_WRAP_2, hex)
+    GENERATE_FIELD(PARAM_WRAP_1, hex)
+    GENERATE_FIELD(PARAM_WRAP_0, hex)
+END_REGISTER(SQ_WRAPPING_0)
+
+START_REGISTER(SQ_WRAPPING_1)
+    GENERATE_FIELD(PARAM_WRAP_15, hex)
+    GENERATE_FIELD(PARAM_WRAP_14, hex)
+    GENERATE_FIELD(PARAM_WRAP_13, hex)
+    GENERATE_FIELD(PARAM_WRAP_12, hex)
+    GENERATE_FIELD(PARAM_WRAP_11, hex)
+    GENERATE_FIELD(PARAM_WRAP_10, hex)
+    GENERATE_FIELD(PARAM_WRAP_9, hex)
+    GENERATE_FIELD(PARAM_WRAP_8, hex)
+END_REGISTER(SQ_WRAPPING_1)
+
+START_REGISTER(SQ_VS_CONST)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(SQ_VS_CONST)
+
+START_REGISTER(SQ_PS_CONST)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(SQ_PS_CONST)
+
+START_REGISTER(SQ_CONTEXT_MISC)
+    GENERATE_FIELD(TX_CACHE_SEL, int)
+    GENERATE_FIELD(YEILD_OPTIMIZE, int)
+    GENERATE_FIELD(PERFCOUNTER_REF, int)
+    GENERATE_FIELD(PARAM_GEN_POS, int)
+    GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl)
+    GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int)
+    GENERATE_FIELD(INST_PRED_OPTIMIZE, int)
+END_REGISTER(SQ_CONTEXT_MISC)
+
+START_REGISTER(SQ_CF_RD_BASE)
+    GENERATE_FIELD(RD_BASE, hex)
+END_REGISTER(SQ_CF_RD_BASE)
+
+START_REGISTER(SQ_DEBUG_MISC_0)
+    GENERATE_FIELD(DB_PROB_COUNT, int)
+    GENERATE_FIELD(DB_PROB_ADDR, int)
+    GENERATE_FIELD(DB_PROB_BREAK, int)
+    GENERATE_FIELD(DB_PROB_ON, int)
+END_REGISTER(SQ_DEBUG_MISC_0)
+
+START_REGISTER(SQ_DEBUG_MISC_1)
+    GENERATE_FIELD(DB_BREAK_ADDR, int)
+    GENERATE_FIELD(DB_INST_COUNT, int)
+    GENERATE_FIELD(DB_ON_VTX, int)
+    GENERATE_FIELD(DB_ON_PIX, int)
+END_REGISTER(SQ_DEBUG_MISC_1)
+
+START_REGISTER(MH_ARBITER_CONFIG)
+    GENERATE_FIELD(PA_CLNT_ENABLE, bool)
+    GENERATE_FIELD(RB_CLNT_ENABLE, bool)
+    GENERATE_FIELD(TC_CLNT_ENABLE, bool)
+    GENERATE_FIELD(VGT_CLNT_ENABLE, bool)
+    GENERATE_FIELD(CP_CLNT_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT, int)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool)
+    GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool)
+    GENERATE_FIELD(TC_REORDER_ENABLE, bool)
+    GENERATE_FIELD(PAGE_SIZE, int)
+    GENERATE_FIELD(L2_ARB_CONTROL, int)
+    GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int)
+    GENERATE_FIELD(L1_ARB_ENABLE, bool)
+    GENERATE_FIELD(SAME_PAGE_GRANULARITY, int)
+    GENERATE_FIELD(SAME_PAGE_LIMIT, int)
+END_REGISTER(MH_ARBITER_CONFIG)
+
+START_REGISTER(MH_CLNT_AXI_ID_REUSE)
+    GENERATE_FIELD(PAw_ID, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(MMUr_ID, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(RBw_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(CPw_ID, int)
+END_REGISTER(MH_CLNT_AXI_ID_REUSE)
+
+START_REGISTER(MH_INTERRUPT_MASK)
+    GENERATE_FIELD(MMU_PAGE_FAULT, bool)
+    GENERATE_FIELD(AXI_WRITE_ERROR, bool)
+    GENERATE_FIELD(AXI_READ_ERROR, bool)
+END_REGISTER(MH_INTERRUPT_MASK)
+
+START_REGISTER(MH_INTERRUPT_STATUS)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+END_REGISTER(MH_INTERRUPT_STATUS)
+
+START_REGISTER(MH_INTERRUPT_CLEAR)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+END_REGISTER(MH_INTERRUPT_CLEAR)
+
+START_REGISTER(MH_AXI_ERROR)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ID, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_READ_ID, int)
+END_REGISTER(MH_AXI_ERROR)
+
+START_REGISTER(MH_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER0_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER1_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER0_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER0_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER1_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER1_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER0_LOW)
+
+START_REGISTER(MH_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER1_LOW)
+
+START_REGISTER(MH_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER0_HI)
+
+START_REGISTER(MH_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER1_HI)
+
+START_REGISTER(MH_DEBUG_CTRL)
+    GENERATE_FIELD(INDEX, int)
+END_REGISTER(MH_DEBUG_CTRL)
+
+START_REGISTER(MH_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(MH_DEBUG_DATA)
+
+START_REGISTER(MH_AXI_HALT_CONTROL)
+    GENERATE_FIELD(AXI_HALT, bool)
+END_REGISTER(MH_AXI_HALT_CONTROL)
+
+START_REGISTER(MH_MMU_CONFIG)
+    GENERATE_FIELD(PA_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(SPLIT_MODE_ENABLE, bool)
+    GENERATE_FIELD(MMU_ENABLE, bool)
+END_REGISTER(MH_MMU_CONFIG)
+
+START_REGISTER(MH_MMU_VA_RANGE)
+    GENERATE_FIELD(VA_BASE, int)
+    GENERATE_FIELD(NUM_64KB_REGIONS, int)
+END_REGISTER(MH_MMU_VA_RANGE)
+
+START_REGISTER(MH_MMU_PT_BASE)
+    GENERATE_FIELD(PT_BASE, int)
+END_REGISTER(MH_MMU_PT_BASE)
+
+START_REGISTER(MH_MMU_PAGE_FAULT)
+    GENERATE_FIELD(REQ_VA, int)
+    GENERATE_FIELD(WRITE_PROTECTION_ERROR, int)
+    GENERATE_FIELD(READ_PROTECTION_ERROR, int)
+    GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(AXI_ID, int)
+    GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(OP_TYPE, int)
+    GENERATE_FIELD(PAGE_FAULT, int)
+END_REGISTER(MH_MMU_PAGE_FAULT)
+
+START_REGISTER(MH_MMU_TRAN_ERROR)
+    GENERATE_FIELD(TRAN_ERROR, int)
+END_REGISTER(MH_MMU_TRAN_ERROR)
+
+START_REGISTER(MH_MMU_INVALIDATE)
+    GENERATE_FIELD(INVALIDATE_TC, int)
+    GENERATE_FIELD(INVALIDATE_ALL, int)
+END_REGISTER(MH_MMU_INVALIDATE)
+
+START_REGISTER(MH_MMU_MPU_BASE)
+    GENERATE_FIELD(MPU_BASE, int)
+END_REGISTER(MH_MMU_MPU_BASE)
+
+START_REGISTER(MH_MMU_MPU_END)
+    GENERATE_FIELD(MPU_END, int)
+END_REGISTER(MH_MMU_MPU_END)
+
+START_REGISTER(WAIT_UNTIL)
+    GENERATE_FIELD(CMDFIFO_ENTRIES, int)
+    GENERATE_FIELD(WAIT_3D_IDLECLEAN, int)
+    GENERATE_FIELD(WAIT_2D_IDLECLEAN, int)
+    GENERATE_FIELD(WAIT_3D_IDLE, int)
+    GENERATE_FIELD(WAIT_2D_IDLE, int)
+    GENERATE_FIELD(WAIT_CMDFIFO, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID2, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID1, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID0, int)
+    GENERATE_FIELD(WAIT_VSYNC, int)
+    GENERATE_FIELD(WAIT_FE_VSYNC, int)
+    GENERATE_FIELD(WAIT_RE_VSYNC, int)
+END_REGISTER(WAIT_UNTIL)
+
+START_REGISTER(RBBM_ISYNC_CNTL)
+    GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int)
+    GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int)
+END_REGISTER(RBBM_ISYNC_CNTL)
+
+START_REGISTER(RBBM_STATUS)
+    GENERATE_FIELD(GUI_ACTIVE, int)
+    GENERATE_FIELD(RB_CNTX_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX0_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX17_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(PA_BUSY, int)
+    GENERATE_FIELD(SC_CNTX_BUSY, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+    GENERATE_FIELD(SX_BUSY, int)
+    GENERATE_FIELD(MH_COHERENCY_BUSY, int)
+    GENERATE_FIELD(MH_BUSY, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(RBBM_WU_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY_NO_DMA, int)
+    GENERATE_FIELD(PFRQ_PENDING, int)
+    GENERATE_FIELD(CFRQ_PENDING, int)
+    GENERATE_FIELD(CPRQ_PENDING, int)
+    GENERATE_FIELD(HIRQ_PENDING, int)
+    GENERATE_FIELD(TC_BUSY, int)
+    GENERATE_FIELD(CMDFIFO_AVAIL, int)
+END_REGISTER(RBBM_STATUS)
+
+START_REGISTER(RBBM_DSPLY)
+    GENERATE_FIELD(DMI_CH4_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH4_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH3_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH3_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CHANNEL_SELECT, int)
+    GENERATE_FIELD(DMI_CH2_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH2_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH1_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH1_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID0, int)
+    GENERATE_FIELD(SEL_DMI_VSYNC_VALID, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID2, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID1, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID0, int)
+END_REGISTER(RBBM_DSPLY)
+
+START_REGISTER(RBBM_RENDER_LATEST)
+    GENERATE_FIELD(DMI_CH4_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH3_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH2_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH1_BUFFER_ID, int)
+END_REGISTER(RBBM_RENDER_LATEST)
+
+START_REGISTER(RBBM_RTL_RELEASE)
+    GENERATE_FIELD(CHANGELIST, int)
+END_REGISTER(RBBM_RTL_RELEASE)
+
+START_REGISTER(RBBM_PATCH_RELEASE)
+    GENERATE_FIELD(CUSTOMER_ID, int)
+    GENERATE_FIELD(PATCH_SELECTION, int)
+    GENERATE_FIELD(PATCH_REVISION, int)
+END_REGISTER(RBBM_PATCH_RELEASE)
+
+START_REGISTER(RBBM_AUXILIARY_CONFIG)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(RBBM_AUXILIARY_CONFIG)
+
+START_REGISTER(RBBM_PERIPHID0)
+    GENERATE_FIELD(PARTNUMBER0, int)
+END_REGISTER(RBBM_PERIPHID0)
+
+START_REGISTER(RBBM_PERIPHID1)
+    GENERATE_FIELD(DESIGNER0, int)
+    GENERATE_FIELD(PARTNUMBER1, int)
+END_REGISTER(RBBM_PERIPHID1)
+
+START_REGISTER(RBBM_PERIPHID2)
+    GENERATE_FIELD(REVISION, int)
+    GENERATE_FIELD(DESIGNER1, int)
+END_REGISTER(RBBM_PERIPHID2)
+
+START_REGISTER(RBBM_PERIPHID3)
+    GENERATE_FIELD(CONTINUATION, int)
+    GENERATE_FIELD(MH_INTERFACE, int)
+    GENERATE_FIELD(GARB_SLAVE_INTERFACE, int)
+    GENERATE_FIELD(RBBM_HOST_INTERFACE, int)
+END_REGISTER(RBBM_PERIPHID3)
+
+START_REGISTER(RBBM_CNTL)
+    GENERATE_FIELD(REGCLK_DEASSERT_TIME, int)
+    GENERATE_FIELD(READ_TIMEOUT, int)
+END_REGISTER(RBBM_CNTL)
+
+START_REGISTER(RBBM_SKEW_CNTL)
+    GENERATE_FIELD(SKEW_COUNT, int)
+    GENERATE_FIELD(SKEW_TOP_THRESHOLD, int)
+END_REGISTER(RBBM_SKEW_CNTL)
+
+START_REGISTER(RBBM_SOFT_RESET)
+    GENERATE_FIELD(SOFT_RESET_VGT, int)
+    GENERATE_FIELD(SOFT_RESET_SC, int)
+    GENERATE_FIELD(SOFT_RESET_CIB, int)
+    GENERATE_FIELD(SOFT_RESET_SX, int)
+    GENERATE_FIELD(SOFT_RESET_SQ, int)
+    GENERATE_FIELD(SOFT_RESET_BC, int)
+    GENERATE_FIELD(SOFT_RESET_MH, int)
+    GENERATE_FIELD(SOFT_RESET_PA, int)
+    GENERATE_FIELD(SOFT_RESET_CP, int)
+END_REGISTER(RBBM_SOFT_RESET)
+
+START_REGISTER(RBBM_PM_OVERRIDE1)
+    GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE1)
+
+START_REGISTER(RBBM_PM_OVERRIDE2)
+    GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int)
+    GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE2)
+
+START_REGISTER(GC_SYS_IDLE)
+    GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_URGENT_RAMP_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI, int)
+    GENERATE_FIELD(GC_SYS_URGENT_RAMP, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI_MASK, int)
+    GENERATE_FIELD(GC_SYS_IDLE_DELAY, int)
+END_REGISTER(GC_SYS_IDLE)
+
+START_REGISTER(NQWAIT_UNTIL)
+    GENERATE_FIELD(WAIT_GUI_IDLE, int)
+END_REGISTER(NQWAIT_UNTIL)
+
+START_REGISTER(RBBM_DEBUG_OUT)
+    GENERATE_FIELD(DEBUG_BUS_OUT, int)
+END_REGISTER(RBBM_DEBUG_OUT)
+
+START_REGISTER(RBBM_DEBUG_CNTL)
+    GENERATE_FIELD(GPIO_BYTE_LANE_ENB, int)
+    GENERATE_FIELD(GPIO_SUB_BLOCK_SEL, int)
+    GENERATE_FIELD(GPIO_SUB_BLOCK_ADDR, int)
+    GENERATE_FIELD(SW_ENABLE, int)
+    GENERATE_FIELD(SUB_BLOCK_SEL, int)
+    GENERATE_FIELD(SUB_BLOCK_ADDR, int)
+END_REGISTER(RBBM_DEBUG_CNTL)
+
+START_REGISTER(RBBM_DEBUG)
+    GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int)
+    GENERATE_FIELD(SQ_RBBM_NRTRTR, int)
+    GENERATE_FIELD(VGT_RBBM_NRTRTR, int)
+    GENERATE_FIELD(CP_RBBM_NRTRTR, int)
+    GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_RTR_FOR_HI, int)
+    GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_WU, int)
+    GENERATE_FIELD(IGNORE_RTR, int)
+END_REGISTER(RBBM_DEBUG)
+
+START_REGISTER(RBBM_READ_ERROR)
+    GENERATE_FIELD(READ_ERROR, int)
+    GENERATE_FIELD(READ_REQUESTER, int)
+    GENERATE_FIELD(READ_ADDRESS, int)
+END_REGISTER(RBBM_READ_ERROR)
+
+START_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+    GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int)
+END_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+
+START_REGISTER(RBBM_INT_CNTL)
+    GENERATE_FIELD(GUI_IDLE_INT_MASK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int)
+    GENERATE_FIELD(RDERR_INT_MASK, int)
+END_REGISTER(RBBM_INT_CNTL)
+
+START_REGISTER(RBBM_INT_STATUS)
+    GENERATE_FIELD(GUI_IDLE_INT_STAT, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int)
+    GENERATE_FIELD(RDERR_INT_STAT, int)
+END_REGISTER(RBBM_INT_STATUS)
+
+START_REGISTER(RBBM_INT_ACK)
+    GENERATE_FIELD(GUI_IDLE_INT_ACK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int)
+    GENERATE_FIELD(RDERR_INT_ACK, int)
+END_REGISTER(RBBM_INT_ACK)
+
+START_REGISTER(MASTER_INT_SIGNAL)
+    GENERATE_FIELD(RBBM_INT_STAT, int)
+    GENERATE_FIELD(CP_INT_STAT, int)
+    GENERATE_FIELD(SQ_INT_STAT, int)
+    GENERATE_FIELD(MH_INT_STAT, int)
+END_REGISTER(MASTER_INT_SIGNAL)
+
+START_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL)
+END_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(RBBM_PERFCOUNTER1_LO)
+    GENERATE_FIELD(PERF_COUNT1_LO, int)
+END_REGISTER(RBBM_PERFCOUNTER1_LO)
+
+START_REGISTER(RBBM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT1_HI, int)
+END_REGISTER(RBBM_PERFCOUNTER1_HI)
+
+START_REGISTER(CP_RB_BASE)
+    GENERATE_FIELD(RB_BASE, int)
+END_REGISTER(CP_RB_BASE)
+
+START_REGISTER(CP_RB_CNTL)
+    GENERATE_FIELD(RB_RPTR_WR_ENA, int)
+    GENERATE_FIELD(RB_NO_UPDATE, int)
+    GENERATE_FIELD(RB_POLL_EN, int)
+    GENERATE_FIELD(BUF_SWAP, int)
+    GENERATE_FIELD(RB_BLKSZ, int)
+    GENERATE_FIELD(RB_BUFSZ, int)
+END_REGISTER(CP_RB_CNTL)
+
+START_REGISTER(CP_RB_RPTR_ADDR)
+    GENERATE_FIELD(RB_RPTR_ADDR, int)
+    GENERATE_FIELD(RB_RPTR_SWAP, int)
+END_REGISTER(CP_RB_RPTR_ADDR)
+
+START_REGISTER(CP_RB_RPTR)
+    GENERATE_FIELD(RB_RPTR, int)
+END_REGISTER(CP_RB_RPTR)
+
+START_REGISTER(CP_RB_RPTR_WR)
+    GENERATE_FIELD(RB_RPTR_WR, int)
+END_REGISTER(CP_RB_RPTR_WR)
+
+START_REGISTER(CP_RB_WPTR)
+    GENERATE_FIELD(RB_WPTR, int)
+END_REGISTER(CP_RB_WPTR)
+
+START_REGISTER(CP_RB_WPTR_DELAY)
+    GENERATE_FIELD(PRE_WRITE_LIMIT, int)
+    GENERATE_FIELD(PRE_WRITE_TIMER, int)
+END_REGISTER(CP_RB_WPTR_DELAY)
+
+START_REGISTER(CP_RB_WPTR_BASE)
+    GENERATE_FIELD(RB_WPTR_BASE, int)
+    GENERATE_FIELD(RB_WPTR_SWAP, int)
+END_REGISTER(CP_RB_WPTR_BASE)
+
+START_REGISTER(CP_IB1_BASE)
+    GENERATE_FIELD(IB1_BASE, int)
+END_REGISTER(CP_IB1_BASE)
+
+START_REGISTER(CP_IB1_BUFSZ)
+    GENERATE_FIELD(IB1_BUFSZ, int)
+END_REGISTER(CP_IB1_BUFSZ)
+
+START_REGISTER(CP_IB2_BASE)
+    GENERATE_FIELD(IB2_BASE, int)
+END_REGISTER(CP_IB2_BASE)
+
+START_REGISTER(CP_IB2_BUFSZ)
+    GENERATE_FIELD(IB2_BUFSZ, int)
+END_REGISTER(CP_IB2_BUFSZ)
+
+START_REGISTER(CP_ST_BASE)
+    GENERATE_FIELD(ST_BASE, int)
+END_REGISTER(CP_ST_BASE)
+
+START_REGISTER(CP_ST_BUFSZ)
+    GENERATE_FIELD(ST_BUFSZ, int)
+END_REGISTER(CP_ST_BUFSZ)
+
+START_REGISTER(CP_QUEUE_THRESHOLDS)
+    GENERATE_FIELD(CSQ_ST_START, int)
+    GENERATE_FIELD(CSQ_IB2_START, int)
+    GENERATE_FIELD(CSQ_IB1_START, int)
+END_REGISTER(CP_QUEUE_THRESHOLDS)
+
+START_REGISTER(CP_MEQ_THRESHOLDS)
+    GENERATE_FIELD(ROQ_END, int)
+    GENERATE_FIELD(MEQ_END, int)
+END_REGISTER(CP_MEQ_THRESHOLDS)
+
+START_REGISTER(CP_CSQ_AVAIL)
+    GENERATE_FIELD(CSQ_CNT_IB2, int)
+    GENERATE_FIELD(CSQ_CNT_IB1, int)
+    GENERATE_FIELD(CSQ_CNT_RING, int)
+END_REGISTER(CP_CSQ_AVAIL)
+
+START_REGISTER(CP_STQ_AVAIL)
+    GENERATE_FIELD(STQ_CNT_ST, int)
+END_REGISTER(CP_STQ_AVAIL)
+
+START_REGISTER(CP_MEQ_AVAIL)
+    GENERATE_FIELD(MEQ_CNT, int)
+END_REGISTER(CP_MEQ_AVAIL)
+
+START_REGISTER(CP_CSQ_RB_STAT)
+    GENERATE_FIELD(CSQ_WPTR_PRIMARY, int)
+    GENERATE_FIELD(CSQ_RPTR_PRIMARY, int)
+END_REGISTER(CP_CSQ_RB_STAT)
+
+START_REGISTER(CP_CSQ_IB1_STAT)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int)
+END_REGISTER(CP_CSQ_IB1_STAT)
+
+START_REGISTER(CP_CSQ_IB2_STAT)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int)
+END_REGISTER(CP_CSQ_IB2_STAT)
+
+START_REGISTER(CP_NON_PREFETCH_CNTRS)
+    GENERATE_FIELD(IB2_COUNTER, int)
+    GENERATE_FIELD(IB1_COUNTER, int)
+END_REGISTER(CP_NON_PREFETCH_CNTRS)
+
+START_REGISTER(CP_STQ_ST_STAT)
+    GENERATE_FIELD(STQ_WPTR_ST, int)
+    GENERATE_FIELD(STQ_RPTR_ST, int)
+END_REGISTER(CP_STQ_ST_STAT)
+
+START_REGISTER(CP_MEQ_STAT)
+    GENERATE_FIELD(MEQ_WPTR, int)
+    GENERATE_FIELD(MEQ_RPTR, int)
+END_REGISTER(CP_MEQ_STAT)
+
+START_REGISTER(CP_MIU_TAG_STAT)
+    GENERATE_FIELD(INVALID_RETURN_TAG, int)
+    GENERATE_FIELD(TAG_17_STAT, int)
+    GENERATE_FIELD(TAG_16_STAT, int)
+    GENERATE_FIELD(TAG_15_STAT, int)
+    GENERATE_FIELD(TAG_14_STAT, int)
+    GENERATE_FIELD(TAG_13_STAT, int)
+    GENERATE_FIELD(TAG_12_STAT, int)
+    GENERATE_FIELD(TAG_11_STAT, int)
+    GENERATE_FIELD(TAG_10_STAT, int)
+    GENERATE_FIELD(TAG_9_STAT, int)
+    GENERATE_FIELD(TAG_8_STAT, int)
+    GENERATE_FIELD(TAG_7_STAT, int)
+    GENERATE_FIELD(TAG_6_STAT, int)
+    GENERATE_FIELD(TAG_5_STAT, int)
+    GENERATE_FIELD(TAG_4_STAT, int)
+    GENERATE_FIELD(TAG_3_STAT, int)
+    GENERATE_FIELD(TAG_2_STAT, int)
+    GENERATE_FIELD(TAG_1_STAT, int)
+    GENERATE_FIELD(TAG_0_STAT, int)
+END_REGISTER(CP_MIU_TAG_STAT)
+
+START_REGISTER(CP_CMD_INDEX)
+    GENERATE_FIELD(CMD_QUEUE_SEL, int)
+    GENERATE_FIELD(CMD_INDEX, int)
+END_REGISTER(CP_CMD_INDEX)
+
+START_REGISTER(CP_CMD_DATA)
+    GENERATE_FIELD(CMD_DATA, int)
+END_REGISTER(CP_CMD_DATA)
+
+START_REGISTER(CP_ME_CNTL)
+    GENERATE_FIELD(PROG_CNT_SIZE, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(ME_HALT, int)
+    GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(ME_STATMUX, int)
+END_REGISTER(CP_ME_CNTL)
+
+START_REGISTER(CP_ME_STATUS)
+    GENERATE_FIELD(ME_DEBUG_DATA, int)
+END_REGISTER(CP_ME_STATUS)
+
+START_REGISTER(CP_ME_RAM_WADDR)
+    GENERATE_FIELD(ME_RAM_WADDR, int)
+END_REGISTER(CP_ME_RAM_WADDR)
+
+START_REGISTER(CP_ME_RAM_RADDR)
+    GENERATE_FIELD(ME_RAM_RADDR, int)
+END_REGISTER(CP_ME_RAM_RADDR)
+
+START_REGISTER(CP_ME_RAM_DATA)
+    GENERATE_FIELD(ME_RAM_DATA, int)
+END_REGISTER(CP_ME_RAM_DATA)
+
+START_REGISTER(CP_ME_RDADDR)
+    GENERATE_FIELD(ME_RDADDR, int)
+END_REGISTER(CP_ME_RDADDR)
+
+START_REGISTER(CP_DEBUG)
+    GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int)
+    GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int)
+    GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int)
+    GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int)
+    GENERATE_FIELD(PREFETCH_PASS_NOPS, int)
+    GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int)
+    GENERATE_FIELD(PROG_END_PTR_ENABLE, int)
+    GENERATE_FIELD(PREDICATE_DISABLE, int)
+    GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int)
+END_REGISTER(CP_DEBUG)
+
+START_REGISTER(SCRATCH_REG0)
+    GENERATE_FIELD(SCRATCH_REG0, int)
+END_REGISTER(SCRATCH_REG0)
+
+START_REGISTER(SCRATCH_REG1)
+    GENERATE_FIELD(SCRATCH_REG1, int)
+END_REGISTER(SCRATCH_REG1)
+
+START_REGISTER(SCRATCH_REG2)
+    GENERATE_FIELD(SCRATCH_REG2, int)
+END_REGISTER(SCRATCH_REG2)
+
+START_REGISTER(SCRATCH_REG3)
+    GENERATE_FIELD(SCRATCH_REG3, int)
+END_REGISTER(SCRATCH_REG3)
+
+START_REGISTER(SCRATCH_REG4)
+    GENERATE_FIELD(SCRATCH_REG4, int)
+END_REGISTER(SCRATCH_REG4)
+
+START_REGISTER(SCRATCH_REG5)
+    GENERATE_FIELD(SCRATCH_REG5, int)
+END_REGISTER(SCRATCH_REG5)
+
+START_REGISTER(SCRATCH_REG6)
+    GENERATE_FIELD(SCRATCH_REG6, int)
+END_REGISTER(SCRATCH_REG6)
+
+START_REGISTER(SCRATCH_REG7)
+    GENERATE_FIELD(SCRATCH_REG7, int)
+END_REGISTER(SCRATCH_REG7)
+
+START_REGISTER(SCRATCH_UMSK)
+    GENERATE_FIELD(SCRATCH_SWAP, int)
+    GENERATE_FIELD(SCRATCH_UMSK, int)
+END_REGISTER(SCRATCH_UMSK)
+
+START_REGISTER(SCRATCH_ADDR)
+    GENERATE_FIELD(SCRATCH_ADDR, hex)
+END_REGISTER(SCRATCH_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_SRC)
+    GENERATE_FIELD(VS_DONE_CNTR, int)
+    GENERATE_FIELD(VS_DONE_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_SRC)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR)
+    GENERATE_FIELD(VS_DONE_ADDR, int)
+    GENERATE_FIELD(VS_DONE_SWAP, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA)
+    GENERATE_FIELD(VS_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(VS_DONE_ADDR_SWM, int)
+    GENERATE_FIELD(VS_DONE_SWAP_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+    GENERATE_FIELD(VS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_SRC)
+    GENERATE_FIELD(PS_DONE_CNTR, int)
+    GENERATE_FIELD(PS_DONE_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_SRC)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR)
+    GENERATE_FIELD(PS_DONE_ADDR, int)
+    GENERATE_FIELD(PS_DONE_SWAP, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA)
+    GENERATE_FIELD(PS_DONE_DATA, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(PS_DONE_ADDR_SWM, int)
+    GENERATE_FIELD(PS_DONE_SWAP_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+    GENERATE_FIELD(PS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_CF_EVENT_SRC)
+    GENERATE_FIELD(CF_DONE_SRC, int)
+END_REGISTER(CP_ME_CF_EVENT_SRC)
+
+START_REGISTER(CP_ME_CF_EVENT_ADDR)
+    GENERATE_FIELD(CF_DONE_ADDR, int)
+    GENERATE_FIELD(CF_DONE_SWAP, int)
+END_REGISTER(CP_ME_CF_EVENT_ADDR)
+
+START_REGISTER(CP_ME_CF_EVENT_DATA)
+    GENERATE_FIELD(CF_DONE_DATA, int)
+END_REGISTER(CP_ME_CF_EVENT_DATA)
+
+START_REGISTER(CP_ME_NRT_ADDR)
+    GENERATE_FIELD(NRT_WRITE_ADDR, int)
+    GENERATE_FIELD(NRT_WRITE_SWAP, int)
+END_REGISTER(CP_ME_NRT_ADDR)
+
+START_REGISTER(CP_ME_NRT_DATA)
+    GENERATE_FIELD(NRT_WRITE_DATA, int)
+END_REGISTER(CP_ME_NRT_DATA)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+    GENERATE_FIELD(VS_FETCH_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+    GENERATE_FIELD(VS_FETCH_DONE_ADDR, int)
+    GENERATE_FIELD(VS_FETCH_DONE_SWAP, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+    GENERATE_FIELD(VS_FETCH_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+
+START_REGISTER(CP_INT_CNTL)
+    GENERATE_FIELD(RB_INT_MASK, int)
+    GENERATE_FIELD(IB1_INT_MASK, int)
+    GENERATE_FIELD(IB2_INT_MASK, int)
+    GENERATE_FIELD(IB_ERROR_MASK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int)
+    GENERATE_FIELD(OPCODE_ERROR_MASK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int)
+    GENERATE_FIELD(SW_INT_MASK, int)
+END_REGISTER(CP_INT_CNTL)
+
+START_REGISTER(CP_INT_STATUS)
+    GENERATE_FIELD(RB_INT_STAT, int)
+    GENERATE_FIELD(IB1_INT_STAT, int)
+    GENERATE_FIELD(IB2_INT_STAT, int)
+    GENERATE_FIELD(IB_ERROR_STAT, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int)
+    GENERATE_FIELD(OPCODE_ERROR_STAT, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int)
+    GENERATE_FIELD(SW_INT_STAT, int)
+END_REGISTER(CP_INT_STATUS)
+
+START_REGISTER(CP_INT_ACK)
+    GENERATE_FIELD(RB_INT_ACK, int)
+    GENERATE_FIELD(IB1_INT_ACK, int)
+    GENERATE_FIELD(IB2_INT_ACK, int)
+    GENERATE_FIELD(IB_ERROR_ACK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int)
+    GENERATE_FIELD(OPCODE_ERROR_ACK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int)
+    GENERATE_FIELD(SW_INT_ACK, int)
+END_REGISTER(CP_INT_ACK)
+
+START_REGISTER(CP_PFP_UCODE_ADDR)
+    GENERATE_FIELD(UCODE_ADDR, hex)
+END_REGISTER(CP_PFP_UCODE_ADDR)
+
+START_REGISTER(CP_PFP_UCODE_DATA)
+    GENERATE_FIELD(UCODE_DATA, hex)
+END_REGISTER(CP_PFP_UCODE_DATA)
+
+START_REGISTER(CP_PERFMON_CNTL)
+    GENERATE_FIELD(PERFMON_ENABLE_MODE, int)
+    GENERATE_FIELD(PERFMON_STATE, int)
+END_REGISTER(CP_PERFMON_CNTL)
+
+START_REGISTER(CP_PERFCOUNTER_SELECT)
+    GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL)
+END_REGISTER(CP_PERFCOUNTER_SELECT)
+
+START_REGISTER(CP_PERFCOUNTER_LO)
+    GENERATE_FIELD(PERFCOUNT_LO, int)
+END_REGISTER(CP_PERFCOUNTER_LO)
+
+START_REGISTER(CP_PERFCOUNTER_HI)
+    GENERATE_FIELD(PERFCOUNT_HI, int)
+END_REGISTER(CP_PERFCOUNTER_HI)
+
+START_REGISTER(CP_BIN_MASK_LO)
+    GENERATE_FIELD(BIN_MASK_LO, int)
+END_REGISTER(CP_BIN_MASK_LO)
+
+START_REGISTER(CP_BIN_MASK_HI)
+    GENERATE_FIELD(BIN_MASK_HI, int)
+END_REGISTER(CP_BIN_MASK_HI)
+
+START_REGISTER(CP_BIN_SELECT_LO)
+    GENERATE_FIELD(BIN_SELECT_LO, int)
+END_REGISTER(CP_BIN_SELECT_LO)
+
+START_REGISTER(CP_BIN_SELECT_HI)
+    GENERATE_FIELD(BIN_SELECT_HI, int)
+END_REGISTER(CP_BIN_SELECT_HI)
+
+START_REGISTER(CP_NV_FLAGS_0)
+    GENERATE_FIELD(END_RCVD_15, int)
+    GENERATE_FIELD(DISCARD_15, int)
+    GENERATE_FIELD(END_RCVD_14, int)
+    GENERATE_FIELD(DISCARD_14, int)
+    GENERATE_FIELD(END_RCVD_13, int)
+    GENERATE_FIELD(DISCARD_13, int)
+    GENERATE_FIELD(END_RCVD_12, int)
+    GENERATE_FIELD(DISCARD_12, int)
+    GENERATE_FIELD(END_RCVD_11, int)
+    GENERATE_FIELD(DISCARD_11, int)
+    GENERATE_FIELD(END_RCVD_10, int)
+    GENERATE_FIELD(DISCARD_10, int)
+    GENERATE_FIELD(END_RCVD_9, int)
+    GENERATE_FIELD(DISCARD_9, int)
+    GENERATE_FIELD(END_RCVD_8, int)
+    GENERATE_FIELD(DISCARD_8, int)
+    GENERATE_FIELD(END_RCVD_7, int)
+    GENERATE_FIELD(DISCARD_7, int)
+    GENERATE_FIELD(END_RCVD_6, int)
+    GENERATE_FIELD(DISCARD_6, int)
+    GENERATE_FIELD(END_RCVD_5, int)
+    GENERATE_FIELD(DISCARD_5, int)
+    GENERATE_FIELD(END_RCVD_4, int)
+    GENERATE_FIELD(DISCARD_4, int)
+    GENERATE_FIELD(END_RCVD_3, int)
+    GENERATE_FIELD(DISCARD_3, int)
+    GENERATE_FIELD(END_RCVD_2, int)
+    GENERATE_FIELD(DISCARD_2, int)
+    GENERATE_FIELD(END_RCVD_1, int)
+    GENERATE_FIELD(DISCARD_1, int)
+    GENERATE_FIELD(END_RCVD_0, int)
+    GENERATE_FIELD(DISCARD_0, int)
+END_REGISTER(CP_NV_FLAGS_0)
+
+START_REGISTER(CP_NV_FLAGS_1)
+    GENERATE_FIELD(END_RCVD_31, int)
+    GENERATE_FIELD(DISCARD_31, int)
+    GENERATE_FIELD(END_RCVD_30, int)
+    GENERATE_FIELD(DISCARD_30, int)
+    GENERATE_FIELD(END_RCVD_29, int)
+    GENERATE_FIELD(DISCARD_29, int)
+    GENERATE_FIELD(END_RCVD_28, int)
+    GENERATE_FIELD(DISCARD_28, int)
+    GENERATE_FIELD(END_RCVD_27, int)
+    GENERATE_FIELD(DISCARD_27, int)
+    GENERATE_FIELD(END_RCVD_26, int)
+    GENERATE_FIELD(DISCARD_26, int)
+    GENERATE_FIELD(END_RCVD_25, int)
+    GENERATE_FIELD(DISCARD_25, int)
+    GENERATE_FIELD(END_RCVD_24, int)
+    GENERATE_FIELD(DISCARD_24, int)
+    GENERATE_FIELD(END_RCVD_23, int)
+    GENERATE_FIELD(DISCARD_23, int)
+    GENERATE_FIELD(END_RCVD_22, int)
+    GENERATE_FIELD(DISCARD_22, int)
+    GENERATE_FIELD(END_RCVD_21, int)
+    GENERATE_FIELD(DISCARD_21, int)
+    GENERATE_FIELD(END_RCVD_20, int)
+    GENERATE_FIELD(DISCARD_20, int)
+    GENERATE_FIELD(END_RCVD_19, int)
+    GENERATE_FIELD(DISCARD_19, int)
+    GENERATE_FIELD(END_RCVD_18, int)
+    GENERATE_FIELD(DISCARD_18, int)
+    GENERATE_FIELD(END_RCVD_17, int)
+    GENERATE_FIELD(DISCARD_17, int)
+    GENERATE_FIELD(END_RCVD_16, int)
+    GENERATE_FIELD(DISCARD_16, int)
+END_REGISTER(CP_NV_FLAGS_1)
+
+START_REGISTER(CP_NV_FLAGS_2)
+    GENERATE_FIELD(END_RCVD_47, int)
+    GENERATE_FIELD(DISCARD_47, int)
+    GENERATE_FIELD(END_RCVD_46, int)
+    GENERATE_FIELD(DISCARD_46, int)
+    GENERATE_FIELD(END_RCVD_45, int)
+    GENERATE_FIELD(DISCARD_45, int)
+    GENERATE_FIELD(END_RCVD_44, int)
+    GENERATE_FIELD(DISCARD_44, int)
+    GENERATE_FIELD(END_RCVD_43, int)
+    GENERATE_FIELD(DISCARD_43, int)
+    GENERATE_FIELD(END_RCVD_42, int)
+    GENERATE_FIELD(DISCARD_42, int)
+    GENERATE_FIELD(END_RCVD_41, int)
+    GENERATE_FIELD(DISCARD_41, int)
+    GENERATE_FIELD(END_RCVD_40, int)
+    GENERATE_FIELD(DISCARD_40, int)
+    GENERATE_FIELD(END_RCVD_39, int)
+    GENERATE_FIELD(DISCARD_39, int)
+    GENERATE_FIELD(END_RCVD_38, int)
+    GENERATE_FIELD(DISCARD_38, int)
+    GENERATE_FIELD(END_RCVD_37, int)
+    GENERATE_FIELD(DISCARD_37, int)
+    GENERATE_FIELD(END_RCVD_36, int)
+    GENERATE_FIELD(DISCARD_36, int)
+    GENERATE_FIELD(END_RCVD_35, int)
+    GENERATE_FIELD(DISCARD_35, int)
+    GENERATE_FIELD(END_RCVD_34, int)
+    GENERATE_FIELD(DISCARD_34, int)
+    GENERATE_FIELD(END_RCVD_33, int)
+    GENERATE_FIELD(DISCARD_33, int)
+    GENERATE_FIELD(END_RCVD_32, int)
+    GENERATE_FIELD(DISCARD_32, int)
+END_REGISTER(CP_NV_FLAGS_2)
+
+START_REGISTER(CP_NV_FLAGS_3)
+    GENERATE_FIELD(END_RCVD_63, int)
+    GENERATE_FIELD(DISCARD_63, int)
+    GENERATE_FIELD(END_RCVD_62, int)
+    GENERATE_FIELD(DISCARD_62, int)
+    GENERATE_FIELD(END_RCVD_61, int)
+    GENERATE_FIELD(DISCARD_61, int)
+    GENERATE_FIELD(END_RCVD_60, int)
+    GENERATE_FIELD(DISCARD_60, int)
+    GENERATE_FIELD(END_RCVD_59, int)
+    GENERATE_FIELD(DISCARD_59, int)
+    GENERATE_FIELD(END_RCVD_58, int)
+    GENERATE_FIELD(DISCARD_58, int)
+    GENERATE_FIELD(END_RCVD_57, int)
+    GENERATE_FIELD(DISCARD_57, int)
+    GENERATE_FIELD(END_RCVD_56, int)
+    GENERATE_FIELD(DISCARD_56, int)
+    GENERATE_FIELD(END_RCVD_55, int)
+    GENERATE_FIELD(DISCARD_55, int)
+    GENERATE_FIELD(END_RCVD_54, int)
+    GENERATE_FIELD(DISCARD_54, int)
+    GENERATE_FIELD(END_RCVD_53, int)
+    GENERATE_FIELD(DISCARD_53, int)
+    GENERATE_FIELD(END_RCVD_52, int)
+    GENERATE_FIELD(DISCARD_52, int)
+    GENERATE_FIELD(END_RCVD_51, int)
+    GENERATE_FIELD(DISCARD_51, int)
+    GENERATE_FIELD(END_RCVD_50, int)
+    GENERATE_FIELD(DISCARD_50, int)
+    GENERATE_FIELD(END_RCVD_49, int)
+    GENERATE_FIELD(DISCARD_49, int)
+    GENERATE_FIELD(END_RCVD_48, int)
+    GENERATE_FIELD(DISCARD_48, int)
+END_REGISTER(CP_NV_FLAGS_3)
+
+START_REGISTER(CP_STATE_DEBUG_INDEX)
+    GENERATE_FIELD(STATE_DEBUG_INDEX, int)
+END_REGISTER(CP_STATE_DEBUG_INDEX)
+
+START_REGISTER(CP_STATE_DEBUG_DATA)
+    GENERATE_FIELD(STATE_DEBUG_DATA, int)
+END_REGISTER(CP_STATE_DEBUG_DATA)
+
+START_REGISTER(CP_PROG_COUNTER)
+    GENERATE_FIELD(COUNTER, int)
+END_REGISTER(CP_PROG_COUNTER)
+
+START_REGISTER(CP_STAT)
+    GENERATE_FIELD(CP_BUSY, int)
+    GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int)
+    GENERATE_FIELD(ME_WC_BUSY, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(_3D_BUSY, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(MIU_WC_STALL, int)
+    GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(MEQ_RING_BUSY, int)
+    GENERATE_FIELD(PFP_BUSY, int)
+    GENERATE_FIELD(ST_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int)
+    GENERATE_FIELD(RING_QUEUE_BUSY, int)
+    GENERATE_FIELD(CSF_BUSY, int)
+    GENERATE_FIELD(CSF_ST_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(CSF_RING_BUSY, int)
+    GENERATE_FIELD(RCIU_BUSY, int)
+    GENERATE_FIELD(RBIU_BUSY, int)
+    GENERATE_FIELD(MIU_RD_RETURN_BUSY, int)
+    GENERATE_FIELD(MIU_RD_REQ_BUSY, int)
+    GENERATE_FIELD(MIU_WR_BUSY, int)
+END_REGISTER(CP_STAT)
+
+START_REGISTER(BIOS_0_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_0_SCRATCH)
+
+START_REGISTER(BIOS_1_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_1_SCRATCH)
+
+START_REGISTER(BIOS_2_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_2_SCRATCH)
+
+START_REGISTER(BIOS_3_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_3_SCRATCH)
+
+START_REGISTER(BIOS_4_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_4_SCRATCH)
+
+START_REGISTER(BIOS_5_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_5_SCRATCH)
+
+START_REGISTER(BIOS_6_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_6_SCRATCH)
+
+START_REGISTER(BIOS_7_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_7_SCRATCH)
+
+START_REGISTER(BIOS_8_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_8_SCRATCH)
+
+START_REGISTER(BIOS_9_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_9_SCRATCH)
+
+START_REGISTER(BIOS_10_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_10_SCRATCH)
+
+START_REGISTER(BIOS_11_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_11_SCRATCH)
+
+START_REGISTER(BIOS_12_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_12_SCRATCH)
+
+START_REGISTER(BIOS_13_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_13_SCRATCH)
+
+START_REGISTER(BIOS_14_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_14_SCRATCH)
+
+START_REGISTER(BIOS_15_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_15_SCRATCH)
+
+START_REGISTER(COHER_SIZE_PM4)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_PM4)
+
+START_REGISTER(COHER_BASE_PM4)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(COHER_BASE_PM4)
+
+START_REGISTER(COHER_STATUS_PM4)
+    GENERATE_FIELD(STATUS, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(RB_COLOR_INFO_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+END_REGISTER(COHER_STATUS_PM4)
+
+START_REGISTER(COHER_SIZE_HOST)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_HOST)
+
+START_REGISTER(COHER_BASE_HOST)
+    GENERATE_FIELD(BASE, hex)
+END_REGISTER(COHER_BASE_HOST)
+
+START_REGISTER(COHER_STATUS_HOST)
+    GENERATE_FIELD(STATUS, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(RB_COLOR_INFO_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+END_REGISTER(COHER_STATUS_HOST)
+
+START_REGISTER(COHER_DEST_BASE_0)
+    GENERATE_FIELD(DEST_BASE_0, hex)
+END_REGISTER(COHER_DEST_BASE_0)
+
+START_REGISTER(COHER_DEST_BASE_1)
+    GENERATE_FIELD(DEST_BASE_1, hex)
+END_REGISTER(COHER_DEST_BASE_1)
+
+START_REGISTER(COHER_DEST_BASE_2)
+    GENERATE_FIELD(DEST_BASE_2, hex)
+END_REGISTER(COHER_DEST_BASE_2)
+
+START_REGISTER(COHER_DEST_BASE_3)
+    GENERATE_FIELD(DEST_BASE_3, hex)
+END_REGISTER(COHER_DEST_BASE_3)
+
+START_REGISTER(COHER_DEST_BASE_4)
+    GENERATE_FIELD(DEST_BASE_4, hex)
+END_REGISTER(COHER_DEST_BASE_4)
+
+START_REGISTER(COHER_DEST_BASE_5)
+    GENERATE_FIELD(DEST_BASE_5, hex)
+END_REGISTER(COHER_DEST_BASE_5)
+
+START_REGISTER(COHER_DEST_BASE_6)
+    GENERATE_FIELD(DEST_BASE_6, hex)
+END_REGISTER(COHER_DEST_BASE_6)
+
+START_REGISTER(COHER_DEST_BASE_7)
+    GENERATE_FIELD(DEST_BASE_7, hex)
+END_REGISTER(COHER_DEST_BASE_7)
+
+START_REGISTER(RB_SURFACE_INFO)
+    GENERATE_FIELD(MSAA_SAMPLES, MSAASamples)
+    GENERATE_FIELD(SURFACE_PITCH, uint)
+END_REGISTER(RB_SURFACE_INFO)
+
+START_REGISTER(RB_COLOR_INFO)
+    GENERATE_FIELD(COLOR_BASE, uint)
+    GENERATE_FIELD(COLOR_SWAP, uint)
+    GENERATE_FIELD(COLOR_ENDIAN, uint)
+    GENERATE_FIELD(COLOR_LINEAR, bool)
+    GENERATE_FIELD(COLOR_ROUND_MODE, uint)
+    GENERATE_FIELD(COLOR_FORMAT, ColorformatX)
+END_REGISTER(RB_COLOR_INFO)
+
+START_REGISTER(RB_DEPTH_INFO)
+    GENERATE_FIELD(DEPTH_BASE, uint)
+    GENERATE_FIELD(DEPTH_FORMAT, DepthformatX)
+END_REGISTER(RB_DEPTH_INFO)
+
+START_REGISTER(RB_STENCILREFMASK)
+    GENERATE_FIELD(RESERVED1, bool)
+    GENERATE_FIELD(RESERVED0, bool)
+    GENERATE_FIELD(STENCILWRITEMASK, hex)
+    GENERATE_FIELD(STENCILMASK, hex)
+    GENERATE_FIELD(STENCILREF, hex)
+END_REGISTER(RB_STENCILREFMASK)
+
+START_REGISTER(RB_ALPHA_REF)
+    GENERATE_FIELD(ALPHA_REF, float)
+END_REGISTER(RB_ALPHA_REF)
+
+START_REGISTER(RB_COLOR_MASK)
+    GENERATE_FIELD(RESERVED3, bool)
+    GENERATE_FIELD(RESERVED2, bool)
+    GENERATE_FIELD(WRITE_ALPHA, bool)
+    GENERATE_FIELD(WRITE_BLUE, bool)
+    GENERATE_FIELD(WRITE_GREEN, bool)
+    GENERATE_FIELD(WRITE_RED, bool)
+END_REGISTER(RB_COLOR_MASK)
+
+START_REGISTER(RB_BLEND_RED)
+    GENERATE_FIELD(BLEND_RED, uint)
+END_REGISTER(RB_BLEND_RED)
+
+START_REGISTER(RB_BLEND_GREEN)
+    GENERATE_FIELD(BLEND_GREEN, uint)
+END_REGISTER(RB_BLEND_GREEN)
+
+START_REGISTER(RB_BLEND_BLUE)
+    GENERATE_FIELD(BLEND_BLUE, uint)
+END_REGISTER(RB_BLEND_BLUE)
+
+START_REGISTER(RB_BLEND_ALPHA)
+    GENERATE_FIELD(BLEND_ALPHA, uint)
+END_REGISTER(RB_BLEND_ALPHA)
+
+START_REGISTER(RB_FOG_COLOR)
+    GENERATE_FIELD(FOG_BLUE, uint)
+    GENERATE_FIELD(FOG_GREEN, uint)
+    GENERATE_FIELD(FOG_RED, uint)
+END_REGISTER(RB_FOG_COLOR)
+
+START_REGISTER(RB_STENCILREFMASK_BF)
+    GENERATE_FIELD(RESERVED5, bool)
+    GENERATE_FIELD(RESERVED4, bool)
+    GENERATE_FIELD(STENCILWRITEMASK_BF, hex)
+    GENERATE_FIELD(STENCILMASK_BF, hex)
+    GENERATE_FIELD(STENCILREF_BF, hex)
+END_REGISTER(RB_STENCILREFMASK_BF)
+
+START_REGISTER(RB_DEPTHCONTROL)
+    GENERATE_FIELD(STENCILZFAIL_BF, StencilOp)
+    GENERATE_FIELD(STENCILZPASS_BF, StencilOp)
+    GENERATE_FIELD(STENCILFAIL_BF, StencilOp)
+    GENERATE_FIELD(STENCILFUNC_BF, CompareRef)
+    GENERATE_FIELD(STENCILZFAIL, StencilOp)
+    GENERATE_FIELD(STENCILZPASS, StencilOp)
+    GENERATE_FIELD(STENCILFAIL, StencilOp)
+    GENERATE_FIELD(STENCILFUNC, CompareRef)
+    GENERATE_FIELD(BACKFACE_ENABLE, bool)
+    GENERATE_FIELD(ZFUNC, CompareFrag)
+    GENERATE_FIELD(EARLY_Z_ENABLE, bool)
+    GENERATE_FIELD(Z_WRITE_ENABLE, bool)
+    GENERATE_FIELD(Z_ENABLE, bool)
+    GENERATE_FIELD(STENCIL_ENABLE, bool)
+END_REGISTER(RB_DEPTHCONTROL)
+
+START_REGISTER(RB_BLENDCONTROL)
+    GENERATE_FIELD(BLEND_FORCE, bool)
+    GENERATE_FIELD(BLEND_FORCE_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX)
+END_REGISTER(RB_BLENDCONTROL)
+
+START_REGISTER(RB_COLORCONTROL)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex)
+    GENERATE_FIELD(PIXEL_FOG, bool)
+    GENERATE_FIELD(DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(ROP_CODE, uint)
+    GENERATE_FIELD(VS_EXPORTS_FOG, bool)
+    GENERATE_FIELD(FOG_ENABLE, bool)
+    GENERATE_FIELD(BLEND_DISABLE, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_TEST_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_FUNC, CompareRef)
+END_REGISTER(RB_COLORCONTROL)
+
+START_REGISTER(RB_MODECONTROL)
+    GENERATE_FIELD(EDRAM_MODE, EdramMode)
+END_REGISTER(RB_MODECONTROL)
+
+START_REGISTER(RB_COLOR_DEST_MASK)
+    GENERATE_FIELD(COLOR_DEST_MASK, uint)
+END_REGISTER(RB_COLOR_DEST_MASK)
+
+START_REGISTER(RB_COPY_CONTROL)
+    GENERATE_FIELD(CLEAR_MASK, uint)
+    GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool)
+    GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect)
+END_REGISTER(RB_COPY_CONTROL)
+
+START_REGISTER(RB_COPY_DEST_BASE)
+    GENERATE_FIELD(COPY_DEST_BASE, uint)
+END_REGISTER(RB_COPY_DEST_BASE)
+
+START_REGISTER(RB_COPY_DEST_PITCH)
+    GENERATE_FIELD(COPY_DEST_PITCH, uint)
+END_REGISTER(RB_COPY_DEST_PITCH)
+
+START_REGISTER(RB_COPY_DEST_INFO)
+    GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_RED, hex)
+    GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(COPY_DEST_SWAP, uint)
+    GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX)
+    GENERATE_FIELD(COPY_DEST_LINEAR, uint)
+    GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian)
+END_REGISTER(RB_COPY_DEST_INFO)
+
+START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+    GENERATE_FIELD(OFFSET_Y, uint)
+    GENERATE_FIELD(OFFSET_X, uint)
+END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+
+START_REGISTER(RB_DEPTH_CLEAR)
+    GENERATE_FIELD(DEPTH_CLEAR, uint)
+END_REGISTER(RB_DEPTH_CLEAR)
+
+START_REGISTER(RB_SAMPLE_COUNT_CTL)
+    GENERATE_FIELD(COPY_SAMPLE_COUNT, bool)
+    GENERATE_FIELD(RESET_SAMPLE_COUNT, bool)
+END_REGISTER(RB_SAMPLE_COUNT_CTL)
+
+START_REGISTER(RB_SAMPLE_COUNT_ADDR)
+    GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint)
+END_REGISTER(RB_SAMPLE_COUNT_ADDR)
+
+START_REGISTER(RB_BC_CONTROL)
+    GENERATE_FIELD(RESERVED6, bool)
+    GENERATE_FIELD(CRC_SYSTEM, bool)
+    GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool)
+    GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_ALLOC_MASK, uint)
+    GENERATE_FIELD(DISABLE_ACCUM, bool)
+    GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool)
+    GENERATE_FIELD(CRC_MODE, bool)
+    GENERATE_FIELD(ENABLE_CRC_UPDATE, bool)
+    GENERATE_FIELD(AZ_THROTTLE_COUNT, uint)
+    GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool)
+    GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool)
+    GENERATE_FIELD(DISABLE_EDRAM_CAM, bool)
+    GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint)
+    GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool)
+END_REGISTER(RB_BC_CONTROL)
+
+START_REGISTER(RB_EDRAM_INFO)
+    GENERATE_FIELD(EDRAM_RANGE, hex)
+    GENERATE_FIELD(EDRAM_MAPPING_MODE, uint)
+    GENERATE_FIELD(EDRAM_SIZE, EdramSizeX)
+END_REGISTER(RB_EDRAM_INFO)
+
+START_REGISTER(RB_CRC_RD_PORT)
+    GENERATE_FIELD(CRC_DATA, hex)
+END_REGISTER(RB_CRC_RD_PORT)
+
+START_REGISTER(RB_CRC_CONTROL)
+    GENERATE_FIELD(CRC_RD_ADVANCE, bool)
+END_REGISTER(RB_CRC_CONTROL)
+
+START_REGISTER(RB_CRC_MASK)
+    GENERATE_FIELD(CRC_MASK, hex)
+END_REGISTER(RB_CRC_MASK)
+
+START_REGISTER(RB_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT)
+END_REGISTER(RB_PERFCOUNTER0_SELECT)
+
+START_REGISTER(RB_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_LOW)
+
+START_REGISTER(RB_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_HI)
+
+START_REGISTER(RB_TOTAL_SAMPLES)
+    GENERATE_FIELD(TOTAL_SAMPLES, int)
+END_REGISTER(RB_TOTAL_SAMPLES)
+
+START_REGISTER(RB_ZPASS_SAMPLES)
+    GENERATE_FIELD(ZPASS_SAMPLES, int)
+END_REGISTER(RB_ZPASS_SAMPLES)
+
+START_REGISTER(RB_ZFAIL_SAMPLES)
+    GENERATE_FIELD(ZFAIL_SAMPLES, int)
+END_REGISTER(RB_ZFAIL_SAMPLES)
+
+START_REGISTER(RB_SFAIL_SAMPLES)
+    GENERATE_FIELD(SFAIL_SAMPLES, int)
+END_REGISTER(RB_SFAIL_SAMPLES)
+
+START_REGISTER(RB_DEBUG_0)
+    GENERATE_FIELD(EZ_INFSAMP_FULL, bool)
+    GENERATE_FIELD(C_MASK_FULL, bool)
+    GENERATE_FIELD(C_REQ_FULL, bool)
+    GENERATE_FIELD(C_EZ_TILE_FULL, bool)
+    GENERATE_FIELD(C_SX_CMD_FULL, bool)
+    GENERATE_FIELD(C_SX_LAT_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool)
+    GENERATE_FIELD(WRREQ_C0_FULL, bool)
+    GENERATE_FIELD(WRREQ_C1_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z0_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z1_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(RDREQ_C0_FULL, bool)
+    GENERATE_FIELD(RDREQ_C1_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z0_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z1_FULL, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool)
+END_REGISTER(RB_DEBUG_0)
+
+START_REGISTER(RB_DEBUG_1)
+    GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool)
+    GENERATE_FIELD(C_MASK_EMPTY, bool)
+    GENERATE_FIELD(C_REQ_EMPTY, bool)
+    GENERATE_FIELD(C_EZ_TILE_EMPTY, bool)
+    GENERATE_FIELD(C_SX_CMD_EMPTY, bool)
+    GENERATE_FIELD(C_SX_LAT_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool)
+END_REGISTER(RB_DEBUG_1)
+
+START_REGISTER(RB_DEBUG_2)
+    GENERATE_FIELD(Z_TILE_EMPTY, bool)
+    GENERATE_FIELD(Z_SAMP_EMPTY, bool)
+    GENERATE_FIELD(Z1_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z0_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z1_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z0_MASK_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_INFTILE_EMPTY, bool)
+    GENERATE_FIELD(Z_TILE_FULL, bool)
+    GENERATE_FIELD(Z_SAMP_FULL, bool)
+    GENERATE_FIELD(Z1_REQ_FULL, bool)
+    GENERATE_FIELD(Z0_REQ_FULL, bool)
+    GENERATE_FIELD(Z1_MASK_FULL, bool)
+    GENERATE_FIELD(Z0_MASK_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_INFTILE_FULL, bool)
+    GENERATE_FIELD(CURRENT_TILE_EVENT, bool)
+    GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool)
+    GENERATE_FIELD(MEM_EXPORT_FLAG, bool)
+    GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool)
+    GENERATE_FIELD(TILE_FIFO_COUNT, bool)
+END_REGISTER(RB_DEBUG_2)
+
+START_REGISTER(RB_DEBUG_3)
+    GENERATE_FIELD(ZEXP_UPPER_FULL, bool)
+    GENERATE_FIELD(ZEXP_LOWER_FULL, bool)
+    GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool)
+    GENERATE_FIELD(SHD_EMPTY, bool)
+    GENERATE_FIELD(SHD_FULL, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool)
+    GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool)
+    GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool)
+    GENERATE_FIELD(ACCUM_FLUSHING, bool)
+    GENERATE_FIELD(ACCUM_VALID, bool)
+END_REGISTER(RB_DEBUG_3)
+
+START_REGISTER(RB_DEBUG_4)
+    GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool)
+    GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool)
+    GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool)
+END_REGISTER(RB_DEBUG_4)
+
+START_REGISTER(RB_FLAG_CONTROL)
+    GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool)
+END_REGISTER(RB_FLAG_CONTROL)
+
+START_REGISTER(RB_BC_SPARES)
+    GENERATE_FIELD(RESERVED, bool)
+END_REGISTER(RB_BC_SPARES)
+
+START_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+    GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat)
+END_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+
+START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX)
+END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h
new file mode 100644
index 000000000000..f31b2a74d1fa
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h
@@ -0,0 +1,5920 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_MASK_HEADER)
+#define _yamato_MASK_HEADER
+/*
+*   yamato_mask.h
+*
+*   Register Spec Release:  Chip Spec 1.0
+*
+*
+*    (c) 2000 ATI Technologies Inc.  (unpublished)
+*
+*    All rights reserved.  This notice is intended as a precaution against
+*    inadvertent publication and does not imply publication or any waiver
+*    of confidentiality.  The year included in the foregoing notice is the
+*    year of creation of the work.
+*
+*/
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK            0xffffffffL
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK             0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA                  0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK            0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA                 0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK             0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA                  0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK            0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA                 0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK             0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA                  0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK            0x00000020L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA                 0x00000020L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK                    0x00000100L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT                         0x00000100L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK                     0x00000200L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT                          0x00000200L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK                    0x00000400L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT                         0x00000400L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK               0x00000800L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF                    0x00000800L
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK                 0x00010000L
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE                      0x00010000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK       0x00040000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA            0x00040000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK            0x00080000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF                 0x00080000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK          0x00100000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT               0x00100000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK                  0x00200000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR                       0x00200000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK                0x00400000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN                     0x00400000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK                 0x00800000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN                      0x00800000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK                 0x01000000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN                      0x01000000L
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK           0x00000001L
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA                0x00000001L
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_CL_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_SC_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK                    0x00000001L
+#define PA_SU_VTX_CNTL__PIX_CENTER                         0x00000001L
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK                    0x00000006L
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK                    0x00000038L
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT_MASK                      0x0000ffffL
+#define PA_SU_POINT_SIZE__WIDTH_MASK                       0xffff0000L
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK                  0x0000ffffL
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK                  0xffff0000L
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH_MASK                        0x0000ffffL
+
+// PA_SU_FACE_DATA
+#define PA_SU_FACE_DATA__BASE_ADDR_MASK                    0xffffffe0L
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK                0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT                     0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK                 0x00000002L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK                      0x00000002L
+#define PA_SU_SC_MODE_CNTL__FACE_MASK                      0x00000004L
+#define PA_SU_SC_MODE_CNTL__FACE                           0x00000004L
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK                 0x00000018L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK      0x000000e0L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK       0x00000700L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK  0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE       0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK   0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE        0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK   0x00002000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE        0x00002000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK               0x00008000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE                    0x00008000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK  0x00010000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE       0x00010000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK       0x00040000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE            0x00040000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK        0x00080000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST             0x00080000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK            0x00100000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS                 0x00100000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK         0x00200000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA              0x00200000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK         0x00800000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE              0x00800000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK      0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI           0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS_MASK        0x20000000L
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS             0x20000000L
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE_MASK          0x40000000L
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE               0x40000000L
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE_MASK         0x80000000L
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE              0x80000000L
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK          0xffffffffL
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK        0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK           0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK         0xffffffffL
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK          0x00007fffL
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK          0x7fff0000L
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK             0x00000007L
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK              0x0001e000L
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK_MASK                        0x0000ffffL
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK              0x0000ffffL
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK              0x00ff0000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK         0x10000000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER              0x10000000L
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK           0x60000000L
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL_MASK                    0x000000ffL
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK                0x00000100L
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL                     0x00000100L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK            0x00000200L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH                 0x00000200L
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK                   0x00000400L
+#define PA_SC_LINE_CNTL__LAST_PIXEL                        0x00000400L
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK                 0x3fff0000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE     0x80000000L
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK                 0x3fff0000L
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK                 0x7fff0000L
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK                 0x7fff0000L
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK                0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA                     0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK                 0x0000003eL
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK        0x00000080L
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z             0x00000080L
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK           0xffffffffL
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK         0x0000000fL
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK       0x0000ff00L
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY_MASK                    0x80000000L
+#define PA_CL_CNTL_STATUS__CL_BUSY                         0x80000000L
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK                    0x80000000L
+#define PA_SU_CNTL_STATUS__SU_BUSY                         0x80000000L
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY_MASK                    0x80000000L
+#define PA_SC_CNTL_STATUS__SC_BUSY                         0x80000000L
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK    0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write         0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK     0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full          0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK    0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write         0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK     0x00000008L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full          0x00000008L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty   0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full    0x00000020L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty      0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK  0x00000080L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full       0x00000080L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK  0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty       0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK   0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full        0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK  0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty       0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK   0x00000800L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full        0x00000800L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty      0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK       0x00002000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full            0x00002000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty  0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full   0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty  0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full   0x00020000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty    0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full     0x00080000L
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK              0xfff00000L
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet   0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim    0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive  0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK      0x00380000L
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK              0xff000000L
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK             0x001fffffL
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK             0x7f000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK             0x000fff00L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK             0xfc000000L
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event  0x00000080L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK             0xffffff00L
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK             0x00000006L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK             0x00c00000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK             0xf0000000L
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK     0x00000001L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event          0x00000001L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK             0x000000c0L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK             0x00003000L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK             0x000c0000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK          0x00100000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid               0x00100000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait      0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK     0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty          0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK      0x20000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full           0x20000000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK             0x00000030L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK             0x00000c00L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK             0x00180000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet  0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK  0xfc000000L
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK              0xfffffff0L
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK             0x0000001cL
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK   0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty        0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK             0x00007800L
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK   0x00200000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid        0x00200000L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK             0xffc00000L
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK        0x0000000fL
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK       0x000007f0L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK             0x00003800L
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK      0x0003c000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1  0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0  0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK        0x07f00000L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK             0xf8000000L
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK             0x0000000fL
+#define SXIFCCG_DEBUG_REG0__position_address_MASK          0x00000070L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK              0x00000380L
+#define SXIFCCG_DEBUG_REG0__point_address_MASK             0x00001c00L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK              0x0000e000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx   0x00010000L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK              0x00060000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK    0x00780000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK         0x3f800000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK     0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc          0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK     0x80000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel          0x80000000L
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK              0x00000003L
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK            0x0000000cL
+#define SXIFCCG_DEBUG_REG1__available_positions_MASK       0x00000070L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK              0x00000780L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK        0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance             0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK           0x00007000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector  0x00008000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK              0x000f0000L
+#define SXIFCCG_DEBUG_REG1__aux_sel_MASK                   0x00100000L
+#define SXIFCCG_DEBUG_REG1__aux_sel                        0x00100000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK              0x00600000L
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK              0x01800000L
+#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK          0xfe000000L
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent_MASK                   0x00000001L
+#define SXIFCCG_DEBUG_REG2__sx_sent                        0x00000001L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK              0x00000002L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3                   0x00000002L
+#define SXIFCCG_DEBUG_REG2__sx_aux_MASK                    0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_aux                         0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK           0x000001f8L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK          0x0000fe00L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK              0x00010000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2                   0x00010000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx    0x00020000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK              0x000c0000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK              0x03c00000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK   0x04000000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded        0x04000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK     0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty          0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK      0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full           0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK  0xe0000000L
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK              0x00000010L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3                   0x00000010L
+#define SXIFCCG_DEBUG_REG3__available_positions_MASK       0x000000e0L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK              0x00000f00L
+#define SXIFCCG_DEBUG_REG3__current_state_MASK             0x00003000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK         0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty              0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK          0x00008000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full               0x00008000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK              0x00030000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK    0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty         0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK     0x00080000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full          0x00080000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK   0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty        0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK    0x00200000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full         0x00200000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK              0xffc00000L
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state_MASK               0x0000001fL
+#define SETUP_DEBUG_REG0__pmode_state_MASK                 0x000007e0L
+#define SETUP_DEBUG_REG0__ge_stallb_MASK                   0x00000800L
+#define SETUP_DEBUG_REG0__ge_stallb                        0x00000800L
+#define SETUP_DEBUG_REG0__geom_enable_MASK                 0x00001000L
+#define SETUP_DEBUG_REG0__geom_enable                      0x00001000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK           0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr                0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_rtr_MASK                 0x00004000L
+#define SETUP_DEBUG_REG0__su_clip_rtr                      0x00004000L
+#define SETUP_DEBUG_REG0__pfifo_busy_MASK                  0x00008000L
+#define SETUP_DEBUG_REG0__pfifo_busy                       0x00008000L
+#define SETUP_DEBUG_REG0__su_cntl_busy_MASK                0x00010000L
+#define SETUP_DEBUG_REG0__su_cntl_busy                     0x00010000L
+#define SETUP_DEBUG_REG0__geom_busy_MASK                   0x00020000L
+#define SETUP_DEBUG_REG0__geom_busy                        0x00020000L
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG4__null_prim_gated_MASK             0x00000800L
+#define SETUP_DEBUG_REG4__null_prim_gated                  0x00000800L
+#define SETUP_DEBUG_REG4__backfacing_gated_MASK            0x00001000L
+#define SETUP_DEBUG_REG4__backfacing_gated                 0x00001000L
+#define SETUP_DEBUG_REG4__st_indx_gated_MASK               0x0000e000L
+#define SETUP_DEBUG_REG4__clipped_gated_MASK               0x00010000L
+#define SETUP_DEBUG_REG4__clipped_gated                    0x00010000L
+#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK          0x000e0000L
+#define SETUP_DEBUG_REG4__xmajor_gated_MASK                0x00100000L
+#define SETUP_DEBUG_REG4__xmajor_gated                     0x00100000L
+#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK          0x00600000L
+#define SETUP_DEBUG_REG4__type_gated_MASK                  0x03800000L
+#define SETUP_DEBUG_REG4__fpov_gated_MASK                  0x04000000L
+#define SETUP_DEBUG_REG4__fpov_gated                       0x04000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK            0x08000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated                 0x08000000L
+#define SETUP_DEBUG_REG4__event_gated_MASK                 0x10000000L
+#define SETUP_DEBUG_REG4__event_gated                      0x10000000L
+#define SETUP_DEBUG_REG4__eop_gated_MASK                   0x20000000L
+#define SETUP_DEBUG_REG4__eop_gated                        0x20000000L
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK       0x003ff800L
+#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK         0x00c00000L
+#define SETUP_DEBUG_REG5__event_id_gated_MASK              0x1f000000L
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1_MASK                      0x00000001L
+#define SC_DEBUG_0__pa_freeze_b1                           0x00000001L
+#define SC_DEBUG_0__pa_sc_valid_MASK                       0x00000002L
+#define SC_DEBUG_0__pa_sc_valid                            0x00000002L
+#define SC_DEBUG_0__pa_sc_phase_MASK                       0x0000001cL
+#define SC_DEBUG_0__cntx_cnt_MASK                          0x00000fe0L
+#define SC_DEBUG_0__decr_cntx_cnt_MASK                     0x00001000L
+#define SC_DEBUG_0__decr_cntx_cnt                          0x00001000L
+#define SC_DEBUG_0__incr_cntx_cnt_MASK                     0x00002000L
+#define SC_DEBUG_0__incr_cntx_cnt                          0x00002000L
+#define SC_DEBUG_0__trigger_MASK                           0x80000000L
+#define SC_DEBUG_0__trigger                                0x80000000L
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state_MASK                          0x00000007L
+#define SC_DEBUG_1__em1_data_ready_MASK                    0x00000008L
+#define SC_DEBUG_1__em1_data_ready                         0x00000008L
+#define SC_DEBUG_1__em2_data_ready_MASK                    0x00000010L
+#define SC_DEBUG_1__em2_data_ready                         0x00000010L
+#define SC_DEBUG_1__move_em1_to_em2_MASK                   0x00000020L
+#define SC_DEBUG_1__move_em1_to_em2                        0x00000020L
+#define SC_DEBUG_1__ef_data_ready_MASK                     0x00000040L
+#define SC_DEBUG_1__ef_data_ready                          0x00000040L
+#define SC_DEBUG_1__ef_state_MASK                          0x00000180L
+#define SC_DEBUG_1__pipe_valid_MASK                        0x00000200L
+#define SC_DEBUG_1__pipe_valid                             0x00000200L
+#define SC_DEBUG_1__trigger_MASK                           0x80000000L
+#define SC_DEBUG_1__trigger                                0x80000000L
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly_MASK                        0x00000001L
+#define SC_DEBUG_2__rc_rtr_dly                             0x00000001L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK              0x00000002L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1                   0x00000002L
+#define SC_DEBUG_2__pipe_freeze_b_MASK                     0x00000008L
+#define SC_DEBUG_2__pipe_freeze_b                          0x00000008L
+#define SC_DEBUG_2__prim_rts_MASK                          0x00000010L
+#define SC_DEBUG_2__prim_rts                               0x00000010L
+#define SC_DEBUG_2__next_prim_rts_dly_MASK                 0x00000020L
+#define SC_DEBUG_2__next_prim_rts_dly                      0x00000020L
+#define SC_DEBUG_2__next_prim_rtr_dly_MASK                 0x00000040L
+#define SC_DEBUG_2__next_prim_rtr_dly                      0x00000040L
+#define SC_DEBUG_2__pre_stage1_rts_d1_MASK                 0x00000080L
+#define SC_DEBUG_2__pre_stage1_rts_d1                      0x00000080L
+#define SC_DEBUG_2__stage0_rts_MASK                        0x00000100L
+#define SC_DEBUG_2__stage0_rts                             0x00000100L
+#define SC_DEBUG_2__phase_rts_dly_MASK                     0x00000200L
+#define SC_DEBUG_2__phase_rts_dly                          0x00000200L
+#define SC_DEBUG_2__end_of_prim_s1_dly_MASK                0x00008000L
+#define SC_DEBUG_2__end_of_prim_s1_dly                     0x00008000L
+#define SC_DEBUG_2__pass_empty_prim_s1_MASK                0x00010000L
+#define SC_DEBUG_2__pass_empty_prim_s1                     0x00010000L
+#define SC_DEBUG_2__event_id_s1_MASK                       0x003e0000L
+#define SC_DEBUG_2__event_s1_MASK                          0x00400000L
+#define SC_DEBUG_2__event_s1                               0x00400000L
+#define SC_DEBUG_2__trigger_MASK                           0x80000000L
+#define SC_DEBUG_2__trigger                                0x80000000L
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1_MASK                         0x000007ffL
+#define SC_DEBUG_3__y_curr_s1_MASK                         0x003ff800L
+#define SC_DEBUG_3__trigger_MASK                           0x80000000L
+#define SC_DEBUG_3__trigger                                0x80000000L
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_4__y_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_4__y_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_4__y_dir_s1                               0x10000000L
+#define SC_DEBUG_4__trigger_MASK                           0x80000000L
+#define SC_DEBUG_4__trigger                                0x80000000L
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_5__x_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_5__x_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_5__x_dir_s1                               0x10000000L
+#define SC_DEBUG_5__trigger_MASK                           0x80000000L
+#define SC_DEBUG_5__trigger                                0x80000000L
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty_MASK                        0x00000001L
+#define SC_DEBUG_6__z_ff_empty                             0x00000001L
+#define SC_DEBUG_6__qmcntl_ff_empty_MASK                   0x00000002L
+#define SC_DEBUG_6__qmcntl_ff_empty                        0x00000002L
+#define SC_DEBUG_6__xy_ff_empty_MASK                       0x00000004L
+#define SC_DEBUG_6__xy_ff_empty                            0x00000004L
+#define SC_DEBUG_6__event_flag_MASK                        0x00000008L
+#define SC_DEBUG_6__event_flag                             0x00000008L
+#define SC_DEBUG_6__z_mask_needed_MASK                     0x00000010L
+#define SC_DEBUG_6__z_mask_needed                          0x00000010L
+#define SC_DEBUG_6__state_MASK                             0x000000e0L
+#define SC_DEBUG_6__state_delayed_MASK                     0x00000700L
+#define SC_DEBUG_6__data_valid_MASK                        0x00000800L
+#define SC_DEBUG_6__data_valid                             0x00000800L
+#define SC_DEBUG_6__data_valid_d_MASK                      0x00001000L
+#define SC_DEBUG_6__data_valid_d                           0x00001000L
+#define SC_DEBUG_6__tilex_delayed_MASK                     0x003fe000L
+#define SC_DEBUG_6__tiley_delayed_MASK                     0x7fc00000L
+#define SC_DEBUG_6__trigger_MASK                           0x80000000L
+#define SC_DEBUG_6__trigger                                0x80000000L
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag_MASK                        0x00000001L
+#define SC_DEBUG_7__event_flag                             0x00000001L
+#define SC_DEBUG_7__deallocate_MASK                        0x0000000eL
+#define SC_DEBUG_7__fposition_MASK                         0x00000010L
+#define SC_DEBUG_7__fposition                              0x00000010L
+#define SC_DEBUG_7__sr_prim_we_MASK                        0x00000020L
+#define SC_DEBUG_7__sr_prim_we                             0x00000020L
+#define SC_DEBUG_7__last_tile_MASK                         0x00000040L
+#define SC_DEBUG_7__last_tile                              0x00000040L
+#define SC_DEBUG_7__tile_ff_we_MASK                        0x00000080L
+#define SC_DEBUG_7__tile_ff_we                             0x00000080L
+#define SC_DEBUG_7__qs_data_valid_MASK                     0x00000100L
+#define SC_DEBUG_7__qs_data_valid                          0x00000100L
+#define SC_DEBUG_7__qs_q0_y_MASK                           0x00000600L
+#define SC_DEBUG_7__qs_q0_x_MASK                           0x00001800L
+#define SC_DEBUG_7__qs_q0_valid_MASK                       0x00002000L
+#define SC_DEBUG_7__qs_q0_valid                            0x00002000L
+#define SC_DEBUG_7__prim_ff_we_MASK                        0x00004000L
+#define SC_DEBUG_7__prim_ff_we                             0x00004000L
+#define SC_DEBUG_7__tile_ff_re_MASK                        0x00008000L
+#define SC_DEBUG_7__tile_ff_re                             0x00008000L
+#define SC_DEBUG_7__fw_prim_data_valid_MASK                0x00010000L
+#define SC_DEBUG_7__fw_prim_data_valid                     0x00010000L
+#define SC_DEBUG_7__last_quad_of_tile_MASK                 0x00020000L
+#define SC_DEBUG_7__last_quad_of_tile                      0x00020000L
+#define SC_DEBUG_7__first_quad_of_tile_MASK                0x00040000L
+#define SC_DEBUG_7__first_quad_of_tile                     0x00040000L
+#define SC_DEBUG_7__first_quad_of_prim_MASK                0x00080000L
+#define SC_DEBUG_7__first_quad_of_prim                     0x00080000L
+#define SC_DEBUG_7__new_prim_MASK                          0x00100000L
+#define SC_DEBUG_7__new_prim                               0x00100000L
+#define SC_DEBUG_7__load_new_tile_data_MASK                0x00200000L
+#define SC_DEBUG_7__load_new_tile_data                     0x00200000L
+#define SC_DEBUG_7__state_MASK                             0x00c00000L
+#define SC_DEBUG_7__fifos_ready_MASK                       0x01000000L
+#define SC_DEBUG_7__fifos_ready                            0x01000000L
+#define SC_DEBUG_7__trigger_MASK                           0x80000000L
+#define SC_DEBUG_7__trigger                                0x80000000L
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last_MASK                       0x00000001L
+#define SC_DEBUG_8__sample_last                            0x00000001L
+#define SC_DEBUG_8__sample_mask_MASK                       0x0000001eL
+#define SC_DEBUG_8__sample_y_MASK                          0x00000060L
+#define SC_DEBUG_8__sample_x_MASK                          0x00000180L
+#define SC_DEBUG_8__sample_send_MASK                       0x00000200L
+#define SC_DEBUG_8__sample_send                            0x00000200L
+#define SC_DEBUG_8__next_cycle_MASK                        0x00000c00L
+#define SC_DEBUG_8__ez_sample_ff_full_MASK                 0x00001000L
+#define SC_DEBUG_8__ez_sample_ff_full                      0x00001000L
+#define SC_DEBUG_8__rb_sc_samp_rtr_MASK                    0x00002000L
+#define SC_DEBUG_8__rb_sc_samp_rtr                         0x00002000L
+#define SC_DEBUG_8__num_samples_MASK                       0x0000c000L
+#define SC_DEBUG_8__last_quad_of_tile_MASK                 0x00010000L
+#define SC_DEBUG_8__last_quad_of_tile                      0x00010000L
+#define SC_DEBUG_8__last_quad_of_prim_MASK                 0x00020000L
+#define SC_DEBUG_8__last_quad_of_prim                      0x00020000L
+#define SC_DEBUG_8__first_quad_of_prim_MASK                0x00040000L
+#define SC_DEBUG_8__first_quad_of_prim                     0x00040000L
+#define SC_DEBUG_8__sample_we_MASK                         0x00080000L
+#define SC_DEBUG_8__sample_we                              0x00080000L
+#define SC_DEBUG_8__fposition_MASK                         0x00100000L
+#define SC_DEBUG_8__fposition                              0x00100000L
+#define SC_DEBUG_8__event_id_MASK                          0x03e00000L
+#define SC_DEBUG_8__event_flag_MASK                        0x04000000L
+#define SC_DEBUG_8__event_flag                             0x04000000L
+#define SC_DEBUG_8__fw_prim_data_valid_MASK                0x08000000L
+#define SC_DEBUG_8__fw_prim_data_valid                     0x08000000L
+#define SC_DEBUG_8__trigger_MASK                           0x80000000L
+#define SC_DEBUG_8__trigger                                0x80000000L
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send_MASK                        0x00000001L
+#define SC_DEBUG_9__rb_sc_send                             0x00000001L
+#define SC_DEBUG_9__rb_sc_ez_mask_MASK                     0x0000001eL
+#define SC_DEBUG_9__fifo_data_ready_MASK                   0x00000020L
+#define SC_DEBUG_9__fifo_data_ready                        0x00000020L
+#define SC_DEBUG_9__early_z_enable_MASK                    0x00000040L
+#define SC_DEBUG_9__early_z_enable                         0x00000040L
+#define SC_DEBUG_9__mask_state_MASK                        0x00000180L
+#define SC_DEBUG_9__next_ez_mask_MASK                      0x01fffe00L
+#define SC_DEBUG_9__mask_ready_MASK                        0x02000000L
+#define SC_DEBUG_9__mask_ready                             0x02000000L
+#define SC_DEBUG_9__drop_sample_MASK                       0x04000000L
+#define SC_DEBUG_9__drop_sample                            0x04000000L
+#define SC_DEBUG_9__fetch_new_sample_data_MASK             0x08000000L
+#define SC_DEBUG_9__fetch_new_sample_data                  0x08000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK          0x10000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask               0x10000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK         0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data              0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK           0x40000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data                0x40000000L
+#define SC_DEBUG_9__trigger_MASK                           0x80000000L
+#define SC_DEBUG_9__trigger                                0x80000000L
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask_MASK             0x0000ffffL
+#define SC_DEBUG_10__trigger_MASK                          0x80000000L
+#define SC_DEBUG_10__trigger                               0x80000000L
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready_MASK             0x00000001L
+#define SC_DEBUG_11__ez_sample_data_ready                  0x00000001L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK        0x00000002L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data             0x00000002L
+#define SC_DEBUG_11__ez_prim_data_ready_MASK               0x00000004L
+#define SC_DEBUG_11__ez_prim_data_ready                    0x00000004L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK          0x00000008L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data               0x00000008L
+#define SC_DEBUG_11__iterator_input_fz_MASK                0x00000010L
+#define SC_DEBUG_11__iterator_input_fz                     0x00000010L
+#define SC_DEBUG_11__packer_send_quads_MASK                0x00000020L
+#define SC_DEBUG_11__packer_send_quads                     0x00000020L
+#define SC_DEBUG_11__packer_send_cmd_MASK                  0x00000040L
+#define SC_DEBUG_11__packer_send_cmd                       0x00000040L
+#define SC_DEBUG_11__packer_send_event_MASK                0x00000080L
+#define SC_DEBUG_11__packer_send_event                     0x00000080L
+#define SC_DEBUG_11__next_state_MASK                       0x00000700L
+#define SC_DEBUG_11__state_MASK                            0x00003800L
+#define SC_DEBUG_11__stall_MASK                            0x00004000L
+#define SC_DEBUG_11__stall                                 0x00004000L
+#define SC_DEBUG_11__trigger_MASK                          0x80000000L
+#define SC_DEBUG_11__trigger                               0x80000000L
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff_MASK            0x00000001L
+#define SC_DEBUG_12__SQ_iterator_free_buff                 0x00000001L
+#define SC_DEBUG_12__event_id_MASK                         0x0000003eL
+#define SC_DEBUG_12__event_flag_MASK                       0x00000040L
+#define SC_DEBUG_12__event_flag                            0x00000040L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK          0x00000080L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly               0x00000080L
+#define SC_DEBUG_12__itercmdfifo_full_MASK                 0x00000100L
+#define SC_DEBUG_12__itercmdfifo_full                      0x00000100L
+#define SC_DEBUG_12__itercmdfifo_empty_MASK                0x00000200L
+#define SC_DEBUG_12__itercmdfifo_empty                     0x00000200L
+#define SC_DEBUG_12__iter_ds_one_clk_command_MASK          0x00000400L
+#define SC_DEBUG_12__iter_ds_one_clk_command               0x00000400L
+#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK             0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_prim0                  0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_vector_MASK            0x00001000L
+#define SC_DEBUG_12__iter_ds_end_of_vector                 0x00001000L
+#define SC_DEBUG_12__iter_qdhit0_MASK                      0x00002000L
+#define SC_DEBUG_12__iter_qdhit0                           0x00002000L
+#define SC_DEBUG_12__bc_use_centers_reg_MASK               0x00004000L
+#define SC_DEBUG_12__bc_use_centers_reg                    0x00004000L
+#define SC_DEBUG_12__bc_output_xy_reg_MASK                 0x00008000L
+#define SC_DEBUG_12__bc_output_xy_reg                      0x00008000L
+#define SC_DEBUG_12__iter_phase_out_MASK                   0x00030000L
+#define SC_DEBUG_12__iter_phase_reg_MASK                   0x000c0000L
+#define SC_DEBUG_12__iterator_SP_valid_MASK                0x00100000L
+#define SC_DEBUG_12__iterator_SP_valid                     0x00100000L
+#define SC_DEBUG_12__eopv_reg_MASK                         0x00200000L
+#define SC_DEBUG_12__eopv_reg                              0x00200000L
+#define SC_DEBUG_12__one_clk_cmd_reg_MASK                  0x00400000L
+#define SC_DEBUG_12__one_clk_cmd_reg                       0x00400000L
+#define SC_DEBUG_12__iter_dx_end_of_prim_MASK              0x00800000L
+#define SC_DEBUG_12__iter_dx_end_of_prim                   0x00800000L
+#define SC_DEBUG_12__trigger_MASK                          0x80000000L
+#define SC_DEBUG_12__trigger                               0x80000000L
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK                  0x00000001L
+#define GFX_COPY_STATE__SRC_STATE_ID                       0x00000001L
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK                 0x0000003fL
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK             0x000000c0L
+#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT_MASK      0x00000300L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK                0x00000800L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE                     0x00000800L
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK                   0x00001000L
+#define VGT_DRAW_INITIATOR__NOT_EOP                        0x00001000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK               0x00002000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX                    0x00002000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK     0x00004000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE          0x00004000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK           0x00008000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE                0x00008000L
+#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK               0xffff0000L
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK               0x0000003fL
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR_MASK                       0xffffffffL
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_DMA_SIZE__SWAP_MODE_MASK                       0xc0000000L
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK                   0xffffffffL
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_BIN_SIZE__FACENESS_FETCH_MASK                  0x40000000L
+#define VGT_BIN_SIZE__FACENESS_FETCH                       0x40000000L
+#define VGT_BIN_SIZE__FACENESS_RESET_MASK                  0x80000000L
+#define VGT_BIN_SIZE__FACENESS_RESET                       0x80000000L
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK                    0x00ffffffL
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK                    0x00ffffffL
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK                  0x00ffffffL
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK  0x00000007L
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK            0x00000003L
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK      0x00ffffffL
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC_MASK                             0x0000ffffL
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK            0x0000001fL
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK             0x00000001L
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID                  0x00000001L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK             0x00010000L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID                  0x00010000L
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK                0x0000001fL
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK                     0x00000001L
+#define VGT_CNTL_STATUS__VGT_BUSY                          0x00000001L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK                 0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY                      0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK             0x00000004L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY                  0x00000004L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK                 0x00000008L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY                      0x00000008L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK                  0x00000010L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY                       0x00000010L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK                 0x00000020L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY                      0x00000020L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK                  0x00000040L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY                       0x00000040L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK                 0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY                      0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK            0x00000100L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY                 0x00000100L
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy_MASK                   0x00000001L
+#define VGT_DEBUG_REG0__te_grp_busy                        0x00000001L
+#define VGT_DEBUG_REG0__pt_grp_busy_MASK                   0x00000002L
+#define VGT_DEBUG_REG0__pt_grp_busy                        0x00000002L
+#define VGT_DEBUG_REG0__vr_grp_busy_MASK                   0x00000004L
+#define VGT_DEBUG_REG0__vr_grp_busy                        0x00000004L
+#define VGT_DEBUG_REG0__dma_request_busy_MASK              0x00000008L
+#define VGT_DEBUG_REG0__dma_request_busy                   0x00000008L
+#define VGT_DEBUG_REG0__out_busy_MASK                      0x00000010L
+#define VGT_DEBUG_REG0__out_busy                           0x00000010L
+#define VGT_DEBUG_REG0__grp_backend_busy_MASK              0x00000020L
+#define VGT_DEBUG_REG0__grp_backend_busy                   0x00000020L
+#define VGT_DEBUG_REG0__grp_busy_MASK                      0x00000040L
+#define VGT_DEBUG_REG0__grp_busy                           0x00000040L
+#define VGT_DEBUG_REG0__dma_busy_MASK                      0x00000080L
+#define VGT_DEBUG_REG0__dma_busy                           0x00000080L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK         0x00000100L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy              0x00000100L
+#define VGT_DEBUG_REG0__rbiu_busy_MASK                     0x00000200L
+#define VGT_DEBUG_REG0__rbiu_busy                          0x00000200L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK      0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended           0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK               0x00000800L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy                    0x00000800L
+#define VGT_DEBUG_REG0__vgt_busy_extended_MASK             0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_extended                  0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_MASK                      0x00002000L
+#define VGT_DEBUG_REG0__vgt_busy                           0x00002000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK       0x00004000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out            0x00004000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK          0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy               0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK                 0x00010000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy                      0x00010000L
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read_MASK              0x00000001L
+#define VGT_DEBUG_REG1__out_te_data_read                   0x00000001L
+#define VGT_DEBUG_REG1__te_out_data_valid_MASK             0x00000002L
+#define VGT_DEBUG_REG1__te_out_data_valid                  0x00000002L
+#define VGT_DEBUG_REG1__out_pt_prim_read_MASK              0x00000004L
+#define VGT_DEBUG_REG1__out_pt_prim_read                   0x00000004L
+#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK             0x00000008L
+#define VGT_DEBUG_REG1__pt_out_prim_valid                  0x00000008L
+#define VGT_DEBUG_REG1__out_pt_data_read_MASK              0x00000010L
+#define VGT_DEBUG_REG1__out_pt_data_read                   0x00000010L
+#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK             0x00000020L
+#define VGT_DEBUG_REG1__pt_out_indx_valid                  0x00000020L
+#define VGT_DEBUG_REG1__out_vr_prim_read_MASK              0x00000040L
+#define VGT_DEBUG_REG1__out_vr_prim_read                   0x00000040L
+#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK             0x00000080L
+#define VGT_DEBUG_REG1__vr_out_prim_valid                  0x00000080L
+#define VGT_DEBUG_REG1__out_vr_indx_read_MASK              0x00000100L
+#define VGT_DEBUG_REG1__out_vr_indx_read                   0x00000100L
+#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK             0x00000200L
+#define VGT_DEBUG_REG1__vr_out_indx_valid                  0x00000200L
+#define VGT_DEBUG_REG1__te_grp_read_MASK                   0x00000400L
+#define VGT_DEBUG_REG1__te_grp_read                        0x00000400L
+#define VGT_DEBUG_REG1__grp_te_valid_MASK                  0x00000800L
+#define VGT_DEBUG_REG1__grp_te_valid                       0x00000800L
+#define VGT_DEBUG_REG1__pt_grp_read_MASK                   0x00001000L
+#define VGT_DEBUG_REG1__pt_grp_read                        0x00001000L
+#define VGT_DEBUG_REG1__grp_pt_valid_MASK                  0x00002000L
+#define VGT_DEBUG_REG1__grp_pt_valid                       0x00002000L
+#define VGT_DEBUG_REG1__vr_grp_read_MASK                   0x00004000L
+#define VGT_DEBUG_REG1__vr_grp_read                        0x00004000L
+#define VGT_DEBUG_REG1__grp_vr_valid_MASK                  0x00008000L
+#define VGT_DEBUG_REG1__grp_vr_valid                       0x00008000L
+#define VGT_DEBUG_REG1__grp_dma_read_MASK                  0x00010000L
+#define VGT_DEBUG_REG1__grp_dma_read                       0x00010000L
+#define VGT_DEBUG_REG1__dma_grp_valid_MASK                 0x00020000L
+#define VGT_DEBUG_REG1__dma_grp_valid                      0x00020000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK              0x00040000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read                   0x00040000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK             0x00080000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid                  0x00080000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK                    0x00100000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr                         0x00100000L
+#define VGT_DEBUG_REG1__VGT_MH_send_MASK                   0x00200000L
+#define VGT_DEBUG_REG1__VGT_MH_send                        0x00200000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK             0x00400000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr                  0x00400000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK            0x00800000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send                 0x00800000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK             0x01000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr                  0x01000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK            0x02000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send                 0x02000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK             0x04000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr                  0x04000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK            0x08000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send                 0x08000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK                    0x10000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr                         0x10000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send_MASK                   0x20000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send                        0x20000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK                0x40000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q                     0x40000000L
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en_MASK                    0x00000001L
+#define VGT_DEBUG_REG3__vgt_clk_en                         0x00000001L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK              0x00000002L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en                   0x00000002L
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK          0x0000001fL
+#define VGT_DEBUG_REG6__right_word_indx_q_MASK             0x000003e0L
+#define VGT_DEBUG_REG6__input_data_valid_MASK              0x00000400L
+#define VGT_DEBUG_REG6__input_data_valid                   0x00000400L
+#define VGT_DEBUG_REG6__input_data_xfer_MASK               0x00000800L
+#define VGT_DEBUG_REG6__input_data_xfer                    0x00000800L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK        0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q             0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK        0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d             0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK    0x00004000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d         0x00004000L
+#define VGT_DEBUG_REG6__space_avail_from_shift_MASK        0x00008000L
+#define VGT_DEBUG_REG6__space_avail_from_shift             0x00008000L
+#define VGT_DEBUG_REG6__shifter_first_load_MASK            0x00010000L
+#define VGT_DEBUG_REG6__shifter_first_load                 0x00010000L
+#define VGT_DEBUG_REG6__di_state_sel_q_MASK                0x00020000L
+#define VGT_DEBUG_REG6__di_state_sel_q                     0x00020000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q   0x00040000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK         0x00080000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q              0x00080000L
+#define VGT_DEBUG_REG6__di_event_flag_q_MASK               0x00100000L
+#define VGT_DEBUG_REG6__di_event_flag_q                    0x00100000L
+#define VGT_DEBUG_REG6__read_draw_initiator_MASK           0x00200000L
+#define VGT_DEBUG_REG6__read_draw_initiator                0x00200000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK   0x00400000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter        0x00400000L
+#define VGT_DEBUG_REG6__last_shift_of_packet_MASK          0x00800000L
+#define VGT_DEBUG_REG6__last_shift_of_packet               0x00800000L
+#define VGT_DEBUG_REG6__last_decr_of_packet_MASK           0x01000000L
+#define VGT_DEBUG_REG6__last_decr_of_packet                0x01000000L
+#define VGT_DEBUG_REG6__extract_vector_MASK                0x02000000L
+#define VGT_DEBUG_REG6__extract_vector                     0x02000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr_MASK                0x04000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr                     0x04000000L
+#define VGT_DEBUG_REG6__destination_rtr_MASK               0x08000000L
+#define VGT_DEBUG_REG6__destination_rtr                    0x08000000L
+#define VGT_DEBUG_REG6__grp_trigger_MASK                   0x10000000L
+#define VGT_DEBUG_REG6__grp_trigger                        0x10000000L
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q_MASK            0x0000ffffL
+#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK       0x000f0000L
+#define VGT_DEBUG_REG7__shift_amount_extract_MASK          0x00f00000L
+#define VGT_DEBUG_REG7__di_prim_type_q_MASK                0x3f000000L
+#define VGT_DEBUG_REG7__current_source_sel_MASK            0xc0000000L
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel_MASK            0x00000003L
+#define VGT_DEBUG_REG8__left_word_indx_q_MASK              0x0000007cL
+#define VGT_DEBUG_REG8__input_data_cnt_MASK                0x00000f80L
+#define VGT_DEBUG_REG8__input_data_lsw_MASK                0x0001f000L
+#define VGT_DEBUG_REG8__input_data_msw_MASK                0x003e0000L
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q_MASK                 0x0000001fL
+#define VGT_DEBUG_REG9__next_stride_d_MASK                 0x000003e0L
+#define VGT_DEBUG_REG9__current_shift_q_MASK               0x00007c00L
+#define VGT_DEBUG_REG9__current_shift_d_MASK               0x000f8000L
+#define VGT_DEBUG_REG9__current_stride_q_MASK              0x01f00000L
+#define VGT_DEBUG_REG9__current_stride_d_MASK              0x3e000000L
+#define VGT_DEBUG_REG9__grp_trigger_MASK                   0x40000000L
+#define VGT_DEBUG_REG9__grp_trigger                        0x40000000L
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0      0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0    0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0    0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L
+#define VGT_DEBUG_REG10__di_state_sel_q_MASK               0x00000010L
+#define VGT_DEBUG_REG10__di_state_sel_q                    0x00000010L
+#define VGT_DEBUG_REG10__last_decr_of_packet_MASK          0x00000020L
+#define VGT_DEBUG_REG10__last_decr_of_packet               0x00000020L
+#define VGT_DEBUG_REG10__bin_valid_MASK                    0x00000040L
+#define VGT_DEBUG_REG10__bin_valid                         0x00000040L
+#define VGT_DEBUG_REG10__read_block_MASK                   0x00000080L
+#define VGT_DEBUG_REG10__read_block                        0x00000080L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK       0x00000100L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read            0x00000100L
+#define VGT_DEBUG_REG10__last_bit_enable_q_MASK            0x00000200L
+#define VGT_DEBUG_REG10__last_bit_enable_q                 0x00000200L
+#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK            0x00000400L
+#define VGT_DEBUG_REG10__last_bit_end_di_q                 0x00000400L
+#define VGT_DEBUG_REG10__selected_data_MASK                0x0007f800L
+#define VGT_DEBUG_REG10__mask_input_data_MASK              0x07f80000L
+#define VGT_DEBUG_REG10__gap_q_MASK                        0x08000000L
+#define VGT_DEBUG_REG10__gap_q                             0x08000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK            0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z                 0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK            0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y                 0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK            0x40000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x                 0x40000000L
+#define VGT_DEBUG_REG10__grp_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG10__grp_trigger                       0x80000000L
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK         0x0000001fL
+#define VGT_DEBUG_REG12__right_word_indx_q_MASK            0x000003e0L
+#define VGT_DEBUG_REG12__input_data_valid_MASK             0x00000400L
+#define VGT_DEBUG_REG12__input_data_valid                  0x00000400L
+#define VGT_DEBUG_REG12__input_data_xfer_MASK              0x00000800L
+#define VGT_DEBUG_REG12__input_data_xfer                   0x00000800L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK       0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q            0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK       0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d            0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK   0x00004000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d        0x00004000L
+#define VGT_DEBUG_REG12__space_avail_from_shift_MASK       0x00008000L
+#define VGT_DEBUG_REG12__space_avail_from_shift            0x00008000L
+#define VGT_DEBUG_REG12__shifter_first_load_MASK           0x00010000L
+#define VGT_DEBUG_REG12__shifter_first_load                0x00010000L
+#define VGT_DEBUG_REG12__di_state_sel_q_MASK               0x00020000L
+#define VGT_DEBUG_REG12__di_state_sel_q                    0x00020000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q  0x00040000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK        0x00080000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q             0x00080000L
+#define VGT_DEBUG_REG12__di_event_flag_q_MASK              0x00100000L
+#define VGT_DEBUG_REG12__di_event_flag_q                   0x00100000L
+#define VGT_DEBUG_REG12__read_draw_initiator_MASK          0x00200000L
+#define VGT_DEBUG_REG12__read_draw_initiator               0x00200000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK  0x00400000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter       0x00400000L
+#define VGT_DEBUG_REG12__last_shift_of_packet_MASK         0x00800000L
+#define VGT_DEBUG_REG12__last_shift_of_packet              0x00800000L
+#define VGT_DEBUG_REG12__last_decr_of_packet_MASK          0x01000000L
+#define VGT_DEBUG_REG12__last_decr_of_packet               0x01000000L
+#define VGT_DEBUG_REG12__extract_vector_MASK               0x02000000L
+#define VGT_DEBUG_REG12__extract_vector                    0x02000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr_MASK               0x04000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr                    0x04000000L
+#define VGT_DEBUG_REG12__destination_rtr_MASK              0x08000000L
+#define VGT_DEBUG_REG12__destination_rtr                   0x08000000L
+#define VGT_DEBUG_REG12__bgrp_trigger_MASK                 0x10000000L
+#define VGT_DEBUG_REG12__bgrp_trigger                      0x10000000L
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q_MASK           0x0000ffffL
+#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK      0x000f0000L
+#define VGT_DEBUG_REG13__shift_amount_extract_MASK         0x00f00000L
+#define VGT_DEBUG_REG13__di_prim_type_q_MASK               0x3f000000L
+#define VGT_DEBUG_REG13__current_source_sel_MASK           0xc0000000L
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel_MASK           0x00000003L
+#define VGT_DEBUG_REG14__left_word_indx_q_MASK             0x0000007cL
+#define VGT_DEBUG_REG14__input_data_cnt_MASK               0x00000f80L
+#define VGT_DEBUG_REG14__input_data_lsw_MASK               0x0001f000L
+#define VGT_DEBUG_REG14__input_data_msw_MASK               0x003e0000L
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q_MASK                0x0000001fL
+#define VGT_DEBUG_REG15__next_stride_d_MASK                0x000003e0L
+#define VGT_DEBUG_REG15__current_shift_q_MASK              0x00007c00L
+#define VGT_DEBUG_REG15__current_shift_d_MASK              0x000f8000L
+#define VGT_DEBUG_REG15__current_stride_q_MASK             0x01f00000L
+#define VGT_DEBUG_REG15__current_stride_d_MASK             0x3e000000L
+#define VGT_DEBUG_REG15__bgrp_trigger_MASK                 0x40000000L
+#define VGT_DEBUG_REG15__bgrp_trigger                      0x40000000L
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK    0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full         0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK   0x00000002L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty        0x00000002L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK     0x00000004L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read          0x00000004L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK      0x00000008L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we           0x00000008L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK     0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full          0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK    0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty         0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK     0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q          0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK       0x00000080L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we            0x00000080L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK           0x00000100L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill                0x00000100L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK           0x00000200L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid                0x00000200L
+#define VGT_DEBUG_REG16__rst_last_bit_MASK                 0x00000400L
+#define VGT_DEBUG_REG16__rst_last_bit                      0x00000400L
+#define VGT_DEBUG_REG16__current_state_q_MASK              0x00000800L
+#define VGT_DEBUG_REG16__current_state_q                   0x00000800L
+#define VGT_DEBUG_REG16__old_state_q_MASK                  0x00001000L
+#define VGT_DEBUG_REG16__old_state_q                       0x00001000L
+#define VGT_DEBUG_REG16__old_state_en_MASK                 0x00002000L
+#define VGT_DEBUG_REG16__old_state_en                      0x00002000L
+#define VGT_DEBUG_REG16__prev_last_bit_q_MASK              0x00004000L
+#define VGT_DEBUG_REG16__prev_last_bit_q                   0x00004000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK               0x00008000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q                    0x00008000L
+#define VGT_DEBUG_REG16__last_bit_block_q_MASK             0x00010000L
+#define VGT_DEBUG_REG16__last_bit_block_q                  0x00010000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK             0x00020000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q                  0x00020000L
+#define VGT_DEBUG_REG16__load_empty_reg_MASK               0x00040000L
+#define VGT_DEBUG_REG16__load_empty_reg                    0x00040000L
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK     0x07f80000L
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK  0x18000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable      0x20000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK     0x40000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q          0x40000000L
+#define VGT_DEBUG_REG16__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG16__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q_MASK                  0x00000001L
+#define VGT_DEBUG_REG17__save_read_q                       0x00000001L
+#define VGT_DEBUG_REG17__extend_read_q_MASK                0x00000002L
+#define VGT_DEBUG_REG17__extend_read_q                     0x00000002L
+#define VGT_DEBUG_REG17__grp_indx_size_MASK                0x0000000cL
+#define VGT_DEBUG_REG17__cull_prim_true_MASK               0x00000010L
+#define VGT_DEBUG_REG17__cull_prim_true                    0x00000010L
+#define VGT_DEBUG_REG17__reset_bit2_q_MASK                 0x00000020L
+#define VGT_DEBUG_REG17__reset_bit2_q                      0x00000020L
+#define VGT_DEBUG_REG17__reset_bit1_q_MASK                 0x00000040L
+#define VGT_DEBUG_REG17__reset_bit1_q                      0x00000040L
+#define VGT_DEBUG_REG17__first_reg_first_q_MASK            0x00000080L
+#define VGT_DEBUG_REG17__first_reg_first_q                 0x00000080L
+#define VGT_DEBUG_REG17__check_second_reg_MASK             0x00000100L
+#define VGT_DEBUG_REG17__check_second_reg                  0x00000100L
+#define VGT_DEBUG_REG17__check_first_reg_MASK              0x00000200L
+#define VGT_DEBUG_REG17__check_first_reg                   0x00000200L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK   0x00000400L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata        0x00000400L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK      0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q           0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK      0x00001000L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q           0x00001000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK       0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q            0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK       0x00004000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q            0x00004000L
+#define VGT_DEBUG_REG17__to_second_reg_q_MASK              0x00008000L
+#define VGT_DEBUG_REG17__to_second_reg_q                   0x00008000L
+#define VGT_DEBUG_REG17__roll_over_msk_q_MASK              0x00010000L
+#define VGT_DEBUG_REG17__roll_over_msk_q                   0x00010000L
+#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK                0x00fe0000L
+#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK                0x7f000000L
+#define VGT_DEBUG_REG17__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG17__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK      0x0000003fL
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK      0x00000fc0L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK   0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re        0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK  0x00006000L
+#define VGT_DEBUG_REG18__dma_mem_full_MASK                 0x00008000L
+#define VGT_DEBUG_REG18__dma_mem_full                      0x00008000L
+#define VGT_DEBUG_REG18__dma_ram_re_MASK                   0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_re                        0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_we_MASK                   0x00020000L
+#define VGT_DEBUG_REG18__dma_ram_we                        0x00020000L
+#define VGT_DEBUG_REG18__dma_mem_empty_MASK                0x00040000L
+#define VGT_DEBUG_REG18__dma_mem_empty                     0x00040000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK         0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re              0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK         0x00100000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we              0x00100000L
+#define VGT_DEBUG_REG18__bin_mem_full_MASK                 0x00200000L
+#define VGT_DEBUG_REG18__bin_mem_full                      0x00200000L
+#define VGT_DEBUG_REG18__bin_ram_we_MASK                   0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_we                        0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_re_MASK                   0x00800000L
+#define VGT_DEBUG_REG18__bin_ram_re                        0x00800000L
+#define VGT_DEBUG_REG18__bin_mem_empty_MASK                0x01000000L
+#define VGT_DEBUG_REG18__bin_mem_empty                     0x01000000L
+#define VGT_DEBUG_REG18__start_bin_req_MASK                0x02000000L
+#define VGT_DEBUG_REG18__start_bin_req                     0x02000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK          0x04000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used               0x04000000L
+#define VGT_DEBUG_REG18__dma_req_xfer_MASK                 0x08000000L
+#define VGT_DEBUG_REG18__dma_req_xfer                      0x08000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req_MASK           0x10000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req                0x10000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req_MASK           0x20000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req                0x20000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK  0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable       0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK         0x00000001L
+#define VGT_DEBUG_REG20__prim_side_indx_valid              0x00000001L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK         0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty              0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK            0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_re                 0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK            0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_we                 0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK          0x00000010L
+#define VGT_DEBUG_REG20__indx_side_fifo_full               0x00000010L
+#define VGT_DEBUG_REG20__prim_buffer_empty_MASK            0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_empty                 0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_re_MASK               0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_re                    0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_we_MASK               0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_we                    0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_full_MASK             0x00000100L
+#define VGT_DEBUG_REG20__prim_buffer_full                  0x00000100L
+#define VGT_DEBUG_REG20__indx_buffer_empty_MASK            0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_empty                 0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_re_MASK               0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_re                    0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_we_MASK               0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_we                    0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_full_MASK             0x00001000L
+#define VGT_DEBUG_REG20__indx_buffer_full                  0x00001000L
+#define VGT_DEBUG_REG20__hold_prim_MASK                    0x00002000L
+#define VGT_DEBUG_REG20__hold_prim                         0x00002000L
+#define VGT_DEBUG_REG20__sent_cnt_MASK                     0x0003c000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK          0x00040000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector               0x00040000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK         0x00080000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim              0x00080000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK         0x00100000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim              0x00100000L
+#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK     0x03e00000L
+#define VGT_DEBUG_REG20__out_trigger_MASK                  0x04000000L
+#define VGT_DEBUG_REG20__out_trigger                       0x04000000L
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK    0x00000001L
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector         0x00000001L
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK   0x0000000eL
+#define VGT_DEBUG_REG21__alloc_counter_q_MASK              0x00000070L
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK      0x00000380L
+#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK            0x00003c00L
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK      0x0003c000L
+#define VGT_DEBUG_REG21__new_packet_q_MASK                 0x00040000L
+#define VGT_DEBUG_REG21__new_packet_q                      0x00040000L
+#define VGT_DEBUG_REG21__new_allocate_q_MASK               0x00080000L
+#define VGT_DEBUG_REG21__new_allocate_q                    0x00080000L
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK      0x00300000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK         0x00400000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q              0x00400000L
+#define VGT_DEBUG_REG21__insert_null_prim_MASK             0x00800000L
+#define VGT_DEBUG_REG21__insert_null_prim                  0x00800000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK        0x01000000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux             0x01000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK        0x02000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux             0x02000000L
+#define VGT_DEBUG_REG21__buffered_thread_size_MASK         0x04000000L
+#define VGT_DEBUG_REG21__buffered_thread_size              0x04000000L
+#define VGT_DEBUG_REG21__out_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG21__out_trigger                       0x80000000L
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC_MASK                          0xffffffffL
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC_MASK                          0xffffffffL
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE_MASK                 0x00000001L
+#define TC_CNTL_STATUS__L2_INVALIDATE                      0x00000001L
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK                0x000c0000L
+#define TC_CNTL_STATUS__TC_BUSY_MASK                       0x80000000L
+#define TC_CNTL_STATUS__TC_BUSY                            0x80000000L
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK                 0x00000100L
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN                      0x00000100L
+#define TCM_CHICKEN__SPARE_MASK                            0xfffffe00L
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK            0x00000007L
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK            0x00000038L
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK               0x00000001L
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY                    0x00000001L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK             0x00000002L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY                  0x00000002L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK          0x00000004L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY               0x00000004L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK          0x00000008L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY               0x00000008L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK         0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY              0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK           0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY                0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK              0x00000040L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY                   0x00000040L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK        0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY             0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK          0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY               0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK             0x00000400L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY                  0x00000400L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK             0x00001000L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY                  0x00001000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK          0x00002000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY               0x00002000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK            0x00004000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY                 0x00004000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK               0x00008000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY                    0x00008000L
+#define TPC_CNTL_STATUS__TF_TW_RTS_MASK                    0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_RTS                         0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK              0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS                   0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_RTR_MASK                    0x00080000L
+#define TPC_CNTL_STATUS__TF_TW_RTR                         0x00080000L
+#define TPC_CNTL_STATUS__TW_TA_RTS_MASK                    0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_RTS                         0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK                 0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS                      0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK               0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS                    0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_RTR_MASK                    0x00800000L
+#define TPC_CNTL_STATUS__TW_TA_RTR                         0x00800000L
+#define TPC_CNTL_STATUS__TA_TB_RTS_MASK                    0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_RTS                         0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK                 0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS                      0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR_MASK                    0x08000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR                         0x08000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS_MASK                    0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS                         0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK            0x20000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN                 0x20000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK                    0x40000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC                         0x40000000L
+#define TPC_CNTL_STATUS__TPC_BUSY_MASK                     0x80000000L
+#define TPC_CNTL_STATUS__TPC_BUSY                          0x80000000L
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL_MASK                          0x00000003L
+#define TPC_DEBUG0__IC_CTR_MASK                            0x0000000cL
+#define TPC_DEBUG0__WALKER_CNTL_MASK                       0x000000f0L
+#define TPC_DEBUG0__ALIGNER_CNTL_MASK                      0x00000700L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK               0x00001000L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID                    0x00001000L
+#define TPC_DEBUG0__WALKER_STATE_MASK                      0x03ff0000L
+#define TPC_DEBUG0__ALIGNER_STATE_MASK                     0x0c000000L
+#define TPC_DEBUG0__REG_CLK_EN_MASK                        0x20000000L
+#define TPC_DEBUG0__REG_CLK_EN                             0x20000000L
+#define TPC_DEBUG0__TPC_CLK_EN_MASK                        0x40000000L
+#define TPC_DEBUG0__TPC_CLK_EN                             0x40000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK                      0x80000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP                           0x80000000L
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED_MASK                            0x00000001L
+#define TPC_DEBUG1__UNUSED                                 0x00000001L
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION_MASK                  0x00000001L
+#define TPC_CHICKEN__BLEND_PRECISION                       0x00000001L
+#define TPC_CHICKEN__SPARE_MASK                            0xfffffffeL
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK                0x00000001L
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY                     0x00000001L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK                  0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY                       0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK             0x00000004L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY                  0x00000004L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK                 0x00000008L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY                      0x00000008L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK           0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY                0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK              0x00000020L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY                   0x00000020L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK              0x00000040L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY                   0x00000040L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK              0x00000080L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY                   0x00000080L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK                0x00000100L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY                     0x00000100L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK             0x00000200L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY                  0x00000200L
+#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK                   0x00000400L
+#define TP0_CNTL_STATUS__TP_TT_BUSY                        0x00000400L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK              0x00000800L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY                   0x00000800L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK                0x00001000L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY                     0x00001000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK             0x00002000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY                  0x00002000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK               0x00004000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY                    0x00004000L
+#define TP0_CNTL_STATUS__IN_LC_RTS_MASK                    0x00010000L
+#define TP0_CNTL_STATUS__IN_LC_RTS                         0x00010000L
+#define TP0_CNTL_STATUS__LC_LA_RTS_MASK                    0x00020000L
+#define TP0_CNTL_STATUS__LC_LA_RTS                         0x00020000L
+#define TP0_CNTL_STATUS__LA_FL_RTS_MASK                    0x00040000L
+#define TP0_CNTL_STATUS__LA_FL_RTS                         0x00040000L
+#define TP0_CNTL_STATUS__FL_TA_RTS_MASK                    0x00080000L
+#define TP0_CNTL_STATUS__FL_TA_RTS                         0x00080000L
+#define TP0_CNTL_STATUS__TA_FA_RTS_MASK                    0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_RTS                         0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK                 0x00200000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS                      0x00200000L
+#define TP0_CNTL_STATUS__FA_AL_RTS_MASK                    0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_RTS                         0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK                 0x00800000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS                      0x00800000L
+#define TP0_CNTL_STATUS__AL_TF_RTS_MASK                    0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_RTS                         0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK                 0x02000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS                      0x02000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS_MASK                    0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS                         0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK                 0x08000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS                      0x08000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS_MASK                    0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS                         0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK               0x20000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET                    0x20000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS_MASK                    0x40000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS                         0x40000000L
+#define TP0_CNTL_STATUS__TP_BUSY_MASK                      0x80000000L
+#define TP0_CNTL_STATUS__TP_BUSY                           0x80000000L
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL_MASK                         0x00000003L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK                     0x00000008L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP                          0x00000008L
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK               0x001ffff0L
+#define TP0_DEBUG__REG_CLK_EN_MASK                         0x00200000L
+#define TP0_DEBUG__REG_CLK_EN                              0x00200000L
+#define TP0_DEBUG__PERF_CLK_EN_MASK                        0x00400000L
+#define TP0_DEBUG__PERF_CLK_EN                             0x00400000L
+#define TP0_DEBUG__TP_CLK_EN_MASK                          0x00800000L
+#define TP0_DEBUG__TP_CLK_EN                               0x00800000L
+#define TP0_DEBUG__Q_WALKER_CNTL_MASK                      0x0f000000L
+#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK                     0x70000000L
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE_MASK                          0x00000001L
+#define TP0_CHICKEN__TT_MODE                               0x00000001L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK              0x00000002L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE                   0x00000002L
+#define TP0_CHICKEN__SPARE_MASK                            0xfffffffcL
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr_MASK                      0x00000040L
+#define TCF_DEBUG__not_MH_TC_rtr                           0x00000040L
+#define TCF_DEBUG__TC_MH_send_MASK                         0x00000080L
+#define TCF_DEBUG__TC_MH_send                              0x00000080L
+#define TCF_DEBUG__not_FG0_rtr_MASK                        0x00000100L
+#define TCF_DEBUG__not_FG0_rtr                             0x00000100L
+#define TCF_DEBUG__not_TCB_TCO_rtr_MASK                    0x00001000L
+#define TCF_DEBUG__not_TCB_TCO_rtr                         0x00001000L
+#define TCF_DEBUG__TCB_ff_stall_MASK                       0x00002000L
+#define TCF_DEBUG__TCB_ff_stall                            0x00002000L
+#define TCF_DEBUG__TCB_miss_stall_MASK                     0x00004000L
+#define TCF_DEBUG__TCB_miss_stall                          0x00004000L
+#define TCF_DEBUG__TCA_TCB_stall_MASK                      0x00008000L
+#define TCF_DEBUG__TCA_TCB_stall                           0x00008000L
+#define TCF_DEBUG__PF0_stall_MASK                          0x00010000L
+#define TCF_DEBUG__PF0_stall                               0x00010000L
+#define TCF_DEBUG__TP0_full_MASK                           0x00100000L
+#define TCF_DEBUG__TP0_full                                0x00100000L
+#define TCF_DEBUG__TPC_full_MASK                           0x01000000L
+#define TCF_DEBUG__TPC_full                                0x01000000L
+#define TCF_DEBUG__not_TPC_rtr_MASK                        0x02000000L
+#define TCF_DEBUG__not_TPC_rtr                             0x02000000L
+#define TCF_DEBUG__tca_state_rts_MASK                      0x04000000L
+#define TCF_DEBUG__tca_state_rts                           0x04000000L
+#define TCF_DEBUG__tca_rts_MASK                            0x08000000L
+#define TCF_DEBUG__tca_rts                                 0x08000000L
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full_MASK                      0x00000001L
+#define TCA_FIFO_DEBUG__tp0_full                           0x00000001L
+#define TCA_FIFO_DEBUG__tpc_full_MASK                      0x00000010L
+#define TCA_FIFO_DEBUG__tpc_full                           0x00000010L
+#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK                 0x00000020L
+#define TCA_FIFO_DEBUG__load_tpc_fifo                      0x00000020L
+#define TCA_FIFO_DEBUG__load_tp_fifos_MASK                 0x00000040L
+#define TCA_FIFO_DEBUG__load_tp_fifos                      0x00000040L
+#define TCA_FIFO_DEBUG__FW_full_MASK                       0x00000080L
+#define TCA_FIFO_DEBUG__FW_full                            0x00000080L
+#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK                   0x00000100L
+#define TCA_FIFO_DEBUG__not_FW_rtr0                        0x00000100L
+#define TCA_FIFO_DEBUG__FW_rts0_MASK                       0x00001000L
+#define TCA_FIFO_DEBUG__FW_rts0                            0x00001000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK                0x00010000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr                     0x00010000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK                    0x00020000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts                         0x00020000L
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK            0x00000001L
+#define TCA_PROBE_DEBUG__ProbeFilter_stall                 0x00000001L
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts_MASK               0x00001000L
+#define TCA_TPC_DEBUG__captue_state_rts                    0x00001000L
+#define TCA_TPC_DEBUG__capture_tca_rts_MASK                0x00002000L
+#define TCA_TPC_DEBUG__capture_tca_rts                     0x00002000L
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512_MASK                     0x00000001L
+#define TCB_CORE_DEBUG__access512                          0x00000001L
+#define TCB_CORE_DEBUG__tiled_MASK                         0x00000002L
+#define TCB_CORE_DEBUG__tiled                              0x00000002L
+#define TCB_CORE_DEBUG__opcode_MASK                        0x00000070L
+#define TCB_CORE_DEBUG__format_MASK                        0x00003f00L
+#define TCB_CORE_DEBUG__sector_format_MASK                 0x001f0000L
+#define TCB_CORE_DEBUG__sector_format512_MASK              0x07000000L
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG0_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG0_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG0_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG0_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG0_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG1_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG1_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG1_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG1_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG1_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG2_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG2_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG2_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG2_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG2_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG3_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG3_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG3_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG3_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG3_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done      0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left    0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q   0x10000000L
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK     0x00000030L
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK      0x000000c0L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK     0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left          0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK     0x00007000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK              0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy                   0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK  0x000f0000L
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK        0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts             0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK         0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts              0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK      0x0000fff0L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK   0x001f0000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK               0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy                    0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK           0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy                0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK            0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy                 0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK           0x0c000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK            0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q                 0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK            0x40000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR                 0x40000000L
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty_MASK                       0x00010000L
+#define TCD_INPUT0_DEBUG__empty                            0x00010000L
+#define TCD_INPUT0_DEBUG__full_MASK                        0x00020000L
+#define TCD_INPUT0_DEBUG__full                             0x00020000L
+#define TCD_INPUT0_DEBUG__valid_q1_MASK                    0x00100000L
+#define TCD_INPUT0_DEBUG__valid_q1                         0x00100000L
+#define TCD_INPUT0_DEBUG__cnt_q1_MASK                      0x00600000L
+#define TCD_INPUT0_DEBUG__last_send_q1_MASK                0x00800000L
+#define TCD_INPUT0_DEBUG__last_send_q1                     0x00800000L
+#define TCD_INPUT0_DEBUG__ip_send_MASK                     0x01000000L
+#define TCD_INPUT0_DEBUG__ip_send                          0x01000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK              0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send                   0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK                  0x04000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy                       0x04000000L
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK        0x00000003L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK            0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8                 0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK        0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send             0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK             0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send                  0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK                 0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall                      0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK                0x00000040L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate                     0x00000040L
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK               0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate                    0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK           0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr                0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK             0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr                  0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send      0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK  0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts       0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK    0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send         0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send     0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK     0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send          0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK        0x20000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send             0x20000000L
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK                  0x00000010L
+#define TCD_DXTC_ARB_DEBUG__n0_stall                       0x00000010L
+#define TCD_DXTC_ARB_DEBUG__pstate_MASK                    0x00000020L
+#define TCD_DXTC_ARB_DEBUG__pstate                         0x00000020L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK      0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send           0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK            0x00000180L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK         0x00000e00L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK      0x0003f000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK         0x3ffc0000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK           0x40000000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send                0x40000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK           0x80000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types                0x80000000L
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK     0x00000400L
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr          0x00000400L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK     0x00000800L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr          0x00000800L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK           0x00020000L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr                0x00020000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK         0x00040000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr              0x00040000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK            0x00080000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr                 0x00080000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK            0x80000000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr                 0x80000000L
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK            0x00000020L
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR                 0x00000020L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK             0x00000040L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR                  0x00000040L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK         0x00000080L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d              0x00000080L
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK         0x000000ffL
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK         0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample              0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK                   0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr                        0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK                   0x00000400L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts                        0x00000400L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK        0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample             0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK                  0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr                       0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK                  0x00002000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts                       0x00002000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK             0x00010000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q                  0x00010000L
+#define TCO_QUAD0_DEBUG0__read_cache_q_MASK                0x01000000L
+#define TCO_QUAD0_DEBUG0__read_cache_q                     0x01000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK              0x02000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR                   0x02000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK    0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3         0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK    0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2         0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK    0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1         0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK    0x20000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0         0x20000000L
+#define TCO_QUAD0_DEBUG0__busy_MASK                        0x40000000L
+#define TCO_QUAD0_DEBUG0__busy                             0x40000000L
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy_MASK                   0x00000001L
+#define TCO_QUAD0_DEBUG1__fifo_busy                        0x00000001L
+#define TCO_QUAD0_DEBUG1__empty_MASK                       0x00000002L
+#define TCO_QUAD0_DEBUG1__empty                            0x00000002L
+#define TCO_QUAD0_DEBUG1__full_MASK                        0x00000004L
+#define TCO_QUAD0_DEBUG1__full                             0x00000004L
+#define TCO_QUAD0_DEBUG1__write_enable_MASK                0x00000008L
+#define TCO_QUAD0_DEBUG1__write_enable                     0x00000008L
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK              0x000007f0L
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK               0x0003f800L
+#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK             0x00100000L
+#define TCO_QUAD0_DEBUG1__cache_read_busy                  0x00100000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK           0x00200000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy                0x00200000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK             0x00400000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy                  0x00400000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK          0x00800000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy               0x00800000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK               0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d                    0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK               0x02000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q                    0x02000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK                   0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr                        0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK                   0x08000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts                        0x08000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK                  0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr                       0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK                  0x20000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts                       0x20000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK            0x40000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc                 0x40000000L
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK                0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC                     0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK               0x000007f0L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK               0x0007f000L
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK     0x00000003L
+#define SQ_FLOW_CONTROL__ONE_THREAD_MASK                   0x00000010L
+#define SQ_FLOW_CONTROL__ONE_THREAD                        0x00000010L
+#define SQ_FLOW_CONTROL__ONE_ALU_MASK                      0x00000100L
+#define SQ_FLOW_CONTROL__ONE_ALU                           0x00000100L
+#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK                   0x0000f000L
+#define SQ_FLOW_CONTROL__NO_PV_PS_MASK                     0x00010000L
+#define SQ_FLOW_CONTROL__NO_PV_PS                          0x00010000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK                 0x00020000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT                      0x00020000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK            0x00040000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE                 0x00040000L
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK   0x00180000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK        0x00200000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY             0x00200000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK       0x00400000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY            0x00400000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK                 0x00800000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT                      0x00800000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK                 0x01000000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT                      0x01000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK             0x02000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY                  0x02000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK  0x04000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION       0x04000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK      0x08000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC           0x08000000L
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK        0x00000fffL
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK        0x0fff0000L
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK     0x01ff0000L
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT_MASK                     0x000000ffL
+#define SQ_EO_RT__EO_TSTATE_RT_MASK                        0x00ff0000L
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK                 0x000007ffL
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK                 0x000ff000L
+#define SQ_DEBUG_MISC__DB_READ_CTX_MASK                    0x00100000L
+#define SQ_DEBUG_MISC__DB_READ_CTX                         0x00100000L
+#define SQ_DEBUG_MISC__RESERVED_MASK                       0x00600000L
+#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK                 0x01800000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK                0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0                     0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK                0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1                     0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK                0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2                     0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK                0x10000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3                     0x10000000L
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK              0x000000ffL
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK         0x0000ff00L
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK        0x00ff0000L
+#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK                 0xff000000L
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK        0x000000ffL
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK        0x00000007L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK          0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN               0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK        0x00000070L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK          0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN               0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK              0x0003ff00L
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK       0x00000007L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK         0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN              0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK       0x00000070L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK         0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN              0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK             0x0003ff00L
+#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK              0x000c0000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK  0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL       0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK  0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL       0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L
+
+// SQ_VS_WATCHDOG_TIMER
+#define SQ_VS_WATCHDOG_TIMER__ENABLE_MASK                  0x00000001L
+#define SQ_VS_WATCHDOG_TIMER__ENABLE                       0x00000001L
+#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK           0xfffffffeL
+
+// SQ_PS_WATCHDOG_TIMER
+#define SQ_PS_WATCHDOG_TIMER__ENABLE_MASK                  0x00000001L
+#define SQ_PS_WATCHDOG_TIMER__ENABLE                       0x00000001L
+#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK           0xfffffffeL
+
+// SQ_INT_CNTL
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK_MASK                 0x00000001L
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK                      0x00000001L
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK_MASK                 0x00000002L
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK                      0x00000002L
+
+// SQ_INT_STATUS
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT_MASK            0x00000001L
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT                 0x00000001L
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT_MASK            0x00000002L
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT                 0x00000002L
+
+// SQ_INT_ACK
+#define SQ_INT_ACK__PS_WATCHDOG_ACK_MASK                   0x00000001L
+#define SQ_INT_ACK__PS_WATCHDOG_ACK                        0x00000001L
+#define SQ_INT_ACK__VS_WATCHDOG_ACK_MASK                   0x00000002L
+#define SQ_INT_ACK__VS_WATCHDOG_ACK                        0x00000002L
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK                 0x00000007L
+#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK                  0x00000008L
+#define SQ_DEBUG_INPUT_FSM__RESERVED                       0x00000008L
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK                 0x000000f0L
+#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK                   0x00000700L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1                      0x00000800L
+#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK                     0x00007000L
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK             0x000f8000L
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK               0x0ff00000L
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK             0x000000e0L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK             0x0000e000L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK  0x00030000L
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK  0x000c0000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK  0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE       0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK  0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE       0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK  0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE       0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK  0x00800000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE       0x00800000L
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP_MASK                        0x00000007L
+#define SQ_DEBUG_TP_FSM__RESERVED0_MASK                    0x00000008L
+#define SQ_DEBUG_TP_FSM__RESERVED0                         0x00000008L
+#define SQ_DEBUG_TP_FSM__CF_TP_MASK                        0x000000f0L
+#define SQ_DEBUG_TP_FSM__IF_TP_MASK                        0x00000700L
+#define SQ_DEBUG_TP_FSM__RESERVED1_MASK                    0x00000800L
+#define SQ_DEBUG_TP_FSM__RESERVED1                         0x00000800L
+#define SQ_DEBUG_TP_FSM__TIS_TP_MASK                       0x00003000L
+#define SQ_DEBUG_TP_FSM__RESERVED2_MASK                    0x0000c000L
+#define SQ_DEBUG_TP_FSM__GS_TP_MASK                        0x00030000L
+#define SQ_DEBUG_TP_FSM__RESERVED3_MASK                    0x000c0000L
+#define SQ_DEBUG_TP_FSM__FCR_TP_MASK                       0x00300000L
+#define SQ_DEBUG_TP_FSM__RESERVED4_MASK                    0x00c00000L
+#define SQ_DEBUG_TP_FSM__FCS_TP_MASK                       0x03000000L
+#define SQ_DEBUG_TP_FSM__RESERVED5_MASK                    0x0c000000L
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK                    0x70000000L
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK             0x0000000fL
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK           0x00000ff0L
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK              0x00007000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK                  0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED                       0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK       0x003f0000L
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK              0x00000001L
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER                   0x00000001L
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK                0x0000001eL
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK            0x00000020L
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR                 0x00000020L
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK           0x000001c0L
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK                0x00003e00L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK                 0x00004000L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT                      0x00004000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK          0x00008000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON               0x00008000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK                   0x00010000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY                        0x00010000L
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK               0x0ffe0000L
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_VTX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_VTX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_VTX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_PIX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_PIX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_PIX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN     0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN     0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK     0x60000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC    0x80000000L
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK             0x0000000fL
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK                 0x000000f0L
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK                 0x00000f00L
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK          0x0000f000L
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK           0x000f0000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK              0x00100000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL                   0x00100000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK                     0x00200000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q                          0x00200000L
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK                0x0000ffffL
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK     0xffffffffL
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK       0xffffffffL
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK               0x0000003fL
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK                   0x00000fc0L
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK                   0x0007f000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK          0x01f80000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK            0x7e000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY_MASK                       0x80000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY                            0x80000000L
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK   0xffffffffL
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL_MASK          0x00000040L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL               0x00000040L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK    0x00000080L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP         0x00000080L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL_MASK          0x00004000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL               0x00004000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK             0x00008000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA                  0x00008000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK          0x000f0000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK          0x00f00000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK            0x01000000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP                 0x01000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK            0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP                 0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK           0xfc000000L
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK         0x00000003L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK         0x0000000cL
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK         0x00000030L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK         0x000000c0L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK         0x00000300L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK         0x00000c00L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK         0x00003000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK         0x0000c000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK         0x00030000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK         0x000c0000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK         0x00300000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK         0x00c00000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK           0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD                0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK           0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD                0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK           0x04000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD                0x04000000L
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK             0x18000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK           0x20000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR                0x20000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK         0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS              0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK         0x80000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS              0x80000000L
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK            0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C                 0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK           0x00000080L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C                0x00000080L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK            0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B                 0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK           0x00008000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B                0x00008000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK           0x003f0000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK            0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A                 0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK           0x00800000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A                0x00800000L
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK           0x1f000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK               0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL                    0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK               0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL                    0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK               0x80000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK             0x000001ffL
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK            0x00000e00L
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK               0x00007000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK               0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD                    0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK         0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0              0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0            0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK         0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1              0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK       0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1            0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK         0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2              0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK       0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2            0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK         0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3              0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK       0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3            0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK         0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4              0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK       0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4            0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK         0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5              0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK       0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5            0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK           0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0                0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK           0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1                0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK           0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2                0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK           0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3                0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK           0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4                0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK           0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5                0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK           0x000003fcL
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK           0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION                0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK             0x01ff0000L
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK            0x0e000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK               0x70000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK               0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK         0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0              0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0            0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK         0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1              0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK       0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1            0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK         0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2              0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK       0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2            0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK         0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3              0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK       0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3            0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK         0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4              0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK       0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4            0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK         0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5              0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK       0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5            0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK           0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0                0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK           0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1                0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK           0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2                0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK           0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3                0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK           0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4                0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK           0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5                0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK           0x03fc0000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK           0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION                0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK             0x000003ffL
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK          0x0000fc00L
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK             0x001f0000L
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK          0xffe00000L
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK          0x000007ffL
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK             0x03ff0000L
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK          0xfc000000L
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK             0x0000001fL
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK            0x07ffffe0L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK         0x000003ffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK      0x00001c00L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK      0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL           0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK  0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP       0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK      0xffff8000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK      0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0           0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION            0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK       0x000003fcL
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK       0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION            0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK    0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE         0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK          0x0000f000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK         0x03ff0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK      0x1c000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK      0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL           0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK      0xc0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK        0x0001ffffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION            0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK       0x03fc0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK       0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION            0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK    0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE         0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK          0xf0000000L
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK               0x0000000fL
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK           0xfffffff0L
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK         0x000000ffL
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK          0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL               0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK      0x00000600L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK         0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE              0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK             0x0000f000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK               0x000f0000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK         0xfff00000L
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK           0x00ffffffL
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK          0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL               0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK      0x06000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK         0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE              0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK             0xf0000000L
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK     0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY          0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK      0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM           0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK            0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK            0x30000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK            0xc0000000L
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK           0x00003000L
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK           0x0000c000L
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK           0x00030000L
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK         0x001c0000L
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK     0x00e00000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK       0x03000000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK       0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK         0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD              0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK          0x60000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK    0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS         0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK      0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION           0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK             0x000001fcL
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK               0x0000fe00L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK             0x001f0000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK             0x03e00000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK             0x7c000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK          0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE               0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK      0x06000000L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK              0xc0000000L
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK      0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL           0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK       0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL            0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK   0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL        0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK          0x003f0000L
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK       0x3f800000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK               0x000000ffL
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK               0x00ff0000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED_MASK                            0xffffffffL
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN_MASK                          0xffffffffL
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE_MASK                           0xffffffffL
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA_MASK                          0xffffffffL
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE_MASK                             0xffffffffL
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE_MASK                    0x00000001L
+#define SQ_CONSTANT_VFETCH_0__TYPE                         0x00000001L
+#define SQ_CONSTANT_VFETCH_0__STATE_MASK                   0x00000002L
+#define SQ_CONSTANT_VFETCH_0__STATE                        0x00000002L
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK            0xfffffffcL
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK             0x00000003L
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK           0xfffffffcL
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE_MASK                         0xffffffffL
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE_MASK                         0xffffffffL
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK                 0x000000ffL
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK                 0x0000ff00L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK                 0x00ff0000L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK                 0xff000000L
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK                     0x000000ffL
+#define SQ_CF_LOOP__CF_LOOP_START_MASK                     0x0000ff00L
+#define SQ_CF_LOOP__CF_LOOP_STEP_MASK                      0x00ff0000L
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED_MASK                         0xffffffffL
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN_MASK                       0xffffffffL
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE_MASK                        0xffffffffL
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA_MASK                       0xffffffffL
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE_MASK                          0xffffffffL
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK              0x000000ffL
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK              0x0000ff00L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK              0x00ff0000L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK              0xff000000L
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK                  0x000000ffL
+#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK                  0x0000ff00L
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK                   0x00ff0000L
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_VS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_PS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK                0x000007ffL
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK                0x007ff000L
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK             0x0000ffffL
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK        0xffff0000L
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK                   0x0000003fL
+#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK                   0x00003f00L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK                  0x00010000L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE                       0x00010000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK                  0x00020000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE                       0x00020000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK                    0x00040000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN                         0x00040000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK                0x00080000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX                     0x00080000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK              0x00f00000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK               0x07000000L
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK               0x78000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK                0x80000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX                     0x80000000L
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK                   0x0000000fL
+#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK                   0x000000f0L
+#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK                   0x00000f00L
+#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK                   0x0000f000L
+#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK                   0x000f0000L
+#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK                   0x00f00000L
+#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK                   0x0f000000L
+#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK                   0xf0000000L
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK                   0x0000000fL
+#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK                   0x000000f0L
+#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK                  0x00000f00L
+#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK                  0x0000f000L
+#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK                  0x000f0000L
+#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK                  0x00f00000L
+#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK                  0x0f000000L
+#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK                  0xf0000000L
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_VS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_PS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK           0x00000001L
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE                0x00000001L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK          0x00000002L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY               0x00000002L
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK               0x0000000cL
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK                0x0000ff00L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK              0x00010000L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF                   0x00010000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK               0x00020000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE                    0x00020000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK                 0x00040000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL                      0x00040000L
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE_MASK                        0x00000007L
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK                   0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_ON                        0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK                0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK                     0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK                 0x0007ff00L
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK                0xff000000L
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK                    0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_PIX                         0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK                    0x00000002L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX                         0x00000002L
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK                0x0000ff00L
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK                0x07ff0000L
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK            0x0000003fL
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK      0x00000040L
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY           0x00000040L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK              0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE                   0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK         0x00000100L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE              0x00000100L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK             0x00000200L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL                  0x00000200L
+#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK                  0x00001c00L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK          0x00002000L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE               0x00002000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK         0x00004000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE              0x00004000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK     0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE          0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK            0x003f0000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK             0x00400000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE                  0x00400000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK            0x00800000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE                 0x00800000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK             0x01000000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE                  0x01000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK             0x02000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE                  0x02000000L
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE_MASK             0x04000000L
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE                  0x04000000L
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK                  0x00000007L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK               0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1                    0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK                  0x00000070L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK               0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2                    0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK                 0x00000700L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3_MASK               0x00000800L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3                    0x00000800L
+#define MH_CLNT_AXI_ID_REUSE__PAw_ID_MASK                  0x00007000L
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK             0x00000001L
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR                  0x00000001L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK            0x00000002L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR                 0x00000002L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK             0x00000004L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT                  0x00000004L
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK           0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR                0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK          0x00000002L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR               0x00000002L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK           0x00000004L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT                0x00000004L
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK            0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR                 0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK           0x00000002L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR                0x00000002L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK            0x00000004L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT                 0x00000004L
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID_MASK                     0x00000007L
+#define MH_AXI_ERROR__AXI_READ_ERROR_MASK                  0x00000008L
+#define MH_AXI_ERROR__AXI_READ_ERROR                       0x00000008L
+#define MH_AXI_ERROR__AXI_WRITE_ID_MASK                    0x00000070L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK                 0x00000080L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR                      0x00000080L
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX_MASK                          0x0000003fL
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA_MASK                           0xffffffffL
+
+// MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL__AXI_HALT_MASK                 0x00000001L
+#define MH_AXI_HALT_CONTROL__AXI_HALT                      0x00000001L
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY_MASK                       0x00000001L
+#define MH_DEBUG_REG00__MH_BUSY                            0x00000001L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK             0x00000002L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING                  0x00000002L
+#define MH_DEBUG_REG00__CP_REQUEST_MASK                    0x00000004L
+#define MH_DEBUG_REG00__CP_REQUEST                         0x00000004L
+#define MH_DEBUG_REG00__VGT_REQUEST_MASK                   0x00000008L
+#define MH_DEBUG_REG00__VGT_REQUEST                        0x00000008L
+#define MH_DEBUG_REG00__TC_REQUEST_MASK                    0x00000010L
+#define MH_DEBUG_REG00__TC_REQUEST                         0x00000010L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK                  0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY                       0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_FULL_MASK                   0x00000040L
+#define MH_DEBUG_REG00__TC_CAM_FULL                        0x00000040L
+#define MH_DEBUG_REG00__TCD_EMPTY_MASK                     0x00000080L
+#define MH_DEBUG_REG00__TCD_EMPTY                          0x00000080L
+#define MH_DEBUG_REG00__TCD_FULL_MASK                      0x00000100L
+#define MH_DEBUG_REG00__TCD_FULL                           0x00000100L
+#define MH_DEBUG_REG00__RB_REQUEST_MASK                    0x00000200L
+#define MH_DEBUG_REG00__RB_REQUEST                         0x00000200L
+#define MH_DEBUG_REG00__PA_REQUEST_MASK                    0x00000400L
+#define MH_DEBUG_REG00__PA_REQUEST                         0x00000400L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK               0x00000800L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE                    0x00000800L
+#define MH_DEBUG_REG00__ARQ_EMPTY_MASK                     0x00001000L
+#define MH_DEBUG_REG00__ARQ_EMPTY                          0x00001000L
+#define MH_DEBUG_REG00__ARQ_FULL_MASK                      0x00002000L
+#define MH_DEBUG_REG00__ARQ_FULL                           0x00002000L
+#define MH_DEBUG_REG00__WDB_EMPTY_MASK                     0x00004000L
+#define MH_DEBUG_REG00__WDB_EMPTY                          0x00004000L
+#define MH_DEBUG_REG00__WDB_FULL_MASK                      0x00008000L
+#define MH_DEBUG_REG00__WDB_FULL                           0x00008000L
+#define MH_DEBUG_REG00__AXI_AVALID_MASK                    0x00010000L
+#define MH_DEBUG_REG00__AXI_AVALID                         0x00010000L
+#define MH_DEBUG_REG00__AXI_AREADY_MASK                    0x00020000L
+#define MH_DEBUG_REG00__AXI_AREADY                         0x00020000L
+#define MH_DEBUG_REG00__AXI_ARVALID_MASK                   0x00040000L
+#define MH_DEBUG_REG00__AXI_ARVALID                        0x00040000L
+#define MH_DEBUG_REG00__AXI_ARREADY_MASK                   0x00080000L
+#define MH_DEBUG_REG00__AXI_ARREADY                        0x00080000L
+#define MH_DEBUG_REG00__AXI_WVALID_MASK                    0x00100000L
+#define MH_DEBUG_REG00__AXI_WVALID                         0x00100000L
+#define MH_DEBUG_REG00__AXI_WREADY_MASK                    0x00200000L
+#define MH_DEBUG_REG00__AXI_WREADY                         0x00200000L
+#define MH_DEBUG_REG00__AXI_RVALID_MASK                    0x00400000L
+#define MH_DEBUG_REG00__AXI_RVALID                         0x00400000L
+#define MH_DEBUG_REG00__AXI_RREADY_MASK                    0x00800000L
+#define MH_DEBUG_REG00__AXI_RREADY                         0x00800000L
+#define MH_DEBUG_REG00__AXI_BVALID_MASK                    0x01000000L
+#define MH_DEBUG_REG00__AXI_BVALID                         0x01000000L
+#define MH_DEBUG_REG00__AXI_BREADY_MASK                    0x02000000L
+#define MH_DEBUG_REG00__AXI_BREADY                         0x02000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK                  0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ                       0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK                  0x08000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK                       0x08000000L
+#define MH_DEBUG_REG00__AXI_RDY_ENA_MASK                   0x10000000L
+#define MH_DEBUG_REG00__AXI_RDY_ENA                        0x10000000L
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q_MASK                     0x00000001L
+#define MH_DEBUG_REG01__CP_SEND_q                          0x00000001L
+#define MH_DEBUG_REG01__CP_RTR_q_MASK                      0x00000002L
+#define MH_DEBUG_REG01__CP_RTR_q                           0x00000002L
+#define MH_DEBUG_REG01__CP_WRITE_q_MASK                    0x00000004L
+#define MH_DEBUG_REG01__CP_WRITE_q                         0x00000004L
+#define MH_DEBUG_REG01__CP_TAG_q_MASK                      0x00000038L
+#define MH_DEBUG_REG01__CP_BLEN_q_MASK                     0x00000040L
+#define MH_DEBUG_REG01__CP_BLEN_q                          0x00000040L
+#define MH_DEBUG_REG01__VGT_SEND_q_MASK                    0x00000080L
+#define MH_DEBUG_REG01__VGT_SEND_q                         0x00000080L
+#define MH_DEBUG_REG01__VGT_RTR_q_MASK                     0x00000100L
+#define MH_DEBUG_REG01__VGT_RTR_q                          0x00000100L
+#define MH_DEBUG_REG01__VGT_TAG_q_MASK                     0x00000200L
+#define MH_DEBUG_REG01__VGT_TAG_q                          0x00000200L
+#define MH_DEBUG_REG01__TC_SEND_q_MASK                     0x00000400L
+#define MH_DEBUG_REG01__TC_SEND_q                          0x00000400L
+#define MH_DEBUG_REG01__TC_RTR_q_MASK                      0x00000800L
+#define MH_DEBUG_REG01__TC_RTR_q                           0x00000800L
+#define MH_DEBUG_REG01__TC_BLEN_q_MASK                     0x00001000L
+#define MH_DEBUG_REG01__TC_BLEN_q                          0x00001000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK                 0x00002000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q                      0x00002000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK                  0x00004000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q                       0x00004000L
+#define MH_DEBUG_REG01__TC_MH_written_MASK                 0x00008000L
+#define MH_DEBUG_REG01__TC_MH_written                      0x00008000L
+#define MH_DEBUG_REG01__RB_SEND_q_MASK                     0x00010000L
+#define MH_DEBUG_REG01__RB_SEND_q                          0x00010000L
+#define MH_DEBUG_REG01__RB_RTR_q_MASK                      0x00020000L
+#define MH_DEBUG_REG01__RB_RTR_q                           0x00020000L
+#define MH_DEBUG_REG01__PA_SEND_q_MASK                     0x00040000L
+#define MH_DEBUG_REG01__PA_SEND_q                          0x00040000L
+#define MH_DEBUG_REG01__PA_RTR_q_MASK                      0x00080000L
+#define MH_DEBUG_REG01__PA_RTR_q                           0x00080000L
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG02__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG02__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG02__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG02__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK                 0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_rlast                      0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_tag_MASK                   0x00000070L
+#define MH_DEBUG_REG02__RDC_RID_MASK                       0x00000380L
+#define MH_DEBUG_REG02__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG02__MH_CP_writeclean_MASK              0x00001000L
+#define MH_DEBUG_REG02__MH_CP_writeclean                   0x00001000L
+#define MH_DEBUG_REG02__MH_RB_writeclean_MASK              0x00002000L
+#define MH_DEBUG_REG02__MH_RB_writeclean                   0x00002000L
+#define MH_DEBUG_REG02__MH_PA_writeclean_MASK              0x00004000L
+#define MH_DEBUG_REG02__MH_PA_writeclean                   0x00004000L
+#define MH_DEBUG_REG02__BRC_BID_MASK                       0x00038000L
+#define MH_DEBUG_REG02__BRC_BRESP_MASK                     0x000c0000L
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK             0xffffffffL
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK            0xffffffffL
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG05__CP_MH_send                         0x00000001L
+#define MH_DEBUG_REG05__CP_MH_write_MASK                   0x00000002L
+#define MH_DEBUG_REG05__CP_MH_write                        0x00000002L
+#define MH_DEBUG_REG05__CP_MH_tag_MASK                     0x0000001cL
+#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK                 0xffffffe0L
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__CP_MH_be_MASK                      0x000000ffL
+#define MH_DEBUG_REG08__RB_MH_be_MASK                      0x0000ff00L
+#define MH_DEBUG_REG08__PA_MH_be_MASK                      0x00ff0000L
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK                   0x00000007L
+#define MH_DEBUG_REG09__VGT_MH_send_MASK                   0x00000008L
+#define MH_DEBUG_REG09__VGT_MH_send                        0x00000008L
+#define MH_DEBUG_REG09__VGT_MH_tagbe_MASK                  0x00000010L
+#define MH_DEBUG_REG09__VGT_MH_tagbe                       0x00000010L
+#define MH_DEBUG_REG09__VGT_MH_ad_31_5_MASK                0xffffffe0L
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG10__TC_MH_send_MASK                    0x00000004L
+#define MH_DEBUG_REG10__TC_MH_send                         0x00000004L
+#define MH_DEBUG_REG10__TC_MH_mask_MASK                    0x00000018L
+#define MH_DEBUG_REG10__TC_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__TC_MH_info_MASK                    0x01ffffffL
+#define MH_DEBUG_REG11__TC_MH_send_MASK                    0x02000000L
+#define MH_DEBUG_REG11__TC_MH_send                         0x02000000L
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__MH_TC_mcinfo_MASK                  0x01ffffffL
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send_MASK             0x02000000L
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send                  0x02000000L
+#define MH_DEBUG_REG12__TC_MH_written_MASK                 0x04000000L
+#define MH_DEBUG_REG12__TC_MH_written                      0x04000000L
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK                   0x00000004L
+#define MH_DEBUG_REG13__TC_ROQ_SEND                        0x00000004L
+#define MH_DEBUG_REG13__TC_ROQ_MASK_MASK                   0x00000018L
+#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5_MASK              0xffffffe0L
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__TC_ROQ_INFO_MASK                   0x01ffffffL
+#define MH_DEBUG_REG14__TC_ROQ_SEND_MASK                   0x02000000L
+#define MH_DEBUG_REG14__TC_ROQ_SEND                        0x02000000L
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG15__RB_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG15__RB_MH_send                         0x00000010L
+#define MH_DEBUG_REG15__RB_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__RB_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG18__PA_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG18__PA_MH_send                         0x00000010L
+#define MH_DEBUG_REG18__PA_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__PA_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__PA_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG21__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG21__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG21__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG21__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG21__ALEN_q_2_0_MASK                    0x000000e0L
+#define MH_DEBUG_REG21__ARVALID_q_MASK                     0x00000100L
+#define MH_DEBUG_REG21__ARVALID_q                          0x00000100L
+#define MH_DEBUG_REG21__ARREADY_q_MASK                     0x00000200L
+#define MH_DEBUG_REG21__ARREADY_q                          0x00000200L
+#define MH_DEBUG_REG21__ARID_q_MASK                        0x00001c00L
+#define MH_DEBUG_REG21__ARLEN_q_1_0_MASK                   0x00006000L
+#define MH_DEBUG_REG21__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG21__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG21__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG21__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG21__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG21__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG21__RID_q_MASK                         0x001c0000L
+#define MH_DEBUG_REG21__WVALID_q_MASK                      0x00200000L
+#define MH_DEBUG_REG21__WVALID_q                           0x00200000L
+#define MH_DEBUG_REG21__WREADY_q_MASK                      0x00400000L
+#define MH_DEBUG_REG21__WREADY_q                           0x00400000L
+#define MH_DEBUG_REG21__WLAST_q_MASK                       0x00800000L
+#define MH_DEBUG_REG21__WLAST_q                            0x00800000L
+#define MH_DEBUG_REG21__WID_q_MASK                         0x07000000L
+#define MH_DEBUG_REG21__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG21__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG21__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG21__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG21__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG22__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG22__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG22__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG22__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG22__ALEN_q_1_0_MASK                    0x00000060L
+#define MH_DEBUG_REG22__ARVALID_q_MASK                     0x00000080L
+#define MH_DEBUG_REG22__ARVALID_q                          0x00000080L
+#define MH_DEBUG_REG22__ARREADY_q_MASK                     0x00000100L
+#define MH_DEBUG_REG22__ARREADY_q                          0x00000100L
+#define MH_DEBUG_REG22__ARID_q_MASK                        0x00000e00L
+#define MH_DEBUG_REG22__ARLEN_q_1_1_MASK                   0x00001000L
+#define MH_DEBUG_REG22__ARLEN_q_1_1                        0x00001000L
+#define MH_DEBUG_REG22__WVALID_q_MASK                      0x00002000L
+#define MH_DEBUG_REG22__WVALID_q                           0x00002000L
+#define MH_DEBUG_REG22__WREADY_q_MASK                      0x00004000L
+#define MH_DEBUG_REG22__WREADY_q                           0x00004000L
+#define MH_DEBUG_REG22__WLAST_q_MASK                       0x00008000L
+#define MH_DEBUG_REG22__WLAST_q                            0x00008000L
+#define MH_DEBUG_REG22__WID_q_MASK                         0x00070000L
+#define MH_DEBUG_REG22__WSTRB_q_MASK                       0x07f80000L
+#define MH_DEBUG_REG22__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG22__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG22__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG22__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG22__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q                      0x00000001L
+#define MH_DEBUG_REG23__CTRL_ARC_ID_MASK                   0x0000000eL
+#define MH_DEBUG_REG23__CTRL_ARC_PAD_MASK                  0xfffffff0L
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG24__REG_A_MASK                         0x0000fffcL
+#define MH_DEBUG_REG24__REG_RE_MASK                        0x00010000L
+#define MH_DEBUG_REG24__REG_RE                             0x00010000L
+#define MH_DEBUG_REG24__REG_WE_MASK                        0x00020000L
+#define MH_DEBUG_REG24__REG_WE                             0x00020000L
+#define MH_DEBUG_REG24__BLOCK_RS_MASK                      0x00040000L
+#define MH_DEBUG_REG24__BLOCK_RS                           0x00040000L
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__REG_WD_MASK                        0xffffffffL
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__MH_RBBM_busy_MASK                  0x00000001L
+#define MH_DEBUG_REG26__MH_RBBM_busy                       0x00000001L
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int_MASK          0x00000002L
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int               0x00000002L
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int_MASK         0x00000004L
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int              0x00000004L
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int_MASK       0x00000008L
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int            0x00000008L
+#define MH_DEBUG_REG26__GAT_CLK_ENA_MASK                   0x00000010L
+#define MH_DEBUG_REG26__GAT_CLK_ENA                        0x00000010L
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override_MASK       0x00000020L
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override            0x00000020L
+#define MH_DEBUG_REG26__CNT_q_MASK                         0x00000fc0L
+#define MH_DEBUG_REG26__TCD_EMPTY_q_MASK                   0x00001000L
+#define MH_DEBUG_REG26__TCD_EMPTY_q                        0x00001000L
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY_MASK                  0x00002000L
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY                       0x00002000L
+#define MH_DEBUG_REG26__MH_BUSY_d_MASK                     0x00004000L
+#define MH_DEBUG_REG26__MH_BUSY_d                          0x00004000L
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY_MASK                 0x00008000L
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY                      0x00008000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL   0x00010000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC    0x00020000L
+#define MH_DEBUG_REG26__CP_SEND_q_MASK                     0x00040000L
+#define MH_DEBUG_REG26__CP_SEND_q                          0x00040000L
+#define MH_DEBUG_REG26__CP_RTR_q_MASK                      0x00080000L
+#define MH_DEBUG_REG26__CP_RTR_q                           0x00080000L
+#define MH_DEBUG_REG26__VGT_SEND_q_MASK                    0x00100000L
+#define MH_DEBUG_REG26__VGT_SEND_q                         0x00100000L
+#define MH_DEBUG_REG26__VGT_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG26__VGT_RTR_q                          0x00200000L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK                 0x00400000L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q                      0x00400000L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK              0x00800000L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q                   0x00800000L
+#define MH_DEBUG_REG26__RB_SEND_q_MASK                     0x01000000L
+#define MH_DEBUG_REG26__RB_SEND_q                          0x01000000L
+#define MH_DEBUG_REG26__RB_RTR_q_MASK                      0x02000000L
+#define MH_DEBUG_REG26__RB_RTR_q                           0x02000000L
+#define MH_DEBUG_REG26__PA_SEND_q_MASK                     0x04000000L
+#define MH_DEBUG_REG26__PA_SEND_q                          0x04000000L
+#define MH_DEBUG_REG26__PA_RTR_q_MASK                      0x08000000L
+#define MH_DEBUG_REG26__PA_RTR_q                           0x08000000L
+#define MH_DEBUG_REG26__RDC_VALID_MASK                     0x10000000L
+#define MH_DEBUG_REG26__RDC_VALID                          0x10000000L
+#define MH_DEBUG_REG26__RDC_RLAST_MASK                     0x20000000L
+#define MH_DEBUG_REG26__RDC_RLAST                          0x20000000L
+#define MH_DEBUG_REG26__TLBMISS_VALID_MASK                 0x40000000L
+#define MH_DEBUG_REG26__TLBMISS_VALID                      0x40000000L
+#define MH_DEBUG_REG26__BRC_VALID_MASK                     0x80000000L
+#define MH_DEBUG_REG26__BRC_VALID                          0x80000000L
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__EFF2_FP_WINNER_MASK                0x00000007L
+#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out_MASK           0x00000038L
+#define MH_DEBUG_REG27__EFF1_WINNER_MASK                   0x000001c0L
+#define MH_DEBUG_REG27__ARB_WINNER_MASK                    0x00000e00L
+#define MH_DEBUG_REG27__ARB_WINNER_q_MASK                  0x00007000L
+#define MH_DEBUG_REG27__EFF1_WIN_MASK                      0x00008000L
+#define MH_DEBUG_REG27__EFF1_WIN                           0x00008000L
+#define MH_DEBUG_REG27__KILL_EFF1_MASK                     0x00010000L
+#define MH_DEBUG_REG27__KILL_EFF1                          0x00010000L
+#define MH_DEBUG_REG27__ARB_HOLD_MASK                      0x00020000L
+#define MH_DEBUG_REG27__ARB_HOLD                           0x00020000L
+#define MH_DEBUG_REG27__ARB_RTR_q_MASK                     0x00040000L
+#define MH_DEBUG_REG27__ARB_RTR_q                          0x00040000L
+#define MH_DEBUG_REG27__CP_SEND_QUAL_MASK                  0x00080000L
+#define MH_DEBUG_REG27__CP_SEND_QUAL                       0x00080000L
+#define MH_DEBUG_REG27__VGT_SEND_QUAL_MASK                 0x00100000L
+#define MH_DEBUG_REG27__VGT_SEND_QUAL                      0x00100000L
+#define MH_DEBUG_REG27__TC_SEND_QUAL_MASK                  0x00200000L
+#define MH_DEBUG_REG27__TC_SEND_QUAL                       0x00200000L
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL_MASK             0x00400000L
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL                  0x00400000L
+#define MH_DEBUG_REG27__RB_SEND_QUAL_MASK                  0x00800000L
+#define MH_DEBUG_REG27__RB_SEND_QUAL                       0x00800000L
+#define MH_DEBUG_REG27__PA_SEND_QUAL_MASK                  0x01000000L
+#define MH_DEBUG_REG27__PA_SEND_QUAL                       0x01000000L
+#define MH_DEBUG_REG27__ARB_QUAL_MASK                      0x02000000L
+#define MH_DEBUG_REG27__ARB_QUAL                           0x02000000L
+#define MH_DEBUG_REG27__CP_EFF1_REQ_MASK                   0x04000000L
+#define MH_DEBUG_REG27__CP_EFF1_REQ                        0x04000000L
+#define MH_DEBUG_REG27__VGT_EFF1_REQ_MASK                  0x08000000L
+#define MH_DEBUG_REG27__VGT_EFF1_REQ                       0x08000000L
+#define MH_DEBUG_REG27__TC_EFF1_REQ_MASK                   0x10000000L
+#define MH_DEBUG_REG27__TC_EFF1_REQ                        0x10000000L
+#define MH_DEBUG_REG27__RB_EFF1_REQ_MASK                   0x20000000L
+#define MH_DEBUG_REG27__RB_EFF1_REQ                        0x20000000L
+#define MH_DEBUG_REG27__TCD_NEARFULL_q_MASK                0x40000000L
+#define MH_DEBUG_REG27__TCD_NEARFULL_q                     0x40000000L
+#define MH_DEBUG_REG27__TCHOLD_IP_q_MASK                   0x80000000L
+#define MH_DEBUG_REG27__TCHOLD_IP_q                        0x80000000L
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__EFF1_WINNER_MASK                   0x00000007L
+#define MH_DEBUG_REG28__ARB_WINNER_MASK                    0x00000038L
+#define MH_DEBUG_REG28__CP_SEND_QUAL_MASK                  0x00000040L
+#define MH_DEBUG_REG28__CP_SEND_QUAL                       0x00000040L
+#define MH_DEBUG_REG28__VGT_SEND_QUAL_MASK                 0x00000080L
+#define MH_DEBUG_REG28__VGT_SEND_QUAL                      0x00000080L
+#define MH_DEBUG_REG28__TC_SEND_QUAL_MASK                  0x00000100L
+#define MH_DEBUG_REG28__TC_SEND_QUAL                       0x00000100L
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL_MASK             0x00000200L
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL                  0x00000200L
+#define MH_DEBUG_REG28__RB_SEND_QUAL_MASK                  0x00000400L
+#define MH_DEBUG_REG28__RB_SEND_QUAL                       0x00000400L
+#define MH_DEBUG_REG28__ARB_QUAL_MASK                      0x00000800L
+#define MH_DEBUG_REG28__ARB_QUAL                           0x00000800L
+#define MH_DEBUG_REG28__CP_EFF1_REQ_MASK                   0x00001000L
+#define MH_DEBUG_REG28__CP_EFF1_REQ                        0x00001000L
+#define MH_DEBUG_REG28__VGT_EFF1_REQ_MASK                  0x00002000L
+#define MH_DEBUG_REG28__VGT_EFF1_REQ                       0x00002000L
+#define MH_DEBUG_REG28__TC_EFF1_REQ_MASK                   0x00004000L
+#define MH_DEBUG_REG28__TC_EFF1_REQ                        0x00004000L
+#define MH_DEBUG_REG28__RB_EFF1_REQ_MASK                   0x00008000L
+#define MH_DEBUG_REG28__RB_EFF1_REQ                        0x00008000L
+#define MH_DEBUG_REG28__EFF1_WIN_MASK                      0x00010000L
+#define MH_DEBUG_REG28__EFF1_WIN                           0x00010000L
+#define MH_DEBUG_REG28__KILL_EFF1_MASK                     0x00020000L
+#define MH_DEBUG_REG28__KILL_EFF1                          0x00020000L
+#define MH_DEBUG_REG28__TCD_NEARFULL_q_MASK                0x00040000L
+#define MH_DEBUG_REG28__TCD_NEARFULL_q                     0x00040000L
+#define MH_DEBUG_REG28__TC_ARB_HOLD_MASK                   0x00080000L
+#define MH_DEBUG_REG28__TC_ARB_HOLD                        0x00080000L
+#define MH_DEBUG_REG28__ARB_HOLD_MASK                      0x00100000L
+#define MH_DEBUG_REG28__ARB_HOLD                           0x00100000L
+#define MH_DEBUG_REG28__ARB_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG28__ARB_RTR_q                          0x00200000L
+#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q_MASK       0xffc00000L
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out_MASK           0x00000007L
+#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d_MASK          0x00000038L
+#define MH_DEBUG_REG29__LEAST_RECENT_d_MASK                0x000001c0L
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d_MASK         0x00000200L
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d              0x00000200L
+#define MH_DEBUG_REG29__ARB_HOLD_MASK                      0x00000400L
+#define MH_DEBUG_REG29__ARB_HOLD                           0x00000400L
+#define MH_DEBUG_REG29__ARB_RTR_q_MASK                     0x00000800L
+#define MH_DEBUG_REG29__ARB_RTR_q                          0x00000800L
+#define MH_DEBUG_REG29__CLNT_REQ_MASK                      0x0001f000L
+#define MH_DEBUG_REG29__RECENT_d_0_MASK                    0x000e0000L
+#define MH_DEBUG_REG29__RECENT_d_1_MASK                    0x00700000L
+#define MH_DEBUG_REG29__RECENT_d_2_MASK                    0x03800000L
+#define MH_DEBUG_REG29__RECENT_d_3_MASK                    0x1c000000L
+#define MH_DEBUG_REG29__RECENT_d_4_MASK                    0xe0000000L
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__TC_ARB_HOLD_MASK                   0x00000001L
+#define MH_DEBUG_REG30__TC_ARB_HOLD                        0x00000001L
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK_MASK        0x00000002L
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK             0x00000002L
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK_MASK          0x00000004L
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK               0x00000004L
+#define MH_DEBUG_REG30__TCD_NEARFULL_q_MASK                0x00000008L
+#define MH_DEBUG_REG30__TCD_NEARFULL_q                     0x00000008L
+#define MH_DEBUG_REG30__TCHOLD_IP_q_MASK                   0x00000010L
+#define MH_DEBUG_REG30__TCHOLD_IP_q                        0x00000010L
+#define MH_DEBUG_REG30__TCHOLD_CNT_q_MASK                  0x000000e0L
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q_MASK              0x00000200L
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q                   0x00000200L
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q_MASK                 0x00000400L
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q                      0x00000400L
+#define MH_DEBUG_REG30__TC_MH_written_MASK                 0x00000800L
+#define MH_DEBUG_REG30__TC_MH_written                      0x00000800L
+#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q_MASK            0x0007f000L
+#define MH_DEBUG_REG30__WBURST_ACTIVE_MASK                 0x00080000L
+#define MH_DEBUG_REG30__WBURST_ACTIVE                      0x00080000L
+#define MH_DEBUG_REG30__WLAST_q_MASK                       0x00100000L
+#define MH_DEBUG_REG30__WLAST_q                            0x00100000L
+#define MH_DEBUG_REG30__WBURST_IP_q_MASK                   0x00200000L
+#define MH_DEBUG_REG30__WBURST_IP_q                        0x00200000L
+#define MH_DEBUG_REG30__WBURST_CNT_q_MASK                  0x01c00000L
+#define MH_DEBUG_REG30__CP_SEND_QUAL_MASK                  0x02000000L
+#define MH_DEBUG_REG30__CP_SEND_QUAL                       0x02000000L
+#define MH_DEBUG_REG30__CP_MH_write_MASK                   0x04000000L
+#define MH_DEBUG_REG30__CP_MH_write                        0x04000000L
+#define MH_DEBUG_REG30__RB_SEND_QUAL_MASK                  0x08000000L
+#define MH_DEBUG_REG30__RB_SEND_QUAL                       0x08000000L
+#define MH_DEBUG_REG30__PA_SEND_QUAL_MASK                  0x10000000L
+#define MH_DEBUG_REG30__PA_SEND_QUAL                       0x10000000L
+#define MH_DEBUG_REG30__ARB_WINNER_MASK                    0xe0000000L
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q_MASK           0x03ffffffL
+#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0x1c000000L
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG32__ROQ_MARK_q_MASK                    0x0000ff00L
+#define MH_DEBUG_REG32__ROQ_VALID_q_MASK                   0x00ff0000L
+#define MH_DEBUG_REG32__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG32__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG32__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG32__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG32__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG32__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG32__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG32__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG33__ROQ_MARK_d_MASK                    0x0000ff00L
+#define MH_DEBUG_REG33__ROQ_VALID_d_MASK                   0x00ff0000L
+#define MH_DEBUG_REG33__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG33__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG33__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG33__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG33__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG33__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG33__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG33__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN_MASK             0x000000ffL
+#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ_MASK             0x0000ff00L
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN_MASK         0x00ff0000L
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ_MASK         0xff000000L
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG35__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG35__ROQ_MARK_q_0_MASK                  0x00000004L
+#define MH_DEBUG_REG35__ROQ_MARK_q_0                       0x00000004L
+#define MH_DEBUG_REG35__ROQ_VALID_q_0_MASK                 0x00000008L
+#define MH_DEBUG_REG35__ROQ_VALID_q_0                      0x00000008L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0_MASK             0x00000010L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0                  0x00000010L
+#define MH_DEBUG_REG35__ROQ_ADDR_0_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG36__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG36__ROQ_MARK_q_1_MASK                  0x00000004L
+#define MH_DEBUG_REG36__ROQ_MARK_q_1                       0x00000004L
+#define MH_DEBUG_REG36__ROQ_VALID_q_1_MASK                 0x00000008L
+#define MH_DEBUG_REG36__ROQ_VALID_q_1                      0x00000008L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1_MASK             0x00000010L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1                  0x00000010L
+#define MH_DEBUG_REG36__ROQ_ADDR_1_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG37__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG37__ROQ_MARK_q_2_MASK                  0x00000004L
+#define MH_DEBUG_REG37__ROQ_MARK_q_2                       0x00000004L
+#define MH_DEBUG_REG37__ROQ_VALID_q_2_MASK                 0x00000008L
+#define MH_DEBUG_REG37__ROQ_VALID_q_2                      0x00000008L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2_MASK             0x00000010L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2                  0x00000010L
+#define MH_DEBUG_REG37__ROQ_ADDR_2_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG38__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG38__ROQ_MARK_q_3_MASK                  0x00000004L
+#define MH_DEBUG_REG38__ROQ_MARK_q_3                       0x00000004L
+#define MH_DEBUG_REG38__ROQ_VALID_q_3_MASK                 0x00000008L
+#define MH_DEBUG_REG38__ROQ_VALID_q_3                      0x00000008L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3_MASK             0x00000010L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3                  0x00000010L
+#define MH_DEBUG_REG38__ROQ_ADDR_3_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG39__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG39__ROQ_MARK_q_4_MASK                  0x00000004L
+#define MH_DEBUG_REG39__ROQ_MARK_q_4                       0x00000004L
+#define MH_DEBUG_REG39__ROQ_VALID_q_4_MASK                 0x00000008L
+#define MH_DEBUG_REG39__ROQ_VALID_q_4                      0x00000008L
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4_MASK             0x00000010L
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4                  0x00000010L
+#define MH_DEBUG_REG39__ROQ_ADDR_4_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG40__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG40__ROQ_MARK_q_5_MASK                  0x00000004L
+#define MH_DEBUG_REG40__ROQ_MARK_q_5                       0x00000004L
+#define MH_DEBUG_REG40__ROQ_VALID_q_5_MASK                 0x00000008L
+#define MH_DEBUG_REG40__ROQ_VALID_q_5                      0x00000008L
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5_MASK             0x00000010L
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5                  0x00000010L
+#define MH_DEBUG_REG40__ROQ_ADDR_5_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG41__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG41__ROQ_MARK_q_6_MASK                  0x00000004L
+#define MH_DEBUG_REG41__ROQ_MARK_q_6                       0x00000004L
+#define MH_DEBUG_REG41__ROQ_VALID_q_6_MASK                 0x00000008L
+#define MH_DEBUG_REG41__ROQ_VALID_q_6                      0x00000008L
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6_MASK             0x00000010L
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6                  0x00000010L
+#define MH_DEBUG_REG41__ROQ_ADDR_6_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG42__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG42__ROQ_MARK_q_7_MASK                  0x00000004L
+#define MH_DEBUG_REG42__ROQ_MARK_q_7                       0x00000004L
+#define MH_DEBUG_REG42__ROQ_VALID_q_7_MASK                 0x00000008L
+#define MH_DEBUG_REG42__ROQ_VALID_q_7                      0x00000008L
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7_MASK             0x00000010L
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7                  0x00000010L
+#define MH_DEBUG_REG42__ROQ_ADDR_7_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_REG_WE_q_MASK                  0x00000001L
+#define MH_DEBUG_REG43__ARB_REG_WE_q                       0x00000001L
+#define MH_DEBUG_REG43__ARB_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG43__ARB_WE                             0x00000002L
+#define MH_DEBUG_REG43__ARB_REG_VALID_q_MASK               0x00000004L
+#define MH_DEBUG_REG43__ARB_REG_VALID_q                    0x00000004L
+#define MH_DEBUG_REG43__ARB_RTR_q_MASK                     0x00000008L
+#define MH_DEBUG_REG43__ARB_RTR_q                          0x00000008L
+#define MH_DEBUG_REG43__ARB_REG_RTR_MASK                   0x00000010L
+#define MH_DEBUG_REG43__ARB_REG_RTR                        0x00000010L
+#define MH_DEBUG_REG43__WDAT_BURST_RTR_MASK                0x00000020L
+#define MH_DEBUG_REG43__WDAT_BURST_RTR                     0x00000020L
+#define MH_DEBUG_REG43__MMU_RTR_MASK                       0x00000040L
+#define MH_DEBUG_REG43__MMU_RTR                            0x00000040L
+#define MH_DEBUG_REG43__ARB_ID_q_MASK                      0x00000380L
+#define MH_DEBUG_REG43__ARB_WRITE_q_MASK                   0x00000400L
+#define MH_DEBUG_REG43__ARB_WRITE_q                        0x00000400L
+#define MH_DEBUG_REG43__ARB_BLEN_q_MASK                    0x00000800L
+#define MH_DEBUG_REG43__ARB_BLEN_q                         0x00000800L
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY_MASK                0x00001000L
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY                     0x00001000L
+#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q_MASK                0x0000e000L
+#define MH_DEBUG_REG43__MMU_WE_MASK                        0x00010000L
+#define MH_DEBUG_REG43__MMU_WE                             0x00010000L
+#define MH_DEBUG_REG43__ARQ_RTR_MASK                       0x00020000L
+#define MH_DEBUG_REG43__ARQ_RTR                            0x00020000L
+#define MH_DEBUG_REG43__MMU_ID_MASK                        0x001c0000L
+#define MH_DEBUG_REG43__MMU_WRITE_MASK                     0x00200000L
+#define MH_DEBUG_REG43__MMU_WRITE                          0x00200000L
+#define MH_DEBUG_REG43__MMU_BLEN_MASK                      0x00400000L
+#define MH_DEBUG_REG43__MMU_BLEN                           0x00400000L
+#define MH_DEBUG_REG43__WBURST_IP_q_MASK                   0x00800000L
+#define MH_DEBUG_REG43__WBURST_IP_q                        0x00800000L
+#define MH_DEBUG_REG43__WDAT_REG_WE_q_MASK                 0x01000000L
+#define MH_DEBUG_REG43__WDAT_REG_WE_q                      0x01000000L
+#define MH_DEBUG_REG43__WDB_WE_MASK                        0x02000000L
+#define MH_DEBUG_REG43__WDB_WE                             0x02000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4_MASK                0x04000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4                     0x04000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3_MASK                0x08000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3                     0x08000000L
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG44__ARB_WE                             0x00000001L
+#define MH_DEBUG_REG44__ARB_ID_q_MASK                      0x0000000eL
+#define MH_DEBUG_REG44__ARB_VAD_q_MASK                     0xfffffff0L
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__MMU_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG45__MMU_WE                             0x00000001L
+#define MH_DEBUG_REG45__MMU_ID_MASK                        0x0000000eL
+#define MH_DEBUG_REG45__MMU_PAD_MASK                       0xfffffff0L
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDAT_REG_WE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG46__WDAT_REG_WE_q                      0x00000001L
+#define MH_DEBUG_REG46__WDB_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG46__WDB_WE                             0x00000002L
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q_MASK              0x00000004L
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q                   0x00000004L
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4_MASK                0x00000008L
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4                     0x00000008L
+#define MH_DEBUG_REG46__ARB_WSTRB_q_MASK                   0x00000ff0L
+#define MH_DEBUG_REG46__ARB_WLAST_MASK                     0x00001000L
+#define MH_DEBUG_REG46__ARB_WLAST                          0x00001000L
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY_MASK                0x00002000L
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY                     0x00002000L
+#define MH_DEBUG_REG46__WDB_FIFO_CNT_q_MASK                0x0007c000L
+#define MH_DEBUG_REG46__WDC_WDB_RE_q_MASK                  0x00080000L
+#define MH_DEBUG_REG46__WDC_WDB_RE_q                       0x00080000L
+#define MH_DEBUG_REG46__WDB_WDC_WID_MASK                   0x00700000L
+#define MH_DEBUG_REG46__WDB_WDC_WLAST_MASK                 0x00800000L
+#define MH_DEBUG_REG46__WDB_WDC_WLAST                      0x00800000L
+#define MH_DEBUG_REG46__WDB_WDC_WSTRB_MASK                 0xff000000L
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0_MASK            0xffffffffL
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32_MASK           0xffffffffL
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY_MASK                0x00000001L
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY                     0x00000001L
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY_MASK               0x00000002L
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY                    0x00000002L
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY_MASK                0x00000004L
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY                     0x00000004L
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE_MASK                0x00000008L
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE                     0x00000008L
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS_MASK              0x00000010L
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS                   0x00000010L
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q_MASK             0x00000020L
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q                  0x00000020L
+#define MH_DEBUG_REG49__INFLT_LIMIT_q_MASK                 0x00000040L
+#define MH_DEBUG_REG49__INFLT_LIMIT_q                      0x00000040L
+#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q_MASK             0x00001f80L
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q_MASK                 0x00002000L
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q                      0x00002000L
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q_MASK                0x00004000L
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q                     0x00004000L
+#define MH_DEBUG_REG49__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG49__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG49__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG49__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG49__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG49__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG49__BVALID_q_MASK                      0x00040000L
+#define MH_DEBUG_REG49__BVALID_q                           0x00040000L
+#define MH_DEBUG_REG49__BREADY_q_MASK                      0x00080000L
+#define MH_DEBUG_REG49__BREADY_q                           0x00080000L
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG50__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG50__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG50__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG50__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG50__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND_MASK               0x00000008L
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND                    0x00000008L
+#define MH_DEBUG_REG50__TLBMISS_VALID_MASK                 0x00000010L
+#define MH_DEBUG_REG50__TLBMISS_VALID                      0x00000010L
+#define MH_DEBUG_REG50__RDC_VALID_MASK                     0x00000020L
+#define MH_DEBUG_REG50__RDC_VALID                          0x00000020L
+#define MH_DEBUG_REG50__RDC_RID_MASK                       0x000001c0L
+#define MH_DEBUG_REG50__RDC_RLAST_MASK                     0x00000200L
+#define MH_DEBUG_REG50__RDC_RLAST                          0x00000200L
+#define MH_DEBUG_REG50__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS_MASK              0x00001000L
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS                   0x00001000L
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q_MASK             0x00002000L
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q                  0x00002000L
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q_MASK              0x00004000L
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q                   0x00004000L
+#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q_MASK       0x001f8000L
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE_MASK               0x00200000L
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE                    0x00200000L
+#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q_MASK          0x0fc00000L
+#define MH_DEBUG_REG50__CNT_HOLD_q1_MASK                   0x10000000L
+#define MH_DEBUG_REG50__CNT_HOLD_q1                        0x10000000L
+#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0xe0000000L
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT_MASK             0xffffffffL
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0_MASK        0x00000003L
+#define MH_DEBUG_REG52__ARB_WE_MASK                        0x00000004L
+#define MH_DEBUG_REG52__ARB_WE                             0x00000004L
+#define MH_DEBUG_REG52__MMU_RTR_MASK                       0x00000008L
+#define MH_DEBUG_REG52__MMU_RTR                            0x00000008L
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4_MASK       0x03fffff0L
+#define MH_DEBUG_REG52__ARB_ID_q_MASK                      0x1c000000L
+#define MH_DEBUG_REG52__ARB_WRITE_q_MASK                   0x20000000L
+#define MH_DEBUG_REG52__ARB_WRITE_q                        0x20000000L
+#define MH_DEBUG_REG52__client_behavior_q_MASK             0xc0000000L
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__stage1_valid_MASK                  0x00000001L
+#define MH_DEBUG_REG53__stage1_valid                       0x00000001L
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q_MASK             0x00000002L
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q                  0x00000002L
+#define MH_DEBUG_REG53__pa_in_mpu_range_MASK               0x00000004L
+#define MH_DEBUG_REG53__pa_in_mpu_range                    0x00000004L
+#define MH_DEBUG_REG53__tag_match_q_MASK                   0x00000008L
+#define MH_DEBUG_REG53__tag_match_q                        0x00000008L
+#define MH_DEBUG_REG53__tag_miss_q_MASK                    0x00000010L
+#define MH_DEBUG_REG53__tag_miss_q                         0x00000010L
+#define MH_DEBUG_REG53__va_in_range_q_MASK                 0x00000020L
+#define MH_DEBUG_REG53__va_in_range_q                      0x00000020L
+#define MH_DEBUG_REG53__MMU_MISS_MASK                      0x00000040L
+#define MH_DEBUG_REG53__MMU_MISS                           0x00000040L
+#define MH_DEBUG_REG53__MMU_READ_MISS_MASK                 0x00000080L
+#define MH_DEBUG_REG53__MMU_READ_MISS                      0x00000080L
+#define MH_DEBUG_REG53__MMU_WRITE_MISS_MASK                0x00000100L
+#define MH_DEBUG_REG53__MMU_WRITE_MISS                     0x00000100L
+#define MH_DEBUG_REG53__MMU_HIT_MASK                       0x00000200L
+#define MH_DEBUG_REG53__MMU_HIT                            0x00000200L
+#define MH_DEBUG_REG53__MMU_READ_HIT_MASK                  0x00000400L
+#define MH_DEBUG_REG53__MMU_READ_HIT                       0x00000400L
+#define MH_DEBUG_REG53__MMU_WRITE_HIT_MASK                 0x00000800L
+#define MH_DEBUG_REG53__MMU_WRITE_HIT                      0x00000800L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS_MASK        0x00001000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS             0x00001000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT_MASK         0x00002000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT              0x00002000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS_MASK     0x00004000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS          0x00004000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT_MASK      0x00008000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT           0x00008000L
+#define MH_DEBUG_REG53__REQ_VA_OFFSET_q_MASK               0xffff0000L
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__ARQ_RTR_MASK                       0x00000001L
+#define MH_DEBUG_REG54__ARQ_RTR                            0x00000001L
+#define MH_DEBUG_REG54__MMU_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG54__MMU_WE                             0x00000002L
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q_MASK             0x00000004L
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q                  0x00000004L
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS_MASK              0x00000008L
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS                   0x00000008L
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND_MASK               0x00000010L
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND                    0x00000010L
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH  0x00000020L
+#define MH_DEBUG_REG54__pa_in_mpu_range_MASK               0x00000040L
+#define MH_DEBUG_REG54__pa_in_mpu_range                    0x00000040L
+#define MH_DEBUG_REG54__stage1_valid_MASK                  0x00000080L
+#define MH_DEBUG_REG54__stage1_valid                       0x00000080L
+#define MH_DEBUG_REG54__stage2_valid_MASK                  0x00000100L
+#define MH_DEBUG_REG54__stage2_valid                       0x00000100L
+#define MH_DEBUG_REG54__client_behavior_q_MASK             0x00000600L
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q_MASK             0x00000800L
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q                  0x00000800L
+#define MH_DEBUG_REG54__tag_match_q_MASK                   0x00001000L
+#define MH_DEBUG_REG54__tag_match_q                        0x00001000L
+#define MH_DEBUG_REG54__tag_miss_q_MASK                    0x00002000L
+#define MH_DEBUG_REG54__tag_miss_q                         0x00002000L
+#define MH_DEBUG_REG54__va_in_range_q_MASK                 0x00004000L
+#define MH_DEBUG_REG54__va_in_range_q                      0x00004000L
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q_MASK          0x00008000L
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q               0x00008000L
+#define MH_DEBUG_REG54__TAG_valid_q_MASK                   0xffff0000L
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG0_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG55__TAG_valid_q_0_MASK                 0x00002000L
+#define MH_DEBUG_REG55__TAG_valid_q_0                      0x00002000L
+#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG55__TAG1_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG55__TAG_valid_q_1_MASK                 0x20000000L
+#define MH_DEBUG_REG55__TAG_valid_q_1                      0x20000000L
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG2_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG56__TAG_valid_q_2_MASK                 0x00002000L
+#define MH_DEBUG_REG56__TAG_valid_q_2                      0x00002000L
+#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG56__TAG3_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG56__TAG_valid_q_3_MASK                 0x20000000L
+#define MH_DEBUG_REG56__TAG_valid_q_3                      0x20000000L
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG4_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG57__TAG_valid_q_4_MASK                 0x00002000L
+#define MH_DEBUG_REG57__TAG_valid_q_4                      0x00002000L
+#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG57__TAG5_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG57__TAG_valid_q_5_MASK                 0x20000000L
+#define MH_DEBUG_REG57__TAG_valid_q_5                      0x20000000L
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG6_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG58__TAG_valid_q_6_MASK                 0x00002000L
+#define MH_DEBUG_REG58__TAG_valid_q_6                      0x00002000L
+#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG58__TAG7_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG58__TAG_valid_q_7_MASK                 0x20000000L
+#define MH_DEBUG_REG58__TAG_valid_q_7                      0x20000000L
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG8_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG59__TAG_valid_q_8_MASK                 0x00002000L
+#define MH_DEBUG_REG59__TAG_valid_q_8                      0x00002000L
+#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG59__TAG9_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG59__TAG_valid_q_9_MASK                 0x20000000L
+#define MH_DEBUG_REG59__TAG_valid_q_9                      0x20000000L
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG10_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG60__TAG_valid_q_10_MASK                0x00002000L
+#define MH_DEBUG_REG60__TAG_valid_q_10                     0x00002000L
+#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG60__TAG11_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG60__TAG_valid_q_11_MASK                0x20000000L
+#define MH_DEBUG_REG60__TAG_valid_q_11                     0x20000000L
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__TAG12_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG61__TAG_valid_q_12_MASK                0x00002000L
+#define MH_DEBUG_REG61__TAG_valid_q_12                     0x00002000L
+#define MH_DEBUG_REG61__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG61__TAG13_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG61__TAG_valid_q_13_MASK                0x20000000L
+#define MH_DEBUG_REG61__TAG_valid_q_13                     0x20000000L
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__TAG14_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG62__TAG_valid_q_14_MASK                0x00002000L
+#define MH_DEBUG_REG62__TAG_valid_q_14                     0x00002000L
+#define MH_DEBUG_REG62__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG62__TAG15_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG62__TAG_valid_q_15_MASK                0x20000000L
+#define MH_DEBUG_REG62__TAG_valid_q_15                     0x20000000L
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE_MASK                     0x00000001L
+#define MH_MMU_CONFIG__MMU_ENABLE                          0x00000001L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK              0x00000002L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE                   0x00000002L
+#define MH_MMU_CONFIG__RESERVED1_MASK                      0x0000000cL
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK             0x00000030L
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK             0x000000c0L
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK            0x00000300L
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK            0x00000c00L
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK            0x00003000L
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK            0x0000c000L
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK            0x00030000L
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK           0x000c0000L
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK           0x00300000L
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK             0x00c00000L
+#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR_MASK             0x03000000L
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK             0x00000fffL
+#define MH_MMU_VA_RANGE__VA_BASE_MASK                      0xfffff000L
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE_MASK                       0xfffff000L
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK                 0x00000001L
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT                      0x00000001L
+#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK                    0x00000002L
+#define MH_MMU_PAGE_FAULT__OP_TYPE                         0x00000002L
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK              0x0000000cL
+#define MH_MMU_PAGE_FAULT__AXI_ID_MASK                     0x00000070L
+#define MH_MMU_PAGE_FAULT__RESERVED1_MASK                  0x00000080L
+#define MH_MMU_PAGE_FAULT__RESERVED1                       0x00000080L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK   0x00000100L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE        0x00000100L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK       0x00000200L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE            0x00000200L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK      0x00000400L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR           0x00000400L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK     0x00000800L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR          0x00000800L
+#define MH_MMU_PAGE_FAULT__REQ_VA_MASK                     0xfffff000L
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK                 0xffffffe0L
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK             0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL                  0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK              0x00000002L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC                   0x00000002L
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE_MASK                     0xfffff000L
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END_MASK                       0xfffff000L
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK                     0x00000002L
+#define WAIT_UNTIL__WAIT_RE_VSYNC                          0x00000002L
+#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK                     0x00000004L
+#define WAIT_UNTIL__WAIT_FE_VSYNC                          0x00000004L
+#define WAIT_UNTIL__WAIT_VSYNC_MASK                        0x00000008L
+#define WAIT_UNTIL__WAIT_VSYNC                             0x00000008L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK                    0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0                         0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK                    0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1                         0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK                    0x00000040L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2                         0x00000040L
+#define WAIT_UNTIL__WAIT_CMDFIFO_MASK                      0x00000400L
+#define WAIT_UNTIL__WAIT_CMDFIFO                           0x00000400L
+#define WAIT_UNTIL__WAIT_2D_IDLE_MASK                      0x00004000L
+#define WAIT_UNTIL__WAIT_2D_IDLE                           0x00004000L
+#define WAIT_UNTIL__WAIT_3D_IDLE_MASK                      0x00008000L
+#define WAIT_UNTIL__WAIT_3D_IDLE                           0x00008000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK                 0x00010000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN                      0x00010000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK                 0x00020000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN                      0x00020000L
+#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK                   0x00f00000L
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK           0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI                0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK      0x00000020L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI           0x00000020L
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL_MASK                    0x0000001fL
+#define RBBM_STATUS__TC_BUSY_MASK                          0x00000020L
+#define RBBM_STATUS__TC_BUSY                               0x00000020L
+#define RBBM_STATUS__HIRQ_PENDING_MASK                     0x00000100L
+#define RBBM_STATUS__HIRQ_PENDING                          0x00000100L
+#define RBBM_STATUS__CPRQ_PENDING_MASK                     0x00000200L
+#define RBBM_STATUS__CPRQ_PENDING                          0x00000200L
+#define RBBM_STATUS__CFRQ_PENDING_MASK                     0x00000400L
+#define RBBM_STATUS__CFRQ_PENDING                          0x00000400L
+#define RBBM_STATUS__PFRQ_PENDING_MASK                     0x00000800L
+#define RBBM_STATUS__PFRQ_PENDING                          0x00000800L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK                  0x00001000L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA                       0x00001000L
+#define RBBM_STATUS__RBBM_WU_BUSY_MASK                     0x00004000L
+#define RBBM_STATUS__RBBM_WU_BUSY                          0x00004000L
+#define RBBM_STATUS__CP_NRT_BUSY_MASK                      0x00010000L
+#define RBBM_STATUS__CP_NRT_BUSY                           0x00010000L
+#define RBBM_STATUS__MH_BUSY_MASK                          0x00040000L
+#define RBBM_STATUS__MH_BUSY                               0x00040000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK                0x00080000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY                     0x00080000L
+#define RBBM_STATUS__SX_BUSY_MASK                          0x00200000L
+#define RBBM_STATUS__SX_BUSY                               0x00200000L
+#define RBBM_STATUS__TPC_BUSY_MASK                         0x00400000L
+#define RBBM_STATUS__TPC_BUSY                              0x00400000L
+#define RBBM_STATUS__SC_CNTX_BUSY_MASK                     0x01000000L
+#define RBBM_STATUS__SC_CNTX_BUSY                          0x01000000L
+#define RBBM_STATUS__PA_BUSY_MASK                          0x02000000L
+#define RBBM_STATUS__PA_BUSY                               0x02000000L
+#define RBBM_STATUS__VGT_BUSY_MASK                         0x04000000L
+#define RBBM_STATUS__VGT_BUSY                              0x04000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK                   0x08000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY                        0x08000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK                    0x10000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY                         0x10000000L
+#define RBBM_STATUS__RB_CNTX_BUSY_MASK                     0x40000000L
+#define RBBM_STATUS__RB_CNTX_BUSY                          0x40000000L
+#define RBBM_STATUS__GUI_ACTIVE_MASK                       0x80000000L
+#define RBBM_STATUS__GUI_ACTIVE                            0x80000000L
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0_MASK             0x00000001L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0                  0x00000001L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1_MASK             0x00000002L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1                  0x00000002L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2_MASK             0x00000004L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2                  0x00000004L
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID_MASK               0x00000008L
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID                    0x00000008L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0_MASK                0x00000010L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0                     0x00000010L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1_MASK                0x00000020L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1                     0x00000020L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2_MASK                0x00000040L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2                     0x00000040L
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL_MASK                   0x00000080L
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL                        0x00000080L
+#define RBBM_DSPLY__DMI_CH1_NUM_BUFS_MASK                  0x00000300L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0_MASK                0x00000400L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0                     0x00000400L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1_MASK                0x00000800L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1                     0x00000800L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2_MASK                0x00001000L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2                     0x00001000L
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL_MASK                   0x00002000L
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL                        0x00002000L
+#define RBBM_DSPLY__DMI_CH2_NUM_BUFS_MASK                  0x0000c000L
+#define RBBM_DSPLY__DMI_CHANNEL_SELECT_MASK                0x00030000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0_MASK                0x00100000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0                     0x00100000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1_MASK                0x00200000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1                     0x00200000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2_MASK                0x00400000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2                     0x00400000L
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL_MASK                   0x00800000L
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL                        0x00800000L
+#define RBBM_DSPLY__DMI_CH3_NUM_BUFS_MASK                  0x03000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0_MASK                0x04000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0                     0x04000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1_MASK                0x08000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1                     0x08000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2_MASK                0x10000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2                     0x10000000L
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL_MASK                   0x20000000L
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL                        0x20000000L
+#define RBBM_DSPLY__DMI_CH4_NUM_BUFS_MASK                  0xc0000000L
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID_MASK         0x00000003L
+#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID_MASK         0x00000300L
+#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID_MASK         0x00030000L
+#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID_MASK         0x03000000L
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST_MASK                  0xffffffffL
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK            0x0000ffffL
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK           0x00ff0000L
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK               0xff000000L
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK               0xffffffffL
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0_MASK                   0x000000ffL
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1_MASK                   0x0000000fL
+#define RBBM_PERIPHID1__DESIGNER0_MASK                     0x000000f0L
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1_MASK                     0x0000000fL
+#define RBBM_PERIPHID2__REVISION_MASK                      0x000000f0L
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK           0x00000003L
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK          0x0000000cL
+#define RBBM_PERIPHID3__MH_INTERFACE_MASK                  0x00000030L
+#define RBBM_PERIPHID3__CONTINUATION_MASK                  0x00000080L
+#define RBBM_PERIPHID3__CONTINUATION                       0x00000080L
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT_MASK                       0x000000ffL
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK               0x0001ff00L
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK            0x0000001fL
+#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK                    0x000003e0L
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK                0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_CP                     0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK                0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA                     0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK                0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH                     0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK                0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC                     0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK                0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ                     0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK                0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX                     0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK               0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB                    0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK                0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC                     0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK               0x00010000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT                    0x00010000L
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK    0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE         0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK        0x00000004L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE             0x00000004L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK    0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE         0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK     0x00000010L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE          0x00000010L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK    0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE         0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE   0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE   0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK     0x00000100L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE          0x00000100L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK        0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE             0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK   0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE        0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK   0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE        0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK   0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE        0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK   0x00004000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE        0x00004000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK   0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE        0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK   0x00010000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE        0x00010000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK   0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE        0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK   0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE        0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE   0x00080000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK     0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE          0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK    0x00200000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE         0x00200000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK      0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE           0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK    0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE         0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK  0x01000000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE       0x01000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK       0x02000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE            0x02000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK    0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE         0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK        0x08000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE             0x08000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK     0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE          0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK    0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE         0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK    0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE         0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK  0x80000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE       0x80000000L
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK     0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE          0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK     0x00000004L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE          0x00000004L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK   0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE        0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE      0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK   0x00000020L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE        0x00000020L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE     0x00000040L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK      0x00000080L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE           0x00000080L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK    0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE         0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK    0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE         0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK    0x00000800L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE         0x00000800L
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK                0x0000ffffL
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK_MASK             0x003f0000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_MASK               0x01000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP                    0x01000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK                  0x02000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI                       0x02000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE_MASK      0x20000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE           0x20000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE_MASK         0x40000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE              0x40000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK             0x80000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE                  0x80000000L
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK                   0x00000001L
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE                        0x00000001L
+
+// RBBM_DEBUG_OUT
+#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT_MASK                 0xffffffffL
+
+// RBBM_DEBUG_CNTL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR_MASK               0x0000003fL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL_MASK                0x00000f00L
+#define RBBM_DEBUG_CNTL__SW_ENABLE_MASK                    0x00001000L
+#define RBBM_DEBUG_CNTL__SW_ENABLE                         0x00001000L
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR_MASK          0x003f0000L
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL_MASK           0x0f000000L
+#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB_MASK           0xf0000000L
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR_MASK                        0x00000002L
+#define RBBM_DEBUG__IGNORE_RTR                             0x00000002L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK                0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU                     0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK             0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC                  0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK             0x00000010L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI                  0x00000010L
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK         0x00000f00L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK                 0x00010000L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI                      0x00010000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK      0x00020000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI           0x00020000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK     0x00040000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI          0x00040000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK      0x00080000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI           0x00080000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK                    0x00100000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR                         0x00100000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK                   0x00200000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR                        0x00200000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK                    0x00400000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR                         0x00400000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK        0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI             0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK               0x01000000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR                    0x01000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK               0x80000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY                    0x80000000L
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS_MASK                 0x0001fffcL
+#define RBBM_READ_ERROR__READ_REQUESTER_MASK               0x40000000L
+#define RBBM_READ_ERROR__READ_REQUESTER                    0x40000000L
+#define RBBM_READ_ERROR__READ_ERROR_MASK                   0x80000000L
+#define RBBM_READ_ERROR__READ_ERROR                        0x80000000L
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK   0x000000ffL
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK                 0x00000001L
+#define RBBM_INT_CNTL__RDERR_INT_MASK                      0x00000001L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK        0x00000002L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK             0x00000002L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK              0x00080000L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK                   0x00080000L
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK               0x00000001L
+#define RBBM_INT_STATUS__RDERR_INT_STAT                    0x00000001L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK      0x00000002L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT           0x00000002L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK            0x00080000L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT                 0x00080000L
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK_MASK                   0x00000001L
+#define RBBM_INT_ACK__RDERR_INT_ACK                        0x00000001L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK          0x00000002L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK               0x00000002L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK                0x00080000L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK                     0x00080000L
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK                0x00000020L
+#define MASTER_INT_SIGNAL__MH_INT_STAT                     0x00000020L
+#define MASTER_INT_SIGNAL__SQ_INT_STAT_MASK                0x04000000L
+#define MASTER_INT_SIGNAL__SQ_INT_STAT                     0x04000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK                0x40000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT                     0x40000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK              0x80000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT                   0x80000000L
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK     0x0000003fL
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK          0xffffffffL
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK          0x0000ffffL
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE_MASK                           0xffffffe0L
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ_MASK                          0x0000003fL
+#define CP_RB_CNTL__RB_BLKSZ_MASK                          0x00003f00L
+#define CP_RB_CNTL__BUF_SWAP_MASK                          0x00030000L
+#define CP_RB_CNTL__RB_POLL_EN_MASK                        0x00100000L
+#define CP_RB_CNTL__RB_POLL_EN                             0x00100000L
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK                      0x08000000L
+#define CP_RB_CNTL__RB_NO_UPDATE                           0x08000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK                    0x80000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA                         0x80000000L
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                 0xfffffffcL
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR_MASK                           0x000fffffL
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK                     0x000fffffL
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR_MASK                           0x000fffffL
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK             0x0fffffffL
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK             0xf0000000L
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK                 0xfffffffcL
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE_MASK                         0xfffffffcL
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK                       0x000fffffL
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE_MASK                         0xfffffffcL
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK                       0x000fffffL
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE_MASK                           0xfffffffcL
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK                         0x000fffffL
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK            0x0000000fL
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK            0x00000f00L
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK             0x000f0000L
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END_MASK                    0x001f0000L
+#define CP_MEQ_THRESHOLDS__ROQ_END_MASK                    0x1f000000L
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK                    0x0000007fL
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK                     0x00007f00L
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK                     0x007f0000L
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST_MASK                      0x0000007fL
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK                         0x0000001fL
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK              0x0000007fL
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK              0x007f0000L
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK           0x0000007fL
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK           0x007f0000L
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK           0x0000007fL
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK           0x007f0000L
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK            0x00000007L
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK            0x00000700L
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK                   0x0000007fL
+#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK                   0x007f0000L
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR_MASK                         0x000003ffL
+#define CP_MEQ_STAT__MEQ_WPTR_MASK                         0x03ff0000L
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK                   0x00000001L
+#define CP_MIU_TAG_STAT__TAG_0_STAT                        0x00000001L
+#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK                   0x00000002L
+#define CP_MIU_TAG_STAT__TAG_1_STAT                        0x00000002L
+#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK                   0x00000004L
+#define CP_MIU_TAG_STAT__TAG_2_STAT                        0x00000004L
+#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK                   0x00000008L
+#define CP_MIU_TAG_STAT__TAG_3_STAT                        0x00000008L
+#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK                   0x00000010L
+#define CP_MIU_TAG_STAT__TAG_4_STAT                        0x00000010L
+#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK                   0x00000020L
+#define CP_MIU_TAG_STAT__TAG_5_STAT                        0x00000020L
+#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK                   0x00000040L
+#define CP_MIU_TAG_STAT__TAG_6_STAT                        0x00000040L
+#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK                   0x00000080L
+#define CP_MIU_TAG_STAT__TAG_7_STAT                        0x00000080L
+#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK                   0x00000100L
+#define CP_MIU_TAG_STAT__TAG_8_STAT                        0x00000100L
+#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK                   0x00000200L
+#define CP_MIU_TAG_STAT__TAG_9_STAT                        0x00000200L
+#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK                  0x00000400L
+#define CP_MIU_TAG_STAT__TAG_10_STAT                       0x00000400L
+#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK                  0x00000800L
+#define CP_MIU_TAG_STAT__TAG_11_STAT                       0x00000800L
+#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK                  0x00001000L
+#define CP_MIU_TAG_STAT__TAG_12_STAT                       0x00001000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK                  0x00002000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT                       0x00002000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK                  0x00004000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT                       0x00004000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK                  0x00008000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT                       0x00008000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK                  0x00010000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT                       0x00010000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK                  0x00020000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT                       0x00020000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK           0x80000000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG                0x80000000L
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX_MASK                       0x0000007fL
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK                   0x00030000L
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA_MASK                         0xffffffffL
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX_MASK                        0x0000ffffL
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK            0x02000000L
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY                 0x02000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK            0x04000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY                 0x04000000L
+#define CP_ME_CNTL__ME_HALT_MASK                           0x10000000L
+#define CP_ME_CNTL__ME_HALT                                0x10000000L
+#define CP_ME_CNTL__ME_BUSY_MASK                           0x20000000L
+#define CP_ME_CNTL__ME_BUSY                                0x20000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE_MASK                     0x80000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE                          0x80000000L
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA_MASK                   0xffffffffL
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK                   0xffffffffL
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR_MASK                       0xffffffffL
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK             0x007fffffL
+#define CP_DEBUG__PREDICATE_DISABLE_MASK                   0x00800000L
+#define CP_DEBUG__PREDICATE_DISABLE                        0x00800000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK                 0x01000000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE                      0x01000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK             0x02000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE                  0x02000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK                  0x04000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS                       0x04000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK                 0x08000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE                      0x08000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK              0x10000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE                   0x10000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK              0x40000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL                   0x40000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK              0x80000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE                   0x80000000L
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK                0xffffffffL
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK                0xffffffffL
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK                0xffffffffL
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK                0xffffffffL
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK                0xffffffffL
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK                0xffffffffL
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK                0xffffffffL
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK                0xffffffffL
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK_MASK                    0x000000ffL
+#define SCRATCH_UMSK__SCRATCH_SWAP_MASK                    0x00030000L
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR_MASK                    0xffffffe0L
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM                    0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR                   0x00000002L
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM                    0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR                   0x00000002L
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK               0x00000001L
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC                    0x00000001L
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK                0x00000003L
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK                0xfffffffcL
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK                0xffffffffL
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK   0x00000001L
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR        0x00000001L
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK  0x00000003L
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK  0xfffffffcL
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK  0xffffffffL
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK_MASK                      0x00080000L
+#define CP_INT_CNTL__SW_INT_MASK                           0x00080000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK             0x00800000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK                  0x00800000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK                0x01000000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK                     0x01000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK        0x02000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK             0x02000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK          0x04000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK               0x04000000L
+#define CP_INT_CNTL__IB_ERROR_MASK_MASK                    0x08000000L
+#define CP_INT_CNTL__IB_ERROR_MASK                         0x08000000L
+#define CP_INT_CNTL__IB2_INT_MASK_MASK                     0x20000000L
+#define CP_INT_CNTL__IB2_INT_MASK                          0x20000000L
+#define CP_INT_CNTL__IB1_INT_MASK_MASK                     0x40000000L
+#define CP_INT_CNTL__IB1_INT_MASK                          0x40000000L
+#define CP_INT_CNTL__RB_INT_MASK_MASK                      0x80000000L
+#define CP_INT_CNTL__RB_INT_MASK                           0x80000000L
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT_MASK                    0x00080000L
+#define CP_INT_STATUS__SW_INT_STAT                         0x00080000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK           0x00800000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT                0x00800000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK              0x01000000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT                   0x01000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK      0x02000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT           0x02000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK        0x04000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT             0x04000000L
+#define CP_INT_STATUS__IB_ERROR_STAT_MASK                  0x08000000L
+#define CP_INT_STATUS__IB_ERROR_STAT                       0x08000000L
+#define CP_INT_STATUS__IB2_INT_STAT_MASK                   0x20000000L
+#define CP_INT_STATUS__IB2_INT_STAT                        0x20000000L
+#define CP_INT_STATUS__IB1_INT_STAT_MASK                   0x40000000L
+#define CP_INT_STATUS__IB1_INT_STAT                        0x40000000L
+#define CP_INT_STATUS__RB_INT_STAT_MASK                    0x80000000L
+#define CP_INT_STATUS__RB_INT_STAT                         0x80000000L
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK_MASK                        0x00080000L
+#define CP_INT_ACK__SW_INT_ACK                             0x00080000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK               0x00800000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK                    0x00800000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK                  0x01000000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK                       0x01000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK          0x02000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK               0x02000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK            0x04000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK                 0x04000000L
+#define CP_INT_ACK__IB_ERROR_ACK_MASK                      0x08000000L
+#define CP_INT_ACK__IB_ERROR_ACK                           0x08000000L
+#define CP_INT_ACK__IB2_INT_ACK_MASK                       0x20000000L
+#define CP_INT_ACK__IB2_INT_ACK                            0x20000000L
+#define CP_INT_ACK__IB1_INT_ACK_MASK                       0x40000000L
+#define CP_INT_ACK__IB1_INT_ACK                            0x40000000L
+#define CP_INT_ACK__RB_INT_ACK_MASK                        0x80000000L
+#define CP_INT_ACK__RB_INT_ACK                             0x80000000L
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                 0x000001ffL
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK                 0x00ffffffL
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK                0x0000000fL
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK          0x00000300L
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK          0x0000003fL
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK               0xffffffffL
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK               0x0000ffffL
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK                   0xffffffffL
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK                   0xffffffffL
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK               0xffffffffL
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK               0xffffffffL
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0_MASK                      0x00000001L
+#define CP_NV_FLAGS_0__DISCARD_0                           0x00000001L
+#define CP_NV_FLAGS_0__END_RCVD_0_MASK                     0x00000002L
+#define CP_NV_FLAGS_0__END_RCVD_0                          0x00000002L
+#define CP_NV_FLAGS_0__DISCARD_1_MASK                      0x00000004L
+#define CP_NV_FLAGS_0__DISCARD_1                           0x00000004L
+#define CP_NV_FLAGS_0__END_RCVD_1_MASK                     0x00000008L
+#define CP_NV_FLAGS_0__END_RCVD_1                          0x00000008L
+#define CP_NV_FLAGS_0__DISCARD_2_MASK                      0x00000010L
+#define CP_NV_FLAGS_0__DISCARD_2                           0x00000010L
+#define CP_NV_FLAGS_0__END_RCVD_2_MASK                     0x00000020L
+#define CP_NV_FLAGS_0__END_RCVD_2                          0x00000020L
+#define CP_NV_FLAGS_0__DISCARD_3_MASK                      0x00000040L
+#define CP_NV_FLAGS_0__DISCARD_3                           0x00000040L
+#define CP_NV_FLAGS_0__END_RCVD_3_MASK                     0x00000080L
+#define CP_NV_FLAGS_0__END_RCVD_3                          0x00000080L
+#define CP_NV_FLAGS_0__DISCARD_4_MASK                      0x00000100L
+#define CP_NV_FLAGS_0__DISCARD_4                           0x00000100L
+#define CP_NV_FLAGS_0__END_RCVD_4_MASK                     0x00000200L
+#define CP_NV_FLAGS_0__END_RCVD_4                          0x00000200L
+#define CP_NV_FLAGS_0__DISCARD_5_MASK                      0x00000400L
+#define CP_NV_FLAGS_0__DISCARD_5                           0x00000400L
+#define CP_NV_FLAGS_0__END_RCVD_5_MASK                     0x00000800L
+#define CP_NV_FLAGS_0__END_RCVD_5                          0x00000800L
+#define CP_NV_FLAGS_0__DISCARD_6_MASK                      0x00001000L
+#define CP_NV_FLAGS_0__DISCARD_6                           0x00001000L
+#define CP_NV_FLAGS_0__END_RCVD_6_MASK                     0x00002000L
+#define CP_NV_FLAGS_0__END_RCVD_6                          0x00002000L
+#define CP_NV_FLAGS_0__DISCARD_7_MASK                      0x00004000L
+#define CP_NV_FLAGS_0__DISCARD_7                           0x00004000L
+#define CP_NV_FLAGS_0__END_RCVD_7_MASK                     0x00008000L
+#define CP_NV_FLAGS_0__END_RCVD_7                          0x00008000L
+#define CP_NV_FLAGS_0__DISCARD_8_MASK                      0x00010000L
+#define CP_NV_FLAGS_0__DISCARD_8                           0x00010000L
+#define CP_NV_FLAGS_0__END_RCVD_8_MASK                     0x00020000L
+#define CP_NV_FLAGS_0__END_RCVD_8                          0x00020000L
+#define CP_NV_FLAGS_0__DISCARD_9_MASK                      0x00040000L
+#define CP_NV_FLAGS_0__DISCARD_9                           0x00040000L
+#define CP_NV_FLAGS_0__END_RCVD_9_MASK                     0x00080000L
+#define CP_NV_FLAGS_0__END_RCVD_9                          0x00080000L
+#define CP_NV_FLAGS_0__DISCARD_10_MASK                     0x00100000L
+#define CP_NV_FLAGS_0__DISCARD_10                          0x00100000L
+#define CP_NV_FLAGS_0__END_RCVD_10_MASK                    0x00200000L
+#define CP_NV_FLAGS_0__END_RCVD_10                         0x00200000L
+#define CP_NV_FLAGS_0__DISCARD_11_MASK                     0x00400000L
+#define CP_NV_FLAGS_0__DISCARD_11                          0x00400000L
+#define CP_NV_FLAGS_0__END_RCVD_11_MASK                    0x00800000L
+#define CP_NV_FLAGS_0__END_RCVD_11                         0x00800000L
+#define CP_NV_FLAGS_0__DISCARD_12_MASK                     0x01000000L
+#define CP_NV_FLAGS_0__DISCARD_12                          0x01000000L
+#define CP_NV_FLAGS_0__END_RCVD_12_MASK                    0x02000000L
+#define CP_NV_FLAGS_0__END_RCVD_12                         0x02000000L
+#define CP_NV_FLAGS_0__DISCARD_13_MASK                     0x04000000L
+#define CP_NV_FLAGS_0__DISCARD_13                          0x04000000L
+#define CP_NV_FLAGS_0__END_RCVD_13_MASK                    0x08000000L
+#define CP_NV_FLAGS_0__END_RCVD_13                         0x08000000L
+#define CP_NV_FLAGS_0__DISCARD_14_MASK                     0x10000000L
+#define CP_NV_FLAGS_0__DISCARD_14                          0x10000000L
+#define CP_NV_FLAGS_0__END_RCVD_14_MASK                    0x20000000L
+#define CP_NV_FLAGS_0__END_RCVD_14                         0x20000000L
+#define CP_NV_FLAGS_0__DISCARD_15_MASK                     0x40000000L
+#define CP_NV_FLAGS_0__DISCARD_15                          0x40000000L
+#define CP_NV_FLAGS_0__END_RCVD_15_MASK                    0x80000000L
+#define CP_NV_FLAGS_0__END_RCVD_15                         0x80000000L
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16_MASK                     0x00000001L
+#define CP_NV_FLAGS_1__DISCARD_16                          0x00000001L
+#define CP_NV_FLAGS_1__END_RCVD_16_MASK                    0x00000002L
+#define CP_NV_FLAGS_1__END_RCVD_16                         0x00000002L
+#define CP_NV_FLAGS_1__DISCARD_17_MASK                     0x00000004L
+#define CP_NV_FLAGS_1__DISCARD_17                          0x00000004L
+#define CP_NV_FLAGS_1__END_RCVD_17_MASK                    0x00000008L
+#define CP_NV_FLAGS_1__END_RCVD_17                         0x00000008L
+#define CP_NV_FLAGS_1__DISCARD_18_MASK                     0x00000010L
+#define CP_NV_FLAGS_1__DISCARD_18                          0x00000010L
+#define CP_NV_FLAGS_1__END_RCVD_18_MASK                    0x00000020L
+#define CP_NV_FLAGS_1__END_RCVD_18                         0x00000020L
+#define CP_NV_FLAGS_1__DISCARD_19_MASK                     0x00000040L
+#define CP_NV_FLAGS_1__DISCARD_19                          0x00000040L
+#define CP_NV_FLAGS_1__END_RCVD_19_MASK                    0x00000080L
+#define CP_NV_FLAGS_1__END_RCVD_19                         0x00000080L
+#define CP_NV_FLAGS_1__DISCARD_20_MASK                     0x00000100L
+#define CP_NV_FLAGS_1__DISCARD_20                          0x00000100L
+#define CP_NV_FLAGS_1__END_RCVD_20_MASK                    0x00000200L
+#define CP_NV_FLAGS_1__END_RCVD_20                         0x00000200L
+#define CP_NV_FLAGS_1__DISCARD_21_MASK                     0x00000400L
+#define CP_NV_FLAGS_1__DISCARD_21                          0x00000400L
+#define CP_NV_FLAGS_1__END_RCVD_21_MASK                    0x00000800L
+#define CP_NV_FLAGS_1__END_RCVD_21                         0x00000800L
+#define CP_NV_FLAGS_1__DISCARD_22_MASK                     0x00001000L
+#define CP_NV_FLAGS_1__DISCARD_22                          0x00001000L
+#define CP_NV_FLAGS_1__END_RCVD_22_MASK                    0x00002000L
+#define CP_NV_FLAGS_1__END_RCVD_22                         0x00002000L
+#define CP_NV_FLAGS_1__DISCARD_23_MASK                     0x00004000L
+#define CP_NV_FLAGS_1__DISCARD_23                          0x00004000L
+#define CP_NV_FLAGS_1__END_RCVD_23_MASK                    0x00008000L
+#define CP_NV_FLAGS_1__END_RCVD_23                         0x00008000L
+#define CP_NV_FLAGS_1__DISCARD_24_MASK                     0x00010000L
+#define CP_NV_FLAGS_1__DISCARD_24                          0x00010000L
+#define CP_NV_FLAGS_1__END_RCVD_24_MASK                    0x00020000L
+#define CP_NV_FLAGS_1__END_RCVD_24                         0x00020000L
+#define CP_NV_FLAGS_1__DISCARD_25_MASK                     0x00040000L
+#define CP_NV_FLAGS_1__DISCARD_25                          0x00040000L
+#define CP_NV_FLAGS_1__END_RCVD_25_MASK                    0x00080000L
+#define CP_NV_FLAGS_1__END_RCVD_25                         0x00080000L
+#define CP_NV_FLAGS_1__DISCARD_26_MASK                     0x00100000L
+#define CP_NV_FLAGS_1__DISCARD_26                          0x00100000L
+#define CP_NV_FLAGS_1__END_RCVD_26_MASK                    0x00200000L
+#define CP_NV_FLAGS_1__END_RCVD_26                         0x00200000L
+#define CP_NV_FLAGS_1__DISCARD_27_MASK                     0x00400000L
+#define CP_NV_FLAGS_1__DISCARD_27                          0x00400000L
+#define CP_NV_FLAGS_1__END_RCVD_27_MASK                    0x00800000L
+#define CP_NV_FLAGS_1__END_RCVD_27                         0x00800000L
+#define CP_NV_FLAGS_1__DISCARD_28_MASK                     0x01000000L
+#define CP_NV_FLAGS_1__DISCARD_28                          0x01000000L
+#define CP_NV_FLAGS_1__END_RCVD_28_MASK                    0x02000000L
+#define CP_NV_FLAGS_1__END_RCVD_28                         0x02000000L
+#define CP_NV_FLAGS_1__DISCARD_29_MASK                     0x04000000L
+#define CP_NV_FLAGS_1__DISCARD_29                          0x04000000L
+#define CP_NV_FLAGS_1__END_RCVD_29_MASK                    0x08000000L
+#define CP_NV_FLAGS_1__END_RCVD_29                         0x08000000L
+#define CP_NV_FLAGS_1__DISCARD_30_MASK                     0x10000000L
+#define CP_NV_FLAGS_1__DISCARD_30                          0x10000000L
+#define CP_NV_FLAGS_1__END_RCVD_30_MASK                    0x20000000L
+#define CP_NV_FLAGS_1__END_RCVD_30                         0x20000000L
+#define CP_NV_FLAGS_1__DISCARD_31_MASK                     0x40000000L
+#define CP_NV_FLAGS_1__DISCARD_31                          0x40000000L
+#define CP_NV_FLAGS_1__END_RCVD_31_MASK                    0x80000000L
+#define CP_NV_FLAGS_1__END_RCVD_31                         0x80000000L
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32_MASK                     0x00000001L
+#define CP_NV_FLAGS_2__DISCARD_32                          0x00000001L
+#define CP_NV_FLAGS_2__END_RCVD_32_MASK                    0x00000002L
+#define CP_NV_FLAGS_2__END_RCVD_32                         0x00000002L
+#define CP_NV_FLAGS_2__DISCARD_33_MASK                     0x00000004L
+#define CP_NV_FLAGS_2__DISCARD_33                          0x00000004L
+#define CP_NV_FLAGS_2__END_RCVD_33_MASK                    0x00000008L
+#define CP_NV_FLAGS_2__END_RCVD_33                         0x00000008L
+#define CP_NV_FLAGS_2__DISCARD_34_MASK                     0x00000010L
+#define CP_NV_FLAGS_2__DISCARD_34                          0x00000010L
+#define CP_NV_FLAGS_2__END_RCVD_34_MASK                    0x00000020L
+#define CP_NV_FLAGS_2__END_RCVD_34                         0x00000020L
+#define CP_NV_FLAGS_2__DISCARD_35_MASK                     0x00000040L
+#define CP_NV_FLAGS_2__DISCARD_35                          0x00000040L
+#define CP_NV_FLAGS_2__END_RCVD_35_MASK                    0x00000080L
+#define CP_NV_FLAGS_2__END_RCVD_35                         0x00000080L
+#define CP_NV_FLAGS_2__DISCARD_36_MASK                     0x00000100L
+#define CP_NV_FLAGS_2__DISCARD_36                          0x00000100L
+#define CP_NV_FLAGS_2__END_RCVD_36_MASK                    0x00000200L
+#define CP_NV_FLAGS_2__END_RCVD_36                         0x00000200L
+#define CP_NV_FLAGS_2__DISCARD_37_MASK                     0x00000400L
+#define CP_NV_FLAGS_2__DISCARD_37                          0x00000400L
+#define CP_NV_FLAGS_2__END_RCVD_37_MASK                    0x00000800L
+#define CP_NV_FLAGS_2__END_RCVD_37                         0x00000800L
+#define CP_NV_FLAGS_2__DISCARD_38_MASK                     0x00001000L
+#define CP_NV_FLAGS_2__DISCARD_38                          0x00001000L
+#define CP_NV_FLAGS_2__END_RCVD_38_MASK                    0x00002000L
+#define CP_NV_FLAGS_2__END_RCVD_38                         0x00002000L
+#define CP_NV_FLAGS_2__DISCARD_39_MASK                     0x00004000L
+#define CP_NV_FLAGS_2__DISCARD_39                          0x00004000L
+#define CP_NV_FLAGS_2__END_RCVD_39_MASK                    0x00008000L
+#define CP_NV_FLAGS_2__END_RCVD_39                         0x00008000L
+#define CP_NV_FLAGS_2__DISCARD_40_MASK                     0x00010000L
+#define CP_NV_FLAGS_2__DISCARD_40                          0x00010000L
+#define CP_NV_FLAGS_2__END_RCVD_40_MASK                    0x00020000L
+#define CP_NV_FLAGS_2__END_RCVD_40                         0x00020000L
+#define CP_NV_FLAGS_2__DISCARD_41_MASK                     0x00040000L
+#define CP_NV_FLAGS_2__DISCARD_41                          0x00040000L
+#define CP_NV_FLAGS_2__END_RCVD_41_MASK                    0x00080000L
+#define CP_NV_FLAGS_2__END_RCVD_41                         0x00080000L
+#define CP_NV_FLAGS_2__DISCARD_42_MASK                     0x00100000L
+#define CP_NV_FLAGS_2__DISCARD_42                          0x00100000L
+#define CP_NV_FLAGS_2__END_RCVD_42_MASK                    0x00200000L
+#define CP_NV_FLAGS_2__END_RCVD_42                         0x00200000L
+#define CP_NV_FLAGS_2__DISCARD_43_MASK                     0x00400000L
+#define CP_NV_FLAGS_2__DISCARD_43                          0x00400000L
+#define CP_NV_FLAGS_2__END_RCVD_43_MASK                    0x00800000L
+#define CP_NV_FLAGS_2__END_RCVD_43                         0x00800000L
+#define CP_NV_FLAGS_2__DISCARD_44_MASK                     0x01000000L
+#define CP_NV_FLAGS_2__DISCARD_44                          0x01000000L
+#define CP_NV_FLAGS_2__END_RCVD_44_MASK                    0x02000000L
+#define CP_NV_FLAGS_2__END_RCVD_44                         0x02000000L
+#define CP_NV_FLAGS_2__DISCARD_45_MASK                     0x04000000L
+#define CP_NV_FLAGS_2__DISCARD_45                          0x04000000L
+#define CP_NV_FLAGS_2__END_RCVD_45_MASK                    0x08000000L
+#define CP_NV_FLAGS_2__END_RCVD_45                         0x08000000L
+#define CP_NV_FLAGS_2__DISCARD_46_MASK                     0x10000000L
+#define CP_NV_FLAGS_2__DISCARD_46                          0x10000000L
+#define CP_NV_FLAGS_2__END_RCVD_46_MASK                    0x20000000L
+#define CP_NV_FLAGS_2__END_RCVD_46                         0x20000000L
+#define CP_NV_FLAGS_2__DISCARD_47_MASK                     0x40000000L
+#define CP_NV_FLAGS_2__DISCARD_47                          0x40000000L
+#define CP_NV_FLAGS_2__END_RCVD_47_MASK                    0x80000000L
+#define CP_NV_FLAGS_2__END_RCVD_47                         0x80000000L
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48_MASK                     0x00000001L
+#define CP_NV_FLAGS_3__DISCARD_48                          0x00000001L
+#define CP_NV_FLAGS_3__END_RCVD_48_MASK                    0x00000002L
+#define CP_NV_FLAGS_3__END_RCVD_48                         0x00000002L
+#define CP_NV_FLAGS_3__DISCARD_49_MASK                     0x00000004L
+#define CP_NV_FLAGS_3__DISCARD_49                          0x00000004L
+#define CP_NV_FLAGS_3__END_RCVD_49_MASK                    0x00000008L
+#define CP_NV_FLAGS_3__END_RCVD_49                         0x00000008L
+#define CP_NV_FLAGS_3__DISCARD_50_MASK                     0x00000010L
+#define CP_NV_FLAGS_3__DISCARD_50                          0x00000010L
+#define CP_NV_FLAGS_3__END_RCVD_50_MASK                    0x00000020L
+#define CP_NV_FLAGS_3__END_RCVD_50                         0x00000020L
+#define CP_NV_FLAGS_3__DISCARD_51_MASK                     0x00000040L
+#define CP_NV_FLAGS_3__DISCARD_51                          0x00000040L
+#define CP_NV_FLAGS_3__END_RCVD_51_MASK                    0x00000080L
+#define CP_NV_FLAGS_3__END_RCVD_51                         0x00000080L
+#define CP_NV_FLAGS_3__DISCARD_52_MASK                     0x00000100L
+#define CP_NV_FLAGS_3__DISCARD_52                          0x00000100L
+#define CP_NV_FLAGS_3__END_RCVD_52_MASK                    0x00000200L
+#define CP_NV_FLAGS_3__END_RCVD_52                         0x00000200L
+#define CP_NV_FLAGS_3__DISCARD_53_MASK                     0x00000400L
+#define CP_NV_FLAGS_3__DISCARD_53                          0x00000400L
+#define CP_NV_FLAGS_3__END_RCVD_53_MASK                    0x00000800L
+#define CP_NV_FLAGS_3__END_RCVD_53                         0x00000800L
+#define CP_NV_FLAGS_3__DISCARD_54_MASK                     0x00001000L
+#define CP_NV_FLAGS_3__DISCARD_54                          0x00001000L
+#define CP_NV_FLAGS_3__END_RCVD_54_MASK                    0x00002000L
+#define CP_NV_FLAGS_3__END_RCVD_54                         0x00002000L
+#define CP_NV_FLAGS_3__DISCARD_55_MASK                     0x00004000L
+#define CP_NV_FLAGS_3__DISCARD_55                          0x00004000L
+#define CP_NV_FLAGS_3__END_RCVD_55_MASK                    0x00008000L
+#define CP_NV_FLAGS_3__END_RCVD_55                         0x00008000L
+#define CP_NV_FLAGS_3__DISCARD_56_MASK                     0x00010000L
+#define CP_NV_FLAGS_3__DISCARD_56                          0x00010000L
+#define CP_NV_FLAGS_3__END_RCVD_56_MASK                    0x00020000L
+#define CP_NV_FLAGS_3__END_RCVD_56                         0x00020000L
+#define CP_NV_FLAGS_3__DISCARD_57_MASK                     0x00040000L
+#define CP_NV_FLAGS_3__DISCARD_57                          0x00040000L
+#define CP_NV_FLAGS_3__END_RCVD_57_MASK                    0x00080000L
+#define CP_NV_FLAGS_3__END_RCVD_57                         0x00080000L
+#define CP_NV_FLAGS_3__DISCARD_58_MASK                     0x00100000L
+#define CP_NV_FLAGS_3__DISCARD_58                          0x00100000L
+#define CP_NV_FLAGS_3__END_RCVD_58_MASK                    0x00200000L
+#define CP_NV_FLAGS_3__END_RCVD_58                         0x00200000L
+#define CP_NV_FLAGS_3__DISCARD_59_MASK                     0x00400000L
+#define CP_NV_FLAGS_3__DISCARD_59                          0x00400000L
+#define CP_NV_FLAGS_3__END_RCVD_59_MASK                    0x00800000L
+#define CP_NV_FLAGS_3__END_RCVD_59                         0x00800000L
+#define CP_NV_FLAGS_3__DISCARD_60_MASK                     0x01000000L
+#define CP_NV_FLAGS_3__DISCARD_60                          0x01000000L
+#define CP_NV_FLAGS_3__END_RCVD_60_MASK                    0x02000000L
+#define CP_NV_FLAGS_3__END_RCVD_60                         0x02000000L
+#define CP_NV_FLAGS_3__DISCARD_61_MASK                     0x04000000L
+#define CP_NV_FLAGS_3__DISCARD_61                          0x04000000L
+#define CP_NV_FLAGS_3__END_RCVD_61_MASK                    0x08000000L
+#define CP_NV_FLAGS_3__END_RCVD_61                         0x08000000L
+#define CP_NV_FLAGS_3__DISCARD_62_MASK                     0x10000000L
+#define CP_NV_FLAGS_3__DISCARD_62                          0x10000000L
+#define CP_NV_FLAGS_3__END_RCVD_62_MASK                    0x20000000L
+#define CP_NV_FLAGS_3__END_RCVD_62                         0x20000000L
+#define CP_NV_FLAGS_3__DISCARD_63_MASK                     0x40000000L
+#define CP_NV_FLAGS_3__DISCARD_63                          0x40000000L
+#define CP_NV_FLAGS_3__END_RCVD_63_MASK                    0x80000000L
+#define CP_NV_FLAGS_3__END_RCVD_63                         0x80000000L
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK       0x0000001fL
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK         0xffffffffL
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER_MASK                      0xffffffffL
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY_MASK                          0x00000001L
+#define CP_STAT__MIU_WR_BUSY                               0x00000001L
+#define CP_STAT__MIU_RD_REQ_BUSY_MASK                      0x00000002L
+#define CP_STAT__MIU_RD_REQ_BUSY                           0x00000002L
+#define CP_STAT__MIU_RD_RETURN_BUSY_MASK                   0x00000004L
+#define CP_STAT__MIU_RD_RETURN_BUSY                        0x00000004L
+#define CP_STAT__RBIU_BUSY_MASK                            0x00000008L
+#define CP_STAT__RBIU_BUSY                                 0x00000008L
+#define CP_STAT__RCIU_BUSY_MASK                            0x00000010L
+#define CP_STAT__RCIU_BUSY                                 0x00000010L
+#define CP_STAT__CSF_RING_BUSY_MASK                        0x00000020L
+#define CP_STAT__CSF_RING_BUSY                             0x00000020L
+#define CP_STAT__CSF_INDIRECTS_BUSY_MASK                   0x00000040L
+#define CP_STAT__CSF_INDIRECTS_BUSY                        0x00000040L
+#define CP_STAT__CSF_INDIRECT2_BUSY_MASK                   0x00000080L
+#define CP_STAT__CSF_INDIRECT2_BUSY                        0x00000080L
+#define CP_STAT__CSF_ST_BUSY_MASK                          0x00000200L
+#define CP_STAT__CSF_ST_BUSY                               0x00000200L
+#define CP_STAT__CSF_BUSY_MASK                             0x00000400L
+#define CP_STAT__CSF_BUSY                                  0x00000400L
+#define CP_STAT__RING_QUEUE_BUSY_MASK                      0x00000800L
+#define CP_STAT__RING_QUEUE_BUSY                           0x00000800L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK                 0x00001000L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY                      0x00001000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK                 0x00002000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY                      0x00002000L
+#define CP_STAT__ST_QUEUE_BUSY_MASK                        0x00010000L
+#define CP_STAT__ST_QUEUE_BUSY                             0x00010000L
+#define CP_STAT__PFP_BUSY_MASK                             0x00020000L
+#define CP_STAT__PFP_BUSY                                  0x00020000L
+#define CP_STAT__MEQ_RING_BUSY_MASK                        0x00040000L
+#define CP_STAT__MEQ_RING_BUSY                             0x00040000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK                   0x00080000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY                        0x00080000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK                   0x00100000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY                        0x00100000L
+#define CP_STAT__MIU_WC_STALL_MASK                         0x00200000L
+#define CP_STAT__MIU_WC_STALL                              0x00200000L
+#define CP_STAT__CP_NRT_BUSY_MASK                          0x00400000L
+#define CP_STAT__CP_NRT_BUSY                               0x00400000L
+#define CP_STAT___3D_BUSY_MASK                             0x00800000L
+#define CP_STAT___3D_BUSY                                  0x00800000L
+#define CP_STAT__ME_BUSY_MASK                              0x04000000L
+#define CP_STAT__ME_BUSY                                   0x04000000L
+#define CP_STAT__ME_WC_BUSY_MASK                           0x20000000L
+#define CP_STAT__ME_WC_BUSY                                0x20000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK              0x40000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY                   0x40000000L
+#define CP_STAT__CP_BUSY_MASK                              0x80000000L
+#define CP_STAT__CP_BUSY                                   0x80000000L
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE_MASK                          0xffffffffL
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE_MASK                          0xffffffffL
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK           0x000000ffL
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK       0x00000100L
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA            0x00000100L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK             0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA                  0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK             0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA                  0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK             0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA                  0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK             0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA                  0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK             0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA                  0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK             0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA                  0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK             0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA                  0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK             0x00010000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA                  0x00010000L
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA_MASK           0x00020000L
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA                0x00020000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK               0x02000000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA                    0x02000000L
+#define COHER_STATUS_PM4__STATUS_MASK                      0x80000000L
+#define COHER_STATUS_PM4__STATUS                           0x80000000L
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE_MASK                         0xffffffffL
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE_MASK                         0xffffffffL
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK          0x000000ffL
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK      0x00000100L
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA           0x00000100L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK            0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA                 0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK            0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA                 0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK            0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA                 0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK            0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA                 0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK            0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA                 0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK            0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA                 0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK            0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA                 0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK            0x00010000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA                 0x00010000L
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA_MASK          0x00020000L
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA               0x00020000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK              0x02000000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA                   0x02000000L
+#define COHER_STATUS_HOST__STATUS_MASK                     0x80000000L
+#define COHER_STATUS_HOST__STATUS                          0x80000000L
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0_MASK                0xfffff000L
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1_MASK                0xfffff000L
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2_MASK                0xfffff000L
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3_MASK                0xfffff000L
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4_MASK                0xfffff000L
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5_MASK                0xfffff000L
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6_MASK                0xfffff000L
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7_MASK                0xfffff000L
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH_MASK                0x00003fffL
+#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK                 0x0000c000L
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT_MASK                   0x0000000fL
+#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK               0x00000030L
+#define RB_COLOR_INFO__COLOR_LINEAR_MASK                   0x00000040L
+#define RB_COLOR_INFO__COLOR_LINEAR                        0x00000040L
+#define RB_COLOR_INFO__COLOR_ENDIAN_MASK                   0x00000180L
+#define RB_COLOR_INFO__COLOR_SWAP_MASK                     0x00000600L
+#define RB_COLOR_INFO__COLOR_BASE_MASK                     0xfffff000L
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK                   0x00000001L
+#define RB_DEPTH_INFO__DEPTH_FORMAT                        0x00000001L
+#define RB_DEPTH_INFO__DEPTH_BASE_MASK                     0xfffff000L
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF_MASK                 0x000000ffL
+#define RB_STENCILREFMASK__STENCILMASK_MASK                0x0000ff00L
+#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK           0x00ff0000L
+#define RB_STENCILREFMASK__RESERVED0_MASK                  0x01000000L
+#define RB_STENCILREFMASK__RESERVED0                       0x01000000L
+#define RB_STENCILREFMASK__RESERVED1_MASK                  0x02000000L
+#define RB_STENCILREFMASK__RESERVED1                       0x02000000L
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF_MASK                       0xffffffffL
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED_MASK                      0x00000001L
+#define RB_COLOR_MASK__WRITE_RED                           0x00000001L
+#define RB_COLOR_MASK__WRITE_GREEN_MASK                    0x00000002L
+#define RB_COLOR_MASK__WRITE_GREEN                         0x00000002L
+#define RB_COLOR_MASK__WRITE_BLUE_MASK                     0x00000004L
+#define RB_COLOR_MASK__WRITE_BLUE                          0x00000004L
+#define RB_COLOR_MASK__WRITE_ALPHA_MASK                    0x00000008L
+#define RB_COLOR_MASK__WRITE_ALPHA                         0x00000008L
+#define RB_COLOR_MASK__RESERVED2_MASK                      0x00000010L
+#define RB_COLOR_MASK__RESERVED2                           0x00000010L
+#define RB_COLOR_MASK__RESERVED3_MASK                      0x00000020L
+#define RB_COLOR_MASK__RESERVED3                           0x00000020L
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED_MASK                       0x000000ffL
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN_MASK                   0x000000ffL
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE_MASK                     0x000000ffL
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK                   0x000000ffL
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED_MASK                         0x000000ffL
+#define RB_FOG_COLOR__FOG_GREEN_MASK                       0x0000ff00L
+#define RB_FOG_COLOR__FOG_BLUE_MASK                        0x00ff0000L
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK           0x000000ffL
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK          0x0000ff00L
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK     0x00ff0000L
+#define RB_STENCILREFMASK_BF__RESERVED4_MASK               0x01000000L
+#define RB_STENCILREFMASK_BF__RESERVED4                    0x01000000L
+#define RB_STENCILREFMASK_BF__RESERVED5_MASK               0x02000000L
+#define RB_STENCILREFMASK_BF__RESERVED5                    0x02000000L
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK               0x00000001L
+#define RB_DEPTHCONTROL__STENCIL_ENABLE                    0x00000001L
+#define RB_DEPTHCONTROL__Z_ENABLE_MASK                     0x00000002L
+#define RB_DEPTHCONTROL__Z_ENABLE                          0x00000002L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK               0x00000004L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE                    0x00000004L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK               0x00000008L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE                    0x00000008L
+#define RB_DEPTHCONTROL__ZFUNC_MASK                        0x00000070L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK              0x00000080L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE                   0x00000080L
+#define RB_DEPTHCONTROL__STENCILFUNC_MASK                  0x00000700L
+#define RB_DEPTHCONTROL__STENCILFAIL_MASK                  0x00003800L
+#define RB_DEPTHCONTROL__STENCILZPASS_MASK                 0x0001c000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_MASK                 0x000e0000L
+#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK               0x00700000L
+#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK               0x03800000L
+#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK              0x1c000000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK              0xe0000000L
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK               0x0000001fL
+#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK               0x000000e0L
+#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK              0x00001f00L
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK               0x001f0000L
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK               0x00e00000L
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK              0x1f000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK           0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE                0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_MASK                  0x40000000L
+#define RB_BLENDCONTROL__BLEND_FORCE                       0x40000000L
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC_MASK                   0x00000007L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK            0x00000008L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE                 0x00000008L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK         0x00000010L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE              0x00000010L
+#define RB_COLORCONTROL__BLEND_DISABLE_MASK                0x00000020L
+#define RB_COLORCONTROL__BLEND_DISABLE                     0x00000020L
+#define RB_COLORCONTROL__FOG_ENABLE_MASK                   0x00000040L
+#define RB_COLORCONTROL__FOG_ENABLE                        0x00000040L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK               0x00000080L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG                    0x00000080L
+#define RB_COLORCONTROL__ROP_CODE_MASK                     0x00000f00L
+#define RB_COLORCONTROL__DITHER_MODE_MASK                  0x00003000L
+#define RB_COLORCONTROL__DITHER_TYPE_MASK                  0x0000c000L
+#define RB_COLORCONTROL__PIXEL_FOG_MASK                    0x00010000L
+#define RB_COLORCONTROL__PIXEL_FOG                         0x00010000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK        0x03000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK        0x0c000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK        0x30000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK        0xc0000000L
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE_MASK                    0x00000007L
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK           0xffffffffL
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK           0x00000007L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK           0x00000008L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE                0x00000008L
+#define RB_COPY_CONTROL__CLEAR_MASK_MASK                   0x000000f0L
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK             0xfffff000L
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK           0x000001ffL
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK           0x00000007L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK           0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR                0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK           0x000000f0L
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK             0x00000300L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK      0x00000c00L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK      0x00003000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK        0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED             0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK      0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN           0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK       0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE            0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK      0x00020000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA           0x00020000L
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK           0x00001fffL
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK           0x03ffe000L
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK                   0xffffffffL
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK       0x00000001L
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT            0x00000001L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK        0x00000002L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT             0x00000002L
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK       0xffffffffL
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK       0x00000001L
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE            0x00000001L
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK           0x00000006L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK              0x00000008L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM                   0x00000008L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH      0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK      0x00000020L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP           0x00000020L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK      0x00000040L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP           0x00000040L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK             0x00000080L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE                  0x00000080L
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK              0x00001f00L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK              0x00004000L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE                   0x00004000L
+#define RB_BC_CONTROL__CRC_MODE_MASK                       0x00008000L
+#define RB_BC_CONTROL__CRC_MODE                            0x00008000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK        0x00010000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS             0x00010000L
+#define RB_BC_CONTROL__DISABLE_ACCUM_MASK                  0x00020000L
+#define RB_BC_CONTROL__DISABLE_ACCUM                       0x00020000L
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK               0x003c0000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK      0x00400000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE           0x00400000L
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK          0x07800000L
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK      0x18000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK  0x20000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE       0x20000000L
+#define RB_BC_CONTROL__CRC_SYSTEM_MASK                     0x40000000L
+#define RB_BC_CONTROL__CRC_SYSTEM                          0x40000000L
+#define RB_BC_CONTROL__RESERVED6_MASK                      0x80000000L
+#define RB_BC_CONTROL__RESERVED6                           0x80000000L
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE_MASK                     0x0000000fL
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK             0x00000030L
+#define RB_EDRAM_INFO__EDRAM_RANGE_MASK                    0xffffc000L
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA_MASK                      0xffffffffL
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK                0x00000001L
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE                     0x00000001L
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK_MASK                         0xffffffffL
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK               0xffffffffL
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK               0xffffffffL
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK             0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL                  0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK             0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL                  0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK             0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL                  0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK             0x00000008L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL                  0x00000008L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK            0x00000010L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL                 0x00000010L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK            0x00000020L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL                 0x00000020L
+#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK                     0x00000040L
+#define RB_DEBUG_0__RDREQ_Z1_FULL                          0x00000040L
+#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK                     0x00000080L
+#define RB_DEBUG_0__RDREQ_Z0_FULL                          0x00000080L
+#define RB_DEBUG_0__RDREQ_C1_FULL_MASK                     0x00000100L
+#define RB_DEBUG_0__RDREQ_C1_FULL                          0x00000100L
+#define RB_DEBUG_0__RDREQ_C0_FULL_MASK                     0x00000200L
+#define RB_DEBUG_0__RDREQ_C0_FULL                          0x00000200L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK            0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL                 0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK            0x00000800L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL                 0x00000800L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK            0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL                 0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK            0x00002000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL                 0x00002000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK                0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL                     0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK                0x00008000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL                     0x00008000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK                     0x00010000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL                          0x00010000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK                     0x00020000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL                          0x00020000L
+#define RB_DEBUG_0__WRREQ_C1_FULL_MASK                     0x00040000L
+#define RB_DEBUG_0__WRREQ_C1_FULL                          0x00040000L
+#define RB_DEBUG_0__WRREQ_C0_FULL_MASK                     0x00080000L
+#define RB_DEBUG_0__WRREQ_C0_FULL                          0x00080000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK              0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL                   0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK              0x00200000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL                   0x00200000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK              0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL                   0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK              0x00800000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL                   0x00800000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK           0x01000000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL                0x01000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK           0x02000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL                0x02000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL_MASK                     0x04000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL                          0x04000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL_MASK                     0x08000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL                          0x08000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK                    0x10000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL                         0x10000000L
+#define RB_DEBUG_0__C_REQ_FULL_MASK                        0x20000000L
+#define RB_DEBUG_0__C_REQ_FULL                             0x20000000L
+#define RB_DEBUG_0__C_MASK_FULL_MASK                       0x40000000L
+#define RB_DEBUG_0__C_MASK_FULL                            0x40000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK                   0x80000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL                        0x80000000L
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK                0x00000001L
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY                     0x00000001L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK                0x00000002L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY                     0x00000002L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK                0x00000004L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY                     0x00000004L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK                0x00000008L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY                     0x00000008L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK           0x00000010L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY                0x00000010L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK           0x00000020L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY                0x00000020L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK                    0x00000040L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY                         0x00000040L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK                    0x00000080L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY                         0x00000080L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK                    0x00000100L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY                         0x00000100L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK                    0x00000200L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY                         0x00000200L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK           0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY                0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK           0x00000800L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY                0x00000800L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK           0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY                0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK           0x00002000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY                0x00002000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK               0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY                    0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK               0x00008000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY                    0x00008000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK                    0x00010000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY                         0x00010000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK                    0x00020000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY                         0x00020000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK                0x00040000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY                     0x00040000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK                0x00080000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY                     0x00080000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK             0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY                  0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY                  0x00200000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY                  0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK             0x00800000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY                  0x00800000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK          0x01000000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY               0x01000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK          0x02000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY               0x02000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK                    0x04000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY                         0x04000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK                    0x08000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY                         0x08000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK                   0x10000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY                        0x10000000L
+#define RB_DEBUG_1__C_REQ_EMPTY_MASK                       0x20000000L
+#define RB_DEBUG_1__C_REQ_EMPTY                            0x20000000L
+#define RB_DEBUG_1__C_MASK_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_1__C_MASK_EMPTY                           0x40000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK                  0x80000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY                       0x80000000L
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK                   0x0000000fL
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK                 0x000007f0L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK                   0x00000800L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG                        0x00000800L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK                 0x00001000L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG                      0x00001000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK                0x00002000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT                     0x00002000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK                   0x00004000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL                        0x00004000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK                0x00008000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL                     0x00008000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK                0x00010000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL                     0x00010000L
+#define RB_DEBUG_2__Z0_MASK_FULL_MASK                      0x00020000L
+#define RB_DEBUG_2__Z0_MASK_FULL                           0x00020000L
+#define RB_DEBUG_2__Z1_MASK_FULL_MASK                      0x00040000L
+#define RB_DEBUG_2__Z1_MASK_FULL                           0x00040000L
+#define RB_DEBUG_2__Z0_REQ_FULL_MASK                       0x00080000L
+#define RB_DEBUG_2__Z0_REQ_FULL                            0x00080000L
+#define RB_DEBUG_2__Z1_REQ_FULL_MASK                       0x00100000L
+#define RB_DEBUG_2__Z1_REQ_FULL                            0x00100000L
+#define RB_DEBUG_2__Z_SAMP_FULL_MASK                       0x00200000L
+#define RB_DEBUG_2__Z_SAMP_FULL                            0x00200000L
+#define RB_DEBUG_2__Z_TILE_FULL_MASK                       0x00400000L
+#define RB_DEBUG_2__Z_TILE_FULL                            0x00400000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK                  0x00800000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY                       0x00800000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK               0x01000000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY                    0x01000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK               0x02000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY                    0x02000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK                     0x04000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY                          0x04000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK                     0x08000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY                          0x08000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK                      0x10000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY                           0x10000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK                      0x20000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY                           0x20000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY                           0x40000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY_MASK                      0x80000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY                           0x80000000L
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID_MASK                       0x0000000fL
+#define RB_DEBUG_3__ACCUM_FLUSHING_MASK                    0x000000f0L
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK           0x00003f00L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK             0x00004000L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID                  0x00004000L
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK               0x00078000L
+#define RB_DEBUG_3__SHD_FULL_MASK                          0x00080000L
+#define RB_DEBUG_3__SHD_FULL                               0x00080000L
+#define RB_DEBUG_3__SHD_EMPTY_MASK                         0x00100000L
+#define RB_DEBUG_3__SHD_EMPTY                              0x00100000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY                  0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY                  0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK              0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL                   0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK              0x01000000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL                   0x01000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK                  0x02000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY                       0x02000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK                  0x04000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY                       0x04000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK                   0x08000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL                        0x08000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK                   0x10000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL                        0x10000000L
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK               0x00000001L
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG                    0x00000001L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK               0x00000002L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG                    0x00000002L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK             0x00000004L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG                  0x00000004L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK             0x00000008L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG                  0x00000008L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK             0x00000010L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY                  0x00000010L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK            0x00000020L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY                 0x00000020L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK              0x00000040L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL                   0x00000040L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK             0x00000080L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL                  0x00000080L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK       0x00000100L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW            0x00000100L
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK               0x00001e00L
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK             0x00000001L
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR                  0x00000001L
+
+// RB_BC_SPARES
+#define RB_BC_SPARES__RESERVED_MASK                        0xffffffffL
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP   0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK     0x00000600L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h
new file mode 100644
index 000000000000..ec7c7e126612
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h
@@ -0,0 +1,590 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _yamato_OFFSET_HEADER
+#define _yamato_OFFSET_HEADER
+
+// Registers from PA block
+
+#define mmPA_CL_VPORT_XSCALE           0x210F
+#define mmPA_CL_VPORT_XOFFSET          0x2110
+#define mmPA_CL_VPORT_YSCALE           0x2111
+#define mmPA_CL_VPORT_YOFFSET          0x2112
+#define mmPA_CL_VPORT_ZSCALE           0x2113
+#define mmPA_CL_VPORT_ZOFFSET          0x2114
+#define mmPA_CL_VTE_CNTL               0x2206
+#define mmPA_CL_CLIP_CNTL              0x2204
+#define mmPA_CL_GB_VERT_CLIP_ADJ       0x2303
+#define mmPA_CL_GB_VERT_DISC_ADJ       0x2304
+#define mmPA_CL_GB_HORZ_CLIP_ADJ       0x2305
+#define mmPA_CL_GB_HORZ_DISC_ADJ       0x2306
+#define mmPA_CL_ENHANCE                0x0C85
+#define mmPA_SC_ENHANCE                0x0CA5
+#define mmPA_SU_VTX_CNTL               0x2302
+#define mmPA_SU_POINT_SIZE             0x2280
+#define mmPA_SU_POINT_MINMAX           0x2281
+#define mmPA_SU_LINE_CNTL              0x2282
+#define mmPA_SU_FACE_DATA              0x0C86
+#define mmPA_SU_SC_MODE_CNTL           0x2205
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383
+#define mmPA_SU_PERFCOUNTER0_SELECT    0x0C88
+#define mmPA_SU_PERFCOUNTER1_SELECT    0x0C89
+#define mmPA_SU_PERFCOUNTER2_SELECT    0x0C8A
+#define mmPA_SU_PERFCOUNTER3_SELECT    0x0C8B
+#define mmPA_SU_PERFCOUNTER0_LOW       0x0C8C
+#define mmPA_SU_PERFCOUNTER0_HI        0x0C8D
+#define mmPA_SU_PERFCOUNTER1_LOW       0x0C8E
+#define mmPA_SU_PERFCOUNTER1_HI        0x0C8F
+#define mmPA_SU_PERFCOUNTER2_LOW       0x0C90
+#define mmPA_SU_PERFCOUNTER2_HI        0x0C91
+#define mmPA_SU_PERFCOUNTER3_LOW       0x0C92
+#define mmPA_SU_PERFCOUNTER3_HI        0x0C93
+#define mmPA_SC_WINDOW_OFFSET          0x2080
+#define mmPA_SC_AA_CONFIG              0x2301
+#define mmPA_SC_AA_MASK                0x2312
+#define mmPA_SC_LINE_STIPPLE           0x2283
+#define mmPA_SC_LINE_CNTL              0x2300
+#define mmPA_SC_WINDOW_SCISSOR_TL      0x2081
+#define mmPA_SC_WINDOW_SCISSOR_BR      0x2082
+#define mmPA_SC_SCREEN_SCISSOR_TL      0x200E
+#define mmPA_SC_SCREEN_SCISSOR_BR      0x200F
+#define mmPA_SC_VIZ_QUERY              0x2293
+#define mmPA_SC_VIZ_QUERY_STATUS       0x0C44
+#define mmPA_SC_LINE_STIPPLE_STATE     0x0C40
+#define mmPA_SC_PERFCOUNTER0_SELECT    0x0C98
+#define mmPA_SC_PERFCOUNTER0_LOW       0x0C99
+#define mmPA_SC_PERFCOUNTER0_HI        0x0C9A
+#define mmPA_CL_CNTL_STATUS            0x0C84
+#define mmPA_SU_CNTL_STATUS            0x0C94
+#define mmPA_SC_CNTL_STATUS            0x0CA4
+#define mmPA_SU_DEBUG_CNTL             0x0C80
+#define mmPA_SU_DEBUG_DATA             0x0C81
+#define mmPA_SC_DEBUG_CNTL             0x0C82
+#define mmPA_SC_DEBUG_DATA             0x0C83
+
+
+// Registers from VGT block
+
+#define mmGFX_COPY_STATE               0x21F4
+#define mmVGT_DRAW_INITIATOR           0x21FC
+#define mmVGT_EVENT_INITIATOR          0x21F9
+#define mmVGT_DMA_BASE                 0x21FA
+#define mmVGT_DMA_SIZE                 0x21FB
+#define mmVGT_BIN_BASE                 0x21FE
+#define mmVGT_BIN_SIZE                 0x21FF
+#define mmVGT_CURRENT_BIN_ID_MIN       0x2207
+#define mmVGT_CURRENT_BIN_ID_MAX       0x2203
+#define mmVGT_IMMED_DATA               0x21FD
+#define mmVGT_MAX_VTX_INDX             0x2100
+#define mmVGT_MIN_VTX_INDX             0x2101
+#define mmVGT_INDX_OFFSET              0x2102
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL  0x2316
+#define mmVGT_OUT_DEALLOC_CNTL         0x2317
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103
+#define mmVGT_ENHANCE                  0x2294
+#define mmVGT_VTX_VECT_EJECT_REG       0x0C2C
+#define mmVGT_LAST_COPY_STATE          0x0C30
+#define mmVGT_DEBUG_CNTL               0x0C38
+#define mmVGT_DEBUG_DATA               0x0C39
+#define mmVGT_CNTL_STATUS              0x0C3C
+#define mmVGT_CRC_SQ_DATA              0x0C3A
+#define mmVGT_CRC_SQ_CTRL              0x0C3B
+#define mmVGT_PERFCOUNTER0_SELECT      0x0C48
+#define mmVGT_PERFCOUNTER1_SELECT      0x0C49
+#define mmVGT_PERFCOUNTER2_SELECT      0x0C4A
+#define mmVGT_PERFCOUNTER3_SELECT      0x0C4B
+#define mmVGT_PERFCOUNTER0_LOW         0x0C4C
+#define mmVGT_PERFCOUNTER1_LOW         0x0C4E
+#define mmVGT_PERFCOUNTER2_LOW         0x0C50
+#define mmVGT_PERFCOUNTER3_LOW         0x0C52
+#define mmVGT_PERFCOUNTER0_HI          0x0C4D
+#define mmVGT_PERFCOUNTER1_HI          0x0C4F
+#define mmVGT_PERFCOUNTER2_HI          0x0C51
+#define mmVGT_PERFCOUNTER3_HI          0x0C53
+
+
+// Registers from TP block
+
+#define mmTC_CNTL_STATUS               0x0E00
+#define mmTCR_CHICKEN                  0x0E02
+#define mmTCF_CHICKEN                  0x0E03
+#define mmTCM_CHICKEN                  0x0E04
+#define mmTCR_PERFCOUNTER0_SELECT      0x0E05
+#define mmTCR_PERFCOUNTER1_SELECT      0x0E08
+#define mmTCR_PERFCOUNTER0_HI          0x0E06
+#define mmTCR_PERFCOUNTER1_HI          0x0E09
+#define mmTCR_PERFCOUNTER0_LOW         0x0E07
+#define mmTCR_PERFCOUNTER1_LOW         0x0E0A
+#define mmTP_TC_CLKGATE_CNTL           0x0E17
+#define mmTPC_CNTL_STATUS              0x0E18
+#define mmTPC_DEBUG0                   0x0E19
+#define mmTPC_DEBUG1                   0x0E1A
+#define mmTPC_CHICKEN                  0x0E1B
+#define mmTP0_CNTL_STATUS              0x0E1C
+#define mmTP0_DEBUG                    0x0E1D
+#define mmTP0_CHICKEN                  0x0E1E
+#define mmTP0_PERFCOUNTER0_SELECT      0x0E1F
+#define mmTP0_PERFCOUNTER0_HI          0x0E20
+#define mmTP0_PERFCOUNTER0_LOW         0x0E21
+#define mmTP0_PERFCOUNTER1_SELECT      0x0E22
+#define mmTP0_PERFCOUNTER1_HI          0x0E23
+#define mmTP0_PERFCOUNTER1_LOW         0x0E24
+#define mmTCM_PERFCOUNTER0_SELECT      0x0E54
+#define mmTCM_PERFCOUNTER1_SELECT      0x0E57
+#define mmTCM_PERFCOUNTER0_HI          0x0E55
+#define mmTCM_PERFCOUNTER1_HI          0x0E58
+#define mmTCM_PERFCOUNTER0_LOW         0x0E56
+#define mmTCM_PERFCOUNTER1_LOW         0x0E59
+#define mmTCF_PERFCOUNTER0_SELECT      0x0E5A
+#define mmTCF_PERFCOUNTER1_SELECT      0x0E5D
+#define mmTCF_PERFCOUNTER2_SELECT      0x0E60
+#define mmTCF_PERFCOUNTER3_SELECT      0x0E63
+#define mmTCF_PERFCOUNTER4_SELECT      0x0E66
+#define mmTCF_PERFCOUNTER5_SELECT      0x0E69
+#define mmTCF_PERFCOUNTER6_SELECT      0x0E6C
+#define mmTCF_PERFCOUNTER7_SELECT      0x0E6F
+#define mmTCF_PERFCOUNTER8_SELECT      0x0E72
+#define mmTCF_PERFCOUNTER9_SELECT      0x0E75
+#define mmTCF_PERFCOUNTER10_SELECT     0x0E78
+#define mmTCF_PERFCOUNTER11_SELECT     0x0E7B
+#define mmTCF_PERFCOUNTER0_HI          0x0E5B
+#define mmTCF_PERFCOUNTER1_HI          0x0E5E
+#define mmTCF_PERFCOUNTER2_HI          0x0E61
+#define mmTCF_PERFCOUNTER3_HI          0x0E64
+#define mmTCF_PERFCOUNTER4_HI          0x0E67
+#define mmTCF_PERFCOUNTER5_HI          0x0E6A
+#define mmTCF_PERFCOUNTER6_HI          0x0E6D
+#define mmTCF_PERFCOUNTER7_HI          0x0E70
+#define mmTCF_PERFCOUNTER8_HI          0x0E73
+#define mmTCF_PERFCOUNTER9_HI          0x0E76
+#define mmTCF_PERFCOUNTER10_HI         0x0E79
+#define mmTCF_PERFCOUNTER11_HI         0x0E7C
+#define mmTCF_PERFCOUNTER0_LOW         0x0E5C
+#define mmTCF_PERFCOUNTER1_LOW         0x0E5F
+#define mmTCF_PERFCOUNTER2_LOW         0x0E62
+#define mmTCF_PERFCOUNTER3_LOW         0x0E65
+#define mmTCF_PERFCOUNTER4_LOW         0x0E68
+#define mmTCF_PERFCOUNTER5_LOW         0x0E6B
+#define mmTCF_PERFCOUNTER6_LOW         0x0E6E
+#define mmTCF_PERFCOUNTER7_LOW         0x0E71
+#define mmTCF_PERFCOUNTER8_LOW         0x0E74
+#define mmTCF_PERFCOUNTER9_LOW         0x0E77
+#define mmTCF_PERFCOUNTER10_LOW        0x0E7A
+#define mmTCF_PERFCOUNTER11_LOW        0x0E7D
+#define mmTCF_DEBUG                    0x0EC0
+#define mmTCA_FIFO_DEBUG               0x0EC1
+#define mmTCA_PROBE_DEBUG              0x0EC2
+#define mmTCA_TPC_DEBUG                0x0EC3
+#define mmTCB_CORE_DEBUG               0x0EC4
+#define mmTCB_TAG0_DEBUG               0x0EC5
+#define mmTCB_TAG1_DEBUG               0x0EC6
+#define mmTCB_TAG2_DEBUG               0x0EC7
+#define mmTCB_TAG3_DEBUG               0x0EC8
+#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9
+#define mmTCB_FETCH_GEN_WALKER_DEBUG   0x0ECB
+#define mmTCB_FETCH_GEN_PIPE0_DEBUG    0x0ECC
+#define mmTCD_INPUT0_DEBUG             0x0ED0
+#define mmTCD_DEGAMMA_DEBUG            0x0ED4
+#define mmTCD_DXTMUX_SCTARB_DEBUG      0x0ED5
+#define mmTCD_DXTC_ARB_DEBUG           0x0ED6
+#define mmTCD_STALLS_DEBUG             0x0ED7
+#define mmTCO_STALLS_DEBUG             0x0EE0
+#define mmTCO_QUAD0_DEBUG0             0x0EE1
+#define mmTCO_QUAD0_DEBUG1             0x0EE2
+
+
+// Registers from TC block
+
+
+
+// Registers from SQ block
+
+#define mmSQ_GPR_MANAGEMENT            0x0D00
+#define mmSQ_FLOW_CONTROL              0x0D01
+#define mmSQ_INST_STORE_MANAGMENT      0x0D02
+#define mmSQ_RESOURCE_MANAGMENT        0x0D03
+#define mmSQ_EO_RT                     0x0D04
+#define mmSQ_DEBUG_MISC                0x0D05
+#define mmSQ_ACTIVITY_METER_CNTL       0x0D06
+#define mmSQ_ACTIVITY_METER_STATUS     0x0D07
+#define mmSQ_INPUT_ARB_PRIORITY        0x0D08
+#define mmSQ_THREAD_ARB_PRIORITY       0x0D09
+#define mmSQ_VS_WATCHDOG_TIMER         0x0D0A
+#define mmSQ_PS_WATCHDOG_TIMER         0x0D0B
+#define mmSQ_INT_CNTL                  0x0D34
+#define mmSQ_INT_STATUS                0x0D35
+#define mmSQ_INT_ACK                   0x0D36
+#define mmSQ_DEBUG_INPUT_FSM           0x0DAE
+#define mmSQ_DEBUG_CONST_MGR_FSM       0x0DAF
+#define mmSQ_DEBUG_TP_FSM              0x0DB0
+#define mmSQ_DEBUG_FSM_ALU_0           0x0DB1
+#define mmSQ_DEBUG_FSM_ALU_1           0x0DB2
+#define mmSQ_DEBUG_EXP_ALLOC           0x0DB3
+#define mmSQ_DEBUG_PTR_BUFF            0x0DB4
+#define mmSQ_DEBUG_GPR_VTX             0x0DB5
+#define mmSQ_DEBUG_GPR_PIX             0x0DB6
+#define mmSQ_DEBUG_TB_STATUS_SEL       0x0DB7
+#define mmSQ_DEBUG_VTX_TB_0            0x0DB8
+#define mmSQ_DEBUG_VTX_TB_1            0x0DB9
+#define mmSQ_DEBUG_VTX_TB_STATUS_REG   0x0DBA
+#define mmSQ_DEBUG_VTX_TB_STATE_MEM    0x0DBB
+#define mmSQ_DEBUG_PIX_TB_0            0x0DBC
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0
+#define mmSQ_DEBUG_PIX_TB_STATE_MEM    0x0DC1
+#define mmSQ_PERFCOUNTER0_SELECT       0x0DC8
+#define mmSQ_PERFCOUNTER1_SELECT       0x0DC9
+#define mmSQ_PERFCOUNTER2_SELECT       0x0DCA
+#define mmSQ_PERFCOUNTER3_SELECT       0x0DCB
+#define mmSQ_PERFCOUNTER0_LOW          0x0DCC
+#define mmSQ_PERFCOUNTER0_HI           0x0DCD
+#define mmSQ_PERFCOUNTER1_LOW          0x0DCE
+#define mmSQ_PERFCOUNTER1_HI           0x0DCF
+#define mmSQ_PERFCOUNTER2_LOW          0x0DD0
+#define mmSQ_PERFCOUNTER2_HI           0x0DD1
+#define mmSQ_PERFCOUNTER3_LOW          0x0DD2
+#define mmSQ_PERFCOUNTER3_HI           0x0DD3
+#define mmSX_PERFCOUNTER0_SELECT       0x0DD4
+#define mmSX_PERFCOUNTER0_LOW          0x0DD8
+#define mmSX_PERFCOUNTER0_HI           0x0DD9
+#define mmSQ_INSTRUCTION_ALU_0         0x5000
+#define mmSQ_INSTRUCTION_ALU_1         0x5001
+#define mmSQ_INSTRUCTION_ALU_2         0x5002
+#define mmSQ_INSTRUCTION_CF_EXEC_0     0x5080
+#define mmSQ_INSTRUCTION_CF_EXEC_1     0x5081
+#define mmSQ_INSTRUCTION_CF_EXEC_2     0x5082
+#define mmSQ_INSTRUCTION_CF_LOOP_0     0x5083
+#define mmSQ_INSTRUCTION_CF_LOOP_1     0x5084
+#define mmSQ_INSTRUCTION_CF_LOOP_2     0x5085
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088
+#define mmSQ_INSTRUCTION_CF_ALLOC_0    0x5089
+#define mmSQ_INSTRUCTION_CF_ALLOC_1    0x508A
+#define mmSQ_INSTRUCTION_CF_ALLOC_2    0x508B
+#define mmSQ_INSTRUCTION_TFETCH_0      0x5043
+#define mmSQ_INSTRUCTION_TFETCH_1      0x5044
+#define mmSQ_INSTRUCTION_TFETCH_2      0x5045
+#define mmSQ_INSTRUCTION_VFETCH_0      0x5040
+#define mmSQ_INSTRUCTION_VFETCH_1      0x5041
+#define mmSQ_INSTRUCTION_VFETCH_2      0x5042
+#define mmSQ_CONSTANT_0                0x4000
+#define mmSQ_CONSTANT_1                0x4001
+#define mmSQ_CONSTANT_2                0x4002
+#define mmSQ_CONSTANT_3                0x4003
+#define mmSQ_FETCH_0                   0x4800
+#define mmSQ_FETCH_1                   0x4801
+#define mmSQ_FETCH_2                   0x4802
+#define mmSQ_FETCH_3                   0x4803
+#define mmSQ_FETCH_4                   0x4804
+#define mmSQ_FETCH_5                   0x4805
+#define mmSQ_CONSTANT_VFETCH_0         0x4806
+#define mmSQ_CONSTANT_VFETCH_1         0x4808
+#define mmSQ_CONSTANT_T2               0x480C
+#define mmSQ_CONSTANT_T3               0x4812
+#define mmSQ_CF_BOOLEANS               0x4900
+#define mmSQ_CF_LOOP                   0x4908
+#define mmSQ_CONSTANT_RT_0             0x4940
+#define mmSQ_CONSTANT_RT_1             0x4941
+#define mmSQ_CONSTANT_RT_2             0x4942
+#define mmSQ_CONSTANT_RT_3             0x4943
+#define mmSQ_FETCH_RT_0                0x4D40
+#define mmSQ_FETCH_RT_1                0x4D41
+#define mmSQ_FETCH_RT_2                0x4D42
+#define mmSQ_FETCH_RT_3                0x4D43
+#define mmSQ_FETCH_RT_4                0x4D44
+#define mmSQ_FETCH_RT_5                0x4D45
+#define mmSQ_CF_RT_BOOLEANS            0x4E00
+#define mmSQ_CF_RT_LOOP                0x4E14
+#define mmSQ_VS_PROGRAM                0x21F7
+#define mmSQ_PS_PROGRAM                0x21F6
+#define mmSQ_CF_PROGRAM_SIZE           0x2315
+#define mmSQ_INTERPOLATOR_CNTL         0x2182
+#define mmSQ_PROGRAM_CNTL              0x2180
+#define mmSQ_WRAPPING_0                0x2183
+#define mmSQ_WRAPPING_1                0x2184
+#define mmSQ_VS_CONST                  0x2307
+#define mmSQ_PS_CONST                  0x2308
+#define mmSQ_CONTEXT_MISC              0x2181
+#define mmSQ_CF_RD_BASE                0x21F5
+#define mmSQ_DEBUG_MISC_0              0x2309
+#define mmSQ_DEBUG_MISC_1              0x230A
+
+
+// Registers from SX block
+
+
+
+// Registers from MH block
+
+#define mmMH_ARBITER_CONFIG            0x0A40
+#define mmMH_CLNT_AXI_ID_REUSE         0x0A41
+#define mmMH_INTERRUPT_MASK            0x0A42
+#define mmMH_INTERRUPT_STATUS          0x0A43
+#define mmMH_INTERRUPT_CLEAR           0x0A44
+#define mmMH_AXI_ERROR                 0x0A45
+#define mmMH_PERFCOUNTER0_SELECT       0x0A46
+#define mmMH_PERFCOUNTER1_SELECT       0x0A4A
+#define mmMH_PERFCOUNTER0_CONFIG       0x0A47
+#define mmMH_PERFCOUNTER1_CONFIG       0x0A4B
+#define mmMH_PERFCOUNTER0_LOW          0x0A48
+#define mmMH_PERFCOUNTER1_LOW          0x0A4C
+#define mmMH_PERFCOUNTER0_HI           0x0A49
+#define mmMH_PERFCOUNTER1_HI           0x0A4D
+#define mmMH_DEBUG_CTRL                0x0A4E
+#define mmMH_DEBUG_DATA                0x0A4F
+#define mmMH_AXI_HALT_CONTROL          0x0A50
+#define mmMH_MMU_CONFIG                0x0040
+#define mmMH_MMU_VA_RANGE              0x0041
+#define mmMH_MMU_PT_BASE               0x0042
+#define mmMH_MMU_PAGE_FAULT            0x0043
+#define mmMH_MMU_TRAN_ERROR            0x0044
+#define mmMH_MMU_INVALIDATE            0x0045
+#define mmMH_MMU_MPU_BASE              0x0046
+#define mmMH_MMU_MPU_END               0x0047
+
+
+// Registers from RBBM block
+
+#define mmWAIT_UNTIL                   0x05C8
+#define mmRBBM_ISYNC_CNTL              0x05C9
+#define mmRBBM_STATUS                  0x05D0
+#define mmRBBM_DSPLY                   0x0391
+#define mmRBBM_RENDER_LATEST           0x0392
+#define mmRBBM_RTL_RELEASE             0x0000
+#define mmRBBM_PATCH_RELEASE           0x0001
+#define mmRBBM_AUXILIARY_CONFIG        0x0002
+#define mmRBBM_PERIPHID0               0x03F8
+#define mmRBBM_PERIPHID1               0x03F9
+#define mmRBBM_PERIPHID2               0x03FA
+#define mmRBBM_PERIPHID3               0x03FB
+#define mmRBBM_CNTL                    0x003B
+#define mmRBBM_SKEW_CNTL               0x003D
+#define mmRBBM_SOFT_RESET              0x003C
+#define mmRBBM_PM_OVERRIDE1            0x039C
+#define mmRBBM_PM_OVERRIDE2            0x039D
+#define mmGC_SYS_IDLE                  0x039E
+#define mmNQWAIT_UNTIL                 0x0394
+#define mmRBBM_DEBUG_OUT               0x03A0
+#define mmRBBM_DEBUG_CNTL              0x03A1
+#define mmRBBM_DEBUG                   0x039B
+#define mmRBBM_READ_ERROR              0x03B3
+#define mmRBBM_WAIT_IDLE_CLOCKS        0x03B2
+#define mmRBBM_INT_CNTL                0x03B4
+#define mmRBBM_INT_STATUS              0x03B5
+#define mmRBBM_INT_ACK                 0x03B6
+#define mmMASTER_INT_SIGNAL            0x03B7
+#define mmRBBM_PERFCOUNTER1_SELECT     0x0395
+#define mmRBBM_PERFCOUNTER1_LO         0x0397
+#define mmRBBM_PERFCOUNTER1_HI         0x0398
+
+
+// Registers from CP block
+
+#define mmCP_RB_BASE                   0x01C0
+#define mmCP_RB_CNTL                   0x01C1
+#define mmCP_RB_RPTR_ADDR              0x01C3
+#define mmCP_RB_RPTR                   0x01C4
+#define mmCP_RB_RPTR_WR                0x01C7
+#define mmCP_RB_WPTR                   0x01C5
+#define mmCP_RB_WPTR_DELAY             0x01C6
+#define mmCP_RB_WPTR_BASE              0x01C8
+#define mmCP_IB1_BASE                  0x0458
+#define mmCP_IB1_BUFSZ                 0x0459
+#define mmCP_IB2_BASE                  0x045A
+#define mmCP_IB2_BUFSZ                 0x045B
+#define mmCP_ST_BASE                   0x044D
+#define mmCP_ST_BUFSZ                  0x044E
+#define mmCP_QUEUE_THRESHOLDS          0x01D5
+#define mmCP_MEQ_THRESHOLDS            0x01D6
+#define mmCP_CSQ_AVAIL                 0x01D7
+#define mmCP_STQ_AVAIL                 0x01D8
+#define mmCP_MEQ_AVAIL                 0x01D9
+#define mmCP_CSQ_RB_STAT               0x01FD
+#define mmCP_CSQ_IB1_STAT              0x01FE
+#define mmCP_CSQ_IB2_STAT              0x01FF
+#define mmCP_NON_PREFETCH_CNTRS        0x0440
+#define mmCP_STQ_ST_STAT               0x0443
+#define mmCP_MEQ_STAT                  0x044F
+#define mmCP_MIU_TAG_STAT              0x0452
+#define mmCP_CMD_INDEX                 0x01DA
+#define mmCP_CMD_DATA                  0x01DB
+#define mmCP_ME_CNTL                   0x01F6
+#define mmCP_ME_STATUS                 0x01F7
+#define mmCP_ME_RAM_WADDR              0x01F8
+#define mmCP_ME_RAM_RADDR              0x01F9
+#define mmCP_ME_RAM_DATA               0x01FA
+#define mmCP_ME_RDADDR                 0x01EA
+#define mmCP_DEBUG                     0x01FC
+#define mmSCRATCH_REG0                 0x0578
+#define mmGUI_SCRATCH_REG0             0x0578
+#define mmSCRATCH_REG1                 0x0579
+#define mmGUI_SCRATCH_REG1             0x0579
+#define mmSCRATCH_REG2                 0x057A
+#define mmGUI_SCRATCH_REG2             0x057A
+#define mmSCRATCH_REG3                 0x057B
+#define mmGUI_SCRATCH_REG3             0x057B
+#define mmSCRATCH_REG4                 0x057C
+#define mmGUI_SCRATCH_REG4             0x057C
+#define mmSCRATCH_REG5                 0x057D
+#define mmGUI_SCRATCH_REG5             0x057D
+#define mmSCRATCH_REG6                 0x057E
+#define mmGUI_SCRATCH_REG6             0x057E
+#define mmSCRATCH_REG7                 0x057F
+#define mmGUI_SCRATCH_REG7             0x057F
+#define mmSCRATCH_UMSK                 0x01DC
+#define mmSCRATCH_ADDR                 0x01DD
+#define mmCP_ME_VS_EVENT_SRC           0x0600
+#define mmCP_ME_VS_EVENT_ADDR          0x0601
+#define mmCP_ME_VS_EVENT_DATA          0x0602
+#define mmCP_ME_VS_EVENT_ADDR_SWM      0x0603
+#define mmCP_ME_VS_EVENT_DATA_SWM      0x0604
+#define mmCP_ME_PS_EVENT_SRC           0x0605
+#define mmCP_ME_PS_EVENT_ADDR          0x0606
+#define mmCP_ME_PS_EVENT_DATA          0x0607
+#define mmCP_ME_PS_EVENT_ADDR_SWM      0x0608
+#define mmCP_ME_PS_EVENT_DATA_SWM      0x0609
+#define mmCP_ME_CF_EVENT_SRC           0x060A
+#define mmCP_ME_CF_EVENT_ADDR          0x060B
+#define mmCP_ME_CF_EVENT_DATA          0x060C
+#define mmCP_ME_NRT_ADDR               0x060D
+#define mmCP_ME_NRT_DATA               0x060E
+#define mmCP_ME_VS_FETCH_DONE_SRC      0x0612
+#define mmCP_ME_VS_FETCH_DONE_ADDR     0x0613
+#define mmCP_ME_VS_FETCH_DONE_DATA     0x0614
+#define mmCP_INT_CNTL                  0x01F2
+#define mmCP_INT_STATUS                0x01F3
+#define mmCP_INT_ACK                   0x01F4
+#define mmCP_PFP_UCODE_ADDR            0x00C0
+#define mmCP_PFP_UCODE_DATA            0x00C1
+#define mmCP_PERFMON_CNTL              0x0444
+#define mmCP_PERFCOUNTER_SELECT        0x0445
+#define mmCP_PERFCOUNTER_LO            0x0446
+#define mmCP_PERFCOUNTER_HI            0x0447
+#define mmCP_BIN_MASK_LO               0x0454
+#define mmCP_BIN_MASK_HI               0x0455
+#define mmCP_BIN_SELECT_LO             0x0456
+#define mmCP_BIN_SELECT_HI             0x0457
+#define mmCP_NV_FLAGS_0                0x01EE
+#define mmCP_NV_FLAGS_1                0x01EF
+#define mmCP_NV_FLAGS_2                0x01F0
+#define mmCP_NV_FLAGS_3                0x01F1
+#define mmCP_STATE_DEBUG_INDEX         0x01EC
+#define mmCP_STATE_DEBUG_DATA          0x01ED
+#define mmCP_PROG_COUNTER              0x044B
+#define mmCP_STAT                      0x047F
+#define mmBIOS_0_SCRATCH               0x0004
+#define mmBIOS_1_SCRATCH               0x0005
+#define mmBIOS_2_SCRATCH               0x0006
+#define mmBIOS_3_SCRATCH               0x0007
+#define mmBIOS_4_SCRATCH               0x0008
+#define mmBIOS_5_SCRATCH               0x0009
+#define mmBIOS_6_SCRATCH               0x000A
+#define mmBIOS_7_SCRATCH               0x000B
+#define mmBIOS_8_SCRATCH               0x0580
+#define mmBIOS_9_SCRATCH               0x0581
+#define mmBIOS_10_SCRATCH              0x0582
+#define mmBIOS_11_SCRATCH              0x0583
+#define mmBIOS_12_SCRATCH              0x0584
+#define mmBIOS_13_SCRATCH              0x0585
+#define mmBIOS_14_SCRATCH              0x0586
+#define mmBIOS_15_SCRATCH              0x0587
+#define mmCOHER_SIZE_PM4               0x0A29
+#define mmCOHER_BASE_PM4               0x0A2A
+#define mmCOHER_STATUS_PM4             0x0A2B
+#define mmCOHER_SIZE_HOST              0x0A2F
+#define mmCOHER_BASE_HOST              0x0A30
+#define mmCOHER_STATUS_HOST            0x0A31
+#define mmCOHER_DEST_BASE_0            0x2006
+#define mmCOHER_DEST_BASE_1            0x2007
+#define mmCOHER_DEST_BASE_2            0x2008
+#define mmCOHER_DEST_BASE_3            0x2009
+#define mmCOHER_DEST_BASE_4            0x200A
+#define mmCOHER_DEST_BASE_5            0x200B
+#define mmCOHER_DEST_BASE_6            0x200C
+#define mmCOHER_DEST_BASE_7            0x200D
+
+
+// Registers from SC block
+
+
+
+// Registers from BC block
+
+#define mmRB_SURFACE_INFO              0x2000
+#define mmRB_COLOR_INFO                0x2001
+#define mmRB_DEPTH_INFO                0x2002
+#define mmRB_STENCILREFMASK            0x210D
+#define mmRB_ALPHA_REF                 0x210E
+#define mmRB_COLOR_MASK                0x2104
+#define mmRB_BLEND_RED                 0x2105
+#define mmRB_BLEND_GREEN               0x2106
+#define mmRB_BLEND_BLUE                0x2107
+#define mmRB_BLEND_ALPHA               0x2108
+#define mmRB_FOG_COLOR                 0x2109
+#define mmRB_STENCILREFMASK_BF         0x210C
+#define mmRB_DEPTHCONTROL              0x2200
+#define mmRB_BLENDCONTROL              0x2201
+#define mmRB_COLORCONTROL              0x2202
+#define mmRB_MODECONTROL               0x2208
+#define mmRB_COLOR_DEST_MASK           0x2326
+#define mmRB_COPY_CONTROL              0x2318
+#define mmRB_COPY_DEST_BASE            0x2319
+#define mmRB_COPY_DEST_PITCH           0x231A
+#define mmRB_COPY_DEST_INFO            0x231B
+#define mmRB_COPY_DEST_PIXEL_OFFSET    0x231C
+#define mmRB_DEPTH_CLEAR               0x231D
+#define mmRB_SAMPLE_COUNT_CTL          0x2324
+#define mmRB_SAMPLE_COUNT_ADDR         0x2325
+#define mmRB_BC_CONTROL                0x0F01
+#define mmRB_EDRAM_INFO                0x0F02
+#define mmRB_CRC_RD_PORT               0x0F0C
+#define mmRB_CRC_CONTROL               0x0F0D
+#define mmRB_CRC_MASK                  0x0F0E
+#define mmRB_PERFCOUNTER0_SELECT       0x0F04
+#define mmRB_PERFCOUNTER0_LOW          0x0F08
+#define mmRB_PERFCOUNTER0_HI           0x0F09
+#define mmRB_TOTAL_SAMPLES             0x0F0F
+#define mmRB_ZPASS_SAMPLES             0x0F10
+#define mmRB_ZFAIL_SAMPLES             0x0F11
+#define mmRB_SFAIL_SAMPLES             0x0F12
+#define mmRB_DEBUG_0                   0x0F26
+#define mmRB_DEBUG_1                   0x0F27
+#define mmRB_DEBUG_2                   0x0F28
+#define mmRB_DEBUG_3                   0x0F29
+#define mmRB_DEBUG_4                   0x0F2A
+#define mmRB_FLAG_CONTROL              0x0F2B
+#define mmRB_BC_SPARES                 0x0F2C
+#define mmBC_DUMMY_CRAYRB_ENUMS        0x0F15
+#define mmBC_DUMMY_CRAYRB_MOREENUMS    0x0F16
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h
new file mode 100644
index 000000000000..17379dcfa0e7
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h
@@ -0,0 +1,223 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_RANDOM_HEADER)
+#define _yamato_RANDOM_HEADER
+
+/*************************************************************
+ * THIS FILE IS AUTOMATICALLY CREATED.  DO NOT EDIT THIS FILE.
+ *************************************************************/
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SU_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SC_PERFCNT_SELECT>;
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRIM_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SOURCE_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_FACENESS_CULL_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_INDEX_SIZE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SMALL_INDEX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRE_FETCH_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_GRP_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_EVENT_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DMA_SWAP_MODE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCR_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TP_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCM_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCF_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SQ_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SX_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Abs_modifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Exporting>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ScalarOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SwizzleType>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<InputModifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredicateSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect1>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VectorOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect0>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Ressource_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Instruction_serial>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VC_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressing>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CFOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Allocation_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexInstOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressmode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexCoordDenorm>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SrcSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DstSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MipFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<AnisoFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ArbitraryFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SampleLocation>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VertexMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Sample_Cntl>;
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MhPerfEncode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MmuClntBeh>;
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RBBM_PERFCOUNT1_SEL>;
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CP_PERFCOUNT_SEL>;
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareFrag>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareRef>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<StencilOp>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<BlendOpX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CombFuncX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherModeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherTypeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceEndian>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramSizeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RB_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceSwap>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumber>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceTiling>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumberX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArrayX>;
+
+#endif /*_yamato_RANDOM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h
new file mode 100644
index 000000000000..3cd315f903db
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h
@@ -0,0 +1,14292 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_REG_HEADER)
+#define _yamato_REG_HEADER
+/*
+*   yamato_registers.h
+*
+*   Register Spec Release:  Chip Spec 1.0
+*
+*
+*    (c) 2000 ATI Technologies Inc.  (unpublished)
+*
+*    All rights reserved.  This notice is intended as a precaution against
+*    inadvertent publication and does not imply publication or any waiver
+*    of confidentiality.  The year included in the foregoing notice is the
+*    year of creation of the work.
+*
+*/
+
+    union PA_CL_VPORT_XSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_XSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_XSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_XOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_XOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_XOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_YSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_YSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_YOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_YOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_ZSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_ZSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_ZOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_ZOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VTE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int                                 : 2;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                                 : 2;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CLIP_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+        unsigned int                                 : 27;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 27;
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 28;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_VTX_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PIX_CENTER : 1;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      PIX_CENTER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          HEIGHT : 16;
+        unsigned int                           WIDTH : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           WIDTH : 16;
+        unsigned int                          HEIGHT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_MINMAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_SIZE : 16;
+        unsigned int                        MAX_SIZE : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MAX_SIZE : 16;
+        unsigned int                        MIN_SIZE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           WIDTH : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                           WIDTH : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_FACE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                       BASE_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_SC_MODE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CULL_FRONT : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                            FACE : 1;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int                                 : 2;
+        unsigned int              ZERO_AREA_FACENESS : 1;
+        unsigned int                FACE_KILL_ENABLE : 1;
+        unsigned int               FACE_WRITE_ENABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               FACE_WRITE_ENABLE : 1;
+        unsigned int                FACE_KILL_ENABLE : 1;
+        unsigned int              ZERO_AREA_FACENESS : 1;
+        unsigned int                                 : 2;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int                            FACE : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                      CULL_FRONT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 WINDOW_X_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_X_OFFSET : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+        unsigned int                                 : 10;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 10;
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         AA_MASK : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                         AA_MASK : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    LINE_PATTERN : 16;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                                 : 4;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                    LINE_PATTERN : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BRES_CNTL : 8;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int                       BRES_CNTL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 1;
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VIZ_QUERY_ENA : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                                 : 1;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                   VIZ_QUERY_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STATUS_BITS : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     STATUS_BITS : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CURRENT_PTR : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int                     CURRENT_PTR : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         CL_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CL_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SU_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SU_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SC_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SU_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SU_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           clip_ga_bc_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int                     ALWAYS_ZERO : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 12;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_ga_bc_fifo_write : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int                     ALWAYS_ZERO : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 8;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO1 : 21;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO1 : 21;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO0 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 6;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO3 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO0 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 24;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            clprim_in_back_event : 1;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int     clip_priority_seq_indx_load : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int     clip_priority_seq_indx_load : 2;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int            clprim_in_back_event : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int         clprim_in_back_event_id : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         clprim_in_back_event_id : 6;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+        unsigned int                     ALWAYS_ZERO : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 28;
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clip_priority_available_vte_out_clip : 2;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clip_priority_available_vte_out_clip : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               sm0_clip_vert_cnt : 4;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int               sm0_current_state : 7;
+        unsigned int                    ALWAYS_ZERO0 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 5;
+        unsigned int               sm0_current_state : 7;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int               sm0_clip_vert_cnt : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   nan_kill_flag : 4;
+        unsigned int                position_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int           sx_pending_rd_aux_sel : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           sx_pending_rd_aux_sel : 1;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                position_address : 3;
+        unsigned int                   nan_kill_flag : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                param_cache_base : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                param_cache_base : 7;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         sx_sent : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                          sx_aux : 1;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                req_active_verts : 7;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int        sx_pending_fifo_contents : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int        sx_pending_fifo_contents : 3;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int                req_active_verts : 7;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                          sx_aux : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                         sx_sent : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    vertex_fifo_entriesavailable : 4;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int                   current_state : 2;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                   current_state : 2;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int    vertex_fifo_entriesavailable : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   su_cntl_state : 5;
+        unsigned int                     pmode_state : 6;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                       geom_busy : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       geom_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     pmode_state : 6;
+        unsigned int                   su_cntl_state : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort0_gated_17_4 : 14;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int              y_sort0_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort1_gated_17_4 : 14;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int              y_sort1_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort2_gated_17_4 : 14;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int              y_sort2_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort0_gated : 11;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                      type_gated : 3;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                       eop_gated : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                       eop_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                      type_gated : 3;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int           attr_indx_sort0_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort2_gated : 11;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int                  event_id_gated : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                  event_id_gated : 5;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int           attr_indx_sort2_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SC_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SC_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    pa_freeze_b1 : 1;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                                 : 17;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 17;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                    pa_freeze_b1 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        em_state : 3;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                                 : 21;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 21;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                        em_state : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rc_rtr_dly : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                                 : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int                        event_s1 : 1;
+        unsigned int                                 : 8;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 8;
+        unsigned int                        event_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                                 : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                      rc_rtr_dly : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       x_curr_s1 : 11;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                                 : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 9;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                       x_curr_s1 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        y_end_s1 : 14;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        x_end_s1 : 14;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      z_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                           state : 3;
+        unsigned int                   state_delayed : 3;
+        unsigned int                      data_valid : 1;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                      data_valid : 1;
+        unsigned int                   state_delayed : 3;
+        unsigned int                           state : 3;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                      z_ff_empty : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      event_flag : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                       fposition : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                           state : 2;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                                 : 6;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 6;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                           state : 2;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       fposition : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                      event_flag : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     sample_last : 1;
+        unsigned int                     sample_mask : 4;
+        unsigned int                        sample_y : 2;
+        unsigned int                        sample_x : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int                       fposition : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                                 : 3;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 3;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                       fposition : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                        sample_x : 2;
+        unsigned int                        sample_y : 2;
+        unsigned int                     sample_mask : 4;
+        unsigned int                     sample_last : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rb_sc_send : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                      mask_state : 2;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_ready : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int                      mask_ready : 1;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_state : 2;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                      rb_sc_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            combined_sample_mask : 16;
+        unsigned int                                 : 15;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 15;
+        unsigned int            combined_sample_mask : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            ez_sample_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_event : 1;
+        unsigned int                      next_state : 3;
+        unsigned int                           state : 3;
+        unsigned int                           stall : 1;
+        unsigned int                                 : 16;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 16;
+        unsigned int                           stall : 1;
+        unsigned int                           state : 3;
+        unsigned int                      next_state : 3;
+        unsigned int               packer_send_event : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int            ez_sample_data_ready : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SQ_iterator_free_buff : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                                 : 7;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 7;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int           SQ_iterator_free_buff : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GFX_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DRAW_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       PRIM_TYPE : 6;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int            FACENESS_CULL_SELECT : 2;
+        unsigned int                                 : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int                     NUM_INDICES : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     NUM_INDICES : 16;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int            FACENESS_CULL_SELECT : 2;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int                       PRIM_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_EVENT_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EVENT_TYPE : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      EVENT_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                       SWAP_MODE : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SWAP_MODE : 2;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                  FACENESS_FETCH : 1;
+        unsigned int                  FACENESS_RESET : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  FACENESS_RESET : 1;
+        unsigned int                  FACENESS_FETCH : 1;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MIN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_IMMED_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MAX_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MAX_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MAX_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MIN_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MIN_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_INDX_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INDX_OFFSET : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                     INDX_OFFSET : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VERTEX_REUSE_BLOCK_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_OUT_DEALLOC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEALLOC_DIST : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    DEALLOC_DIST : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MULTI_PRIM_IB_RESET_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESET_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      RESET_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            MISC : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                            MISC : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VTX_VECT_EJECT_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PRIM_COUNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                      PRIM_COUNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_LAST_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VGT_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                  VGT_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     te_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     te_grp_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                out_te_data_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_te_data_read : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      vgt_clk_en : 1;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                      vgt_clk_en : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int                      read_block : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int                   selected_data : 8;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                           gap_q : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int                     grp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     grp_trigger : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int                           gap_q : 1;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                   selected_data : 8;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int                      read_block : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     save_read_q : 1;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                     save_read_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            prim_side_indx_valid : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                       hold_prim : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int                       hold_prim : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int            prim_side_indx_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       null_terminate_vtx_vector : 1;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int                    new_packet_q : 1;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int                                 : 4;
+        unsigned int                     out_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 4;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int                    new_packet_q : 1;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int       null_terminate_vtx_vector : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   L2_INVALIDATE : 1;
+        unsigned int                                 : 17;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 11;
+        unsigned int                         TC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 11;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 17;
+        unsigned int                   L2_INVALIDATE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int                           SPARE : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 23;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP_TC_CLKGATE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TP_BUSY_EXTEND : 3;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                  TP_BUSY_EXTEND : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TPC_INPUT_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int                        TPC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int                  TPC_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        LOD_CNTL : 2;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                                 : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                    SQ_TP_WAKEUP : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SQ_TP_WAKEUP : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                                 : 3;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 1;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                        LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          UNUSED : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                          UNUSED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 BLEND_PRECISION : 1;
+        unsigned int                           SPARE : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 31;
+        unsigned int                 BLEND_PRECISION : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TP_INPUT_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                         TP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TP_BUSY : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                   TP_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      Q_LOD_CNTL : 2;
+        unsigned int                                 : 1;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int                                 : 1;
+        unsigned int                      Q_LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TT_MODE : 1;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                           SPARE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 30;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                         TT_MODE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 6;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TPC_full : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                         tca_rts : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                         tca_rts : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                        TPC_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                                 : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_FIFO_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        tp0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tpc_full : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                        tpc_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tp0_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_PROBE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               ProbeFilter_stall : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int               ProbeFilter_stall : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_TPC_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                                 : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 18;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_CORE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       access512 : 1;
+        unsigned int                           tiled : 1;
+        unsigned int                                 : 2;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 1;
+        unsigned int                          format : 6;
+        unsigned int                                 : 2;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 3;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 3;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 2;
+        unsigned int                          format : 6;
+        unsigned int                                 : 1;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 2;
+        unsigned int                           tiled : 1;
+        unsigned int                       access512 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG1_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG2_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG3_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       left_done : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int                     update_left : 1;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int                    valid_left_q : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    valid_left_q : 1;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int                     update_left : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int                       left_done : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_WALKER_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                                 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                            busy : 1;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                            busy : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                                 : 3;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_PIPE0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     tc0_arb_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                            busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         valid_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                         valid_q : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                            busy : 1;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                     tc0_arb_rts : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_INPUT0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                                 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DEGAMMA_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTMUX_SCTARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 9;
+        unsigned int                          pstate : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int                                 : 3;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 6;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                                 : 6;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 3;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int                                 : 3;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                                 : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTC_ARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                        n0_stall : 1;
+        unsigned int                          pstate : 1;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int                 n0_dxt2_4_types : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 n0_dxt2_4_types : 1;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                        n0_stall : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 10;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_incoming_rtr : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                not_incoming_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int                                 : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             rl_sg_sector_format : 8;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                                 : 2;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int                            busy : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            busy : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 2;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int             rl_sg_sector_format : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       fifo_busy : 1;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                    write_enable : 1;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                                 : 2;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int                                 : 2;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                    write_enable : 1;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                       fifo_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_GPR_MANAGEMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     REG_DYNAMIC : 1;
+        unsigned int                                 : 3;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 3;
+        unsigned int                     REG_DYNAMIC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FLOW_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+        unsigned int                                 : 2;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 2;
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INST_STORE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   INST_BASE_PIX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_PIX : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_RESOURCE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_EO_RT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 EO_CONSTANTS_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                 EO_CONSTANTS_RT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  DB_ALUCST_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                        RESERVED : 2;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                                 : 1;
+        unsigned int                  DB_ALUCST_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TIMEBASE : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                           SPARE : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                        TIMEBASE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERCENT_BUSY : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    PERCENT_BUSY : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INPUT_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_THREAD_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                        RESERVED : 2;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_WATCHDOG_TIMER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ENABLE : 1;
+        unsigned int                   TIMEOUT_COUNT : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TIMEOUT_COUNT : 31;
+        unsigned int                          ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_WATCHDOG_TIMER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ENABLE : 1;
+        unsigned int                   TIMEOUT_COUNT : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TIMEOUT_COUNT : 31;
+        unsigned int                          ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_WATCHDOG_MASK : 1;
+        unsigned int                VS_WATCHDOG_MASK : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                VS_WATCHDOG_MASK : 1;
+        unsigned int                PS_WATCHDOG_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PS_WATCHDOG_TIMEOUT : 1;
+        unsigned int             VS_WATCHDOG_TIMEOUT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int             VS_WATCHDOG_TIMEOUT : 1;
+        unsigned int             PS_WATCHDOG_TIMEOUT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PS_WATCHDOG_ACK : 1;
+        unsigned int                 VS_WATCHDOG_ACK : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                 VS_WATCHDOG_ACK : 1;
+        unsigned int                 PS_WATCHDOG_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_INPUT_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       VC_VSR_LD : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           PC_AS : 3;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                           PC_AS : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_VSR_LD : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_CONST_MGR_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TP_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           EX_TP : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           CF_TP : 4;
+        unsigned int                           IF_TP : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           IF_TP : 3;
+        unsigned int                           CF_TP : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           EX_TP : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_EXP_ALLOC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   POS_BUF_AVAIL : 4;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                   POS_BUF_AVAIL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PTR_BUFF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   END_OF_BUFFER : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                   END_OF_BUFFER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_VTX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VTX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_PIX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TB_STATUS_SEL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int                                 : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_PTR : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                     VS_DONE_PTR : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATUS_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VS_STATUS_REG : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VS_STATUS_REG : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_HEAD_PTR : 6;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int                            BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BUSY : 1;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                    PIX_HEAD_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VECTOR_RESULT : 6;
+        unsigned int                  VECTOR_DST_REL : 1;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int                  SCALAR_DST_REL : 1;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                   SCALAR_OPCODE : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SCALAR_OPCODE : 6;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  SCALAR_DST_REL : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                  VECTOR_DST_REL : 1;
+        unsigned int                   VECTOR_RESULT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                 CONST_0_REL_ABS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CONST_0_REL_ABS : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SRC_C_REG_PTR : 6;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_A_SEL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_A_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   SRC_C_REG_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_1 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 11;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 11;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 6;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                      RESERVED_0 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                        RESERVED : 22;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                        RESERVED : 22;
+        unsigned int                         LOOP_ID : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      RESERVED_1 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 17;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 1;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_2 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_2 : 2;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                      RESERVED_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 17;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                        RESERVED : 17;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 4;
+        unsigned int                        RESERVED : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 28;
+        unsigned int                            SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 8;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                            SIZE : 4;
+        unsigned int                      RESERVED_1 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 12;
+        unsigned int                            SIZE : 4;
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                      RESERVED_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 24;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                        RESERVED : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_Z : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_SEL_Z : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               USE_REG_GRADIENTS : 1;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int               USE_REG_GRADIENTS : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                         SRC_SEL : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SRC_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          STRIDE : 8;
+        unsigned int                                 : 8;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 7;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                                 : 7;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 8;
+        unsigned int                          STRIDE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TYPE : 1;
+        unsigned int                           STATE : 1;
+        unsigned int                    BASE_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BASE_ADDRESS : 30;
+        unsigned int                           STATE : 1;
+        unsigned int                            TYPE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ENDIAN_SWAP : 2;
+        unsigned int                   LIMIT_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   LIMIT_ADDRESS : 30;
+        unsigned int                     ENDIAN_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_PROGRAM_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      VS_CF_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INTERPOLATOR_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARAM_SHADE : 16;
+        unsigned int                SAMPLING_PATTERN : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                SAMPLING_PATTERN : 16;
+        unsigned int                     PARAM_SHADE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PROGRAM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                   GEN_INDEX_VTX : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   GEN_INDEX_VTX : 1;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      VS_NUM_REG : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_0 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_7 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PARAM_WRAP_7 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_0 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_8 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_15 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PARAM_WRAP_15 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                    PARAM_WRAP_8 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONTEXT_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                                 : 4;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RD_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RD_BASE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                         RD_BASE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DB_PROB_ON : 1;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 5;
+        unsigned int                   DB_PROB_COUNT : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DB_PROB_COUNT : 8;
+        unsigned int                                 : 5;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      DB_PROB_ON : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DB_ON_PIX : 1;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                                 : 6;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                                 : 6;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                       DB_ON_PIX : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_ARBITER_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  PA_CLNT_ENABLE : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                  PA_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_CLNT_AXI_ID_REUSE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          CPw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                          PAw_ID : 3;
+        unsigned int                                 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 17;
+        unsigned int                          PAw_ID : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          CPw_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     AXI_READ_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                     AXI_READ_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           INDEX : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                           INDEX : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_HALT_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AXI_HALT : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                        AXI_HALT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                      PA_REQUEST : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                      PA_REQUEST : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                         MH_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                       CP_BLEN_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_BLEN_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       TC_BLEN_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       CP_BLEN_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_PA_writeclean : 1;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                MH_PA_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CP_MH_send : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                   CP_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CP_MH_ad_31_5 : 27;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                      CP_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG06 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 CP_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CP_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG07 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CP_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                CP_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG08 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CP_MH_be : 8;
+        unsigned int                        RB_MH_be : 8;
+        unsigned int                        PA_MH_be : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        PA_MH_be : 8;
+        unsigned int                        RB_MH_be : 8;
+        unsigned int                        CP_MH_be : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 3;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                 TC_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 TC_MH_addr_31_5 : 27;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_info : 25;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_info : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_TC_mcinfo : 25;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                    MH_TC_mcinfo : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ROQ_INFO : 25;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_INFO : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                 RB_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_addr_31_5 : 27;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 RB_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                RB_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                RB_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      PA_MH_send : 1;
+        unsigned int                 PA_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PA_MH_addr_31_5 : 27;
+        unsigned int                      PA_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG19 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PA_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PA_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PA_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PA_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG22 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG23 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                    CTRL_ARC_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CTRL_ARC_PAD : 28;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG24 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                           REG_A : 14;
+        unsigned int                          REG_RE : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                          REG_RE : 1;
+        unsigned int                           REG_A : 14;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG25 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          REG_WD : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REG_WD : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG26 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_RBBM_busy : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       BRC_VALID : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BRC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int                    MH_RBBM_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG27 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  EFF2_FP_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                  EFF2_FP_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG28 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG29 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        CLNT_REQ : 5;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_4 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RECENT_d_4 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                        CLNT_REQ : 5;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG30 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG31 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG32 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG33 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG34 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG35 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                      ROQ_ADDR_0 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_0 : 27;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG36 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                      ROQ_ADDR_1 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_1 : 27;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG37 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                      ROQ_ADDR_2 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_2 : 27;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG38 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                      ROQ_ADDR_3 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_3 : 27;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG39 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                      ROQ_ADDR_4 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_4 : 27;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG40 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                      ROQ_ADDR_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_5 : 27;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG41 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                      ROQ_ADDR_6 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_6 : 27;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG42 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                      ROQ_ADDR_7 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_7 : 27;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG43 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ARB_REG_WE_q : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                 ARB_REG_VALID_q : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                     ARB_REG_RTR : 1;
+        unsigned int                  WDAT_BURST_RTR : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                  WDB_RTR_SKID_3 : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                  WDB_RTR_SKID_3 : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                  WDAT_BURST_RTR : 1;
+        unsigned int                     ARB_REG_RTR : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                 ARB_REG_VALID_q : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                    ARB_REG_WE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG44 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ARB_WE : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                       ARB_VAD_q : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ARB_VAD_q : 28;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                          ARB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG45 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          MMU_WE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         MMU_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MMU_PAD : 28;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                          MMU_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG46 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                WDAT_REG_VALID_q : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                   WDB_WDC_WSTRB : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   WDB_WDC_WSTRB : 8;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                WDAT_REG_VALID_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG47 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG48 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG49 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG50 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG51 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG52 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          RF_MMU_CONFIG_q_1_to_0 : 2;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int         RF_MMU_CONFIG_q_25_to_4 : 22;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int               client_behavior_q : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               client_behavior_q : 2;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int         RF_MMU_CONFIG_q_25_to_4 : 22;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int          RF_MMU_CONFIG_q_1_to_0 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG53 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    stage1_valid : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                    stage1_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG54 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                    stage2_valid : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                     TAG_valid_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TAG_valid_q : 16;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                    stage2_valid : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG55 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG0_VA : 13;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                         TAG0_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG56 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG2_VA : 13;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                         TAG2_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG57 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG4_VA : 13;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                         TAG4_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG58 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG6_VA : 13;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                         TAG6_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG59 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG8_VA : 13;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                         TAG8_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG60 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG10_VA : 13;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                        TAG10_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG61 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG12_VA : 13;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                        TAG12_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG62 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG14_VA : 13;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                        TAG14_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG63 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      MMU_ENABLE : 1;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int              PA_W_CLNT_BEHAVIOR : 2;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int              PA_W_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                      MMU_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_VA_RANGE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                NUM_64KB_REGIONS : 12;
+        unsigned int                         VA_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         VA_BASE : 20;
+        unsigned int                NUM_64KB_REGIONS : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PT_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         PT_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         PT_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PAGE_FAULT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PAGE_FAULT : 1;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int                          REQ_VA : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REQ_VA : 20;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                      PAGE_FAULT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_TRAN_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                      TRAN_ERROR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      TRAN_ERROR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_INVALIDATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  INVALIDATE_ALL : 1;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                  INVALIDATE_ALL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                        MPU_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MPU_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_END {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         MPU_END : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MPU_END : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union WAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int                                 : 2;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 2;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_ISYNC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CMDFIFO_AVAIL : 5;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                      GUI_ACTIVE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      GUI_ACTIVE : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                                 : 2;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                   CMDFIFO_AVAIL : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DSPLY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SEL_DMI_ACTIVE_BUFID0 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID1 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID2 : 1;
+        unsigned int             SEL_DMI_VSYNC_VALID : 1;
+        unsigned int              DMI_CH1_USE_BUFID0 : 1;
+        unsigned int              DMI_CH1_USE_BUFID1 : 1;
+        unsigned int              DMI_CH1_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH1_SW_CNTL : 1;
+        unsigned int                DMI_CH1_NUM_BUFS : 2;
+        unsigned int              DMI_CH2_USE_BUFID0 : 1;
+        unsigned int              DMI_CH2_USE_BUFID1 : 1;
+        unsigned int              DMI_CH2_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH2_SW_CNTL : 1;
+        unsigned int                DMI_CH2_NUM_BUFS : 2;
+        unsigned int              DMI_CHANNEL_SELECT : 2;
+        unsigned int                                 : 2;
+        unsigned int              DMI_CH3_USE_BUFID0 : 1;
+        unsigned int              DMI_CH3_USE_BUFID1 : 1;
+        unsigned int              DMI_CH3_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH3_SW_CNTL : 1;
+        unsigned int                DMI_CH3_NUM_BUFS : 2;
+        unsigned int              DMI_CH4_USE_BUFID0 : 1;
+        unsigned int              DMI_CH4_USE_BUFID1 : 1;
+        unsigned int              DMI_CH4_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH4_SW_CNTL : 1;
+        unsigned int                DMI_CH4_NUM_BUFS : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                DMI_CH4_NUM_BUFS : 2;
+        unsigned int                 DMI_CH4_SW_CNTL : 1;
+        unsigned int              DMI_CH4_USE_BUFID2 : 1;
+        unsigned int              DMI_CH4_USE_BUFID1 : 1;
+        unsigned int              DMI_CH4_USE_BUFID0 : 1;
+        unsigned int                DMI_CH3_NUM_BUFS : 2;
+        unsigned int                 DMI_CH3_SW_CNTL : 1;
+        unsigned int              DMI_CH3_USE_BUFID2 : 1;
+        unsigned int              DMI_CH3_USE_BUFID1 : 1;
+        unsigned int              DMI_CH3_USE_BUFID0 : 1;
+        unsigned int                                 : 2;
+        unsigned int              DMI_CHANNEL_SELECT : 2;
+        unsigned int                DMI_CH2_NUM_BUFS : 2;
+        unsigned int                 DMI_CH2_SW_CNTL : 1;
+        unsigned int              DMI_CH2_USE_BUFID2 : 1;
+        unsigned int              DMI_CH2_USE_BUFID1 : 1;
+        unsigned int              DMI_CH2_USE_BUFID0 : 1;
+        unsigned int                DMI_CH1_NUM_BUFS : 2;
+        unsigned int                 DMI_CH1_SW_CNTL : 1;
+        unsigned int              DMI_CH1_USE_BUFID2 : 1;
+        unsigned int              DMI_CH1_USE_BUFID1 : 1;
+        unsigned int              DMI_CH1_USE_BUFID0 : 1;
+        unsigned int             SEL_DMI_VSYNC_VALID : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID2 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID1 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RENDER_LATEST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               DMI_CH1_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH2_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH3_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH4_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH4_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH3_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH2_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH1_BUFFER_ID : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RTL_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CHANGELIST : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      CHANGELIST : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PATCH_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PATCH_REVISION : 16;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                     CUSTOMER_ID : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     CUSTOMER_ID : 8;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                  PATCH_REVISION : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_AUXILIARY_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER0 : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     PARTNUMBER0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER1 : 4;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                     PARTNUMBER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DESIGNER1 : 4;
+        unsigned int                        REVISION : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        REVISION : 4;
+        unsigned int                       DESIGNER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int                                 : 1;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 1;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    READ_TIMEOUT : 8;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                    READ_TIMEOUT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SKEW_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SOFT_RESET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SOFT_RESET_CP : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                                 : 5;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 2;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                                 : 2;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 5;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_CP : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GC_SYS_IDLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+        unsigned int            GC_SYS_WAIT_DMI_MASK : 6;
+        unsigned int                                 : 2;
+        unsigned int              GC_SYS_URGENT_RAMP : 1;
+        unsigned int                 GC_SYS_WAIT_DMI : 1;
+        unsigned int                                 : 3;
+        unsigned int     GC_SYS_URGENT_RAMP_OVERRIDE : 1;
+        unsigned int        GC_SYS_WAIT_DMI_OVERRIDE : 1;
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+        unsigned int        GC_SYS_WAIT_DMI_OVERRIDE : 1;
+        unsigned int     GC_SYS_URGENT_RAMP_OVERRIDE : 1;
+        unsigned int                                 : 3;
+        unsigned int                 GC_SYS_WAIT_DMI : 1;
+        unsigned int              GC_SYS_URGENT_RAMP : 1;
+        unsigned int                                 : 2;
+        unsigned int            GC_SYS_WAIT_DMI_MASK : 6;
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union NQWAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WAIT_GUI_IDLE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                   WAIT_GUI_IDLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG_OUT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DEBUG_BUS_OUT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DEBUG_BUS_OUT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 2;
+        unsigned int                   SUB_BLOCK_SEL : 4;
+        unsigned int                       SW_ENABLE : 1;
+        unsigned int                                 : 3;
+        unsigned int             GPIO_SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 2;
+        unsigned int              GPIO_SUB_BLOCK_SEL : 4;
+        unsigned int              GPIO_BYTE_LANE_ENB : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              GPIO_BYTE_LANE_ENB : 4;
+        unsigned int              GPIO_SUB_BLOCK_SEL : 4;
+        unsigned int                                 : 2;
+        unsigned int             GPIO_SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 3;
+        unsigned int                       SW_ENABLE : 1;
+        unsigned int                   SUB_BLOCK_SEL : 4;
+        unsigned int                                 : 2;
+        unsigned int                  SUB_BLOCK_ADDR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int                                 : 3;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 4;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int                                 : 6;
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+        unsigned int                                 : 6;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int                                 : 4;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 3;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_READ_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 13;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                      READ_ERROR : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      READ_ERROR : 1;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                                 : 13;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_WAIT_IDLE_CLOCKS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_MASK : 1;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                  RDERR_INT_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_STAT : 1;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                  RDERR_INT_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   RDERR_INT_ACK : 1;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                   RDERR_INT_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MASTER_INT_SIGNAL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 20;
+        unsigned int                     SQ_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                   RBBM_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   RBBM_INT_STAT : 1;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SQ_INT_STAT : 1;
+        unsigned int                                 : 20;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNT1_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                 PERF_COUNT1_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PERF_COUNT1_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERF_COUNT1_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                         RB_BASE : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         RB_BASE : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RB_BUFSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 6;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 3;
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+        unsigned int                                 : 3;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 6;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BUFSZ : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_RPTR_SWAP : 2;
+        unsigned int                    RB_RPTR_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_RPTR_ADDR : 30;
+        unsigned int                    RB_RPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_RPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_RPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_WR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RB_RPTR_WR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                      RB_RPTR_WR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_WPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_WPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_DELAY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PRE_WRITE_TIMER : 28;
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+        unsigned int                 PRE_WRITE_TIMER : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_WPTR_SWAP : 2;
+        unsigned int                    RB_WPTR_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_WPTR_BASE : 30;
+        unsigned int                    RB_WPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB1_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB1_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB1_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB1_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB2_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB2_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB2_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB2_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                         ST_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         ST_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        ST_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        ST_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_QUEUE_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CSQ_IB1_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB1_START : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CSQ_CNT_RING : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                    CSQ_CNT_RING : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STQ_CNT_ST : 7;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                      STQ_CNT_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MEQ_CNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                         MEQ_CNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_RB_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB1_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB2_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NON_PREFETCH_CNTRS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     IB1_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB1_COUNTER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_ST_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STQ_RPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_RPTR_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MEQ_RPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_RPTR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MIU_TAG_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TAG_0_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                                 : 13;
+        unsigned int              INVALID_RETURN_TAG : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              INVALID_RETURN_TAG : 1;
+        unsigned int                                 : 13;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_0_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CMD_INDEX : 7;
+        unsigned int                                 : 9;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 9;
+        unsigned int                       CMD_INDEX : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CMD_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CMD_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ME_STATMUX : 16;
+        unsigned int                                 : 9;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   PROG_CNT_SIZE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PROG_CNT_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                                 : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 9;
+        unsigned int                      ME_STATMUX : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ME_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ME_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_WADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_WADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_WADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_RADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_RADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_RADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ME_RAM_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ME_RAM_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RDADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ME_RDADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ME_RDADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int                                 : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG4 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG4 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG5 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG5 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG6 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG6 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG7 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG7 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_UMSK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_UMSK : 8;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_UMSK : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                    SCRATCH_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_SWM : 1;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                     VS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_SWAP : 2;
+        unsigned int                    VS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_ADDR : 30;
+        unsigned int                    VS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PS_DONE_SWM : 1;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                     PS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_SWAP : 2;
+        unsigned int                    PS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_ADDR : 30;
+        unsigned int                    PS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CF_DONE_SRC : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                     CF_DONE_SRC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_SWAP : 2;
+        unsigned int                    CF_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_ADDR : 30;
+        unsigned int                    CF_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_SWAP : 2;
+        unsigned int                  NRT_WRITE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_ADDR : 30;
+        unsigned int                  NRT_WRITE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                     RB_INT_MASK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                     RB_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                      RB_INT_ACK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RB_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_ADDR : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      UCODE_ADDR : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_DATA : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      UCODE_DATA : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFMON_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFMON_STATE : 4;
+        unsigned int                                 : 4;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PERFMON_STATE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFCOUNT_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                   PERFCOUNT_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PERFCOUNT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    PERFCOUNT_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DISCARD_0 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_15 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_15 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_16 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_31 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_31 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_16 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_32 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_47 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_47 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_32 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_48 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_63 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_63 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_48 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               STATE_DEBUG_INDEX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int               STATE_DEBUG_INDEX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                STATE_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                STATE_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PROG_COUNTER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         COUNTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         COUNTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     MIU_WR_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                         CP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CP_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int                     MIU_WR_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_0_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_1_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_2_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_3_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_4_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_5_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_6_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_7_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_8_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_9_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_10_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_11_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_12_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_13_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_14_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_15_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_0 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_0 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_1 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_1 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_2 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_2 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_3 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_3 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_4 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_4 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_5 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_5 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_6 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_6 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_7 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_7 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SURFACE_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SURFACE_PITCH : 14;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                   SURFACE_PITCH : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    COLOR_FORMAT : 4;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      COLOR_BASE : 20;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_FORMAT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEPTH_FORMAT : 1;
+        unsigned int                                 : 11;
+        unsigned int                      DEPTH_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      DEPTH_BASE : 20;
+        unsigned int                                 : 11;
+        unsigned int                    DEPTH_FORMAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STENCILREF : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                      STENCILREF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ALPHA_REF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ALPHA_REF : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ALPHA_REF : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       WRITE_RED : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                       WRITE_RED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_RED {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BLEND_RED : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       BLEND_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_GREEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_GREEN : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_GREEN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_BLUE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      BLEND_BLUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      BLEND_BLUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_ALPHA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_ALPHA : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_ALPHA : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FOG_COLOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         FOG_RED : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                         FOG_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK_BF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   STENCILREF_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int                   STENCILREF_BF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTHCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  STENCIL_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                 STENCILZFAIL_BF : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 STENCILZFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  STENCIL_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLENDCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  COLOR_SRCBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                  COLOR_SRCBLEND : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLORCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ALPHA_FUNC : 3;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                                 : 7;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int                                 : 7;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int                      ALPHA_FUNC : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_MODECONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_MODE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                      EDRAM_MODE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_DEST_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COLOR_DEST_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 COLOR_DEST_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                  COPY_DEST_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  COPY_DEST_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PITCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COPY_DEST_PITCH : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                 COPY_DEST_PITCH : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                COPY_DEST_ENDIAN : 3;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_ENDIAN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PIXEL_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        OFFSET_X : 13;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                        OFFSET_X : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     DEPTH_CLEAR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEPTH_CLEAR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_CTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int                                 : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int                      CRC_SYSTEM : 1;
+        unsigned int                       RESERVED6 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       RESERVED6 : 1;
+        unsigned int                      CRC_SYSTEM : 1;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                                 : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_EDRAM_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_SIZE : 4;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                                 : 8;
+        unsigned int                     EDRAM_RANGE : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     EDRAM_RANGE : 18;
+        unsigned int                                 : 8;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                      EDRAM_SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_RD_PORT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CRC_RD_ADVANCE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                  CRC_RD_ADVANCE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_TOTAL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TOTAL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TOTAL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZPASS_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZPASS_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZPASS_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 TILE_FIFO_COUNT : 4;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z_TILE_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    Z_TILE_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 TILE_FIFO_COUNT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ACCUM_VALID : 4;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int                     ACCUM_VALID : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int                                 : 19;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 19;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FLAG_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_SPARES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_ENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_MOREENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h
new file mode 100644
index 000000000000..10807b43ea44
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h
@@ -0,0 +1,4183 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_SHIFT_HEADER)
+#define _yamato_SHIFT_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT          0x00000000
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT           0x00000000
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT          0x00000001
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT           0x00000002
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT          0x00000003
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT           0x00000004
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT          0x00000005
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT                  0x00000008
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT                   0x00000009
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT                  0x0000000a
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT             0x0000000b
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT               0x00000010
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT     0x00000012
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT          0x00000013
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT        0x00000014
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT                0x00000015
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT              0x00000016
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT               0x00000017
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT               0x00000018
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT         0x00000000
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT                  0x00000000
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT                  0x00000001
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT                  0x00000003
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT                    0x00000000
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT                     0x00000010
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT                0x00000000
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT                0x00000010
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT                      0x00000000
+
+// PA_SU_FACE_DATA
+#define PA_SU_FACE_DATA__BASE_ADDR__SHIFT                  0x00000005
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT              0x00000000
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT               0x00000001
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT                    0x00000002
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT               0x00000003
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT    0x00000005
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT     0x00000008
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT             0x0000000f
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT     0x00000012
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT      0x00000013
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT          0x00000014
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT       0x00000015
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT       0x00000017
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT    0x00000019
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS__SHIFT      0x0000001d
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE__SHIFT        0x0000001e
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE__SHIFT       0x0000001f
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT        0x00000000
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT      0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT         0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT       0x00000000
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT        0x00000000
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT        0x00000010
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT           0x00000000
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT            0x0000000d
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK__SHIFT                      0x00000000
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT            0x00000000
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT            0x00000010
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT       0x0000001c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT         0x0000001d
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT                  0x00000000
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT              0x00000008
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT          0x00000009
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT                 0x0000000a
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT              0x00000000
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT               0x00000001
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT      0x00000007
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT         0x00000000
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT       0x00000000
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT     0x00000008
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT                  0x0000001f
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT  0x00000000
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT   0x00000001
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT  0x00000002
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT   0x00000003
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT     0x0000000d
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT            0x00000014
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT    0x00000013
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT            0x00000018
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT           0x00000018
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT           0x00000008
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT           0x0000001a
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT           0x00000008
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT           0x00000001
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT           0x00000016
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT           0x0000001c
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT   0x00000000
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT           0x00000006
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT           0x0000000c
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT           0x00000012
+#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT        0x00000014
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT   0x0000001c
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT    0x0000001d
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT           0x0000000a
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT           0x00000013
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT            0x00000004
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT           0x00000002
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT           0x00000016
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT      0x00000000
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT     0x00000004
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT    0x0000000e
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT      0x00000014
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT           0x0000001b
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT           0x00000000
+#define SXIFCCG_DEBUG_REG0__position_address__SHIFT        0x00000004
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG0__point_address__SHIFT           0x0000000a
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT            0x0000000d
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT            0x00000011
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT  0x00000013
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT       0x00000017
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT   0x0000001e
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT   0x0000001f
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT            0x00000000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT          0x00000002
+#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT     0x00000004
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT      0x0000000b
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT         0x0000000c
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT                 0x00000014
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT            0x00000015
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT            0x00000017
+#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT        0x00000019
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT                 0x00000000
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT            0x00000001
+#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT                  0x00000002
+#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT         0x00000003
+#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT        0x00000009
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT            0x00000012
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT            0x00000016
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT   0x0000001b
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT    0x0000001c
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT            0x00000004
+#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT     0x00000005
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT            0x00000008
+#define SXIFCCG_DEBUG_REG3__current_state__SHIFT           0x0000000c
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT       0x0000000e
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT        0x0000000f
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT  0x00000012
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT   0x00000013
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT  0x00000015
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT            0x00000016
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT             0x00000000
+#define SETUP_DEBUG_REG0__pmode_state__SHIFT               0x00000005
+#define SETUP_DEBUG_REG0__ge_stallb__SHIFT                 0x0000000b
+#define SETUP_DEBUG_REG0__geom_enable__SHIFT               0x0000000c
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT         0x0000000d
+#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT               0x0000000e
+#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT                0x0000000f
+#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT              0x00000010
+#define SETUP_DEBUG_REG0__geom_busy__SHIFT                 0x00000011
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT           0x0000000b
+#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT          0x0000000c
+#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT             0x0000000d
+#define SETUP_DEBUG_REG4__clipped_gated__SHIFT             0x00000010
+#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT        0x00000011
+#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT              0x00000014
+#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT        0x00000015
+#define SETUP_DEBUG_REG4__type_gated__SHIFT                0x00000017
+#define SETUP_DEBUG_REG4__fpov_gated__SHIFT                0x0000001a
+#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT          0x0000001b
+#define SETUP_DEBUG_REG4__event_gated__SHIFT               0x0000001c
+#define SETUP_DEBUG_REG4__eop_gated__SHIFT                 0x0000001d
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT     0x0000000b
+#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT       0x00000016
+#define SETUP_DEBUG_REG5__event_id_gated__SHIFT            0x00000018
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1__SHIFT                    0x00000000
+#define SC_DEBUG_0__pa_sc_valid__SHIFT                     0x00000001
+#define SC_DEBUG_0__pa_sc_phase__SHIFT                     0x00000002
+#define SC_DEBUG_0__cntx_cnt__SHIFT                        0x00000005
+#define SC_DEBUG_0__decr_cntx_cnt__SHIFT                   0x0000000c
+#define SC_DEBUG_0__incr_cntx_cnt__SHIFT                   0x0000000d
+#define SC_DEBUG_0__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state__SHIFT                        0x00000000
+#define SC_DEBUG_1__em1_data_ready__SHIFT                  0x00000003
+#define SC_DEBUG_1__em2_data_ready__SHIFT                  0x00000004
+#define SC_DEBUG_1__move_em1_to_em2__SHIFT                 0x00000005
+#define SC_DEBUG_1__ef_data_ready__SHIFT                   0x00000006
+#define SC_DEBUG_1__ef_state__SHIFT                        0x00000007
+#define SC_DEBUG_1__pipe_valid__SHIFT                      0x00000009
+#define SC_DEBUG_1__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly__SHIFT                      0x00000000
+#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT            0x00000001
+#define SC_DEBUG_2__pipe_freeze_b__SHIFT                   0x00000003
+#define SC_DEBUG_2__prim_rts__SHIFT                        0x00000004
+#define SC_DEBUG_2__next_prim_rts_dly__SHIFT               0x00000005
+#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT               0x00000006
+#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT               0x00000007
+#define SC_DEBUG_2__stage0_rts__SHIFT                      0x00000008
+#define SC_DEBUG_2__phase_rts_dly__SHIFT                   0x00000009
+#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT              0x0000000f
+#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT              0x00000010
+#define SC_DEBUG_2__event_id_s1__SHIFT                     0x00000011
+#define SC_DEBUG_2__event_s1__SHIFT                        0x00000016
+#define SC_DEBUG_2__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1__SHIFT                       0x00000000
+#define SC_DEBUG_3__y_curr_s1__SHIFT                       0x0000000b
+#define SC_DEBUG_3__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_4__y_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_4__y_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_4__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_5__x_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_5__x_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_5__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty__SHIFT                      0x00000000
+#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT                 0x00000001
+#define SC_DEBUG_6__xy_ff_empty__SHIFT                     0x00000002
+#define SC_DEBUG_6__event_flag__SHIFT                      0x00000003
+#define SC_DEBUG_6__z_mask_needed__SHIFT                   0x00000004
+#define SC_DEBUG_6__state__SHIFT                           0x00000005
+#define SC_DEBUG_6__state_delayed__SHIFT                   0x00000008
+#define SC_DEBUG_6__data_valid__SHIFT                      0x0000000b
+#define SC_DEBUG_6__data_valid_d__SHIFT                    0x0000000c
+#define SC_DEBUG_6__tilex_delayed__SHIFT                   0x0000000d
+#define SC_DEBUG_6__tiley_delayed__SHIFT                   0x00000016
+#define SC_DEBUG_6__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag__SHIFT                      0x00000000
+#define SC_DEBUG_7__deallocate__SHIFT                      0x00000001
+#define SC_DEBUG_7__fposition__SHIFT                       0x00000004
+#define SC_DEBUG_7__sr_prim_we__SHIFT                      0x00000005
+#define SC_DEBUG_7__last_tile__SHIFT                       0x00000006
+#define SC_DEBUG_7__tile_ff_we__SHIFT                      0x00000007
+#define SC_DEBUG_7__qs_data_valid__SHIFT                   0x00000008
+#define SC_DEBUG_7__qs_q0_y__SHIFT                         0x00000009
+#define SC_DEBUG_7__qs_q0_x__SHIFT                         0x0000000b
+#define SC_DEBUG_7__qs_q0_valid__SHIFT                     0x0000000d
+#define SC_DEBUG_7__prim_ff_we__SHIFT                      0x0000000e
+#define SC_DEBUG_7__tile_ff_re__SHIFT                      0x0000000f
+#define SC_DEBUG_7__fw_prim_data_valid__SHIFT              0x00000010
+#define SC_DEBUG_7__last_quad_of_tile__SHIFT               0x00000011
+#define SC_DEBUG_7__first_quad_of_tile__SHIFT              0x00000012
+#define SC_DEBUG_7__first_quad_of_prim__SHIFT              0x00000013
+#define SC_DEBUG_7__new_prim__SHIFT                        0x00000014
+#define SC_DEBUG_7__load_new_tile_data__SHIFT              0x00000015
+#define SC_DEBUG_7__state__SHIFT                           0x00000016
+#define SC_DEBUG_7__fifos_ready__SHIFT                     0x00000018
+#define SC_DEBUG_7__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last__SHIFT                     0x00000000
+#define SC_DEBUG_8__sample_mask__SHIFT                     0x00000001
+#define SC_DEBUG_8__sample_y__SHIFT                        0x00000005
+#define SC_DEBUG_8__sample_x__SHIFT                        0x00000007
+#define SC_DEBUG_8__sample_send__SHIFT                     0x00000009
+#define SC_DEBUG_8__next_cycle__SHIFT                      0x0000000a
+#define SC_DEBUG_8__ez_sample_ff_full__SHIFT               0x0000000c
+#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT                  0x0000000d
+#define SC_DEBUG_8__num_samples__SHIFT                     0x0000000e
+#define SC_DEBUG_8__last_quad_of_tile__SHIFT               0x00000010
+#define SC_DEBUG_8__last_quad_of_prim__SHIFT               0x00000011
+#define SC_DEBUG_8__first_quad_of_prim__SHIFT              0x00000012
+#define SC_DEBUG_8__sample_we__SHIFT                       0x00000013
+#define SC_DEBUG_8__fposition__SHIFT                       0x00000014
+#define SC_DEBUG_8__event_id__SHIFT                        0x00000015
+#define SC_DEBUG_8__event_flag__SHIFT                      0x0000001a
+#define SC_DEBUG_8__fw_prim_data_valid__SHIFT              0x0000001b
+#define SC_DEBUG_8__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send__SHIFT                      0x00000000
+#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT                   0x00000001
+#define SC_DEBUG_9__fifo_data_ready__SHIFT                 0x00000005
+#define SC_DEBUG_9__early_z_enable__SHIFT                  0x00000006
+#define SC_DEBUG_9__mask_state__SHIFT                      0x00000007
+#define SC_DEBUG_9__next_ez_mask__SHIFT                    0x00000009
+#define SC_DEBUG_9__mask_ready__SHIFT                      0x00000019
+#define SC_DEBUG_9__drop_sample__SHIFT                     0x0000001a
+#define SC_DEBUG_9__fetch_new_sample_data__SHIFT           0x0000001b
+#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT        0x0000001c
+#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT       0x0000001d
+#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT         0x0000001e
+#define SC_DEBUG_9__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask__SHIFT           0x00000000
+#define SC_DEBUG_10__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready__SHIFT           0x00000000
+#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT      0x00000001
+#define SC_DEBUG_11__ez_prim_data_ready__SHIFT             0x00000002
+#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT        0x00000003
+#define SC_DEBUG_11__iterator_input_fz__SHIFT              0x00000004
+#define SC_DEBUG_11__packer_send_quads__SHIFT              0x00000005
+#define SC_DEBUG_11__packer_send_cmd__SHIFT                0x00000006
+#define SC_DEBUG_11__packer_send_event__SHIFT              0x00000007
+#define SC_DEBUG_11__next_state__SHIFT                     0x00000008
+#define SC_DEBUG_11__state__SHIFT                          0x0000000b
+#define SC_DEBUG_11__stall__SHIFT                          0x0000000e
+#define SC_DEBUG_11__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT          0x00000000
+#define SC_DEBUG_12__event_id__SHIFT                       0x00000001
+#define SC_DEBUG_12__event_flag__SHIFT                     0x00000006
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT        0x00000007
+#define SC_DEBUG_12__itercmdfifo_full__SHIFT               0x00000008
+#define SC_DEBUG_12__itercmdfifo_empty__SHIFT              0x00000009
+#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT        0x0000000a
+#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT           0x0000000b
+#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT          0x0000000c
+#define SC_DEBUG_12__iter_qdhit0__SHIFT                    0x0000000d
+#define SC_DEBUG_12__bc_use_centers_reg__SHIFT             0x0000000e
+#define SC_DEBUG_12__bc_output_xy_reg__SHIFT               0x0000000f
+#define SC_DEBUG_12__iter_phase_out__SHIFT                 0x00000010
+#define SC_DEBUG_12__iter_phase_reg__SHIFT                 0x00000012
+#define SC_DEBUG_12__iterator_SP_valid__SHIFT              0x00000014
+#define SC_DEBUG_12__eopv_reg__SHIFT                       0x00000015
+#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT                0x00000016
+#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT            0x00000017
+#define SC_DEBUG_12__trigger__SHIFT                        0x0000001f
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT                0x00000000
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT               0x00000000
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT           0x00000006
+#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT__SHIFT    0x00000008
+#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT              0x0000000b
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT                 0x0000000c
+#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT             0x0000000d
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT   0x0000000e
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT         0x0000000f
+#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT             0x00000010
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT             0x00000000
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT                     0x00000000
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_DMA_SIZE__SWAP_MODE__SHIFT                     0x0000001e
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT                 0x00000000
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_BIN_SIZE__FACENESS_FETCH__SHIFT                0x0000001e
+#define VGT_BIN_SIZE__FACENESS_RESET__SHIFT                0x0000001f
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT                  0x00000000
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT                  0x00000000
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT                0x00000000
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT          0x00000000
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT    0x00000000
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC__SHIFT                           0x00000000
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT          0x00000000
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT           0x00000000
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT           0x00000010
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT              0x00000000
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT                   0x00000000
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT               0x00000001
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT           0x00000002
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT               0x00000003
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT                0x00000004
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT               0x00000005
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT                0x00000006
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT               0x00000007
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT          0x00000008
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy__SHIFT                 0x00000000
+#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT                 0x00000001
+#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT                 0x00000002
+#define VGT_DEBUG_REG0__dma_request_busy__SHIFT            0x00000003
+#define VGT_DEBUG_REG0__out_busy__SHIFT                    0x00000004
+#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT            0x00000005
+#define VGT_DEBUG_REG0__grp_busy__SHIFT                    0x00000006
+#define VGT_DEBUG_REG0__dma_busy__SHIFT                    0x00000007
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT       0x00000008
+#define VGT_DEBUG_REG0__rbiu_busy__SHIFT                   0x00000009
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT    0x0000000a
+#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT             0x0000000b
+#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT           0x0000000c
+#define VGT_DEBUG_REG0__vgt_busy__SHIFT                    0x0000000d
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT     0x0000000e
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT        0x0000000f
+#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT               0x00000010
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read__SHIFT            0x00000000
+#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT           0x00000001
+#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT            0x00000002
+#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT           0x00000003
+#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT            0x00000004
+#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT           0x00000005
+#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT            0x00000006
+#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT           0x00000007
+#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT            0x00000008
+#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT           0x00000009
+#define VGT_DEBUG_REG1__te_grp_read__SHIFT                 0x0000000a
+#define VGT_DEBUG_REG1__grp_te_valid__SHIFT                0x0000000b
+#define VGT_DEBUG_REG1__pt_grp_read__SHIFT                 0x0000000c
+#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT                0x0000000d
+#define VGT_DEBUG_REG1__vr_grp_read__SHIFT                 0x0000000e
+#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT                0x0000000f
+#define VGT_DEBUG_REG1__grp_dma_read__SHIFT                0x00000010
+#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT               0x00000011
+#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT            0x00000012
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT           0x00000013
+#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT                  0x00000014
+#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT                 0x00000015
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT           0x00000016
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT          0x00000017
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT           0x00000018
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT          0x00000019
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT           0x0000001a
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT          0x0000001b
+#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT                  0x0000001c
+#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT                 0x0000001d
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT              0x0000001e
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT                  0x00000000
+#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT            0x00000001
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT        0x00000000
+#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT           0x00000005
+#define VGT_DEBUG_REG6__input_data_valid__SHIFT            0x0000000a
+#define VGT_DEBUG_REG6__input_data_xfer__SHIFT             0x0000000b
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT      0x0000000c
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT      0x0000000d
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT  0x0000000e
+#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT      0x0000000f
+#define VGT_DEBUG_REG6__shifter_first_load__SHIFT          0x00000010
+#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT       0x00000013
+#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT             0x00000014
+#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT         0x00000015
+#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT        0x00000017
+#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT         0x00000018
+#define VGT_DEBUG_REG6__extract_vector__SHIFT              0x00000019
+#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT              0x0000001a
+#define VGT_DEBUG_REG6__destination_rtr__SHIFT             0x0000001b
+#define VGT_DEBUG_REG6__grp_trigger__SHIFT                 0x0000001c
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT          0x00000000
+#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT     0x00000010
+#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT        0x00000014
+#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG7__current_source_sel__SHIFT          0x0000001e
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel__SHIFT          0x00000000
+#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT            0x00000002
+#define VGT_DEBUG_REG8__input_data_cnt__SHIFT              0x00000007
+#define VGT_DEBUG_REG8__input_data_lsw__SHIFT              0x0000000c
+#define VGT_DEBUG_REG8__input_data_msw__SHIFT              0x00000011
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q__SHIFT               0x00000000
+#define VGT_DEBUG_REG9__next_stride_d__SHIFT               0x00000005
+#define VGT_DEBUG_REG9__current_shift_q__SHIFT             0x0000000a
+#define VGT_DEBUG_REG9__current_shift_d__SHIFT             0x0000000f
+#define VGT_DEBUG_REG9__current_stride_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG9__current_stride_d__SHIFT            0x00000019
+#define VGT_DEBUG_REG9__grp_trigger__SHIFT                 0x0000001e
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003
+#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT             0x00000004
+#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT        0x00000005
+#define VGT_DEBUG_REG10__bin_valid__SHIFT                  0x00000006
+#define VGT_DEBUG_REG10__read_block__SHIFT                 0x00000007
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT     0x00000008
+#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT          0x00000009
+#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG10__selected_data__SHIFT              0x0000000b
+#define VGT_DEBUG_REG10__mask_input_data__SHIFT            0x00000013
+#define VGT_DEBUG_REG10__gap_q__SHIFT                      0x0000001b
+#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT          0x0000001c
+#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT          0x0000001d
+#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT          0x0000001e
+#define VGT_DEBUG_REG10__grp_trigger__SHIFT                0x0000001f
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT       0x00000000
+#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT          0x00000005
+#define VGT_DEBUG_REG12__input_data_valid__SHIFT           0x0000000a
+#define VGT_DEBUG_REG12__input_data_xfer__SHIFT            0x0000000b
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT     0x0000000c
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT     0x0000000d
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e
+#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT     0x0000000f
+#define VGT_DEBUG_REG12__shifter_first_load__SHIFT         0x00000010
+#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT             0x00000011
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT      0x00000013
+#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT        0x00000015
+#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT       0x00000017
+#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT        0x00000018
+#define VGT_DEBUG_REG12__extract_vector__SHIFT             0x00000019
+#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT             0x0000001a
+#define VGT_DEBUG_REG12__destination_rtr__SHIFT            0x0000001b
+#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT               0x0000001c
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT         0x00000000
+#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT    0x00000010
+#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT       0x00000014
+#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT             0x00000018
+#define VGT_DEBUG_REG13__current_source_sel__SHIFT         0x0000001e
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel__SHIFT         0x00000000
+#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT           0x00000002
+#define VGT_DEBUG_REG14__input_data_cnt__SHIFT             0x00000007
+#define VGT_DEBUG_REG14__input_data_lsw__SHIFT             0x0000000c
+#define VGT_DEBUG_REG14__input_data_msw__SHIFT             0x00000011
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q__SHIFT              0x00000000
+#define VGT_DEBUG_REG15__next_stride_d__SHIFT              0x00000005
+#define VGT_DEBUG_REG15__current_shift_q__SHIFT            0x0000000a
+#define VGT_DEBUG_REG15__current_shift_d__SHIFT            0x0000000f
+#define VGT_DEBUG_REG15__current_stride_q__SHIFT           0x00000014
+#define VGT_DEBUG_REG15__current_stride_d__SHIFT           0x00000019
+#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT               0x0000001e
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT  0x00000000
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT   0x00000002
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT    0x00000003
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT   0x00000004
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT  0x00000005
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT   0x00000006
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT     0x00000007
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT         0x00000008
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT         0x00000009
+#define VGT_DEBUG_REG16__rst_last_bit__SHIFT               0x0000000a
+#define VGT_DEBUG_REG16__current_state_q__SHIFT            0x0000000b
+#define VGT_DEBUG_REG16__old_state_q__SHIFT                0x0000000c
+#define VGT_DEBUG_REG16__old_state_en__SHIFT               0x0000000d
+#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT            0x0000000e
+#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT             0x0000000f
+#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT           0x00000010
+#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT           0x00000011
+#define VGT_DEBUG_REG16__load_empty_reg__SHIFT             0x00000012
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT   0x00000013
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT   0x0000001e
+#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q__SHIFT                0x00000000
+#define VGT_DEBUG_REG17__extend_read_q__SHIFT              0x00000001
+#define VGT_DEBUG_REG17__grp_indx_size__SHIFT              0x00000002
+#define VGT_DEBUG_REG17__cull_prim_true__SHIFT             0x00000004
+#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT               0x00000005
+#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT               0x00000006
+#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT          0x00000007
+#define VGT_DEBUG_REG17__check_second_reg__SHIFT           0x00000008
+#define VGT_DEBUG_REG17__check_first_reg__SHIFT            0x00000009
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT    0x0000000b
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT    0x0000000c
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT     0x0000000d
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT     0x0000000e
+#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT            0x0000000f
+#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT            0x00000010
+#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT    0x00000000
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT    0x00000006
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d
+#define VGT_DEBUG_REG18__dma_mem_full__SHIFT               0x0000000f
+#define VGT_DEBUG_REG18__dma_ram_re__SHIFT                 0x00000010
+#define VGT_DEBUG_REG18__dma_ram_we__SHIFT                 0x00000011
+#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT              0x00000012
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT       0x00000013
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT       0x00000014
+#define VGT_DEBUG_REG18__bin_mem_full__SHIFT               0x00000015
+#define VGT_DEBUG_REG18__bin_ram_we__SHIFT                 0x00000016
+#define VGT_DEBUG_REG18__bin_ram_re__SHIFT                 0x00000017
+#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT              0x00000018
+#define VGT_DEBUG_REG18__start_bin_req__SHIFT              0x00000019
+#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT        0x0000001a
+#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT               0x0000001b
+#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT         0x0000001c
+#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT         0x0000001d
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT       0x00000000
+#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT       0x00000001
+#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT          0x00000002
+#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT          0x00000003
+#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT        0x00000004
+#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT          0x00000005
+#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT             0x00000006
+#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT             0x00000007
+#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT           0x00000008
+#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT          0x00000009
+#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT             0x0000000a
+#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT             0x0000000b
+#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT           0x0000000c
+#define VGT_DEBUG_REG20__hold_prim__SHIFT                  0x0000000d
+#define VGT_DEBUG_REG20__sent_cnt__SHIFT                   0x0000000e
+#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT        0x00000012
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT       0x00000013
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT       0x00000014
+#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT   0x00000015
+#define VGT_DEBUG_REG20__out_trigger__SHIFT                0x0000001a
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT  0x00000000
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001
+#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT            0x00000004
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT    0x00000007
+#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT    0x0000000e
+#define VGT_DEBUG_REG21__new_packet_q__SHIFT               0x00000012
+#define VGT_DEBUG_REG21__new_allocate_q__SHIFT             0x00000013
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT    0x00000014
+#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT       0x00000016
+#define VGT_DEBUG_REG21__insert_null_prim__SHIFT           0x00000017
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT      0x00000018
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT      0x00000019
+#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT       0x0000001a
+#define VGT_DEBUG_REG21__out_trigger__SHIFT                0x0000001f
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC__SHIFT                        0x00000000
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC__SHIFT                        0x00000000
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT             0x00000000
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT               0x00000000
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT              0x00000012
+#define TC_CNTL_STATUS__TC_BUSY__SHIFT                     0x0000001f
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT               0x00000008
+#define TCM_CHICKEN__SPARE__SHIFT                          0x00000009
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT          0x00000000
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT          0x00000003
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT             0x00000000
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT           0x00000001
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT        0x00000002
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT        0x00000003
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT       0x00000004
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT         0x00000005
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT            0x00000006
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT      0x00000008
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT        0x00000009
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT           0x0000000a
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT           0x0000000c
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT        0x0000000d
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT          0x0000000e
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT             0x0000000f
+#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT                  0x00000010
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT            0x00000011
+#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT                  0x00000013
+#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT                  0x00000014
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT               0x00000015
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT             0x00000016
+#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT                  0x00000017
+#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT                  0x00000018
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT               0x00000019
+#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT                  0x0000001b
+#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT                  0x0000001c
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT          0x0000001d
+#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT                  0x0000001e
+#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT                   0x0000001f
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL__SHIFT                        0x00000000
+#define TPC_DEBUG0__IC_CTR__SHIFT                          0x00000002
+#define TPC_DEBUG0__WALKER_CNTL__SHIFT                     0x00000004
+#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT                    0x00000008
+#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT             0x0000000c
+#define TPC_DEBUG0__WALKER_STATE__SHIFT                    0x00000010
+#define TPC_DEBUG0__ALIGNER_STATE__SHIFT                   0x0000001a
+#define TPC_DEBUG0__REG_CLK_EN__SHIFT                      0x0000001d
+#define TPC_DEBUG0__TPC_CLK_EN__SHIFT                      0x0000001e
+#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT                    0x0000001f
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED__SHIFT                          0x00000000
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION__SHIFT                0x00000000
+#define TPC_CHICKEN__SPARE__SHIFT                          0x00000001
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT              0x00000000
+#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT                0x00000001
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT           0x00000002
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT               0x00000003
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT         0x00000004
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT            0x00000005
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT            0x00000006
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT            0x00000007
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT              0x00000008
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT           0x00000009
+#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT                 0x0000000a
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT            0x0000000b
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT              0x0000000c
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT           0x0000000d
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT             0x0000000e
+#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT                  0x00000010
+#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT                  0x00000011
+#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT                  0x00000012
+#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT                  0x00000013
+#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT                  0x00000014
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT               0x00000015
+#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT                  0x00000016
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT               0x00000017
+#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT                  0x00000018
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT               0x00000019
+#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT                  0x0000001a
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT               0x0000001b
+#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT                  0x0000001c
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT             0x0000001d
+#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT                  0x0000001e
+#define TP0_CNTL_STATUS__TP_BUSY__SHIFT                    0x0000001f
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL__SHIFT                       0x00000000
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT                   0x00000003
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT             0x00000004
+#define TP0_DEBUG__REG_CLK_EN__SHIFT                       0x00000015
+#define TP0_DEBUG__PERF_CLK_EN__SHIFT                      0x00000016
+#define TP0_DEBUG__TP_CLK_EN__SHIFT                        0x00000017
+#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT                    0x00000018
+#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT                   0x0000001c
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE__SHIFT                        0x00000000
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT            0x00000001
+#define TP0_CHICKEN__SPARE__SHIFT                          0x00000002
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr__SHIFT                    0x00000006
+#define TCF_DEBUG__TC_MH_send__SHIFT                       0x00000007
+#define TCF_DEBUG__not_FG0_rtr__SHIFT                      0x00000008
+#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT                  0x0000000c
+#define TCF_DEBUG__TCB_ff_stall__SHIFT                     0x0000000d
+#define TCF_DEBUG__TCB_miss_stall__SHIFT                   0x0000000e
+#define TCF_DEBUG__TCA_TCB_stall__SHIFT                    0x0000000f
+#define TCF_DEBUG__PF0_stall__SHIFT                        0x00000010
+#define TCF_DEBUG__TP0_full__SHIFT                         0x00000014
+#define TCF_DEBUG__TPC_full__SHIFT                         0x00000018
+#define TCF_DEBUG__not_TPC_rtr__SHIFT                      0x00000019
+#define TCF_DEBUG__tca_state_rts__SHIFT                    0x0000001a
+#define TCF_DEBUG__tca_rts__SHIFT                          0x0000001b
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full__SHIFT                    0x00000000
+#define TCA_FIFO_DEBUG__tpc_full__SHIFT                    0x00000004
+#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT               0x00000005
+#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT               0x00000006
+#define TCA_FIFO_DEBUG__FW_full__SHIFT                     0x00000007
+#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT                 0x00000008
+#define TCA_FIFO_DEBUG__FW_rts0__SHIFT                     0x0000000c
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT              0x00000010
+#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT                  0x00000011
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT          0x00000000
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts__SHIFT             0x0000000c
+#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT              0x0000000d
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512__SHIFT                   0x00000000
+#define TCB_CORE_DEBUG__tiled__SHIFT                       0x00000001
+#define TCB_CORE_DEBUG__opcode__SHIFT                      0x00000004
+#define TCB_CORE_DEBUG__format__SHIFT                      0x00000008
+#define TCB_CORE_DEBUG__sector_format__SHIFT               0x00000010
+#define TCB_CORE_DEBUG__sector_format512__SHIFT            0x00000018
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG0_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG0_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG1_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG1_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG2_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG2_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG3_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG3_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT   0x00000004
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT    0x00000006
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT   0x0000000b
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT   0x0000000c
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT            0x0000000f
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT      0x00000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT       0x00000002
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT    0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT             0x00000017
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT         0x00000018
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT          0x00000019
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT         0x0000001a
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT          0x0000001c
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT          0x0000001e
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty__SHIFT                     0x00000010
+#define TCD_INPUT0_DEBUG__full__SHIFT                      0x00000011
+#define TCD_INPUT0_DEBUG__valid_q1__SHIFT                  0x00000014
+#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT                    0x00000015
+#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT              0x00000017
+#define TCD_INPUT0_DEBUG__ip_send__SHIFT                   0x00000018
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT            0x00000019
+#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT                0x0000001a
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT      0x00000000
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT          0x00000002
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT      0x00000003
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT           0x00000004
+#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT               0x00000005
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT              0x00000006
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT             0x00000009
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT         0x0000000a
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT           0x0000000b
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT  0x00000014
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT   0x0000001c
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT      0x0000001d
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT                0x00000004
+#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT                  0x00000005
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT    0x00000006
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT          0x00000007
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT       0x00000009
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT    0x0000000c
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT       0x00000012
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT         0x0000001e
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT         0x0000001f
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT   0x0000000a
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT   0x0000000b
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT         0x00000011
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT       0x00000012
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT          0x00000013
+#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT          0x0000001f
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT          0x00000005
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT           0x00000006
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT       0x00000007
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT       0x00000000
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT       0x00000008
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT                 0x00000009
+#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT                 0x0000000a
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT      0x0000000b
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT                0x0000000c
+#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT                0x0000000d
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT           0x00000010
+#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT              0x00000018
+#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT            0x00000019
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT  0x0000001a
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT  0x0000001b
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT  0x0000001c
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT  0x0000001d
+#define TCO_QUAD0_DEBUG0__busy__SHIFT                      0x0000001e
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT                 0x00000000
+#define TCO_QUAD0_DEBUG1__empty__SHIFT                     0x00000001
+#define TCO_QUAD0_DEBUG1__full__SHIFT                      0x00000002
+#define TCO_QUAD0_DEBUG1__write_enable__SHIFT              0x00000003
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT            0x00000004
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT             0x0000000b
+#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT           0x00000014
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT         0x00000015
+#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT           0x00000016
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT        0x00000017
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT             0x00000018
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT             0x00000019
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT                 0x0000001a
+#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT                 0x0000001b
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT                0x0000001c
+#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT                0x0000001d
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT          0x0000001e
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT              0x00000000
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT             0x00000004
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT             0x0000000c
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT   0x00000000
+#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT                 0x00000004
+#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT                    0x00000008
+#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT                 0x0000000c
+#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT                   0x00000010
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT               0x00000011
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT          0x00000012
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT      0x00000015
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT     0x00000016
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT               0x00000017
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT               0x00000018
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT           0x00000019
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT    0x0000001b
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT      0x00000000
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT      0x00000010
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT   0x00000010
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT                   0x00000000
+#define SQ_EO_RT__EO_TSTATE_RT__SHIFT                      0x00000010
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT               0x00000000
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT               0x0000000c
+#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT                  0x00000014
+#define SQ_DEBUG_MISC__RESERVED__SHIFT                     0x00000015
+#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT               0x00000017
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT              0x00000019
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT              0x0000001a
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT              0x0000001b
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT              0x0000001c
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT            0x00000000
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT       0x00000008
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT      0x00000010
+#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT               0x00000018
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT      0x00000000
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT      0x00000000
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT        0x00000003
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT      0x00000004
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT        0x00000007
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT            0x00000008
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT     0x00000000
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT       0x00000003
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT     0x00000004
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT       0x00000007
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT           0x00000008
+#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT            0x00000012
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016
+
+// SQ_VS_WATCHDOG_TIMER
+#define SQ_VS_WATCHDOG_TIMER__ENABLE__SHIFT                0x00000000
+#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT         0x00000001
+
+// SQ_PS_WATCHDOG_TIMER
+#define SQ_PS_WATCHDOG_TIMER__ENABLE__SHIFT                0x00000000
+#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT         0x00000001
+
+// SQ_INT_CNTL
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK__SHIFT               0x00000000
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK__SHIFT               0x00000001
+
+// SQ_INT_STATUS
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT__SHIFT          0x00000000
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT__SHIFT          0x00000001
+
+// SQ_INT_ACK
+#define SQ_INT_ACK__PS_WATCHDOG_ACK__SHIFT                 0x00000000
+#define SQ_INT_ACK__VS_WATCHDOG_ACK__SHIFT                 0x00000001
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT               0x00000000
+#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT                0x00000003
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT               0x00000004
+#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT                 0x00000008
+#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT                   0x0000000c
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT           0x0000000f
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT             0x00000014
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT           0x00000005
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT           0x0000000d
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT                      0x00000000
+#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT                  0x00000003
+#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT                      0x00000004
+#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT                      0x00000008
+#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT                  0x0000000b
+#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT                     0x0000000c
+#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT                  0x0000000e
+#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT                      0x00000010
+#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT                  0x00000012
+#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT                     0x00000014
+#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT                  0x00000016
+#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT                     0x00000018
+#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT                  0x0000001a
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT                  0x0000001c
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT           0x00000000
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT         0x00000004
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT            0x0000000c
+#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT                0x0000000f
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT     0x00000010
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT            0x00000000
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT              0x00000001
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT          0x00000005
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT         0x00000006
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT              0x00000009
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT               0x0000000e
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT        0x0000000f
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT                 0x00000010
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT             0x00000011
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT   0x0000001d
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT           0x00000000
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT               0x00000004
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT               0x00000008
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT        0x0000000c
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT         0x00000010
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT            0x00000014
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT                   0x00000015
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT              0x00000000
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT   0x00000000
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT     0x00000000
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT             0x00000000
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT                 0x00000006
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT                 0x0000000c
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT        0x00000013
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT          0x00000019
+#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT                     0x0000001f
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL__SHIFT        0x00000006
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT  0x00000007
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL__SHIFT        0x0000000e
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT           0x0000000f
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT        0x00000010
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT        0x00000014
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT          0x00000018
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT          0x00000019
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT         0x0000001a
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT       0x00000000
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT       0x00000002
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT       0x00000004
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT       0x00000006
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT       0x00000008
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT       0x0000000c
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT       0x0000000e
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT       0x00000010
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT       0x00000012
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT       0x00000014
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT       0x00000016
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT         0x00000019
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT           0x0000001b
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT       0x0000001e
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT       0x0000001f
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT          0x00000006
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT         0x00000007
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT          0x0000000e
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT         0x00000010
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT          0x00000016
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT         0x00000017
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT             0x0000001d
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT             0x0000001e
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT          0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT             0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT             0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT       0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT     0x00000013
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT       0x00000014
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT     0x00000015
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT       0x00000016
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT     0x00000017
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT       0x00000018
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT     0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT       0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT     0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT         0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT         0x0000001e
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT         0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT         0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT         0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT         0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT          0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT             0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT       0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT     0x00000003
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT       0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT     0x00000005
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT       0x00000006
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT     0x00000007
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT       0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT     0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT     0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT         0x0000000d
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT         0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT         0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT         0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT        0x0000000a
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT        0x00000015
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT        0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT        0x0000001a
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT          0x00000005
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT    0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT    0x0000000d
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT    0x0000000f
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT    0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT     0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT     0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT  0x0000000b
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT        0x0000000c
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT    0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT    0x0000001d
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT    0x0000001e
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT      0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT     0x00000012
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT  0x0000001b
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT        0x0000001c
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT         0x00000004
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT        0x00000008
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT    0x00000009
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT       0x0000000b
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT           0x0000000c
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT             0x00000010
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT       0x00000014
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT        0x00000018
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT    0x00000019
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT       0x0000001b
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT           0x0000001c
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT   0x00000013
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT    0x00000019
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT          0x0000001a
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT          0x0000001c
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT          0x0000001e
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT         0x00000010
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT       0x00000012
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT   0x00000015
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT     0x00000018
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT       0x0000001c
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT        0x0000001d
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT  0x00000000
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT    0x00000001
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT           0x00000002
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT             0x00000009
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT           0x00000010
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT           0x00000015
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT           0x0000001a
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT        0x00000013
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT    0x00000019
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT            0x0000001e
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT    0x0000000c
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT     0x0000000d
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT        0x00000010
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT     0x00000017
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT             0x00000010
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED__SHIFT                          0x00000000
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN__SHIFT                        0x00000000
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE__SHIFT                         0x00000000
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA__SHIFT                        0x00000000
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE__SHIFT                           0x00000000
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT                  0x00000000
+#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT                 0x00000001
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT          0x00000002
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT           0x00000000
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT         0x00000002
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE__SHIFT                       0x00000000
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE__SHIFT                       0x00000000
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT               0x00000000
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT               0x00000008
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT               0x00000010
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT               0x00000018
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT                   0x00000000
+#define SQ_CF_LOOP__CF_LOOP_START__SHIFT                   0x00000008
+#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT                    0x00000010
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED__SHIFT                       0x00000000
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN__SHIFT                     0x00000000
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE__SHIFT                      0x00000000
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA__SHIFT                     0x00000000
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE__SHIFT                        0x00000000
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT            0x00000000
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT            0x00000008
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT            0x00000010
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT            0x00000018
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT                0x00000000
+#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT                0x00000008
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT                 0x00000010
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_VS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_PS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT              0x00000000
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT              0x0000000c
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT           0x00000000
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT      0x00000010
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT                 0x00000000
+#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT                 0x00000008
+#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT                0x00000010
+#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT                0x00000011
+#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT                  0x00000012
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT              0x00000013
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT            0x00000014
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT             0x00000018
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT             0x0000001b
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT              0x0000001f
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT                 0x00000000
+#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT                 0x00000004
+#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT                 0x00000008
+#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT                 0x0000000c
+#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT                 0x00000010
+#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT                 0x00000014
+#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT                 0x00000018
+#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT                 0x0000001c
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT                 0x00000000
+#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT                 0x00000004
+#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT                0x00000008
+#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT                0x0000000c
+#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT                0x00000010
+#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT                0x00000014
+#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT                0x00000018
+#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT                0x0000001c
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_VS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_PS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT         0x00000000
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT        0x00000001
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT             0x00000002
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT              0x00000008
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT            0x00000010
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT             0x00000011
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT               0x00000012
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE__SHIFT                      0x00000000
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT                 0x00000000
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT              0x00000004
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT               0x00000008
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT              0x00000018
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT                  0x00000000
+#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT                  0x00000001
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT              0x00000008
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT              0x00000010
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT          0x00000000
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT    0x00000006
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT            0x00000007
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT       0x00000008
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT           0x00000009
+#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT                0x0000000a
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT        0x0000000d
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT       0x0000000e
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT   0x0000000f
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT          0x00000010
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT           0x00000016
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT          0x00000017
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT           0x00000018
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT           0x00000019
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT           0x0000001a
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT                0x00000000
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT             0x00000003
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT                0x00000004
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT             0x00000007
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT               0x00000008
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3__SHIFT             0x0000000b
+#define MH_CLNT_AXI_ID_REUSE__PAw_ID__SHIFT                0x0000000c
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT           0x00000000
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT          0x00000001
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT           0x00000002
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT         0x00000000
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT        0x00000001
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT         0x00000002
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT          0x00000000
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT         0x00000001
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT          0x00000002
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID__SHIFT                   0x00000000
+#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT                0x00000003
+#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT                  0x00000004
+#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT               0x00000007
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX__SHIFT                        0x00000000
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA__SHIFT                         0x00000000
+
+// MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL__AXI_HALT__SHIFT               0x00000000
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY__SHIFT                     0x00000000
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT           0x00000001
+#define MH_DEBUG_REG00__CP_REQUEST__SHIFT                  0x00000002
+#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT                 0x00000003
+#define MH_DEBUG_REG00__TC_REQUEST__SHIFT                  0x00000004
+#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT                0x00000005
+#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT                 0x00000006
+#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT                   0x00000007
+#define MH_DEBUG_REG00__TCD_FULL__SHIFT                    0x00000008
+#define MH_DEBUG_REG00__RB_REQUEST__SHIFT                  0x00000009
+#define MH_DEBUG_REG00__PA_REQUEST__SHIFT                  0x0000000a
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT             0x0000000b
+#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT                   0x0000000c
+#define MH_DEBUG_REG00__ARQ_FULL__SHIFT                    0x0000000d
+#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT                   0x0000000e
+#define MH_DEBUG_REG00__WDB_FULL__SHIFT                    0x0000000f
+#define MH_DEBUG_REG00__AXI_AVALID__SHIFT                  0x00000010
+#define MH_DEBUG_REG00__AXI_AREADY__SHIFT                  0x00000011
+#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT                 0x00000012
+#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT                 0x00000013
+#define MH_DEBUG_REG00__AXI_WVALID__SHIFT                  0x00000014
+#define MH_DEBUG_REG00__AXI_WREADY__SHIFT                  0x00000015
+#define MH_DEBUG_REG00__AXI_RVALID__SHIFT                  0x00000016
+#define MH_DEBUG_REG00__AXI_RREADY__SHIFT                  0x00000017
+#define MH_DEBUG_REG00__AXI_BVALID__SHIFT                  0x00000018
+#define MH_DEBUG_REG00__AXI_BREADY__SHIFT                  0x00000019
+#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT                0x0000001a
+#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT                0x0000001b
+#define MH_DEBUG_REG00__AXI_RDY_ENA__SHIFT                 0x0000001c
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q__SHIFT                   0x00000000
+#define MH_DEBUG_REG01__CP_RTR_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT                  0x00000002
+#define MH_DEBUG_REG01__CP_TAG_q__SHIFT                    0x00000003
+#define MH_DEBUG_REG01__CP_BLEN_q__SHIFT                   0x00000006
+#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT                  0x00000007
+#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG01__TC_SEND_q__SHIFT                   0x0000000a
+#define MH_DEBUG_REG01__TC_RTR_q__SHIFT                    0x0000000b
+#define MH_DEBUG_REG01__TC_BLEN_q__SHIFT                   0x0000000c
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT                0x0000000e
+#define MH_DEBUG_REG01__TC_MH_written__SHIFT               0x0000000f
+#define MH_DEBUG_REG01__RB_SEND_q__SHIFT                   0x00000010
+#define MH_DEBUG_REG01__RB_RTR_q__SHIFT                    0x00000011
+#define MH_DEBUG_REG01__PA_SEND_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG01__PA_RTR_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT               0x00000003
+#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT                 0x00000004
+#define MH_DEBUG_REG02__RDC_RID__SHIFT                     0x00000007
+#define MH_DEBUG_REG02__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT            0x0000000c
+#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT            0x0000000d
+#define MH_DEBUG_REG02__MH_PA_writeclean__SHIFT            0x0000000e
+#define MH_DEBUG_REG02__BRC_BID__SHIFT                     0x0000000f
+#define MH_DEBUG_REG02__BRC_BRESP__SHIFT                   0x00000012
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT           0x00000000
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT          0x00000000
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG05__CP_MH_write__SHIFT                 0x00000001
+#define MH_DEBUG_REG05__CP_MH_tag__SHIFT                   0x00000002
+#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT               0x00000005
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__CP_MH_be__SHIFT                    0x00000000
+#define MH_DEBUG_REG08__RB_MH_be__SHIFT                    0x00000008
+#define MH_DEBUG_REG08__PA_MH_be__SHIFT                    0x00000010
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG09__VGT_MH_send__SHIFT                 0x00000003
+#define MH_DEBUG_REG09__VGT_MH_tagbe__SHIFT                0x00000004
+#define MH_DEBUG_REG09__VGT_MH_ad_31_5__SHIFT              0x00000005
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG10__TC_MH_send__SHIFT                  0x00000002
+#define MH_DEBUG_REG10__TC_MH_mask__SHIFT                  0x00000003
+#define MH_DEBUG_REG10__TC_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__TC_MH_info__SHIFT                  0x00000000
+#define MH_DEBUG_REG11__TC_MH_send__SHIFT                  0x00000019
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__MH_TC_mcinfo__SHIFT                0x00000000
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send__SHIFT           0x00000019
+#define MH_DEBUG_REG12__TC_MH_written__SHIFT               0x0000001a
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT                 0x00000002
+#define MH_DEBUG_REG13__TC_ROQ_MASK__SHIFT                 0x00000003
+#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5__SHIFT            0x00000005
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__TC_ROQ_INFO__SHIFT                 0x00000000
+#define MH_DEBUG_REG14__TC_ROQ_SEND__SHIFT                 0x00000019
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG15__RB_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG15__RB_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__RB_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG18__PA_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG18__PA_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__PA_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__PA_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG21__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG21__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG21__ALEN_q_2_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG21__ARVALID_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG21__ARREADY_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG21__ARID_q__SHIFT                      0x0000000a
+#define MH_DEBUG_REG21__ARLEN_q_1_0__SHIFT                 0x0000000d
+#define MH_DEBUG_REG21__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG21__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG21__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG21__RID_q__SHIFT                       0x00000012
+#define MH_DEBUG_REG21__WVALID_q__SHIFT                    0x00000015
+#define MH_DEBUG_REG21__WREADY_q__SHIFT                    0x00000016
+#define MH_DEBUG_REG21__WLAST_q__SHIFT                     0x00000017
+#define MH_DEBUG_REG21__WID_q__SHIFT                       0x00000018
+#define MH_DEBUG_REG21__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG21__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG21__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG22__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG22__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG22__ALEN_q_1_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG22__ARVALID_q__SHIFT                   0x00000007
+#define MH_DEBUG_REG22__ARREADY_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG22__ARID_q__SHIFT                      0x00000009
+#define MH_DEBUG_REG22__ARLEN_q_1_1__SHIFT                 0x0000000c
+#define MH_DEBUG_REG22__WVALID_q__SHIFT                    0x0000000d
+#define MH_DEBUG_REG22__WREADY_q__SHIFT                    0x0000000e
+#define MH_DEBUG_REG22__WLAST_q__SHIFT                     0x0000000f
+#define MH_DEBUG_REG22__WID_q__SHIFT                       0x00000010
+#define MH_DEBUG_REG22__WSTRB_q__SHIFT                     0x00000013
+#define MH_DEBUG_REG22__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG22__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG22__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG23__CTRL_ARC_ID__SHIFT                 0x00000001
+#define MH_DEBUG_REG23__CTRL_ARC_PAD__SHIFT                0x00000004
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG24__REG_A__SHIFT                       0x00000002
+#define MH_DEBUG_REG24__REG_RE__SHIFT                      0x00000010
+#define MH_DEBUG_REG24__REG_WE__SHIFT                      0x00000011
+#define MH_DEBUG_REG24__BLOCK_RS__SHIFT                    0x00000012
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__REG_WD__SHIFT                      0x00000000
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__MH_RBBM_busy__SHIFT                0x00000000
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int__SHIFT        0x00000001
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int__SHIFT       0x00000002
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int__SHIFT     0x00000003
+#define MH_DEBUG_REG26__GAT_CLK_ENA__SHIFT                 0x00000004
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override__SHIFT     0x00000005
+#define MH_DEBUG_REG26__CNT_q__SHIFT                       0x00000006
+#define MH_DEBUG_REG26__TCD_EMPTY_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY__SHIFT                0x0000000d
+#define MH_DEBUG_REG26__MH_BUSY_d__SHIFT                   0x0000000e
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY__SHIFT               0x0000000f
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000010
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC__SHIFT 0x00000011
+#define MH_DEBUG_REG26__CP_SEND_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG26__CP_RTR_q__SHIFT                    0x00000013
+#define MH_DEBUG_REG26__VGT_SEND_q__SHIFT                  0x00000014
+#define MH_DEBUG_REG26__VGT_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT               0x00000016
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT            0x00000017
+#define MH_DEBUG_REG26__RB_SEND_q__SHIFT                   0x00000018
+#define MH_DEBUG_REG26__RB_RTR_q__SHIFT                    0x00000019
+#define MH_DEBUG_REG26__PA_SEND_q__SHIFT                   0x0000001a
+#define MH_DEBUG_REG26__PA_RTR_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG26__RDC_VALID__SHIFT                   0x0000001c
+#define MH_DEBUG_REG26__RDC_RLAST__SHIFT                   0x0000001d
+#define MH_DEBUG_REG26__TLBMISS_VALID__SHIFT               0x0000001e
+#define MH_DEBUG_REG26__BRC_VALID__SHIFT                   0x0000001f
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__EFF2_FP_WINNER__SHIFT              0x00000000
+#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out__SHIFT         0x00000003
+#define MH_DEBUG_REG27__EFF1_WINNER__SHIFT                 0x00000006
+#define MH_DEBUG_REG27__ARB_WINNER__SHIFT                  0x00000009
+#define MH_DEBUG_REG27__ARB_WINNER_q__SHIFT                0x0000000c
+#define MH_DEBUG_REG27__EFF1_WIN__SHIFT                    0x0000000f
+#define MH_DEBUG_REG27__KILL_EFF1__SHIFT                   0x00000010
+#define MH_DEBUG_REG27__ARB_HOLD__SHIFT                    0x00000011
+#define MH_DEBUG_REG27__ARB_RTR_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG27__CP_SEND_QUAL__SHIFT                0x00000013
+#define MH_DEBUG_REG27__VGT_SEND_QUAL__SHIFT               0x00000014
+#define MH_DEBUG_REG27__TC_SEND_QUAL__SHIFT                0x00000015
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL__SHIFT           0x00000016
+#define MH_DEBUG_REG27__RB_SEND_QUAL__SHIFT                0x00000017
+#define MH_DEBUG_REG27__PA_SEND_QUAL__SHIFT                0x00000018
+#define MH_DEBUG_REG27__ARB_QUAL__SHIFT                    0x00000019
+#define MH_DEBUG_REG27__CP_EFF1_REQ__SHIFT                 0x0000001a
+#define MH_DEBUG_REG27__VGT_EFF1_REQ__SHIFT                0x0000001b
+#define MH_DEBUG_REG27__TC_EFF1_REQ__SHIFT                 0x0000001c
+#define MH_DEBUG_REG27__RB_EFF1_REQ__SHIFT                 0x0000001d
+#define MH_DEBUG_REG27__TCD_NEARFULL_q__SHIFT              0x0000001e
+#define MH_DEBUG_REG27__TCHOLD_IP_q__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__EFF1_WINNER__SHIFT                 0x00000000
+#define MH_DEBUG_REG28__ARB_WINNER__SHIFT                  0x00000003
+#define MH_DEBUG_REG28__CP_SEND_QUAL__SHIFT                0x00000006
+#define MH_DEBUG_REG28__VGT_SEND_QUAL__SHIFT               0x00000007
+#define MH_DEBUG_REG28__TC_SEND_QUAL__SHIFT                0x00000008
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL__SHIFT           0x00000009
+#define MH_DEBUG_REG28__RB_SEND_QUAL__SHIFT                0x0000000a
+#define MH_DEBUG_REG28__ARB_QUAL__SHIFT                    0x0000000b
+#define MH_DEBUG_REG28__CP_EFF1_REQ__SHIFT                 0x0000000c
+#define MH_DEBUG_REG28__VGT_EFF1_REQ__SHIFT                0x0000000d
+#define MH_DEBUG_REG28__TC_EFF1_REQ__SHIFT                 0x0000000e
+#define MH_DEBUG_REG28__RB_EFF1_REQ__SHIFT                 0x0000000f
+#define MH_DEBUG_REG28__EFF1_WIN__SHIFT                    0x00000010
+#define MH_DEBUG_REG28__KILL_EFF1__SHIFT                   0x00000011
+#define MH_DEBUG_REG28__TCD_NEARFULL_q__SHIFT              0x00000012
+#define MH_DEBUG_REG28__TC_ARB_HOLD__SHIFT                 0x00000013
+#define MH_DEBUG_REG28__ARB_HOLD__SHIFT                    0x00000014
+#define MH_DEBUG_REG28__ARB_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q__SHIFT     0x00000016
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out__SHIFT         0x00000000
+#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d__SHIFT        0x00000003
+#define MH_DEBUG_REG29__LEAST_RECENT_d__SHIFT              0x00000006
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d__SHIFT       0x00000009
+#define MH_DEBUG_REG29__ARB_HOLD__SHIFT                    0x0000000a
+#define MH_DEBUG_REG29__ARB_RTR_q__SHIFT                   0x0000000b
+#define MH_DEBUG_REG29__CLNT_REQ__SHIFT                    0x0000000c
+#define MH_DEBUG_REG29__RECENT_d_0__SHIFT                  0x00000011
+#define MH_DEBUG_REG29__RECENT_d_1__SHIFT                  0x00000014
+#define MH_DEBUG_REG29__RECENT_d_2__SHIFT                  0x00000017
+#define MH_DEBUG_REG29__RECENT_d_3__SHIFT                  0x0000001a
+#define MH_DEBUG_REG29__RECENT_d_4__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__TC_ARB_HOLD__SHIFT                 0x00000000
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK__SHIFT      0x00000001
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK__SHIFT        0x00000002
+#define MH_DEBUG_REG30__TCD_NEARFULL_q__SHIFT              0x00000003
+#define MH_DEBUG_REG30__TCHOLD_IP_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG30__TCHOLD_CNT_q__SHIFT                0x00000005
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q__SHIFT            0x00000009
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q__SHIFT               0x0000000a
+#define MH_DEBUG_REG30__TC_MH_written__SHIFT               0x0000000b
+#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q__SHIFT          0x0000000c
+#define MH_DEBUG_REG30__WBURST_ACTIVE__SHIFT               0x00000013
+#define MH_DEBUG_REG30__WLAST_q__SHIFT                     0x00000014
+#define MH_DEBUG_REG30__WBURST_IP_q__SHIFT                 0x00000015
+#define MH_DEBUG_REG30__WBURST_CNT_q__SHIFT                0x00000016
+#define MH_DEBUG_REG30__CP_SEND_QUAL__SHIFT                0x00000019
+#define MH_DEBUG_REG30__CP_MH_write__SHIFT                 0x0000001a
+#define MH_DEBUG_REG30__RB_SEND_QUAL__SHIFT                0x0000001b
+#define MH_DEBUG_REG30__PA_SEND_QUAL__SHIFT                0x0000001c
+#define MH_DEBUG_REG30__ARB_WINNER__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q__SHIFT         0x00000000
+#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG32__ROQ_MARK_q__SHIFT                  0x00000008
+#define MH_DEBUG_REG32__ROQ_VALID_q__SHIFT                 0x00000010
+#define MH_DEBUG_REG32__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG32__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG32__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG32__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG33__ROQ_MARK_d__SHIFT                  0x00000008
+#define MH_DEBUG_REG33__ROQ_VALID_d__SHIFT                 0x00000010
+#define MH_DEBUG_REG33__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG33__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG33__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG33__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN__SHIFT           0x00000000
+#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ__SHIFT           0x00000008
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN__SHIFT       0x00000010
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ__SHIFT       0x00000018
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG35__ROQ_MARK_q_0__SHIFT                0x00000002
+#define MH_DEBUG_REG35__ROQ_VALID_q_0__SHIFT               0x00000003
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0__SHIFT           0x00000004
+#define MH_DEBUG_REG35__ROQ_ADDR_0__SHIFT                  0x00000005
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG36__ROQ_MARK_q_1__SHIFT                0x00000002
+#define MH_DEBUG_REG36__ROQ_VALID_q_1__SHIFT               0x00000003
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1__SHIFT           0x00000004
+#define MH_DEBUG_REG36__ROQ_ADDR_1__SHIFT                  0x00000005
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG37__ROQ_MARK_q_2__SHIFT                0x00000002
+#define MH_DEBUG_REG37__ROQ_VALID_q_2__SHIFT               0x00000003
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2__SHIFT           0x00000004
+#define MH_DEBUG_REG37__ROQ_ADDR_2__SHIFT                  0x00000005
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG38__ROQ_MARK_q_3__SHIFT                0x00000002
+#define MH_DEBUG_REG38__ROQ_VALID_q_3__SHIFT               0x00000003
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3__SHIFT           0x00000004
+#define MH_DEBUG_REG38__ROQ_ADDR_3__SHIFT                  0x00000005
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG39__ROQ_MARK_q_4__SHIFT                0x00000002
+#define MH_DEBUG_REG39__ROQ_VALID_q_4__SHIFT               0x00000003
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4__SHIFT           0x00000004
+#define MH_DEBUG_REG39__ROQ_ADDR_4__SHIFT                  0x00000005
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG40__ROQ_MARK_q_5__SHIFT                0x00000002
+#define MH_DEBUG_REG40__ROQ_VALID_q_5__SHIFT               0x00000003
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5__SHIFT           0x00000004
+#define MH_DEBUG_REG40__ROQ_ADDR_5__SHIFT                  0x00000005
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG41__ROQ_MARK_q_6__SHIFT                0x00000002
+#define MH_DEBUG_REG41__ROQ_VALID_q_6__SHIFT               0x00000003
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6__SHIFT           0x00000004
+#define MH_DEBUG_REG41__ROQ_ADDR_6__SHIFT                  0x00000005
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG42__ROQ_MARK_q_7__SHIFT                0x00000002
+#define MH_DEBUG_REG42__ROQ_VALID_q_7__SHIFT               0x00000003
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7__SHIFT           0x00000004
+#define MH_DEBUG_REG42__ROQ_ADDR_7__SHIFT                  0x00000005
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_REG_WE_q__SHIFT                0x00000000
+#define MH_DEBUG_REG43__ARB_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG43__ARB_REG_VALID_q__SHIFT             0x00000002
+#define MH_DEBUG_REG43__ARB_RTR_q__SHIFT                   0x00000003
+#define MH_DEBUG_REG43__ARB_REG_RTR__SHIFT                 0x00000004
+#define MH_DEBUG_REG43__WDAT_BURST_RTR__SHIFT              0x00000005
+#define MH_DEBUG_REG43__MMU_RTR__SHIFT                     0x00000006
+#define MH_DEBUG_REG43__ARB_ID_q__SHIFT                    0x00000007
+#define MH_DEBUG_REG43__ARB_WRITE_q__SHIFT                 0x0000000a
+#define MH_DEBUG_REG43__ARB_BLEN_q__SHIFT                  0x0000000b
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY__SHIFT              0x0000000c
+#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q__SHIFT              0x0000000d
+#define MH_DEBUG_REG43__MMU_WE__SHIFT                      0x00000010
+#define MH_DEBUG_REG43__ARQ_RTR__SHIFT                     0x00000011
+#define MH_DEBUG_REG43__MMU_ID__SHIFT                      0x00000012
+#define MH_DEBUG_REG43__MMU_WRITE__SHIFT                   0x00000015
+#define MH_DEBUG_REG43__MMU_BLEN__SHIFT                    0x00000016
+#define MH_DEBUG_REG43__WBURST_IP_q__SHIFT                 0x00000017
+#define MH_DEBUG_REG43__WDAT_REG_WE_q__SHIFT               0x00000018
+#define MH_DEBUG_REG43__WDB_WE__SHIFT                      0x00000019
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4__SHIFT              0x0000001a
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3__SHIFT              0x0000001b
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG44__ARB_ID_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG44__ARB_VAD_q__SHIFT                   0x00000004
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__MMU_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG45__MMU_ID__SHIFT                      0x00000001
+#define MH_DEBUG_REG45__MMU_PAD__SHIFT                     0x00000004
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDAT_REG_WE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG46__WDB_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q__SHIFT            0x00000002
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4__SHIFT              0x00000003
+#define MH_DEBUG_REG46__ARB_WSTRB_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG46__ARB_WLAST__SHIFT                   0x0000000c
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY__SHIFT              0x0000000d
+#define MH_DEBUG_REG46__WDB_FIFO_CNT_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG46__WDC_WDB_RE_q__SHIFT                0x00000013
+#define MH_DEBUG_REG46__WDB_WDC_WID__SHIFT                 0x00000014
+#define MH_DEBUG_REG46__WDB_WDC_WLAST__SHIFT               0x00000017
+#define MH_DEBUG_REG46__WDB_WDC_WSTRB__SHIFT               0x00000018
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0__SHIFT          0x00000000
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32__SHIFT         0x00000000
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY__SHIFT              0x00000000
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY__SHIFT             0x00000001
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY__SHIFT              0x00000002
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE__SHIFT              0x00000003
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS__SHIFT            0x00000004
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q__SHIFT           0x00000005
+#define MH_DEBUG_REG49__INFLT_LIMIT_q__SHIFT               0x00000006
+#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q__SHIFT           0x00000007
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG49__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG49__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG49__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG49__BVALID_q__SHIFT                    0x00000012
+#define MH_DEBUG_REG49__BREADY_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG50__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG50__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND__SHIFT             0x00000003
+#define MH_DEBUG_REG50__TLBMISS_VALID__SHIFT               0x00000004
+#define MH_DEBUG_REG50__RDC_VALID__SHIFT                   0x00000005
+#define MH_DEBUG_REG50__RDC_RID__SHIFT                     0x00000006
+#define MH_DEBUG_REG50__RDC_RLAST__SHIFT                   0x00000009
+#define MH_DEBUG_REG50__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS__SHIFT            0x0000000c
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q__SHIFT           0x0000000d
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q__SHIFT            0x0000000e
+#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q__SHIFT     0x0000000f
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE__SHIFT             0x00000015
+#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q__SHIFT        0x00000016
+#define MH_DEBUG_REG50__CNT_HOLD_q1__SHIFT                 0x0000001c
+#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT__SHIFT           0x00000000
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0__SHIFT      0x00000000
+#define MH_DEBUG_REG52__ARB_WE__SHIFT                      0x00000002
+#define MH_DEBUG_REG52__MMU_RTR__SHIFT                     0x00000003
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4__SHIFT     0x00000004
+#define MH_DEBUG_REG52__ARB_ID_q__SHIFT                    0x0000001a
+#define MH_DEBUG_REG52__ARB_WRITE_q__SHIFT                 0x0000001d
+#define MH_DEBUG_REG52__client_behavior_q__SHIFT           0x0000001e
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__stage1_valid__SHIFT                0x00000000
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q__SHIFT           0x00000001
+#define MH_DEBUG_REG53__pa_in_mpu_range__SHIFT             0x00000002
+#define MH_DEBUG_REG53__tag_match_q__SHIFT                 0x00000003
+#define MH_DEBUG_REG53__tag_miss_q__SHIFT                  0x00000004
+#define MH_DEBUG_REG53__va_in_range_q__SHIFT               0x00000005
+#define MH_DEBUG_REG53__MMU_MISS__SHIFT                    0x00000006
+#define MH_DEBUG_REG53__MMU_READ_MISS__SHIFT               0x00000007
+#define MH_DEBUG_REG53__MMU_WRITE_MISS__SHIFT              0x00000008
+#define MH_DEBUG_REG53__MMU_HIT__SHIFT                     0x00000009
+#define MH_DEBUG_REG53__MMU_READ_HIT__SHIFT                0x0000000a
+#define MH_DEBUG_REG53__MMU_WRITE_HIT__SHIFT               0x0000000b
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS__SHIFT      0x0000000c
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT__SHIFT       0x0000000d
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS__SHIFT   0x0000000e
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT__SHIFT    0x0000000f
+#define MH_DEBUG_REG53__REQ_VA_OFFSET_q__SHIFT             0x00000010
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__ARQ_RTR__SHIFT                     0x00000000
+#define MH_DEBUG_REG54__MMU_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q__SHIFT           0x00000002
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS__SHIFT            0x00000003
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND__SHIFT             0x00000004
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005
+#define MH_DEBUG_REG54__pa_in_mpu_range__SHIFT             0x00000006
+#define MH_DEBUG_REG54__stage1_valid__SHIFT                0x00000007
+#define MH_DEBUG_REG54__stage2_valid__SHIFT                0x00000008
+#define MH_DEBUG_REG54__client_behavior_q__SHIFT           0x00000009
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q__SHIFT           0x0000000b
+#define MH_DEBUG_REG54__tag_match_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG54__tag_miss_q__SHIFT                  0x0000000d
+#define MH_DEBUG_REG54__va_in_range_q__SHIFT               0x0000000e
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q__SHIFT        0x0000000f
+#define MH_DEBUG_REG54__TAG_valid_q__SHIFT                 0x00000010
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG0_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG55__TAG_valid_q_0__SHIFT               0x0000000d
+#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG55__TAG1_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG55__TAG_valid_q_1__SHIFT               0x0000001d
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG2_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG56__TAG_valid_q_2__SHIFT               0x0000000d
+#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG56__TAG3_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG56__TAG_valid_q_3__SHIFT               0x0000001d
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG4_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG57__TAG_valid_q_4__SHIFT               0x0000000d
+#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG57__TAG5_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG57__TAG_valid_q_5__SHIFT               0x0000001d
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG6_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG58__TAG_valid_q_6__SHIFT               0x0000000d
+#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG58__TAG7_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG58__TAG_valid_q_7__SHIFT               0x0000001d
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG8_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG59__TAG_valid_q_8__SHIFT               0x0000000d
+#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG59__TAG9_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG59__TAG_valid_q_9__SHIFT               0x0000001d
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG10_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG60__TAG_valid_q_10__SHIFT              0x0000000d
+#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG60__TAG11_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG60__TAG_valid_q_11__SHIFT              0x0000001d
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__TAG12_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG61__TAG_valid_q_12__SHIFT              0x0000000d
+#define MH_DEBUG_REG61__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG61__TAG13_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG61__TAG_valid_q_13__SHIFT              0x0000001d
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__TAG14_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG62__TAG_valid_q_14__SHIFT              0x0000000d
+#define MH_DEBUG_REG62__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG62__TAG15_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG62__TAG_valid_q_15__SHIFT              0x0000001d
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT                   0x00000000
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT            0x00000001
+#define MH_MMU_CONFIG__RESERVED1__SHIFT                    0x00000002
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT           0x00000004
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT           0x00000006
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT          0x00000008
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT          0x0000000a
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT          0x0000000c
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT          0x0000000e
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT          0x00000010
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT         0x00000012
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT         0x00000014
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT           0x00000016
+#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT           0x00000018
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT           0x00000000
+#define MH_MMU_VA_RANGE__VA_BASE__SHIFT                    0x0000000c
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE__SHIFT                     0x0000000c
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT               0x00000000
+#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT                  0x00000001
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT            0x00000002
+#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT                   0x00000004
+#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT                0x00000007
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT     0x00000009
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT    0x0000000a
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT   0x0000000b
+#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT                   0x0000000c
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT               0x00000005
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT           0x00000000
+#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT            0x00000001
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT                   0x0000000c
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END__SHIFT                     0x0000000c
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT                   0x00000001
+#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT                   0x00000002
+#define WAIT_UNTIL__WAIT_VSYNC__SHIFT                      0x00000003
+#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT                  0x00000004
+#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT                  0x00000005
+#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT                  0x00000006
+#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT                    0x0000000a
+#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT                    0x0000000e
+#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT                    0x0000000f
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT               0x00000010
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT               0x00000011
+#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT                 0x00000014
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT         0x00000004
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT    0x00000005
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT                  0x00000000
+#define RBBM_STATUS__TC_BUSY__SHIFT                        0x00000005
+#define RBBM_STATUS__HIRQ_PENDING__SHIFT                   0x00000008
+#define RBBM_STATUS__CPRQ_PENDING__SHIFT                   0x00000009
+#define RBBM_STATUS__CFRQ_PENDING__SHIFT                   0x0000000a
+#define RBBM_STATUS__PFRQ_PENDING__SHIFT                   0x0000000b
+#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT                0x0000000c
+#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT                   0x0000000e
+#define RBBM_STATUS__CP_NRT_BUSY__SHIFT                    0x00000010
+#define RBBM_STATUS__MH_BUSY__SHIFT                        0x00000012
+#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT              0x00000013
+#define RBBM_STATUS__SX_BUSY__SHIFT                        0x00000015
+#define RBBM_STATUS__TPC_BUSY__SHIFT                       0x00000016
+#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT                   0x00000018
+#define RBBM_STATUS__PA_BUSY__SHIFT                        0x00000019
+#define RBBM_STATUS__VGT_BUSY__SHIFT                       0x0000001a
+#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT                 0x0000001b
+#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT                  0x0000001c
+#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT                   0x0000001e
+#define RBBM_STATUS__GUI_ACTIVE__SHIFT                     0x0000001f
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0__SHIFT           0x00000000
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1__SHIFT           0x00000001
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2__SHIFT           0x00000002
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID__SHIFT             0x00000003
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0__SHIFT              0x00000004
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1__SHIFT              0x00000005
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2__SHIFT              0x00000006
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL__SHIFT                 0x00000007
+#define RBBM_DSPLY__DMI_CH1_NUM_BUFS__SHIFT                0x00000008
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0__SHIFT              0x0000000a
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1__SHIFT              0x0000000b
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2__SHIFT              0x0000000c
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL__SHIFT                 0x0000000d
+#define RBBM_DSPLY__DMI_CH2_NUM_BUFS__SHIFT                0x0000000e
+#define RBBM_DSPLY__DMI_CHANNEL_SELECT__SHIFT              0x00000010
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0__SHIFT              0x00000014
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1__SHIFT              0x00000015
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2__SHIFT              0x00000016
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL__SHIFT                 0x00000017
+#define RBBM_DSPLY__DMI_CH3_NUM_BUFS__SHIFT                0x00000018
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0__SHIFT              0x0000001a
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1__SHIFT              0x0000001b
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2__SHIFT              0x0000001c
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL__SHIFT                 0x0000001d
+#define RBBM_DSPLY__DMI_CH4_NUM_BUFS__SHIFT                0x0000001e
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID__SHIFT       0x00000000
+#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID__SHIFT       0x00000008
+#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID__SHIFT       0x00000010
+#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID__SHIFT       0x00000018
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT                0x00000000
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT          0x00000000
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT         0x00000010
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT             0x00000018
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT             0x00000000
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT                 0x00000000
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT                 0x00000000
+#define RBBM_PERIPHID1__DESIGNER0__SHIFT                   0x00000004
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1__SHIFT                   0x00000000
+#define RBBM_PERIPHID2__REVISION__SHIFT                    0x00000004
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT         0x00000000
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT        0x00000002
+#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT                0x00000004
+#define RBBM_PERIPHID3__CONTINUATION__SHIFT                0x00000007
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT__SHIFT                     0x00000000
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT             0x00000008
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT          0x00000000
+#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT                  0x00000005
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT              0x00000000
+#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT              0x00000002
+#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT              0x00000003
+#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT              0x00000004
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT              0x00000005
+#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT              0x00000006
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT             0x0000000c
+#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT              0x0000000f
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT             0x00000010
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000001
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT      0x00000002
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT  0x00000003
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT   0x00000004
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000005
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT   0x00000008
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT      0x00000009
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT   0x00000014
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000015
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT    0x00000016
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000017
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT     0x00000019
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001a
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT      0x0000001b
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT   0x0000001c
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001d
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT  0x0000001e
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT   0x00000001
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT   0x00000002
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT    0x00000007
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT  0x00000008
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT  0x00000009
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT  0x0000000b
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT              0x00000000
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK__SHIFT           0x00000010
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP__SHIFT             0x00000018
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI__SHIFT                0x00000019
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE__SHIFT    0x0000001d
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE__SHIFT       0x0000001e
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT           0x0000001f
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT                 0x00000000
+
+// RBBM_DEBUG_OUT
+#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT__SHIFT               0x00000000
+
+// RBBM_DEBUG_CNTL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR__SHIFT             0x00000000
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL__SHIFT              0x00000008
+#define RBBM_DEBUG_CNTL__SW_ENABLE__SHIFT                  0x0000000c
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR__SHIFT        0x00000010
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL__SHIFT         0x00000018
+#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB__SHIFT         0x0000001c
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR__SHIFT                      0x00000001
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT              0x00000002
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT           0x00000003
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT           0x00000004
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT       0x00000008
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT               0x00000010
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000011
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT   0x00000012
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000013
+#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT                  0x00000014
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT                 0x00000015
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT                  0x00000016
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT      0x00000017
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT             0x00000018
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT             0x0000001f
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT               0x00000002
+#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT             0x0000001e
+#define RBBM_READ_ERROR__READ_ERROR__SHIFT                 0x0000001f
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT               0x00000000
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT      0x00000001
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT            0x00000013
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT             0x00000000
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT    0x00000001
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT          0x00000013
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT                 0x00000000
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT        0x00000001
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT              0x00000013
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT              0x00000005
+#define MASTER_INT_SIGNAL__SQ_INT_STAT__SHIFT              0x0000001a
+#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT              0x0000001e
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT            0x0000001f
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT   0x00000000
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT        0x00000000
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT        0x00000000
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE__SHIFT                         0x00000005
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT                        0x00000000
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT                        0x00000008
+#define CP_RB_CNTL__BUF_SWAP__SHIFT                        0x00000010
+#define CP_RB_CNTL__RB_POLL_EN__SHIFT                      0x00000014
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT                    0x0000001b
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT                  0x0000001f
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT               0x00000002
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR__SHIFT                         0x00000000
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT                   0x00000000
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR__SHIFT                         0x00000000
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT           0x00000000
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT           0x0000001c
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT               0x00000002
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE__SHIFT                       0x00000002
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT                     0x00000000
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE__SHIFT                       0x00000002
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT                     0x00000000
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE__SHIFT                         0x00000002
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT                       0x00000000
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT          0x00000000
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT          0x00000008
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT           0x00000010
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT                  0x00000010
+#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT                  0x00000018
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT                  0x00000000
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT                   0x00000008
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT                   0x00000010
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT                    0x00000000
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT                       0x00000000
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT            0x00000000
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT            0x00000010
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT         0x00000000
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT         0x00000010
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT         0x00000000
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT         0x00000010
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT          0x00000000
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT          0x00000008
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT                 0x00000000
+#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT                 0x00000010
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT                       0x00000000
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT                       0x00000010
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT                 0x00000000
+#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT                 0x00000001
+#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT                 0x00000002
+#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT                 0x00000003
+#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT                 0x00000004
+#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT                 0x00000005
+#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT                 0x00000006
+#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT                 0x00000007
+#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT                 0x00000008
+#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT                 0x00000009
+#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT                0x0000000a
+#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT                0x0000000b
+#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT                0x0000000c
+#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT                0x0000000d
+#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT                0x0000000e
+#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT                0x0000000f
+#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT                0x00000010
+#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT                0x00000011
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT         0x0000001f
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT                     0x00000000
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT                 0x00000010
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA__SHIFT                       0x00000000
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX__SHIFT                      0x00000000
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT          0x00000019
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT          0x0000001a
+#define CP_ME_CNTL__ME_HALT__SHIFT                         0x0000001c
+#define CP_ME_CNTL__ME_BUSY__SHIFT                         0x0000001d
+#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT                   0x0000001f
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT                 0x00000000
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT                 0x00000000
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR__SHIFT                     0x00000000
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT           0x00000000
+#define CP_DEBUG__PREDICATE_DISABLE__SHIFT                 0x00000017
+#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT               0x00000018
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT           0x00000019
+#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT                0x0000001a
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT               0x0000001b
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT            0x0000001c
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT            0x0000001e
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT            0x0000001f
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT              0x00000000
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT              0x00000000
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT              0x00000000
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT              0x00000000
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT              0x00000000
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT              0x00000000
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT              0x00000000
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT              0x00000000
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT                  0x00000000
+#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT                  0x00000010
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT                  0x00000005
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT             0x00000000
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT              0x00000000
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT              0x00000002
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT              0x00000000
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK__SHIFT                    0x00000013
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT           0x00000017
+#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT              0x00000018
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT      0x00000019
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT        0x0000001a
+#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT                  0x0000001b
+#define CP_INT_CNTL__IB2_INT_MASK__SHIFT                   0x0000001d
+#define CP_INT_CNTL__IB1_INT_MASK__SHIFT                   0x0000001e
+#define CP_INT_CNTL__RB_INT_MASK__SHIFT                    0x0000001f
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT__SHIFT                  0x00000013
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT         0x00000017
+#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT            0x00000018
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT    0x00000019
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT      0x0000001a
+#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT                0x0000001b
+#define CP_INT_STATUS__IB2_INT_STAT__SHIFT                 0x0000001d
+#define CP_INT_STATUS__IB1_INT_STAT__SHIFT                 0x0000001e
+#define CP_INT_STATUS__RB_INT_STAT__SHIFT                  0x0000001f
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK__SHIFT                      0x00000013
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT             0x00000017
+#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT                0x00000018
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT        0x00000019
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT          0x0000001a
+#define CP_INT_ACK__IB_ERROR_ACK__SHIFT                    0x0000001b
+#define CP_INT_ACK__IB2_INT_ACK__SHIFT                     0x0000001d
+#define CP_INT_ACK__IB1_INT_ACK__SHIFT                     0x0000001e
+#define CP_INT_ACK__RB_INT_ACK__SHIFT                      0x0000001f
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT               0x00000000
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT               0x00000000
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT              0x00000000
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT        0x00000008
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT        0x00000000
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT             0x00000000
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT             0x00000000
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT                 0x00000000
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT                 0x00000000
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT             0x00000000
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT             0x00000000
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0__SHIFT                    0x00000000
+#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT                   0x00000001
+#define CP_NV_FLAGS_0__DISCARD_1__SHIFT                    0x00000002
+#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT                   0x00000003
+#define CP_NV_FLAGS_0__DISCARD_2__SHIFT                    0x00000004
+#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT                   0x00000005
+#define CP_NV_FLAGS_0__DISCARD_3__SHIFT                    0x00000006
+#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT                   0x00000007
+#define CP_NV_FLAGS_0__DISCARD_4__SHIFT                    0x00000008
+#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT                   0x00000009
+#define CP_NV_FLAGS_0__DISCARD_5__SHIFT                    0x0000000a
+#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT                   0x0000000b
+#define CP_NV_FLAGS_0__DISCARD_6__SHIFT                    0x0000000c
+#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT                   0x0000000d
+#define CP_NV_FLAGS_0__DISCARD_7__SHIFT                    0x0000000e
+#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT                   0x0000000f
+#define CP_NV_FLAGS_0__DISCARD_8__SHIFT                    0x00000010
+#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT                   0x00000011
+#define CP_NV_FLAGS_0__DISCARD_9__SHIFT                    0x00000012
+#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT                   0x00000013
+#define CP_NV_FLAGS_0__DISCARD_10__SHIFT                   0x00000014
+#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT                  0x00000015
+#define CP_NV_FLAGS_0__DISCARD_11__SHIFT                   0x00000016
+#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT                  0x00000017
+#define CP_NV_FLAGS_0__DISCARD_12__SHIFT                   0x00000018
+#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT                  0x00000019
+#define CP_NV_FLAGS_0__DISCARD_13__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_0__DISCARD_14__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_0__DISCARD_15__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16__SHIFT                   0x00000000
+#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT                  0x00000001
+#define CP_NV_FLAGS_1__DISCARD_17__SHIFT                   0x00000002
+#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT                  0x00000003
+#define CP_NV_FLAGS_1__DISCARD_18__SHIFT                   0x00000004
+#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT                  0x00000005
+#define CP_NV_FLAGS_1__DISCARD_19__SHIFT                   0x00000006
+#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT                  0x00000007
+#define CP_NV_FLAGS_1__DISCARD_20__SHIFT                   0x00000008
+#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT                  0x00000009
+#define CP_NV_FLAGS_1__DISCARD_21__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_1__DISCARD_22__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_1__DISCARD_23__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_1__DISCARD_24__SHIFT                   0x00000010
+#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT                  0x00000011
+#define CP_NV_FLAGS_1__DISCARD_25__SHIFT                   0x00000012
+#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT                  0x00000013
+#define CP_NV_FLAGS_1__DISCARD_26__SHIFT                   0x00000014
+#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT                  0x00000015
+#define CP_NV_FLAGS_1__DISCARD_27__SHIFT                   0x00000016
+#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT                  0x00000017
+#define CP_NV_FLAGS_1__DISCARD_28__SHIFT                   0x00000018
+#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT                  0x00000019
+#define CP_NV_FLAGS_1__DISCARD_29__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_1__DISCARD_30__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_1__DISCARD_31__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32__SHIFT                   0x00000000
+#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT                  0x00000001
+#define CP_NV_FLAGS_2__DISCARD_33__SHIFT                   0x00000002
+#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT                  0x00000003
+#define CP_NV_FLAGS_2__DISCARD_34__SHIFT                   0x00000004
+#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT                  0x00000005
+#define CP_NV_FLAGS_2__DISCARD_35__SHIFT                   0x00000006
+#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT                  0x00000007
+#define CP_NV_FLAGS_2__DISCARD_36__SHIFT                   0x00000008
+#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT                  0x00000009
+#define CP_NV_FLAGS_2__DISCARD_37__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_2__DISCARD_38__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_2__DISCARD_39__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_2__DISCARD_40__SHIFT                   0x00000010
+#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT                  0x00000011
+#define CP_NV_FLAGS_2__DISCARD_41__SHIFT                   0x00000012
+#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT                  0x00000013
+#define CP_NV_FLAGS_2__DISCARD_42__SHIFT                   0x00000014
+#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT                  0x00000015
+#define CP_NV_FLAGS_2__DISCARD_43__SHIFT                   0x00000016
+#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT                  0x00000017
+#define CP_NV_FLAGS_2__DISCARD_44__SHIFT                   0x00000018
+#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT                  0x00000019
+#define CP_NV_FLAGS_2__DISCARD_45__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_2__DISCARD_46__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_2__DISCARD_47__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48__SHIFT                   0x00000000
+#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT                  0x00000001
+#define CP_NV_FLAGS_3__DISCARD_49__SHIFT                   0x00000002
+#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT                  0x00000003
+#define CP_NV_FLAGS_3__DISCARD_50__SHIFT                   0x00000004
+#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT                  0x00000005
+#define CP_NV_FLAGS_3__DISCARD_51__SHIFT                   0x00000006
+#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT                  0x00000007
+#define CP_NV_FLAGS_3__DISCARD_52__SHIFT                   0x00000008
+#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT                  0x00000009
+#define CP_NV_FLAGS_3__DISCARD_53__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_3__DISCARD_54__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_3__DISCARD_55__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_3__DISCARD_56__SHIFT                   0x00000010
+#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT                  0x00000011
+#define CP_NV_FLAGS_3__DISCARD_57__SHIFT                   0x00000012
+#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT                  0x00000013
+#define CP_NV_FLAGS_3__DISCARD_58__SHIFT                   0x00000014
+#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT                  0x00000015
+#define CP_NV_FLAGS_3__DISCARD_59__SHIFT                   0x00000016
+#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT                  0x00000017
+#define CP_NV_FLAGS_3__DISCARD_60__SHIFT                   0x00000018
+#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT                  0x00000019
+#define CP_NV_FLAGS_3__DISCARD_61__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_3__DISCARD_62__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_3__DISCARD_63__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT                  0x0000001f
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT     0x00000000
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT       0x00000000
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER__SHIFT                    0x00000000
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY__SHIFT                        0x00000000
+#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT                    0x00000001
+#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT                 0x00000002
+#define CP_STAT__RBIU_BUSY__SHIFT                          0x00000003
+#define CP_STAT__RCIU_BUSY__SHIFT                          0x00000004
+#define CP_STAT__CSF_RING_BUSY__SHIFT                      0x00000005
+#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT                 0x00000006
+#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT                 0x00000007
+#define CP_STAT__CSF_ST_BUSY__SHIFT                        0x00000009
+#define CP_STAT__CSF_BUSY__SHIFT                           0x0000000a
+#define CP_STAT__RING_QUEUE_BUSY__SHIFT                    0x0000000b
+#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT               0x0000000c
+#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT               0x0000000d
+#define CP_STAT__ST_QUEUE_BUSY__SHIFT                      0x00000010
+#define CP_STAT__PFP_BUSY__SHIFT                           0x00000011
+#define CP_STAT__MEQ_RING_BUSY__SHIFT                      0x00000012
+#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT                 0x00000013
+#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT                 0x00000014
+#define CP_STAT__MIU_WC_STALL__SHIFT                       0x00000015
+#define CP_STAT__CP_NRT_BUSY__SHIFT                        0x00000016
+#define CP_STAT___3D_BUSY__SHIFT                           0x00000017
+#define CP_STAT__ME_BUSY__SHIFT                            0x0000001a
+#define CP_STAT__ME_WC_BUSY__SHIFT                         0x0000001d
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT            0x0000001e
+#define CP_STAT__CP_BUSY__SHIFT                            0x0000001f
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE__SHIFT                        0x00000000
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE__SHIFT                        0x00000000
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT         0x00000000
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT     0x00000008
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT           0x00000009
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT           0x0000000a
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT           0x0000000b
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT           0x0000000c
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT           0x0000000d
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT           0x0000000e
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT           0x0000000f
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT           0x00000010
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA__SHIFT         0x00000011
+#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT             0x00000019
+#define COHER_STATUS_PM4__STATUS__SHIFT                    0x0000001f
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE__SHIFT                       0x00000000
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE__SHIFT                       0x00000000
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT        0x00000000
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT    0x00000008
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT          0x00000009
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT          0x0000000a
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT          0x0000000b
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT          0x0000000c
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT          0x0000000d
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT          0x0000000e
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT          0x0000000f
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT          0x00000010
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA__SHIFT        0x00000011
+#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT            0x00000019
+#define COHER_STATUS_HOST__STATUS__SHIFT                   0x0000001f
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT              0x0000000c
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT              0x00000000
+#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT               0x0000000e
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT                 0x00000000
+#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT             0x00000004
+#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT                 0x00000006
+#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT                 0x00000007
+#define RB_COLOR_INFO__COLOR_SWAP__SHIFT                   0x00000009
+#define RB_COLOR_INFO__COLOR_BASE__SHIFT                   0x0000000c
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT                 0x00000000
+#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT                   0x0000000c
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF__SHIFT               0x00000000
+#define RB_STENCILREFMASK__STENCILMASK__SHIFT              0x00000008
+#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT         0x00000010
+#define RB_STENCILREFMASK__RESERVED0__SHIFT                0x00000018
+#define RB_STENCILREFMASK__RESERVED1__SHIFT                0x00000019
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF__SHIFT                     0x00000000
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED__SHIFT                    0x00000000
+#define RB_COLOR_MASK__WRITE_GREEN__SHIFT                  0x00000001
+#define RB_COLOR_MASK__WRITE_BLUE__SHIFT                   0x00000002
+#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT                  0x00000003
+#define RB_COLOR_MASK__RESERVED2__SHIFT                    0x00000004
+#define RB_COLOR_MASK__RESERVED3__SHIFT                    0x00000005
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED__SHIFT                     0x00000000
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT                 0x00000000
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT                   0x00000000
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT                 0x00000000
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED__SHIFT                       0x00000000
+#define RB_FOG_COLOR__FOG_GREEN__SHIFT                     0x00000008
+#define RB_FOG_COLOR__FOG_BLUE__SHIFT                      0x00000010
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT         0x00000000
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT        0x00000008
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT   0x00000010
+#define RB_STENCILREFMASK_BF__RESERVED4__SHIFT             0x00000018
+#define RB_STENCILREFMASK_BF__RESERVED5__SHIFT             0x00000019
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT             0x00000000
+#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT                   0x00000001
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT             0x00000002
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT             0x00000003
+#define RB_DEPTHCONTROL__ZFUNC__SHIFT                      0x00000004
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT            0x00000007
+#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT                0x00000008
+#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT                0x0000000b
+#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT               0x0000000e
+#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT               0x00000011
+#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT             0x00000014
+#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT             0x00000017
+#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT            0x0000001a
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT            0x0000001d
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT             0x00000000
+#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT             0x00000005
+#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT            0x00000008
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT             0x00000010
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT             0x00000015
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT            0x00000018
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT         0x0000001d
+#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT                0x0000001e
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT                 0x00000000
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT          0x00000003
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT       0x00000004
+#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT              0x00000005
+#define RB_COLORCONTROL__FOG_ENABLE__SHIFT                 0x00000006
+#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT             0x00000007
+#define RB_COLORCONTROL__ROP_CODE__SHIFT                   0x00000008
+#define RB_COLORCONTROL__DITHER_MODE__SHIFT                0x0000000c
+#define RB_COLORCONTROL__DITHER_TYPE__SHIFT                0x0000000e
+#define RB_COLORCONTROL__PIXEL_FOG__SHIFT                  0x00000010
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT      0x00000018
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT      0x0000001a
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT      0x0000001c
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT      0x0000001e
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE__SHIFT                  0x00000000
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT         0x00000000
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT         0x00000000
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT         0x00000003
+#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT                 0x00000004
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT           0x0000000c
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT         0x00000000
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT         0x00000000
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT         0x00000003
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT         0x00000004
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT           0x00000008
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT    0x0000000a
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT    0x0000000c
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT      0x0000000e
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT    0x0000000f
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT     0x00000010
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT    0x00000011
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT         0x00000000
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT         0x0000000d
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT                 0x00000000
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT     0x00000000
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT      0x00000001
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT     0x00000000
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT     0x00000000
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT         0x00000001
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT            0x00000003
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT    0x00000005
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT    0x00000006
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT           0x00000007
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT            0x00000008
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT            0x0000000e
+#define RB_BC_CONTROL__CRC_MODE__SHIFT                     0x0000000f
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT      0x00000010
+#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT                0x00000011
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT             0x00000012
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT    0x00000016
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT        0x00000017
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT    0x0000001b
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d
+#define RB_BC_CONTROL__CRC_SYSTEM__SHIFT                   0x0000001e
+#define RB_BC_CONTROL__RESERVED6__SHIFT                    0x0000001f
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT                   0x00000000
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT           0x00000004
+#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT                  0x0000000e
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA__SHIFT                    0x00000000
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT              0x00000000
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK__SHIFT                       0x00000000
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT             0x00000000
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT             0x00000000
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT           0x00000000
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT           0x00000001
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT           0x00000002
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT           0x00000003
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT          0x00000004
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT          0x00000005
+#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT                   0x00000006
+#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT                   0x00000007
+#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT                   0x00000008
+#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT                   0x00000009
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT          0x0000000a
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT          0x0000000b
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT          0x0000000c
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT          0x0000000d
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT              0x0000000e
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT                   0x00000010
+#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT                   0x00000011
+#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT                   0x00000012
+#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT                   0x00000013
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT            0x00000014
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT            0x00000015
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT            0x00000016
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT            0x00000017
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT         0x00000018
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT         0x00000019
+#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT                   0x0000001a
+#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT                   0x0000001b
+#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT                  0x0000001c
+#define RB_DEBUG_0__C_REQ_FULL__SHIFT                      0x0000001d
+#define RB_DEBUG_0__C_MASK_FULL__SHIFT                     0x0000001e
+#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT                 0x0000001f
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT              0x00000000
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT              0x00000001
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT              0x00000002
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT              0x00000003
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT         0x00000004
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT         0x00000005
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT                  0x00000006
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT                  0x00000007
+#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT                  0x00000008
+#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT                  0x00000009
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT         0x0000000a
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT         0x0000000b
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT         0x0000000c
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT         0x0000000d
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT             0x0000000e
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT             0x0000000f
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT                  0x00000010
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT                  0x00000011
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT              0x00000012
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT              0x00000013
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT           0x00000014
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT           0x00000017
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT        0x00000018
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT        0x00000019
+#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT                  0x0000001a
+#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT                  0x0000001b
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT                 0x0000001c
+#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT                     0x0000001d
+#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT                0x0000001f
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT                 0x00000000
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT               0x00000004
+#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT                 0x0000000b
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT               0x0000000c
+#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT              0x0000000d
+#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT                 0x0000000e
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT              0x00000010
+#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT                    0x00000011
+#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT                    0x00000012
+#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT                     0x00000013
+#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT                     0x00000014
+#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT                     0x00000015
+#define RB_DEBUG_2__Z_TILE_FULL__SHIFT                     0x00000016
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT                0x00000017
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT             0x00000018
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT             0x00000019
+#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT                   0x0000001a
+#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT                   0x0000001b
+#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT                    0x0000001c
+#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT                    0x0000001d
+#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT                    0x0000001f
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID__SHIFT                     0x00000000
+#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT                  0x00000004
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT         0x00000008
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT           0x0000000e
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT             0x0000000f
+#define RB_DEBUG_3__SHD_FULL__SHIFT                        0x00000013
+#define RB_DEBUG_3__SHD_EMPTY__SHIFT                       0x00000014
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT            0x00000017
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT            0x00000018
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT                0x00000019
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT                0x0000001a
+#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT                 0x0000001b
+#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT                 0x0000001c
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT             0x00000000
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT             0x00000001
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT           0x00000002
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT           0x00000003
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT           0x00000004
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT          0x00000005
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT            0x00000006
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT           0x00000007
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT     0x00000008
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT             0x00000009
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT           0x00000000
+
+// RB_BC_SPARES
+#define RB_BC_SPARES__RESERVED__SHIFT                      0x00000000
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT   0x00000009
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h
new file mode 100644
index 000000000000..9e9c7282dcdb
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h
@@ -0,0 +1,52571 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_CP_FIDDLE_H)
+#define _CP_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * CP_RB_BASE struct
+ */
+
+#define CP_RB_BASE_RB_BASE_SIZE        27
+
+#define CP_RB_BASE_RB_BASE_SHIFT       5
+
+#define CP_RB_BASE_RB_BASE_MASK        0xffffffe0
+
+#define CP_RB_BASE_MASK \
+     (CP_RB_BASE_RB_BASE_MASK)
+
+#define CP_RB_BASE(rb_base) \
+     ((rb_base << CP_RB_BASE_RB_BASE_SHIFT))
+
+#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \
+     ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT)
+
+#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \
+     cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int                                : 5;
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+     } cp_rb_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+          unsigned int                                : 5;
+     } cp_rb_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_base_t f;
+} cp_rb_base_u;
+
+
+/*
+ * CP_RB_CNTL struct
+ */
+
+#define CP_RB_CNTL_RB_BUFSZ_SIZE       6
+#define CP_RB_CNTL_RB_BLKSZ_SIZE       6
+#define CP_RB_CNTL_BUF_SWAP_SIZE       2
+#define CP_RB_CNTL_RB_POLL_EN_SIZE     1
+#define CP_RB_CNTL_RB_NO_UPDATE_SIZE   1
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1
+
+#define CP_RB_CNTL_RB_BUFSZ_SHIFT      0
+#define CP_RB_CNTL_RB_BLKSZ_SHIFT      8
+#define CP_RB_CNTL_BUF_SWAP_SHIFT      16
+#define CP_RB_CNTL_RB_POLL_EN_SHIFT    20
+#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT  27
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31
+
+#define CP_RB_CNTL_RB_BUFSZ_MASK       0x0000003f
+#define CP_RB_CNTL_RB_BLKSZ_MASK       0x00003f00
+#define CP_RB_CNTL_BUF_SWAP_MASK       0x00030000
+#define CP_RB_CNTL_RB_POLL_EN_MASK     0x00100000
+#define CP_RB_CNTL_RB_NO_UPDATE_MASK   0x08000000
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000
+
+#define CP_RB_CNTL_MASK \
+     (CP_RB_CNTL_RB_BUFSZ_MASK | \
+      CP_RB_CNTL_RB_BLKSZ_MASK | \
+      CP_RB_CNTL_BUF_SWAP_MASK | \
+      CP_RB_CNTL_RB_POLL_EN_MASK | \
+      CP_RB_CNTL_RB_NO_UPDATE_MASK | \
+      CP_RB_CNTL_RB_RPTR_WR_ENA_MASK)
+
+#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \
+     ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \
+      (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \
+      (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \
+      (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \
+      (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \
+      (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT))
+
+#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+     } cp_rb_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+     } cp_rb_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_cntl_t f;
+} cp_rb_cntl_u;
+
+
+/*
+ * CP_RB_RPTR_ADDR struct
+ */
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc
+
+#define CP_RB_RPTR_ADDR_MASK \
+     (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \
+      CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK)
+
+#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \
+     ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \
+      (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT))
+
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_addr_t f;
+} cp_rb_rptr_addr_u;
+
+
+/*
+ * CP_RB_RPTR struct
+ */
+
+#define CP_RB_RPTR_RB_RPTR_SIZE        20
+
+#define CP_RB_RPTR_RB_RPTR_SHIFT       0
+
+#define CP_RB_RPTR_RB_RPTR_MASK        0x000fffff
+
+#define CP_RB_RPTR_MASK \
+     (CP_RB_RPTR_RB_RPTR_MASK)
+
+#define CP_RB_RPTR(rb_rptr) \
+     ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT))
+
+#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \
+     ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \
+     cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+     } cp_rb_rptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_t f;
+} cp_rb_rptr_u;
+
+
+/*
+ * CP_RB_RPTR_WR struct
+ */
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE  20
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK  0x000fffff
+
+#define CP_RB_RPTR_WR_MASK \
+     (CP_RB_RPTR_WR_RB_RPTR_WR_MASK)
+
+#define CP_RB_RPTR_WR(rb_rptr_wr) \
+     ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT))
+
+#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \
+     ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \
+     cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_wr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+     } cp_rb_rptr_wr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_wr_t f;
+} cp_rb_rptr_wr_u;
+
+
+/*
+ * CP_RB_WPTR struct
+ */
+
+#define CP_RB_WPTR_RB_WPTR_SIZE        20
+
+#define CP_RB_WPTR_RB_WPTR_SHIFT       0
+
+#define CP_RB_WPTR_RB_WPTR_MASK        0x000fffff
+
+#define CP_RB_WPTR_MASK \
+     (CP_RB_WPTR_RB_WPTR_MASK)
+
+#define CP_RB_WPTR(rb_wptr) \
+     ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT))
+
+#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \
+     ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \
+     cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_wptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+     } cp_rb_wptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_t f;
+} cp_rb_wptr_u;
+
+
+/*
+ * CP_RB_WPTR_DELAY struct
+ */
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000
+
+#define CP_RB_WPTR_DELAY_MASK \
+     (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \
+      CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK)
+
+#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \
+     ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \
+      (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT))
+
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_delay_t f;
+} cp_rb_wptr_delay_u;
+
+
+/*
+ * CP_RB_WPTR_BASE struct
+ */
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc
+
+#define CP_RB_WPTR_BASE_MASK \
+     (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \
+      CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK)
+
+#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \
+     ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \
+      (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT))
+
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+     } cp_rb_wptr_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+     } cp_rb_wptr_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_base_t f;
+} cp_rb_wptr_base_u;
+
+
+/*
+ * CP_IB1_BASE struct
+ */
+
+#define CP_IB1_BASE_IB1_BASE_SIZE      30
+
+#define CP_IB1_BASE_IB1_BASE_SHIFT     2
+
+#define CP_IB1_BASE_IB1_BASE_MASK      0xfffffffc
+
+#define CP_IB1_BASE_MASK \
+     (CP_IB1_BASE_IB1_BASE_MASK)
+
+#define CP_IB1_BASE(ib1_base) \
+     ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT))
+
+#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \
+     ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \
+     cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int                                : 2;
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+     } cp_ib1_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib1_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_base_t f;
+} cp_ib1_base_u;
+
+
+/*
+ * CP_IB1_BUFSZ struct
+ */
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE    20
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT   0
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK    0x000fffff
+
+#define CP_IB1_BUFSZ_MASK \
+     (CP_IB1_BUFSZ_IB1_BUFSZ_MASK)
+
+#define CP_IB1_BUFSZ(ib1_bufsz) \
+     ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT))
+
+#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \
+     ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \
+     cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib1_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+     } cp_ib1_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_bufsz_t f;
+} cp_ib1_bufsz_u;
+
+
+/*
+ * CP_IB2_BASE struct
+ */
+
+#define CP_IB2_BASE_IB2_BASE_SIZE      30
+
+#define CP_IB2_BASE_IB2_BASE_SHIFT     2
+
+#define CP_IB2_BASE_IB2_BASE_MASK      0xfffffffc
+
+#define CP_IB2_BASE_MASK \
+     (CP_IB2_BASE_IB2_BASE_MASK)
+
+#define CP_IB2_BASE(ib2_base) \
+     ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT))
+
+#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \
+     ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \
+     cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int                                : 2;
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+     } cp_ib2_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib2_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_base_t f;
+} cp_ib2_base_u;
+
+
+/*
+ * CP_IB2_BUFSZ struct
+ */
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE    20
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT   0
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK    0x000fffff
+
+#define CP_IB2_BUFSZ_MASK \
+     (CP_IB2_BUFSZ_IB2_BUFSZ_MASK)
+
+#define CP_IB2_BUFSZ(ib2_bufsz) \
+     ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT))
+
+#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \
+     ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \
+     cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib2_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+     } cp_ib2_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_bufsz_t f;
+} cp_ib2_bufsz_u;
+
+
+/*
+ * CP_ST_BASE struct
+ */
+
+#define CP_ST_BASE_ST_BASE_SIZE        30
+
+#define CP_ST_BASE_ST_BASE_SHIFT       2
+
+#define CP_ST_BASE_ST_BASE_MASK        0xfffffffc
+
+#define CP_ST_BASE_MASK \
+     (CP_ST_BASE_ST_BASE_MASK)
+
+#define CP_ST_BASE(st_base) \
+     ((st_base << CP_ST_BASE_ST_BASE_SHIFT))
+
+#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \
+     ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT)
+
+#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \
+     cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int                                : 2;
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+     } cp_st_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_st_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_base_t f;
+} cp_st_base_u;
+
+
+/*
+ * CP_ST_BUFSZ struct
+ */
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SIZE      20
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT     0
+
+#define CP_ST_BUFSZ_ST_BUFSZ_MASK      0x000fffff
+
+#define CP_ST_BUFSZ_MASK \
+     (CP_ST_BUFSZ_ST_BUFSZ_MASK)
+
+#define CP_ST_BUFSZ(st_bufsz) \
+     ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT))
+
+#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \
+     ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \
+     cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_st_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+     } cp_st_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_bufsz_t f;
+} cp_st_bufsz_u;
+
+
+/*
+ * CP_QUEUE_THRESHOLDS struct
+ */
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000
+
+#define CP_QUEUE_THRESHOLDS_MASK \
+     (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK)
+
+#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \
+     ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \
+      (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \
+      (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT))
+
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 12;
+     } cp_queue_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int                                : 12;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+     } cp_queue_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_queue_thresholds_t f;
+} cp_queue_thresholds_u;
+
+
+/*
+ * CP_MEQ_THRESHOLDS struct
+ */
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5
+#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16
+#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000
+#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000
+
+#define CP_MEQ_THRESHOLDS_MASK \
+     (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \
+      CP_MEQ_THRESHOLDS_ROQ_END_MASK)
+
+#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \
+     ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \
+      (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT))
+
+#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 16;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+     } cp_meq_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 16;
+     } cp_meq_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_thresholds_t f;
+} cp_meq_thresholds_u;
+
+
+/*
+ * CP_CSQ_AVAIL struct
+ */
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE  7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE  7
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK  0x00007f00
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK  0x007f0000
+
+#define CP_CSQ_AVAIL_MASK \
+     (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK)
+
+#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \
+     ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \
+      (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \
+      (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT))
+
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int                                : 9;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+     } cp_csq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_avail_t f;
+} cp_csq_avail_u;
+
+
+/*
+ * CP_STQ_AVAIL struct
+ */
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE   7
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT  0
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_MASK   0x0000007f
+
+#define CP_STQ_AVAIL_MASK \
+     (CP_STQ_AVAIL_STQ_CNT_ST_MASK)
+
+#define CP_STQ_AVAIL(stq_cnt_st) \
+     ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT))
+
+#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \
+     ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \
+     cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+          unsigned int                                : 25;
+     } cp_stq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int                                : 25;
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+     } cp_stq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_avail_t f;
+} cp_stq_avail_u;
+
+
+/*
+ * CP_MEQ_AVAIL struct
+ */
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SIZE      5
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT     0
+
+#define CP_MEQ_AVAIL_MEQ_CNT_MASK      0x0000001f
+
+#define CP_MEQ_AVAIL_MASK \
+     (CP_MEQ_AVAIL_MEQ_CNT_MASK)
+
+#define CP_MEQ_AVAIL(meq_cnt) \
+     ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT))
+
+#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \
+     ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \
+     cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+          unsigned int                                : 27;
+     } cp_meq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int                                : 27;
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+     } cp_meq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_avail_t f;
+} cp_meq_avail_u;
+
+
+/*
+ * CP_CSQ_RB_STAT struct
+ */
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000
+
+#define CP_CSQ_RB_STAT_MASK \
+     (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \
+      CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK)
+
+#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \
+     ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \
+      (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT))
+
+#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_rb_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+     } cp_csq_rb_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_rb_stat_t f;
+} cp_csq_rb_stat_u;
+
+
+/*
+ * CP_CSQ_IB1_STAT struct
+ */
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000
+
+#define CP_CSQ_IB1_STAT_MASK \
+     (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \
+      CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK)
+
+#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \
+     ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \
+      (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT))
+
+#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib1_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+     } cp_csq_ib1_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib1_stat_t f;
+} cp_csq_ib1_stat_u;
+
+
+/*
+ * CP_CSQ_IB2_STAT struct
+ */
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000
+
+#define CP_CSQ_IB2_STAT_MASK \
+     (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \
+      CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK)
+
+#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \
+     ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \
+      (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT))
+
+#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib2_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+     } cp_csq_ib2_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib2_stat_t f;
+} cp_csq_ib2_stat_u;
+
+
+/*
+ * CP_NON_PREFETCH_CNTRS struct
+ */
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700
+
+#define CP_NON_PREFETCH_CNTRS_MASK \
+     (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \
+      CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK)
+
+#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \
+     ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \
+      (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT))
+
+#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 21;
+     } cp_non_prefetch_cntrs_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int                                : 21;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+     } cp_non_prefetch_cntrs_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_non_prefetch_cntrs_t f;
+} cp_non_prefetch_cntrs_u;
+
+
+/*
+ * CP_STQ_ST_STAT struct
+ */
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000
+
+#define CP_STQ_ST_STAT_MASK \
+     (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \
+      CP_STQ_ST_STAT_STQ_WPTR_ST_MASK)
+
+#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \
+     ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \
+      (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT))
+
+#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+     } cp_stq_st_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+     } cp_stq_st_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_st_stat_t f;
+} cp_stq_st_stat_u;
+
+
+/*
+ * CP_MEQ_STAT struct
+ */
+
+#define CP_MEQ_STAT_MEQ_RPTR_SIZE      10
+#define CP_MEQ_STAT_MEQ_WPTR_SIZE      10
+
+#define CP_MEQ_STAT_MEQ_RPTR_SHIFT     0
+#define CP_MEQ_STAT_MEQ_WPTR_SHIFT     16
+
+#define CP_MEQ_STAT_MEQ_RPTR_MASK      0x000003ff
+#define CP_MEQ_STAT_MEQ_WPTR_MASK      0x03ff0000
+
+#define CP_MEQ_STAT_MASK \
+     (CP_MEQ_STAT_MEQ_RPTR_MASK | \
+      CP_MEQ_STAT_MEQ_WPTR_MASK)
+
+#define CP_MEQ_STAT(meq_rptr, meq_wptr) \
+     ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \
+      (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT))
+
+#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+     } cp_meq_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+     } cp_meq_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_stat_t f;
+} cp_meq_stat_u;
+
+
+/*
+ * CP_MIU_TAG_STAT struct
+ */
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001
+#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002
+#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004
+#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008
+#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010
+#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020
+#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040
+#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080
+#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100
+#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200
+#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400
+#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800
+#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000
+#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000
+#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000
+#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000
+#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000
+#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000
+
+#define CP_MIU_TAG_STAT_MASK \
+     (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \
+      CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK)
+
+#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \
+     ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \
+      (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \
+      (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \
+      (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \
+      (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \
+      (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \
+      (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \
+      (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \
+      (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \
+      (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \
+      (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \
+      (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \
+      (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \
+      (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \
+      (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \
+      (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \
+      (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \
+      (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \
+      (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT))
+
+#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int                                : 13;
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+     } cp_miu_tag_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+          unsigned int                                : 13;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+     } cp_miu_tag_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_miu_tag_stat_t f;
+} cp_miu_tag_stat_u;
+
+
+/*
+ * CP_CMD_INDEX struct
+ */
+
+#define CP_CMD_INDEX_CMD_INDEX_SIZE    7
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2
+
+#define CP_CMD_INDEX_CMD_INDEX_SHIFT   0
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16
+
+#define CP_CMD_INDEX_CMD_INDEX_MASK    0x0000007f
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000
+
+#define CP_CMD_INDEX_MASK \
+     (CP_CMD_INDEX_CMD_INDEX_MASK | \
+      CP_CMD_INDEX_CMD_QUEUE_SEL_MASK)
+
+#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \
+     ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \
+      (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT))
+
+#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 14;
+     } cp_cmd_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int                                : 14;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+     } cp_cmd_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_index_t f;
+} cp_cmd_index_u;
+
+
+/*
+ * CP_CMD_DATA struct
+ */
+
+#define CP_CMD_DATA_CMD_DATA_SIZE      32
+
+#define CP_CMD_DATA_CMD_DATA_SHIFT     0
+
+#define CP_CMD_DATA_CMD_DATA_MASK      0xffffffff
+
+#define CP_CMD_DATA_MASK \
+     (CP_CMD_DATA_CMD_DATA_MASK)
+
+#define CP_CMD_DATA(cmd_data) \
+     ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT))
+
+#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \
+     ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \
+     cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_data_t f;
+} cp_cmd_data_u;
+
+
+/*
+ * CP_ME_CNTL struct
+ */
+
+#define CP_ME_CNTL_ME_STATMUX_SIZE     16
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_ME_HALT_SIZE        1
+#define CP_ME_CNTL_ME_BUSY_SIZE        1
+#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE  1
+
+#define CP_ME_CNTL_ME_STATMUX_SHIFT    0
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26
+#define CP_ME_CNTL_ME_HALT_SHIFT       28
+#define CP_ME_CNTL_ME_BUSY_SHIFT       29
+#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31
+
+#define CP_ME_CNTL_ME_STATMUX_MASK     0x0000ffff
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000
+#define CP_ME_CNTL_ME_HALT_MASK        0x10000000
+#define CP_ME_CNTL_ME_BUSY_MASK        0x20000000
+#define CP_ME_CNTL_PROG_CNT_SIZE_MASK  0x80000000
+
+#define CP_ME_CNTL_MASK \
+     (CP_ME_CNTL_ME_STATMUX_MASK | \
+      CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_ME_HALT_MASK | \
+      CP_ME_CNTL_ME_BUSY_MASK | \
+      CP_ME_CNTL_PROG_CNT_SIZE_MASK)
+
+#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \
+     ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \
+      (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \
+      (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \
+      (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT))
+
+#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+          unsigned int                                : 9;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+     } cp_me_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 9;
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+     } cp_me_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cntl_t f;
+} cp_me_cntl_u;
+
+
+/*
+ * CP_ME_STATUS struct
+ */
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_ME_STATUS_MASK \
+     (CP_ME_STATUS_ME_DEBUG_DATA_MASK)
+
+#define CP_ME_STATUS(me_debug_data) \
+     ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT))
+
+#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \
+     ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \
+     cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_status_t f;
+} cp_me_status_u;
+
+
+/*
+ * CP_ME_RAM_WADDR struct
+ */
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_WADDR_MASK \
+     (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK)
+
+#define CP_ME_RAM_WADDR(me_ram_waddr) \
+     ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT))
+
+#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \
+     ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \
+     cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_waddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+     } cp_me_ram_waddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_waddr_t f;
+} cp_me_ram_waddr_u;
+
+
+/*
+ * CP_ME_RAM_RADDR struct
+ */
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_RADDR_MASK \
+     (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK)
+
+#define CP_ME_RAM_RADDR(me_ram_raddr) \
+     ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT))
+
+#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \
+     ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \
+     cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_raddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+     } cp_me_ram_raddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_raddr_t f;
+} cp_me_ram_raddr_u;
+
+
+/*
+ * CP_ME_RAM_DATA struct
+ */
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff
+
+#define CP_ME_RAM_DATA_MASK \
+     (CP_ME_RAM_DATA_ME_RAM_DATA_MASK)
+
+#define CP_ME_RAM_DATA(me_ram_data) \
+     ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT))
+
+#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \
+     ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \
+     cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_data_t f;
+} cp_me_ram_data_u;
+
+
+/*
+ * CP_ME_RDADDR struct
+ */
+
+#define CP_ME_RDADDR_ME_RDADDR_SIZE    32
+
+#define CP_ME_RDADDR_ME_RDADDR_SHIFT   0
+
+#define CP_ME_RDADDR_ME_RDADDR_MASK    0xffffffff
+
+#define CP_ME_RDADDR_MASK \
+     (CP_ME_RDADDR_ME_RDADDR_MASK)
+
+#define CP_ME_RDADDR(me_rdaddr) \
+     ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT))
+
+#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \
+     ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \
+     cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_rdaddr_t f;
+} cp_me_rdaddr_u;
+
+
+/*
+ * CP_DEBUG struct
+ */
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23
+#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0
+#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff
+#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000
+#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000
+#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000
+
+#define CP_DEBUG_MASK \
+     (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \
+      CP_DEBUG_PREDICATE_DISABLE_MASK | \
+      CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \
+      CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \
+      CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \
+      CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \
+      CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \
+      CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \
+      CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK)
+
+#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \
+     ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \
+      (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \
+      (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \
+      (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \
+      (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \
+      (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \
+      (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \
+      (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \
+      (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT))
+
+#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \
+     ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \
+     ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+     } cp_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+     } cp_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_debug_t f;
+} cp_debug_u;
+
+
+/*
+ * SCRATCH_REG0 struct
+ */
+
+#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32
+
+#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0
+
+#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff
+
+#define SCRATCH_REG0_MASK \
+     (SCRATCH_REG0_SCRATCH_REG0_MASK)
+
+#define SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT))
+
+#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \
+     scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg0_t f;
+} scratch_reg0_u;
+
+
+/*
+ * SCRATCH_REG1 struct
+ */
+
+#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32
+
+#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0
+
+#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff
+
+#define SCRATCH_REG1_MASK \
+     (SCRATCH_REG1_SCRATCH_REG1_MASK)
+
+#define SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT))
+
+#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \
+     scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg1_t f;
+} scratch_reg1_u;
+
+
+/*
+ * SCRATCH_REG2 struct
+ */
+
+#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32
+
+#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0
+
+#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff
+
+#define SCRATCH_REG2_MASK \
+     (SCRATCH_REG2_SCRATCH_REG2_MASK)
+
+#define SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT))
+
+#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \
+     scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg2_t f;
+} scratch_reg2_u;
+
+
+/*
+ * SCRATCH_REG3 struct
+ */
+
+#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32
+
+#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0
+
+#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff
+
+#define SCRATCH_REG3_MASK \
+     (SCRATCH_REG3_SCRATCH_REG3_MASK)
+
+#define SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT))
+
+#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \
+     scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg3_t f;
+} scratch_reg3_u;
+
+
+/*
+ * SCRATCH_REG4 struct
+ */
+
+#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32
+
+#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0
+
+#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff
+
+#define SCRATCH_REG4_MASK \
+     (SCRATCH_REG4_SCRATCH_REG4_MASK)
+
+#define SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT))
+
+#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \
+     scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg4_t f;
+} scratch_reg4_u;
+
+
+/*
+ * SCRATCH_REG5 struct
+ */
+
+#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32
+
+#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0
+
+#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff
+
+#define SCRATCH_REG5_MASK \
+     (SCRATCH_REG5_SCRATCH_REG5_MASK)
+
+#define SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT))
+
+#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \
+     scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg5_t f;
+} scratch_reg5_u;
+
+
+/*
+ * SCRATCH_REG6 struct
+ */
+
+#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32
+
+#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0
+
+#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff
+
+#define SCRATCH_REG6_MASK \
+     (SCRATCH_REG6_SCRATCH_REG6_MASK)
+
+#define SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT))
+
+#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \
+     scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg6_t f;
+} scratch_reg6_u;
+
+
+/*
+ * SCRATCH_REG7 struct
+ */
+
+#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32
+
+#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0
+
+#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff
+
+#define SCRATCH_REG7_MASK \
+     (SCRATCH_REG7_SCRATCH_REG7_MASK)
+
+#define SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT))
+
+#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \
+     scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg7_t f;
+} scratch_reg7_u;
+
+
+/*
+ * SCRATCH_UMSK struct
+ */
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8
+#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0
+#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff
+#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000
+
+#define SCRATCH_UMSK_MASK \
+     (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \
+      SCRATCH_UMSK_SCRATCH_SWAP_MASK)
+
+#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \
+     ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \
+      (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT))
+
+#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 14;
+     } scratch_umsk_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int                                : 14;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+     } scratch_umsk_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_umsk_t f;
+} scratch_umsk_u;
+
+
+/*
+ * SCRATCH_ADDR struct
+ */
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0
+
+#define SCRATCH_ADDR_MASK \
+     (SCRATCH_ADDR_SCRATCH_ADDR_MASK)
+
+#define SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT))
+
+#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \
+     scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int                                : 5;
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+     } scratch_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+          unsigned int                                : 5;
+     } scratch_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_addr_t f;
+} scratch_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_SRC struct
+ */
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_VS_EVENT_SRC_MASK \
+     (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \
+      CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK)
+
+#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \
+     ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \
+      (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_vs_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int                                : 30;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+     } cp_me_vs_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_src_t f;
+} cp_me_vs_event_src_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_MASK \
+     (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \
+      CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK)
+
+#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \
+     ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \
+      (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_t f;
+} cp_me_vs_event_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_MASK \
+     (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK)
+
+#define CP_ME_VS_EVENT_DATA(vs_done_data) \
+     ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \
+     ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \
+     cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_t f;
+} cp_me_vs_event_data_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \
+      CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \
+     ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \
+      (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_swm_t f;
+} cp_me_vs_event_addr_swm_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_SWM_MASK \
+     (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \
+     ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \
+     ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \
+     cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_swm_t f;
+} cp_me_vs_event_data_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_SRC struct
+ */
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_PS_EVENT_SRC_MASK \
+     (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \
+      CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK)
+
+#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \
+     ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \
+      (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT))
+
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_ps_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int                                : 30;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+     } cp_me_ps_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_src_t f;
+} cp_me_ps_event_src_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_MASK \
+     (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \
+      CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK)
+
+#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \
+     ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \
+      (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_t f;
+} cp_me_ps_event_addr_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_MASK \
+     (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK)
+
+#define CP_ME_PS_EVENT_DATA(ps_done_data) \
+     ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \
+     ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \
+     cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_t f;
+} cp_me_ps_event_data_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \
+      CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \
+     ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \
+      (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_swm_t f;
+} cp_me_ps_event_addr_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_SWM_MASK \
+     (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \
+     ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \
+     ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \
+     cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_swm_t f;
+} cp_me_ps_event_data_swm_u;
+
+
+/*
+ * CP_ME_CF_EVENT_SRC struct
+ */
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001
+
+#define CP_ME_CF_EVENT_SRC_MASK \
+     (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK)
+
+#define CP_ME_CF_EVENT_SRC(cf_done_src) \
+     ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT))
+
+#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \
+     ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \
+     cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+          unsigned int                                : 31;
+     } cp_me_cf_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int                                : 31;
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+     } cp_me_cf_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_src_t f;
+} cp_me_cf_event_src_u;
+
+
+/*
+ * CP_ME_CF_EVENT_ADDR struct
+ */
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_CF_EVENT_ADDR_MASK \
+     (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \
+      CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK)
+
+#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \
+     ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \
+      (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT))
+
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_addr_t f;
+} cp_me_cf_event_addr_u;
+
+
+/*
+ * CP_ME_CF_EVENT_DATA struct
+ */
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_CF_EVENT_DATA_MASK \
+     (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK)
+
+#define CP_ME_CF_EVENT_DATA(cf_done_data) \
+     ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT))
+
+#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \
+     ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \
+     cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_data_t f;
+} cp_me_cf_event_data_u;
+
+
+/*
+ * CP_ME_NRT_ADDR struct
+ */
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_NRT_ADDR_MASK \
+     (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \
+      CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK)
+
+#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \
+     ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \
+      (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT))
+
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+     } cp_me_nrt_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+     } cp_me_nrt_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_addr_t f;
+} cp_me_nrt_addr_u;
+
+
+/*
+ * CP_ME_NRT_DATA struct
+ */
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff
+
+#define CP_ME_NRT_DATA_MASK \
+     (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK)
+
+#define CP_ME_NRT_DATA(nrt_write_data) \
+     ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT))
+
+#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \
+     ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \
+     cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_data_t f;
+} cp_me_nrt_data_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_SRC struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001
+
+#define CP_ME_VS_FETCH_DONE_SRC_MASK \
+     (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \
+     ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \
+     ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \
+     cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+          unsigned int                                : 31;
+     } cp_me_vs_fetch_done_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int                                : 31;
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+     } cp_me_vs_fetch_done_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_src_t f;
+} cp_me_vs_fetch_done_src_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_ADDR struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_FETCH_DONE_ADDR_MASK \
+     (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \
+      CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \
+     ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \
+      (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_addr_t f;
+} cp_me_vs_fetch_done_addr_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_DATA struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_FETCH_DONE_DATA_MASK \
+     (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK)
+
+#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \
+     ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \
+     ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \
+     cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_data_t f;
+} cp_me_vs_fetch_done_data_u;
+
+
+/*
+ * CP_INT_CNTL struct
+ */
+
+#define CP_INT_CNTL_SW_INT_MASK_SIZE   1
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB2_INT_MASK_SIZE  1
+#define CP_INT_CNTL_IB1_INT_MASK_SIZE  1
+#define CP_INT_CNTL_RB_INT_MASK_SIZE   1
+
+#define CP_INT_CNTL_SW_INT_MASK_SHIFT  19
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26
+#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27
+#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29
+#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30
+#define CP_INT_CNTL_RB_INT_MASK_SHIFT  31
+
+#define CP_INT_CNTL_SW_INT_MASK_MASK   0x00080000
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000
+#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000
+#define CP_INT_CNTL_IB2_INT_MASK_MASK  0x20000000
+#define CP_INT_CNTL_IB1_INT_MASK_MASK  0x40000000
+#define CP_INT_CNTL_RB_INT_MASK_MASK   0x80000000
+
+#define CP_INT_CNTL_MASK \
+     (CP_INT_CNTL_SW_INT_MASK_MASK | \
+      CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \
+      CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB2_INT_MASK_MASK | \
+      CP_INT_CNTL_IB1_INT_MASK_MASK | \
+      CP_INT_CNTL_RB_INT_MASK_MASK)
+
+#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \
+     ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \
+      (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \
+      (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \
+      (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \
+      (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \
+      (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \
+      (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \
+      (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \
+      (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT))
+
+#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+     } cp_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_cntl_t f;
+} cp_int_cntl_u;
+
+
+/*
+ * CP_INT_STATUS struct
+ */
+
+#define CP_INT_STATUS_SW_INT_STAT_SIZE 1
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1
+#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1
+#define CP_INT_STATUS_RB_INT_STAT_SIZE 1
+
+#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26
+#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27
+#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29
+#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30
+#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31
+
+#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000
+#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000
+#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000
+
+#define CP_INT_STATUS_MASK \
+     (CP_INT_STATUS_SW_INT_STAT_MASK | \
+      CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \
+      CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB2_INT_STAT_MASK | \
+      CP_INT_STATUS_IB1_INT_STAT_MASK | \
+      CP_INT_STATUS_RB_INT_STAT_MASK)
+
+#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \
+     ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \
+      (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \
+      (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \
+      (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \
+      (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \
+      (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \
+      (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \
+      (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \
+      (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT))
+
+#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+     } cp_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 19;
+     } cp_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_status_t f;
+} cp_int_status_u;
+
+
+/*
+ * CP_INT_ACK struct
+ */
+
+#define CP_INT_ACK_SW_INT_ACK_SIZE     1
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_IB_ERROR_ACK_SIZE   1
+#define CP_INT_ACK_IB2_INT_ACK_SIZE    1
+#define CP_INT_ACK_IB1_INT_ACK_SIZE    1
+#define CP_INT_ACK_RB_INT_ACK_SIZE     1
+
+#define CP_INT_ACK_SW_INT_ACK_SHIFT    19
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26
+#define CP_INT_ACK_IB_ERROR_ACK_SHIFT  27
+#define CP_INT_ACK_IB2_INT_ACK_SHIFT   29
+#define CP_INT_ACK_IB1_INT_ACK_SHIFT   30
+#define CP_INT_ACK_RB_INT_ACK_SHIFT    31
+
+#define CP_INT_ACK_SW_INT_ACK_MASK     0x00080000
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000
+#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000
+#define CP_INT_ACK_IB_ERROR_ACK_MASK   0x08000000
+#define CP_INT_ACK_IB2_INT_ACK_MASK    0x20000000
+#define CP_INT_ACK_IB1_INT_ACK_MASK    0x40000000
+#define CP_INT_ACK_RB_INT_ACK_MASK     0x80000000
+
+#define CP_INT_ACK_MASK \
+     (CP_INT_ACK_SW_INT_ACK_MASK | \
+      CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \
+      CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB2_INT_ACK_MASK | \
+      CP_INT_ACK_IB1_INT_ACK_MASK | \
+      CP_INT_ACK_RB_INT_ACK_MASK)
+
+#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \
+     ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \
+      (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \
+      (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \
+      (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \
+      (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \
+      (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \
+      (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \
+      (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \
+      (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT))
+
+#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+     } cp_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_ack_t f;
+} cp_int_ack_u;
+
+
+/*
+ * CP_PFP_UCODE_ADDR struct
+ */
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff
+
+#define CP_PFP_UCODE_ADDR_MASK \
+     (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK)
+
+#define CP_PFP_UCODE_ADDR(ucode_addr) \
+     ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT))
+
+#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \
+     ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \
+     cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+          unsigned int                                : 23;
+     } cp_pfp_ucode_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int                                : 23;
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+     } cp_pfp_ucode_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_addr_t f;
+} cp_pfp_ucode_addr_u;
+
+
+/*
+ * CP_PFP_UCODE_DATA struct
+ */
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff
+
+#define CP_PFP_UCODE_DATA_MASK \
+     (CP_PFP_UCODE_DATA_UCODE_DATA_MASK)
+
+#define CP_PFP_UCODE_DATA(ucode_data) \
+     ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT))
+
+#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \
+     ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \
+     cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+          unsigned int                                : 8;
+     } cp_pfp_ucode_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int                                : 8;
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+     } cp_pfp_ucode_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_data_t f;
+} cp_pfp_ucode_data_u;
+
+
+/*
+ * CP_PERFMON_CNTL struct
+ */
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300
+
+#define CP_PERFMON_CNTL_MASK \
+     (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \
+      CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK)
+
+#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \
+     ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \
+      (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT))
+
+#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 22;
+     } cp_perfmon_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int                                : 22;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+     } cp_perfmon_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfmon_cntl_t f;
+} cp_perfmon_cntl_u;
+
+
+/*
+ * CP_PERFCOUNTER_SELECT struct
+ */
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f
+
+#define CP_PERFCOUNTER_SELECT_MASK \
+     (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK)
+
+#define CP_PERFCOUNTER_SELECT(perfcount_sel) \
+     ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT))
+
+#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \
+     ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \
+     cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+          unsigned int                                : 26;
+     } cp_perfcounter_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int                                : 26;
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+     } cp_perfcounter_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_select_t f;
+} cp_perfcounter_select_u;
+
+
+/*
+ * CP_PERFCOUNTER_LO struct
+ */
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff
+
+#define CP_PERFCOUNTER_LO_MASK \
+     (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK)
+
+#define CP_PERFCOUNTER_LO(perfcount_lo) \
+     ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT))
+
+#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \
+     ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \
+     cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_lo_t f;
+} cp_perfcounter_lo_u;
+
+
+/*
+ * CP_PERFCOUNTER_HI struct
+ */
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff
+
+#define CP_PERFCOUNTER_HI_MASK \
+     (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK)
+
+#define CP_PERFCOUNTER_HI(perfcount_hi) \
+     ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT))
+
+#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \
+     ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \
+     cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+          unsigned int                                : 16;
+     } cp_perfcounter_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+     } cp_perfcounter_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_hi_t f;
+} cp_perfcounter_hi_u;
+
+
+/*
+ * CP_BIN_MASK_LO struct
+ */
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff
+
+#define CP_BIN_MASK_LO_MASK \
+     (CP_BIN_MASK_LO_BIN_MASK_LO_MASK)
+
+#define CP_BIN_MASK_LO(bin_mask_lo) \
+     ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT))
+
+#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \
+     ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \
+     cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_lo_t f;
+} cp_bin_mask_lo_u;
+
+
+/*
+ * CP_BIN_MASK_HI struct
+ */
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff
+
+#define CP_BIN_MASK_HI_MASK \
+     (CP_BIN_MASK_HI_BIN_MASK_HI_MASK)
+
+#define CP_BIN_MASK_HI(bin_mask_hi) \
+     ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT))
+
+#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \
+     ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \
+     cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_hi_t f;
+} cp_bin_mask_hi_u;
+
+
+/*
+ * CP_BIN_SELECT_LO struct
+ */
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff
+
+#define CP_BIN_SELECT_LO_MASK \
+     (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK)
+
+#define CP_BIN_SELECT_LO(bin_select_lo) \
+     ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT))
+
+#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \
+     ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \
+     cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_lo_t f;
+} cp_bin_select_lo_u;
+
+
+/*
+ * CP_BIN_SELECT_HI struct
+ */
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff
+
+#define CP_BIN_SELECT_HI_MASK \
+     (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK)
+
+#define CP_BIN_SELECT_HI(bin_select_hi) \
+     ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT))
+
+#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \
+     ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \
+     cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_hi_t f;
+} cp_bin_select_hi_u;
+
+
+/*
+ * CP_NV_FLAGS_0 struct
+ */
+
+#define CP_NV_FLAGS_0_DISCARD_0_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_0_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_1_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_1_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_2_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_2_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_3_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_3_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_4_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_4_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_5_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_5_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_6_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_6_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_7_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_7_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_8_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_8_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_9_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_9_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_10_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_11_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_12_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_13_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_14_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_15_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1
+
+#define CP_NV_FLAGS_0_DISCARD_0_SHIFT  0
+#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1
+#define CP_NV_FLAGS_0_DISCARD_1_SHIFT  2
+#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3
+#define CP_NV_FLAGS_0_DISCARD_2_SHIFT  4
+#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5
+#define CP_NV_FLAGS_0_DISCARD_3_SHIFT  6
+#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7
+#define CP_NV_FLAGS_0_DISCARD_4_SHIFT  8
+#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9
+#define CP_NV_FLAGS_0_DISCARD_5_SHIFT  10
+#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11
+#define CP_NV_FLAGS_0_DISCARD_6_SHIFT  12
+#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13
+#define CP_NV_FLAGS_0_DISCARD_7_SHIFT  14
+#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15
+#define CP_NV_FLAGS_0_DISCARD_8_SHIFT  16
+#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17
+#define CP_NV_FLAGS_0_DISCARD_9_SHIFT  18
+#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19
+#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20
+#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21
+#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22
+#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23
+#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24
+#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25
+#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26
+#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27
+#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28
+#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29
+#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30
+#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31
+
+#define CP_NV_FLAGS_0_DISCARD_0_MASK   0x00000001
+#define CP_NV_FLAGS_0_END_RCVD_0_MASK  0x00000002
+#define CP_NV_FLAGS_0_DISCARD_1_MASK   0x00000004
+#define CP_NV_FLAGS_0_END_RCVD_1_MASK  0x00000008
+#define CP_NV_FLAGS_0_DISCARD_2_MASK   0x00000010
+#define CP_NV_FLAGS_0_END_RCVD_2_MASK  0x00000020
+#define CP_NV_FLAGS_0_DISCARD_3_MASK   0x00000040
+#define CP_NV_FLAGS_0_END_RCVD_3_MASK  0x00000080
+#define CP_NV_FLAGS_0_DISCARD_4_MASK   0x00000100
+#define CP_NV_FLAGS_0_END_RCVD_4_MASK  0x00000200
+#define CP_NV_FLAGS_0_DISCARD_5_MASK   0x00000400
+#define CP_NV_FLAGS_0_END_RCVD_5_MASK  0x00000800
+#define CP_NV_FLAGS_0_DISCARD_6_MASK   0x00001000
+#define CP_NV_FLAGS_0_END_RCVD_6_MASK  0x00002000
+#define CP_NV_FLAGS_0_DISCARD_7_MASK   0x00004000
+#define CP_NV_FLAGS_0_END_RCVD_7_MASK  0x00008000
+#define CP_NV_FLAGS_0_DISCARD_8_MASK   0x00010000
+#define CP_NV_FLAGS_0_END_RCVD_8_MASK  0x00020000
+#define CP_NV_FLAGS_0_DISCARD_9_MASK   0x00040000
+#define CP_NV_FLAGS_0_END_RCVD_9_MASK  0x00080000
+#define CP_NV_FLAGS_0_DISCARD_10_MASK  0x00100000
+#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000
+#define CP_NV_FLAGS_0_DISCARD_11_MASK  0x00400000
+#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000
+#define CP_NV_FLAGS_0_DISCARD_12_MASK  0x01000000
+#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000
+#define CP_NV_FLAGS_0_DISCARD_13_MASK  0x04000000
+#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000
+#define CP_NV_FLAGS_0_DISCARD_14_MASK  0x10000000
+#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000
+#define CP_NV_FLAGS_0_DISCARD_15_MASK  0x40000000
+#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000
+
+#define CP_NV_FLAGS_0_MASK \
+     (CP_NV_FLAGS_0_DISCARD_0_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_0_MASK | \
+      CP_NV_FLAGS_0_DISCARD_1_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_1_MASK | \
+      CP_NV_FLAGS_0_DISCARD_2_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_2_MASK | \
+      CP_NV_FLAGS_0_DISCARD_3_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_3_MASK | \
+      CP_NV_FLAGS_0_DISCARD_4_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_4_MASK | \
+      CP_NV_FLAGS_0_DISCARD_5_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_5_MASK | \
+      CP_NV_FLAGS_0_DISCARD_6_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_6_MASK | \
+      CP_NV_FLAGS_0_DISCARD_7_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_7_MASK | \
+      CP_NV_FLAGS_0_DISCARD_8_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_8_MASK | \
+      CP_NV_FLAGS_0_DISCARD_9_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_9_MASK | \
+      CP_NV_FLAGS_0_DISCARD_10_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_10_MASK | \
+      CP_NV_FLAGS_0_DISCARD_11_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_11_MASK | \
+      CP_NV_FLAGS_0_DISCARD_12_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_12_MASK | \
+      CP_NV_FLAGS_0_DISCARD_13_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_13_MASK | \
+      CP_NV_FLAGS_0_DISCARD_14_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_14_MASK | \
+      CP_NV_FLAGS_0_DISCARD_15_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_15_MASK)
+
+#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \
+     ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \
+      (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \
+      (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \
+      (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \
+      (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \
+      (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \
+      (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \
+      (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \
+      (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \
+      (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \
+      (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \
+      (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \
+      (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \
+      (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \
+      (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \
+      (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \
+      (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \
+      (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \
+      (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \
+      (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \
+      (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \
+      (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \
+      (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \
+      (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \
+      (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \
+      (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \
+      (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \
+      (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \
+      (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \
+      (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \
+      (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \
+      (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT))
+
+#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+     } cp_nv_flags_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+     } cp_nv_flags_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_0_t f;
+} cp_nv_flags_0_u;
+
+
+/*
+ * CP_NV_FLAGS_1 struct
+ */
+
+#define CP_NV_FLAGS_1_DISCARD_16_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_17_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_18_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_19_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_20_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_21_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_22_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_23_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_24_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_25_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_26_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_27_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_28_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_29_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_30_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_31_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1
+
+#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0
+#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1
+#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2
+#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3
+#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4
+#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5
+#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6
+#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7
+#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8
+#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9
+#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10
+#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11
+#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12
+#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13
+#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14
+#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15
+#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16
+#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17
+#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18
+#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19
+#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20
+#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21
+#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22
+#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23
+#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24
+#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25
+#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26
+#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27
+#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28
+#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29
+#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30
+#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31
+
+#define CP_NV_FLAGS_1_DISCARD_16_MASK  0x00000001
+#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002
+#define CP_NV_FLAGS_1_DISCARD_17_MASK  0x00000004
+#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008
+#define CP_NV_FLAGS_1_DISCARD_18_MASK  0x00000010
+#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020
+#define CP_NV_FLAGS_1_DISCARD_19_MASK  0x00000040
+#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080
+#define CP_NV_FLAGS_1_DISCARD_20_MASK  0x00000100
+#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200
+#define CP_NV_FLAGS_1_DISCARD_21_MASK  0x00000400
+#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800
+#define CP_NV_FLAGS_1_DISCARD_22_MASK  0x00001000
+#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000
+#define CP_NV_FLAGS_1_DISCARD_23_MASK  0x00004000
+#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000
+#define CP_NV_FLAGS_1_DISCARD_24_MASK  0x00010000
+#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000
+#define CP_NV_FLAGS_1_DISCARD_25_MASK  0x00040000
+#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000
+#define CP_NV_FLAGS_1_DISCARD_26_MASK  0x00100000
+#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000
+#define CP_NV_FLAGS_1_DISCARD_27_MASK  0x00400000
+#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000
+#define CP_NV_FLAGS_1_DISCARD_28_MASK  0x01000000
+#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000
+#define CP_NV_FLAGS_1_DISCARD_29_MASK  0x04000000
+#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000
+#define CP_NV_FLAGS_1_DISCARD_30_MASK  0x10000000
+#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000
+#define CP_NV_FLAGS_1_DISCARD_31_MASK  0x40000000
+#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000
+
+#define CP_NV_FLAGS_1_MASK \
+     (CP_NV_FLAGS_1_DISCARD_16_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_16_MASK | \
+      CP_NV_FLAGS_1_DISCARD_17_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_17_MASK | \
+      CP_NV_FLAGS_1_DISCARD_18_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_18_MASK | \
+      CP_NV_FLAGS_1_DISCARD_19_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_19_MASK | \
+      CP_NV_FLAGS_1_DISCARD_20_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_20_MASK | \
+      CP_NV_FLAGS_1_DISCARD_21_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_21_MASK | \
+      CP_NV_FLAGS_1_DISCARD_22_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_22_MASK | \
+      CP_NV_FLAGS_1_DISCARD_23_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_23_MASK | \
+      CP_NV_FLAGS_1_DISCARD_24_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_24_MASK | \
+      CP_NV_FLAGS_1_DISCARD_25_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_25_MASK | \
+      CP_NV_FLAGS_1_DISCARD_26_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_26_MASK | \
+      CP_NV_FLAGS_1_DISCARD_27_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_27_MASK | \
+      CP_NV_FLAGS_1_DISCARD_28_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_28_MASK | \
+      CP_NV_FLAGS_1_DISCARD_29_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_29_MASK | \
+      CP_NV_FLAGS_1_DISCARD_30_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_30_MASK | \
+      CP_NV_FLAGS_1_DISCARD_31_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_31_MASK)
+
+#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \
+     ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \
+      (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \
+      (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \
+      (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \
+      (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \
+      (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \
+      (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \
+      (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \
+      (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \
+      (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \
+      (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \
+      (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \
+      (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \
+      (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \
+      (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \
+      (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \
+      (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \
+      (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \
+      (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \
+      (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \
+      (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \
+      (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \
+      (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \
+      (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \
+      (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \
+      (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \
+      (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \
+      (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \
+      (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \
+      (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \
+      (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \
+      (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT))
+
+#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+     } cp_nv_flags_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+     } cp_nv_flags_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_1_t f;
+} cp_nv_flags_1_u;
+
+
+/*
+ * CP_NV_FLAGS_2 struct
+ */
+
+#define CP_NV_FLAGS_2_DISCARD_32_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_33_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_34_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_35_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_36_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_37_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_38_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_39_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_40_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_41_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_42_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_43_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_44_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_45_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_46_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_47_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1
+
+#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0
+#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1
+#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2
+#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3
+#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4
+#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5
+#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6
+#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7
+#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8
+#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9
+#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10
+#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11
+#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12
+#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13
+#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14
+#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15
+#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16
+#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17
+#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18
+#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19
+#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20
+#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21
+#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22
+#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23
+#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24
+#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25
+#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26
+#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27
+#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28
+#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29
+#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30
+#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31
+
+#define CP_NV_FLAGS_2_DISCARD_32_MASK  0x00000001
+#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002
+#define CP_NV_FLAGS_2_DISCARD_33_MASK  0x00000004
+#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008
+#define CP_NV_FLAGS_2_DISCARD_34_MASK  0x00000010
+#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020
+#define CP_NV_FLAGS_2_DISCARD_35_MASK  0x00000040
+#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080
+#define CP_NV_FLAGS_2_DISCARD_36_MASK  0x00000100
+#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200
+#define CP_NV_FLAGS_2_DISCARD_37_MASK  0x00000400
+#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800
+#define CP_NV_FLAGS_2_DISCARD_38_MASK  0x00001000
+#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000
+#define CP_NV_FLAGS_2_DISCARD_39_MASK  0x00004000
+#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000
+#define CP_NV_FLAGS_2_DISCARD_40_MASK  0x00010000
+#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000
+#define CP_NV_FLAGS_2_DISCARD_41_MASK  0x00040000
+#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000
+#define CP_NV_FLAGS_2_DISCARD_42_MASK  0x00100000
+#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000
+#define CP_NV_FLAGS_2_DISCARD_43_MASK  0x00400000
+#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000
+#define CP_NV_FLAGS_2_DISCARD_44_MASK  0x01000000
+#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000
+#define CP_NV_FLAGS_2_DISCARD_45_MASK  0x04000000
+#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000
+#define CP_NV_FLAGS_2_DISCARD_46_MASK  0x10000000
+#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000
+#define CP_NV_FLAGS_2_DISCARD_47_MASK  0x40000000
+#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000
+
+#define CP_NV_FLAGS_2_MASK \
+     (CP_NV_FLAGS_2_DISCARD_32_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_32_MASK | \
+      CP_NV_FLAGS_2_DISCARD_33_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_33_MASK | \
+      CP_NV_FLAGS_2_DISCARD_34_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_34_MASK | \
+      CP_NV_FLAGS_2_DISCARD_35_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_35_MASK | \
+      CP_NV_FLAGS_2_DISCARD_36_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_36_MASK | \
+      CP_NV_FLAGS_2_DISCARD_37_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_37_MASK | \
+      CP_NV_FLAGS_2_DISCARD_38_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_38_MASK | \
+      CP_NV_FLAGS_2_DISCARD_39_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_39_MASK | \
+      CP_NV_FLAGS_2_DISCARD_40_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_40_MASK | \
+      CP_NV_FLAGS_2_DISCARD_41_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_41_MASK | \
+      CP_NV_FLAGS_2_DISCARD_42_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_42_MASK | \
+      CP_NV_FLAGS_2_DISCARD_43_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_43_MASK | \
+      CP_NV_FLAGS_2_DISCARD_44_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_44_MASK | \
+      CP_NV_FLAGS_2_DISCARD_45_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_45_MASK | \
+      CP_NV_FLAGS_2_DISCARD_46_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_46_MASK | \
+      CP_NV_FLAGS_2_DISCARD_47_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_47_MASK)
+
+#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \
+     ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \
+      (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \
+      (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \
+      (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \
+      (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \
+      (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \
+      (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \
+      (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \
+      (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \
+      (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \
+      (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \
+      (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \
+      (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \
+      (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \
+      (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \
+      (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \
+      (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \
+      (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \
+      (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \
+      (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \
+      (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \
+      (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \
+      (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \
+      (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \
+      (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \
+      (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \
+      (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \
+      (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \
+      (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \
+      (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \
+      (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \
+      (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT))
+
+#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+     } cp_nv_flags_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+     } cp_nv_flags_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_2_t f;
+} cp_nv_flags_2_u;
+
+
+/*
+ * CP_NV_FLAGS_3 struct
+ */
+
+#define CP_NV_FLAGS_3_DISCARD_48_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_49_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_50_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_51_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_52_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_53_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_54_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_55_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_56_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_57_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_58_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_59_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_60_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_61_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_62_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_63_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1
+
+#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0
+#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1
+#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2
+#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3
+#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4
+#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5
+#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6
+#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7
+#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8
+#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9
+#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10
+#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11
+#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12
+#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13
+#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14
+#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15
+#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16
+#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17
+#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18
+#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19
+#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20
+#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21
+#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22
+#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23
+#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24
+#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25
+#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26
+#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27
+#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28
+#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29
+#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30
+#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31
+
+#define CP_NV_FLAGS_3_DISCARD_48_MASK  0x00000001
+#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002
+#define CP_NV_FLAGS_3_DISCARD_49_MASK  0x00000004
+#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008
+#define CP_NV_FLAGS_3_DISCARD_50_MASK  0x00000010
+#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020
+#define CP_NV_FLAGS_3_DISCARD_51_MASK  0x00000040
+#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080
+#define CP_NV_FLAGS_3_DISCARD_52_MASK  0x00000100
+#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200
+#define CP_NV_FLAGS_3_DISCARD_53_MASK  0x00000400
+#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800
+#define CP_NV_FLAGS_3_DISCARD_54_MASK  0x00001000
+#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000
+#define CP_NV_FLAGS_3_DISCARD_55_MASK  0x00004000
+#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000
+#define CP_NV_FLAGS_3_DISCARD_56_MASK  0x00010000
+#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000
+#define CP_NV_FLAGS_3_DISCARD_57_MASK  0x00040000
+#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000
+#define CP_NV_FLAGS_3_DISCARD_58_MASK  0x00100000
+#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000
+#define CP_NV_FLAGS_3_DISCARD_59_MASK  0x00400000
+#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000
+#define CP_NV_FLAGS_3_DISCARD_60_MASK  0x01000000
+#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000
+#define CP_NV_FLAGS_3_DISCARD_61_MASK  0x04000000
+#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000
+#define CP_NV_FLAGS_3_DISCARD_62_MASK  0x10000000
+#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000
+#define CP_NV_FLAGS_3_DISCARD_63_MASK  0x40000000
+#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000
+
+#define CP_NV_FLAGS_3_MASK \
+     (CP_NV_FLAGS_3_DISCARD_48_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_48_MASK | \
+      CP_NV_FLAGS_3_DISCARD_49_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_49_MASK | \
+      CP_NV_FLAGS_3_DISCARD_50_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_50_MASK | \
+      CP_NV_FLAGS_3_DISCARD_51_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_51_MASK | \
+      CP_NV_FLAGS_3_DISCARD_52_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_52_MASK | \
+      CP_NV_FLAGS_3_DISCARD_53_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_53_MASK | \
+      CP_NV_FLAGS_3_DISCARD_54_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_54_MASK | \
+      CP_NV_FLAGS_3_DISCARD_55_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_55_MASK | \
+      CP_NV_FLAGS_3_DISCARD_56_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_56_MASK | \
+      CP_NV_FLAGS_3_DISCARD_57_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_57_MASK | \
+      CP_NV_FLAGS_3_DISCARD_58_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_58_MASK | \
+      CP_NV_FLAGS_3_DISCARD_59_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_59_MASK | \
+      CP_NV_FLAGS_3_DISCARD_60_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_60_MASK | \
+      CP_NV_FLAGS_3_DISCARD_61_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_61_MASK | \
+      CP_NV_FLAGS_3_DISCARD_62_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_62_MASK | \
+      CP_NV_FLAGS_3_DISCARD_63_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_63_MASK)
+
+#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \
+     ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \
+      (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \
+      (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \
+      (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \
+      (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \
+      (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \
+      (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \
+      (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \
+      (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \
+      (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \
+      (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \
+      (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \
+      (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \
+      (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \
+      (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \
+      (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \
+      (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \
+      (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \
+      (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \
+      (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \
+      (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \
+      (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \
+      (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \
+      (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \
+      (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \
+      (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \
+      (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \
+      (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \
+      (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \
+      (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \
+      (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \
+      (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT))
+
+#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+     } cp_nv_flags_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+     } cp_nv_flags_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_3_t f;
+} cp_nv_flags_3_u;
+
+
+/*
+ * CP_STATE_DEBUG_INDEX struct
+ */
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f
+
+#define CP_STATE_DEBUG_INDEX_MASK \
+     (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK)
+
+#define CP_STATE_DEBUG_INDEX(state_debug_index) \
+     ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT))
+
+#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \
+     ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \
+     cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+          unsigned int                                : 27;
+     } cp_state_debug_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int                                : 27;
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+     } cp_state_debug_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_index_t f;
+} cp_state_debug_index_u;
+
+
+/*
+ * CP_STATE_DEBUG_DATA struct
+ */
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_STATE_DEBUG_DATA_MASK \
+     (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK)
+
+#define CP_STATE_DEBUG_DATA(state_debug_data) \
+     ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT))
+
+#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \
+     ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \
+     cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_data_t f;
+} cp_state_debug_data_u;
+
+
+/*
+ * CP_PROG_COUNTER struct
+ */
+
+#define CP_PROG_COUNTER_COUNTER_SIZE   32
+
+#define CP_PROG_COUNTER_COUNTER_SHIFT  0
+
+#define CP_PROG_COUNTER_COUNTER_MASK   0xffffffff
+
+#define CP_PROG_COUNTER_MASK \
+     (CP_PROG_COUNTER_COUNTER_MASK)
+
+#define CP_PROG_COUNTER(counter) \
+     ((counter << CP_PROG_COUNTER_COUNTER_SHIFT))
+
+#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \
+     ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \
+     cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_prog_counter_t f;
+} cp_prog_counter_u;
+
+
+/*
+ * CP_STAT struct
+ */
+
+#define CP_STAT_MIU_WR_BUSY_SIZE       1
+#define CP_STAT_MIU_RD_REQ_BUSY_SIZE   1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1
+#define CP_STAT_RBIU_BUSY_SIZE         1
+#define CP_STAT_RCIU_BUSY_SIZE         1
+#define CP_STAT_CSF_RING_BUSY_SIZE     1
+#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_CSF_ST_BUSY_SIZE       1
+#define CP_STAT_CSF_BUSY_SIZE          1
+#define CP_STAT_RING_QUEUE_BUSY_SIZE   1
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1
+#define CP_STAT_ST_QUEUE_BUSY_SIZE     1
+#define CP_STAT_PFP_BUSY_SIZE          1
+#define CP_STAT_MEQ_RING_BUSY_SIZE     1
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_MIU_WC_STALL_SIZE      1
+#define CP_STAT_CP_NRT_BUSY_SIZE       1
+#define CP_STAT__3D_BUSY_SIZE          1
+#define CP_STAT_ME_BUSY_SIZE           1
+#define CP_STAT_ME_WC_BUSY_SIZE        1
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1
+#define CP_STAT_CP_BUSY_SIZE           1
+
+#define CP_STAT_MIU_WR_BUSY_SHIFT      0
+#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT  1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2
+#define CP_STAT_RBIU_BUSY_SHIFT        3
+#define CP_STAT_RCIU_BUSY_SHIFT        4
+#define CP_STAT_CSF_RING_BUSY_SHIFT    5
+#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6
+#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7
+#define CP_STAT_CSF_ST_BUSY_SHIFT      9
+#define CP_STAT_CSF_BUSY_SHIFT         10
+#define CP_STAT_RING_QUEUE_BUSY_SHIFT  11
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13
+#define CP_STAT_ST_QUEUE_BUSY_SHIFT    16
+#define CP_STAT_PFP_BUSY_SHIFT         17
+#define CP_STAT_MEQ_RING_BUSY_SHIFT    18
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20
+#define CP_STAT_MIU_WC_STALL_SHIFT     21
+#define CP_STAT_CP_NRT_BUSY_SHIFT      22
+#define CP_STAT__3D_BUSY_SHIFT         23
+#define CP_STAT_ME_BUSY_SHIFT          26
+#define CP_STAT_ME_WC_BUSY_SHIFT       29
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30
+#define CP_STAT_CP_BUSY_SHIFT          31
+
+#define CP_STAT_MIU_WR_BUSY_MASK       0x00000001
+#define CP_STAT_MIU_RD_REQ_BUSY_MASK   0x00000002
+#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004
+#define CP_STAT_RBIU_BUSY_MASK         0x00000008
+#define CP_STAT_RCIU_BUSY_MASK         0x00000010
+#define CP_STAT_CSF_RING_BUSY_MASK     0x00000020
+#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040
+#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080
+#define CP_STAT_CSF_ST_BUSY_MASK       0x00000200
+#define CP_STAT_CSF_BUSY_MASK          0x00000400
+#define CP_STAT_RING_QUEUE_BUSY_MASK   0x00000800
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000
+#define CP_STAT_ST_QUEUE_BUSY_MASK     0x00010000
+#define CP_STAT_PFP_BUSY_MASK          0x00020000
+#define CP_STAT_MEQ_RING_BUSY_MASK     0x00040000
+#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000
+#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000
+#define CP_STAT_MIU_WC_STALL_MASK      0x00200000
+#define CP_STAT_CP_NRT_BUSY_MASK       0x00400000
+#define CP_STAT__3D_BUSY_MASK          0x00800000
+#define CP_STAT_ME_BUSY_MASK           0x04000000
+#define CP_STAT_ME_WC_BUSY_MASK        0x20000000
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000
+#define CP_STAT_CP_BUSY_MASK           0x80000000
+
+#define CP_STAT_MASK \
+     (CP_STAT_MIU_WR_BUSY_MASK | \
+      CP_STAT_MIU_RD_REQ_BUSY_MASK | \
+      CP_STAT_MIU_RD_RETURN_BUSY_MASK | \
+      CP_STAT_RBIU_BUSY_MASK | \
+      CP_STAT_RCIU_BUSY_MASK | \
+      CP_STAT_CSF_RING_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECTS_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECT2_BUSY_MASK | \
+      CP_STAT_CSF_ST_BUSY_MASK | \
+      CP_STAT_CSF_BUSY_MASK | \
+      CP_STAT_RING_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \
+      CP_STAT_ST_QUEUE_BUSY_MASK | \
+      CP_STAT_PFP_BUSY_MASK | \
+      CP_STAT_MEQ_RING_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \
+      CP_STAT_MIU_WC_STALL_MASK | \
+      CP_STAT_CP_NRT_BUSY_MASK | \
+      CP_STAT__3D_BUSY_MASK | \
+      CP_STAT_ME_BUSY_MASK | \
+      CP_STAT_ME_WC_BUSY_MASK | \
+      CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \
+      CP_STAT_CP_BUSY_MASK)
+
+#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \
+     ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \
+      (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \
+      (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \
+      (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \
+      (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \
+      (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \
+      (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \
+      (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \
+      (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \
+      (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \
+      (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \
+      (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \
+      (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \
+      (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \
+      (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \
+      (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \
+      (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \
+      (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \
+      (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \
+      (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \
+      (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \
+      (me_busy << CP_STAT_ME_BUSY_SHIFT) | \
+      (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \
+      (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \
+      (cp_busy << CP_STAT_CP_BUSY_SHIFT))
+
+#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_GET_RBIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_GET_RCIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_PFP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_GET__3D_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_GET_ME_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_GET_CP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT)
+
+#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+     } cp_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+     } cp_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stat_t f;
+} cp_stat_u;
+
+
+/*
+ * BIOS_0_SCRATCH struct
+ */
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_0_SCRATCH_MASK \
+     (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_0_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \
+     ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \
+     bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_0_scratch_t f;
+} bios_0_scratch_u;
+
+
+/*
+ * BIOS_1_SCRATCH struct
+ */
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_1_SCRATCH_MASK \
+     (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_1_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \
+     ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \
+     bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_1_scratch_t f;
+} bios_1_scratch_u;
+
+
+/*
+ * BIOS_2_SCRATCH struct
+ */
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_2_SCRATCH_MASK \
+     (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_2_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \
+     ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \
+     bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_2_scratch_t f;
+} bios_2_scratch_u;
+
+
+/*
+ * BIOS_3_SCRATCH struct
+ */
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_3_SCRATCH_MASK \
+     (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_3_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \
+     ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \
+     bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_3_scratch_t f;
+} bios_3_scratch_u;
+
+
+/*
+ * BIOS_4_SCRATCH struct
+ */
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_4_SCRATCH_MASK \
+     (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_4_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \
+     ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \
+     bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_4_scratch_t f;
+} bios_4_scratch_u;
+
+
+/*
+ * BIOS_5_SCRATCH struct
+ */
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_5_SCRATCH_MASK \
+     (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_5_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \
+     ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \
+     bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_5_scratch_t f;
+} bios_5_scratch_u;
+
+
+/*
+ * BIOS_6_SCRATCH struct
+ */
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_6_SCRATCH_MASK \
+     (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_6_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \
+     ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \
+     bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_6_scratch_t f;
+} bios_6_scratch_u;
+
+
+/*
+ * BIOS_7_SCRATCH struct
+ */
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_7_SCRATCH_MASK \
+     (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_7_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \
+     ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \
+     bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_7_scratch_t f;
+} bios_7_scratch_u;
+
+
+/*
+ * BIOS_8_SCRATCH struct
+ */
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_8_SCRATCH_MASK \
+     (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_8_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \
+     ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \
+     bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_8_scratch_t f;
+} bios_8_scratch_u;
+
+
+/*
+ * BIOS_9_SCRATCH struct
+ */
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_9_SCRATCH_MASK \
+     (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_9_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \
+     ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \
+     bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_9_scratch_t f;
+} bios_9_scratch_u;
+
+
+/*
+ * BIOS_10_SCRATCH struct
+ */
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_10_SCRATCH_MASK \
+     (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_10_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \
+     ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \
+     bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_10_scratch_t f;
+} bios_10_scratch_u;
+
+
+/*
+ * BIOS_11_SCRATCH struct
+ */
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_11_SCRATCH_MASK \
+     (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_11_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \
+     ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \
+     bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_11_scratch_t f;
+} bios_11_scratch_u;
+
+
+/*
+ * BIOS_12_SCRATCH struct
+ */
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_12_SCRATCH_MASK \
+     (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_12_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \
+     ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \
+     bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_12_scratch_t f;
+} bios_12_scratch_u;
+
+
+/*
+ * BIOS_13_SCRATCH struct
+ */
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_13_SCRATCH_MASK \
+     (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_13_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \
+     ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \
+     bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_13_scratch_t f;
+} bios_13_scratch_u;
+
+
+/*
+ * BIOS_14_SCRATCH struct
+ */
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_14_SCRATCH_MASK \
+     (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_14_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \
+     ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \
+     bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_14_scratch_t f;
+} bios_14_scratch_u;
+
+
+/*
+ * BIOS_15_SCRATCH struct
+ */
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_15_SCRATCH_MASK \
+     (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_15_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \
+     ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \
+     bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_15_scratch_t f;
+} bios_15_scratch_u;
+
+
+/*
+ * COHER_SIZE_PM4 struct
+ */
+
+#define COHER_SIZE_PM4_SIZE_SIZE       32
+
+#define COHER_SIZE_PM4_SIZE_SHIFT      0
+
+#define COHER_SIZE_PM4_SIZE_MASK       0xffffffff
+
+#define COHER_SIZE_PM4_MASK \
+     (COHER_SIZE_PM4_SIZE_MASK)
+
+#define COHER_SIZE_PM4(size) \
+     ((size << COHER_SIZE_PM4_SIZE_SHIFT))
+
+#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \
+     ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT)
+
+#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \
+     coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_pm4_t f;
+} coher_size_pm4_u;
+
+
+/*
+ * COHER_BASE_PM4 struct
+ */
+
+#define COHER_BASE_PM4_BASE_SIZE       32
+
+#define COHER_BASE_PM4_BASE_SHIFT      0
+
+#define COHER_BASE_PM4_BASE_MASK       0xffffffff
+
+#define COHER_BASE_PM4_MASK \
+     (COHER_BASE_PM4_BASE_MASK)
+
+#define COHER_BASE_PM4(base) \
+     ((base << COHER_BASE_PM4_BASE_SHIFT))
+
+#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \
+     ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT)
+
+#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \
+     coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_pm4_t f;
+} coher_base_pm4_u;
+
+
+/*
+ * COHER_STATUS_PM4 struct
+ */
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE 1
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_PM4_STATUS_SIZE   1
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT 17
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_PM4_STATUS_SHIFT  31
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK 0x00020000
+#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_PM4_STATUS_MASK   0x80000000
+
+#define COHER_STATUS_PM4_MASK \
+     (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK | \
+      COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_PM4_STATUS_MASK)
+
+#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \
+      (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_PM4_STATUS_SHIFT))
+
+#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COLOR_INFO_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT)
+
+#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COLOR_INFO_ENA(coher_status_pm4_reg, rb_color_info_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int rb_color_info_ena              : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+     } coher_status_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int rb_color_info_ena              : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+     } coher_status_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_pm4_t f;
+} coher_status_pm4_u;
+
+
+/*
+ * COHER_SIZE_HOST struct
+ */
+
+#define COHER_SIZE_HOST_SIZE_SIZE      32
+
+#define COHER_SIZE_HOST_SIZE_SHIFT     0
+
+#define COHER_SIZE_HOST_SIZE_MASK      0xffffffff
+
+#define COHER_SIZE_HOST_MASK \
+     (COHER_SIZE_HOST_SIZE_MASK)
+
+#define COHER_SIZE_HOST(size) \
+     ((size << COHER_SIZE_HOST_SIZE_SHIFT))
+
+#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \
+     ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT)
+
+#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \
+     coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_host_t f;
+} coher_size_host_u;
+
+
+/*
+ * COHER_BASE_HOST struct
+ */
+
+#define COHER_BASE_HOST_BASE_SIZE      32
+
+#define COHER_BASE_HOST_BASE_SHIFT     0
+
+#define COHER_BASE_HOST_BASE_MASK      0xffffffff
+
+#define COHER_BASE_HOST_MASK \
+     (COHER_BASE_HOST_BASE_MASK)
+
+#define COHER_BASE_HOST(base) \
+     ((base << COHER_BASE_HOST_BASE_SHIFT))
+
+#define COHER_BASE_HOST_GET_BASE(coher_base_host) \
+     ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT)
+
+#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \
+     coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_host_t f;
+} coher_base_host_u;
+
+
+/*
+ * COHER_STATUS_HOST struct
+ */
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE 1
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_HOST_STATUS_SIZE  1
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT 17
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_HOST_STATUS_SHIFT 31
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK 0x00020000
+#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_HOST_STATUS_MASK  0x80000000
+
+#define COHER_STATUS_HOST_MASK \
+     (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK | \
+      COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_HOST_STATUS_MASK)
+
+#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \
+      (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_HOST_STATUS_SHIFT))
+
+#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COLOR_INFO_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT)
+
+#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COLOR_INFO_ENA(coher_status_host_reg, rb_color_info_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int rb_color_info_ena              : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+     } coher_status_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int rb_color_info_ena              : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+     } coher_status_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_host_t f;
+} coher_status_host_u;
+
+
+/*
+ * COHER_DEST_BASE_0 struct
+ */
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000
+
+#define COHER_DEST_BASE_0_MASK \
+     (COHER_DEST_BASE_0_DEST_BASE_0_MASK)
+
+#define COHER_DEST_BASE_0(dest_base_0) \
+     ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT))
+
+#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \
+     ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \
+     coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+     } coher_dest_base_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_0_t f;
+} coher_dest_base_0_u;
+
+
+/*
+ * COHER_DEST_BASE_1 struct
+ */
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000
+
+#define COHER_DEST_BASE_1_MASK \
+     (COHER_DEST_BASE_1_DEST_BASE_1_MASK)
+
+#define COHER_DEST_BASE_1(dest_base_1) \
+     ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT))
+
+#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \
+     ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \
+     coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+     } coher_dest_base_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_1_t f;
+} coher_dest_base_1_u;
+
+
+/*
+ * COHER_DEST_BASE_2 struct
+ */
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000
+
+#define COHER_DEST_BASE_2_MASK \
+     (COHER_DEST_BASE_2_DEST_BASE_2_MASK)
+
+#define COHER_DEST_BASE_2(dest_base_2) \
+     ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT))
+
+#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \
+     ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \
+     coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+     } coher_dest_base_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_2_t f;
+} coher_dest_base_2_u;
+
+
+/*
+ * COHER_DEST_BASE_3 struct
+ */
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000
+
+#define COHER_DEST_BASE_3_MASK \
+     (COHER_DEST_BASE_3_DEST_BASE_3_MASK)
+
+#define COHER_DEST_BASE_3(dest_base_3) \
+     ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT))
+
+#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \
+     ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \
+     coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+     } coher_dest_base_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_3_t f;
+} coher_dest_base_3_u;
+
+
+/*
+ * COHER_DEST_BASE_4 struct
+ */
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000
+
+#define COHER_DEST_BASE_4_MASK \
+     (COHER_DEST_BASE_4_DEST_BASE_4_MASK)
+
+#define COHER_DEST_BASE_4(dest_base_4) \
+     ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT))
+
+#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \
+     ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \
+     coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+     } coher_dest_base_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_4_t f;
+} coher_dest_base_4_u;
+
+
+/*
+ * COHER_DEST_BASE_5 struct
+ */
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000
+
+#define COHER_DEST_BASE_5_MASK \
+     (COHER_DEST_BASE_5_DEST_BASE_5_MASK)
+
+#define COHER_DEST_BASE_5(dest_base_5) \
+     ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT))
+
+#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \
+     ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \
+     coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+     } coher_dest_base_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_5_t f;
+} coher_dest_base_5_u;
+
+
+/*
+ * COHER_DEST_BASE_6 struct
+ */
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000
+
+#define COHER_DEST_BASE_6_MASK \
+     (COHER_DEST_BASE_6_DEST_BASE_6_MASK)
+
+#define COHER_DEST_BASE_6(dest_base_6) \
+     ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT))
+
+#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \
+     ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \
+     coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+     } coher_dest_base_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_6_t f;
+} coher_dest_base_6_u;
+
+
+/*
+ * COHER_DEST_BASE_7 struct
+ */
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000
+
+#define COHER_DEST_BASE_7_MASK \
+     (COHER_DEST_BASE_7_DEST_BASE_7_MASK)
+
+#define COHER_DEST_BASE_7(dest_base_7) \
+     ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT))
+
+#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \
+     ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \
+     coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+     } coher_dest_base_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_7_t f;
+} coher_dest_base_7_u;
+
+
+#endif
+
+
+#if !defined (_RBBM_FIDDLE_H)
+#define _RBBM_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  rbbm_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * WAIT_UNTIL struct
+ */
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_VSYNC_SIZE     1
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1
+#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2
+#define WAIT_UNTIL_WAIT_VSYNC_SHIFT    3
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6
+#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT  10
+#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT  14
+#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT  15
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK  0x00000002
+#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK  0x00000004
+#define WAIT_UNTIL_WAIT_VSYNC_MASK     0x00000008
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040
+#define WAIT_UNTIL_WAIT_CMDFIFO_MASK   0x00000400
+#define WAIT_UNTIL_WAIT_2D_IDLE_MASK   0x00004000
+#define WAIT_UNTIL_WAIT_3D_IDLE_MASK   0x00008000
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000
+
+#define WAIT_UNTIL_MASK \
+     (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \
+      WAIT_UNTIL_WAIT_CMDFIFO_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_CMDFIFO_ENTRIES_MASK)
+
+#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \
+     ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \
+      (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \
+      (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \
+      (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \
+      (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \
+      (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \
+      (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \
+      (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \
+      (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \
+      (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \
+      (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \
+      (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT))
+
+#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \
+     ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 1;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int                                : 2;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 8;
+     } wait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 8;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 2;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int                                : 1;
+     } wait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     wait_until_t f;
+} wait_until_u;
+
+
+/*
+ * RBBM_ISYNC_CNTL struct
+ */
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020
+
+#define RBBM_ISYNC_CNTL_MASK \
+     (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \
+      RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK)
+
+#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \
+     ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \
+      (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT))
+
+#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 4;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int                                : 26;
+     } rbbm_isync_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 26;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int                                : 4;
+     } rbbm_isync_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_isync_cntl_t f;
+} rbbm_isync_cntl_u;
+
+
+/*
+ * RBBM_STATUS struct
+ */
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5
+#define RBBM_STATUS_TC_BUSY_SIZE       1
+#define RBBM_STATUS_HIRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CPRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_PFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1
+#define RBBM_STATUS_RBBM_WU_BUSY_SIZE  1
+#define RBBM_STATUS_CP_NRT_BUSY_SIZE   1
+#define RBBM_STATUS_MH_BUSY_SIZE       1
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1
+#define RBBM_STATUS_SX_BUSY_SIZE       1
+#define RBBM_STATUS_TPC_BUSY_SIZE      1
+#define RBBM_STATUS_SC_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_PA_BUSY_SIZE       1
+#define RBBM_STATUS_VGT_BUSY_SIZE      1
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1
+#define RBBM_STATUS_RB_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_GUI_ACTIVE_SIZE    1
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0
+#define RBBM_STATUS_TC_BUSY_SHIFT      5
+#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8
+#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9
+#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10
+#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12
+#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14
+#define RBBM_STATUS_CP_NRT_BUSY_SHIFT  16
+#define RBBM_STATUS_MH_BUSY_SHIFT      18
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19
+#define RBBM_STATUS_SX_BUSY_SHIFT      21
+#define RBBM_STATUS_TPC_BUSY_SHIFT     22
+#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24
+#define RBBM_STATUS_PA_BUSY_SHIFT      25
+#define RBBM_STATUS_VGT_BUSY_SHIFT     26
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28
+#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30
+#define RBBM_STATUS_GUI_ACTIVE_SHIFT   31
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f
+#define RBBM_STATUS_TC_BUSY_MASK       0x00000020
+#define RBBM_STATUS_HIRQ_PENDING_MASK  0x00000100
+#define RBBM_STATUS_CPRQ_PENDING_MASK  0x00000200
+#define RBBM_STATUS_CFRQ_PENDING_MASK  0x00000400
+#define RBBM_STATUS_PFRQ_PENDING_MASK  0x00000800
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000
+#define RBBM_STATUS_RBBM_WU_BUSY_MASK  0x00004000
+#define RBBM_STATUS_CP_NRT_BUSY_MASK   0x00010000
+#define RBBM_STATUS_MH_BUSY_MASK       0x00040000
+#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000
+#define RBBM_STATUS_SX_BUSY_MASK       0x00200000
+#define RBBM_STATUS_TPC_BUSY_MASK      0x00400000
+#define RBBM_STATUS_SC_CNTX_BUSY_MASK  0x01000000
+#define RBBM_STATUS_PA_BUSY_MASK       0x02000000
+#define RBBM_STATUS_VGT_BUSY_MASK      0x04000000
+#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000
+#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000
+#define RBBM_STATUS_RB_CNTX_BUSY_MASK  0x40000000
+#define RBBM_STATUS_GUI_ACTIVE_MASK    0x80000000
+
+#define RBBM_STATUS_MASK \
+     (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \
+      RBBM_STATUS_TC_BUSY_MASK | \
+      RBBM_STATUS_HIRQ_PENDING_MASK | \
+      RBBM_STATUS_CPRQ_PENDING_MASK | \
+      RBBM_STATUS_CFRQ_PENDING_MASK | \
+      RBBM_STATUS_PFRQ_PENDING_MASK | \
+      RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \
+      RBBM_STATUS_RBBM_WU_BUSY_MASK | \
+      RBBM_STATUS_CP_NRT_BUSY_MASK | \
+      RBBM_STATUS_MH_BUSY_MASK | \
+      RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \
+      RBBM_STATUS_SX_BUSY_MASK | \
+      RBBM_STATUS_TPC_BUSY_MASK | \
+      RBBM_STATUS_SC_CNTX_BUSY_MASK | \
+      RBBM_STATUS_PA_BUSY_MASK | \
+      RBBM_STATUS_VGT_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \
+      RBBM_STATUS_RB_CNTX_BUSY_MASK | \
+      RBBM_STATUS_GUI_ACTIVE_MASK)
+
+#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \
+     ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \
+      (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \
+      (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \
+      (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \
+      (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \
+      (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \
+      (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \
+      (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \
+      (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \
+      (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \
+      (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \
+      (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \
+      (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \
+      (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \
+      (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \
+      (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \
+      (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \
+      (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \
+      (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \
+      (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT))
+
+#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+     } rbbm_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int                                : 2;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+     } rbbm_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_status_t f;
+} rbbm_status_u;
+
+
+/*
+ * RBBM_DSPLY struct
+ */
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE 2
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE 2
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT 0
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT 2
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT 3
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT 4
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT 5
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT 6
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT 7
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT 8
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT 10
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT 11
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT 12
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT 13
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT 14
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT 16
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT 20
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT 21
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT 22
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT 23
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT 24
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT 26
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT 27
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT 28
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT 29
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT 30
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK 0x00000008
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK 0x00000010
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK 0x00000020
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK 0x00000040
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK 0x00000080
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK 0x00000300
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK 0x00000400
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK 0x00000800
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK 0x00001000
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK 0x00002000
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK 0x0000c000
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK 0x00030000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK 0x00100000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK 0x00200000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK 0x00400000
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK 0x00800000
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK 0x03000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK 0x04000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK 0x08000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK 0x10000000
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK 0x20000000
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK 0xc0000000
+
+#define RBBM_DSPLY_MASK \
+     (RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK | \
+      RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK | \
+      RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK | \
+      RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK)
+
+#define RBBM_DSPLY(sel_dmi_active_bufid0, sel_dmi_active_bufid1, sel_dmi_active_bufid2, sel_dmi_vsync_valid, dmi_ch1_use_bufid0, dmi_ch1_use_bufid1, dmi_ch1_use_bufid2, dmi_ch1_sw_cntl, dmi_ch1_num_bufs, dmi_ch2_use_bufid0, dmi_ch2_use_bufid1, dmi_ch2_use_bufid2, dmi_ch2_sw_cntl, dmi_ch2_num_bufs, dmi_channel_select, dmi_ch3_use_bufid0, dmi_ch3_use_bufid1, dmi_ch3_use_bufid2, dmi_ch3_sw_cntl, dmi_ch3_num_bufs, dmi_ch4_use_bufid0, dmi_ch4_use_bufid1, dmi_ch4_use_bufid2, dmi_ch4_sw_cntl, dmi_ch4_num_bufs) \
+     ((sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) | \
+      (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) | \
+      (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) | \
+      (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) | \
+      (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) | \
+      (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) | \
+      (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) | \
+      (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) | \
+      (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) | \
+      (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) | \
+      (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) | \
+      (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) | \
+      (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) | \
+      (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) | \
+      (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) | \
+      (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) | \
+      (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) | \
+      (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) | \
+      (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) | \
+      (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) | \
+      (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) | \
+      (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) | \
+      (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) | \
+      (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) | \
+      (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT))
+
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_VSYNC_VALID(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) >> RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CHANNEL_SELECT(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) >> RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)
+
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply_reg, sel_dmi_active_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) | (sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply_reg, sel_dmi_active_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) | (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply_reg, sel_dmi_active_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) | (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_VSYNC_VALID(rbbm_dsply_reg, sel_dmi_vsync_valid) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) | (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID0(rbbm_dsply_reg, dmi_ch1_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) | (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID1(rbbm_dsply_reg, dmi_ch1_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) | (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID2(rbbm_dsply_reg, dmi_ch1_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) | (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_SW_CNTL(rbbm_dsply_reg, dmi_ch1_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) | (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_NUM_BUFS(rbbm_dsply_reg, dmi_ch1_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) | (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID0(rbbm_dsply_reg, dmi_ch2_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) | (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID1(rbbm_dsply_reg, dmi_ch2_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) | (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID2(rbbm_dsply_reg, dmi_ch2_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) | (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_SW_CNTL(rbbm_dsply_reg, dmi_ch2_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) | (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_NUM_BUFS(rbbm_dsply_reg, dmi_ch2_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) | (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CHANNEL_SELECT(rbbm_dsply_reg, dmi_channel_select) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) | (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID0(rbbm_dsply_reg, dmi_ch3_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) | (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID1(rbbm_dsply_reg, dmi_ch3_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) | (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID2(rbbm_dsply_reg, dmi_ch3_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) | (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_SW_CNTL(rbbm_dsply_reg, dmi_ch3_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) | (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_NUM_BUFS(rbbm_dsply_reg, dmi_ch3_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) | (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID0(rbbm_dsply_reg, dmi_ch4_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) | (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID1(rbbm_dsply_reg, dmi_ch4_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) | (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID2(rbbm_dsply_reg, dmi_ch4_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) | (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_SW_CNTL(rbbm_dsply_reg, dmi_ch4_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) | (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_NUM_BUFS(rbbm_dsply_reg, dmi_ch4_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) | (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int sel_dmi_active_bufid0          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE;
+          unsigned int sel_dmi_active_bufid1          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE;
+          unsigned int sel_dmi_active_bufid2          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE;
+          unsigned int sel_dmi_vsync_valid            : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE;
+          unsigned int dmi_ch1_use_bufid0             : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE;
+          unsigned int dmi_ch1_use_bufid1             : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE;
+          unsigned int dmi_ch1_use_bufid2             : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE;
+          unsigned int dmi_ch1_sw_cntl                : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE;
+          unsigned int dmi_ch1_num_bufs               : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE;
+          unsigned int dmi_ch2_use_bufid0             : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE;
+          unsigned int dmi_ch2_use_bufid1             : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE;
+          unsigned int dmi_ch2_use_bufid2             : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE;
+          unsigned int dmi_ch2_sw_cntl                : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE;
+          unsigned int dmi_ch2_num_bufs               : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE;
+          unsigned int dmi_channel_select             : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE;
+          unsigned int                                : 2;
+          unsigned int dmi_ch3_use_bufid0             : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE;
+          unsigned int dmi_ch3_use_bufid1             : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE;
+          unsigned int dmi_ch3_use_bufid2             : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE;
+          unsigned int dmi_ch3_sw_cntl                : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE;
+          unsigned int dmi_ch3_num_bufs               : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE;
+          unsigned int dmi_ch4_use_bufid0             : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE;
+          unsigned int dmi_ch4_use_bufid1             : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE;
+          unsigned int dmi_ch4_use_bufid2             : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE;
+          unsigned int dmi_ch4_sw_cntl                : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE;
+          unsigned int dmi_ch4_num_bufs               : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE;
+     } rbbm_dsply_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int dmi_ch4_num_bufs               : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE;
+          unsigned int dmi_ch4_sw_cntl                : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE;
+          unsigned int dmi_ch4_use_bufid2             : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE;
+          unsigned int dmi_ch4_use_bufid1             : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE;
+          unsigned int dmi_ch4_use_bufid0             : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE;
+          unsigned int dmi_ch3_num_bufs               : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE;
+          unsigned int dmi_ch3_sw_cntl                : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE;
+          unsigned int dmi_ch3_use_bufid2             : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE;
+          unsigned int dmi_ch3_use_bufid1             : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE;
+          unsigned int dmi_ch3_use_bufid0             : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE;
+          unsigned int                                : 2;
+          unsigned int dmi_channel_select             : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE;
+          unsigned int dmi_ch2_num_bufs               : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE;
+          unsigned int dmi_ch2_sw_cntl                : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE;
+          unsigned int dmi_ch2_use_bufid2             : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE;
+          unsigned int dmi_ch2_use_bufid1             : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE;
+          unsigned int dmi_ch2_use_bufid0             : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE;
+          unsigned int dmi_ch1_num_bufs               : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE;
+          unsigned int dmi_ch1_sw_cntl                : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE;
+          unsigned int dmi_ch1_use_bufid2             : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE;
+          unsigned int dmi_ch1_use_bufid1             : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE;
+          unsigned int dmi_ch1_use_bufid0             : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE;
+          unsigned int sel_dmi_vsync_valid            : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE;
+          unsigned int sel_dmi_active_bufid2          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE;
+          unsigned int sel_dmi_active_bufid1          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE;
+          unsigned int sel_dmi_active_bufid0          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE;
+     } rbbm_dsply_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_dsply_t f;
+} rbbm_dsply_u;
+
+
+/*
+ * RBBM_RENDER_LATEST struct
+ */
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE 2
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT 0
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT 8
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT 16
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT 24
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK 0x00000003
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK 0x00000300
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK 0x00030000
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK 0x03000000
+
+#define RBBM_RENDER_LATEST_MASK \
+     (RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK)
+
+#define RBBM_RENDER_LATEST(dmi_ch1_buffer_id, dmi_ch2_buffer_id, dmi_ch3_buffer_id, dmi_ch4_buffer_id) \
+     ((dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) | \
+      (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) | \
+      (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) | \
+      (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT))
+
+#define RBBM_RENDER_LATEST_GET_DMI_CH1_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH2_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH3_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH4_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)
+
+#define RBBM_RENDER_LATEST_SET_DMI_CH1_BUFFER_ID(rbbm_render_latest_reg, dmi_ch1_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) | (dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH2_BUFFER_ID(rbbm_render_latest_reg, dmi_ch2_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) | (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH3_BUFFER_ID(rbbm_render_latest_reg, dmi_ch3_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) | (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH4_BUFFER_ID(rbbm_render_latest_reg, dmi_ch4_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) | (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int dmi_ch1_buffer_id              : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch2_buffer_id              : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch3_buffer_id              : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch4_buffer_id              : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+     } rbbm_render_latest_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int                                : 6;
+          unsigned int dmi_ch4_buffer_id              : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch3_buffer_id              : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch2_buffer_id              : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch1_buffer_id              : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE;
+     } rbbm_render_latest_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_render_latest_t f;
+} rbbm_render_latest_u;
+
+
+/*
+ * RBBM_RTL_RELEASE struct
+ */
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0
+
+#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff
+
+#define RBBM_RTL_RELEASE_MASK \
+     (RBBM_RTL_RELEASE_CHANGELIST_MASK)
+
+#define RBBM_RTL_RELEASE(changelist) \
+     ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT))
+
+#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \
+     ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \
+     rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_rtl_release_t f;
+} rbbm_rtl_release_u;
+
+
+/*
+ * RBBM_PATCH_RELEASE struct
+ */
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000
+
+#define RBBM_PATCH_RELEASE_MASK \
+     (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \
+      RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \
+      RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK)
+
+#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \
+     ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \
+      (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \
+      (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT))
+
+#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+     } rbbm_patch_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+     } rbbm_patch_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_patch_release_t f;
+} rbbm_patch_release_u;
+
+
+/*
+ * RBBM_AUXILIARY_CONFIG struct
+ */
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff
+
+#define RBBM_AUXILIARY_CONFIG_MASK \
+     (RBBM_AUXILIARY_CONFIG_RESERVED_MASK)
+
+#define RBBM_AUXILIARY_CONFIG(reserved) \
+     ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT))
+
+#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \
+     ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \
+     rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_auxiliary_config_t f;
+} rbbm_auxiliary_config_u;
+
+
+/*
+ * RBBM_PERIPHID0 struct
+ */
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0
+
+#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff
+
+#define RBBM_PERIPHID0_MASK \
+     (RBBM_PERIPHID0_PARTNUMBER0_MASK)
+
+#define RBBM_PERIPHID0(partnumber0) \
+     ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT))
+
+#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \
+     ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \
+     rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int                                : 24;
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+     } rbbm_periphid0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid0_t f;
+} rbbm_periphid0_u;
+
+
+/*
+ * RBBM_PERIPHID1 struct
+ */
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4
+#define RBBM_PERIPHID1_DESIGNER0_SIZE  4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0
+#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f
+#define RBBM_PERIPHID1_DESIGNER0_MASK  0x000000f0
+
+#define RBBM_PERIPHID1_MASK \
+     (RBBM_PERIPHID1_PARTNUMBER1_MASK | \
+      RBBM_PERIPHID1_DESIGNER0_MASK)
+
+#define RBBM_PERIPHID1(partnumber1, designer0) \
+     ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \
+      (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT))
+
+#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int                                : 24;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+     } rbbm_periphid1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid1_t f;
+} rbbm_periphid1_u;
+
+
+/*
+ * RBBM_PERIPHID2 struct
+ */
+
+#define RBBM_PERIPHID2_DESIGNER1_SIZE  4
+#define RBBM_PERIPHID2_REVISION_SIZE   4
+
+#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0
+#define RBBM_PERIPHID2_REVISION_SHIFT  4
+
+#define RBBM_PERIPHID2_DESIGNER1_MASK  0x0000000f
+#define RBBM_PERIPHID2_REVISION_MASK   0x000000f0
+
+#define RBBM_PERIPHID2_MASK \
+     (RBBM_PERIPHID2_DESIGNER1_MASK | \
+      RBBM_PERIPHID2_REVISION_MASK)
+
+#define RBBM_PERIPHID2(designer1, revision) \
+     ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \
+      (revision << RBBM_PERIPHID2_REVISION_SHIFT))
+
+#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT)
+
+#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int                                : 24;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+     } rbbm_periphid2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid2_t f;
+} rbbm_periphid2_u;
+
+
+/*
+ * RBBM_PERIPHID3 struct
+ */
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_CONTINUATION_SIZE 1
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4
+#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c
+#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030
+#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080
+
+#define RBBM_PERIPHID3_MASK \
+     (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \
+      RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \
+      RBBM_PERIPHID3_MH_INTERFACE_MASK | \
+      RBBM_PERIPHID3_CONTINUATION_MASK)
+
+#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \
+     ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \
+      (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \
+      (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \
+      (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT))
+
+#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int                                : 1;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int                                : 24;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+     } rbbm_periphid3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid3_t f;
+} rbbm_periphid3_u;
+
+
+/*
+ * RBBM_CNTL struct
+ */
+
+#define RBBM_CNTL_READ_TIMEOUT_SIZE    8
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9
+
+#define RBBM_CNTL_READ_TIMEOUT_SHIFT   0
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8
+
+#define RBBM_CNTL_READ_TIMEOUT_MASK    0x000000ff
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00
+
+#define RBBM_CNTL_MASK \
+     (RBBM_CNTL_READ_TIMEOUT_MASK | \
+      RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK)
+
+#define RBBM_CNTL(read_timeout, regclk_deassert_time) \
+     ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \
+      (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT))
+
+#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int                                : 15;
+     } rbbm_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int                                : 15;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+     } rbbm_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_cntl_t f;
+} rbbm_cntl_u;
+
+
+/*
+ * RBBM_SKEW_CNTL struct
+ */
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f
+#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0
+
+#define RBBM_SKEW_CNTL_MASK \
+     (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \
+      RBBM_SKEW_CNTL_SKEW_COUNT_MASK)
+
+#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \
+     ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \
+      (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT))
+
+#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int                                : 22;
+     } rbbm_skew_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int                                : 22;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+     } rbbm_skew_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_skew_cntl_t f;
+} rbbm_skew_cntl_u;
+
+
+/*
+ * RBBM_SOFT_RESET struct
+ */
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000
+
+#define RBBM_SOFT_RESET_MASK \
+     (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK)
+
+#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \
+     ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \
+      (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \
+      (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \
+      (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \
+      (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \
+      (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \
+      (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \
+      (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \
+      (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT))
+
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int                                : 15;
+     } rbbm_soft_reset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int                                : 15;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+     } rbbm_soft_reset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_soft_reset_t f;
+} rbbm_soft_reset_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE1 struct
+ */
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000
+
+#define RBBM_PM_OVERRIDE1_MASK \
+     (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \
+     ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override1_t f;
+} rbbm_pm_override1_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE2 struct
+ */
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800
+
+#define RBBM_PM_OVERRIDE2_MASK \
+     (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \
+     ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \
+      (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \
+      (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int                                : 20;
+     } rbbm_pm_override2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int                                : 20;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override2_t f;
+} rbbm_pm_override2_u;
+
+
+/*
+ * GC_SYS_IDLE struct
+ */
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE 6
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT 16
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT 24
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT 25
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT 29
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT 30
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK 0x01000000
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK 0x02000000
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000
+
+#define GC_SYS_IDLE_MASK \
+     (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK | \
+      GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK | \
+      GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK | \
+      GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK)
+
+#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_wait_dmi_mask, gc_sys_urgent_ramp, gc_sys_wait_dmi, gc_sys_urgent_ramp_override, gc_sys_wait_dmi_override, gc_sys_idle_override) \
+     ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \
+      (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) | \
+      (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) | \
+      (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) | \
+      (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) | \
+      (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) | \
+      (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT))
+
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle_reg, gc_sys_wait_dmi_mask) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) | (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP(gc_sys_idle_reg, gc_sys_urgent_ramp) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) | (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI(gc_sys_idle_reg, gc_sys_wait_dmi) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) | (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle_reg, gc_sys_urgent_ramp_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) | (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle_reg, gc_sys_wait_dmi_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) | (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+          unsigned int gc_sys_wait_dmi_mask           : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE;
+          unsigned int                                : 2;
+          unsigned int gc_sys_urgent_ramp             : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE;
+          unsigned int gc_sys_wait_dmi                : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE;
+          unsigned int                                : 3;
+          unsigned int gc_sys_urgent_ramp_override    : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE;
+          unsigned int gc_sys_wait_dmi_override       : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE;
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+     } gc_sys_idle_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+          unsigned int gc_sys_wait_dmi_override       : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE;
+          unsigned int gc_sys_urgent_ramp_override    : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE;
+          unsigned int                                : 3;
+          unsigned int gc_sys_wait_dmi                : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE;
+          unsigned int gc_sys_urgent_ramp             : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE;
+          unsigned int                                : 2;
+          unsigned int gc_sys_wait_dmi_mask           : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE;
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+     } gc_sys_idle_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gc_sys_idle_t f;
+} gc_sys_idle_u;
+
+
+/*
+ * NQWAIT_UNTIL struct
+ */
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001
+
+#define NQWAIT_UNTIL_MASK \
+     (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK)
+
+#define NQWAIT_UNTIL(wait_gui_idle) \
+     ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT))
+
+#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \
+     ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \
+     nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+          unsigned int                                : 31;
+     } nqwait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int                                : 31;
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+     } nqwait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     nqwait_until_t f;
+} nqwait_until_u;
+
+
+/*
+ * RBBM_DEBUG_OUT struct
+ */
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE 32
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT 0
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK 0xffffffff
+
+#define RBBM_DEBUG_OUT_MASK \
+     (RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK)
+
+#define RBBM_DEBUG_OUT(debug_bus_out) \
+     ((debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT))
+
+#define RBBM_DEBUG_OUT_GET_DEBUG_BUS_OUT(rbbm_debug_out) \
+     ((rbbm_debug_out & RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) >> RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)
+
+#define RBBM_DEBUG_OUT_SET_DEBUG_BUS_OUT(rbbm_debug_out_reg, debug_bus_out) \
+     rbbm_debug_out_reg = (rbbm_debug_out_reg & ~RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) | (debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_out_t {
+          unsigned int debug_bus_out                  : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE;
+     } rbbm_debug_out_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_out_t {
+          unsigned int debug_bus_out                  : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE;
+     } rbbm_debug_out_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_out_t f;
+} rbbm_debug_out_u;
+
+
+/*
+ * RBBM_DEBUG_CNTL struct
+ */
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE 6
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE 4
+#define RBBM_DEBUG_CNTL_SW_ENABLE_SIZE 1
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE 6
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE 4
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE 4
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT 0
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT 8
+#define RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT 12
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT 16
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT 24
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT 28
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK 0x0000003f
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK 0x00000f00
+#define RBBM_DEBUG_CNTL_SW_ENABLE_MASK 0x00001000
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK 0x0f000000
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK 0xf0000000
+
+#define RBBM_DEBUG_CNTL_MASK \
+     (RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK | \
+      RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK | \
+      RBBM_DEBUG_CNTL_SW_ENABLE_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK)
+
+#define RBBM_DEBUG_CNTL(sub_block_addr, sub_block_sel, sw_enable, gpio_sub_block_addr, gpio_sub_block_sel, gpio_byte_lane_enb) \
+     ((sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) | \
+      (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) | \
+      (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) | \
+      (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) | \
+      (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) | \
+      (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT))
+
+#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_ADDR(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_SEL(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_SW_ENABLE(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SW_ENABLE_MASK) >> RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) >> RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)
+
+#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, sub_block_addr) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) | (sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, sub_block_sel) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) | (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_SW_ENABLE(rbbm_debug_cntl_reg, sw_enable) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SW_ENABLE_MASK) | (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, gpio_sub_block_addr) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) | (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, gpio_sub_block_sel) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) | (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl_reg, gpio_byte_lane_enb) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) | (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_cntl_t {
+          unsigned int sub_block_addr                 : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 2;
+          unsigned int sub_block_sel                  : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE;
+          unsigned int sw_enable                      : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int gpio_sub_block_addr            : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 2;
+          unsigned int gpio_sub_block_sel             : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE;
+          unsigned int gpio_byte_lane_enb             : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE;
+     } rbbm_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_cntl_t {
+          unsigned int gpio_byte_lane_enb             : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE;
+          unsigned int gpio_sub_block_sel             : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE;
+          unsigned int                                : 2;
+          unsigned int gpio_sub_block_addr            : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_enable                      : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE;
+          unsigned int sub_block_sel                  : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE;
+          unsigned int                                : 2;
+          unsigned int sub_block_addr                 : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE;
+     } rbbm_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_cntl_t f;
+} rbbm_debug_cntl_u;
+
+
+/*
+ * RBBM_DEBUG struct
+ */
+
+#define RBBM_DEBUG_IGNORE_RTR_SIZE     1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1
+
+#define RBBM_DEBUG_IGNORE_RTR_SHIFT    1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31
+
+#define RBBM_DEBUG_IGNORE_RTR_MASK     0x00000002
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000
+
+#define RBBM_DEBUG_MASK \
+     (RBBM_DEBUG_IGNORE_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \
+      RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \
+      RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK)
+
+#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \
+     ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \
+      (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \
+      (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \
+      (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \
+      (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \
+      (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \
+      (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \
+      (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \
+      (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \
+      (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \
+      (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \
+      (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT))
+
+#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int                                : 1;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int                                : 3;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 4;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+     } rbbm_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+          unsigned int                                : 6;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int                                : 4;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 3;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int                                : 1;
+     } rbbm_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_t f;
+} rbbm_debug_u;
+
+
+/*
+ * RBBM_READ_ERROR struct
+ */
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15
+#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1
+#define RBBM_READ_ERROR_READ_ERROR_SIZE 1
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2
+#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30
+#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31
+
+#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc
+#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000
+#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000
+
+#define RBBM_READ_ERROR_MASK \
+     (RBBM_READ_ERROR_READ_ADDRESS_MASK | \
+      RBBM_READ_ERROR_READ_REQUESTER_MASK | \
+      RBBM_READ_ERROR_READ_ERROR_MASK)
+
+#define RBBM_READ_ERROR(read_address, read_requester, read_error) \
+     ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \
+      (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \
+      (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT))
+
+#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int                                : 2;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+     } rbbm_read_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 2;
+     } rbbm_read_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_read_error_t f;
+} rbbm_read_error_u;
+
+
+/*
+ * RBBM_WAIT_IDLE_CLOCKS struct
+ */
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff
+
+#define RBBM_WAIT_IDLE_CLOCKS_MASK \
+     (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK)
+
+#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \
+     ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT))
+
+#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \
+     ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \
+     rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+          unsigned int                                : 24;
+     } rbbm_wait_idle_clocks_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int                                : 24;
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+     } rbbm_wait_idle_clocks_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_wait_idle_clocks_t f;
+} rbbm_wait_idle_clocks_u;
+
+
+/*
+ * RBBM_INT_CNTL struct
+ */
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000
+
+#define RBBM_INT_CNTL_MASK \
+     (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \
+      RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \
+      RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK)
+
+#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \
+     ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \
+      (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \
+      (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT))
+
+#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+     } rbbm_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_cntl_t f;
+} rbbm_int_cntl_u;
+
+
+/*
+ * RBBM_INT_STATUS struct
+ */
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000
+
+#define RBBM_INT_STATUS_MASK \
+     (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \
+      RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \
+      RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK)
+
+#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \
+     ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \
+      (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \
+      (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT))
+
+#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+     } rbbm_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_status_t f;
+} rbbm_int_status_u;
+
+
+/*
+ * RBBM_INT_ACK struct
+ */
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000
+
+#define RBBM_INT_ACK_MASK \
+     (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \
+      RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \
+      RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK)
+
+#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \
+     ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \
+      (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \
+      (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT))
+
+#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+     } rbbm_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_ack_t f;
+} rbbm_int_ack_u;
+
+
+/*
+ * MASTER_INT_SIGNAL struct
+ */
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT 26
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_MASK 0x04000000
+#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000
+
+#define MASTER_INT_SIGNAL_MASK \
+     (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_SQ_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK)
+
+#define MASTER_INT_SIGNAL(mh_int_stat, sq_int_stat, cp_int_stat, rbbm_int_stat) \
+     ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \
+      (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) | \
+      (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \
+      (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT))
+
+#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_SQ_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) >> MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_SQ_INT_STAT(master_int_signal_reg, sq_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) | (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int                                : 5;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 20;
+          unsigned int sq_int_stat                    : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+     } master_int_signal_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sq_int_stat                    : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE;
+          unsigned int                                : 20;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 5;
+     } master_int_signal_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     master_int_signal_t f;
+} master_int_signal_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_SELECT struct
+ */
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f
+
+#define RBBM_PERFCOUNTER1_SELECT_MASK \
+     (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK)
+
+#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \
+     ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT))
+
+#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \
+     ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \
+     rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+          unsigned int                                : 26;
+     } rbbm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int                                : 26;
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+     } rbbm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_select_t f;
+} rbbm_perfcounter1_select_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_LO struct
+ */
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff
+
+#define RBBM_PERFCOUNTER1_LO_MASK \
+     (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK)
+
+#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \
+     ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT))
+
+#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \
+     ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \
+     rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_lo_t f;
+} rbbm_perfcounter1_lo_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_HI struct
+ */
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff
+
+#define RBBM_PERFCOUNTER1_HI_MASK \
+     (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK)
+
+#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \
+     ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT))
+
+#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \
+     ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \
+     rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+          unsigned int                                : 16;
+     } rbbm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+     } rbbm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_hi_t f;
+} rbbm_perfcounter1_hi_u;
+
+
+#endif
+
+
+#if !defined (_MH_FIDDLE_H)
+#define _MH_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  mh_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * MH_ARBITER_CONFIG struct
+ */
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE 1
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT 26
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200
+#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK 0x04000000
+
+#define MH_ARBITER_CONFIG_MASK \
+     (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \
+      MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \
+      MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK)
+
+#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable, pa_clnt_enable) \
+     ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \
+      (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \
+      (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \
+      (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \
+      (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \
+      (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \
+      (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \
+      (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \
+      (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \
+      (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \
+      (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \
+      (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \
+      (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) | \
+      (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT))
+
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PA_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)
+
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PA_CLNT_ENABLE(mh_arbiter_config_reg, pa_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) | (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int pa_clnt_enable                 : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE;
+          unsigned int                                : 5;
+     } mh_arbiter_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int                                : 5;
+          unsigned int pa_clnt_enable                 : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+     } mh_arbiter_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_arbiter_config_t f;
+} mh_arbiter_config_u;
+
+
+/*
+ * MH_CLNT_AXI_ID_REUSE struct
+ */
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE 3
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT 11
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT 12
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK 0x00000800
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK 0x00007000
+
+#define MH_CLNT_AXI_ID_REUSE_MASK \
+     (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \
+      MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK | \
+      MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK)
+
+#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id, reserved3, paw_id) \
+     ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \
+      (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \
+      (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \
+      (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \
+      (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) | \
+      (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) | \
+      (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT))
+
+#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED3(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_PAw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)
+
+#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED3(mh_clnt_axi_id_reuse_reg, reserved3) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) | (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_PAw_ID(mh_clnt_axi_id_reuse_reg, paw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) | (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved3                      : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE;
+          unsigned int paw_id                         : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE;
+          unsigned int                                : 17;
+     } mh_clnt_axi_id_reuse_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int                                : 17;
+          unsigned int paw_id                         : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE;
+          unsigned int reserved3                      : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+     } mh_clnt_axi_id_reuse_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_clnt_axi_id_reuse_t f;
+} mh_clnt_axi_id_reuse_u;
+
+
+/*
+ * MH_INTERRUPT_MASK struct
+ */
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_MASK_MASK \
+     (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_mask_t f;
+} mh_interrupt_mask_u;
+
+
+/*
+ * MH_INTERRUPT_STATUS struct
+ */
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_STATUS_MASK \
+     (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_status_t f;
+} mh_interrupt_status_u;
+
+
+/*
+ * MH_INTERRUPT_CLEAR struct
+ */
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_CLEAR_MASK \
+     (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_clear_t f;
+} mh_interrupt_clear_u;
+
+
+/*
+ * MH_AXI_ERROR struct
+ */
+
+#define MH_AXI_ERROR_AXI_READ_ID_SIZE  3
+#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1
+#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1
+
+#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0
+#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3
+#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7
+
+#define MH_AXI_ERROR_AXI_READ_ID_MASK  0x00000007
+#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008
+#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080
+
+#define MH_AXI_ERROR_MASK \
+     (MH_AXI_ERROR_AXI_READ_ID_MASK | \
+      MH_AXI_ERROR_AXI_READ_ERROR_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ID_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ERROR_MASK)
+
+#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \
+     ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \
+      (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \
+      (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT))
+
+#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int                                : 24;
+     } mh_axi_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int                                : 24;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+     } mh_axi_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_error_t f;
+} mh_axi_error_u;
+
+
+/*
+ * MH_PERFCOUNTER0_SELECT struct
+ */
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_SELECT_MASK \
+     (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \
+     ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \
+     mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_select_t f;
+} mh_perfcounter0_select_u;
+
+
+/*
+ * MH_PERFCOUNTER1_SELECT struct
+ */
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_SELECT_MASK \
+     (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \
+     ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \
+     mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_select_t f;
+} mh_perfcounter1_select_u;
+
+
+/*
+ * MH_PERFCOUNTER0_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_CONFIG_MASK \
+     (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER0_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \
+     ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \
+     mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter0_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_config_t f;
+} mh_perfcounter0_config_u;
+
+
+/*
+ * MH_PERFCOUNTER1_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_CONFIG_MASK \
+     (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER1_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \
+     ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \
+     mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter1_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_config_t f;
+} mh_perfcounter1_config_u;
+
+
+/*
+ * MH_PERFCOUNTER0_LOW struct
+ */
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER0_LOW_MASK \
+     (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER0_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \
+     ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \
+     mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_low_t f;
+} mh_perfcounter0_low_u;
+
+
+/*
+ * MH_PERFCOUNTER1_LOW struct
+ */
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER1_LOW_MASK \
+     (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER1_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \
+     ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \
+     mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_low_t f;
+} mh_perfcounter1_low_u;
+
+
+/*
+ * MH_PERFCOUNTER0_HI struct
+ */
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER0_HI_MASK \
+     (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER0_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \
+     ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \
+     mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_hi_t f;
+} mh_perfcounter0_hi_u;
+
+
+/*
+ * MH_PERFCOUNTER1_HI struct
+ */
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER1_HI_MASK \
+     (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER1_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \
+     ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \
+     mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_hi_t f;
+} mh_perfcounter1_hi_u;
+
+
+/*
+ * MH_DEBUG_CTRL struct
+ */
+
+#define MH_DEBUG_CTRL_INDEX_SIZE       6
+
+#define MH_DEBUG_CTRL_INDEX_SHIFT      0
+
+#define MH_DEBUG_CTRL_INDEX_MASK       0x0000003f
+
+#define MH_DEBUG_CTRL_MASK \
+     (MH_DEBUG_CTRL_INDEX_MASK)
+
+#define MH_DEBUG_CTRL(index) \
+     ((index << MH_DEBUG_CTRL_INDEX_SHIFT))
+
+#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \
+     ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \
+     mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+          unsigned int                                : 26;
+     } mh_debug_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int                                : 26;
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+     } mh_debug_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_ctrl_t f;
+} mh_debug_ctrl_u;
+
+
+/*
+ * MH_DEBUG_DATA struct
+ */
+
+#define MH_DEBUG_DATA_DATA_SIZE        32
+
+#define MH_DEBUG_DATA_DATA_SHIFT       0
+
+#define MH_DEBUG_DATA_DATA_MASK        0xffffffff
+
+#define MH_DEBUG_DATA_MASK \
+     (MH_DEBUG_DATA_DATA_MASK)
+
+#define MH_DEBUG_DATA(data) \
+     ((data << MH_DEBUG_DATA_DATA_SHIFT))
+
+#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \
+     ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT)
+
+#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \
+     mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_data_t f;
+} mh_debug_data_u;
+
+
+/*
+ * MH_AXI_HALT_CONTROL struct
+ */
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_SIZE 1
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT 0
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_MASK 0x00000001
+
+#define MH_AXI_HALT_CONTROL_MASK \
+     (MH_AXI_HALT_CONTROL_AXI_HALT_MASK)
+
+#define MH_AXI_HALT_CONTROL(axi_halt) \
+     ((axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT))
+
+#define MH_AXI_HALT_CONTROL_GET_AXI_HALT(mh_axi_halt_control) \
+     ((mh_axi_halt_control & MH_AXI_HALT_CONTROL_AXI_HALT_MASK) >> MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)
+
+#define MH_AXI_HALT_CONTROL_SET_AXI_HALT(mh_axi_halt_control_reg, axi_halt) \
+     mh_axi_halt_control_reg = (mh_axi_halt_control_reg & ~MH_AXI_HALT_CONTROL_AXI_HALT_MASK) | (axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_halt_control_t {
+          unsigned int axi_halt                       : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE;
+          unsigned int                                : 31;
+     } mh_axi_halt_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_halt_control_t {
+          unsigned int                                : 31;
+          unsigned int axi_halt                       : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE;
+     } mh_axi_halt_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_halt_control_t f;
+} mh_axi_halt_control_u;
+
+
+/*
+ * MH_DEBUG_REG00 struct
+ */
+
+#define MH_DEBUG_REG00_MH_BUSY_SIZE    1
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1
+#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1
+#define MH_DEBUG_REG00_TCD_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_TCD_FULL_SIZE   1
+#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_PA_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1
+#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_ARQ_FULL_SIZE   1
+#define MH_DEBUG_REG00_WDB_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_WDB_FULL_SIZE   1
+#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1
+#define MH_DEBUG_REG00_AXI_RDY_ENA_SIZE 1
+
+#define MH_DEBUG_REG00_MH_BUSY_SHIFT   0
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1
+#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2
+#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3
+#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5
+#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6
+#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7
+#define MH_DEBUG_REG00_TCD_FULL_SHIFT  8
+#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9
+#define MH_DEBUG_REG00_PA_REQUEST_SHIFT 10
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 11
+#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 12
+#define MH_DEBUG_REG00_ARQ_FULL_SHIFT  13
+#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 14
+#define MH_DEBUG_REG00_WDB_FULL_SHIFT  15
+#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 16
+#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 17
+#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 18
+#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 19
+#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 20
+#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 21
+#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 22
+#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 23
+#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 24
+#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 25
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 26
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 27
+#define MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT 28
+
+#define MH_DEBUG_REG00_MH_BUSY_MASK    0x00000001
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002
+#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004
+#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008
+#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020
+#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040
+#define MH_DEBUG_REG00_TCD_EMPTY_MASK  0x00000080
+#define MH_DEBUG_REG00_TCD_FULL_MASK   0x00000100
+#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200
+#define MH_DEBUG_REG00_PA_REQUEST_MASK 0x00000400
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000800
+#define MH_DEBUG_REG00_ARQ_EMPTY_MASK  0x00001000
+#define MH_DEBUG_REG00_ARQ_FULL_MASK   0x00002000
+#define MH_DEBUG_REG00_WDB_EMPTY_MASK  0x00004000
+#define MH_DEBUG_REG00_WDB_FULL_MASK   0x00008000
+#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00010000
+#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00020000
+#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00040000
+#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00080000
+#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00100000
+#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00200000
+#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00400000
+#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00800000
+#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x01000000
+#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x02000000
+#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x04000000
+#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x08000000
+#define MH_DEBUG_REG00_AXI_RDY_ENA_MASK 0x10000000
+
+#define MH_DEBUG_REG00_MASK \
+     (MH_DEBUG_REG00_MH_BUSY_MASK | \
+      MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \
+      MH_DEBUG_REG00_CP_REQUEST_MASK | \
+      MH_DEBUG_REG00_VGT_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \
+      MH_DEBUG_REG00_TC_CAM_FULL_MASK | \
+      MH_DEBUG_REG00_TCD_EMPTY_MASK | \
+      MH_DEBUG_REG00_TCD_FULL_MASK | \
+      MH_DEBUG_REG00_RB_REQUEST_MASK | \
+      MH_DEBUG_REG00_PA_REQUEST_MASK | \
+      MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \
+      MH_DEBUG_REG00_ARQ_EMPTY_MASK | \
+      MH_DEBUG_REG00_ARQ_FULL_MASK | \
+      MH_DEBUG_REG00_WDB_EMPTY_MASK | \
+      MH_DEBUG_REG00_WDB_FULL_MASK | \
+      MH_DEBUG_REG00_AXI_AVALID_MASK | \
+      MH_DEBUG_REG00_AXI_AREADY_MASK | \
+      MH_DEBUG_REG00_AXI_ARVALID_MASK | \
+      MH_DEBUG_REG00_AXI_ARREADY_MASK | \
+      MH_DEBUG_REG00_AXI_WVALID_MASK | \
+      MH_DEBUG_REG00_AXI_WREADY_MASK | \
+      MH_DEBUG_REG00_AXI_RVALID_MASK | \
+      MH_DEBUG_REG00_AXI_RREADY_MASK | \
+      MH_DEBUG_REG00_AXI_BVALID_MASK | \
+      MH_DEBUG_REG00_AXI_BREADY_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_ACK_MASK | \
+      MH_DEBUG_REG00_AXI_RDY_ENA_MASK)
+
+#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, pa_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack, axi_rdy_ena) \
+     ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \
+      (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \
+      (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \
+      (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \
+      (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \
+      (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \
+      (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \
+      (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \
+      (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \
+      (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \
+      (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) | \
+      (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \
+      (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \
+      (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \
+      (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \
+      (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \
+      (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \
+      (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \
+      (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \
+      (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \
+      (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \
+      (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \
+      (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \
+      (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \
+      (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \
+      (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \
+      (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \
+      (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) | \
+      (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT))
+
+#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_PA_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_PA_REQUEST_MASK) >> MH_DEBUG_REG00_PA_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RDY_ENA(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)
+
+#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_PA_REQUEST(mh_debug_reg00_reg, pa_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_PA_REQUEST_MASK) | (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RDY_ENA(mh_debug_reg00_reg, axi_rdy_ena) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int pa_request                     : MH_DEBUG_REG00_PA_REQUEST_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int                                : 3;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int pa_request                     : MH_DEBUG_REG00_PA_REQUEST_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+     } mh_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg00_t f;
+} mh_debug_reg00_u;
+
+
+/*
+ * MH_DEBUG_REG01 struct
+ */
+
+#define MH_DEBUG_REG01_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1
+#define MH_DEBUG_REG01_CP_TAG_q_SIZE   3
+#define MH_DEBUG_REG01_CP_BLEN_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_TAG_q_SIZE  1
+#define MH_DEBUG_REG01_TC_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_TC_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_TC_BLEN_q_SIZE  1
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG01_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG01_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_PA_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_PA_RTR_q_SIZE   1
+
+#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0
+#define MH_DEBUG_REG01_CP_RTR_q_SHIFT  1
+#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2
+#define MH_DEBUG_REG01_CP_TAG_q_SHIFT  3
+#define MH_DEBUG_REG01_CP_BLEN_q_SHIFT 6
+#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 7
+#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 8
+#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 9
+#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 10
+#define MH_DEBUG_REG01_TC_RTR_q_SHIFT  11
+#define MH_DEBUG_REG01_TC_BLEN_q_SHIFT 12
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 13
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 14
+#define MH_DEBUG_REG01_TC_MH_written_SHIFT 15
+#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 16
+#define MH_DEBUG_REG01_RB_RTR_q_SHIFT  17
+#define MH_DEBUG_REG01_PA_SEND_q_SHIFT 18
+#define MH_DEBUG_REG01_PA_RTR_q_SHIFT  19
+
+#define MH_DEBUG_REG01_CP_SEND_q_MASK  0x00000001
+#define MH_DEBUG_REG01_CP_RTR_q_MASK   0x00000002
+#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004
+#define MH_DEBUG_REG01_CP_TAG_q_MASK   0x00000038
+#define MH_DEBUG_REG01_CP_BLEN_q_MASK  0x00000040
+#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00000080
+#define MH_DEBUG_REG01_VGT_RTR_q_MASK  0x00000100
+#define MH_DEBUG_REG01_VGT_TAG_q_MASK  0x00000200
+#define MH_DEBUG_REG01_TC_SEND_q_MASK  0x00000400
+#define MH_DEBUG_REG01_TC_RTR_q_MASK   0x00000800
+#define MH_DEBUG_REG01_TC_BLEN_q_MASK  0x00001000
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00002000
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00004000
+#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00008000
+#define MH_DEBUG_REG01_RB_SEND_q_MASK  0x00010000
+#define MH_DEBUG_REG01_RB_RTR_q_MASK   0x00020000
+#define MH_DEBUG_REG01_PA_SEND_q_MASK  0x00040000
+#define MH_DEBUG_REG01_PA_RTR_q_MASK   0x00080000
+
+#define MH_DEBUG_REG01_MASK \
+     (MH_DEBUG_REG01_CP_SEND_q_MASK | \
+      MH_DEBUG_REG01_CP_RTR_q_MASK | \
+      MH_DEBUG_REG01_CP_WRITE_q_MASK | \
+      MH_DEBUG_REG01_CP_TAG_q_MASK | \
+      MH_DEBUG_REG01_CP_BLEN_q_MASK | \
+      MH_DEBUG_REG01_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG01_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG01_VGT_TAG_q_MASK | \
+      MH_DEBUG_REG01_TC_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_BLEN_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_MH_written_MASK | \
+      MH_DEBUG_REG01_RB_SEND_q_MASK | \
+      MH_DEBUG_REG01_RB_RTR_q_MASK | \
+      MH_DEBUG_REG01_PA_SEND_q_MASK | \
+      MH_DEBUG_REG01_PA_RTR_q_MASK)
+
+#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_blen_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_blen_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q) \
+     ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \
+      (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \
+      (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \
+      (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \
+      (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \
+      (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \
+      (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \
+      (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \
+      (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) | \
+      (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT))
+
+#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_BLEN_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BLEN_q_MASK) >> MH_DEBUG_REG01_CP_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_BLEN_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_BLEN_q_MASK) >> MH_DEBUG_REG01_TC_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_PA_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_PA_SEND_q_MASK) >> MH_DEBUG_REG01_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_PA_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_PA_RTR_q_MASK) >> MH_DEBUG_REG01_PA_RTR_q_SHIFT)
+
+#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_BLEN_q(mh_debug_reg01_reg, cp_blen_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BLEN_q_MASK) | (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_BLEN_q(mh_debug_reg01_reg, tc_blen_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_BLEN_q_MASK) | (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_PA_SEND_q(mh_debug_reg01_reg, pa_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_PA_RTR_q(mh_debug_reg01_reg, pa_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_blen_q                      : MH_DEBUG_REG01_CP_BLEN_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_blen_q                      : MH_DEBUG_REG01_TC_BLEN_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG01_PA_SEND_q_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG01_PA_RTR_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int                                : 12;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG01_PA_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG01_PA_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_blen_q                      : MH_DEBUG_REG01_TC_BLEN_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int cp_blen_q                      : MH_DEBUG_REG01_CP_BLEN_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+     } mh_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg01_t f;
+} mh_debug_reg01_u;
+
+
+/*
+ * MH_DEBUG_REG02 struct
+ */
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3
+#define MH_DEBUG_REG02_RDC_RID_SIZE    3
+#define MH_DEBUG_REG02_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_PA_writeclean_SIZE 1
+#define MH_DEBUG_REG02_BRC_BID_SIZE    3
+#define MH_DEBUG_REG02_BRC_BRESP_SIZE  2
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3
+#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4
+#define MH_DEBUG_REG02_RDC_RID_SHIFT   7
+#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12
+#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13
+#define MH_DEBUG_REG02_MH_PA_writeclean_SHIFT 14
+#define MH_DEBUG_REG02_BRC_BID_SHIFT   15
+#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 18
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008
+#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070
+#define MH_DEBUG_REG02_RDC_RID_MASK    0x00000380
+#define MH_DEBUG_REG02_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000
+#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000
+#define MH_DEBUG_REG02_MH_PA_writeclean_MASK 0x00004000
+#define MH_DEBUG_REG02_BRC_BID_MASK    0x00038000
+#define MH_DEBUG_REG02_BRC_BRESP_MASK  0x000c0000
+
+#define MH_DEBUG_REG02_MASK \
+     (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_tag_MASK | \
+      MH_DEBUG_REG02_RDC_RID_MASK | \
+      MH_DEBUG_REG02_RDC_RRESP_MASK | \
+      MH_DEBUG_REG02_MH_CP_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_RB_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_PA_writeclean_MASK | \
+      MH_DEBUG_REG02_BRC_BID_MASK | \
+      MH_DEBUG_REG02_BRC_BRESP_MASK)
+
+#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, mh_pa_writeclean, brc_bid, brc_bresp) \
+     ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \
+      (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \
+      (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \
+      (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \
+      (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \
+      (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) | \
+      (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \
+      (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT))
+
+#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_PA_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_PA_writeclean_MASK) >> MH_DEBUG_REG02_MH_PA_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_PA_writeclean(mh_debug_reg02_reg, mh_pa_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_PA_writeclean_MASK) | (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_pa_writeclean               : MH_DEBUG_REG02_MH_PA_writeclean_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int                                : 12;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int mh_pa_writeclean               : MH_DEBUG_REG02_MH_PA_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+     } mh_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg02_t f;
+} mh_debug_reg02_u;
+
+
+/*
+ * MH_DEBUG_REG03 struct
+ */
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG03_MASK \
+     (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK)
+
+#define MH_DEBUG_REG03(mh_clnt_data_31_0) \
+     ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \
+     ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \
+     mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg03_t f;
+} mh_debug_reg03_u;
+
+
+/*
+ * MH_DEBUG_REG04 struct
+ */
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG04_MASK \
+     (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK)
+
+#define MH_DEBUG_REG04(mh_clnt_data_63_32) \
+     ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \
+     ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \
+     mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg04_t f;
+} mh_debug_reg04_u;
+
+
+/*
+ * MH_DEBUG_REG05 struct
+ */
+
+#define MH_DEBUG_REG05_CP_MH_send_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_tag_SIZE  3
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0
+#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1
+#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002
+#define MH_DEBUG_REG05_CP_MH_tag_MASK  0x0000001c
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG05_MASK \
+     (MH_DEBUG_REG05_CP_MH_send_MASK | \
+      MH_DEBUG_REG05_CP_MH_write_MASK | \
+      MH_DEBUG_REG05_CP_MH_tag_MASK | \
+      MH_DEBUG_REG05_CP_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \
+     ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \
+      (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \
+      (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+     } mh_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+     } mh_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg05_t f;
+} mh_debug_reg05_u;
+
+
+/*
+ * MH_DEBUG_REG06 struct
+ */
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG06_MASK \
+     (MH_DEBUG_REG06_CP_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG06(cp_mh_data_31_0) \
+     ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \
+     ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \
+     mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg06_t f;
+} mh_debug_reg06_u;
+
+
+/*
+ * MH_DEBUG_REG07 struct
+ */
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG07_MASK \
+     (MH_DEBUG_REG07_CP_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG07(cp_mh_data_63_32) \
+     ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \
+     ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \
+     mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg07_t f;
+} mh_debug_reg07_u;
+
+
+/*
+ * MH_DEBUG_REG08 struct
+ */
+
+#define MH_DEBUG_REG08_CP_MH_be_SIZE   8
+#define MH_DEBUG_REG08_RB_MH_be_SIZE   8
+#define MH_DEBUG_REG08_PA_MH_be_SIZE   8
+
+#define MH_DEBUG_REG08_CP_MH_be_SHIFT  0
+#define MH_DEBUG_REG08_RB_MH_be_SHIFT  8
+#define MH_DEBUG_REG08_PA_MH_be_SHIFT  16
+
+#define MH_DEBUG_REG08_CP_MH_be_MASK   0x000000ff
+#define MH_DEBUG_REG08_RB_MH_be_MASK   0x0000ff00
+#define MH_DEBUG_REG08_PA_MH_be_MASK   0x00ff0000
+
+#define MH_DEBUG_REG08_MASK \
+     (MH_DEBUG_REG08_CP_MH_be_MASK | \
+      MH_DEBUG_REG08_RB_MH_be_MASK | \
+      MH_DEBUG_REG08_PA_MH_be_MASK)
+
+#define MH_DEBUG_REG08(cp_mh_be, rb_mh_be, pa_mh_be) \
+     ((cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) | \
+      (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) | \
+      (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT))
+
+#define MH_DEBUG_REG08_GET_CP_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_CP_MH_be_MASK) >> MH_DEBUG_REG08_CP_MH_be_SHIFT)
+#define MH_DEBUG_REG08_GET_RB_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_RB_MH_be_MASK) >> MH_DEBUG_REG08_RB_MH_be_SHIFT)
+#define MH_DEBUG_REG08_GET_PA_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_PA_MH_be_MASK) >> MH_DEBUG_REG08_PA_MH_be_SHIFT)
+
+#define MH_DEBUG_REG08_SET_CP_MH_be(mh_debug_reg08_reg, cp_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_CP_MH_be_MASK) | (cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT)
+#define MH_DEBUG_REG08_SET_RB_MH_be(mh_debug_reg08_reg, rb_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_RB_MH_be_MASK) | (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT)
+#define MH_DEBUG_REG08_SET_PA_MH_be(mh_debug_reg08_reg, pa_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_PA_MH_be_MASK) | (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int cp_mh_be                       : MH_DEBUG_REG08_CP_MH_be_SIZE;
+          unsigned int rb_mh_be                       : MH_DEBUG_REG08_RB_MH_be_SIZE;
+          unsigned int pa_mh_be                       : MH_DEBUG_REG08_PA_MH_be_SIZE;
+          unsigned int                                : 8;
+     } mh_debug_reg08_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int                                : 8;
+          unsigned int pa_mh_be                       : MH_DEBUG_REG08_PA_MH_be_SIZE;
+          unsigned int rb_mh_be                       : MH_DEBUG_REG08_RB_MH_be_SIZE;
+          unsigned int cp_mh_be                       : MH_DEBUG_REG08_CP_MH_be_SIZE;
+     } mh_debug_reg08_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg08_t f;
+} mh_debug_reg08_u;
+
+
+/*
+ * MH_DEBUG_REG09 struct
+ */
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 3
+#define MH_DEBUG_REG09_VGT_MH_send_SIZE 1
+#define MH_DEBUG_REG09_VGT_MH_tagbe_SIZE 1
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG09_VGT_MH_send_SHIFT 3
+#define MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT 4
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000007
+#define MH_DEBUG_REG09_VGT_MH_send_MASK 0x00000008
+#define MH_DEBUG_REG09_VGT_MH_tagbe_MASK 0x00000010
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG09_MASK \
+     (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG09_VGT_MH_send_MASK | \
+      MH_DEBUG_REG09_VGT_MH_tagbe_MASK | \
+      MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG09(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \
+     ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \
+      (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) | \
+      (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) | \
+      (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_send(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_send_MASK) >> MH_DEBUG_REG09_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_tagbe(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_ad_31_5(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_send(mh_debug_reg09_reg, vgt_mh_send) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_tagbe(mh_debug_reg09_reg, vgt_mh_tagbe) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_ad_31_5(mh_debug_reg09_reg, vgt_mh_ad_31_5) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG09_VGT_MH_send_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE;
+     } mh_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG09_VGT_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg09_t f;
+} mh_debug_reg09_u;
+
+
+/*
+ * MH_DEBUG_REG10 struct
+ */
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG10_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG10_TC_MH_mask_SIZE 2
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG10_TC_MH_send_SHIFT 2
+#define MH_DEBUG_REG10_TC_MH_mask_SHIFT 3
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG10_TC_MH_send_MASK 0x00000004
+#define MH_DEBUG_REG10_TC_MH_mask_MASK 0x00000018
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG10_MASK \
+     (MH_DEBUG_REG10_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG10_TC_MH_send_MASK | \
+      MH_DEBUG_REG10_TC_MH_mask_MASK | \
+      MH_DEBUG_REG10_TC_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG10(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) | \
+      (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) | \
+      (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG10_GET_ALWAYS_ZERO(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_mask(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_mask_MASK) >> MH_DEBUG_REG10_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_addr_31_5(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG10_SET_ALWAYS_ZERO(mh_debug_reg10_reg, always_zero) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_mask(mh_debug_reg10_reg, tc_mh_mask) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_addr_31_5(mh_debug_reg10_reg, tc_mh_addr_31_5) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int always_zero                    : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG10_TC_MH_mask_SIZE;
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE;
+     } mh_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG10_TC_MH_mask_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg10_t f;
+} mh_debug_reg10_u;
+
+
+/*
+ * MH_DEBUG_REG11 struct
+ */
+
+#define MH_DEBUG_REG11_TC_MH_info_SIZE 25
+#define MH_DEBUG_REG11_TC_MH_send_SIZE 1
+
+#define MH_DEBUG_REG11_TC_MH_info_SHIFT 0
+#define MH_DEBUG_REG11_TC_MH_send_SHIFT 25
+
+#define MH_DEBUG_REG11_TC_MH_info_MASK 0x01ffffff
+#define MH_DEBUG_REG11_TC_MH_send_MASK 0x02000000
+
+#define MH_DEBUG_REG11_MASK \
+     (MH_DEBUG_REG11_TC_MH_info_MASK | \
+      MH_DEBUG_REG11_TC_MH_send_MASK)
+
+#define MH_DEBUG_REG11(tc_mh_info, tc_mh_send) \
+     ((tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT))
+
+#define MH_DEBUG_REG11_GET_TC_MH_info(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_info_MASK) >> MH_DEBUG_REG11_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG11_GET_TC_MH_send(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_send_MASK) >> MH_DEBUG_REG11_TC_MH_send_SHIFT)
+
+#define MH_DEBUG_REG11_SET_TC_MH_info(mh_debug_reg11_reg, tc_mh_info) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG11_SET_TC_MH_send(mh_debug_reg11_reg, tc_mh_send) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int tc_mh_info                     : MH_DEBUG_REG11_TC_MH_info_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG11_TC_MH_send_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int                                : 6;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG11_TC_MH_send_SIZE;
+          unsigned int tc_mh_info                     : MH_DEBUG_REG11_TC_MH_info_SIZE;
+     } mh_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg11_t f;
+} mh_debug_reg11_u;
+
+
+/*
+ * MH_DEBUG_REG12 struct
+ */
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_SIZE 25
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE 1
+#define MH_DEBUG_REG12_TC_MH_written_SIZE 1
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT 0
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT 25
+#define MH_DEBUG_REG12_TC_MH_written_SHIFT 26
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_MASK 0x01ffffff
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK 0x02000000
+#define MH_DEBUG_REG12_TC_MH_written_MASK 0x04000000
+
+#define MH_DEBUG_REG12_MASK \
+     (MH_DEBUG_REG12_MH_TC_mcinfo_MASK | \
+      MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK | \
+      MH_DEBUG_REG12_TC_MH_written_MASK)
+
+#define MH_DEBUG_REG12(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \
+     ((mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) | \
+      (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT))
+
+#define MH_DEBUG_REG12_GET_MH_TC_mcinfo(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG12_GET_MH_TC_mcinfo_send(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_MH_written(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_MH_written_MASK) >> MH_DEBUG_REG12_TC_MH_written_SHIFT)
+
+#define MH_DEBUG_REG12_SET_MH_TC_mcinfo(mh_debug_reg12_reg, mh_tc_mcinfo) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG12_SET_MH_TC_mcinfo_send(mh_debug_reg12_reg, mh_tc_mcinfo_send) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_MH_written(mh_debug_reg12_reg, tc_mh_written) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG12_TC_MH_written_SIZE;
+          unsigned int                                : 5;
+     } mh_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int                                : 5;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG12_TC_MH_written_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE;
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE;
+     } mh_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg12_t f;
+} mh_debug_reg12_u;
+
+
+/*
+ * MH_DEBUG_REG13 struct
+ */
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1
+#define MH_DEBUG_REG13_TC_ROQ_MASK_SIZE 2
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE 27
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 2
+#define MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT 3
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT 5
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x00000004
+#define MH_DEBUG_REG13_TC_ROQ_MASK_MASK 0x00000018
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG13_MASK \
+     (MH_DEBUG_REG13_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_SEND_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_MASK_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK)
+
+#define MH_DEBUG_REG13(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) | \
+      (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) | \
+      (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT))
+
+#define MH_DEBUG_REG13_GET_ALWAYS_ZERO(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_MASK(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_ADDR_31_5(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)
+
+#define MH_DEBUG_REG13_SET_ALWAYS_ZERO(mh_debug_reg13_reg, always_zero) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_MASK(mh_debug_reg13_reg, tc_roq_mask) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_ADDR_31_5(mh_debug_reg13_reg, tc_roq_addr_31_5) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int always_zero                    : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE;
+     } mh_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg13_t f;
+} mh_debug_reg13_u;
+
+
+/*
+ * MH_DEBUG_REG14 struct
+ */
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_SIZE 25
+#define MH_DEBUG_REG14_TC_ROQ_SEND_SIZE 1
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT 0
+#define MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT 25
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_MASK 0x01ffffff
+#define MH_DEBUG_REG14_TC_ROQ_SEND_MASK 0x02000000
+
+#define MH_DEBUG_REG14_MASK \
+     (MH_DEBUG_REG14_TC_ROQ_INFO_MASK | \
+      MH_DEBUG_REG14_TC_ROQ_SEND_MASK)
+
+#define MH_DEBUG_REG14(tc_roq_info, tc_roq_send) \
+     ((tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT))
+
+#define MH_DEBUG_REG14_GET_TC_ROQ_INFO(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG14_GET_TC_ROQ_SEND(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)
+
+#define MH_DEBUG_REG14_SET_TC_ROQ_INFO(mh_debug_reg14_reg, tc_roq_info) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG14_SET_TC_ROQ_SEND(mh_debug_reg14_reg, tc_roq_send) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int tc_roq_info                    : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int                                : 6;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_info                    : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE;
+     } mh_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg14_t f;
+} mh_debug_reg14_u;
+
+
+/*
+ * MH_DEBUG_REG15 struct
+ */
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG15_RB_MH_send_SIZE 1
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG15_RB_MH_send_SHIFT 4
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG15_RB_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG15_MASK \
+     (MH_DEBUG_REG15_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG15_RB_MH_send_MASK | \
+      MH_DEBUG_REG15_RB_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG15(always_zero, rb_mh_send, rb_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) | \
+      (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) | \
+      (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG15_GET_ALWAYS_ZERO(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG15_GET_RB_MH_send(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_send_MASK) >> MH_DEBUG_REG15_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG15_GET_RB_MH_addr_31_5(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG15_SET_ALWAYS_ZERO(mh_debug_reg15_reg, always_zero) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG15_SET_RB_MH_send(mh_debug_reg15_reg, rb_mh_send) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG15_SET_RB_MH_addr_31_5(mh_debug_reg15_reg, rb_mh_addr_31_5) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int always_zero                    : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG15_RB_MH_send_SIZE;
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE;
+     } mh_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG15_RB_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg15_t f;
+} mh_debug_reg15_u;
+
+
+/*
+ * MH_DEBUG_REG16 struct
+ */
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG16_MASK \
+     (MH_DEBUG_REG16_RB_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG16(rb_mh_data_31_0) \
+     ((rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG16_GET_RB_MH_data_31_0(mh_debug_reg16) \
+     ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG16_SET_RB_MH_data_31_0(mh_debug_reg16_reg, rb_mh_data_31_0) \
+     mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg16_t f;
+} mh_debug_reg16_u;
+
+
+/*
+ * MH_DEBUG_REG17 struct
+ */
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG17_MASK \
+     (MH_DEBUG_REG17_RB_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG17(rb_mh_data_63_32) \
+     ((rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG17_GET_RB_MH_data_63_32(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG17_SET_RB_MH_data_63_32(mh_debug_reg17_reg, rb_mh_data_63_32) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg17_t f;
+} mh_debug_reg17_u;
+
+
+/*
+ * MH_DEBUG_REG18 struct
+ */
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG18_PA_MH_send_SIZE 1
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG18_PA_MH_send_SHIFT 4
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG18_PA_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG18_MASK \
+     (MH_DEBUG_REG18_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG18_PA_MH_send_MASK | \
+      MH_DEBUG_REG18_PA_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG18(always_zero, pa_mh_send, pa_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) | \
+      (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) | \
+      (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG18_GET_ALWAYS_ZERO(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG18_GET_PA_MH_send(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_send_MASK) >> MH_DEBUG_REG18_PA_MH_send_SHIFT)
+#define MH_DEBUG_REG18_GET_PA_MH_addr_31_5(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) >> MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG18_SET_ALWAYS_ZERO(mh_debug_reg18_reg, always_zero) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG18_SET_PA_MH_send(mh_debug_reg18_reg, pa_mh_send) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_send_MASK) | (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT)
+#define MH_DEBUG_REG18_SET_PA_MH_addr_31_5(mh_debug_reg18_reg, pa_mh_addr_31_5) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) | (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int always_zero                    : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE;
+          unsigned int pa_mh_send                     : MH_DEBUG_REG18_PA_MH_send_SIZE;
+          unsigned int pa_mh_addr_31_5                : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE;
+     } mh_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int pa_mh_addr_31_5                : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE;
+          unsigned int pa_mh_send                     : MH_DEBUG_REG18_PA_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg18_t f;
+} mh_debug_reg18_u;
+
+
+/*
+ * MH_DEBUG_REG19 struct
+ */
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG19_MASK \
+     (MH_DEBUG_REG19_PA_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG19(pa_mh_data_31_0) \
+     ((pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG19_GET_PA_MH_data_31_0(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_PA_MH_data_31_0_MASK) >> MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG19_SET_PA_MH_data_31_0(mh_debug_reg19_reg, pa_mh_data_31_0) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_PA_MH_data_31_0_MASK) | (pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int pa_mh_data_31_0                : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE;
+     } mh_debug_reg19_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int pa_mh_data_31_0                : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE;
+     } mh_debug_reg19_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg19_t f;
+} mh_debug_reg19_u;
+
+
+/*
+ * MH_DEBUG_REG20 struct
+ */
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG20_MASK \
+     (MH_DEBUG_REG20_PA_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG20(pa_mh_data_63_32) \
+     ((pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG20_GET_PA_MH_data_63_32(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_PA_MH_data_63_32_MASK) >> MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG20_SET_PA_MH_data_63_32(mh_debug_reg20_reg, pa_mh_data_63_32) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_PA_MH_data_63_32_MASK) | (pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int pa_mh_data_63_32               : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE;
+     } mh_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int pa_mh_data_63_32               : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE;
+     } mh_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg20_t f;
+} mh_debug_reg20_u;
+
+
+/*
+ * MH_DEBUG_REG21 struct
+ */
+
+#define MH_DEBUG_REG21_AVALID_q_SIZE   1
+#define MH_DEBUG_REG21_AREADY_q_SIZE   1
+#define MH_DEBUG_REG21_AID_q_SIZE      3
+#define MH_DEBUG_REG21_ALEN_q_2_0_SIZE 3
+#define MH_DEBUG_REG21_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG21_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG21_ARID_q_SIZE     3
+#define MH_DEBUG_REG21_ARLEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG21_RVALID_q_SIZE   1
+#define MH_DEBUG_REG21_RREADY_q_SIZE   1
+#define MH_DEBUG_REG21_RLAST_q_SIZE    1
+#define MH_DEBUG_REG21_RID_q_SIZE      3
+#define MH_DEBUG_REG21_WVALID_q_SIZE   1
+#define MH_DEBUG_REG21_WREADY_q_SIZE   1
+#define MH_DEBUG_REG21_WLAST_q_SIZE    1
+#define MH_DEBUG_REG21_WID_q_SIZE      3
+#define MH_DEBUG_REG21_BVALID_q_SIZE   1
+#define MH_DEBUG_REG21_BREADY_q_SIZE   1
+#define MH_DEBUG_REG21_BID_q_SIZE      3
+
+#define MH_DEBUG_REG21_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG21_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG21_AID_q_SHIFT     2
+#define MH_DEBUG_REG21_ALEN_q_2_0_SHIFT 5
+#define MH_DEBUG_REG21_ARVALID_q_SHIFT 8
+#define MH_DEBUG_REG21_ARREADY_q_SHIFT 9
+#define MH_DEBUG_REG21_ARID_q_SHIFT    10
+#define MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT 13
+#define MH_DEBUG_REG21_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG21_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG21_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG21_RID_q_SHIFT     18
+#define MH_DEBUG_REG21_WVALID_q_SHIFT  21
+#define MH_DEBUG_REG21_WREADY_q_SHIFT  22
+#define MH_DEBUG_REG21_WLAST_q_SHIFT   23
+#define MH_DEBUG_REG21_WID_q_SHIFT     24
+#define MH_DEBUG_REG21_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG21_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG21_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG21_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG21_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG21_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG21_ALEN_q_2_0_MASK 0x000000e0
+#define MH_DEBUG_REG21_ARVALID_q_MASK  0x00000100
+#define MH_DEBUG_REG21_ARREADY_q_MASK  0x00000200
+#define MH_DEBUG_REG21_ARID_q_MASK     0x00001c00
+#define MH_DEBUG_REG21_ARLEN_q_1_0_MASK 0x00006000
+#define MH_DEBUG_REG21_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG21_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG21_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG21_RID_q_MASK      0x001c0000
+#define MH_DEBUG_REG21_WVALID_q_MASK   0x00200000
+#define MH_DEBUG_REG21_WREADY_q_MASK   0x00400000
+#define MH_DEBUG_REG21_WLAST_q_MASK    0x00800000
+#define MH_DEBUG_REG21_WID_q_MASK      0x07000000
+#define MH_DEBUG_REG21_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG21_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG21_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG21_MASK \
+     (MH_DEBUG_REG21_AVALID_q_MASK | \
+      MH_DEBUG_REG21_AREADY_q_MASK | \
+      MH_DEBUG_REG21_AID_q_MASK | \
+      MH_DEBUG_REG21_ALEN_q_2_0_MASK | \
+      MH_DEBUG_REG21_ARVALID_q_MASK | \
+      MH_DEBUG_REG21_ARREADY_q_MASK | \
+      MH_DEBUG_REG21_ARID_q_MASK | \
+      MH_DEBUG_REG21_ARLEN_q_1_0_MASK | \
+      MH_DEBUG_REG21_RVALID_q_MASK | \
+      MH_DEBUG_REG21_RREADY_q_MASK | \
+      MH_DEBUG_REG21_RLAST_q_MASK | \
+      MH_DEBUG_REG21_RID_q_MASK | \
+      MH_DEBUG_REG21_WVALID_q_MASK | \
+      MH_DEBUG_REG21_WREADY_q_MASK | \
+      MH_DEBUG_REG21_WLAST_q_MASK | \
+      MH_DEBUG_REG21_WID_q_MASK | \
+      MH_DEBUG_REG21_BVALID_q_MASK | \
+      MH_DEBUG_REG21_BREADY_q_MASK | \
+      MH_DEBUG_REG21_BID_q_MASK)
+
+#define MH_DEBUG_REG21(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) | \
+      (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) | \
+      (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) | \
+      (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG21_BID_q_SHIFT))
+
+#define MH_DEBUG_REG21_GET_AVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AVALID_q_MASK) >> MH_DEBUG_REG21_AVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_AREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AREADY_q_MASK) >> MH_DEBUG_REG21_AREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_AID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AID_q_MASK) >> MH_DEBUG_REG21_AID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ALEN_q_2_0(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ALEN_q_2_0_MASK) >> MH_DEBUG_REG21_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG21_GET_ARVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARVALID_q_MASK) >> MH_DEBUG_REG21_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARREADY_q_MASK) >> MH_DEBUG_REG21_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARID_q_MASK) >> MH_DEBUG_REG21_ARID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARLEN_q_1_0(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG21_GET_RVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RVALID_q_MASK) >> MH_DEBUG_REG21_RVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RREADY_q_MASK) >> MH_DEBUG_REG21_RREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RLAST_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RLAST_q_MASK) >> MH_DEBUG_REG21_RLAST_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RID_q_MASK) >> MH_DEBUG_REG21_RID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WVALID_q_MASK) >> MH_DEBUG_REG21_WVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WREADY_q_MASK) >> MH_DEBUG_REG21_WREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WLAST_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WLAST_q_MASK) >> MH_DEBUG_REG21_WLAST_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WID_q_MASK) >> MH_DEBUG_REG21_WID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BVALID_q_MASK) >> MH_DEBUG_REG21_BVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BREADY_q_MASK) >> MH_DEBUG_REG21_BREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BID_q_MASK) >> MH_DEBUG_REG21_BID_q_SHIFT)
+
+#define MH_DEBUG_REG21_SET_AVALID_q(mh_debug_reg21_reg, avalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_AREADY_q(mh_debug_reg21_reg, aready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_AID_q(mh_debug_reg21_reg, aid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AID_q_MASK) | (aid_q << MH_DEBUG_REG21_AID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ALEN_q_2_0(mh_debug_reg21_reg, alen_q_2_0) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG21_SET_ARVALID_q(mh_debug_reg21_reg, arvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARREADY_q(mh_debug_reg21_reg, arready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARID_q(mh_debug_reg21_reg, arid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARID_q_MASK) | (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARLEN_q_1_0(mh_debug_reg21_reg, arlen_q_1_0) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG21_SET_RVALID_q(mh_debug_reg21_reg, rvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RREADY_q(mh_debug_reg21_reg, rready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RLAST_q(mh_debug_reg21_reg, rlast_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RID_q(mh_debug_reg21_reg, rid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RID_q_MASK) | (rid_q << MH_DEBUG_REG21_RID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WVALID_q(mh_debug_reg21_reg, wvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WREADY_q(mh_debug_reg21_reg, wready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WLAST_q(mh_debug_reg21_reg, wlast_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WID_q(mh_debug_reg21_reg, wid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WID_q_MASK) | (wid_q << MH_DEBUG_REG21_WID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BVALID_q(mh_debug_reg21_reg, bvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BREADY_q(mh_debug_reg21_reg, bready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BID_q(mh_debug_reg21_reg, bid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BID_q_MASK) | (bid_q << MH_DEBUG_REG21_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG21_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG21_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG21_AID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG21_ALEN_q_2_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG21_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG21_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG21_ARID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG21_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG21_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG21_RLAST_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG21_RID_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG21_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG21_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG21_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG21_WID_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG21_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG21_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG21_BID_q_SIZE;
+     } mh_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int bid_q                          : MH_DEBUG_REG21_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG21_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG21_BVALID_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG21_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG21_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG21_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG21_WVALID_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG21_RID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG21_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG21_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG21_RVALID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG21_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG21_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG21_ARVALID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG21_ALEN_q_2_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG21_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG21_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG21_AVALID_q_SIZE;
+     } mh_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg21_t f;
+} mh_debug_reg21_u;
+
+
+/*
+ * MH_DEBUG_REG22 struct
+ */
+
+#define MH_DEBUG_REG22_AVALID_q_SIZE   1
+#define MH_DEBUG_REG22_AREADY_q_SIZE   1
+#define MH_DEBUG_REG22_AID_q_SIZE      3
+#define MH_DEBUG_REG22_ALEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG22_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG22_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG22_ARID_q_SIZE     3
+#define MH_DEBUG_REG22_ARLEN_q_1_1_SIZE 1
+#define MH_DEBUG_REG22_WVALID_q_SIZE   1
+#define MH_DEBUG_REG22_WREADY_q_SIZE   1
+#define MH_DEBUG_REG22_WLAST_q_SIZE    1
+#define MH_DEBUG_REG22_WID_q_SIZE      3
+#define MH_DEBUG_REG22_WSTRB_q_SIZE    8
+#define MH_DEBUG_REG22_BVALID_q_SIZE   1
+#define MH_DEBUG_REG22_BREADY_q_SIZE   1
+#define MH_DEBUG_REG22_BID_q_SIZE      3
+
+#define MH_DEBUG_REG22_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG22_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG22_AID_q_SHIFT     2
+#define MH_DEBUG_REG22_ALEN_q_1_0_SHIFT 5
+#define MH_DEBUG_REG22_ARVALID_q_SHIFT 7
+#define MH_DEBUG_REG22_ARREADY_q_SHIFT 8
+#define MH_DEBUG_REG22_ARID_q_SHIFT    9
+#define MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT 12
+#define MH_DEBUG_REG22_WVALID_q_SHIFT  13
+#define MH_DEBUG_REG22_WREADY_q_SHIFT  14
+#define MH_DEBUG_REG22_WLAST_q_SHIFT   15
+#define MH_DEBUG_REG22_WID_q_SHIFT     16
+#define MH_DEBUG_REG22_WSTRB_q_SHIFT   19
+#define MH_DEBUG_REG22_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG22_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG22_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG22_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG22_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG22_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG22_ALEN_q_1_0_MASK 0x00000060
+#define MH_DEBUG_REG22_ARVALID_q_MASK  0x00000080
+#define MH_DEBUG_REG22_ARREADY_q_MASK  0x00000100
+#define MH_DEBUG_REG22_ARID_q_MASK     0x00000e00
+#define MH_DEBUG_REG22_ARLEN_q_1_1_MASK 0x00001000
+#define MH_DEBUG_REG22_WVALID_q_MASK   0x00002000
+#define MH_DEBUG_REG22_WREADY_q_MASK   0x00004000
+#define MH_DEBUG_REG22_WLAST_q_MASK    0x00008000
+#define MH_DEBUG_REG22_WID_q_MASK      0x00070000
+#define MH_DEBUG_REG22_WSTRB_q_MASK    0x07f80000
+#define MH_DEBUG_REG22_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG22_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG22_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG22_MASK \
+     (MH_DEBUG_REG22_AVALID_q_MASK | \
+      MH_DEBUG_REG22_AREADY_q_MASK | \
+      MH_DEBUG_REG22_AID_q_MASK | \
+      MH_DEBUG_REG22_ALEN_q_1_0_MASK | \
+      MH_DEBUG_REG22_ARVALID_q_MASK | \
+      MH_DEBUG_REG22_ARREADY_q_MASK | \
+      MH_DEBUG_REG22_ARID_q_MASK | \
+      MH_DEBUG_REG22_ARLEN_q_1_1_MASK | \
+      MH_DEBUG_REG22_WVALID_q_MASK | \
+      MH_DEBUG_REG22_WREADY_q_MASK | \
+      MH_DEBUG_REG22_WLAST_q_MASK | \
+      MH_DEBUG_REG22_WID_q_MASK | \
+      MH_DEBUG_REG22_WSTRB_q_MASK | \
+      MH_DEBUG_REG22_BVALID_q_MASK | \
+      MH_DEBUG_REG22_BREADY_q_MASK | \
+      MH_DEBUG_REG22_BID_q_MASK)
+
+#define MH_DEBUG_REG22(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) | \
+      (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) | \
+      (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) | \
+      (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG22_BID_q_SHIFT))
+
+#define MH_DEBUG_REG22_GET_AVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AVALID_q_MASK) >> MH_DEBUG_REG22_AVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_AREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AREADY_q_MASK) >> MH_DEBUG_REG22_AREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_AID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AID_q_MASK) >> MH_DEBUG_REG22_AID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ALEN_q_1_0(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ALEN_q_1_0_MASK) >> MH_DEBUG_REG22_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG22_GET_ARVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARVALID_q_MASK) >> MH_DEBUG_REG22_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARREADY_q_MASK) >> MH_DEBUG_REG22_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARID_q_MASK) >> MH_DEBUG_REG22_ARID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARLEN_q_1_1(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG22_GET_WVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WVALID_q_MASK) >> MH_DEBUG_REG22_WVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WREADY_q_MASK) >> MH_DEBUG_REG22_WREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WLAST_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WLAST_q_MASK) >> MH_DEBUG_REG22_WLAST_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WID_q_MASK) >> MH_DEBUG_REG22_WID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WSTRB_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WSTRB_q_MASK) >> MH_DEBUG_REG22_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BVALID_q_MASK) >> MH_DEBUG_REG22_BVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BREADY_q_MASK) >> MH_DEBUG_REG22_BREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BID_q_MASK) >> MH_DEBUG_REG22_BID_q_SHIFT)
+
+#define MH_DEBUG_REG22_SET_AVALID_q(mh_debug_reg22_reg, avalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_AREADY_q(mh_debug_reg22_reg, aready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_AID_q(mh_debug_reg22_reg, aid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AID_q_MASK) | (aid_q << MH_DEBUG_REG22_AID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ALEN_q_1_0(mh_debug_reg22_reg, alen_q_1_0) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG22_SET_ARVALID_q(mh_debug_reg22_reg, arvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARREADY_q(mh_debug_reg22_reg, arready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARID_q(mh_debug_reg22_reg, arid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARID_q_MASK) | (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARLEN_q_1_1(mh_debug_reg22_reg, arlen_q_1_1) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG22_SET_WVALID_q(mh_debug_reg22_reg, wvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WREADY_q(mh_debug_reg22_reg, wready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WLAST_q(mh_debug_reg22_reg, wlast_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WID_q(mh_debug_reg22_reg, wid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WID_q_MASK) | (wid_q << MH_DEBUG_REG22_WID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WSTRB_q(mh_debug_reg22_reg, wstrb_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BVALID_q(mh_debug_reg22_reg, bvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BREADY_q(mh_debug_reg22_reg, bready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BID_q(mh_debug_reg22_reg, bid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BID_q_MASK) | (bid_q << MH_DEBUG_REG22_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG22_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG22_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG22_AID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG22_ALEN_q_1_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG22_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG22_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG22_ARID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG22_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG22_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG22_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG22_WID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG22_WSTRB_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG22_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG22_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG22_BID_q_SIZE;
+     } mh_debug_reg22_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int bid_q                          : MH_DEBUG_REG22_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG22_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG22_BVALID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG22_WSTRB_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG22_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG22_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG22_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG22_WVALID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG22_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG22_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG22_ARVALID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG22_ALEN_q_1_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG22_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG22_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG22_AVALID_q_SIZE;
+     } mh_debug_reg22_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg22_t f;
+} mh_debug_reg22_u;
+
+
+/*
+ * MH_DEBUG_REG23 struct
+ */
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG23_CTRL_ARC_ID_SIZE 3
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE 28
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT 0
+#define MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT 1
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT 4
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK 0x00000001
+#define MH_DEBUG_REG23_CTRL_ARC_ID_MASK 0x0000000e
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_MASK 0xfffffff0
+
+#define MH_DEBUG_REG23_MASK \
+     (MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG23_CTRL_ARC_ID_MASK | \
+      MH_DEBUG_REG23_CTRL_ARC_PAD_MASK)
+
+#define MH_DEBUG_REG23(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \
+     ((arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) | \
+      (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) | \
+      (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT))
+
+#define MH_DEBUG_REG23_GET_ARC_CTRL_RE_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG23_GET_CTRL_ARC_ID(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG23_GET_CTRL_ARC_PAD(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)
+
+#define MH_DEBUG_REG23_SET_ARC_CTRL_RE_q(mh_debug_reg23_reg, arc_ctrl_re_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG23_SET_CTRL_ARC_ID(mh_debug_reg23_reg, ctrl_arc_id) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG23_SET_CTRL_ARC_PAD(mh_debug_reg23_reg, ctrl_arc_pad) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE;
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE;
+     } mh_debug_reg23_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE;
+     } mh_debug_reg23_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg23_t f;
+} mh_debug_reg23_u;
+
+
+/*
+ * MH_DEBUG_REG24 struct
+ */
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG24_REG_A_SIZE      14
+#define MH_DEBUG_REG24_REG_RE_SIZE     1
+#define MH_DEBUG_REG24_REG_WE_SIZE     1
+#define MH_DEBUG_REG24_BLOCK_RS_SIZE   1
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG24_REG_A_SHIFT     2
+#define MH_DEBUG_REG24_REG_RE_SHIFT    16
+#define MH_DEBUG_REG24_REG_WE_SHIFT    17
+#define MH_DEBUG_REG24_BLOCK_RS_SHIFT  18
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG24_REG_A_MASK      0x0000fffc
+#define MH_DEBUG_REG24_REG_RE_MASK     0x00010000
+#define MH_DEBUG_REG24_REG_WE_MASK     0x00020000
+#define MH_DEBUG_REG24_BLOCK_RS_MASK   0x00040000
+
+#define MH_DEBUG_REG24_MASK \
+     (MH_DEBUG_REG24_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG24_REG_A_MASK | \
+      MH_DEBUG_REG24_REG_RE_MASK | \
+      MH_DEBUG_REG24_REG_WE_MASK | \
+      MH_DEBUG_REG24_BLOCK_RS_MASK)
+
+#define MH_DEBUG_REG24(always_zero, reg_a, reg_re, reg_we, block_rs) \
+     ((always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) | \
+      (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) | \
+      (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) | \
+      (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) | \
+      (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT))
+
+#define MH_DEBUG_REG24_GET_ALWAYS_ZERO(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_A(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_A_MASK) >> MH_DEBUG_REG24_REG_A_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_RE(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_RE_MASK) >> MH_DEBUG_REG24_REG_RE_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_WE(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_WE_MASK) >> MH_DEBUG_REG24_REG_WE_SHIFT)
+#define MH_DEBUG_REG24_GET_BLOCK_RS(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_BLOCK_RS_MASK) >> MH_DEBUG_REG24_BLOCK_RS_SHIFT)
+
+#define MH_DEBUG_REG24_SET_ALWAYS_ZERO(mh_debug_reg24_reg, always_zero) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_A(mh_debug_reg24_reg, reg_a) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_A_MASK) | (reg_a << MH_DEBUG_REG24_REG_A_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_RE(mh_debug_reg24_reg, reg_re) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_RE_MASK) | (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_WE(mh_debug_reg24_reg, reg_we) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_WE_MASK) | (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT)
+#define MH_DEBUG_REG24_SET_BLOCK_RS(mh_debug_reg24_reg, block_rs) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int always_zero                    : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG24_REG_A_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG24_REG_RE_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG24_REG_WE_SIZE;
+          unsigned int block_rs                       : MH_DEBUG_REG24_BLOCK_RS_SIZE;
+          unsigned int                                : 13;
+     } mh_debug_reg24_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int                                : 13;
+          unsigned int block_rs                       : MH_DEBUG_REG24_BLOCK_RS_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG24_REG_WE_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG24_REG_RE_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG24_REG_A_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg24_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg24_t f;
+} mh_debug_reg24_u;
+
+
+/*
+ * MH_DEBUG_REG25 struct
+ */
+
+#define MH_DEBUG_REG25_REG_WD_SIZE     32
+
+#define MH_DEBUG_REG25_REG_WD_SHIFT    0
+
+#define MH_DEBUG_REG25_REG_WD_MASK     0xffffffff
+
+#define MH_DEBUG_REG25_MASK \
+     (MH_DEBUG_REG25_REG_WD_MASK)
+
+#define MH_DEBUG_REG25(reg_wd) \
+     ((reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT))
+
+#define MH_DEBUG_REG25_GET_REG_WD(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_REG_WD_MASK) >> MH_DEBUG_REG25_REG_WD_SHIFT)
+
+#define MH_DEBUG_REG25_SET_REG_WD(mh_debug_reg25_reg, reg_wd) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG25_REG_WD_SIZE;
+     } mh_debug_reg25_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG25_REG_WD_SIZE;
+     } mh_debug_reg25_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg25_t f;
+} mh_debug_reg25_u;
+
+
+/*
+ * MH_DEBUG_REG26 struct
+ */
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_GAT_CLK_ENA_SIZE 1
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE 1
+#define MH_DEBUG_REG26_CNT_q_SIZE      6
+#define MH_DEBUG_REG26_TCD_EMPTY_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG26_MH_BUSY_d_SIZE  1
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE 1
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+#define MH_DEBUG_REG26_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG26_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_PA_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_PA_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG26_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG26_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG26_BRC_VALID_SIZE  1
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_SHIFT 0
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT 1
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT 2
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT 3
+#define MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT 4
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT 5
+#define MH_DEBUG_REG26_CNT_q_SHIFT     6
+#define MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT 12
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT 13
+#define MH_DEBUG_REG26_MH_BUSY_d_SHIFT 14
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT 15
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 16
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 17
+#define MH_DEBUG_REG26_CP_SEND_q_SHIFT 18
+#define MH_DEBUG_REG26_CP_RTR_q_SHIFT  19
+#define MH_DEBUG_REG26_VGT_SEND_q_SHIFT 20
+#define MH_DEBUG_REG26_VGT_RTR_q_SHIFT 21
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 22
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 23
+#define MH_DEBUG_REG26_RB_SEND_q_SHIFT 24
+#define MH_DEBUG_REG26_RB_RTR_q_SHIFT  25
+#define MH_DEBUG_REG26_PA_SEND_q_SHIFT 26
+#define MH_DEBUG_REG26_PA_RTR_q_SHIFT  27
+#define MH_DEBUG_REG26_RDC_VALID_SHIFT 28
+#define MH_DEBUG_REG26_RDC_RLAST_SHIFT 29
+#define MH_DEBUG_REG26_TLBMISS_VALID_SHIFT 30
+#define MH_DEBUG_REG26_BRC_VALID_SHIFT 31
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_MASK 0x00000001
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK 0x00000002
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK 0x00000004
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK 0x00000008
+#define MH_DEBUG_REG26_GAT_CLK_ENA_MASK 0x00000010
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK 0x00000020
+#define MH_DEBUG_REG26_CNT_q_MASK      0x00000fc0
+#define MH_DEBUG_REG26_TCD_EMPTY_q_MASK 0x00001000
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK 0x00002000
+#define MH_DEBUG_REG26_MH_BUSY_d_MASK  0x00004000
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK 0x00008000
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000
+#define MH_DEBUG_REG26_CP_SEND_q_MASK  0x00040000
+#define MH_DEBUG_REG26_CP_RTR_q_MASK   0x00080000
+#define MH_DEBUG_REG26_VGT_SEND_q_MASK 0x00100000
+#define MH_DEBUG_REG26_VGT_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00400000
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00800000
+#define MH_DEBUG_REG26_RB_SEND_q_MASK  0x01000000
+#define MH_DEBUG_REG26_RB_RTR_q_MASK   0x02000000
+#define MH_DEBUG_REG26_PA_SEND_q_MASK  0x04000000
+#define MH_DEBUG_REG26_PA_RTR_q_MASK   0x08000000
+#define MH_DEBUG_REG26_RDC_VALID_MASK  0x10000000
+#define MH_DEBUG_REG26_RDC_RLAST_MASK  0x20000000
+#define MH_DEBUG_REG26_TLBMISS_VALID_MASK 0x40000000
+#define MH_DEBUG_REG26_BRC_VALID_MASK  0x80000000
+
+#define MH_DEBUG_REG26_MASK \
+     (MH_DEBUG_REG26_MH_RBBM_busy_MASK | \
+      MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK | \
+      MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK | \
+      MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK | \
+      MH_DEBUG_REG26_GAT_CLK_ENA_MASK | \
+      MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK | \
+      MH_DEBUG_REG26_CNT_q_MASK | \
+      MH_DEBUG_REG26_TCD_EMPTY_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG26_MH_BUSY_d_MASK | \
+      MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK | \
+      MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK | \
+      MH_DEBUG_REG26_CP_SEND_q_MASK | \
+      MH_DEBUG_REG26_CP_RTR_q_MASK | \
+      MH_DEBUG_REG26_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG26_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG26_RB_SEND_q_MASK | \
+      MH_DEBUG_REG26_RB_RTR_q_MASK | \
+      MH_DEBUG_REG26_PA_SEND_q_MASK | \
+      MH_DEBUG_REG26_PA_RTR_q_MASK | \
+      MH_DEBUG_REG26_RDC_VALID_MASK | \
+      MH_DEBUG_REG26_RDC_RLAST_MASK | \
+      MH_DEBUG_REG26_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG26_BRC_VALID_MASK)
+
+#define MH_DEBUG_REG26(mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, mh_mmu_invalidate_invalidate_tc, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_dbg_q, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \
+     ((mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) | \
+      (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) | \
+      (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) | \
+      (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) | \
+      (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) | \
+      (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) | \
+      (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) | \
+      (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) | \
+      (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) | \
+      (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) | \
+      (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) | \
+      (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) | \
+      (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) | \
+      (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT))
+
+#define MH_DEBUG_REG26_GET_MH_RBBM_busy(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_RBBM_busy_MASK) >> MH_DEBUG_REG26_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_mh_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_GAT_CLK_ENA(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG26_GET_RBBM_MH_clk_en_override(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG26_GET_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CNT_q_MASK) >> MH_DEBUG_REG26_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TCD_EMPTY_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_EMPTY(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_BUSY_d(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_BUSY_d_MASK) >> MH_DEBUG_REG26_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG26_GET_ANY_CLNT_BUSY(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_q_MASK) >> MH_DEBUG_REG26_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_RTR_q_MASK) >> MH_DEBUG_REG26_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_VGT_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_SEND_q_MASK) >> MH_DEBUG_REG26_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_VGT_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_RTR_q_MASK) >> MH_DEBUG_REG26_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_q_MASK) >> MH_DEBUG_REG26_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_RTR_q_MASK) >> MH_DEBUG_REG26_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_PA_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_PA_SEND_q_MASK) >> MH_DEBUG_REG26_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_PA_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_PA_RTR_q_MASK) >> MH_DEBUG_REG26_PA_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RDC_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_VALID_MASK) >> MH_DEBUG_REG26_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG26_GET_RDC_RLAST(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_RLAST_MASK) >> MH_DEBUG_REG26_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG26_GET_TLBMISS_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TLBMISS_VALID_MASK) >> MH_DEBUG_REG26_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG26_GET_BRC_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_BRC_VALID_MASK) >> MH_DEBUG_REG26_BRC_VALID_SHIFT)
+
+#define MH_DEBUG_REG26_SET_MH_RBBM_busy(mh_debug_reg26_reg, mh_rbbm_busy) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_mh_clk_en_int(mh_debug_reg26_reg, mh_cib_mh_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg26_reg, mh_cib_mmu_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26_reg, mh_cib_tcroq_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_GAT_CLK_ENA(mh_debug_reg26_reg, gat_clk_ena) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG26_SET_RBBM_MH_clk_en_override(mh_debug_reg26_reg, rbbm_mh_clk_en_override) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG26_SET_CNT_q(mh_debug_reg26_reg, cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TCD_EMPTY_q(mh_debug_reg26_reg, tcd_empty_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_EMPTY(mh_debug_reg26_reg, tc_roq_empty) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_BUSY_d(mh_debug_reg26_reg, mh_busy_d) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG26_SET_ANY_CLNT_BUSY(mh_debug_reg26_reg, any_clnt_busy) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_all) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_tc) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_SEND_q(mh_debug_reg26_reg, cp_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_RTR_q(mh_debug_reg26_reg, cp_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_VGT_SEND_q(mh_debug_reg26_reg, vgt_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_VGT_RTR_q(mh_debug_reg26_reg, vgt_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_SEND_q(mh_debug_reg26_reg, rb_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_RTR_q(mh_debug_reg26_reg, rb_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_PA_SEND_q(mh_debug_reg26_reg, pa_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_PA_RTR_q(mh_debug_reg26_reg, pa_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RDC_VALID(mh_debug_reg26_reg, rdc_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG26_SET_RDC_RLAST(mh_debug_reg26_reg, rdc_rlast) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG26_SET_TLBMISS_VALID(mh_debug_reg26_reg, tlbmiss_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG26_SET_BRC_VALID(mh_debug_reg26_reg, brc_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG26_MH_RBBM_busy_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG26_CNT_q_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG26_MH_BUSY_d_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG26_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG26_CP_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG26_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG26_VGT_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG26_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG26_RB_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG26_PA_SEND_q_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG26_PA_RTR_q_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG26_RDC_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG26_RDC_RLAST_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG26_TLBMISS_VALID_SIZE;
+          unsigned int brc_valid                      : MH_DEBUG_REG26_BRC_VALID_SIZE;
+     } mh_debug_reg26_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int brc_valid                      : MH_DEBUG_REG26_BRC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG26_TLBMISS_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG26_RDC_RLAST_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG26_RDC_VALID_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG26_PA_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG26_PA_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG26_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG26_RB_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG26_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG26_VGT_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG26_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG26_CP_SEND_q_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG26_MH_BUSY_d_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG26_CNT_q_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG26_MH_RBBM_busy_SIZE;
+     } mh_debug_reg26_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg26_t f;
+} mh_debug_reg26_u;
+
+
+/*
+ * MH_DEBUG_REG27 struct
+ */
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE 3
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG27_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG27_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG27_ARB_WINNER_q_SIZE 3
+#define MH_DEBUG_REG27_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG27_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG27_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG27_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG27_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG27_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_PA_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG27_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG27_TCHOLD_IP_q_SIZE 1
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT 0
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT 3
+#define MH_DEBUG_REG27_EFF1_WINNER_SHIFT 6
+#define MH_DEBUG_REG27_ARB_WINNER_SHIFT 9
+#define MH_DEBUG_REG27_ARB_WINNER_q_SHIFT 12
+#define MH_DEBUG_REG27_EFF1_WIN_SHIFT  15
+#define MH_DEBUG_REG27_KILL_EFF1_SHIFT 16
+#define MH_DEBUG_REG27_ARB_HOLD_SHIFT  17
+#define MH_DEBUG_REG27_ARB_RTR_q_SHIFT 18
+#define MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT 19
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT 20
+#define MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT 21
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT 22
+#define MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT 23
+#define MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT 24
+#define MH_DEBUG_REG27_ARB_QUAL_SHIFT  25
+#define MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT 26
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT 27
+#define MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT 28
+#define MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT 29
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT 30
+#define MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT 31
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK 0x00000038
+#define MH_DEBUG_REG27_EFF1_WINNER_MASK 0x000001c0
+#define MH_DEBUG_REG27_ARB_WINNER_MASK 0x00000e00
+#define MH_DEBUG_REG27_ARB_WINNER_q_MASK 0x00007000
+#define MH_DEBUG_REG27_EFF1_WIN_MASK   0x00008000
+#define MH_DEBUG_REG27_KILL_EFF1_MASK  0x00010000
+#define MH_DEBUG_REG27_ARB_HOLD_MASK   0x00020000
+#define MH_DEBUG_REG27_ARB_RTR_q_MASK  0x00040000
+#define MH_DEBUG_REG27_CP_SEND_QUAL_MASK 0x00080000
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_MASK 0x00100000
+#define MH_DEBUG_REG27_TC_SEND_QUAL_MASK 0x00200000
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK 0x00400000
+#define MH_DEBUG_REG27_RB_SEND_QUAL_MASK 0x00800000
+#define MH_DEBUG_REG27_PA_SEND_QUAL_MASK 0x01000000
+#define MH_DEBUG_REG27_ARB_QUAL_MASK   0x02000000
+#define MH_DEBUG_REG27_CP_EFF1_REQ_MASK 0x04000000
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_MASK 0x08000000
+#define MH_DEBUG_REG27_TC_EFF1_REQ_MASK 0x10000000
+#define MH_DEBUG_REG27_RB_EFF1_REQ_MASK 0x20000000
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_MASK 0x40000000
+#define MH_DEBUG_REG27_TCHOLD_IP_q_MASK 0x80000000
+
+#define MH_DEBUG_REG27_MASK \
+     (MH_DEBUG_REG27_EFF2_FP_WINNER_MASK | \
+      MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG27_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG27_ARB_WINNER_MASK | \
+      MH_DEBUG_REG27_ARB_WINNER_q_MASK | \
+      MH_DEBUG_REG27_EFF1_WIN_MASK | \
+      MH_DEBUG_REG27_KILL_EFF1_MASK | \
+      MH_DEBUG_REG27_ARB_HOLD_MASK | \
+      MH_DEBUG_REG27_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG27_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG27_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_PA_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_ARB_QUAL_MASK | \
+      MH_DEBUG_REG27_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG27_TCHOLD_IP_q_MASK)
+
+#define MH_DEBUG_REG27(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, pa_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, tcd_nearfull_q, tchold_ip_q) \
+     ((eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) | \
+      (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) | \
+      (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) | \
+      (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) | \
+      (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT))
+
+#define MH_DEBUG_REG27_GET_EFF2_FP_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF2_LRU_WINNER_out(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF1_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WINNER_MASK) >> MH_DEBUG_REG27_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_MASK) >> MH_DEBUG_REG27_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_WINNER_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_q_MASK) >> MH_DEBUG_REG27_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF1_WIN(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WIN_MASK) >> MH_DEBUG_REG27_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG27_GET_KILL_EFF1(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_KILL_EFF1_MASK) >> MH_DEBUG_REG27_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_HOLD(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_HOLD_MASK) >> MH_DEBUG_REG27_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_RTR_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_RTR_q_MASK) >> MH_DEBUG_REG27_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG27_GET_CP_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_VGT_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_SEND_EFF1_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_RB_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_PA_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_QUAL_MASK) >> MH_DEBUG_REG27_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_CP_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_VGT_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_RB_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_TCD_NEARFULL_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG27_GET_TCHOLD_IP_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)
+
+#define MH_DEBUG_REG27_SET_EFF2_FP_WINNER(mh_debug_reg27_reg, eff2_fp_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF2_LRU_WINNER_out(mh_debug_reg27_reg, eff2_lru_winner_out) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF1_WINNER(mh_debug_reg27_reg, eff1_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_WINNER(mh_debug_reg27_reg, arb_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_WINNER_q(mh_debug_reg27_reg, arb_winner_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF1_WIN(mh_debug_reg27_reg, eff1_win) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG27_SET_KILL_EFF1(mh_debug_reg27_reg, kill_eff1) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_HOLD(mh_debug_reg27_reg, arb_hold) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_RTR_q(mh_debug_reg27_reg, arb_rtr_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG27_SET_CP_SEND_QUAL(mh_debug_reg27_reg, cp_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_VGT_SEND_QUAL(mh_debug_reg27_reg, vgt_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_SEND_QUAL(mh_debug_reg27_reg, tc_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_SEND_EFF1_QUAL(mh_debug_reg27_reg, tc_send_eff1_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_RB_SEND_QUAL(mh_debug_reg27_reg, rb_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_PA_SEND_QUAL(mh_debug_reg27_reg, pa_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_QUAL(mh_debug_reg27_reg, arb_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_CP_EFF1_REQ(mh_debug_reg27_reg, cp_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_VGT_EFF1_REQ(mh_debug_reg27_reg, vgt_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_EFF1_REQ(mh_debug_reg27_reg, tc_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_RB_EFF1_REQ(mh_debug_reg27_reg, rb_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_TCD_NEARFULL_q(mh_debug_reg27_reg, tcd_nearfull_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG27_SET_TCHOLD_IP_q(mh_debug_reg27_reg, tchold_ip_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG27_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG27_ARB_WINNER_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG27_ARB_WINNER_q_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG27_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG27_KILL_EFF1_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG27_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG27_ARB_RTR_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG27_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE;
+     } mh_debug_reg27_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG27_ARB_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG27_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG27_ARB_HOLD_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG27_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG27_EFF1_WIN_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG27_ARB_WINNER_q_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG27_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG27_EFF1_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE;
+     } mh_debug_reg27_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg27_t f;
+} mh_debug_reg27_u;
+
+
+/*
+ * MH_DEBUG_REG28 struct
+ */
+
+#define MH_DEBUG_REG28_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG28_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG28_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG28_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG28_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG28_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG28_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG28_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG28_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE 10
+
+#define MH_DEBUG_REG28_EFF1_WINNER_SHIFT 0
+#define MH_DEBUG_REG28_ARB_WINNER_SHIFT 3
+#define MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT 6
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT 7
+#define MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT 8
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT 9
+#define MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT 10
+#define MH_DEBUG_REG28_ARB_QUAL_SHIFT  11
+#define MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT 12
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT 13
+#define MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT 14
+#define MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT 15
+#define MH_DEBUG_REG28_EFF1_WIN_SHIFT  16
+#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 17
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT 18
+#define MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT 19
+#define MH_DEBUG_REG28_ARB_HOLD_SHIFT  20
+#define MH_DEBUG_REG28_ARB_RTR_q_SHIFT 21
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22
+
+#define MH_DEBUG_REG28_EFF1_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG28_ARB_WINNER_MASK 0x00000038
+#define MH_DEBUG_REG28_CP_SEND_QUAL_MASK 0x00000040
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_MASK 0x00000080
+#define MH_DEBUG_REG28_TC_SEND_QUAL_MASK 0x00000100
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK 0x00000200
+#define MH_DEBUG_REG28_RB_SEND_QUAL_MASK 0x00000400
+#define MH_DEBUG_REG28_ARB_QUAL_MASK   0x00000800
+#define MH_DEBUG_REG28_CP_EFF1_REQ_MASK 0x00001000
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_MASK 0x00002000
+#define MH_DEBUG_REG28_TC_EFF1_REQ_MASK 0x00004000
+#define MH_DEBUG_REG28_RB_EFF1_REQ_MASK 0x00008000
+#define MH_DEBUG_REG28_EFF1_WIN_MASK   0x00010000
+#define MH_DEBUG_REG28_KILL_EFF1_MASK  0x00020000
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_MASK 0x00040000
+#define MH_DEBUG_REG28_TC_ARB_HOLD_MASK 0x00080000
+#define MH_DEBUG_REG28_ARB_HOLD_MASK   0x00100000
+#define MH_DEBUG_REG28_ARB_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000
+
+#define MH_DEBUG_REG28_MASK \
+     (MH_DEBUG_REG28_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG28_ARB_WINNER_MASK | \
+      MH_DEBUG_REG28_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG28_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_ARB_QUAL_MASK | \
+      MH_DEBUG_REG28_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_EFF1_WIN_MASK | \
+      MH_DEBUG_REG28_KILL_EFF1_MASK | \
+      MH_DEBUG_REG28_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG28_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG28_ARB_HOLD_MASK | \
+      MH_DEBUG_REG28_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK)
+
+#define MH_DEBUG_REG28(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \
+     ((eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) | \
+      (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) | \
+      (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT))
+
+#define MH_DEBUG_REG28_GET_EFF1_WINNER(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WINNER_MASK) >> MH_DEBUG_REG28_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_WINNER(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_WINNER_MASK) >> MH_DEBUG_REG28_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG28_GET_CP_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_VGT_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_SEND_EFF1_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_RB_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_QUAL_MASK) >> MH_DEBUG_REG28_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_CP_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_VGT_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_RB_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_EFF1_WIN(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WIN_MASK) >> MH_DEBUG_REG28_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_GET_TCD_NEARFULL_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ARB_HOLD(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_HOLD(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_HOLD_MASK) >> MH_DEBUG_REG28_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_RTR_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_RTR_q_MASK) >> MH_DEBUG_REG28_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#define MH_DEBUG_REG28_SET_EFF1_WINNER(mh_debug_reg28_reg, eff1_winner) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_WINNER(mh_debug_reg28_reg, arb_winner) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG28_SET_CP_SEND_QUAL(mh_debug_reg28_reg, cp_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_VGT_SEND_QUAL(mh_debug_reg28_reg, vgt_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_SEND_QUAL(mh_debug_reg28_reg, tc_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_SEND_EFF1_QUAL(mh_debug_reg28_reg, tc_send_eff1_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_RB_SEND_QUAL(mh_debug_reg28_reg, rb_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_QUAL(mh_debug_reg28_reg, arb_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_CP_EFF1_REQ(mh_debug_reg28_reg, cp_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_VGT_EFF1_REQ(mh_debug_reg28_reg, vgt_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_EFF1_REQ(mh_debug_reg28_reg, tc_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_RB_EFF1_REQ(mh_debug_reg28_reg, rb_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_EFF1_WIN(mh_debug_reg28_reg, eff1_win) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_SET_TCD_NEARFULL_q(mh_debug_reg28_reg, tcd_nearfull_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ARB_HOLD(mh_debug_reg28_reg, tc_arb_hold) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_HOLD(mh_debug_reg28_reg, arb_hold) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_RTR_q(mh_debug_reg28_reg, arb_rtr_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28_reg, same_page_limit_count_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int eff1_winner                    : MH_DEBUG_REG28_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG28_ARB_WINNER_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG28_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG28_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG28_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG28_ARB_RTR_q_SIZE;
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+     } mh_debug_reg28_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG28_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG28_ARB_HOLD_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG28_EFF1_WIN_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG28_ARB_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG28_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG28_EFF1_WINNER_SIZE;
+     } mh_debug_reg28_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg28_t f;
+} mh_debug_reg28_u;
+
+
+/*
+ * MH_DEBUG_REG29 struct
+ */
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE 3
+#define MH_DEBUG_REG29_LEAST_RECENT_d_SIZE 3
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE 1
+#define MH_DEBUG_REG29_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG29_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG29_CLNT_REQ_SIZE   5
+#define MH_DEBUG_REG29_RECENT_d_0_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_1_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_2_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_3_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_4_SIZE 3
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT 0
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT 3
+#define MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT 6
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT 9
+#define MH_DEBUG_REG29_ARB_HOLD_SHIFT  10
+#define MH_DEBUG_REG29_ARB_RTR_q_SHIFT 11
+#define MH_DEBUG_REG29_CLNT_REQ_SHIFT  12
+#define MH_DEBUG_REG29_RECENT_d_0_SHIFT 17
+#define MH_DEBUG_REG29_RECENT_d_1_SHIFT 20
+#define MH_DEBUG_REG29_RECENT_d_2_SHIFT 23
+#define MH_DEBUG_REG29_RECENT_d_3_SHIFT 26
+#define MH_DEBUG_REG29_RECENT_d_4_SHIFT 29
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK 0x00000007
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK 0x00000038
+#define MH_DEBUG_REG29_LEAST_RECENT_d_MASK 0x000001c0
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK 0x00000200
+#define MH_DEBUG_REG29_ARB_HOLD_MASK   0x00000400
+#define MH_DEBUG_REG29_ARB_RTR_q_MASK  0x00000800
+#define MH_DEBUG_REG29_CLNT_REQ_MASK   0x0001f000
+#define MH_DEBUG_REG29_RECENT_d_0_MASK 0x000e0000
+#define MH_DEBUG_REG29_RECENT_d_1_MASK 0x00700000
+#define MH_DEBUG_REG29_RECENT_d_2_MASK 0x03800000
+#define MH_DEBUG_REG29_RECENT_d_3_MASK 0x1c000000
+#define MH_DEBUG_REG29_RECENT_d_4_MASK 0xe0000000
+
+#define MH_DEBUG_REG29_MASK \
+     (MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK | \
+      MH_DEBUG_REG29_LEAST_RECENT_d_MASK | \
+      MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK | \
+      MH_DEBUG_REG29_ARB_HOLD_MASK | \
+      MH_DEBUG_REG29_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG29_CLNT_REQ_MASK | \
+      MH_DEBUG_REG29_RECENT_d_0_MASK | \
+      MH_DEBUG_REG29_RECENT_d_1_MASK | \
+      MH_DEBUG_REG29_RECENT_d_2_MASK | \
+      MH_DEBUG_REG29_RECENT_d_3_MASK | \
+      MH_DEBUG_REG29_RECENT_d_4_MASK)
+
+#define MH_DEBUG_REG29(eff2_lru_winner_out, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3, recent_d_4) \
+     ((eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) | \
+      (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) | \
+      (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) | \
+      (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) | \
+      (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) | \
+      (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) | \
+      (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) | \
+      (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) | \
+      (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) | \
+      (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT))
+
+#define MH_DEBUG_REG29_GET_EFF2_LRU_WINNER_out(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG29_GET_LEAST_RECENT_INDEX_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG29_GET_LEAST_RECENT_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG29_GET_UPDATE_RECENT_STACK_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG29_GET_ARB_HOLD(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_HOLD_MASK) >> MH_DEBUG_REG29_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG29_GET_ARB_RTR_q(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_RTR_q_MASK) >> MH_DEBUG_REG29_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_GET_CLNT_REQ(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_CLNT_REQ_MASK) >> MH_DEBUG_REG29_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_0(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_0_MASK) >> MH_DEBUG_REG29_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_1(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_1_MASK) >> MH_DEBUG_REG29_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_2(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_2_MASK) >> MH_DEBUG_REG29_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_3(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_3_MASK) >> MH_DEBUG_REG29_RECENT_d_3_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_4(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_4_MASK) >> MH_DEBUG_REG29_RECENT_d_4_SHIFT)
+
+#define MH_DEBUG_REG29_SET_EFF2_LRU_WINNER_out(mh_debug_reg29_reg, eff2_lru_winner_out) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG29_SET_LEAST_RECENT_INDEX_d(mh_debug_reg29_reg, least_recent_index_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG29_SET_LEAST_RECENT_d(mh_debug_reg29_reg, least_recent_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG29_SET_UPDATE_RECENT_STACK_d(mh_debug_reg29_reg, update_recent_stack_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG29_SET_ARB_HOLD(mh_debug_reg29_reg, arb_hold) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG29_SET_ARB_RTR_q(mh_debug_reg29_reg, arb_rtr_q) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_SET_CLNT_REQ(mh_debug_reg29_reg, clnt_req) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_0(mh_debug_reg29_reg, recent_d_0) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_1(mh_debug_reg29_reg, recent_d_1) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_2(mh_debug_reg29_reg, recent_d_2) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_3(mh_debug_reg29_reg, recent_d_3) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_4(mh_debug_reg29_reg, recent_d_4) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_4_MASK) | (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG29_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG29_ARB_RTR_q_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG29_CLNT_REQ_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG29_RECENT_d_0_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG29_RECENT_d_1_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG29_RECENT_d_2_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG29_RECENT_d_3_SIZE;
+          unsigned int recent_d_4                     : MH_DEBUG_REG29_RECENT_d_4_SIZE;
+     } mh_debug_reg29_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int recent_d_4                     : MH_DEBUG_REG29_RECENT_d_4_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG29_RECENT_d_3_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG29_RECENT_d_2_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG29_RECENT_d_1_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG29_RECENT_d_0_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG29_CLNT_REQ_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG29_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG29_ARB_HOLD_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE;
+     } mh_debug_reg29_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg29_t f;
+} mh_debug_reg29_u;
+
+
+/*
+ * MH_DEBUG_REG30 struct
+ */
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG30_TCHOLD_IP_q_SIZE 1
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE 3
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG30_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE 7
+#define MH_DEBUG_REG30_WBURST_ACTIVE_SIZE 1
+#define MH_DEBUG_REG30_WLAST_q_SIZE    1
+#define MH_DEBUG_REG30_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG30_WBURST_CNT_q_SIZE 3
+#define MH_DEBUG_REG30_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG30_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_PA_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_ARB_WINNER_SIZE 3
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT 0
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT 1
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT 2
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT 3
+#define MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT 4
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT 5
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT 9
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT 10
+#define MH_DEBUG_REG30_TC_MH_written_SHIFT 11
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT 12
+#define MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT 19
+#define MH_DEBUG_REG30_WLAST_q_SHIFT   20
+#define MH_DEBUG_REG30_WBURST_IP_q_SHIFT 21
+#define MH_DEBUG_REG30_WBURST_CNT_q_SHIFT 22
+#define MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT 25
+#define MH_DEBUG_REG30_CP_MH_write_SHIFT 26
+#define MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT 27
+#define MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT 28
+#define MH_DEBUG_REG30_ARB_WINNER_SHIFT 29
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_MASK 0x00000001
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_MASK 0x00000008
+#define MH_DEBUG_REG30_TCHOLD_IP_q_MASK 0x00000010
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_MASK 0x000000e0
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK 0x00000200
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK 0x00000400
+#define MH_DEBUG_REG30_TC_MH_written_MASK 0x00000800
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK 0x0007f000
+#define MH_DEBUG_REG30_WBURST_ACTIVE_MASK 0x00080000
+#define MH_DEBUG_REG30_WLAST_q_MASK    0x00100000
+#define MH_DEBUG_REG30_WBURST_IP_q_MASK 0x00200000
+#define MH_DEBUG_REG30_WBURST_CNT_q_MASK 0x01c00000
+#define MH_DEBUG_REG30_CP_SEND_QUAL_MASK 0x02000000
+#define MH_DEBUG_REG30_CP_MH_write_MASK 0x04000000
+#define MH_DEBUG_REG30_RB_SEND_QUAL_MASK 0x08000000
+#define MH_DEBUG_REG30_PA_SEND_QUAL_MASK 0x10000000
+#define MH_DEBUG_REG30_ARB_WINNER_MASK 0xe0000000
+
+#define MH_DEBUG_REG30_MASK \
+     (MH_DEBUG_REG30_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG30_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG30_TCHOLD_IP_q_MASK | \
+      MH_DEBUG_REG30_TCHOLD_CNT_q_MASK | \
+      MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG30_TC_MH_written_MASK | \
+      MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK | \
+      MH_DEBUG_REG30_WBURST_ACTIVE_MASK | \
+      MH_DEBUG_REG30_WLAST_q_MASK | \
+      MH_DEBUG_REG30_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG30_WBURST_CNT_q_MASK | \
+      MH_DEBUG_REG30_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_CP_MH_write_MASK | \
+      MH_DEBUG_REG30_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_PA_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_ARB_WINNER_MASK)
+
+#define MH_DEBUG_REG30(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, pa_send_qual, arb_winner) \
+     ((tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) | \
+      (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \
+      (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) | \
+      (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) | \
+      (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) | \
+      (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) | \
+      (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) | \
+      (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) | \
+      (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT))
+
+#define MH_DEBUG_REG30_GET_TC_ARB_HOLD(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_GET_TCD_NEARFULL_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TCHOLD_IP_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TCHOLD_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_SEND_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_MH_written(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_MH_written_MASK) >> MH_DEBUG_REG30_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG30_GET_TCD_FULLNESS_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_ACTIVE(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG30_GET_WLAST_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WLAST_q_MASK) >> MH_DEBUG_REG30_WLAST_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_IP_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_IP_q_MASK) >> MH_DEBUG_REG30_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_CNT_q_MASK) >> MH_DEBUG_REG30_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_CP_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_CP_MH_write(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_CP_MH_write_MASK) >> MH_DEBUG_REG30_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG30_GET_RB_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_PA_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_ARB_WINNER(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_ARB_WINNER_MASK) >> MH_DEBUG_REG30_ARB_WINNER_SHIFT)
+
+#define MH_DEBUG_REG30_SET_TC_ARB_HOLD(mh_debug_reg30_reg, tc_arb_hold) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_noroq_same_row_bank) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_roq_same_row_bank) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_SET_TCD_NEARFULL_q(mh_debug_reg30_reg, tcd_nearfull_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TCHOLD_IP_q(mh_debug_reg30_reg, tchold_ip_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TCHOLD_CNT_q(mh_debug_reg30_reg, tchold_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30_reg, mh_arbiter_config_tc_reorder_enable) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg30_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_SEND_q(mh_debug_reg30_reg, tc_roq_send_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_MH_written(mh_debug_reg30_reg, tc_mh_written) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG30_SET_TCD_FULLNESS_CNT_q(mh_debug_reg30_reg, tcd_fullness_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_ACTIVE(mh_debug_reg30_reg, wburst_active) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG30_SET_WLAST_q(mh_debug_reg30_reg, wlast_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_IP_q(mh_debug_reg30_reg, wburst_ip_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_CNT_q(mh_debug_reg30_reg, wburst_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_CP_SEND_QUAL(mh_debug_reg30_reg, cp_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_CP_MH_write(mh_debug_reg30_reg, cp_mh_write) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG30_SET_RB_SEND_QUAL(mh_debug_reg30_reg, rb_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_PA_SEND_QUAL(mh_debug_reg30_reg, pa_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_ARB_WINNER(mh_debug_reg30_reg, arb_winner) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG30_TC_MH_written_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG30_WLAST_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG30_WBURST_IP_q_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG30_WBURST_CNT_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG30_CP_MH_write_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG30_ARB_WINNER_SIZE;
+     } mh_debug_reg30_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int arb_winner                     : MH_DEBUG_REG30_ARB_WINNER_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG30_CP_MH_write_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG30_WBURST_CNT_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG30_WBURST_IP_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG30_WLAST_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG30_TC_MH_written_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE;
+     } mh_debug_reg30_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg30_t f;
+} mh_debug_reg30_u;
+
+
+/*
+ * MH_DEBUG_REG31 struct
+ */
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE 26
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT 0
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK 0x03ffffff
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000
+
+#define MH_DEBUG_REG31_MASK \
+     (MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK | \
+      MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG31(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \
+     ((rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG31_GET_RF_ARBITER_CONFIG_q(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG31_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG31_SET_RF_ARBITER_CONFIG_q(mh_debug_reg31_reg, rf_arbiter_config_q) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG31_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg31_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int                                : 3;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE;
+     } mh_debug_reg31_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg31_t f;
+} mh_debug_reg31_u;
+
+
+/*
+ * MH_DEBUG_REG32 struct
+ */
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG32_ROQ_MARK_q_SIZE 8
+#define MH_DEBUG_REG32_ROQ_VALID_q_SIZE 8
+#define MH_DEBUG_REG32_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG32_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG32_ROQ_MARK_q_SHIFT 8
+#define MH_DEBUG_REG32_ROQ_VALID_q_SHIFT 16
+#define MH_DEBUG_REG32_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG32_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG32_ROQ_MARK_q_MASK 0x0000ff00
+#define MH_DEBUG_REG32_ROQ_VALID_q_MASK 0x00ff0000
+#define MH_DEBUG_REG32_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG32_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG32_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG32_MASK \
+     (MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG32_ROQ_MARK_q_MASK | \
+      MH_DEBUG_REG32_ROQ_VALID_q_MASK | \
+      MH_DEBUG_REG32_TC_MH_send_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG32_KILL_EFF1_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG32_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG32(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) | \
+      (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_MARK_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_VALID_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_GET_KILL_EFF1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_KILL_EFF1_MASK) >> MH_DEBUG_REG32_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG32_GET_ANY_SAME_ROW_BANK(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_EFF1_QUAL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_EMPTY(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_FULL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q(mh_debug_reg32_reg, same_row_bank_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_MARK_q(mh_debug_reg32_reg, roq_mark_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_VALID_q(mh_debug_reg32_reg, roq_valid_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_SET_KILL_EFF1(mh_debug_reg32_reg, kill_eff1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG32_SET_ANY_SAME_ROW_BANK(mh_debug_reg32_reg, any_same_row_bank) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_EFF1_QUAL(mh_debug_reg32_reg, tc_eff1_qual) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_EMPTY(mh_debug_reg32_reg, tc_roq_empty) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_FULL(mh_debug_reg32_reg, tc_roq_full) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG32_ROQ_MARK_q_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG32_ROQ_VALID_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG32_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg32_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG32_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG32_ROQ_VALID_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG32_ROQ_MARK_q_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg32_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg32_t f;
+} mh_debug_reg32_u;
+
+
+/*
+ * MH_DEBUG_REG33 struct
+ */
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG33_ROQ_MARK_d_SIZE 8
+#define MH_DEBUG_REG33_ROQ_VALID_d_SIZE 8
+#define MH_DEBUG_REG33_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG33_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG33_ROQ_MARK_d_SHIFT 8
+#define MH_DEBUG_REG33_ROQ_VALID_d_SHIFT 16
+#define MH_DEBUG_REG33_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG33_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG33_ROQ_MARK_d_MASK 0x0000ff00
+#define MH_DEBUG_REG33_ROQ_VALID_d_MASK 0x00ff0000
+#define MH_DEBUG_REG33_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG33_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG33_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG33_MASK \
+     (MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG33_ROQ_MARK_d_MASK | \
+      MH_DEBUG_REG33_ROQ_VALID_d_MASK | \
+      MH_DEBUG_REG33_TC_MH_send_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG33_KILL_EFF1_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG33_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG33(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) | \
+      (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_MARK_d(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_d_MASK) >> MH_DEBUG_REG33_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_VALID_d(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_d_MASK) >> MH_DEBUG_REG33_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_GET_KILL_EFF1(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_KILL_EFF1_MASK) >> MH_DEBUG_REG33_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG33_GET_ANY_SAME_ROW_BANK(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_EFF1_QUAL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_EMPTY(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_FULL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q(mh_debug_reg33_reg, same_row_bank_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_MARK_d(mh_debug_reg33_reg, roq_mark_d) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_VALID_d(mh_debug_reg33_reg, roq_valid_d) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_SET_KILL_EFF1(mh_debug_reg33_reg, kill_eff1) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG33_SET_ANY_SAME_ROW_BANK(mh_debug_reg33_reg, any_same_row_bank) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_EFF1_QUAL(mh_debug_reg33_reg, tc_eff1_qual) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_EMPTY(mh_debug_reg33_reg, tc_roq_empty) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_FULL(mh_debug_reg33_reg, tc_roq_full) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG33_ROQ_MARK_d_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG33_ROQ_VALID_d_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG33_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg33_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG33_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG33_ROQ_VALID_d_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG33_ROQ_MARK_d_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg33_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg33_t f;
+} mh_debug_reg33_u;
+
+
+/*
+ * MH_DEBUG_REG34 struct
+ */
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE 8
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT 0
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT 16
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT 24
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK 0x000000ff
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK 0x0000ff00
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK 0xff000000
+
+#define MH_DEBUG_REG34_MASK \
+     (MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK | \
+      MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK)
+
+#define MH_DEBUG_REG34(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \
+     ((same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) | \
+      (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) | \
+      (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) | \
+      (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT))
+
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_WIN(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_REQ(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, same_row_bank_win) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, same_row_bank_req) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, non_same_row_bank_win) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, non_same_row_bank_req) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int same_row_bank_win              : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE;
+     } mh_debug_reg34_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int same_row_bank_win              : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE;
+     } mh_debug_reg34_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg34_t f;
+} mh_debug_reg34_u;
+
+
+/*
+ * MH_DEBUG_REG35 struct
+ */
+
+#define MH_DEBUG_REG35_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE 1
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE 1
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE 1
+#define MH_DEBUG_REG35_ROQ_ADDR_0_SIZE 27
+
+#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT 2
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT 3
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT 4
+#define MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT 5
+
+#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_MASK 0x00000004
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_MASK 0x00000008
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK 0x00000010
+#define MH_DEBUG_REG35_ROQ_ADDR_0_MASK 0xffffffe0
+
+#define MH_DEBUG_REG35_MASK \
+     (MH_DEBUG_REG35_TC_MH_send_MASK | \
+      MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG35_ROQ_MARK_q_0_MASK | \
+      MH_DEBUG_REG35_ROQ_VALID_q_0_MASK | \
+      MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK | \
+      MH_DEBUG_REG35_ROQ_ADDR_0_MASK)
+
+#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \
+     ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) | \
+      (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) | \
+      (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) | \
+      (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT))
+
+#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_MARK_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_VALID_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_ADDR_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)
+
+#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_MARK_q_0(mh_debug_reg35_reg, roq_mark_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_VALID_q_0(mh_debug_reg35_reg, roq_valid_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_0(mh_debug_reg35_reg, same_row_bank_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_ADDR_0(mh_debug_reg35_reg, roq_addr_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_addr_0                     : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE;
+     } mh_debug_reg35_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int roq_addr_0                     : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+     } mh_debug_reg35_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg35_t f;
+} mh_debug_reg35_u;
+
+
+/*
+ * MH_DEBUG_REG36 struct
+ */
+
+#define MH_DEBUG_REG36_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE 1
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE 1
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE 1
+#define MH_DEBUG_REG36_ROQ_ADDR_1_SIZE 27
+
+#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT 2
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT 3
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT 4
+#define MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT 5
+
+#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_MASK 0x00000004
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_MASK 0x00000008
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK 0x00000010
+#define MH_DEBUG_REG36_ROQ_ADDR_1_MASK 0xffffffe0
+
+#define MH_DEBUG_REG36_MASK \
+     (MH_DEBUG_REG36_TC_MH_send_MASK | \
+      MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG36_ROQ_MARK_q_1_MASK | \
+      MH_DEBUG_REG36_ROQ_VALID_q_1_MASK | \
+      MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK | \
+      MH_DEBUG_REG36_ROQ_ADDR_1_MASK)
+
+#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \
+     ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) | \
+      (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) | \
+      (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) | \
+      (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT))
+
+#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_MARK_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_VALID_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_ADDR_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)
+
+#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_MARK_q_1(mh_debug_reg36_reg, roq_mark_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_VALID_q_1(mh_debug_reg36_reg, roq_valid_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_1(mh_debug_reg36_reg, same_row_bank_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_ADDR_1(mh_debug_reg36_reg, roq_addr_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_addr_1                     : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE;
+     } mh_debug_reg36_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int roq_addr_1                     : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+     } mh_debug_reg36_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg36_t f;
+} mh_debug_reg36_u;
+
+
+/*
+ * MH_DEBUG_REG37 struct
+ */
+
+#define MH_DEBUG_REG37_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE 1
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE 1
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE 1
+#define MH_DEBUG_REG37_ROQ_ADDR_2_SIZE 27
+
+#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT 2
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT 3
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT 4
+#define MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT 5
+
+#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_MASK 0x00000004
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_MASK 0x00000008
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK 0x00000010
+#define MH_DEBUG_REG37_ROQ_ADDR_2_MASK 0xffffffe0
+
+#define MH_DEBUG_REG37_MASK \
+     (MH_DEBUG_REG37_TC_MH_send_MASK | \
+      MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG37_ROQ_MARK_q_2_MASK | \
+      MH_DEBUG_REG37_ROQ_VALID_q_2_MASK | \
+      MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK | \
+      MH_DEBUG_REG37_ROQ_ADDR_2_MASK)
+
+#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \
+     ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) | \
+      (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) | \
+      (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) | \
+      (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT))
+
+#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_MARK_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_VALID_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_ADDR_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)
+
+#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_MARK_q_2(mh_debug_reg37_reg, roq_mark_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_VALID_q_2(mh_debug_reg37_reg, roq_valid_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_2(mh_debug_reg37_reg, same_row_bank_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_ADDR_2(mh_debug_reg37_reg, roq_addr_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_addr_2                     : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE;
+     } mh_debug_reg37_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int roq_addr_2                     : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+     } mh_debug_reg37_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg37_t f;
+} mh_debug_reg37_u;
+
+
+/*
+ * MH_DEBUG_REG38 struct
+ */
+
+#define MH_DEBUG_REG38_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE 1
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE 1
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE 1
+#define MH_DEBUG_REG38_ROQ_ADDR_3_SIZE 27
+
+#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT 2
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT 3
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT 4
+#define MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT 5
+
+#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_MASK 0x00000004
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_MASK 0x00000008
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK 0x00000010
+#define MH_DEBUG_REG38_ROQ_ADDR_3_MASK 0xffffffe0
+
+#define MH_DEBUG_REG38_MASK \
+     (MH_DEBUG_REG38_TC_MH_send_MASK | \
+      MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG38_ROQ_MARK_q_3_MASK | \
+      MH_DEBUG_REG38_ROQ_VALID_q_3_MASK | \
+      MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK | \
+      MH_DEBUG_REG38_ROQ_ADDR_3_MASK)
+
+#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \
+     ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) | \
+      (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) | \
+      (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) | \
+      (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT))
+
+#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_MARK_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_VALID_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_ADDR_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)
+
+#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_MARK_q_3(mh_debug_reg38_reg, roq_mark_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_VALID_q_3(mh_debug_reg38_reg, roq_valid_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_3(mh_debug_reg38_reg, same_row_bank_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_ADDR_3(mh_debug_reg38_reg, roq_addr_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_addr_3                     : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE;
+     } mh_debug_reg38_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int roq_addr_3                     : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+     } mh_debug_reg38_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg38_t f;
+} mh_debug_reg38_u;
+
+
+/*
+ * MH_DEBUG_REG39 struct
+ */
+
+#define MH_DEBUG_REG39_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE 1
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE 1
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE 1
+#define MH_DEBUG_REG39_ROQ_ADDR_4_SIZE 27
+
+#define MH_DEBUG_REG39_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT 2
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT 3
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT 4
+#define MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT 5
+
+#define MH_DEBUG_REG39_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_MASK 0x00000004
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_MASK 0x00000008
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK 0x00000010
+#define MH_DEBUG_REG39_ROQ_ADDR_4_MASK 0xffffffe0
+
+#define MH_DEBUG_REG39_MASK \
+     (MH_DEBUG_REG39_TC_MH_send_MASK | \
+      MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG39_ROQ_MARK_q_4_MASK | \
+      MH_DEBUG_REG39_ROQ_VALID_q_4_MASK | \
+      MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK | \
+      MH_DEBUG_REG39_ROQ_ADDR_4_MASK)
+
+#define MH_DEBUG_REG39(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \
+     ((tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) | \
+      (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) | \
+      (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) | \
+      (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT))
+
+#define MH_DEBUG_REG39_GET_TC_MH_send(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_TC_MH_send_MASK) >> MH_DEBUG_REG39_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG39_GET_TC_ROQ_RTR_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_MARK_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_VALID_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_SAME_ROW_BANK_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_ADDR_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)
+
+#define MH_DEBUG_REG39_SET_TC_MH_send(mh_debug_reg39_reg, tc_mh_send) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG39_SET_TC_ROQ_RTR_q(mh_debug_reg39_reg, tc_roq_rtr_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_MARK_q_4(mh_debug_reg39_reg, roq_mark_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_VALID_q_4(mh_debug_reg39_reg, roq_valid_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_SAME_ROW_BANK_q_4(mh_debug_reg39_reg, same_row_bank_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_ADDR_4(mh_debug_reg39_reg, roq_addr_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG39_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_addr_4                     : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE;
+     } mh_debug_reg39_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int roq_addr_4                     : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG39_TC_MH_send_SIZE;
+     } mh_debug_reg39_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg39_t f;
+} mh_debug_reg39_u;
+
+
+/*
+ * MH_DEBUG_REG40 struct
+ */
+
+#define MH_DEBUG_REG40_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE 1
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE 1
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE 1
+#define MH_DEBUG_REG40_ROQ_ADDR_5_SIZE 27
+
+#define MH_DEBUG_REG40_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT 2
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT 3
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT 4
+#define MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT 5
+
+#define MH_DEBUG_REG40_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_MASK 0x00000004
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_MASK 0x00000008
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK 0x00000010
+#define MH_DEBUG_REG40_ROQ_ADDR_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG40_MASK \
+     (MH_DEBUG_REG40_TC_MH_send_MASK | \
+      MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG40_ROQ_MARK_q_5_MASK | \
+      MH_DEBUG_REG40_ROQ_VALID_q_5_MASK | \
+      MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK | \
+      MH_DEBUG_REG40_ROQ_ADDR_5_MASK)
+
+#define MH_DEBUG_REG40(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \
+     ((tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) | \
+      (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) | \
+      (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) | \
+      (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT))
+
+#define MH_DEBUG_REG40_GET_TC_MH_send(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_TC_MH_send_MASK) >> MH_DEBUG_REG40_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG40_GET_TC_ROQ_RTR_q(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_MARK_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_VALID_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_SAME_ROW_BANK_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_ADDR_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)
+
+#define MH_DEBUG_REG40_SET_TC_MH_send(mh_debug_reg40_reg, tc_mh_send) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG40_SET_TC_ROQ_RTR_q(mh_debug_reg40_reg, tc_roq_rtr_q) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_MARK_q_5(mh_debug_reg40_reg, roq_mark_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_VALID_q_5(mh_debug_reg40_reg, roq_valid_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_SAME_ROW_BANK_q_5(mh_debug_reg40_reg, same_row_bank_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_ADDR_5(mh_debug_reg40_reg, roq_addr_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG40_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_addr_5                     : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE;
+     } mh_debug_reg40_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int roq_addr_5                     : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG40_TC_MH_send_SIZE;
+     } mh_debug_reg40_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg40_t f;
+} mh_debug_reg40_u;
+
+
+/*
+ * MH_DEBUG_REG41 struct
+ */
+
+#define MH_DEBUG_REG41_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE 1
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE 1
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE 1
+#define MH_DEBUG_REG41_ROQ_ADDR_6_SIZE 27
+
+#define MH_DEBUG_REG41_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT 2
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT 3
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT 4
+#define MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT 5
+
+#define MH_DEBUG_REG41_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_MASK 0x00000004
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_MASK 0x00000008
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK 0x00000010
+#define MH_DEBUG_REG41_ROQ_ADDR_6_MASK 0xffffffe0
+
+#define MH_DEBUG_REG41_MASK \
+     (MH_DEBUG_REG41_TC_MH_send_MASK | \
+      MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG41_ROQ_MARK_q_6_MASK | \
+      MH_DEBUG_REG41_ROQ_VALID_q_6_MASK | \
+      MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK | \
+      MH_DEBUG_REG41_ROQ_ADDR_6_MASK)
+
+#define MH_DEBUG_REG41(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \
+     ((tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) | \
+      (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) | \
+      (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) | \
+      (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT))
+
+#define MH_DEBUG_REG41_GET_TC_MH_send(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_TC_MH_send_MASK) >> MH_DEBUG_REG41_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG41_GET_TC_ROQ_RTR_q(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_MARK_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_VALID_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_SAME_ROW_BANK_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_ADDR_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)
+
+#define MH_DEBUG_REG41_SET_TC_MH_send(mh_debug_reg41_reg, tc_mh_send) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG41_SET_TC_ROQ_RTR_q(mh_debug_reg41_reg, tc_roq_rtr_q) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_MARK_q_6(mh_debug_reg41_reg, roq_mark_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_VALID_q_6(mh_debug_reg41_reg, roq_valid_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_SAME_ROW_BANK_q_6(mh_debug_reg41_reg, same_row_bank_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_ADDR_6(mh_debug_reg41_reg, roq_addr_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG41_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_addr_6                     : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE;
+     } mh_debug_reg41_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int roq_addr_6                     : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG41_TC_MH_send_SIZE;
+     } mh_debug_reg41_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg41_t f;
+} mh_debug_reg41_u;
+
+
+/*
+ * MH_DEBUG_REG42 struct
+ */
+
+#define MH_DEBUG_REG42_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE 1
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE 1
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE 1
+#define MH_DEBUG_REG42_ROQ_ADDR_7_SIZE 27
+
+#define MH_DEBUG_REG42_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT 2
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT 3
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT 4
+#define MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT 5
+
+#define MH_DEBUG_REG42_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_MASK 0x00000004
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_MASK 0x00000008
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK 0x00000010
+#define MH_DEBUG_REG42_ROQ_ADDR_7_MASK 0xffffffe0
+
+#define MH_DEBUG_REG42_MASK \
+     (MH_DEBUG_REG42_TC_MH_send_MASK | \
+      MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG42_ROQ_MARK_q_7_MASK | \
+      MH_DEBUG_REG42_ROQ_VALID_q_7_MASK | \
+      MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK | \
+      MH_DEBUG_REG42_ROQ_ADDR_7_MASK)
+
+#define MH_DEBUG_REG42(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \
+     ((tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) | \
+      (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) | \
+      (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) | \
+      (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT))
+
+#define MH_DEBUG_REG42_GET_TC_MH_send(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_TC_MH_send_MASK) >> MH_DEBUG_REG42_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG42_GET_TC_ROQ_RTR_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_MARK_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_VALID_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_SAME_ROW_BANK_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_ADDR_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)
+
+#define MH_DEBUG_REG42_SET_TC_MH_send(mh_debug_reg42_reg, tc_mh_send) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG42_SET_TC_ROQ_RTR_q(mh_debug_reg42_reg, tc_roq_rtr_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_MARK_q_7(mh_debug_reg42_reg, roq_mark_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_VALID_q_7(mh_debug_reg42_reg, roq_valid_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_SAME_ROW_BANK_q_7(mh_debug_reg42_reg, same_row_bank_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_ADDR_7(mh_debug_reg42_reg, roq_addr_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG42_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_addr_7                     : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE;
+     } mh_debug_reg42_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int roq_addr_7                     : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG42_TC_MH_send_SIZE;
+     } mh_debug_reg42_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg42_t f;
+} mh_debug_reg42_u;
+
+
+/*
+ * MH_DEBUG_REG43 struct
+ */
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_WE_SIZE     1
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG43_ARB_REG_RTR_SIZE 1
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE 1
+#define MH_DEBUG_REG43_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG43_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG43_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_BLEN_q_SIZE 1
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE 3
+#define MH_DEBUG_REG43_MMU_WE_SIZE     1
+#define MH_DEBUG_REG43_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG43_MMU_ID_SIZE     3
+#define MH_DEBUG_REG43_MMU_WRITE_SIZE  1
+#define MH_DEBUG_REG43_MMU_BLEN_SIZE   1
+#define MH_DEBUG_REG43_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG43_WDB_WE_SIZE     1
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE 1
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE 1
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT 0
+#define MH_DEBUG_REG43_ARB_WE_SHIFT    1
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT 2
+#define MH_DEBUG_REG43_ARB_RTR_q_SHIFT 3
+#define MH_DEBUG_REG43_ARB_REG_RTR_SHIFT 4
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT 5
+#define MH_DEBUG_REG43_MMU_RTR_SHIFT   6
+#define MH_DEBUG_REG43_ARB_ID_q_SHIFT  7
+#define MH_DEBUG_REG43_ARB_WRITE_q_SHIFT 10
+#define MH_DEBUG_REG43_ARB_BLEN_q_SHIFT 11
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT 12
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT 13
+#define MH_DEBUG_REG43_MMU_WE_SHIFT    16
+#define MH_DEBUG_REG43_ARQ_RTR_SHIFT   17
+#define MH_DEBUG_REG43_MMU_ID_SHIFT    18
+#define MH_DEBUG_REG43_MMU_WRITE_SHIFT 21
+#define MH_DEBUG_REG43_MMU_BLEN_SHIFT  22
+#define MH_DEBUG_REG43_WBURST_IP_q_SHIFT 23
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT 24
+#define MH_DEBUG_REG43_WDB_WE_SHIFT    25
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT 26
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT 27
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_MASK 0x00000001
+#define MH_DEBUG_REG43_ARB_WE_MASK     0x00000002
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_MASK 0x00000004
+#define MH_DEBUG_REG43_ARB_RTR_q_MASK  0x00000008
+#define MH_DEBUG_REG43_ARB_REG_RTR_MASK 0x00000010
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_MASK 0x00000020
+#define MH_DEBUG_REG43_MMU_RTR_MASK    0x00000040
+#define MH_DEBUG_REG43_ARB_ID_q_MASK   0x00000380
+#define MH_DEBUG_REG43_ARB_WRITE_q_MASK 0x00000400
+#define MH_DEBUG_REG43_ARB_BLEN_q_MASK 0x00000800
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK 0x00001000
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK 0x0000e000
+#define MH_DEBUG_REG43_MMU_WE_MASK     0x00010000
+#define MH_DEBUG_REG43_ARQ_RTR_MASK    0x00020000
+#define MH_DEBUG_REG43_MMU_ID_MASK     0x001c0000
+#define MH_DEBUG_REG43_MMU_WRITE_MASK  0x00200000
+#define MH_DEBUG_REG43_MMU_BLEN_MASK   0x00400000
+#define MH_DEBUG_REG43_WBURST_IP_q_MASK 0x00800000
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_MASK 0x01000000
+#define MH_DEBUG_REG43_WDB_WE_MASK     0x02000000
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK 0x04000000
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK 0x08000000
+
+#define MH_DEBUG_REG43_MASK \
+     (MH_DEBUG_REG43_ARB_REG_WE_q_MASK | \
+      MH_DEBUG_REG43_ARB_WE_MASK | \
+      MH_DEBUG_REG43_ARB_REG_VALID_q_MASK | \
+      MH_DEBUG_REG43_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG43_ARB_REG_RTR_MASK | \
+      MH_DEBUG_REG43_WDAT_BURST_RTR_MASK | \
+      MH_DEBUG_REG43_MMU_RTR_MASK | \
+      MH_DEBUG_REG43_ARB_ID_q_MASK | \
+      MH_DEBUG_REG43_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG43_ARB_BLEN_q_MASK | \
+      MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG43_MMU_WE_MASK | \
+      MH_DEBUG_REG43_ARQ_RTR_MASK | \
+      MH_DEBUG_REG43_MMU_ID_MASK | \
+      MH_DEBUG_REG43_MMU_WRITE_MASK | \
+      MH_DEBUG_REG43_MMU_BLEN_MASK | \
+      MH_DEBUG_REG43_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG43_WDAT_REG_WE_q_MASK | \
+      MH_DEBUG_REG43_WDB_WE_MASK | \
+      MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK | \
+      MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK)
+
+#define MH_DEBUG_REG43(arb_reg_we_q, arb_we, arb_reg_valid_q, arb_rtr_q, arb_reg_rtr, wdat_burst_rtr, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen, wburst_ip_q, wdat_reg_we_q, wdb_we, wdb_rtr_skid_4, wdb_rtr_skid_3) \
+     ((arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) | \
+      (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) | \
+      (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) | \
+      (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) | \
+      (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) | \
+      (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) | \
+      (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) | \
+      (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) | \
+      (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) | \
+      (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) | \
+      (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) | \
+      (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) | \
+      (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT))
+
+#define MH_DEBUG_REG43_GET_ARB_REG_WE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_WE_q_MASK) >> MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WE_MASK) >> MH_DEBUG_REG43_ARB_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_REG_VALID_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) >> MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_RTR_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_RTR_q_MASK) >> MH_DEBUG_REG43_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_REG_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_RTR_MASK) >> MH_DEBUG_REG43_ARB_REG_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_WDAT_BURST_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) >> MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_RTR_MASK) >> MH_DEBUG_REG43_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_ID_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_ID_q_MASK) >> MH_DEBUG_REG43_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_WRITE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WRITE_q_MASK) >> MH_DEBUG_REG43_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_BLEN_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_BLEN_q_MASK) >> MH_DEBUG_REG43_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_CTRL_EMPTY(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_FIFO_CNT_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WE_MASK) >> MH_DEBUG_REG43_MMU_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_RTR_MASK) >> MH_DEBUG_REG43_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_ID(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_ID_MASK) >> MH_DEBUG_REG43_MMU_ID_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_WRITE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WRITE_MASK) >> MH_DEBUG_REG43_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_BLEN(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_BLEN_MASK) >> MH_DEBUG_REG43_MMU_BLEN_SHIFT)
+#define MH_DEBUG_REG43_GET_WBURST_IP_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WBURST_IP_q_MASK) >> MH_DEBUG_REG43_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG43_GET_WDAT_REG_WE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_WE_MASK) >> MH_DEBUG_REG43_WDB_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_4(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_3(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)
+
+#define MH_DEBUG_REG43_SET_ARB_REG_WE_q(mh_debug_reg43_reg, arb_reg_we_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_WE_q_MASK) | (arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_WE(mh_debug_reg43_reg, arb_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_REG_VALID_q(mh_debug_reg43_reg, arb_reg_valid_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) | (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_RTR_q(mh_debug_reg43_reg, arb_rtr_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_REG_RTR(mh_debug_reg43_reg, arb_reg_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_RTR_MASK) | (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_WDAT_BURST_RTR(mh_debug_reg43_reg, wdat_burst_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) | (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_RTR(mh_debug_reg43_reg, mmu_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_ID_q(mh_debug_reg43_reg, arb_id_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_WRITE_q(mh_debug_reg43_reg, arb_write_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_BLEN_q(mh_debug_reg43_reg, arb_blen_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_CTRL_EMPTY(mh_debug_reg43_reg, arq_ctrl_empty) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_FIFO_CNT_q(mh_debug_reg43_reg, arq_fifo_cnt_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_WE(mh_debug_reg43_reg, mmu_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_RTR(mh_debug_reg43_reg, arq_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_ID(mh_debug_reg43_reg, mmu_id) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_WRITE(mh_debug_reg43_reg, mmu_write) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_BLEN(mh_debug_reg43_reg, mmu_blen) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT)
+#define MH_DEBUG_REG43_SET_WBURST_IP_q(mh_debug_reg43_reg, wburst_ip_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG43_SET_WDAT_REG_WE_q(mh_debug_reg43_reg, wdat_reg_we_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_WE(mh_debug_reg43_reg, wdb_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_4(mh_debug_reg43_reg, wdb_rtr_skid_4) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_3(mh_debug_reg43_reg, wdb_rtr_skid_3) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) | (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int arb_reg_we_q                   : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG43_ARB_WE_SIZE;
+          unsigned int arb_reg_valid_q                : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG43_ARB_RTR_q_SIZE;
+          unsigned int arb_reg_rtr                    : MH_DEBUG_REG43_ARB_REG_RTR_SIZE;
+          unsigned int wdat_burst_rtr                 : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG43_MMU_RTR_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG43_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG43_ARB_WRITE_q_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG43_ARB_BLEN_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG43_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG43_ARQ_RTR_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG43_MMU_ID_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG43_MMU_WRITE_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG43_MMU_BLEN_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG43_WBURST_IP_q_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG43_WDB_WE_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdb_rtr_skid_3                 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE;
+          unsigned int                                : 4;
+     } mh_debug_reg43_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int                                : 4;
+          unsigned int wdb_rtr_skid_3                 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG43_WDB_WE_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG43_WBURST_IP_q_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG43_MMU_BLEN_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG43_MMU_WRITE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG43_MMU_ID_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG43_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG43_MMU_WE_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG43_ARB_BLEN_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG43_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG43_ARB_ID_q_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG43_MMU_RTR_SIZE;
+          unsigned int wdat_burst_rtr                 : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE;
+          unsigned int arb_reg_rtr                    : MH_DEBUG_REG43_ARB_REG_RTR_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG43_ARB_RTR_q_SIZE;
+          unsigned int arb_reg_valid_q                : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG43_ARB_WE_SIZE;
+          unsigned int arb_reg_we_q                   : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE;
+     } mh_debug_reg43_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg43_t f;
+} mh_debug_reg43_u;
+
+
+/*
+ * MH_DEBUG_REG44 struct
+ */
+
+#define MH_DEBUG_REG44_ARB_WE_SIZE     1
+#define MH_DEBUG_REG44_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG44_ARB_VAD_q_SIZE  28
+
+#define MH_DEBUG_REG44_ARB_WE_SHIFT    0
+#define MH_DEBUG_REG44_ARB_ID_q_SHIFT  1
+#define MH_DEBUG_REG44_ARB_VAD_q_SHIFT 4
+
+#define MH_DEBUG_REG44_ARB_WE_MASK     0x00000001
+#define MH_DEBUG_REG44_ARB_ID_q_MASK   0x0000000e
+#define MH_DEBUG_REG44_ARB_VAD_q_MASK  0xfffffff0
+
+#define MH_DEBUG_REG44_MASK \
+     (MH_DEBUG_REG44_ARB_WE_MASK | \
+      MH_DEBUG_REG44_ARB_ID_q_MASK | \
+      MH_DEBUG_REG44_ARB_VAD_q_MASK)
+
+#define MH_DEBUG_REG44(arb_we, arb_id_q, arb_vad_q) \
+     ((arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) | \
+      (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT))
+
+#define MH_DEBUG_REG44_GET_ARB_WE(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WE_MASK) >> MH_DEBUG_REG44_ARB_WE_SHIFT)
+#define MH_DEBUG_REG44_GET_ARB_ID_q(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_ID_q_MASK) >> MH_DEBUG_REG44_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG44_GET_ARB_VAD_q(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_VAD_q_MASK) >> MH_DEBUG_REG44_ARB_VAD_q_SHIFT)
+
+#define MH_DEBUG_REG44_SET_ARB_WE(mh_debug_reg44_reg, arb_we) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT)
+#define MH_DEBUG_REG44_SET_ARB_ID_q(mh_debug_reg44_reg, arb_id_q) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG44_SET_ARB_VAD_q(mh_debug_reg44_reg, arb_vad_q) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_we                         : MH_DEBUG_REG44_ARB_WE_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG44_ARB_ID_q_SIZE;
+          unsigned int arb_vad_q                      : MH_DEBUG_REG44_ARB_VAD_q_SIZE;
+     } mh_debug_reg44_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_vad_q                      : MH_DEBUG_REG44_ARB_VAD_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG44_ARB_ID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG44_ARB_WE_SIZE;
+     } mh_debug_reg44_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg44_t f;
+} mh_debug_reg44_u;
+
+
+/*
+ * MH_DEBUG_REG45 struct
+ */
+
+#define MH_DEBUG_REG45_MMU_WE_SIZE     1
+#define MH_DEBUG_REG45_MMU_ID_SIZE     3
+#define MH_DEBUG_REG45_MMU_PAD_SIZE    28
+
+#define MH_DEBUG_REG45_MMU_WE_SHIFT    0
+#define MH_DEBUG_REG45_MMU_ID_SHIFT    1
+#define MH_DEBUG_REG45_MMU_PAD_SHIFT   4
+
+#define MH_DEBUG_REG45_MMU_WE_MASK     0x00000001
+#define MH_DEBUG_REG45_MMU_ID_MASK     0x0000000e
+#define MH_DEBUG_REG45_MMU_PAD_MASK    0xfffffff0
+
+#define MH_DEBUG_REG45_MASK \
+     (MH_DEBUG_REG45_MMU_WE_MASK | \
+      MH_DEBUG_REG45_MMU_ID_MASK | \
+      MH_DEBUG_REG45_MMU_PAD_MASK)
+
+#define MH_DEBUG_REG45(mmu_we, mmu_id, mmu_pad) \
+     ((mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) | \
+      (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT))
+
+#define MH_DEBUG_REG45_GET_MMU_WE(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_WE_MASK) >> MH_DEBUG_REG45_MMU_WE_SHIFT)
+#define MH_DEBUG_REG45_GET_MMU_ID(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_ID_MASK) >> MH_DEBUG_REG45_MMU_ID_SHIFT)
+#define MH_DEBUG_REG45_GET_MMU_PAD(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_PAD_MASK) >> MH_DEBUG_REG45_MMU_PAD_SHIFT)
+
+#define MH_DEBUG_REG45_SET_MMU_WE(mh_debug_reg45_reg, mmu_we) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT)
+#define MH_DEBUG_REG45_SET_MMU_ID(mh_debug_reg45_reg, mmu_id) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT)
+#define MH_DEBUG_REG45_SET_MMU_PAD(mh_debug_reg45_reg, mmu_pad) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int mmu_we                         : MH_DEBUG_REG45_MMU_WE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG45_MMU_ID_SIZE;
+          unsigned int mmu_pad                        : MH_DEBUG_REG45_MMU_PAD_SIZE;
+     } mh_debug_reg45_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int mmu_pad                        : MH_DEBUG_REG45_MMU_PAD_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG45_MMU_ID_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG45_MMU_WE_SIZE;
+     } mh_debug_reg45_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg45_t f;
+} mh_debug_reg45_u;
+
+
+/*
+ * MH_DEBUG_REG46 struct
+ */
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_WE_SIZE     1
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE 1
+#define MH_DEBUG_REG46_ARB_WSTRB_q_SIZE 8
+#define MH_DEBUG_REG46_ARB_WLAST_SIZE  1
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE 5
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_WDC_WID_SIZE 3
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE 1
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE 8
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT 0
+#define MH_DEBUG_REG46_WDB_WE_SHIFT    1
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT 2
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT 3
+#define MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT 4
+#define MH_DEBUG_REG46_ARB_WLAST_SHIFT 12
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT 13
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT 14
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT 19
+#define MH_DEBUG_REG46_WDB_WDC_WID_SHIFT 20
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT 23
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT 24
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_MASK 0x00000001
+#define MH_DEBUG_REG46_WDB_WE_MASK     0x00000002
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK 0x00000004
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK 0x00000008
+#define MH_DEBUG_REG46_ARB_WSTRB_q_MASK 0x00000ff0
+#define MH_DEBUG_REG46_ARB_WLAST_MASK  0x00001000
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK 0x00002000
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK 0x0007c000
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_MASK 0x00080000
+#define MH_DEBUG_REG46_WDB_WDC_WID_MASK 0x00700000
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_MASK 0x00800000
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK 0xff000000
+
+#define MH_DEBUG_REG46_MASK \
+     (MH_DEBUG_REG46_WDAT_REG_WE_q_MASK | \
+      MH_DEBUG_REG46_WDB_WE_MASK | \
+      MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK | \
+      MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK | \
+      MH_DEBUG_REG46_ARB_WSTRB_q_MASK | \
+      MH_DEBUG_REG46_ARB_WLAST_MASK | \
+      MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG46_WDC_WDB_RE_q_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WID_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WLAST_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK)
+
+#define MH_DEBUG_REG46(wdat_reg_we_q, wdb_we, wdat_reg_valid_q, wdb_rtr_skid_4, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \
+     ((wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) | \
+      (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) | \
+      (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) | \
+      (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) | \
+      (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) | \
+      (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) | \
+      (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) | \
+      (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) | \
+      (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) | \
+      (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) | \
+      (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) | \
+      (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT))
+
+#define MH_DEBUG_REG46_GET_WDAT_REG_WE_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WE(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WE_MASK) >> MH_DEBUG_REG46_WDB_WE_SHIFT)
+#define MH_DEBUG_REG46_GET_WDAT_REG_VALID_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_RTR_SKID_4(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG46_GET_ARB_WSTRB_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG46_GET_ARB_WLAST(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WLAST_MASK) >> MH_DEBUG_REG46_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_CTRL_EMPTY(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_FIFO_CNT_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDC_WDB_RE_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WID(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WID_MASK) >> MH_DEBUG_REG46_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WLAST(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WSTRB(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)
+
+#define MH_DEBUG_REG46_SET_WDAT_REG_WE_q(mh_debug_reg46_reg, wdat_reg_we_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WE(mh_debug_reg46_reg, wdb_we) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT)
+#define MH_DEBUG_REG46_SET_WDAT_REG_VALID_q(mh_debug_reg46_reg, wdat_reg_valid_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) | (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_RTR_SKID_4(mh_debug_reg46_reg, wdb_rtr_skid_4) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG46_SET_ARB_WSTRB_q(mh_debug_reg46_reg, arb_wstrb_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG46_SET_ARB_WLAST(mh_debug_reg46_reg, arb_wlast) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_CTRL_EMPTY(mh_debug_reg46_reg, wdb_ctrl_empty) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_FIFO_CNT_q(mh_debug_reg46_reg, wdb_fifo_cnt_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDC_WDB_RE_q(mh_debug_reg46_reg, wdc_wdb_re_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WID(mh_debug_reg46_reg, wdb_wdc_wid) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WLAST(mh_debug_reg46_reg, wdb_wdc_wlast) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WSTRB(mh_debug_reg46_reg, wdb_wdc_wstrb) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG46_WDB_WE_SIZE;
+          unsigned int wdat_reg_valid_q               : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG46_ARB_WLAST_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG46_WDB_WDC_WID_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE;
+     } mh_debug_reg46_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG46_WDB_WDC_WID_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG46_ARB_WLAST_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdat_reg_valid_q               : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG46_WDB_WE_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE;
+     } mh_debug_reg46_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg46_t f;
+} mh_debug_reg46_u;
+
+
+/*
+ * MH_DEBUG_REG47 struct
+ */
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE 32
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT 0
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG47_MASK \
+     (MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK)
+
+#define MH_DEBUG_REG47(wdb_wdc_wdata_31_0) \
+     ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT))
+
+#define MH_DEBUG_REG47_GET_WDB_WDC_WDATA_31_0(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)
+
+#define MH_DEBUG_REG47_SET_WDB_WDC_WDATA_31_0(mh_debug_reg47_reg, wdb_wdc_wdata_31_0) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg47_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg47_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg47_t f;
+} mh_debug_reg47_u;
+
+
+/*
+ * MH_DEBUG_REG48 struct
+ */
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE 32
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT 0
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG48_MASK \
+     (MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK)
+
+#define MH_DEBUG_REG48(wdb_wdc_wdata_63_32) \
+     ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT))
+
+#define MH_DEBUG_REG48_GET_WDB_WDC_WDATA_63_32(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)
+
+#define MH_DEBUG_REG48_SET_WDB_WDC_WDATA_63_32(mh_debug_reg48_reg, wdb_wdc_wdata_63_32) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg48_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg48_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg48_t f;
+} mh_debug_reg48_u;
+
+
+/*
+ * MH_DEBUG_REG49 struct
+ */
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE 1
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE 1
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE 6
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG49_RVALID_q_SIZE   1
+#define MH_DEBUG_REG49_RREADY_q_SIZE   1
+#define MH_DEBUG_REG49_RLAST_q_SIZE    1
+#define MH_DEBUG_REG49_BVALID_q_SIZE   1
+#define MH_DEBUG_REG49_BREADY_q_SIZE   1
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT 0
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT 1
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT 2
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT 3
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT 4
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT 5
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT 6
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT 7
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT 13
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT 14
+#define MH_DEBUG_REG49_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG49_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG49_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG49_BVALID_q_SHIFT  18
+#define MH_DEBUG_REG49_BREADY_q_SHIFT  19
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK 0x00000001
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK 0x00000002
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK 0x00000004
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK 0x00000008
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK 0x00000010
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK 0x00000020
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_MASK 0x00000040
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK 0x00001f80
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK 0x00004000
+#define MH_DEBUG_REG49_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG49_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG49_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG49_BVALID_q_MASK   0x00040000
+#define MH_DEBUG_REG49_BREADY_q_MASK   0x00080000
+
+#define MH_DEBUG_REG49_MASK \
+     (MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK | \
+      MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK | \
+      MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK | \
+      MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG49_INFLT_LIMIT_q_MASK | \
+      MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK | \
+      MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG49_RVALID_q_MASK | \
+      MH_DEBUG_REG49_RREADY_q_MASK | \
+      MH_DEBUG_REG49_RLAST_q_MASK | \
+      MH_DEBUG_REG49_BVALID_q_MASK | \
+      MH_DEBUG_REG49_BREADY_q_MASK)
+
+#define MH_DEBUG_REG49(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \
+     ((ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) | \
+      (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) | \
+      (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) | \
+      (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) | \
+      (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT))
+
+#define MH_DEBUG_REG49_GET_CTRL_ARC_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_CTRL_RARC_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_ARQ_CTRL_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_ARQ_CTRL_WRITE(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG49_GET_TLBMISS_CTRL_RTS(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG49_GET_CTRL_TLBMISS_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_INFLT_LIMIT_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG49_GET_INFLT_LIMIT_CNT_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG49_GET_ARC_CTRL_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RARC_CTRL_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RVALID_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RVALID_q_MASK) >> MH_DEBUG_REG49_RVALID_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RREADY_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RREADY_q_MASK) >> MH_DEBUG_REG49_RREADY_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RLAST_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RLAST_q_MASK) >> MH_DEBUG_REG49_RLAST_q_SHIFT)
+#define MH_DEBUG_REG49_GET_BVALID_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_BVALID_q_MASK) >> MH_DEBUG_REG49_BVALID_q_SHIFT)
+#define MH_DEBUG_REG49_GET_BREADY_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_BREADY_q_MASK) >> MH_DEBUG_REG49_BREADY_q_SHIFT)
+
+#define MH_DEBUG_REG49_SET_CTRL_ARC_EMPTY(mh_debug_reg49_reg, ctrl_arc_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_CTRL_RARC_EMPTY(mh_debug_reg49_reg, ctrl_rarc_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_ARQ_CTRL_EMPTY(mh_debug_reg49_reg, arq_ctrl_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_ARQ_CTRL_WRITE(mh_debug_reg49_reg, arq_ctrl_write) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG49_SET_TLBMISS_CTRL_RTS(mh_debug_reg49_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG49_SET_CTRL_TLBMISS_RE_q(mh_debug_reg49_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_INFLT_LIMIT_q(mh_debug_reg49_reg, inflt_limit_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG49_SET_INFLT_LIMIT_CNT_q(mh_debug_reg49_reg, inflt_limit_cnt_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG49_SET_ARC_CTRL_RE_q(mh_debug_reg49_reg, arc_ctrl_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RARC_CTRL_RE_q(mh_debug_reg49_reg, rarc_ctrl_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RVALID_q(mh_debug_reg49_reg, rvalid_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RREADY_q(mh_debug_reg49_reg, rready_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RLAST_q(mh_debug_reg49_reg, rlast_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT)
+#define MH_DEBUG_REG49_SET_BVALID_q(mh_debug_reg49_reg, bvalid_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT)
+#define MH_DEBUG_REG49_SET_BREADY_q(mh_debug_reg49_reg, bready_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG49_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG49_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG49_RLAST_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG49_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG49_BREADY_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg49_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int                                : 12;
+          unsigned int bready_q                       : MH_DEBUG_REG49_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG49_BVALID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG49_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG49_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG49_RVALID_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE;
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE;
+     } mh_debug_reg49_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg49_t f;
+} mh_debug_reg49_u;
+
+
+/*
+ * MH_DEBUG_REG50 struct
+ */
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG50_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG50_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG50_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG50_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG50_RDC_RID_SIZE    3
+#define MH_DEBUG_REG50_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG50_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE 1
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE 6
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE 1
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE 6
+#define MH_DEBUG_REG50_CNT_HOLD_q1_SIZE 1
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG50_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT 3
+#define MH_DEBUG_REG50_TLBMISS_VALID_SHIFT 4
+#define MH_DEBUG_REG50_RDC_VALID_SHIFT 5
+#define MH_DEBUG_REG50_RDC_RID_SHIFT   6
+#define MH_DEBUG_REG50_RDC_RLAST_SHIFT 9
+#define MH_DEBUG_REG50_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT 12
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT 13
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT 14
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT 15
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT 21
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT 22
+#define MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT 28
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG50_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG50_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK 0x00000008
+#define MH_DEBUG_REG50_TLBMISS_VALID_MASK 0x00000010
+#define MH_DEBUG_REG50_RDC_VALID_MASK  0x00000020
+#define MH_DEBUG_REG50_RDC_RID_MASK    0x000001c0
+#define MH_DEBUG_REG50_RDC_RLAST_MASK  0x00000200
+#define MH_DEBUG_REG50_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK 0x00001000
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK 0x00004000
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK 0x00200000
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000
+#define MH_DEBUG_REG50_CNT_HOLD_q1_MASK 0x10000000
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000
+
+#define MH_DEBUG_REG50_MASK \
+     (MH_DEBUG_REG50_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG50_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG50_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG50_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG50_RDC_VALID_MASK | \
+      MH_DEBUG_REG50_RDC_RID_MASK | \
+      MH_DEBUG_REG50_RDC_RLAST_MASK | \
+      MH_DEBUG_REG50_RDC_RRESP_MASK | \
+      MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK | \
+      MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK | \
+      MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK | \
+      MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK | \
+      MH_DEBUG_REG50_CNT_HOLD_q1_MASK | \
+      MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG50(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \
+     ((mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) | \
+      (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) | \
+      (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) | \
+      (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) | \
+      (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG50_GET_MH_CP_grb_send(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CP_grb_send_MASK) >> MH_DEBUG_REG50_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_VGT_grb_send(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_TC_mcsend(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TC_mcsend_MASK) >> MH_DEBUG_REG50_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_TLBMISS_SEND(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_VALID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_VALID_MASK) >> MH_DEBUG_REG50_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_VALID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_VALID_MASK) >> MH_DEBUG_REG50_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RID_MASK) >> MH_DEBUG_REG50_RDC_RID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RLAST(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RLAST_MASK) >> MH_DEBUG_REG50_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RRESP(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RRESP_MASK) >> MH_DEBUG_REG50_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_CTRL_RTS(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG50_GET_CTRL_TLBMISS_RE_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_ID_REQUEST_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG50_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_ID_RESPONSE(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_GET_CNT_HOLD_q1(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG50_SET_MH_CP_grb_send(mh_debug_reg50_reg, mh_cp_grb_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_VGT_grb_send(mh_debug_reg50_reg, mh_vgt_grb_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_TC_mcsend(mh_debug_reg50_reg, mh_tc_mcsend) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_TLBMISS_SEND(mh_debug_reg50_reg, mh_tlbmiss_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_VALID(mh_debug_reg50_reg, tlbmiss_valid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_VALID(mh_debug_reg50_reg, rdc_valid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RID(mh_debug_reg50_reg, rdc_rid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RLAST(mh_debug_reg50_reg, rdc_rlast) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RRESP(mh_debug_reg50_reg, rdc_rresp) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_CTRL_RTS(mh_debug_reg50_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG50_SET_CTRL_TLBMISS_RE_q(mh_debug_reg50_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_ID_REQUEST_q(mh_debug_reg50_reg, mmu_id_request_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG50_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50_reg, outstanding_mmuid_cnt_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_ID_RESPONSE(mh_debug_reg50_reg, mmu_id_response) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg50_reg, tlbmiss_return_cnt_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_SET_CNT_HOLD_q1(mh_debug_reg50_reg, cnt_hold_q1) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG50_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG50_MH_TC_mcsend_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG50_TLBMISS_VALID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG50_RDC_VALID_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG50_RDC_RID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG50_RDC_RLAST_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG50_RDC_RRESP_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+     } mh_debug_reg50_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG50_RDC_RRESP_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG50_RDC_RLAST_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG50_RDC_RID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG50_RDC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG50_TLBMISS_VALID_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG50_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG50_MH_CP_grb_send_SIZE;
+     } mh_debug_reg50_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg50_t f;
+} mh_debug_reg50_u;
+
+
+/*
+ * MH_DEBUG_REG51 struct
+ */
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE 32
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT 0
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG51_MASK \
+     (MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK)
+
+#define MH_DEBUG_REG51(rf_mmu_page_fault) \
+     ((rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_DEBUG_REG51_GET_RF_MMU_PAGE_FAULT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_DEBUG_REG51_SET_RF_MMU_PAGE_FAULT(mh_debug_reg51_reg, rf_mmu_page_fault) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg51_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg51_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg51_t f;
+} mh_debug_reg51_u;
+
+
+/*
+ * MH_DEBUG_REG52 struct
+ */
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE 2
+#define MH_DEBUG_REG52_ARB_WE_SIZE     1
+#define MH_DEBUG_REG52_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE 22
+#define MH_DEBUG_REG52_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG52_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG52_client_behavior_q_SIZE 2
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT 0
+#define MH_DEBUG_REG52_ARB_WE_SHIFT    2
+#define MH_DEBUG_REG52_MMU_RTR_SHIFT   3
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT 4
+#define MH_DEBUG_REG52_ARB_ID_q_SHIFT  26
+#define MH_DEBUG_REG52_ARB_WRITE_q_SHIFT 29
+#define MH_DEBUG_REG52_client_behavior_q_SHIFT 30
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003
+#define MH_DEBUG_REG52_ARB_WE_MASK     0x00000004
+#define MH_DEBUG_REG52_MMU_RTR_MASK    0x00000008
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0
+#define MH_DEBUG_REG52_ARB_ID_q_MASK   0x1c000000
+#define MH_DEBUG_REG52_ARB_WRITE_q_MASK 0x20000000
+#define MH_DEBUG_REG52_client_behavior_q_MASK 0xc0000000
+
+#define MH_DEBUG_REG52_MASK \
+     (MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK | \
+      MH_DEBUG_REG52_ARB_WE_MASK | \
+      MH_DEBUG_REG52_MMU_RTR_MASK | \
+      MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK | \
+      MH_DEBUG_REG52_ARB_ID_q_MASK | \
+      MH_DEBUG_REG52_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG52_client_behavior_q_MASK)
+
+#define MH_DEBUG_REG52(rf_mmu_config_q_1_to_0, arb_we, mmu_rtr, rf_mmu_config_q_25_to_4, arb_id_q, arb_write_q, client_behavior_q) \
+     ((rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) | \
+      (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) | \
+      (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT))
+
+#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_WE(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WE_MASK) >> MH_DEBUG_REG52_ARB_WE_SHIFT)
+#define MH_DEBUG_REG52_GET_MMU_RTR(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_RTR_MASK) >> MH_DEBUG_REG52_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_ID_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_ID_q_MASK) >> MH_DEBUG_REG52_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_WRITE_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WRITE_q_MASK) >> MH_DEBUG_REG52_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT)
+
+#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52_reg, rf_mmu_config_q_1_to_0) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) | (rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_WE(mh_debug_reg52_reg, arb_we) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT)
+#define MH_DEBUG_REG52_SET_MMU_RTR(mh_debug_reg52_reg, mmu_rtr) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52_reg, rf_mmu_config_q_25_to_4) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) | (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_ID_q(mh_debug_reg52_reg, arb_id_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_WRITE_q(mh_debug_reg52_reg, arb_write_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int rf_mmu_config_q_1_to_0         : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG52_ARB_WE_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG52_MMU_RTR_SIZE;
+          unsigned int rf_mmu_config_q_25_to_4        : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG52_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG52_ARB_WRITE_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+     } mh_debug_reg52_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG52_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG52_ARB_ID_q_SIZE;
+          unsigned int rf_mmu_config_q_25_to_4        : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG52_MMU_RTR_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG52_ARB_WE_SIZE;
+          unsigned int rf_mmu_config_q_1_to_0         : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE;
+     } mh_debug_reg52_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg52_t f;
+} mh_debug_reg52_u;
+
+
+/*
+ * MH_DEBUG_REG53 struct
+ */
+
+#define MH_DEBUG_REG53_stage1_valid_SIZE 1
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG53_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG53_tag_match_q_SIZE 1
+#define MH_DEBUG_REG53_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG53_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG53_MMU_MISS_SIZE   1
+#define MH_DEBUG_REG53_MMU_READ_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_HIT_SIZE    1
+#define MH_DEBUG_REG53_MMU_READ_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE 16
+
+#define MH_DEBUG_REG53_stage1_valid_SHIFT 0
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT 1
+#define MH_DEBUG_REG53_pa_in_mpu_range_SHIFT 2
+#define MH_DEBUG_REG53_tag_match_q_SHIFT 3
+#define MH_DEBUG_REG53_tag_miss_q_SHIFT 4
+#define MH_DEBUG_REG53_va_in_range_q_SHIFT 5
+#define MH_DEBUG_REG53_MMU_MISS_SHIFT  6
+#define MH_DEBUG_REG53_MMU_READ_MISS_SHIFT 7
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT 8
+#define MH_DEBUG_REG53_MMU_HIT_SHIFT   9
+#define MH_DEBUG_REG53_MMU_READ_HIT_SHIFT 10
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT 11
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT 12
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT 13
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT 16
+
+#define MH_DEBUG_REG53_stage1_valid_MASK 0x00000001
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK 0x00000002
+#define MH_DEBUG_REG53_pa_in_mpu_range_MASK 0x00000004
+#define MH_DEBUG_REG53_tag_match_q_MASK 0x00000008
+#define MH_DEBUG_REG53_tag_miss_q_MASK 0x00000010
+#define MH_DEBUG_REG53_va_in_range_q_MASK 0x00000020
+#define MH_DEBUG_REG53_MMU_MISS_MASK   0x00000040
+#define MH_DEBUG_REG53_MMU_READ_MISS_MASK 0x00000080
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_MASK 0x00000100
+#define MH_DEBUG_REG53_MMU_HIT_MASK    0x00000200
+#define MH_DEBUG_REG53_MMU_READ_HIT_MASK 0x00000400
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_MASK 0x00000800
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG53_MASK \
+     (MH_DEBUG_REG53_stage1_valid_MASK | \
+      MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG53_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG53_tag_match_q_MASK | \
+      MH_DEBUG_REG53_tag_miss_q_MASK | \
+      MH_DEBUG_REG53_va_in_range_q_MASK | \
+      MH_DEBUG_REG53_MMU_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_READ_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_WRITE_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_READ_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_WRITE_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK | \
+      MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK)
+
+#define MH_DEBUG_REG53(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \
+     ((stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) | \
+      (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) | \
+      (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) | \
+      (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) | \
+      (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) | \
+      (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) | \
+      (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) | \
+      (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \
+      (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \
+      (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \
+      (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \
+      (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT))
+
+#define MH_DEBUG_REG53_GET_stage1_valid(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_stage1_valid_MASK) >> MH_DEBUG_REG53_stage1_valid_SHIFT)
+#define MH_DEBUG_REG53_GET_IGNORE_TAG_MISS_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG53_GET_pa_in_mpu_range(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_pa_in_mpu_range_MASK) >> MH_DEBUG_REG53_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG53_GET_tag_match_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_tag_match_q_MASK) >> MH_DEBUG_REG53_tag_match_q_SHIFT)
+#define MH_DEBUG_REG53_GET_tag_miss_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_tag_miss_q_MASK) >> MH_DEBUG_REG53_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG53_GET_va_in_range_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_va_in_range_q_MASK) >> MH_DEBUG_REG53_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_MISS_MASK) >> MH_DEBUG_REG53_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_READ_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_MISS_MASK) >> MH_DEBUG_REG53_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_WRITE_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_HIT_MASK) >> MH_DEBUG_REG53_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_READ_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_HIT_MASK) >> MH_DEBUG_REG53_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_WRITE_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_REQ_VA_OFFSET_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)
+
+#define MH_DEBUG_REG53_SET_stage1_valid(mh_debug_reg53_reg, stage1_valid) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT)
+#define MH_DEBUG_REG53_SET_IGNORE_TAG_MISS_q(mh_debug_reg53_reg, ignore_tag_miss_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG53_SET_pa_in_mpu_range(mh_debug_reg53_reg, pa_in_mpu_range) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG53_SET_tag_match_q(mh_debug_reg53_reg, tag_match_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT)
+#define MH_DEBUG_REG53_SET_tag_miss_q(mh_debug_reg53_reg, tag_miss_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG53_SET_va_in_range_q(mh_debug_reg53_reg, va_in_range_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_MISS(mh_debug_reg53_reg, mmu_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_READ_MISS(mh_debug_reg53_reg, mmu_read_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_WRITE_MISS(mh_debug_reg53_reg, mmu_write_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_HIT(mh_debug_reg53_reg, mmu_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_READ_HIT(mh_debug_reg53_reg, mmu_read_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_WRITE_HIT(mh_debug_reg53_reg, mmu_write_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53_reg, mmu_split_mode_tc_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53_reg, mmu_split_mode_tc_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53_reg, mmu_split_mode_nontc_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53_reg, mmu_split_mode_nontc_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_REQ_VA_OFFSET_q(mh_debug_reg53_reg, req_va_offset_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int stage1_valid                   : MH_DEBUG_REG53_stage1_valid_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG53_pa_in_mpu_range_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG53_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG53_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG53_va_in_range_q_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG53_MMU_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG53_MMU_READ_MISS_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG53_MMU_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG53_MMU_READ_HIT_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int req_va_offset_q                : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE;
+     } mh_debug_reg53_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int req_va_offset_q                : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG53_MMU_READ_HIT_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG53_MMU_HIT_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG53_MMU_READ_MISS_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG53_MMU_MISS_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG53_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG53_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG53_tag_match_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG53_pa_in_mpu_range_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG53_stage1_valid_SIZE;
+     } mh_debug_reg53_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg53_t f;
+} mh_debug_reg53_u;
+
+
+/*
+ * MH_DEBUG_REG54 struct
+ */
+
+#define MH_DEBUG_REG54_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG54_MMU_WE_SIZE     1
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1
+#define MH_DEBUG_REG54_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG54_stage1_valid_SIZE 1
+#define MH_DEBUG_REG54_stage2_valid_SIZE 1
+#define MH_DEBUG_REG54_client_behavior_q_SIZE 2
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG54_tag_match_q_SIZE 1
+#define MH_DEBUG_REG54_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG54_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE 1
+#define MH_DEBUG_REG54_TAG_valid_q_SIZE 16
+
+#define MH_DEBUG_REG54_ARQ_RTR_SHIFT   0
+#define MH_DEBUG_REG54_MMU_WE_SHIFT    1
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT 2
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT 3
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT 4
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5
+#define MH_DEBUG_REG54_pa_in_mpu_range_SHIFT 6
+#define MH_DEBUG_REG54_stage1_valid_SHIFT 7
+#define MH_DEBUG_REG54_stage2_valid_SHIFT 8
+#define MH_DEBUG_REG54_client_behavior_q_SHIFT 9
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT 11
+#define MH_DEBUG_REG54_tag_match_q_SHIFT 12
+#define MH_DEBUG_REG54_tag_miss_q_SHIFT 13
+#define MH_DEBUG_REG54_va_in_range_q_SHIFT 14
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT 15
+#define MH_DEBUG_REG54_TAG_valid_q_SHIFT 16
+
+#define MH_DEBUG_REG54_ARQ_RTR_MASK    0x00000001
+#define MH_DEBUG_REG54_MMU_WE_MASK     0x00000002
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK 0x00000004
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK 0x00000008
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK 0x00000010
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020
+#define MH_DEBUG_REG54_pa_in_mpu_range_MASK 0x00000040
+#define MH_DEBUG_REG54_stage1_valid_MASK 0x00000080
+#define MH_DEBUG_REG54_stage2_valid_MASK 0x00000100
+#define MH_DEBUG_REG54_client_behavior_q_MASK 0x00000600
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK 0x00000800
+#define MH_DEBUG_REG54_tag_match_q_MASK 0x00001000
+#define MH_DEBUG_REG54_tag_miss_q_MASK 0x00002000
+#define MH_DEBUG_REG54_va_in_range_q_MASK 0x00004000
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK 0x00008000
+#define MH_DEBUG_REG54_TAG_valid_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG54_MASK \
+     (MH_DEBUG_REG54_ARQ_RTR_MASK | \
+      MH_DEBUG_REG54_MMU_WE_MASK | \
+      MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \
+      MH_DEBUG_REG54_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG54_stage1_valid_MASK | \
+      MH_DEBUG_REG54_stage2_valid_MASK | \
+      MH_DEBUG_REG54_client_behavior_q_MASK | \
+      MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG54_tag_match_q_MASK | \
+      MH_DEBUG_REG54_tag_miss_q_MASK | \
+      MH_DEBUG_REG54_va_in_range_q_MASK | \
+      MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK | \
+      MH_DEBUG_REG54_TAG_valid_q_MASK)
+
+#define MH_DEBUG_REG54(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \
+     ((arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) | \
+      (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) | \
+      (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) | \
+      (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) | \
+      (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) | \
+      (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT))
+
+#define MH_DEBUG_REG54_GET_ARQ_RTR(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_ARQ_RTR_MASK) >> MH_DEBUG_REG54_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG54_GET_MMU_WE(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_WE_MASK) >> MH_DEBUG_REG54_MMU_WE_SHIFT)
+#define MH_DEBUG_REG54_GET_CTRL_TLBMISS_RE_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG54_GET_TLBMISS_CTRL_RTS(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG54_GET_MH_TLBMISS_SEND(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG54_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG54_GET_pa_in_mpu_range(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_pa_in_mpu_range_MASK) >> MH_DEBUG_REG54_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG54_GET_stage1_valid(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_stage1_valid_MASK) >> MH_DEBUG_REG54_stage1_valid_SHIFT)
+#define MH_DEBUG_REG54_GET_stage2_valid(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_stage2_valid_MASK) >> MH_DEBUG_REG54_stage2_valid_SHIFT)
+#define MH_DEBUG_REG54_GET_client_behavior_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_client_behavior_q_MASK) >> MH_DEBUG_REG54_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG54_GET_IGNORE_TAG_MISS_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG54_GET_tag_match_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_tag_match_q_MASK) >> MH_DEBUG_REG54_tag_match_q_SHIFT)
+#define MH_DEBUG_REG54_GET_tag_miss_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_tag_miss_q_MASK) >> MH_DEBUG_REG54_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG54_GET_va_in_range_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_va_in_range_q_MASK) >> MH_DEBUG_REG54_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG54_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG_valid_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_MASK) >> MH_DEBUG_REG54_TAG_valid_q_SHIFT)
+
+#define MH_DEBUG_REG54_SET_ARQ_RTR(mh_debug_reg54_reg, arq_rtr) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG54_SET_MMU_WE(mh_debug_reg54_reg, mmu_we) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT)
+#define MH_DEBUG_REG54_SET_CTRL_TLBMISS_RE_q(mh_debug_reg54_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG54_SET_TLBMISS_CTRL_RTS(mh_debug_reg54_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG54_SET_MH_TLBMISS_SEND(mh_debug_reg54_reg, mh_tlbmiss_send) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG54_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54_reg, mmu_stall_awaiting_tlb_miss_fetch) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG54_SET_pa_in_mpu_range(mh_debug_reg54_reg, pa_in_mpu_range) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG54_SET_stage1_valid(mh_debug_reg54_reg, stage1_valid) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT)
+#define MH_DEBUG_REG54_SET_stage2_valid(mh_debug_reg54_reg, stage2_valid) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT)
+#define MH_DEBUG_REG54_SET_client_behavior_q(mh_debug_reg54_reg, client_behavior_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG54_SET_IGNORE_TAG_MISS_q(mh_debug_reg54_reg, ignore_tag_miss_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG54_SET_tag_match_q(mh_debug_reg54_reg, tag_match_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT)
+#define MH_DEBUG_REG54_SET_tag_miss_q(mh_debug_reg54_reg, tag_miss_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG54_SET_va_in_range_q(mh_debug_reg54_reg, va_in_range_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG54_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg54_reg, pte_fetch_complete_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG_valid_q(mh_debug_reg54_reg, tag_valid_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int arq_rtr                        : MH_DEBUG_REG54_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG54_MMU_WE_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG54_pa_in_mpu_range_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG54_stage1_valid_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG54_stage2_valid_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG54_client_behavior_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG54_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG54_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG54_va_in_range_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int tag_valid_q                    : MH_DEBUG_REG54_TAG_valid_q_SIZE;
+     } mh_debug_reg54_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int tag_valid_q                    : MH_DEBUG_REG54_TAG_valid_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG54_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG54_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG54_tag_match_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG54_client_behavior_q_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG54_stage2_valid_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG54_stage1_valid_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG54_pa_in_mpu_range_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG54_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG54_ARQ_RTR_SIZE;
+     } mh_debug_reg54_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg54_t f;
+} mh_debug_reg54_u;
+
+
+/*
+ * MH_DEBUG_REG55 struct
+ */
+
+#define MH_DEBUG_REG55_TAG0_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_0_SIZE 1
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG55_TAG1_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_1_SIZE 1
+
+#define MH_DEBUG_REG55_TAG0_VA_SHIFT   0
+#define MH_DEBUG_REG55_TAG_valid_q_0_SHIFT 13
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG55_TAG1_VA_SHIFT   16
+#define MH_DEBUG_REG55_TAG_valid_q_1_SHIFT 29
+
+#define MH_DEBUG_REG55_TAG0_VA_MASK    0x00001fff
+#define MH_DEBUG_REG55_TAG_valid_q_0_MASK 0x00002000
+#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG55_TAG1_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG55_TAG_valid_q_1_MASK 0x20000000
+
+#define MH_DEBUG_REG55_MASK \
+     (MH_DEBUG_REG55_TAG0_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_0_MASK | \
+      MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG55_TAG1_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_1_MASK)
+
+#define MH_DEBUG_REG55(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \
+     ((tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) | \
+      (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) | \
+      (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \
+      (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) | \
+      (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT))
+
+#define MH_DEBUG_REG55_GET_TAG0_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG0_VA_MASK) >> MH_DEBUG_REG55_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_0(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_0_MASK) >> MH_DEBUG_REG55_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG1_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG1_VA_MASK) >> MH_DEBUG_REG55_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_1(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_1_MASK) >> MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)
+
+#define MH_DEBUG_REG55_SET_TAG0_VA(mh_debug_reg55_reg, tag0_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_0(mh_debug_reg55_reg, tag_valid_q_0) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG1_VA(mh_debug_reg55_reg, tag1_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_1(mh_debug_reg55_reg, tag_valid_q_1) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int tag0_va                        : MH_DEBUG_REG55_TAG0_VA_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG55_TAG_valid_q_0_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG55_TAG1_VA_SIZE;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG55_TAG_valid_q_1_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg55_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG55_TAG_valid_q_1_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG55_TAG1_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG55_TAG_valid_q_0_SIZE;
+          unsigned int tag0_va                        : MH_DEBUG_REG55_TAG0_VA_SIZE;
+     } mh_debug_reg55_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg55_t f;
+} mh_debug_reg55_u;
+
+
+/*
+ * MH_DEBUG_REG56 struct
+ */
+
+#define MH_DEBUG_REG56_TAG2_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_2_SIZE 1
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG56_TAG3_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_3_SIZE 1
+
+#define MH_DEBUG_REG56_TAG2_VA_SHIFT   0
+#define MH_DEBUG_REG56_TAG_valid_q_2_SHIFT 13
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG56_TAG3_VA_SHIFT   16
+#define MH_DEBUG_REG56_TAG_valid_q_3_SHIFT 29
+
+#define MH_DEBUG_REG56_TAG2_VA_MASK    0x00001fff
+#define MH_DEBUG_REG56_TAG_valid_q_2_MASK 0x00002000
+#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG56_TAG3_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG56_TAG_valid_q_3_MASK 0x20000000
+
+#define MH_DEBUG_REG56_MASK \
+     (MH_DEBUG_REG56_TAG2_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_2_MASK | \
+      MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG56_TAG3_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_3_MASK)
+
+#define MH_DEBUG_REG56(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \
+     ((tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) | \
+      (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) | \
+      (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \
+      (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) | \
+      (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT))
+
+#define MH_DEBUG_REG56_GET_TAG2_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG2_VA_MASK) >> MH_DEBUG_REG56_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_2(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_2_MASK) >> MH_DEBUG_REG56_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG3_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG3_VA_MASK) >> MH_DEBUG_REG56_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_3(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_3_MASK) >> MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)
+
+#define MH_DEBUG_REG56_SET_TAG2_VA(mh_debug_reg56_reg, tag2_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_2(mh_debug_reg56_reg, tag_valid_q_2) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG3_VA(mh_debug_reg56_reg, tag3_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_3(mh_debug_reg56_reg, tag_valid_q_3) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int tag2_va                        : MH_DEBUG_REG56_TAG2_VA_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG56_TAG_valid_q_2_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG56_TAG3_VA_SIZE;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG56_TAG_valid_q_3_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg56_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG56_TAG_valid_q_3_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG56_TAG3_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG56_TAG_valid_q_2_SIZE;
+          unsigned int tag2_va                        : MH_DEBUG_REG56_TAG2_VA_SIZE;
+     } mh_debug_reg56_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg56_t f;
+} mh_debug_reg56_u;
+
+
+/*
+ * MH_DEBUG_REG57 struct
+ */
+
+#define MH_DEBUG_REG57_TAG4_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_4_SIZE 1
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG57_TAG5_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_5_SIZE 1
+
+#define MH_DEBUG_REG57_TAG4_VA_SHIFT   0
+#define MH_DEBUG_REG57_TAG_valid_q_4_SHIFT 13
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG57_TAG5_VA_SHIFT   16
+#define MH_DEBUG_REG57_TAG_valid_q_5_SHIFT 29
+
+#define MH_DEBUG_REG57_TAG4_VA_MASK    0x00001fff
+#define MH_DEBUG_REG57_TAG_valid_q_4_MASK 0x00002000
+#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG57_TAG5_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG57_TAG_valid_q_5_MASK 0x20000000
+
+#define MH_DEBUG_REG57_MASK \
+     (MH_DEBUG_REG57_TAG4_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_4_MASK | \
+      MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG57_TAG5_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_5_MASK)
+
+#define MH_DEBUG_REG57(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \
+     ((tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) | \
+      (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) | \
+      (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \
+      (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) | \
+      (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT))
+
+#define MH_DEBUG_REG57_GET_TAG4_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG4_VA_MASK) >> MH_DEBUG_REG57_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_4(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_4_MASK) >> MH_DEBUG_REG57_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG5_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG5_VA_MASK) >> MH_DEBUG_REG57_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_5(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_5_MASK) >> MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)
+
+#define MH_DEBUG_REG57_SET_TAG4_VA(mh_debug_reg57_reg, tag4_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_4(mh_debug_reg57_reg, tag_valid_q_4) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG5_VA(mh_debug_reg57_reg, tag5_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_5(mh_debug_reg57_reg, tag_valid_q_5) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int tag4_va                        : MH_DEBUG_REG57_TAG4_VA_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG57_TAG_valid_q_4_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG57_TAG5_VA_SIZE;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG57_TAG_valid_q_5_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg57_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG57_TAG_valid_q_5_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG57_TAG5_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG57_TAG_valid_q_4_SIZE;
+          unsigned int tag4_va                        : MH_DEBUG_REG57_TAG4_VA_SIZE;
+     } mh_debug_reg57_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg57_t f;
+} mh_debug_reg57_u;
+
+
+/*
+ * MH_DEBUG_REG58 struct
+ */
+
+#define MH_DEBUG_REG58_TAG6_VA_SIZE    13
+#define MH_DEBUG_REG58_TAG_valid_q_6_SIZE 1
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG58_TAG7_VA_SIZE    13
+#define MH_DEBUG_REG58_TAG_valid_q_7_SIZE 1
+
+#define MH_DEBUG_REG58_TAG6_VA_SHIFT   0
+#define MH_DEBUG_REG58_TAG_valid_q_6_SHIFT 13
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG58_TAG7_VA_SHIFT   16
+#define MH_DEBUG_REG58_TAG_valid_q_7_SHIFT 29
+
+#define MH_DEBUG_REG58_TAG6_VA_MASK    0x00001fff
+#define MH_DEBUG_REG58_TAG_valid_q_6_MASK 0x00002000
+#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG58_TAG7_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG58_TAG_valid_q_7_MASK 0x20000000
+
+#define MH_DEBUG_REG58_MASK \
+     (MH_DEBUG_REG58_TAG6_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_6_MASK | \
+      MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG58_TAG7_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_7_MASK)
+
+#define MH_DEBUG_REG58(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \
+     ((tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) | \
+      (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) | \
+      (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \
+      (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) | \
+      (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT))
+
+#define MH_DEBUG_REG58_GET_TAG6_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG6_VA_MASK) >> MH_DEBUG_REG58_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_6(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_6_MASK) >> MH_DEBUG_REG58_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG7_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG7_VA_MASK) >> MH_DEBUG_REG58_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_7(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_7_MASK) >> MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)
+
+#define MH_DEBUG_REG58_SET_TAG6_VA(mh_debug_reg58_reg, tag6_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_6(mh_debug_reg58_reg, tag_valid_q_6) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG7_VA(mh_debug_reg58_reg, tag7_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_7(mh_debug_reg58_reg, tag_valid_q_7) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int tag6_va                        : MH_DEBUG_REG58_TAG6_VA_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG58_TAG_valid_q_6_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG58_TAG7_VA_SIZE;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG58_TAG_valid_q_7_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg58_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG58_TAG_valid_q_7_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG58_TAG7_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG58_TAG_valid_q_6_SIZE;
+          unsigned int tag6_va                        : MH_DEBUG_REG58_TAG6_VA_SIZE;
+     } mh_debug_reg58_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg58_t f;
+} mh_debug_reg58_u;
+
+
+/*
+ * MH_DEBUG_REG59 struct
+ */
+
+#define MH_DEBUG_REG59_TAG8_VA_SIZE    13
+#define MH_DEBUG_REG59_TAG_valid_q_8_SIZE 1
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG59_TAG9_VA_SIZE    13
+#define MH_DEBUG_REG59_TAG_valid_q_9_SIZE 1
+
+#define MH_DEBUG_REG59_TAG8_VA_SHIFT   0
+#define MH_DEBUG_REG59_TAG_valid_q_8_SHIFT 13
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG59_TAG9_VA_SHIFT   16
+#define MH_DEBUG_REG59_TAG_valid_q_9_SHIFT 29
+
+#define MH_DEBUG_REG59_TAG8_VA_MASK    0x00001fff
+#define MH_DEBUG_REG59_TAG_valid_q_8_MASK 0x00002000
+#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG59_TAG9_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG59_TAG_valid_q_9_MASK 0x20000000
+
+#define MH_DEBUG_REG59_MASK \
+     (MH_DEBUG_REG59_TAG8_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_8_MASK | \
+      MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG59_TAG9_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_9_MASK)
+
+#define MH_DEBUG_REG59(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \
+     ((tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) | \
+      (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) | \
+      (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \
+      (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) | \
+      (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT))
+
+#define MH_DEBUG_REG59_GET_TAG8_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG8_VA_MASK) >> MH_DEBUG_REG59_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_8(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_8_MASK) >> MH_DEBUG_REG59_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG9_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG9_VA_MASK) >> MH_DEBUG_REG59_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_9(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_9_MASK) >> MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)
+
+#define MH_DEBUG_REG59_SET_TAG8_VA(mh_debug_reg59_reg, tag8_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_8(mh_debug_reg59_reg, tag_valid_q_8) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG9_VA(mh_debug_reg59_reg, tag9_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_9(mh_debug_reg59_reg, tag_valid_q_9) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int tag8_va                        : MH_DEBUG_REG59_TAG8_VA_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG59_TAG_valid_q_8_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG59_TAG9_VA_SIZE;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG59_TAG_valid_q_9_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg59_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG59_TAG_valid_q_9_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG59_TAG9_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG59_TAG_valid_q_8_SIZE;
+          unsigned int tag8_va                        : MH_DEBUG_REG59_TAG8_VA_SIZE;
+     } mh_debug_reg59_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg59_t f;
+} mh_debug_reg59_u;
+
+
+/*
+ * MH_DEBUG_REG60 struct
+ */
+
+#define MH_DEBUG_REG60_TAG10_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_10_SIZE 1
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG60_TAG11_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_11_SIZE 1
+
+#define MH_DEBUG_REG60_TAG10_VA_SHIFT  0
+#define MH_DEBUG_REG60_TAG_valid_q_10_SHIFT 13
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG60_TAG11_VA_SHIFT  16
+#define MH_DEBUG_REG60_TAG_valid_q_11_SHIFT 29
+
+#define MH_DEBUG_REG60_TAG10_VA_MASK   0x00001fff
+#define MH_DEBUG_REG60_TAG_valid_q_10_MASK 0x00002000
+#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG60_TAG11_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG60_TAG_valid_q_11_MASK 0x20000000
+
+#define MH_DEBUG_REG60_MASK \
+     (MH_DEBUG_REG60_TAG10_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_10_MASK | \
+      MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG60_TAG11_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_11_MASK)
+
+#define MH_DEBUG_REG60(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \
+     ((tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) | \
+      (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) | \
+      (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \
+      (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) | \
+      (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT))
+
+#define MH_DEBUG_REG60_GET_TAG10_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG10_VA_MASK) >> MH_DEBUG_REG60_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_10(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_10_MASK) >> MH_DEBUG_REG60_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG11_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG11_VA_MASK) >> MH_DEBUG_REG60_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_11(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_11_MASK) >> MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)
+
+#define MH_DEBUG_REG60_SET_TAG10_VA(mh_debug_reg60_reg, tag10_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_10(mh_debug_reg60_reg, tag_valid_q_10) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG11_VA(mh_debug_reg60_reg, tag11_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_11(mh_debug_reg60_reg, tag_valid_q_11) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int tag10_va                       : MH_DEBUG_REG60_TAG10_VA_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG60_TAG11_VA_SIZE;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg60_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG60_TAG11_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE;
+          unsigned int tag10_va                       : MH_DEBUG_REG60_TAG10_VA_SIZE;
+     } mh_debug_reg60_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg60_t f;
+} mh_debug_reg60_u;
+
+
+/*
+ * MH_DEBUG_REG61 struct
+ */
+
+#define MH_DEBUG_REG61_TAG12_VA_SIZE   13
+#define MH_DEBUG_REG61_TAG_valid_q_12_SIZE 1
+#define MH_DEBUG_REG61_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG61_TAG13_VA_SIZE   13
+#define MH_DEBUG_REG61_TAG_valid_q_13_SIZE 1
+
+#define MH_DEBUG_REG61_TAG12_VA_SHIFT  0
+#define MH_DEBUG_REG61_TAG_valid_q_12_SHIFT 13
+#define MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG61_TAG13_VA_SHIFT  16
+#define MH_DEBUG_REG61_TAG_valid_q_13_SHIFT 29
+
+#define MH_DEBUG_REG61_TAG12_VA_MASK   0x00001fff
+#define MH_DEBUG_REG61_TAG_valid_q_12_MASK 0x00002000
+#define MH_DEBUG_REG61_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG61_TAG13_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG61_TAG_valid_q_13_MASK 0x20000000
+
+#define MH_DEBUG_REG61_MASK \
+     (MH_DEBUG_REG61_TAG12_VA_MASK | \
+      MH_DEBUG_REG61_TAG_valid_q_12_MASK | \
+      MH_DEBUG_REG61_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG61_TAG13_VA_MASK | \
+      MH_DEBUG_REG61_TAG_valid_q_13_MASK)
+
+#define MH_DEBUG_REG61(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \
+     ((tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) | \
+      (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) | \
+      (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) | \
+      (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) | \
+      (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT))
+
+#define MH_DEBUG_REG61_GET_TAG12_VA(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG12_VA_MASK) >> MH_DEBUG_REG61_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG_valid_q_12(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_12_MASK) >> MH_DEBUG_REG61_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG61_GET_ALWAYS_ZERO(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG13_VA(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG13_VA_MASK) >> MH_DEBUG_REG61_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG_valid_q_13(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_13_MASK) >> MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)
+
+#define MH_DEBUG_REG61_SET_TAG12_VA(mh_debug_reg61_reg, tag12_va) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG_valid_q_12(mh_debug_reg61_reg, tag_valid_q_12) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG61_SET_ALWAYS_ZERO(mh_debug_reg61_reg, always_zero) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG13_VA(mh_debug_reg61_reg, tag13_va) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG_valid_q_13(mh_debug_reg61_reg, tag_valid_q_13) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int tag12_va                       : MH_DEBUG_REG61_TAG12_VA_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG61_TAG13_VA_SIZE;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg61_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG61_TAG13_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE;
+          unsigned int tag12_va                       : MH_DEBUG_REG61_TAG12_VA_SIZE;
+     } mh_debug_reg61_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg61_t f;
+} mh_debug_reg61_u;
+
+
+/*
+ * MH_DEBUG_REG62 struct
+ */
+
+#define MH_DEBUG_REG62_TAG14_VA_SIZE   13
+#define MH_DEBUG_REG62_TAG_valid_q_14_SIZE 1
+#define MH_DEBUG_REG62_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG62_TAG15_VA_SIZE   13
+#define MH_DEBUG_REG62_TAG_valid_q_15_SIZE 1
+
+#define MH_DEBUG_REG62_TAG14_VA_SHIFT  0
+#define MH_DEBUG_REG62_TAG_valid_q_14_SHIFT 13
+#define MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG62_TAG15_VA_SHIFT  16
+#define MH_DEBUG_REG62_TAG_valid_q_15_SHIFT 29
+
+#define MH_DEBUG_REG62_TAG14_VA_MASK   0x00001fff
+#define MH_DEBUG_REG62_TAG_valid_q_14_MASK 0x00002000
+#define MH_DEBUG_REG62_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG62_TAG15_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG62_TAG_valid_q_15_MASK 0x20000000
+
+#define MH_DEBUG_REG62_MASK \
+     (MH_DEBUG_REG62_TAG14_VA_MASK | \
+      MH_DEBUG_REG62_TAG_valid_q_14_MASK | \
+      MH_DEBUG_REG62_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG62_TAG15_VA_MASK | \
+      MH_DEBUG_REG62_TAG_valid_q_15_MASK)
+
+#define MH_DEBUG_REG62(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \
+     ((tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) | \
+      (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) | \
+      (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) | \
+      (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) | \
+      (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT))
+
+#define MH_DEBUG_REG62_GET_TAG14_VA(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG14_VA_MASK) >> MH_DEBUG_REG62_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG_valid_q_14(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_14_MASK) >> MH_DEBUG_REG62_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG62_GET_ALWAYS_ZERO(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG15_VA(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG15_VA_MASK) >> MH_DEBUG_REG62_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG_valid_q_15(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_15_MASK) >> MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)
+
+#define MH_DEBUG_REG62_SET_TAG14_VA(mh_debug_reg62_reg, tag14_va) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG_valid_q_14(mh_debug_reg62_reg, tag_valid_q_14) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG62_SET_ALWAYS_ZERO(mh_debug_reg62_reg, always_zero) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG15_VA(mh_debug_reg62_reg, tag15_va) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG_valid_q_15(mh_debug_reg62_reg, tag_valid_q_15) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int tag14_va                       : MH_DEBUG_REG62_TAG14_VA_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG62_TAG15_VA_SIZE;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg62_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG62_TAG15_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE;
+          unsigned int tag14_va                       : MH_DEBUG_REG62_TAG14_VA_SIZE;
+     } mh_debug_reg62_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg62_t f;
+} mh_debug_reg62_u;
+
+
+/*
+ * MH_DEBUG_REG63 struct
+ */
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG63_MASK \
+     (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG63(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \
+     ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \
+     mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg63_t f;
+} mh_debug_reg63_u;
+
+
+/*
+ * MH_MMU_CONFIG struct
+ */
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SIZE  1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1
+#define MH_MMU_CONFIG_RESERVED1_SIZE   2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE 2
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1
+#define MH_MMU_CONFIG_RESERVED1_SHIFT  2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT 24
+
+#define MH_MMU_CONFIG_MMU_ENABLE_MASK  0x00000001
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002
+#define MH_MMU_CONFIG_RESERVED1_MASK   0x0000000c
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK 0x03000000
+
+#define MH_MMU_CONFIG_MASK \
+     (MH_MMU_CONFIG_MMU_ENABLE_MASK | \
+      MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \
+      MH_MMU_CONFIG_RESERVED1_MASK | \
+      MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK)
+
+#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior, pa_w_clnt_behavior) \
+     ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \
+      (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \
+      (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \
+      (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) | \
+      (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT))
+
+#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_PA_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)
+
+#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_PA_W_CLNT_BEHAVIOR(mh_mmu_config_reg, pa_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) | (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int pa_w_clnt_behavior             : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int                                : 6;
+     } mh_mmu_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int                                : 6;
+          unsigned int pa_w_clnt_behavior             : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+     } mh_mmu_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_config_t f;
+} mh_mmu_config_u;
+
+
+/*
+ * MH_MMU_VA_RANGE struct
+ */
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12
+#define MH_MMU_VA_RANGE_VA_BASE_SIZE   20
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0
+#define MH_MMU_VA_RANGE_VA_BASE_SHIFT  12
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff
+#define MH_MMU_VA_RANGE_VA_BASE_MASK   0xfffff000
+
+#define MH_MMU_VA_RANGE_MASK \
+     (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \
+      MH_MMU_VA_RANGE_VA_BASE_MASK)
+
+#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \
+     ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \
+      (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT))
+
+#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+     } mh_mmu_va_range_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+     } mh_mmu_va_range_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_va_range_t f;
+} mh_mmu_va_range_u;
+
+
+/*
+ * MH_MMU_PT_BASE struct
+ */
+
+#define MH_MMU_PT_BASE_PT_BASE_SIZE    20
+
+#define MH_MMU_PT_BASE_PT_BASE_SHIFT   12
+
+#define MH_MMU_PT_BASE_PT_BASE_MASK    0xfffff000
+
+#define MH_MMU_PT_BASE_MASK \
+     (MH_MMU_PT_BASE_PT_BASE_MASK)
+
+#define MH_MMU_PT_BASE(pt_base) \
+     ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT))
+
+#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \
+     ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \
+     mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int                                : 12;
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+     } mh_mmu_pt_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_pt_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_pt_base_t f;
+} mh_mmu_pt_base_u;
+
+
+/*
+ * MH_MMU_PAGE_FAULT struct
+ */
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE  3
+#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE  20
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4
+#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11
+#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001
+#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c
+#define MH_MMU_PAGE_FAULT_AXI_ID_MASK  0x00000070
+#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800
+#define MH_MMU_PAGE_FAULT_REQ_VA_MASK  0xfffff000
+
+#define MH_MMU_PAGE_FAULT_MASK \
+     (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \
+      MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \
+      MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_PAGE_FAULT_AXI_ID_MASK | \
+      MH_MMU_PAGE_FAULT_RESERVED1_MASK | \
+      MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_REQ_VA_MASK)
+
+#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \
+     ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \
+      (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \
+      (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \
+      (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \
+      (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \
+      (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \
+      (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \
+      (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT))
+
+#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+     } mh_mmu_page_fault_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+     } mh_mmu_page_fault_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_page_fault_t f;
+} mh_mmu_page_fault_u;
+
+
+/*
+ * MH_MMU_TRAN_ERROR struct
+ */
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0
+
+#define MH_MMU_TRAN_ERROR_MASK \
+     (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK)
+
+#define MH_MMU_TRAN_ERROR(tran_error) \
+     ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT))
+
+#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \
+     ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \
+     mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int                                : 5;
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+     } mh_mmu_tran_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+          unsigned int                                : 5;
+     } mh_mmu_tran_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_tran_error_t f;
+} mh_mmu_tran_error_u;
+
+
+/*
+ * MH_MMU_INVALIDATE struct
+ */
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002
+
+#define MH_MMU_INVALIDATE_MASK \
+     (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_MMU_INVALIDATE_INVALIDATE_TC_MASK)
+
+#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \
+     ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT))
+
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int                                : 30;
+     } mh_mmu_invalidate_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int                                : 30;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+     } mh_mmu_invalidate_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_invalidate_t f;
+} mh_mmu_invalidate_u;
+
+
+/*
+ * MH_MMU_MPU_BASE struct
+ */
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SIZE  20
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12
+
+#define MH_MMU_MPU_BASE_MPU_BASE_MASK  0xfffff000
+
+#define MH_MMU_MPU_BASE_MASK \
+     (MH_MMU_MPU_BASE_MPU_BASE_MASK)
+
+#define MH_MMU_MPU_BASE(mpu_base) \
+     ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT))
+
+#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \
+     ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \
+     mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int                                : 12;
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+     } mh_mmu_mpu_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_base_t f;
+} mh_mmu_mpu_base_u;
+
+
+/*
+ * MH_MMU_MPU_END struct
+ */
+
+#define MH_MMU_MPU_END_MPU_END_SIZE    20
+
+#define MH_MMU_MPU_END_MPU_END_SHIFT   12
+
+#define MH_MMU_MPU_END_MPU_END_MASK    0xfffff000
+
+#define MH_MMU_MPU_END_MASK \
+     (MH_MMU_MPU_END_MPU_END_MASK)
+
+#define MH_MMU_MPU_END(mpu_end) \
+     ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT))
+
+#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \
+     ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \
+     mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int                                : 12;
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+     } mh_mmu_mpu_end_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_end_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_end_t f;
+} mh_mmu_mpu_end_u;
+
+
+#endif
+
+
+#if !defined (_PA_FIDDLE_H)
+#define _PA_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  pa_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * PA_CL_VPORT_XSCALE struct
+ */
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_XSCALE_MASK \
+     (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK)
+
+#define PA_CL_VPORT_XSCALE(vport_xscale) \
+     ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT))
+
+#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \
+     ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \
+     pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xscale_t f;
+} pa_cl_vport_xscale_u;
+
+
+/*
+ * PA_CL_VPORT_XOFFSET struct
+ */
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_XOFFSET_MASK \
+     (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK)
+
+#define PA_CL_VPORT_XOFFSET(vport_xoffset) \
+     ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT))
+
+#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \
+     ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \
+     pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xoffset_t f;
+} pa_cl_vport_xoffset_u;
+
+
+/*
+ * PA_CL_VPORT_YSCALE struct
+ */
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_YSCALE_MASK \
+     (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK)
+
+#define PA_CL_VPORT_YSCALE(vport_yscale) \
+     ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT))
+
+#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \
+     ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \
+     pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yscale_t f;
+} pa_cl_vport_yscale_u;
+
+
+/*
+ * PA_CL_VPORT_YOFFSET struct
+ */
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_YOFFSET_MASK \
+     (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK)
+
+#define PA_CL_VPORT_YOFFSET(vport_yoffset) \
+     ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT))
+
+#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \
+     ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \
+     pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yoffset_t f;
+} pa_cl_vport_yoffset_u;
+
+
+/*
+ * PA_CL_VPORT_ZSCALE struct
+ */
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZSCALE_MASK \
+     (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK)
+
+#define PA_CL_VPORT_ZSCALE(vport_zscale) \
+     ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT))
+
+#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \
+     ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \
+     pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zscale_t f;
+} pa_cl_vport_zscale_u;
+
+
+/*
+ * PA_CL_VPORT_ZOFFSET struct
+ */
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZOFFSET_MASK \
+     (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK)
+
+#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \
+     ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT))
+
+#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \
+     ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \
+     pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zoffset_t f;
+} pa_cl_vport_zoffset_u;
+
+
+/*
+ * PA_CL_VTE_CNTL struct
+ */
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE  1
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK  0x00000200
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800
+
+#define PA_CL_VTE_CNTL_MASK \
+     (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \
+      PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK)
+
+#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \
+     ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \
+      (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \
+      (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \
+      (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \
+      (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \
+      (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \
+      (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \
+      (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \
+      (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \
+      (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT))
+
+#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int                                : 2;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int                                : 20;
+     } pa_cl_vte_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int                                : 20;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int                                : 2;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+     } pa_cl_vte_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vte_cntl_t f;
+} pa_cl_vte_cntl_u;
+
+
+/*
+ * PA_CL_CLIP_CNTL struct
+ */
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000
+
+#define PA_CL_CLIP_CNTL_MASK \
+     (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \
+      PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \
+      PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \
+      PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \
+      PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \
+      PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK)
+
+#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \
+     ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \
+      (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \
+      (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \
+      (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \
+      (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \
+      (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \
+      (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \
+      (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT))
+
+#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 16;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int                                : 7;
+     } pa_cl_clip_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 7;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 16;
+     } pa_cl_clip_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_clip_cntl_t f;
+} pa_cl_clip_cntl_u;
+
+
+/*
+ * PA_CL_GB_VERT_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_CLIP_ADJ_MASK \
+     (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \
+     ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \
+     pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_clip_adj_t f;
+} pa_cl_gb_vert_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_VERT_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_DISC_ADJ_MASK \
+     (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \
+     ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \
+     pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_disc_adj_t f;
+} pa_cl_gb_vert_disc_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \
+     (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \
+     ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \
+     pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_clip_adj_t f;
+} pa_cl_gb_horz_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_DISC_ADJ_MASK \
+     (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \
+     ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \
+     pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_disc_adj_t f;
+} pa_cl_gb_horz_disc_adj_u;
+
+
+/*
+ * PA_CL_ENHANCE struct
+ */
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1
+#define PA_CL_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0
+#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001
+#define PA_CL_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_CL_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_CL_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_CL_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_CL_ENHANCE_MASK \
+     (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE3_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE2_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE1_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \
+      (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+          unsigned int                                : 27;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_cl_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 27;
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+     } pa_cl_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_enhance_t f;
+} pa_cl_enhance_u;
+
+
+/*
+ * PA_SC_ENHANCE struct
+ */
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_SC_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_SC_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_SC_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_SC_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_SC_ENHANCE_MASK \
+     (PA_SC_ENHANCE_ECO_SPARE3_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE2_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE1_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int                                : 28;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_sc_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 28;
+     } pa_sc_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_enhance_t f;
+} pa_sc_enhance_u;
+
+
+/*
+ * PA_SU_VTX_CNTL struct
+ */
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1
+#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2
+#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0
+#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1
+#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001
+#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006
+#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038
+
+#define PA_SU_VTX_CNTL_MASK \
+     (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \
+      PA_SU_VTX_CNTL_ROUND_MODE_MASK | \
+      PA_SU_VTX_CNTL_QUANT_MODE_MASK)
+
+#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \
+     ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \
+      (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \
+      (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT))
+
+#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int                                : 26;
+     } pa_su_vtx_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int                                : 26;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+     } pa_su_vtx_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_vtx_cntl_t f;
+} pa_su_vtx_cntl_u;
+
+
+/*
+ * PA_SU_POINT_SIZE struct
+ */
+
+#define PA_SU_POINT_SIZE_HEIGHT_SIZE   16
+#define PA_SU_POINT_SIZE_WIDTH_SIZE    16
+
+#define PA_SU_POINT_SIZE_HEIGHT_SHIFT  0
+#define PA_SU_POINT_SIZE_WIDTH_SHIFT   16
+
+#define PA_SU_POINT_SIZE_HEIGHT_MASK   0x0000ffff
+#define PA_SU_POINT_SIZE_WIDTH_MASK    0xffff0000
+
+#define PA_SU_POINT_SIZE_MASK \
+     (PA_SU_POINT_SIZE_HEIGHT_MASK | \
+      PA_SU_POINT_SIZE_WIDTH_MASK)
+
+#define PA_SU_POINT_SIZE(height, width) \
+     ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \
+      (width << PA_SU_POINT_SIZE_WIDTH_SHIFT))
+
+#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+     } pa_su_point_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+     } pa_su_point_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_size_t f;
+} pa_su_point_size_u;
+
+
+/*
+ * PA_SU_POINT_MINMAX struct
+ */
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff
+#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000
+
+#define PA_SU_POINT_MINMAX_MASK \
+     (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \
+      PA_SU_POINT_MINMAX_MAX_SIZE_MASK)
+
+#define PA_SU_POINT_MINMAX(min_size, max_size) \
+     ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \
+      (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT))
+
+#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_minmax_t f;
+} pa_su_point_minmax_u;
+
+
+/*
+ * PA_SU_LINE_CNTL struct
+ */
+
+#define PA_SU_LINE_CNTL_WIDTH_SIZE     16
+
+#define PA_SU_LINE_CNTL_WIDTH_SHIFT    0
+
+#define PA_SU_LINE_CNTL_WIDTH_MASK     0x0000ffff
+
+#define PA_SU_LINE_CNTL_MASK \
+     (PA_SU_LINE_CNTL_WIDTH_MASK)
+
+#define PA_SU_LINE_CNTL(width) \
+     ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT))
+
+#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \
+     ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \
+     pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+          unsigned int                                : 16;
+     } pa_su_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int                                : 16;
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+     } pa_su_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_line_cntl_t f;
+} pa_su_line_cntl_u;
+
+
+/*
+ * PA_SU_FACE_DATA struct
+ */
+
+#define PA_SU_FACE_DATA_BASE_ADDR_SIZE 27
+
+#define PA_SU_FACE_DATA_BASE_ADDR_SHIFT 5
+
+#define PA_SU_FACE_DATA_BASE_ADDR_MASK 0xffffffe0
+
+#define PA_SU_FACE_DATA_MASK \
+     (PA_SU_FACE_DATA_BASE_ADDR_MASK)
+
+#define PA_SU_FACE_DATA(base_addr) \
+     ((base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT))
+
+#define PA_SU_FACE_DATA_GET_BASE_ADDR(pa_su_face_data) \
+     ((pa_su_face_data & PA_SU_FACE_DATA_BASE_ADDR_MASK) >> PA_SU_FACE_DATA_BASE_ADDR_SHIFT)
+
+#define PA_SU_FACE_DATA_SET_BASE_ADDR(pa_su_face_data_reg, base_addr) \
+     pa_su_face_data_reg = (pa_su_face_data_reg & ~PA_SU_FACE_DATA_BASE_ADDR_MASK) | (base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_face_data_t {
+          unsigned int                                : 5;
+          unsigned int base_addr                      : PA_SU_FACE_DATA_BASE_ADDR_SIZE;
+     } pa_su_face_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_face_data_t {
+          unsigned int base_addr                      : PA_SU_FACE_DATA_BASE_ADDR_SIZE;
+          unsigned int                                : 5;
+     } pa_su_face_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_face_data_t f;
+} pa_su_face_data_u;
+
+
+/*
+ * PA_SU_SC_MODE_CNTL struct
+ */
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_SIZE   1
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE 1
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1
+#define PA_SU_SC_MODE_CNTL_FACE_SHIFT  2
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT 29
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT 30
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT 31
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002
+#define PA_SU_SC_MODE_CNTL_FACE_MASK   0x00000004
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK 0x20000000
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK 0x40000000
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK 0x80000000
+
+#define PA_SU_SC_MODE_CNTL_MASK \
+     (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \
+      PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \
+      PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \
+      PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \
+      PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK | \
+      PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK)
+
+#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state, zero_area_faceness, face_kill_enable, face_write_enable) \
+     ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \
+      (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \
+      (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \
+      (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \
+      (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \
+      (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \
+      (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \
+      (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \
+      (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \
+      (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \
+      (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \
+      (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \
+      (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \
+      (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \
+      (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \
+      (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \
+      (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \
+      (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) | \
+      (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) | \
+      (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) | \
+      (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT))
+
+#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)
+
+#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl_reg, zero_area_faceness) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) | (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl_reg, face_kill_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) | (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl_reg, face_write_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) | (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int                                : 2;
+          unsigned int zero_area_faceness             : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE;
+          unsigned int face_kill_enable               : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE;
+          unsigned int face_write_enable              : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int face_write_enable              : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE;
+          unsigned int face_kill_enable               : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE;
+          unsigned int zero_area_faceness             : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE;
+          unsigned int                                : 2;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_sc_mode_cntl_t f;
+} pa_su_sc_mode_cntl_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \
+     ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \
+     pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_scale_t f;
+} pa_su_poly_offset_front_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \
+     ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \
+     pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_offset_t f;
+} pa_su_poly_offset_front_offset_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \
+     ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \
+     pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_scale_t f;
+} pa_su_poly_offset_back_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \
+     ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \
+     pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_offset_t f;
+} pa_su_poly_offset_back_offset_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER0_SELECT_MASK \
+     (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \
+     ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \
+     pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_select_t f;
+} pa_su_perfcounter0_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER1_SELECT_MASK \
+     (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \
+     ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \
+     pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_select_t f;
+} pa_su_perfcounter1_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER2_SELECT_MASK \
+     (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \
+     ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \
+     pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_select_t f;
+} pa_su_perfcounter2_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER3_SELECT_MASK \
+     (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \
+     ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \
+     pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_select_t f;
+} pa_su_perfcounter3_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER0_LOW_MASK \
+     (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \
+     ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \
+     pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_low_t f;
+} pa_su_perfcounter0_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER0_HI_MASK \
+     (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \
+     ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \
+     pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_hi_t f;
+} pa_su_perfcounter0_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER1_LOW_MASK \
+     (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \
+     ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \
+     pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_low_t f;
+} pa_su_perfcounter1_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER1_HI_MASK \
+     (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \
+     ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \
+     pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_hi_t f;
+} pa_su_perfcounter1_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER2_LOW_MASK \
+     (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \
+     ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \
+     pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_low_t f;
+} pa_su_perfcounter2_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER2_HI_MASK \
+     (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \
+     ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \
+     pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_hi_t f;
+} pa_su_perfcounter2_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER3_LOW_MASK \
+     (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \
+     ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \
+     pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_low_t f;
+} pa_su_perfcounter3_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER3_HI_MASK \
+     (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \
+     ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \
+     pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_hi_t f;
+} pa_su_perfcounter3_hi_u;
+
+
+/*
+ * PA_SC_WINDOW_OFFSET struct
+ */
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000
+
+#define PA_SC_WINDOW_OFFSET_MASK \
+     (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \
+      PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK)
+
+#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \
+     ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \
+      (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT))
+
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_window_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+     } pa_sc_window_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_offset_t f;
+} pa_sc_window_offset_u;
+
+
+/*
+ * PA_SC_AA_CONFIG struct
+ */
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000
+
+#define PA_SC_AA_CONFIG_MASK \
+     (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \
+      PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK)
+
+#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \
+     ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \
+      (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT))
+
+#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+          unsigned int                                : 10;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 15;
+     } pa_sc_aa_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int                                : 15;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 10;
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+     } pa_sc_aa_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_config_t f;
+} pa_sc_aa_config_u;
+
+
+/*
+ * PA_SC_AA_MASK struct
+ */
+
+#define PA_SC_AA_MASK_AA_MASK_SIZE     16
+
+#define PA_SC_AA_MASK_AA_MASK_SHIFT    0
+
+#define PA_SC_AA_MASK_AA_MASK_MASK     0x0000ffff
+
+#define PA_SC_AA_MASK_MASK \
+     (PA_SC_AA_MASK_AA_MASK_MASK)
+
+#define PA_SC_AA_MASK(aa_mask) \
+     ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT))
+
+#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \
+     ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \
+     pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_aa_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int                                : 16;
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+     } pa_sc_aa_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_mask_t f;
+} pa_sc_aa_mask_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000
+
+#define PA_SC_LINE_STIPPLE_MASK \
+     (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \
+      PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \
+      PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \
+      PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK)
+
+#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \
+     ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \
+      (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \
+      (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \
+      (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_line_stipple_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int                                : 1;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int                                : 4;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+     } pa_sc_line_stipple_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_t f;
+} pa_sc_line_stipple_u;
+
+
+/*
+ * PA_SC_LINE_CNTL struct
+ */
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200
+#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400
+
+#define PA_SC_LINE_CNTL_MASK \
+     (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \
+      PA_SC_LINE_CNTL_LAST_PIXEL_MASK)
+
+#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \
+     ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \
+      (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \
+      (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \
+      (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT))
+
+#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int                                : 21;
+     } pa_sc_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int                                : 21;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+     } pa_sc_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_cntl_t f;
+} pa_sc_line_cntl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_TL struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000
+
+#define PA_SC_WINDOW_SCISSOR_TL_MASK \
+     (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \
+     ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \
+      (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_tl_t f;
+} pa_sc_window_scissor_tl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_BR struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000
+
+#define PA_SC_WINDOW_SCISSOR_BR_MASK \
+     (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+     } pa_sc_window_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_window_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_br_t f;
+} pa_sc_window_scissor_br_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_TL struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_TL_MASK \
+     (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \
+     ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_screen_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_tl_t f;
+} pa_sc_screen_scissor_tl_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_BR struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_BR_MASK \
+     (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_screen_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_br_t f;
+} pa_sc_screen_scissor_br_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY struct
+ */
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080
+
+#define PA_SC_VIZ_QUERY_MASK \
+     (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \
+      PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \
+      PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK)
+
+#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \
+     ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \
+      (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \
+      (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT))
+
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int                                : 1;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_viz_query_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int                                : 24;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 1;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+     } pa_sc_viz_query_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_t f;
+} pa_sc_viz_query_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY_STATUS struct
+ */
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff
+
+#define PA_SC_VIZ_QUERY_STATUS_MASK \
+     (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK)
+
+#define PA_SC_VIZ_QUERY_STATUS(status_bits) \
+     ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT))
+
+#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \
+     ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \
+     pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_status_t f;
+} pa_sc_viz_query_status_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE_STATE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00
+
+#define PA_SC_LINE_STIPPLE_STATE_MASK \
+     (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \
+      PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK)
+
+#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \
+     ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \
+      (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_line_stipple_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int                                : 16;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+     } pa_sc_line_stipple_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_state_t f;
+} pa_sc_line_stipple_state_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SC_PERFCOUNTER0_SELECT_MASK \
+     (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \
+     ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \
+     pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_sc_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_select_t f;
+} pa_sc_perfcounter0_select_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SC_PERFCOUNTER0_LOW_MASK \
+     (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \
+     ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \
+     pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_low_t f;
+} pa_sc_perfcounter0_low_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SC_PERFCOUNTER0_HI_MASK \
+     (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \
+     ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \
+     pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_hi_t f;
+} pa_sc_perfcounter0_hi_u;
+
+
+/*
+ * PA_CL_CNTL_STATUS struct
+ */
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000
+
+#define PA_CL_CNTL_STATUS_MASK \
+     (PA_CL_CNTL_STATUS_CL_BUSY_MASK)
+
+#define PA_CL_CNTL_STATUS(cl_busy) \
+     ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT))
+
+#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \
+     ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \
+     pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+     } pa_cl_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_cl_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_cntl_status_t f;
+} pa_cl_cntl_status_u;
+
+
+/*
+ * PA_SU_CNTL_STATUS struct
+ */
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000
+
+#define PA_SU_CNTL_STATUS_MASK \
+     (PA_SU_CNTL_STATUS_SU_BUSY_MASK)
+
+#define PA_SU_CNTL_STATUS(su_busy) \
+     ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT))
+
+#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \
+     ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \
+     pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+     } pa_su_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_su_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_cntl_status_t f;
+} pa_su_cntl_status_u;
+
+
+/*
+ * PA_SC_CNTL_STATUS struct
+ */
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000
+
+#define PA_SC_CNTL_STATUS_MASK \
+     (PA_SC_CNTL_STATUS_SC_BUSY_MASK)
+
+#define PA_SC_CNTL_STATUS(sc_busy) \
+     ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT))
+
+#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \
+     ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \
+     pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+     } pa_sc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_sc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_cntl_status_t f;
+} pa_sc_cntl_status_u;
+
+
+/*
+ * PA_SU_DEBUG_CNTL struct
+ */
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SU_DEBUG_CNTL_MASK \
+     (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK)
+
+#define PA_SU_DEBUG_CNTL(su_debug_indx) \
+     ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT))
+
+#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \
+     ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \
+     pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_su_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+     } pa_su_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_cntl_t f;
+} pa_su_debug_cntl_u;
+
+
+/*
+ * PA_SU_DEBUG_DATA struct
+ */
+
+#define PA_SU_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SU_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SU_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SU_DEBUG_DATA_MASK \
+     (PA_SU_DEBUG_DATA_DATA_MASK)
+
+#define PA_SU_DEBUG_DATA(data) \
+     ((data << PA_SU_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \
+     ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \
+     pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_data_t f;
+} pa_su_debug_data_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG00 struct
+ */
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000
+
+#define CLIPPER_DEBUG_REG00_MASK \
+     (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \
+     ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \
+      (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \
+      (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \
+      (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \
+      (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \
+      (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \
+      (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \
+      (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \
+      (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \
+      (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \
+      (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \
+      (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \
+      (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \
+      (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \
+      (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \
+      (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \
+      (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \
+      (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \
+      (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \
+      (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+     } clipper_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg00_t f;
+} clipper_debug_reg00_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG01 struct
+ */
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000
+
+#define CLIPPER_DEBUG_REG01_MASK \
+     (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \
+      CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \
+     ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \
+      (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \
+      (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \
+      (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \
+      (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \
+      (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \
+      (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+     } clipper_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg01_t f;
+} clipper_debug_reg01_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG02 struct
+ */
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+
+#define CLIPPER_DEBUG_REG02_MASK \
+     (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \
+      CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK)
+
+#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \
+     ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \
+      (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT))
+
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+     } clipper_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+     } clipper_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg02_t f;
+} clipper_debug_reg02_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG03 struct
+ */
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG03_MASK \
+     (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \
+     ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+     } clipper_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg03_t f;
+} clipper_debug_reg03_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG04 struct
+ */
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00
+
+#define CLIPPER_DEBUG_REG04_MASK \
+     (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \
+     ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+     } clipper_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg04_t f;
+} clipper_debug_reg04_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG05 struct
+ */
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000
+
+#define CLIPPER_DEBUG_REG05_MASK \
+     (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \
+     ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \
+      (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+     } clipper_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg05_t f;
+} clipper_debug_reg05_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG09 struct
+ */
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000
+#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000
+
+#define CLIPPER_DEBUG_REG09_MASK \
+     (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \
+      CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK)
+
+#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \
+     ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \
+      (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \
+      (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \
+      (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \
+      (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \
+      (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \
+      (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \
+      (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \
+      (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT))
+
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+     } clipper_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+     } clipper_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg09_t f;
+} clipper_debug_reg09_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG10 struct
+ */
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG10_MASK \
+     (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK)
+
+#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \
+     ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \
+      (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \
+      (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \
+      (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \
+      (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT))
+
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+     } clipper_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+     } clipper_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg10_t f;
+} clipper_debug_reg10_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG11 struct
+ */
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0
+
+#define CLIPPER_DEBUG_REG11_MASK \
+     (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \
+      CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \
+     ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+     } clipper_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg11_t f;
+} clipper_debug_reg11_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG12 struct
+ */
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define CLIPPER_DEBUG_REG12_MASK \
+     (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \
+      CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \
+     ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \
+      (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \
+      (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \
+      (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \
+      (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \
+      (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+     } clipper_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg12_t f;
+} clipper_debug_reg12_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG13 struct
+ */
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000
+#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000
+
+#define CLIPPER_DEBUG_REG13_MASK \
+     (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \
+     ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \
+      (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \
+      (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \
+      (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+     } clipper_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg13_t f;
+} clipper_debug_reg13_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG0 struct
+ */
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4
+#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3
+#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0
+#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380
+#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000
+
+#define SXIFCCG_DEBUG_REG0_MASK \
+     (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \
+      SXIFCCG_DEBUG_REG0_position_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG0_point_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK)
+
+#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \
+     ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \
+      (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \
+      (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \
+      (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \
+      (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \
+      (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \
+      (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \
+      (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT))
+
+#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg0_t f;
+} sxifccg_debug_reg0_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG1 struct
+ */
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4
+#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c
+#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000
+#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000
+#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000
+
+#define SXIFCCG_DEBUG_REG1_MASK \
+     (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \
+      SXIFCCG_DEBUG_REG1_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \
+      SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG1_aux_sel_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \
+      SXIFCCG_DEBUG_REG1_param_cache_base_MASK)
+
+#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \
+     ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \
+      (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \
+      (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \
+      (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \
+      (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \
+      (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \
+      (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \
+      (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT))
+
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg1_t f;
+} sxifccg_debug_reg1_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG2 struct
+ */
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002
+#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8
+#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000
+
+#define SXIFCCG_DEBUG_REG2_MASK \
+     (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_aux_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK)
+
+#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \
+     ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \
+      (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \
+      (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \
+      (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \
+      (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \
+      (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \
+      (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \
+      (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \
+      (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \
+      (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT))
+
+#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg2_t f;
+} sxifccg_debug_reg2_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG3 struct
+ */
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4
+#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8
+#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010
+#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00
+#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define SXIFCCG_DEBUG_REG3_MASK \
+     (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG3_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG3_current_state_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK)
+
+#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \
+     ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \
+      (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \
+      (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \
+      (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \
+      (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \
+      (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \
+      (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \
+      (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT))
+
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg3_t f;
+} sxifccg_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG0 struct
+ */
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5
+#define SETUP_DEBUG_REG0_pmode_state_SIZE 6
+#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1
+#define SETUP_DEBUG_REG0_geom_enable_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1
+#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1
+#define SETUP_DEBUG_REG0_geom_busy_SIZE 1
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0
+#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5
+#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11
+#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13
+#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14
+#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15
+#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16
+#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17
+
+#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f
+#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0
+#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800
+#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000
+#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000
+#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000
+#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000
+#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000
+
+#define SETUP_DEBUG_REG0_MASK \
+     (SETUP_DEBUG_REG0_su_cntl_state_MASK | \
+      SETUP_DEBUG_REG0_pmode_state_MASK | \
+      SETUP_DEBUG_REG0_ge_stallb_MASK | \
+      SETUP_DEBUG_REG0_geom_enable_MASK | \
+      SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \
+      SETUP_DEBUG_REG0_su_clip_rtr_MASK | \
+      SETUP_DEBUG_REG0_pfifo_busy_MASK | \
+      SETUP_DEBUG_REG0_su_cntl_busy_MASK | \
+      SETUP_DEBUG_REG0_geom_busy_MASK)
+
+#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \
+     ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \
+      (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \
+      (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \
+      (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \
+      (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \
+      (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \
+      (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \
+      (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \
+      (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT))
+
+#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int                                : 14;
+     } setup_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int                                : 14;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+     } setup_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg0_t f;
+} setup_debug_reg0_u;
+
+
+/*
+ * SETUP_DEBUG_REG1 struct
+ */
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG1_MASK \
+     (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \
+      SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \
+     ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \
+      (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int                                : 4;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+     } setup_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg1_t f;
+} setup_debug_reg1_u;
+
+
+/*
+ * SETUP_DEBUG_REG2 struct
+ */
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG2_MASK \
+     (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \
+      SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \
+     ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \
+      (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int                                : 4;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+     } setup_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg2_t f;
+} setup_debug_reg2_u;
+
+
+/*
+ * SETUP_DEBUG_REG3 struct
+ */
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG3_MASK \
+     (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \
+      SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \
+     ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \
+      (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int                                : 4;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+     } setup_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg3_t f;
+} setup_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG4 struct
+ */
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11
+#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1
+#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3
+#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3
+#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2
+#define SETUP_DEBUG_REG4_type_gated_SIZE 3
+#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_event_gated_SIZE 1
+#define SETUP_DEBUG_REG4_eop_gated_SIZE 1
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0
+#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11
+#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12
+#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13
+#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17
+#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21
+#define SETUP_DEBUG_REG4_type_gated_SHIFT 23
+#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27
+#define SETUP_DEBUG_REG4_event_gated_SHIFT 28
+#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800
+#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000
+#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000
+#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000
+#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000
+#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000
+#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000
+#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000
+#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000
+#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000
+#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000
+
+#define SETUP_DEBUG_REG4_MASK \
+     (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \
+      SETUP_DEBUG_REG4_null_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_backfacing_gated_MASK | \
+      SETUP_DEBUG_REG4_st_indx_gated_MASK | \
+      SETUP_DEBUG_REG4_clipped_gated_MASK | \
+      SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \
+      SETUP_DEBUG_REG4_xmajor_gated_MASK | \
+      SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \
+      SETUP_DEBUG_REG4_type_gated_MASK | \
+      SETUP_DEBUG_REG4_fpov_gated_MASK | \
+      SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_event_gated_MASK | \
+      SETUP_DEBUG_REG4_eop_gated_MASK)
+
+#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \
+     ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \
+      (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \
+      (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \
+      (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \
+      (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \
+      (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \
+      (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \
+      (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \
+      (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \
+      (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \
+      (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \
+      (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \
+      (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT))
+
+#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int                                : 2;
+     } setup_debug_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int                                : 2;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+     } setup_debug_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg4_t f;
+} setup_debug_reg4_u;
+
+
+/*
+ * SETUP_DEBUG_REG5 struct
+ */
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2
+#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22
+#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000
+#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000
+
+#define SETUP_DEBUG_REG5_MASK \
+     (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \
+      SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \
+      SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \
+      SETUP_DEBUG_REG5_event_id_gated_MASK)
+
+#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \
+     ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \
+      (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \
+      (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \
+      (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT))
+
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int                                : 3;
+     } setup_debug_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int                                : 3;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+     } setup_debug_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg5_t f;
+} setup_debug_reg5_u;
+
+
+/*
+ * PA_SC_DEBUG_CNTL struct
+ */
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SC_DEBUG_CNTL_MASK \
+     (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK)
+
+#define PA_SC_DEBUG_CNTL(sc_debug_indx) \
+     ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT))
+
+#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \
+     ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \
+     pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_sc_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+     } pa_sc_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_cntl_t f;
+} pa_sc_debug_cntl_u;
+
+
+/*
+ * PA_SC_DEBUG_DATA struct
+ */
+
+#define PA_SC_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SC_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SC_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SC_DEBUG_DATA_MASK \
+     (PA_SC_DEBUG_DATA_DATA_MASK)
+
+#define PA_SC_DEBUG_DATA(data) \
+     ((data << PA_SC_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \
+     ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \
+     pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_data_t f;
+} pa_sc_debug_data_u;
+
+
+/*
+ * SC_DEBUG_0 struct
+ */
+
+#define SC_DEBUG_0_pa_freeze_b1_SIZE   1
+#define SC_DEBUG_0_pa_sc_valid_SIZE    1
+#define SC_DEBUG_0_pa_sc_phase_SIZE    3
+#define SC_DEBUG_0_cntx_cnt_SIZE       7
+#define SC_DEBUG_0_decr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_incr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_trigger_SIZE        1
+
+#define SC_DEBUG_0_pa_freeze_b1_SHIFT  0
+#define SC_DEBUG_0_pa_sc_valid_SHIFT   1
+#define SC_DEBUG_0_pa_sc_phase_SHIFT   2
+#define SC_DEBUG_0_cntx_cnt_SHIFT      5
+#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12
+#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13
+#define SC_DEBUG_0_trigger_SHIFT       31
+
+#define SC_DEBUG_0_pa_freeze_b1_MASK   0x00000001
+#define SC_DEBUG_0_pa_sc_valid_MASK    0x00000002
+#define SC_DEBUG_0_pa_sc_phase_MASK    0x0000001c
+#define SC_DEBUG_0_cntx_cnt_MASK       0x00000fe0
+#define SC_DEBUG_0_decr_cntx_cnt_MASK  0x00001000
+#define SC_DEBUG_0_incr_cntx_cnt_MASK  0x00002000
+#define SC_DEBUG_0_trigger_MASK        0x80000000
+
+#define SC_DEBUG_0_MASK \
+     (SC_DEBUG_0_pa_freeze_b1_MASK | \
+      SC_DEBUG_0_pa_sc_valid_MASK | \
+      SC_DEBUG_0_pa_sc_phase_MASK | \
+      SC_DEBUG_0_cntx_cnt_MASK | \
+      SC_DEBUG_0_decr_cntx_cnt_MASK | \
+      SC_DEBUG_0_incr_cntx_cnt_MASK | \
+      SC_DEBUG_0_trigger_MASK)
+
+#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \
+     ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \
+      (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \
+      (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \
+      (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \
+      (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \
+      (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \
+      (trigger << SC_DEBUG_0_trigger_SHIFT))
+
+#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_trigger(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT)
+
+#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int                                : 17;
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+     } sc_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+          unsigned int                                : 17;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+     } sc_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_0_t f;
+} sc_debug_0_u;
+
+
+/*
+ * SC_DEBUG_1 struct
+ */
+
+#define SC_DEBUG_1_em_state_SIZE       3
+#define SC_DEBUG_1_em1_data_ready_SIZE 1
+#define SC_DEBUG_1_em2_data_ready_SIZE 1
+#define SC_DEBUG_1_move_em1_to_em2_SIZE 1
+#define SC_DEBUG_1_ef_data_ready_SIZE  1
+#define SC_DEBUG_1_ef_state_SIZE       2
+#define SC_DEBUG_1_pipe_valid_SIZE     1
+#define SC_DEBUG_1_trigger_SIZE        1
+
+#define SC_DEBUG_1_em_state_SHIFT      0
+#define SC_DEBUG_1_em1_data_ready_SHIFT 3
+#define SC_DEBUG_1_em2_data_ready_SHIFT 4
+#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5
+#define SC_DEBUG_1_ef_data_ready_SHIFT 6
+#define SC_DEBUG_1_ef_state_SHIFT      7
+#define SC_DEBUG_1_pipe_valid_SHIFT    9
+#define SC_DEBUG_1_trigger_SHIFT       31
+
+#define SC_DEBUG_1_em_state_MASK       0x00000007
+#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008
+#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010
+#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020
+#define SC_DEBUG_1_ef_data_ready_MASK  0x00000040
+#define SC_DEBUG_1_ef_state_MASK       0x00000180
+#define SC_DEBUG_1_pipe_valid_MASK     0x00000200
+#define SC_DEBUG_1_trigger_MASK        0x80000000
+
+#define SC_DEBUG_1_MASK \
+     (SC_DEBUG_1_em_state_MASK | \
+      SC_DEBUG_1_em1_data_ready_MASK | \
+      SC_DEBUG_1_em2_data_ready_MASK | \
+      SC_DEBUG_1_move_em1_to_em2_MASK | \
+      SC_DEBUG_1_ef_data_ready_MASK | \
+      SC_DEBUG_1_ef_state_MASK | \
+      SC_DEBUG_1_pipe_valid_MASK | \
+      SC_DEBUG_1_trigger_MASK)
+
+#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \
+     ((em_state << SC_DEBUG_1_em_state_SHIFT) | \
+      (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \
+      (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \
+      (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \
+      (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \
+      (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \
+      (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \
+      (trigger << SC_DEBUG_1_trigger_SHIFT))
+
+#define SC_DEBUG_1_GET_em_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_GET_trigger(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT)
+
+#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int                                : 21;
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+     } sc_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+          unsigned int                                : 21;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+     } sc_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_1_t f;
+} sc_debug_1_u;
+
+
+/*
+ * SC_DEBUG_2 struct
+ */
+
+#define SC_DEBUG_2_rc_rtr_dly_SIZE     1
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1
+#define SC_DEBUG_2_pipe_freeze_b_SIZE  1
+#define SC_DEBUG_2_prim_rts_SIZE       1
+#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1
+#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1
+#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1
+#define SC_DEBUG_2_stage0_rts_SIZE     1
+#define SC_DEBUG_2_phase_rts_dly_SIZE  1
+#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1
+#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1
+#define SC_DEBUG_2_event_id_s1_SIZE    5
+#define SC_DEBUG_2_event_s1_SIZE       1
+#define SC_DEBUG_2_trigger_SIZE        1
+
+#define SC_DEBUG_2_rc_rtr_dly_SHIFT    0
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1
+#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3
+#define SC_DEBUG_2_prim_rts_SHIFT      4
+#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5
+#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6
+#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7
+#define SC_DEBUG_2_stage0_rts_SHIFT    8
+#define SC_DEBUG_2_phase_rts_dly_SHIFT 9
+#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15
+#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16
+#define SC_DEBUG_2_event_id_s1_SHIFT   17
+#define SC_DEBUG_2_event_s1_SHIFT      22
+#define SC_DEBUG_2_trigger_SHIFT       31
+
+#define SC_DEBUG_2_rc_rtr_dly_MASK     0x00000001
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002
+#define SC_DEBUG_2_pipe_freeze_b_MASK  0x00000008
+#define SC_DEBUG_2_prim_rts_MASK       0x00000010
+#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020
+#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040
+#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080
+#define SC_DEBUG_2_stage0_rts_MASK     0x00000100
+#define SC_DEBUG_2_phase_rts_dly_MASK  0x00000200
+#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000
+#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000
+#define SC_DEBUG_2_event_id_s1_MASK    0x003e0000
+#define SC_DEBUG_2_event_s1_MASK       0x00400000
+#define SC_DEBUG_2_trigger_MASK        0x80000000
+
+#define SC_DEBUG_2_MASK \
+     (SC_DEBUG_2_rc_rtr_dly_MASK | \
+      SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \
+      SC_DEBUG_2_pipe_freeze_b_MASK | \
+      SC_DEBUG_2_prim_rts_MASK | \
+      SC_DEBUG_2_next_prim_rts_dly_MASK | \
+      SC_DEBUG_2_next_prim_rtr_dly_MASK | \
+      SC_DEBUG_2_pre_stage1_rts_d1_MASK | \
+      SC_DEBUG_2_stage0_rts_MASK | \
+      SC_DEBUG_2_phase_rts_dly_MASK | \
+      SC_DEBUG_2_end_of_prim_s1_dly_MASK | \
+      SC_DEBUG_2_pass_empty_prim_s1_MASK | \
+      SC_DEBUG_2_event_id_s1_MASK | \
+      SC_DEBUG_2_event_s1_MASK | \
+      SC_DEBUG_2_trigger_MASK)
+
+#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \
+     ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \
+      (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \
+      (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \
+      (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \
+      (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \
+      (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \
+      (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \
+      (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \
+      (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \
+      (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \
+      (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \
+      (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \
+      (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \
+      (trigger << SC_DEBUG_2_trigger_SHIFT))
+
+#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_GET_trigger(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT)
+
+#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int                                : 1;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int                                : 8;
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+     } sc_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+          unsigned int                                : 8;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int                                : 1;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+     } sc_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_2_t f;
+} sc_debug_2_u;
+
+
+/*
+ * SC_DEBUG_3 struct
+ */
+
+#define SC_DEBUG_3_x_curr_s1_SIZE      11
+#define SC_DEBUG_3_y_curr_s1_SIZE      11
+#define SC_DEBUG_3_trigger_SIZE        1
+
+#define SC_DEBUG_3_x_curr_s1_SHIFT     0
+#define SC_DEBUG_3_y_curr_s1_SHIFT     11
+#define SC_DEBUG_3_trigger_SHIFT       31
+
+#define SC_DEBUG_3_x_curr_s1_MASK      0x000007ff
+#define SC_DEBUG_3_y_curr_s1_MASK      0x003ff800
+#define SC_DEBUG_3_trigger_MASK        0x80000000
+
+#define SC_DEBUG_3_MASK \
+     (SC_DEBUG_3_x_curr_s1_MASK | \
+      SC_DEBUG_3_y_curr_s1_MASK | \
+      SC_DEBUG_3_trigger_MASK)
+
+#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \
+     ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \
+      (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \
+      (trigger << SC_DEBUG_3_trigger_SHIFT))
+
+#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_trigger(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT)
+
+#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int                                : 9;
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+     } sc_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+          unsigned int                                : 9;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+     } sc_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_3_t f;
+} sc_debug_3_u;
+
+
+/*
+ * SC_DEBUG_4 struct
+ */
+
+#define SC_DEBUG_4_y_end_s1_SIZE       14
+#define SC_DEBUG_4_y_start_s1_SIZE     14
+#define SC_DEBUG_4_y_dir_s1_SIZE       1
+#define SC_DEBUG_4_trigger_SIZE        1
+
+#define SC_DEBUG_4_y_end_s1_SHIFT      0
+#define SC_DEBUG_4_y_start_s1_SHIFT    14
+#define SC_DEBUG_4_y_dir_s1_SHIFT      28
+#define SC_DEBUG_4_trigger_SHIFT       31
+
+#define SC_DEBUG_4_y_end_s1_MASK       0x00003fff
+#define SC_DEBUG_4_y_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_4_y_dir_s1_MASK       0x10000000
+#define SC_DEBUG_4_trigger_MASK        0x80000000
+
+#define SC_DEBUG_4_MASK \
+     (SC_DEBUG_4_y_end_s1_MASK | \
+      SC_DEBUG_4_y_start_s1_MASK | \
+      SC_DEBUG_4_y_dir_s1_MASK | \
+      SC_DEBUG_4_trigger_MASK)
+
+#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \
+     ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \
+      (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \
+      (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_4_trigger_SHIFT))
+
+#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_GET_trigger(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT)
+
+#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+     } sc_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+     } sc_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_4_t f;
+} sc_debug_4_u;
+
+
+/*
+ * SC_DEBUG_5 struct
+ */
+
+#define SC_DEBUG_5_x_end_s1_SIZE       14
+#define SC_DEBUG_5_x_start_s1_SIZE     14
+#define SC_DEBUG_5_x_dir_s1_SIZE       1
+#define SC_DEBUG_5_trigger_SIZE        1
+
+#define SC_DEBUG_5_x_end_s1_SHIFT      0
+#define SC_DEBUG_5_x_start_s1_SHIFT    14
+#define SC_DEBUG_5_x_dir_s1_SHIFT      28
+#define SC_DEBUG_5_trigger_SHIFT       31
+
+#define SC_DEBUG_5_x_end_s1_MASK       0x00003fff
+#define SC_DEBUG_5_x_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_5_x_dir_s1_MASK       0x10000000
+#define SC_DEBUG_5_trigger_MASK        0x80000000
+
+#define SC_DEBUG_5_MASK \
+     (SC_DEBUG_5_x_end_s1_MASK | \
+      SC_DEBUG_5_x_start_s1_MASK | \
+      SC_DEBUG_5_x_dir_s1_MASK | \
+      SC_DEBUG_5_trigger_MASK)
+
+#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \
+     ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \
+      (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \
+      (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_5_trigger_SHIFT))
+
+#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_GET_trigger(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT)
+
+#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+     } sc_debug_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+     } sc_debug_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_5_t f;
+} sc_debug_5_u;
+
+
+/*
+ * SC_DEBUG_6 struct
+ */
+
+#define SC_DEBUG_6_z_ff_empty_SIZE     1
+#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1
+#define SC_DEBUG_6_xy_ff_empty_SIZE    1
+#define SC_DEBUG_6_event_flag_SIZE     1
+#define SC_DEBUG_6_z_mask_needed_SIZE  1
+#define SC_DEBUG_6_state_SIZE          3
+#define SC_DEBUG_6_state_delayed_SIZE  3
+#define SC_DEBUG_6_data_valid_SIZE     1
+#define SC_DEBUG_6_data_valid_d_SIZE   1
+#define SC_DEBUG_6_tilex_delayed_SIZE  9
+#define SC_DEBUG_6_tiley_delayed_SIZE  9
+#define SC_DEBUG_6_trigger_SIZE        1
+
+#define SC_DEBUG_6_z_ff_empty_SHIFT    0
+#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1
+#define SC_DEBUG_6_xy_ff_empty_SHIFT   2
+#define SC_DEBUG_6_event_flag_SHIFT    3
+#define SC_DEBUG_6_z_mask_needed_SHIFT 4
+#define SC_DEBUG_6_state_SHIFT         5
+#define SC_DEBUG_6_state_delayed_SHIFT 8
+#define SC_DEBUG_6_data_valid_SHIFT    11
+#define SC_DEBUG_6_data_valid_d_SHIFT  12
+#define SC_DEBUG_6_tilex_delayed_SHIFT 13
+#define SC_DEBUG_6_tiley_delayed_SHIFT 22
+#define SC_DEBUG_6_trigger_SHIFT       31
+
+#define SC_DEBUG_6_z_ff_empty_MASK     0x00000001
+#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002
+#define SC_DEBUG_6_xy_ff_empty_MASK    0x00000004
+#define SC_DEBUG_6_event_flag_MASK     0x00000008
+#define SC_DEBUG_6_z_mask_needed_MASK  0x00000010
+#define SC_DEBUG_6_state_MASK          0x000000e0
+#define SC_DEBUG_6_state_delayed_MASK  0x00000700
+#define SC_DEBUG_6_data_valid_MASK     0x00000800
+#define SC_DEBUG_6_data_valid_d_MASK   0x00001000
+#define SC_DEBUG_6_tilex_delayed_MASK  0x003fe000
+#define SC_DEBUG_6_tiley_delayed_MASK  0x7fc00000
+#define SC_DEBUG_6_trigger_MASK        0x80000000
+
+#define SC_DEBUG_6_MASK \
+     (SC_DEBUG_6_z_ff_empty_MASK | \
+      SC_DEBUG_6_qmcntl_ff_empty_MASK | \
+      SC_DEBUG_6_xy_ff_empty_MASK | \
+      SC_DEBUG_6_event_flag_MASK | \
+      SC_DEBUG_6_z_mask_needed_MASK | \
+      SC_DEBUG_6_state_MASK | \
+      SC_DEBUG_6_state_delayed_MASK | \
+      SC_DEBUG_6_data_valid_MASK | \
+      SC_DEBUG_6_data_valid_d_MASK | \
+      SC_DEBUG_6_tilex_delayed_MASK | \
+      SC_DEBUG_6_tiley_delayed_MASK | \
+      SC_DEBUG_6_trigger_MASK)
+
+#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \
+     ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \
+      (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \
+      (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \
+      (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \
+      (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \
+      (state << SC_DEBUG_6_state_SHIFT) | \
+      (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \
+      (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \
+      (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \
+      (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \
+      (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \
+      (trigger << SC_DEBUG_6_trigger_SHIFT))
+
+#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_GET_state(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_GET_trigger(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT)
+
+#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+     } sc_debug_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+     } sc_debug_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_6_t f;
+} sc_debug_6_u;
+
+
+/*
+ * SC_DEBUG_7 struct
+ */
+
+#define SC_DEBUG_7_event_flag_SIZE     1
+#define SC_DEBUG_7_deallocate_SIZE     3
+#define SC_DEBUG_7_fposition_SIZE      1
+#define SC_DEBUG_7_sr_prim_we_SIZE     1
+#define SC_DEBUG_7_last_tile_SIZE      1
+#define SC_DEBUG_7_tile_ff_we_SIZE     1
+#define SC_DEBUG_7_qs_data_valid_SIZE  1
+#define SC_DEBUG_7_qs_q0_y_SIZE        2
+#define SC_DEBUG_7_qs_q0_x_SIZE        2
+#define SC_DEBUG_7_qs_q0_valid_SIZE    1
+#define SC_DEBUG_7_prim_ff_we_SIZE     1
+#define SC_DEBUG_7_tile_ff_re_SIZE     1
+#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_7_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_7_new_prim_SIZE       1
+#define SC_DEBUG_7_load_new_tile_data_SIZE 1
+#define SC_DEBUG_7_state_SIZE          2
+#define SC_DEBUG_7_fifos_ready_SIZE    1
+#define SC_DEBUG_7_trigger_SIZE        1
+
+#define SC_DEBUG_7_event_flag_SHIFT    0
+#define SC_DEBUG_7_deallocate_SHIFT    1
+#define SC_DEBUG_7_fposition_SHIFT     4
+#define SC_DEBUG_7_sr_prim_we_SHIFT    5
+#define SC_DEBUG_7_last_tile_SHIFT     6
+#define SC_DEBUG_7_tile_ff_we_SHIFT    7
+#define SC_DEBUG_7_qs_data_valid_SHIFT 8
+#define SC_DEBUG_7_qs_q0_y_SHIFT       9
+#define SC_DEBUG_7_qs_q0_x_SHIFT       11
+#define SC_DEBUG_7_qs_q0_valid_SHIFT   13
+#define SC_DEBUG_7_prim_ff_we_SHIFT    14
+#define SC_DEBUG_7_tile_ff_re_SHIFT    15
+#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16
+#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17
+#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18
+#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19
+#define SC_DEBUG_7_new_prim_SHIFT      20
+#define SC_DEBUG_7_load_new_tile_data_SHIFT 21
+#define SC_DEBUG_7_state_SHIFT         22
+#define SC_DEBUG_7_fifos_ready_SHIFT   24
+#define SC_DEBUG_7_trigger_SHIFT       31
+
+#define SC_DEBUG_7_event_flag_MASK     0x00000001
+#define SC_DEBUG_7_deallocate_MASK     0x0000000e
+#define SC_DEBUG_7_fposition_MASK      0x00000010
+#define SC_DEBUG_7_sr_prim_we_MASK     0x00000020
+#define SC_DEBUG_7_last_tile_MASK      0x00000040
+#define SC_DEBUG_7_tile_ff_we_MASK     0x00000080
+#define SC_DEBUG_7_qs_data_valid_MASK  0x00000100
+#define SC_DEBUG_7_qs_q0_y_MASK        0x00000600
+#define SC_DEBUG_7_qs_q0_x_MASK        0x00001800
+#define SC_DEBUG_7_qs_q0_valid_MASK    0x00002000
+#define SC_DEBUG_7_prim_ff_we_MASK     0x00004000
+#define SC_DEBUG_7_tile_ff_re_MASK     0x00008000
+#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000
+#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000
+#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000
+#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000
+#define SC_DEBUG_7_new_prim_MASK       0x00100000
+#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000
+#define SC_DEBUG_7_state_MASK          0x00c00000
+#define SC_DEBUG_7_fifos_ready_MASK    0x01000000
+#define SC_DEBUG_7_trigger_MASK        0x80000000
+
+#define SC_DEBUG_7_MASK \
+     (SC_DEBUG_7_event_flag_MASK | \
+      SC_DEBUG_7_deallocate_MASK | \
+      SC_DEBUG_7_fposition_MASK | \
+      SC_DEBUG_7_sr_prim_we_MASK | \
+      SC_DEBUG_7_last_tile_MASK | \
+      SC_DEBUG_7_tile_ff_we_MASK | \
+      SC_DEBUG_7_qs_data_valid_MASK | \
+      SC_DEBUG_7_qs_q0_y_MASK | \
+      SC_DEBUG_7_qs_q0_x_MASK | \
+      SC_DEBUG_7_qs_q0_valid_MASK | \
+      SC_DEBUG_7_prim_ff_we_MASK | \
+      SC_DEBUG_7_tile_ff_re_MASK | \
+      SC_DEBUG_7_fw_prim_data_valid_MASK | \
+      SC_DEBUG_7_last_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_prim_MASK | \
+      SC_DEBUG_7_new_prim_MASK | \
+      SC_DEBUG_7_load_new_tile_data_MASK | \
+      SC_DEBUG_7_state_MASK | \
+      SC_DEBUG_7_fifos_ready_MASK | \
+      SC_DEBUG_7_trigger_MASK)
+
+#define SC_DEBUG_7(event_flag, deallocate, fposition, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \
+     ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \
+      (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \
+      (fposition << SC_DEBUG_7_fposition_SHIFT) | \
+      (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \
+      (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \
+      (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \
+      (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \
+      (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \
+      (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \
+      (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \
+      (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \
+      (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \
+      (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \
+      (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \
+      (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \
+      (state << SC_DEBUG_7_state_SHIFT) | \
+      (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \
+      (trigger << SC_DEBUG_7_trigger_SHIFT))
+
+#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_GET_fposition(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fposition_MASK) >> SC_DEBUG_7_fposition_SHIFT)
+#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_GET_state(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_GET_trigger(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT)
+
+#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_SET_fposition(sc_debug_7_reg, fposition) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fposition_MASK) | (fposition << SC_DEBUG_7_fposition_SHIFT)
+#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int fposition                      : SC_DEBUG_7_fposition_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int                                : 6;
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+     } sc_debug_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+          unsigned int                                : 6;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int fposition                      : SC_DEBUG_7_fposition_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+     } sc_debug_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_7_t f;
+} sc_debug_7_u;
+
+
+/*
+ * SC_DEBUG_8 struct
+ */
+
+#define SC_DEBUG_8_sample_last_SIZE    1
+#define SC_DEBUG_8_sample_mask_SIZE    4
+#define SC_DEBUG_8_sample_y_SIZE       2
+#define SC_DEBUG_8_sample_x_SIZE       2
+#define SC_DEBUG_8_sample_send_SIZE    1
+#define SC_DEBUG_8_next_cycle_SIZE     2
+#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1
+#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1
+#define SC_DEBUG_8_num_samples_SIZE    2
+#define SC_DEBUG_8_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_8_last_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_sample_we_SIZE      1
+#define SC_DEBUG_8_fposition_SIZE      1
+#define SC_DEBUG_8_event_id_SIZE       5
+#define SC_DEBUG_8_event_flag_SIZE     1
+#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_8_trigger_SIZE        1
+
+#define SC_DEBUG_8_sample_last_SHIFT   0
+#define SC_DEBUG_8_sample_mask_SHIFT   1
+#define SC_DEBUG_8_sample_y_SHIFT      5
+#define SC_DEBUG_8_sample_x_SHIFT      7
+#define SC_DEBUG_8_sample_send_SHIFT   9
+#define SC_DEBUG_8_next_cycle_SHIFT    10
+#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12
+#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13
+#define SC_DEBUG_8_num_samples_SHIFT   14
+#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16
+#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17
+#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18
+#define SC_DEBUG_8_sample_we_SHIFT     19
+#define SC_DEBUG_8_fposition_SHIFT     20
+#define SC_DEBUG_8_event_id_SHIFT      21
+#define SC_DEBUG_8_event_flag_SHIFT    26
+#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27
+#define SC_DEBUG_8_trigger_SHIFT       31
+
+#define SC_DEBUG_8_sample_last_MASK    0x00000001
+#define SC_DEBUG_8_sample_mask_MASK    0x0000001e
+#define SC_DEBUG_8_sample_y_MASK       0x00000060
+#define SC_DEBUG_8_sample_x_MASK       0x00000180
+#define SC_DEBUG_8_sample_send_MASK    0x00000200
+#define SC_DEBUG_8_next_cycle_MASK     0x00000c00
+#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000
+#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000
+#define SC_DEBUG_8_num_samples_MASK    0x0000c000
+#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000
+#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000
+#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000
+#define SC_DEBUG_8_sample_we_MASK      0x00080000
+#define SC_DEBUG_8_fposition_MASK      0x00100000
+#define SC_DEBUG_8_event_id_MASK       0x03e00000
+#define SC_DEBUG_8_event_flag_MASK     0x04000000
+#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000
+#define SC_DEBUG_8_trigger_MASK        0x80000000
+
+#define SC_DEBUG_8_MASK \
+     (SC_DEBUG_8_sample_last_MASK | \
+      SC_DEBUG_8_sample_mask_MASK | \
+      SC_DEBUG_8_sample_y_MASK | \
+      SC_DEBUG_8_sample_x_MASK | \
+      SC_DEBUG_8_sample_send_MASK | \
+      SC_DEBUG_8_next_cycle_MASK | \
+      SC_DEBUG_8_ez_sample_ff_full_MASK | \
+      SC_DEBUG_8_rb_sc_samp_rtr_MASK | \
+      SC_DEBUG_8_num_samples_MASK | \
+      SC_DEBUG_8_last_quad_of_tile_MASK | \
+      SC_DEBUG_8_last_quad_of_prim_MASK | \
+      SC_DEBUG_8_first_quad_of_prim_MASK | \
+      SC_DEBUG_8_sample_we_MASK | \
+      SC_DEBUG_8_fposition_MASK | \
+      SC_DEBUG_8_event_id_MASK | \
+      SC_DEBUG_8_event_flag_MASK | \
+      SC_DEBUG_8_fw_prim_data_valid_MASK | \
+      SC_DEBUG_8_trigger_MASK)
+
+#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fposition, event_id, event_flag, fw_prim_data_valid, trigger) \
+     ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \
+      (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \
+      (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \
+      (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \
+      (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \
+      (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \
+      (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \
+      (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \
+      (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \
+      (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \
+      (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \
+      (fposition << SC_DEBUG_8_fposition_SHIFT) | \
+      (event_id << SC_DEBUG_8_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \
+      (trigger << SC_DEBUG_8_trigger_SHIFT))
+
+#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_GET_fposition(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fposition_MASK) >> SC_DEBUG_8_fposition_SHIFT)
+#define SC_DEBUG_8_GET_event_id(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_GET_trigger(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT)
+
+#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_SET_fposition(sc_debug_8_reg, fposition) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fposition_MASK) | (fposition << SC_DEBUG_8_fposition_SHIFT)
+#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int fposition                      : SC_DEBUG_8_fposition_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int                                : 3;
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+     } sc_debug_8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int fposition                      : SC_DEBUG_8_fposition_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+     } sc_debug_8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_8_t f;
+} sc_debug_8_u;
+
+
+/*
+ * SC_DEBUG_9 struct
+ */
+
+#define SC_DEBUG_9_rb_sc_send_SIZE     1
+#define SC_DEBUG_9_rb_sc_ez_mask_SIZE  4
+#define SC_DEBUG_9_fifo_data_ready_SIZE 1
+#define SC_DEBUG_9_early_z_enable_SIZE 1
+#define SC_DEBUG_9_mask_state_SIZE     2
+#define SC_DEBUG_9_next_ez_mask_SIZE   16
+#define SC_DEBUG_9_mask_ready_SIZE     1
+#define SC_DEBUG_9_drop_sample_SIZE    1
+#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_9_trigger_SIZE        1
+
+#define SC_DEBUG_9_rb_sc_send_SHIFT    0
+#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1
+#define SC_DEBUG_9_fifo_data_ready_SHIFT 5
+#define SC_DEBUG_9_early_z_enable_SHIFT 6
+#define SC_DEBUG_9_mask_state_SHIFT    7
+#define SC_DEBUG_9_next_ez_mask_SHIFT  9
+#define SC_DEBUG_9_mask_ready_SHIFT    25
+#define SC_DEBUG_9_drop_sample_SHIFT   26
+#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30
+#define SC_DEBUG_9_trigger_SHIFT       31
+
+#define SC_DEBUG_9_rb_sc_send_MASK     0x00000001
+#define SC_DEBUG_9_rb_sc_ez_mask_MASK  0x0000001e
+#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020
+#define SC_DEBUG_9_early_z_enable_MASK 0x00000040
+#define SC_DEBUG_9_mask_state_MASK     0x00000180
+#define SC_DEBUG_9_next_ez_mask_MASK   0x01fffe00
+#define SC_DEBUG_9_mask_ready_MASK     0x02000000
+#define SC_DEBUG_9_drop_sample_MASK    0x04000000
+#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000
+#define SC_DEBUG_9_trigger_MASK        0x80000000
+
+#define SC_DEBUG_9_MASK \
+     (SC_DEBUG_9_rb_sc_send_MASK | \
+      SC_DEBUG_9_rb_sc_ez_mask_MASK | \
+      SC_DEBUG_9_fifo_data_ready_MASK | \
+      SC_DEBUG_9_early_z_enable_MASK | \
+      SC_DEBUG_9_mask_state_MASK | \
+      SC_DEBUG_9_next_ez_mask_MASK | \
+      SC_DEBUG_9_mask_ready_MASK | \
+      SC_DEBUG_9_drop_sample_MASK | \
+      SC_DEBUG_9_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_9_trigger_MASK)
+
+#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \
+     ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \
+      (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \
+      (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \
+      (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \
+      (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \
+      (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \
+      (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \
+      (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \
+      (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \
+      (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \
+      (trigger << SC_DEBUG_9_trigger_SHIFT))
+
+#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_GET_trigger(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT)
+
+#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+     } sc_debug_9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+     } sc_debug_9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_9_t f;
+} sc_debug_9_u;
+
+
+/*
+ * SC_DEBUG_10 struct
+ */
+
+#define SC_DEBUG_10_combined_sample_mask_SIZE 16
+#define SC_DEBUG_10_trigger_SIZE       1
+
+#define SC_DEBUG_10_combined_sample_mask_SHIFT 0
+#define SC_DEBUG_10_trigger_SHIFT      31
+
+#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff
+#define SC_DEBUG_10_trigger_MASK       0x80000000
+
+#define SC_DEBUG_10_MASK \
+     (SC_DEBUG_10_combined_sample_mask_MASK | \
+      SC_DEBUG_10_trigger_MASK)
+
+#define SC_DEBUG_10(combined_sample_mask, trigger) \
+     ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \
+      (trigger << SC_DEBUG_10_trigger_SHIFT))
+
+#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_GET_trigger(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT)
+
+#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+          unsigned int                                : 15;
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+     } sc_debug_10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+          unsigned int                                : 15;
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+     } sc_debug_10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_10_t f;
+} sc_debug_10_u;
+
+
+/*
+ * SC_DEBUG_11 struct
+ */
+
+#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_11_iterator_input_fz_SIZE 1
+#define SC_DEBUG_11_packer_send_quads_SIZE 1
+#define SC_DEBUG_11_packer_send_cmd_SIZE 1
+#define SC_DEBUG_11_packer_send_event_SIZE 1
+#define SC_DEBUG_11_next_state_SIZE    3
+#define SC_DEBUG_11_state_SIZE         3
+#define SC_DEBUG_11_stall_SIZE         1
+#define SC_DEBUG_11_trigger_SIZE       1
+
+#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1
+#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3
+#define SC_DEBUG_11_iterator_input_fz_SHIFT 4
+#define SC_DEBUG_11_packer_send_quads_SHIFT 5
+#define SC_DEBUG_11_packer_send_cmd_SHIFT 6
+#define SC_DEBUG_11_packer_send_event_SHIFT 7
+#define SC_DEBUG_11_next_state_SHIFT   8
+#define SC_DEBUG_11_state_SHIFT        11
+#define SC_DEBUG_11_stall_SHIFT        14
+#define SC_DEBUG_11_trigger_SHIFT      31
+
+#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002
+#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008
+#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010
+#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020
+#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040
+#define SC_DEBUG_11_packer_send_event_MASK 0x00000080
+#define SC_DEBUG_11_next_state_MASK    0x00000700
+#define SC_DEBUG_11_state_MASK         0x00003800
+#define SC_DEBUG_11_stall_MASK         0x00004000
+#define SC_DEBUG_11_trigger_MASK       0x80000000
+
+#define SC_DEBUG_11_MASK \
+     (SC_DEBUG_11_ez_sample_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_11_ez_prim_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_11_iterator_input_fz_MASK | \
+      SC_DEBUG_11_packer_send_quads_MASK | \
+      SC_DEBUG_11_packer_send_cmd_MASK | \
+      SC_DEBUG_11_packer_send_event_MASK | \
+      SC_DEBUG_11_next_state_MASK | \
+      SC_DEBUG_11_state_MASK | \
+      SC_DEBUG_11_stall_MASK | \
+      SC_DEBUG_11_trigger_MASK)
+
+#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \
+     ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \
+      (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \
+      (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \
+      (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \
+      (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \
+      (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \
+      (next_state << SC_DEBUG_11_next_state_SHIFT) | \
+      (state << SC_DEBUG_11_state_SHIFT) | \
+      (stall << SC_DEBUG_11_stall_SHIFT) | \
+      (trigger << SC_DEBUG_11_trigger_SHIFT))
+
+#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_GET_next_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_GET_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_GET_stall(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_GET_trigger(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT)
+
+#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int                                : 16;
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+     } sc_debug_11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+          unsigned int                                : 16;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+     } sc_debug_11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_11_t f;
+} sc_debug_11_u;
+
+
+/*
+ * SC_DEBUG_12 struct
+ */
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1
+#define SC_DEBUG_12_event_id_SIZE      5
+#define SC_DEBUG_12_event_flag_SIZE    1
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_full_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1
+#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1
+#define SC_DEBUG_12_iter_qdhit0_SIZE   1
+#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1
+#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1
+#define SC_DEBUG_12_iter_phase_out_SIZE 2
+#define SC_DEBUG_12_iter_phase_reg_SIZE 2
+#define SC_DEBUG_12_iterator_SP_valid_SIZE 1
+#define SC_DEBUG_12_eopv_reg_SIZE      1
+#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1
+#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1
+#define SC_DEBUG_12_trigger_SIZE       1
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0
+#define SC_DEBUG_12_event_id_SHIFT     1
+#define SC_DEBUG_12_event_flag_SHIFT   6
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7
+#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8
+#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9
+#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11
+#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12
+#define SC_DEBUG_12_iter_qdhit0_SHIFT  13
+#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14
+#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15
+#define SC_DEBUG_12_iter_phase_out_SHIFT 16
+#define SC_DEBUG_12_iter_phase_reg_SHIFT 18
+#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20
+#define SC_DEBUG_12_eopv_reg_SHIFT     21
+#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22
+#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23
+#define SC_DEBUG_12_trigger_SHIFT      31
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001
+#define SC_DEBUG_12_event_id_MASK      0x0000003e
+#define SC_DEBUG_12_event_flag_MASK    0x00000040
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080
+#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100
+#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200
+#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400
+#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800
+#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000
+#define SC_DEBUG_12_iter_qdhit0_MASK   0x00002000
+#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000
+#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000
+#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000
+#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000
+#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000
+#define SC_DEBUG_12_eopv_reg_MASK      0x00200000
+#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000
+#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000
+#define SC_DEBUG_12_trigger_MASK       0x80000000
+
+#define SC_DEBUG_12_MASK \
+     (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \
+      SC_DEBUG_12_event_id_MASK | \
+      SC_DEBUG_12_event_flag_MASK | \
+      SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \
+      SC_DEBUG_12_itercmdfifo_full_MASK | \
+      SC_DEBUG_12_itercmdfifo_empty_MASK | \
+      SC_DEBUG_12_iter_ds_one_clk_command_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_vector_MASK | \
+      SC_DEBUG_12_iter_qdhit0_MASK | \
+      SC_DEBUG_12_bc_use_centers_reg_MASK | \
+      SC_DEBUG_12_bc_output_xy_reg_MASK | \
+      SC_DEBUG_12_iter_phase_out_MASK | \
+      SC_DEBUG_12_iter_phase_reg_MASK | \
+      SC_DEBUG_12_iterator_SP_valid_MASK | \
+      SC_DEBUG_12_eopv_reg_MASK | \
+      SC_DEBUG_12_one_clk_cmd_reg_MASK | \
+      SC_DEBUG_12_iter_dx_end_of_prim_MASK | \
+      SC_DEBUG_12_trigger_MASK)
+
+#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \
+     ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \
+      (event_id << SC_DEBUG_12_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \
+      (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \
+      (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \
+      (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \
+      (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \
+      (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \
+      (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \
+      (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \
+      (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \
+      (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \
+      (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \
+      (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \
+      (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \
+      (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \
+      (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \
+      (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \
+      (trigger << SC_DEBUG_12_trigger_SHIFT))
+
+#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_GET_event_id(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_GET_trigger(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT)
+
+#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int                                : 7;
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+     } sc_debug_12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+          unsigned int                                : 7;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+     } sc_debug_12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_12_t f;
+} sc_debug_12_u;
+
+
+#endif
+
+
+#if !defined (_VGT_FIDDLE_H)
+#define _VGT_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  vgt_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+/*
+ * VGT_OUT_PRIM_TYPE enum
+ */
+
+#define VGT_OUT_POINT                  0x00000000
+#define VGT_OUT_LINE                   0x00000001
+#define VGT_OUT_TRI                    0x00000002
+#define VGT_OUT_RECT_V0                0x00000003
+#define VGT_OUT_RECT_V1                0x00000004
+#define VGT_OUT_RECT_V2                0x00000005
+#define VGT_OUT_RECT_V3                0x00000006
+#define VGT_OUT_RESERVED               0x00000007
+#define VGT_TE_QUAD                    0x00000008
+#define VGT_TE_PRIM_INDEX_LINE         0x00000009
+#define VGT_TE_PRIM_INDEX_TRI          0x0000000a
+#define VGT_TE_PRIM_INDEX_QUAD         0x0000000b
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * GFX_COPY_STATE struct
+ */
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0
+
+#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+
+#define GFX_COPY_STATE_MASK \
+     (GFX_COPY_STATE_SRC_STATE_ID_MASK)
+
+#define GFX_COPY_STATE(src_state_id) \
+     ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT))
+
+#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \
+     ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \
+     gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 31;
+     } gfx_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int                                : 31;
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+     } gfx_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gfx_copy_state_t f;
+} gfx_copy_state_u;
+
+
+/*
+ * VGT_DRAW_INITIATOR struct
+ */
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1
+#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT 8
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11
+#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK 0x00000300
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800
+#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000
+#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000
+
+#define VGT_DRAW_INITIATOR_MASK \
+     (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \
+      VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \
+      VGT_DRAW_INITIATOR_NOT_EOP_MASK | \
+      VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \
+      VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_NUM_INDICES_MASK)
+
+#define VGT_DRAW_INITIATOR(prim_type, source_select, faceness_cull_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \
+     ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \
+      (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \
+      (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) | \
+      (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \
+      (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \
+      (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \
+      (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \
+      (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \
+      (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT))
+
+#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_FACENESS_CULL_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) >> VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_FACENESS_CULL_SELECT(vgt_draw_initiator_reg, faceness_cull_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) | (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int faceness_cull_select           : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+     } vgt_draw_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int faceness_cull_select           : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+     } vgt_draw_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_draw_initiator_t f;
+} vgt_draw_initiator_u;
+
+
+/*
+ * VGT_EVENT_INITIATOR struct
+ */
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f
+
+#define VGT_EVENT_INITIATOR_MASK \
+     (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK)
+
+#define VGT_EVENT_INITIATOR(event_type) \
+     ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT))
+
+#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \
+     ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \
+     vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+          unsigned int                                : 26;
+     } vgt_event_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int                                : 26;
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+     } vgt_event_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_event_initiator_t f;
+} vgt_event_initiator_u;
+
+
+/*
+ * VGT_DMA_BASE struct
+ */
+
+#define VGT_DMA_BASE_BASE_ADDR_SIZE    32
+
+#define VGT_DMA_BASE_BASE_ADDR_SHIFT   0
+
+#define VGT_DMA_BASE_BASE_ADDR_MASK    0xffffffff
+
+#define VGT_DMA_BASE_MASK \
+     (VGT_DMA_BASE_BASE_ADDR_MASK)
+
+#define VGT_DMA_BASE(base_addr) \
+     ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT))
+
+#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \
+     ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \
+     vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_base_t f;
+} vgt_dma_base_u;
+
+
+/*
+ * VGT_DMA_SIZE struct
+ */
+
+#define VGT_DMA_SIZE_NUM_WORDS_SIZE    24
+#define VGT_DMA_SIZE_SWAP_MODE_SIZE    2
+
+#define VGT_DMA_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_DMA_SIZE_SWAP_MODE_SHIFT   30
+
+#define VGT_DMA_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_DMA_SIZE_SWAP_MODE_MASK    0xc0000000
+
+#define VGT_DMA_SIZE_MASK \
+     (VGT_DMA_SIZE_NUM_WORDS_MASK | \
+      VGT_DMA_SIZE_SWAP_MODE_MASK)
+
+#define VGT_DMA_SIZE(num_words, swap_mode) \
+     ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \
+      (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT))
+
+#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+     } vgt_dma_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+     } vgt_dma_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_size_t f;
+} vgt_dma_size_u;
+
+
+/*
+ * VGT_BIN_BASE struct
+ */
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff
+
+#define VGT_BIN_BASE_MASK \
+     (VGT_BIN_BASE_BIN_BASE_ADDR_MASK)
+
+#define VGT_BIN_BASE(bin_base_addr) \
+     ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT))
+
+#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \
+     ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \
+     vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_base_t f;
+} vgt_bin_base_u;
+
+
+/*
+ * VGT_BIN_SIZE struct
+ */
+
+#define VGT_BIN_SIZE_NUM_WORDS_SIZE    24
+#define VGT_BIN_SIZE_FACENESS_FETCH_SIZE 1
+#define VGT_BIN_SIZE_FACENESS_RESET_SIZE 1
+
+#define VGT_BIN_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_BIN_SIZE_FACENESS_FETCH_SHIFT 30
+#define VGT_BIN_SIZE_FACENESS_RESET_SHIFT 31
+
+#define VGT_BIN_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_BIN_SIZE_FACENESS_FETCH_MASK 0x40000000
+#define VGT_BIN_SIZE_FACENESS_RESET_MASK 0x80000000
+
+#define VGT_BIN_SIZE_MASK \
+     (VGT_BIN_SIZE_NUM_WORDS_MASK | \
+      VGT_BIN_SIZE_FACENESS_FETCH_MASK | \
+      VGT_BIN_SIZE_FACENESS_RESET_MASK)
+
+#define VGT_BIN_SIZE(num_words, faceness_fetch, faceness_reset) \
+     ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) | \
+      (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) | \
+      (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT))
+
+#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+#define VGT_BIN_SIZE_GET_FACENESS_FETCH(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_FETCH_MASK) >> VGT_BIN_SIZE_FACENESS_FETCH_SHIFT)
+#define VGT_BIN_SIZE_GET_FACENESS_RESET(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_RESET_MASK) >> VGT_BIN_SIZE_FACENESS_RESET_SHIFT)
+
+#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+#define VGT_BIN_SIZE_SET_FACENESS_FETCH(vgt_bin_size_reg, faceness_fetch) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_FETCH_MASK) | (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT)
+#define VGT_BIN_SIZE_SET_FACENESS_RESET(vgt_bin_size_reg, faceness_reset) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_RESET_MASK) | (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int faceness_fetch                 : VGT_BIN_SIZE_FACENESS_FETCH_SIZE;
+          unsigned int faceness_reset                 : VGT_BIN_SIZE_FACENESS_RESET_SIZE;
+     } vgt_bin_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int faceness_reset                 : VGT_BIN_SIZE_FACENESS_RESET_SIZE;
+          unsigned int faceness_fetch                 : VGT_BIN_SIZE_FACENESS_FETCH_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+     } vgt_bin_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_size_t f;
+} vgt_bin_size_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MIN struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MIN_MASK \
+     (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_min_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+     } vgt_current_bin_id_min_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_min_t f;
+} vgt_current_bin_id_min_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MAX struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MAX_MASK \
+     (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_max_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+     } vgt_current_bin_id_max_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_max_t f;
+} vgt_current_bin_id_max_u;
+
+
+/*
+ * VGT_IMMED_DATA struct
+ */
+
+#define VGT_IMMED_DATA_DATA_SIZE       32
+
+#define VGT_IMMED_DATA_DATA_SHIFT      0
+
+#define VGT_IMMED_DATA_DATA_MASK       0xffffffff
+
+#define VGT_IMMED_DATA_MASK \
+     (VGT_IMMED_DATA_DATA_MASK)
+
+#define VGT_IMMED_DATA(data) \
+     ((data << VGT_IMMED_DATA_DATA_SHIFT))
+
+#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \
+     ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT)
+
+#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \
+     vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_immed_data_t f;
+} vgt_immed_data_u;
+
+
+/*
+ * VGT_MAX_VTX_INDX struct
+ */
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff
+
+#define VGT_MAX_VTX_INDX_MASK \
+     (VGT_MAX_VTX_INDX_MAX_INDX_MASK)
+
+#define VGT_MAX_VTX_INDX(max_indx) \
+     ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT))
+
+#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \
+     ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \
+     vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_max_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+     } vgt_max_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_max_vtx_indx_t f;
+} vgt_max_vtx_indx_u;
+
+
+/*
+ * VGT_MIN_VTX_INDX struct
+ */
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff
+
+#define VGT_MIN_VTX_INDX_MASK \
+     (VGT_MIN_VTX_INDX_MIN_INDX_MASK)
+
+#define VGT_MIN_VTX_INDX(min_indx) \
+     ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT))
+
+#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \
+     ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \
+     vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_min_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+     } vgt_min_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_min_vtx_indx_t f;
+} vgt_min_vtx_indx_u;
+
+
+/*
+ * VGT_INDX_OFFSET struct
+ */
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff
+
+#define VGT_INDX_OFFSET_MASK \
+     (VGT_INDX_OFFSET_INDX_OFFSET_MASK)
+
+#define VGT_INDX_OFFSET(indx_offset) \
+     ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT))
+
+#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \
+     ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \
+     vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+          unsigned int                                : 8;
+     } vgt_indx_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int                                : 8;
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+     } vgt_indx_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_indx_offset_t f;
+} vgt_indx_offset_u;
+
+
+/*
+ * VGT_VERTEX_REUSE_BLOCK_CNTL struct
+ */
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \
+     (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \
+     ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT))
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \
+     ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \
+     vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+          unsigned int                                : 29;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int                                : 29;
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vertex_reuse_block_cntl_t f;
+} vgt_vertex_reuse_block_cntl_u;
+
+
+/*
+ * VGT_OUT_DEALLOC_CNTL struct
+ */
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003
+
+#define VGT_OUT_DEALLOC_CNTL_MASK \
+     (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK)
+
+#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \
+     ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT))
+
+#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \
+     ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \
+     vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+          unsigned int                                : 30;
+     } vgt_out_dealloc_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int                                : 30;
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+     } vgt_out_dealloc_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_out_dealloc_cntl_t f;
+} vgt_out_dealloc_cntl_u;
+
+
+/*
+ * VGT_MULTI_PRIM_IB_RESET_INDX struct
+ */
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \
+     (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \
+     ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT))
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \
+     ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \
+     vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int                                : 8;
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_multi_prim_ib_reset_indx_t f;
+} vgt_multi_prim_ib_reset_indx_u;
+
+
+/*
+ * VGT_ENHANCE struct
+ */
+
+#define VGT_ENHANCE_MISC_SIZE          16
+
+#define VGT_ENHANCE_MISC_SHIFT         0
+
+#define VGT_ENHANCE_MISC_MASK          0x0000ffff
+
+#define VGT_ENHANCE_MASK \
+     (VGT_ENHANCE_MISC_MASK)
+
+#define VGT_ENHANCE(misc) \
+     ((misc << VGT_ENHANCE_MISC_SHIFT))
+
+#define VGT_ENHANCE_GET_MISC(vgt_enhance) \
+     ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT)
+
+#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \
+     vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+          unsigned int                                : 16;
+     } vgt_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int                                : 16;
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+     } vgt_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_enhance_t f;
+} vgt_enhance_u;
+
+
+/*
+ * VGT_VTX_VECT_EJECT_REG struct
+ */
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f
+
+#define VGT_VTX_VECT_EJECT_REG_MASK \
+     (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK)
+
+#define VGT_VTX_VECT_EJECT_REG(prim_count) \
+     ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT))
+
+#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \
+     ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \
+     vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+          unsigned int                                : 27;
+     } vgt_vtx_vect_eject_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int                                : 27;
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+     } vgt_vtx_vect_eject_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vtx_vect_eject_reg_t f;
+} vgt_vtx_vect_eject_reg_u;
+
+
+/*
+ * VGT_LAST_COPY_STATE struct
+ */
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000
+
+#define VGT_LAST_COPY_STATE_MASK \
+     (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \
+      VGT_LAST_COPY_STATE_DST_STATE_ID_MASK)
+
+#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \
+     ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \
+      (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT))
+
+#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+     } vgt_last_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+     } vgt_last_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_last_copy_state_t f;
+} vgt_last_copy_state_u;
+
+
+/*
+ * VGT_DEBUG_CNTL struct
+ */
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f
+
+#define VGT_DEBUG_CNTL_MASK \
+     (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK)
+
+#define VGT_DEBUG_CNTL(vgt_debug_indx) \
+     ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT))
+
+#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \
+     ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \
+     vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } vgt_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+     } vgt_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_cntl_t f;
+} vgt_debug_cntl_u;
+
+
+/*
+ * VGT_DEBUG_DATA struct
+ */
+
+#define VGT_DEBUG_DATA_DATA_SIZE       32
+
+#define VGT_DEBUG_DATA_DATA_SHIFT      0
+
+#define VGT_DEBUG_DATA_DATA_MASK       0xffffffff
+
+#define VGT_DEBUG_DATA_MASK \
+     (VGT_DEBUG_DATA_DATA_MASK)
+
+#define VGT_DEBUG_DATA(data) \
+     ((data << VGT_DEBUG_DATA_DATA_SHIFT))
+
+#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \
+     ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT)
+
+#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \
+     vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_data_t f;
+} vgt_debug_data_u;
+
+
+/*
+ * VGT_CNTL_STATUS struct
+ */
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SIZE  1
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8
+
+#define VGT_CNTL_STATUS_VGT_BUSY_MASK  0x00000001
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100
+
+#define VGT_CNTL_STATUS_MASK \
+     (VGT_CNTL_STATUS_VGT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK)
+
+#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \
+     ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \
+      (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \
+      (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \
+      (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \
+      (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \
+      (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \
+      (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \
+      (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \
+      (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT))
+
+#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int                                : 23;
+     } vgt_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int                                : 23;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+     } vgt_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_cntl_status_t f;
+} vgt_cntl_status_u;
+
+
+/*
+ * VGT_DEBUG_REG0 struct
+ */
+
+#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_out_busy_SIZE   1
+#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1
+#define VGT_DEBUG_REG0_grp_busy_SIZE   1
+#define VGT_DEBUG_REG0_dma_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_rbiu_busy_SIZE  1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1
+
+#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0
+#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2
+#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3
+#define VGT_DEBUG_REG0_out_busy_SHIFT  4
+#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5
+#define VGT_DEBUG_REG0_grp_busy_SHIFT  6
+#define VGT_DEBUG_REG0_dma_busy_SHIFT  7
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8
+#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11
+#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12
+#define VGT_DEBUG_REG0_vgt_busy_SHIFT  13
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16
+
+#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001
+#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002
+#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004
+#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008
+#define VGT_DEBUG_REG0_out_busy_MASK   0x00000010
+#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020
+#define VGT_DEBUG_REG0_grp_busy_MASK   0x00000040
+#define VGT_DEBUG_REG0_dma_busy_MASK   0x00000080
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100
+#define VGT_DEBUG_REG0_rbiu_busy_MASK  0x00000200
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800
+#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000
+#define VGT_DEBUG_REG0_vgt_busy_MASK   0x00002000
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000
+
+#define VGT_DEBUG_REG0_MASK \
+     (VGT_DEBUG_REG0_te_grp_busy_MASK | \
+      VGT_DEBUG_REG0_pt_grp_busy_MASK | \
+      VGT_DEBUG_REG0_vr_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_out_busy_MASK | \
+      VGT_DEBUG_REG0_grp_backend_busy_MASK | \
+      VGT_DEBUG_REG0_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_MASK | \
+      VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_busy_MASK)
+
+#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \
+     ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \
+      (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \
+      (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \
+      (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \
+      (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \
+      (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \
+      (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \
+      (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \
+      (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \
+      (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \
+      (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \
+      (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \
+      (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \
+      (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \
+      (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \
+      (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \
+      (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT))
+
+#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int                                : 15;
+     } vgt_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int                                : 15;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+     } vgt_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg0_t f;
+} vgt_debug_reg0_u;
+
+
+/*
+ * VGT_DEBUG_REG1 struct
+ */
+
+#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1
+#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_te_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1
+#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1
+#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1
+#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1
+
+#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0
+#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3
+#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5
+#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7
+#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9
+#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10
+#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11
+#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12
+#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13
+#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14
+#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15
+#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16
+#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20
+#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28
+#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30
+
+#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001
+#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002
+#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004
+#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008
+#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010
+#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020
+#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040
+#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080
+#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100
+#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200
+#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400
+#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800
+#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000
+#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000
+#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000
+#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000
+#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000
+#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000
+#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000
+#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000
+
+#define VGT_DEBUG_REG1_MASK \
+     (VGT_DEBUG_REG1_out_te_data_read_MASK | \
+      VGT_DEBUG_REG1_te_out_data_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_prim_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_data_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_prim_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_indx_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_te_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_te_valid_MASK | \
+      VGT_DEBUG_REG1_pt_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_pt_valid_MASK | \
+      VGT_DEBUG_REG1_vr_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_vr_valid_MASK | \
+      VGT_DEBUG_REG1_grp_dma_read_MASK | \
+      VGT_DEBUG_REG1_dma_grp_valid_MASK | \
+      VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \
+      VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \
+      VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_MH_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \
+      VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_SQ_send_MASK | \
+      VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK)
+
+#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \
+     ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \
+      (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \
+      (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \
+      (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \
+      (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \
+      (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \
+      (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \
+      (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \
+      (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \
+      (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \
+      (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \
+      (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \
+      (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \
+      (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \
+      (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \
+      (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \
+      (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \
+      (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \
+      (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \
+      (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \
+      (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \
+      (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \
+      (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \
+      (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \
+      (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \
+      (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \
+      (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \
+      (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \
+      (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \
+      (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \
+      (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT))
+
+#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int                                : 1;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+     } vgt_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg1_t f;
+} vgt_debug_reg1_u;
+
+
+/*
+ * VGT_DEBUG_REG3 struct
+ */
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002
+
+#define VGT_DEBUG_REG3_MASK \
+     (VGT_DEBUG_REG3_vgt_clk_en_MASK | \
+      VGT_DEBUG_REG3_reg_fifos_clk_en_MASK)
+
+#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \
+     ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \
+      (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT))
+
+#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int                                : 30;
+     } vgt_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int                                : 30;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+     } vgt_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg3_t f;
+} vgt_debug_reg3_u;
+
+
+/*
+ * VGT_DEBUG_REG6 struct
+ */
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG6_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_extract_vector_SIZE 1
+#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG6_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG6_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG6_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG6_MASK \
+     (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG6_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG6_input_data_valid_MASK | \
+      VGT_DEBUG_REG6_input_data_xfer_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG6_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG6_shifter_first_load_MASK | \
+      VGT_DEBUG_REG6_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG6_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG6_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG6_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG6_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG6_extract_vector_MASK | \
+      VGT_DEBUG_REG6_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG6_destination_rtr_MASK | \
+      VGT_DEBUG_REG6_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int                                : 3;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg6_t f;
+} vgt_debug_reg6_u;
+
+
+/*
+ * VGT_DEBUG_REG7 struct
+ */
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG7_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG7_MASK \
+     (VGT_DEBUG_REG7_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG7_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG7_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG7_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+     } vgt_debug_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+     } vgt_debug_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg7_t f;
+} vgt_debug_reg7_u;
+
+
+/*
+ * VGT_DEBUG_REG8 struct
+ */
+
+#define VGT_DEBUG_REG8_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG8_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG8_MASK \
+     (VGT_DEBUG_REG8_current_source_sel_MASK | \
+      VGT_DEBUG_REG8_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG8_input_data_cnt_MASK | \
+      VGT_DEBUG_REG8_input_data_lsw_MASK | \
+      VGT_DEBUG_REG8_input_data_msw_MASK | \
+      VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+     } vgt_debug_reg8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg8_t f;
+} vgt_debug_reg8_u;
+
+
+/*
+ * VGT_DEBUG_REG9 struct
+ */
+
+#define VGT_DEBUG_REG9_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG9_MASK \
+     (VGT_DEBUG_REG9_next_stride_q_MASK | \
+      VGT_DEBUG_REG9_next_stride_d_MASK | \
+      VGT_DEBUG_REG9_current_shift_q_MASK | \
+      VGT_DEBUG_REG9_current_shift_d_MASK | \
+      VGT_DEBUG_REG9_current_stride_q_MASK | \
+      VGT_DEBUG_REG9_current_stride_d_MASK | \
+      VGT_DEBUG_REG9_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int                                : 1;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+     } vgt_debug_reg9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg9_t f;
+} vgt_debug_reg9_u;
+
+
+/*
+ * VGT_DEBUG_REG10 struct
+ */
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG10_bin_valid_SIZE 1
+#define VGT_DEBUG_REG10_read_block_SIZE 1
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1
+#define VGT_DEBUG_REG10_selected_data_SIZE 8
+#define VGT_DEBUG_REG10_mask_input_data_SIZE 8
+#define VGT_DEBUG_REG10_gap_q_SIZE     1
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1
+#define VGT_DEBUG_REG10_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3
+#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4
+#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5
+#define VGT_DEBUG_REG10_bin_valid_SHIFT 6
+#define VGT_DEBUG_REG10_read_block_SHIFT 7
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8
+#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10
+#define VGT_DEBUG_REG10_selected_data_SHIFT 11
+#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19
+#define VGT_DEBUG_REG10_gap_q_SHIFT    27
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30
+#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008
+#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010
+#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020
+#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040
+#define VGT_DEBUG_REG10_read_block_MASK 0x00000080
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100
+#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200
+#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400
+#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800
+#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000
+#define VGT_DEBUG_REG10_gap_q_MASK     0x08000000
+#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000
+#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000
+#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000
+#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG10_MASK \
+     (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG10_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG10_bin_valid_MASK | \
+      VGT_DEBUG_REG10_read_block_MASK | \
+      VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \
+      VGT_DEBUG_REG10_last_bit_enable_q_MASK | \
+      VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \
+      VGT_DEBUG_REG10_selected_data_MASK | \
+      VGT_DEBUG_REG10_mask_input_data_MASK | \
+      VGT_DEBUG_REG10_gap_q_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \
+      VGT_DEBUG_REG10_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \
+     ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \
+      (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \
+      (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \
+      (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \
+      (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \
+      (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \
+      (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \
+      (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \
+      (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \
+      (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \
+      (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \
+      (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \
+      (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \
+      (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \
+      (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+     } vgt_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+     } vgt_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg10_t f;
+} vgt_debug_reg10_u;
+
+
+/*
+ * VGT_DEBUG_REG12 struct
+ */
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG12_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_extract_vector_SIZE 1
+#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG12_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG12_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG12_MASK \
+     (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG12_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG12_input_data_valid_MASK | \
+      VGT_DEBUG_REG12_input_data_xfer_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG12_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG12_shifter_first_load_MASK | \
+      VGT_DEBUG_REG12_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG12_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG12_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG12_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG12_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG12_extract_vector_MASK | \
+      VGT_DEBUG_REG12_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG12_destination_rtr_MASK | \
+      VGT_DEBUG_REG12_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int                                : 3;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg12_t f;
+} vgt_debug_reg12_u;
+
+
+/*
+ * VGT_DEBUG_REG13 struct
+ */
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG13_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG13_MASK \
+     (VGT_DEBUG_REG13_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG13_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG13_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG13_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+     } vgt_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+     } vgt_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg13_t f;
+} vgt_debug_reg13_u;
+
+
+/*
+ * VGT_DEBUG_REG14 struct
+ */
+
+#define VGT_DEBUG_REG14_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG14_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG14_MASK \
+     (VGT_DEBUG_REG14_current_source_sel_MASK | \
+      VGT_DEBUG_REG14_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG14_input_data_cnt_MASK | \
+      VGT_DEBUG_REG14_input_data_lsw_MASK | \
+      VGT_DEBUG_REG14_input_data_msw_MASK | \
+      VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+     } vgt_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg14_t f;
+} vgt_debug_reg14_u;
+
+
+/*
+ * VGT_DEBUG_REG15 struct
+ */
+
+#define VGT_DEBUG_REG15_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG15_MASK \
+     (VGT_DEBUG_REG15_next_stride_q_MASK | \
+      VGT_DEBUG_REG15_next_stride_d_MASK | \
+      VGT_DEBUG_REG15_current_shift_q_MASK | \
+      VGT_DEBUG_REG15_current_shift_d_MASK | \
+      VGT_DEBUG_REG15_current_stride_q_MASK | \
+      VGT_DEBUG_REG15_current_stride_d_MASK | \
+      VGT_DEBUG_REG15_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int                                : 1;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+     } vgt_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg15_t f;
+} vgt_debug_reg15_u;
+
+
+/*
+ * VGT_DEBUG_REG16 struct
+ */
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1
+#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1
+#define VGT_DEBUG_REG16_current_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_en_SIZE 1
+#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1
+#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9
+#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10
+#define VGT_DEBUG_REG16_current_state_q_SHIFT 11
+#define VGT_DEBUG_REG16_old_state_q_SHIFT 12
+#define VGT_DEBUG_REG16_old_state_en_SHIFT 13
+#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15
+#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17
+#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30
+#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200
+#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400
+#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800
+#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000
+#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000
+#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000
+#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000
+#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000
+#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000
+#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000
+#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG16_MASK \
+     (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \
+      VGT_DEBUG_REG16_rst_last_bit_MASK | \
+      VGT_DEBUG_REG16_current_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_en_MASK | \
+      VGT_DEBUG_REG16_prev_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_last_bit_block_q_MASK | \
+      VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \
+      VGT_DEBUG_REG16_load_empty_reg_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \
+      VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \
+     ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \
+      (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \
+      (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \
+      (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \
+      (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \
+      (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \
+      (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \
+      (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \
+      (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \
+      (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \
+      (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \
+      (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \
+      (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \
+      (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \
+      (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \
+      (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \
+      (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \
+      (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \
+      (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \
+      (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \
+      (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+     } vgt_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+     } vgt_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg16_t f;
+} vgt_debug_reg16_u;
+
+
+/*
+ * VGT_DEBUG_REG17 struct
+ */
+
+#define VGT_DEBUG_REG17_save_read_q_SIZE 1
+#define VGT_DEBUG_REG17_extend_read_q_SIZE 1
+#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2
+#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1
+#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1
+#define VGT_DEBUG_REG17_check_second_reg_SIZE 1
+#define VGT_DEBUG_REG17_check_first_reg_SIZE 1
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1
+#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG17_save_read_q_SHIFT 0
+#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1
+#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2
+#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4
+#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5
+#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6
+#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7
+#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8
+#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14
+#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15
+#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24
+#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001
+#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002
+#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c
+#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010
+#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020
+#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040
+#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080
+#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100
+#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000
+#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000
+#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000
+#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000
+#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000
+#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG17_MASK \
+     (VGT_DEBUG_REG17_save_read_q_MASK | \
+      VGT_DEBUG_REG17_extend_read_q_MASK | \
+      VGT_DEBUG_REG17_grp_indx_size_MASK | \
+      VGT_DEBUG_REG17_cull_prim_true_MASK | \
+      VGT_DEBUG_REG17_reset_bit2_q_MASK | \
+      VGT_DEBUG_REG17_reset_bit1_q_MASK | \
+      VGT_DEBUG_REG17_first_reg_first_q_MASK | \
+      VGT_DEBUG_REG17_check_second_reg_MASK | \
+      VGT_DEBUG_REG17_check_first_reg_MASK | \
+      VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \
+      VGT_DEBUG_REG17_to_second_reg_q_MASK | \
+      VGT_DEBUG_REG17_roll_over_msk_q_MASK | \
+      VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \
+     ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \
+      (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \
+      (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \
+      (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \
+      (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \
+      (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \
+      (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \
+      (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \
+      (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \
+      (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \
+      (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \
+      (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \
+      (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \
+      (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \
+      (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \
+      (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \
+      (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \
+      (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+     } vgt_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+     } vgt_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg17_t f;
+} vgt_debug_reg17_u;
+
+
+/*
+ * VGT_DEBUG_REG18 struct
+ */
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_start_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1
+#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13
+#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15
+#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16
+#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17
+#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20
+#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21
+#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22
+#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23
+#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24
+#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26
+#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27
+#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28
+#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000
+#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000
+#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000
+#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000
+#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000
+#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000
+#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000
+#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000
+#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000
+#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000
+#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000
+#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000
+#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000
+#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000
+
+#define VGT_DEBUG_REG18_MASK \
+     (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG18_dma_mem_full_MASK | \
+      VGT_DEBUG_REG18_dma_ram_re_MASK | \
+      VGT_DEBUG_REG18_dma_ram_we_MASK | \
+      VGT_DEBUG_REG18_dma_mem_empty_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \
+      VGT_DEBUG_REG18_bin_mem_full_MASK | \
+      VGT_DEBUG_REG18_bin_ram_we_MASK | \
+      VGT_DEBUG_REG18_bin_ram_re_MASK | \
+      VGT_DEBUG_REG18_bin_mem_empty_MASK | \
+      VGT_DEBUG_REG18_start_bin_req_MASK | \
+      VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \
+      VGT_DEBUG_REG18_dma_req_xfer_MASK | \
+      VGT_DEBUG_REG18_have_valid_bin_req_MASK | \
+      VGT_DEBUG_REG18_have_valid_dma_req_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK)
+
+#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \
+     ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \
+      (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \
+      (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \
+      (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \
+      (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \
+      (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \
+      (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \
+      (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \
+      (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \
+      (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \
+      (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \
+      (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \
+      (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \
+      (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \
+      (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \
+      (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \
+      (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \
+      (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \
+      (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT))
+
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+     } vgt_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+     } vgt_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg18_t f;
+} vgt_debug_reg18_u;
+
+
+/*
+ * VGT_DEBUG_REG20 struct
+ */
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_sent_cnt_SIZE  4
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5
+#define VGT_DEBUG_REG20_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5
+#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6
+#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7
+#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8
+#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9
+#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10
+#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11
+#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12
+#define VGT_DEBUG_REG20_hold_prim_SHIFT 13
+#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21
+#define VGT_DEBUG_REG20_out_trigger_SHIFT 26
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004
+#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020
+#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040
+#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080
+#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100
+#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200
+#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400
+#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800
+#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000
+#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000
+#define VGT_DEBUG_REG20_sent_cnt_MASK  0x0003c000
+#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000
+#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000
+#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000
+
+#define VGT_DEBUG_REG20_MASK \
+     (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_re_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_we_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_full_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_re_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_we_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_full_MASK | \
+      VGT_DEBUG_REG20_hold_prim_MASK | \
+      VGT_DEBUG_REG20_sent_cnt_MASK | \
+      VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \
+      VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \
+      VGT_DEBUG_REG20_out_trigger_MASK)
+
+#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \
+     ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \
+      (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \
+      (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \
+      (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \
+      (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \
+      (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \
+      (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \
+      (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \
+      (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \
+      (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \
+      (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \
+      (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \
+      (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \
+      (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \
+      (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \
+      (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \
+      (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \
+      (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \
+      (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int                                : 5;
+     } vgt_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int                                : 5;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+     } vgt_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg20_t f;
+} vgt_debug_reg20_u;
+
+
+/*
+ * VGT_DEBUG_REG21 struct
+ */
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3
+#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4
+#define VGT_DEBUG_REG21_new_packet_q_SIZE 1
+#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1
+#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1
+#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1
+#define VGT_DEBUG_REG21_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1
+#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14
+#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18
+#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22
+#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25
+#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26
+#define VGT_DEBUG_REG21_out_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e
+#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380
+#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000
+#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000
+#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000
+#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000
+#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000
+#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000
+#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG21_MASK \
+     (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \
+      VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \
+      VGT_DEBUG_REG21_alloc_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \
+      VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \
+      VGT_DEBUG_REG21_new_packet_q_MASK | \
+      VGT_DEBUG_REG21_new_allocate_q_MASK | \
+      VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \
+      VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \
+      VGT_DEBUG_REG21_insert_null_prim_MASK | \
+      VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \
+      VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \
+      VGT_DEBUG_REG21_buffered_thread_size_MASK | \
+      VGT_DEBUG_REG21_out_trigger_MASK)
+
+#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \
+     ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \
+      (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \
+      (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \
+      (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \
+      (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \
+      (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \
+      (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \
+      (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \
+      (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \
+      (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \
+      (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \
+      (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \
+      (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \
+      (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int                                : 4;
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+     } vgt_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+          unsigned int                                : 4;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+     } vgt_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg21_t f;
+} vgt_debug_reg21_u;
+
+
+/*
+ * VGT_CRC_SQ_DATA struct
+ */
+
+#define VGT_CRC_SQ_DATA_CRC_SIZE       32
+
+#define VGT_CRC_SQ_DATA_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_DATA_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_DATA_MASK \
+     (VGT_CRC_SQ_DATA_CRC_MASK)
+
+#define VGT_CRC_SQ_DATA(crc) \
+     ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT))
+
+#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \
+     ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \
+     vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_data_t f;
+} vgt_crc_sq_data_u;
+
+
+/*
+ * VGT_CRC_SQ_CTRL struct
+ */
+
+#define VGT_CRC_SQ_CTRL_CRC_SIZE       32
+
+#define VGT_CRC_SQ_CTRL_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_CTRL_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_CTRL_MASK \
+     (VGT_CRC_SQ_CTRL_CRC_MASK)
+
+#define VGT_CRC_SQ_CTRL(crc) \
+     ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT))
+
+#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \
+     ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \
+     vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_ctrl_t f;
+} vgt_crc_sq_ctrl_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER0_SELECT_MASK \
+     (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \
+     ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \
+     vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_select_t f;
+} vgt_perfcounter0_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER1_SELECT_MASK \
+     (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \
+     ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \
+     vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_select_t f;
+} vgt_perfcounter1_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER2_SELECT_MASK \
+     (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \
+     ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \
+     vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_select_t f;
+} vgt_perfcounter2_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER3_SELECT_MASK \
+     (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \
+     ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \
+     vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_select_t f;
+} vgt_perfcounter3_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_LOW struct
+ */
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER0_LOW_MASK \
+     (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \
+     ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \
+     vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_low_t f;
+} vgt_perfcounter0_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_LOW struct
+ */
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER1_LOW_MASK \
+     (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \
+     ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \
+     vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_low_t f;
+} vgt_perfcounter1_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_LOW struct
+ */
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER2_LOW_MASK \
+     (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \
+     ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \
+     vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_low_t f;
+} vgt_perfcounter2_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_LOW struct
+ */
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER3_LOW_MASK \
+     (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \
+     ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \
+     vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_low_t f;
+} vgt_perfcounter3_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_HI struct
+ */
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER0_HI_MASK \
+     (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \
+     ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \
+     vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_hi_t f;
+} vgt_perfcounter0_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_HI struct
+ */
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER1_HI_MASK \
+     (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \
+     ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \
+     vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_hi_t f;
+} vgt_perfcounter1_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_HI struct
+ */
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER2_HI_MASK \
+     (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \
+     ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \
+     vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_hi_t f;
+} vgt_perfcounter2_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_HI struct
+ */
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER3_HI_MASK \
+     (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \
+     ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \
+     vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_hi_t f;
+} vgt_perfcounter3_hi_u;
+
+
+#endif
+
+
+#if !defined (_SQ_FIDDLE_H)
+#define _SQ_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sq_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * SQ_GPR_MANAGEMENT struct
+ */
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000
+
+#define SQ_GPR_MANAGEMENT_MASK \
+     (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK)
+
+#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \
+     ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \
+      (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \
+      (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT))
+
+#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 13;
+     } sq_gpr_management_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int                                : 13;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+     } sq_gpr_management_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_gpr_management_t f;
+} sq_gpr_management_u;
+
+
+/*
+ * SQ_FLOW_CONTROL struct
+ */
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1
+#define SQ_FLOW_CONTROL_ONE_ALU_SIZE   1
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4
+#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE  1
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0
+#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4
+#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT  8
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12
+#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003
+#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010
+#define SQ_FLOW_CONTROL_ONE_ALU_MASK   0x00000100
+#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000
+#define SQ_FLOW_CONTROL_NO_PV_PS_MASK  0x00010000
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000
+
+#define SQ_FLOW_CONTROL_MASK \
+     (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ONE_THREAD_MASK | \
+      SQ_FLOW_CONTROL_ONE_ALU_MASK | \
+      SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \
+      SQ_FLOW_CONTROL_NO_PV_PS_MASK | \
+      SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \
+      SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \
+      SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \
+      SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \
+      SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \
+      SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \
+      SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK)
+
+#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \
+     ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \
+      (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \
+      (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \
+      (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \
+      (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \
+      (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \
+      (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \
+      (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \
+      (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \
+      (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \
+      (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \
+      (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \
+      (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \
+      (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \
+      (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT))
+
+#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+          unsigned int                                : 2;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int                                : 4;
+     } sq_flow_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int                                : 4;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 2;
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+     } sq_flow_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_flow_control_t f;
+} sq_flow_control_u;
+
+
+/*
+ * SQ_INST_STORE_MANAGMENT struct
+ */
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000
+
+#define SQ_INST_STORE_MANAGMENT_MASK \
+     (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \
+      SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK)
+
+#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \
+     ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \
+      (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT))
+
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+     } sq_inst_store_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+     } sq_inst_store_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_inst_store_managment_t f;
+} sq_inst_store_managment_u;
+
+
+/*
+ * SQ_RESOURCE_MANAGMENT struct
+ */
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000
+
+#define SQ_RESOURCE_MANAGMENT_MASK \
+     (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK)
+
+#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \
+     ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT))
+
+#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int                                : 7;
+     } sq_resource_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int                                : 7;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+     } sq_resource_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_resource_managment_t f;
+} sq_resource_managment_u;
+
+
+/*
+ * SQ_EO_RT struct
+ */
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE  8
+#define SQ_EO_RT_EO_TSTATE_RT_SIZE     8
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0
+#define SQ_EO_RT_EO_TSTATE_RT_SHIFT    16
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_MASK  0x000000ff
+#define SQ_EO_RT_EO_TSTATE_RT_MASK     0x00ff0000
+
+#define SQ_EO_RT_MASK \
+     (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \
+      SQ_EO_RT_EO_TSTATE_RT_MASK)
+
+#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \
+     ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \
+      (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT))
+
+#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+     } sq_eo_rt_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+     } sq_eo_rt_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_eo_rt_t f;
+} sq_eo_rt_u;
+
+
+/*
+ * SQ_DEBUG_MISC struct
+ */
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8
+#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1
+#define SQ_DEBUG_MISC_RESERVED_SIZE    2
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12
+#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20
+#define SQ_DEBUG_MISC_RESERVED_SHIFT   21
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000
+#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000
+#define SQ_DEBUG_MISC_RESERVED_MASK    0x00600000
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000
+
+#define SQ_DEBUG_MISC_MASK \
+     (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_READ_CTX_MASK | \
+      SQ_DEBUG_MISC_RESERVED_MASK | \
+      SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK)
+
+#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \
+     ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \
+      (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \
+      (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \
+      (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \
+      (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \
+      (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \
+      (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \
+      (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \
+      (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT))
+
+#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int                                : 3;
+     } sq_debug_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int                                : 3;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+     } sq_debug_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_t f;
+} sq_debug_misc_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_CNTL struct
+ */
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000
+#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000
+
+#define SQ_ACTIVITY_METER_CNTL_MASK \
+     (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \
+      SQ_ACTIVITY_METER_CNTL_SPARE_MASK)
+
+#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \
+     ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \
+      (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \
+      (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \
+      (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT))
+
+#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_cntl_t f;
+} sq_activity_meter_cntl_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_STATUS struct
+ */
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff
+
+#define SQ_ACTIVITY_METER_STATUS_MASK \
+     (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK)
+
+#define SQ_ACTIVITY_METER_STATUS(percent_busy) \
+     ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT))
+
+#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \
+     ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \
+     sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+          unsigned int                                : 24;
+     } sq_activity_meter_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int                                : 24;
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+     } sq_activity_meter_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_status_t f;
+} sq_activity_meter_status_u;
+
+
+/*
+ * SQ_INPUT_ARB_PRIORITY struct
+ */
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+
+#define SQ_INPUT_ARB_PRIORITY_MASK \
+     (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK)
+
+#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \
+     ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT))
+
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int                                : 14;
+     } sq_input_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int                                : 14;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_input_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_input_arb_priority_t f;
+} sq_input_arb_priority_u;
+
+
+/*
+ * SQ_THREAD_ARB_PRIORITY struct
+ */
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000
+
+#define SQ_THREAD_ARB_PRIORITY_MASK \
+     (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \
+      SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \
+      SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK)
+
+#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \
+     ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \
+      (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \
+      (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \
+      (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \
+      (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT))
+
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int                                : 9;
+     } sq_thread_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int                                : 9;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_thread_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_thread_arb_priority_t f;
+} sq_thread_arb_priority_u;
+
+
+/*
+ * SQ_VS_WATCHDOG_TIMER struct
+ */
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE 1
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT 0
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe
+
+#define SQ_VS_WATCHDOG_TIMER_MASK \
+     (SQ_VS_WATCHDOG_TIMER_ENABLE_MASK | \
+      SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK)
+
+#define SQ_VS_WATCHDOG_TIMER(enable, timeout_count) \
+     ((enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) | \
+      (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT))
+
+#define SQ_VS_WATCHDOG_TIMER_GET_ENABLE(sq_vs_watchdog_timer) \
+     ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_VS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_vs_watchdog_timer) \
+     ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#define SQ_VS_WATCHDOG_TIMER_SET_ENABLE(sq_vs_watchdog_timer_reg, enable) \
+     sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_VS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_vs_watchdog_timer_reg, timeout_count) \
+     sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_watchdog_timer_t {
+          unsigned int enable                         : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE;
+          unsigned int timeout_count                  : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+     } sq_vs_watchdog_timer_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_watchdog_timer_t {
+          unsigned int timeout_count                  : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+          unsigned int enable                         : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE;
+     } sq_vs_watchdog_timer_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_watchdog_timer_t f;
+} sq_vs_watchdog_timer_u;
+
+
+/*
+ * SQ_PS_WATCHDOG_TIMER struct
+ */
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE 1
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT 0
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe
+
+#define SQ_PS_WATCHDOG_TIMER_MASK \
+     (SQ_PS_WATCHDOG_TIMER_ENABLE_MASK | \
+      SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK)
+
+#define SQ_PS_WATCHDOG_TIMER(enable, timeout_count) \
+     ((enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) | \
+      (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT))
+
+#define SQ_PS_WATCHDOG_TIMER_GET_ENABLE(sq_ps_watchdog_timer) \
+     ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_PS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_ps_watchdog_timer) \
+     ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#define SQ_PS_WATCHDOG_TIMER_SET_ENABLE(sq_ps_watchdog_timer_reg, enable) \
+     sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_PS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_ps_watchdog_timer_reg, timeout_count) \
+     sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_watchdog_timer_t {
+          unsigned int enable                         : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE;
+          unsigned int timeout_count                  : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+     } sq_ps_watchdog_timer_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_watchdog_timer_t {
+          unsigned int timeout_count                  : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+          unsigned int enable                         : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE;
+     } sq_ps_watchdog_timer_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_watchdog_timer_t f;
+} sq_ps_watchdog_timer_u;
+
+
+/*
+ * SQ_INT_CNTL struct
+ */
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE 1
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE 1
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT 0
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT 1
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK 0x00000001
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK 0x00000002
+
+#define SQ_INT_CNTL_MASK \
+     (SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK | \
+      SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK)
+
+#define SQ_INT_CNTL(ps_watchdog_mask, vs_watchdog_mask) \
+     ((ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) | \
+      (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT))
+
+#define SQ_INT_CNTL_GET_PS_WATCHDOG_MASK(sq_int_cntl) \
+     ((sq_int_cntl & SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT)
+#define SQ_INT_CNTL_GET_VS_WATCHDOG_MASK(sq_int_cntl) \
+     ((sq_int_cntl & SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)
+
+#define SQ_INT_CNTL_SET_PS_WATCHDOG_MASK(sq_int_cntl_reg, ps_watchdog_mask) \
+     sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) | (ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT)
+#define SQ_INT_CNTL_SET_VS_WATCHDOG_MASK(sq_int_cntl_reg, vs_watchdog_mask) \
+     sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) | (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_cntl_t {
+          unsigned int ps_watchdog_mask               : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE;
+          unsigned int vs_watchdog_mask               : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE;
+          unsigned int                                : 30;
+     } sq_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_cntl_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_mask               : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE;
+          unsigned int ps_watchdog_mask               : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE;
+     } sq_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_cntl_t f;
+} sq_int_cntl_u;
+
+
+/*
+ * SQ_INT_STATUS struct
+ */
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE 1
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE 1
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT 0
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT 1
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK 0x00000001
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK 0x00000002
+
+#define SQ_INT_STATUS_MASK \
+     (SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK | \
+      SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK)
+
+#define SQ_INT_STATUS(ps_watchdog_timeout, vs_watchdog_timeout) \
+     ((ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) | \
+      (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT))
+
+#define SQ_INT_STATUS_GET_PS_WATCHDOG_TIMEOUT(sq_int_status) \
+     ((sq_int_status & SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT)
+#define SQ_INT_STATUS_GET_VS_WATCHDOG_TIMEOUT(sq_int_status) \
+     ((sq_int_status & SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)
+
+#define SQ_INT_STATUS_SET_PS_WATCHDOG_TIMEOUT(sq_int_status_reg, ps_watchdog_timeout) \
+     sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) | (ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT)
+#define SQ_INT_STATUS_SET_VS_WATCHDOG_TIMEOUT(sq_int_status_reg, vs_watchdog_timeout) \
+     sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) | (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_status_t {
+          unsigned int ps_watchdog_timeout            : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int vs_watchdog_timeout            : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int                                : 30;
+     } sq_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_status_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_timeout            : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int ps_watchdog_timeout            : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE;
+     } sq_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_status_t f;
+} sq_int_status_u;
+
+
+/*
+ * SQ_INT_ACK struct
+ */
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE 1
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE 1
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT 0
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT 1
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_MASK 0x00000001
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_MASK 0x00000002
+
+#define SQ_INT_ACK_MASK \
+     (SQ_INT_ACK_PS_WATCHDOG_ACK_MASK | \
+      SQ_INT_ACK_VS_WATCHDOG_ACK_MASK)
+
+#define SQ_INT_ACK(ps_watchdog_ack, vs_watchdog_ack) \
+     ((ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) | \
+      (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT))
+
+#define SQ_INT_ACK_GET_PS_WATCHDOG_ACK(sq_int_ack) \
+     ((sq_int_ack & SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT)
+#define SQ_INT_ACK_GET_VS_WATCHDOG_ACK(sq_int_ack) \
+     ((sq_int_ack & SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)
+
+#define SQ_INT_ACK_SET_PS_WATCHDOG_ACK(sq_int_ack_reg, ps_watchdog_ack) \
+     sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) | (ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT)
+#define SQ_INT_ACK_SET_VS_WATCHDOG_ACK(sq_int_ack_reg, vs_watchdog_ack) \
+     sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) | (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_ack_t {
+          unsigned int ps_watchdog_ack                : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE;
+          unsigned int vs_watchdog_ack                : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE;
+          unsigned int                                : 30;
+     } sq_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_ack_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_ack                : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE;
+          unsigned int ps_watchdog_ack                : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE;
+     } sq_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_ack_t f;
+} sq_int_ack_u;
+
+
+/*
+ * SQ_DEBUG_INPUT_FSM struct
+ */
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE  3
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007
+#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK  0x00007000
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000
+
+#define SQ_DEBUG_INPUT_FSM_MASK \
+     (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \
+      SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK)
+
+#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \
+     ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \
+      (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \
+      (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \
+      (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \
+      (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \
+      (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \
+      (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \
+      (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT))
+
+#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_input_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int                                : 4;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+     } sq_debug_input_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_input_fsm_t f;
+} sq_debug_input_fsm_u;
+
+
+/*
+ * SQ_DEBUG_CONST_MGR_FSM struct
+ */
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000
+
+#define SQ_DEBUG_CONST_MGR_FSM_MASK \
+     (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK)
+
+#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \
+     ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \
+      (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \
+      (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \
+      (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \
+      (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \
+      (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \
+      (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \
+      (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \
+      (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \
+      (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT))
+
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int                                : 8;
+     } sq_debug_const_mgr_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int                                : 8;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+     } sq_debug_const_mgr_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_const_mgr_fsm_t f;
+} sq_debug_const_mgr_fsm_u;
+
+
+/*
+ * SQ_DEBUG_TP_FSM struct
+ */
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1
+#define SQ_DEBUG_TP_FSM_CF_TP_SIZE     4
+#define SQ_DEBUG_TP_FSM_IF_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2
+#define SQ_DEBUG_TP_FSM_GS_TP_SIZE     2
+#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT    0
+#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3
+#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT    4
+#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT    8
+#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT   12
+#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14
+#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT    16
+#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18
+#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT   20
+#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22
+#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT   24
+#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28
+
+#define SQ_DEBUG_TP_FSM_EX_TP_MASK     0x00000007
+#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_TP_FSM_CF_TP_MASK     0x000000f0
+#define SQ_DEBUG_TP_FSM_IF_TP_MASK     0x00000700
+#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_TP_FSM_TIS_TP_MASK    0x00003000
+#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000
+#define SQ_DEBUG_TP_FSM_GS_TP_MASK     0x00030000
+#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000
+#define SQ_DEBUG_TP_FSM_FCR_TP_MASK    0x00300000
+#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000
+#define SQ_DEBUG_TP_FSM_FCS_TP_MASK    0x03000000
+#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000
+
+#define SQ_DEBUG_TP_FSM_MASK \
+     (SQ_DEBUG_TP_FSM_EX_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED0_MASK | \
+      SQ_DEBUG_TP_FSM_CF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_IF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_TP_FSM_TIS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_TP_FSM_GS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED3_MASK | \
+      SQ_DEBUG_TP_FSM_FCR_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED4_MASK | \
+      SQ_DEBUG_TP_FSM_FCS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED5_MASK | \
+      SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK)
+
+#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \
+     ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \
+      (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \
+      (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \
+      (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \
+      (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \
+      (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \
+      (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \
+      (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \
+      (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \
+      (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \
+      (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \
+      (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \
+      (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \
+      (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT))
+
+#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_tp_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+     } sq_debug_tp_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tp_fsm_t f;
+} sq_debug_tp_fsm_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_0 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_0_MASK \
+     (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_0_t f;
+} sq_debug_fsm_alu_0_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_1 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_1_MASK \
+     (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_1_t f;
+} sq_debug_fsm_alu_1_u;
+
+
+/*
+ * SQ_DEBUG_EXP_ALLOC struct
+ */
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000
+
+#define SQ_DEBUG_EXP_ALLOC_MASK \
+     (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \
+      SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK)
+
+#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \
+     ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \
+      (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \
+      (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \
+      (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \
+      (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT))
+
+#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_exp_alloc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int                                : 10;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+     } sq_debug_exp_alloc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_exp_alloc_t f;
+} sq_debug_exp_alloc_u;
+
+
+/*
+ * SQ_DEBUG_PTR_BUFF struct
+ */
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000
+
+#define SQ_DEBUG_PTR_BUFF_MASK \
+     (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \
+      SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \
+      SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \
+      SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \
+      SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \
+      SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK)
+
+#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \
+     ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \
+      (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \
+      (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \
+      (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \
+      (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \
+      (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \
+      (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \
+      (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \
+      (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT))
+
+#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_ptr_buff_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int                                : 4;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+     } sq_debug_ptr_buff_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_ptr_buff_t f;
+} sq_debug_ptr_buff_u;
+
+
+/*
+ * SQ_DEBUG_GPR_VTX struct
+ */
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_VTX_MASK \
+     (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \
+     ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \
+      (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \
+      (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \
+      (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_vtx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int                                : 1;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_vtx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_vtx_t f;
+} sq_debug_gpr_vtx_u;
+
+
+/*
+ * SQ_DEBUG_GPR_PIX struct
+ */
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_PIX_MASK \
+     (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \
+     ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \
+      (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \
+      (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \
+      (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_pix_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int                                : 1;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_pix_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_pix_t f;
+} sq_debug_gpr_pix_u;
+
+
+/*
+ * SQ_DEBUG_TB_STATUS_SEL struct
+ */
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000
+
+#define SQ_DEBUG_TB_STATUS_SEL_MASK \
+     (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK)
+
+#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \
+     ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \
+      (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \
+      (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \
+      (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \
+      (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT))
+
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tb_status_sel_t f;
+} sq_debug_tb_status_sel_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_0 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE  1
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK  0x00200000
+
+#define SQ_DEBUG_VTX_TB_0_MASK \
+     (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \
+      SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK)
+
+#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \
+     ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \
+      (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \
+      (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \
+      (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \
+      (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \
+      (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \
+      (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_vtx_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int                                : 10;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+     } sq_debug_vtx_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_0_t f;
+} sq_debug_vtx_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_1 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff
+
+#define SQ_DEBUG_VTX_TB_1_MASK \
+     (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK)
+
+#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \
+     ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \
+     ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \
+     sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+          unsigned int                                : 16;
+     } sq_debug_vtx_tb_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int                                : 16;
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+     } sq_debug_vtx_tb_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_1_t f;
+} sq_debug_vtx_tb_1_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATUS_REG struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \
+     (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \
+     ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \
+     ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \
+     sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_status_reg_t f;
+} sq_debug_vtx_tb_status_reg_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \
+     ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \
+     ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \
+     sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_state_mem_t f;
+} sq_debug_vtx_tb_state_mem_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE    1
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25
+#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT   31
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000
+#define SQ_DEBUG_PIX_TB_0_BUSY_MASK    0x80000000
+
+#define SQ_DEBUG_PIX_TB_0_MASK \
+     (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_BUSY_MASK)
+
+#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \
+     ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \
+      (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \
+      (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \
+      (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \
+      (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \
+      (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_0_t f;
+} sq_debug_pix_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \
+     ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \
+     ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \
+     sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_0_t f;
+} sq_debug_pix_tb_status_reg_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \
+     ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \
+     ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \
+     sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_1_t f;
+} sq_debug_pix_tb_status_reg_1_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \
+     ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \
+     ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \
+     sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_2_t f;
+} sq_debug_pix_tb_status_reg_2_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \
+     ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \
+     ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \
+     sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_3_t f;
+} sq_debug_pix_tb_status_reg_3_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \
+     ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \
+     ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \
+     sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_state_mem_t f;
+} sq_debug_pix_tb_state_mem_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER0_SELECT_MASK \
+     (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \
+     ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \
+     sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_select_t f;
+} sq_perfcounter0_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER1_SELECT_MASK \
+     (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \
+     ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \
+     sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_select_t f;
+} sq_perfcounter1_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER2_SELECT_MASK \
+     (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \
+     ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \
+     sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_select_t f;
+} sq_perfcounter2_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER3_SELECT_MASK \
+     (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \
+     ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \
+     sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_select_t f;
+} sq_perfcounter3_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_LOW struct
+ */
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER0_LOW_MASK \
+     (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \
+     ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \
+     sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_low_t f;
+} sq_perfcounter0_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_HI struct
+ */
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER0_HI_MASK \
+     (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \
+     ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \
+     sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_hi_t f;
+} sq_perfcounter0_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_LOW struct
+ */
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER1_LOW_MASK \
+     (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \
+     ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \
+     sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_low_t f;
+} sq_perfcounter1_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_HI struct
+ */
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER1_HI_MASK \
+     (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \
+     ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \
+     sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_hi_t f;
+} sq_perfcounter1_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_LOW struct
+ */
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER2_LOW_MASK \
+     (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \
+     ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \
+     sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_low_t f;
+} sq_perfcounter2_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_HI struct
+ */
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER2_HI_MASK \
+     (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \
+     ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \
+     sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_hi_t f;
+} sq_perfcounter2_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_LOW struct
+ */
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER3_LOW_MASK \
+     (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \
+     ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \
+     sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_low_t f;
+} sq_perfcounter3_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_HI struct
+ */
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER3_HI_MASK \
+     (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \
+     ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \
+     sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_hi_t f;
+} sq_perfcounter3_hi_u;
+
+
+/*
+ * SX_PERFCOUNTER0_SELECT struct
+ */
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SX_PERFCOUNTER0_SELECT_MASK \
+     (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SX_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \
+     ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \
+     sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sx_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sx_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_select_t f;
+} sx_perfcounter0_select_u;
+
+
+/*
+ * SX_PERFCOUNTER0_LOW struct
+ */
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SX_PERFCOUNTER0_LOW_MASK \
+     (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \
+     ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \
+     sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_low_t f;
+} sx_perfcounter0_low_u;
+
+
+/*
+ * SX_PERFCOUNTER0_HI struct
+ */
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SX_PERFCOUNTER0_HI_MASK \
+     (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \
+     ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \
+     sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sx_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sx_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_hi_t f;
+} sx_perfcounter0_hi_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_0 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT 6
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT 14
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_ALU_0_MASK \
+     (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK | \
+      SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK | \
+      SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_ALU_0(vector_result, vector_dst_rel, low_precision_16b_fp, scalar_result, scalar_dst_rel, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \
+     ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \
+      (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) | \
+      (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \
+      (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \
+      (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) | \
+      (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \
+      (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \
+      (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \
+      (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \
+      (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \
+      (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_DST_REL(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_DST_REL(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_DST_REL(sq_instruction_alu_0_reg, vector_dst_rel) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) | (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_DST_REL(sq_instruction_alu_0_reg, scalar_dst_rel) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) | (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+          unsigned int vector_dst_rel                 : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int scalar_dst_rel                 : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+     } sq_instruction_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int scalar_dst_rel                 : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int vector_dst_rel                 : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE;
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+     } sq_instruction_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_0_t f;
+} sq_instruction_alu_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_1 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_1_MASK \
+     (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \
+      SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK)
+
+#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \
+     ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \
+      (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \
+      (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \
+      (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \
+      (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \
+      (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \
+      (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \
+      (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \
+      (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \
+      (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \
+      (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \
+      (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \
+      (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \
+      (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \
+      (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \
+      (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \
+      (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \
+      (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+     } sq_instruction_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+     } sq_instruction_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_1_t f;
+} sq_instruction_alu_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_2 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_2_MASK \
+     (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK)
+
+#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \
+     ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \
+      (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \
+      (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \
+      (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \
+      (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \
+      (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \
+      (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \
+      (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \
+      (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \
+      (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \
+      (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \
+      (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \
+      (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+     } sq_instruction_alu_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+     } sq_instruction_alu_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_2_t f;
+} sq_instruction_alu_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_0_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \
+     ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \
+      (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_0_t f;
+} sq_instruction_cf_exec_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_1_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \
+     ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_1_t f;
+} sq_instruction_cf_exec_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_EXEC_2_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \
+     ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \
+      (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_2_t f;
+} sq_instruction_cf_exec_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000
+
+#define SQ_INSTRUCTION_CF_LOOP_0_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \
+      (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_0_t f;
+} sq_instruction_cf_loop_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_CF_LOOP_1_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_1_t f;
+} sq_instruction_cf_loop_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_LOOP_2_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \
+     ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_2_t f;
+} sq_instruction_cf_loop_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \
+      (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_0_t f;
+} sq_instruction_cf_jmp_call_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \
+      (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_1_t f;
+} sq_instruction_cf_jmp_call_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_2_t f;
+} sq_instruction_cf_jmp_call_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \
+     ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_0_t f;
+} sq_instruction_cf_alloc_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \
+      (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_1_t f;
+} sq_instruction_cf_alloc_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_2_t f;
+} sq_instruction_cf_alloc_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_TFETCH_0_MASK \
+     (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \
+     ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \
+      (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \
+      (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \
+      (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \
+      (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \
+      (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_0_t f;
+} sq_instruction_tfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_1_MASK \
+     (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \
+      (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \
+      (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \
+      (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \
+      (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \
+      (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \
+      (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \
+      (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \
+      (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \
+      (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_1_t f;
+} sq_instruction_tfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_2_MASK \
+     (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \
+     ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \
+      (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \
+      (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \
+      (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \
+      (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \
+      (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \
+      (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_2_t f;
+} sq_instruction_tfetch_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_VFETCH_0_MASK \
+     (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \
+     ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \
+      (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \
+      (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \
+      (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_0_t f;
+} sq_instruction_vfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_1_MASK \
+     (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \
+      (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \
+      (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \
+      (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \
+      (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \
+      (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_1_t f;
+} sq_instruction_vfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_2_MASK \
+     (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \
+     ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \
+      (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+          unsigned int                                : 8;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 7;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int                                : 7;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 8;
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_2_t f;
+} sq_instruction_vfetch_2_u;
+
+
+/*
+ * SQ_CONSTANT_0 struct
+ */
+
+#define SQ_CONSTANT_0_RED_SIZE         32
+
+#define SQ_CONSTANT_0_RED_SHIFT        0
+
+#define SQ_CONSTANT_0_RED_MASK         0xffffffff
+
+#define SQ_CONSTANT_0_MASK \
+     (SQ_CONSTANT_0_RED_MASK)
+
+#define SQ_CONSTANT_0(red) \
+     ((red << SQ_CONSTANT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \
+     ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \
+     sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_0_t f;
+} sq_constant_0_u;
+
+
+/*
+ * SQ_CONSTANT_1 struct
+ */
+
+#define SQ_CONSTANT_1_GREEN_SIZE       32
+
+#define SQ_CONSTANT_1_GREEN_SHIFT      0
+
+#define SQ_CONSTANT_1_GREEN_MASK       0xffffffff
+
+#define SQ_CONSTANT_1_MASK \
+     (SQ_CONSTANT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_1(green) \
+     ((green << SQ_CONSTANT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \
+     ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \
+     sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_1_t f;
+} sq_constant_1_u;
+
+
+/*
+ * SQ_CONSTANT_2 struct
+ */
+
+#define SQ_CONSTANT_2_BLUE_SIZE        32
+
+#define SQ_CONSTANT_2_BLUE_SHIFT       0
+
+#define SQ_CONSTANT_2_BLUE_MASK        0xffffffff
+
+#define SQ_CONSTANT_2_MASK \
+     (SQ_CONSTANT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_2(blue) \
+     ((blue << SQ_CONSTANT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \
+     ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \
+     sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_2_t f;
+} sq_constant_2_u;
+
+
+/*
+ * SQ_CONSTANT_3 struct
+ */
+
+#define SQ_CONSTANT_3_ALPHA_SIZE       32
+
+#define SQ_CONSTANT_3_ALPHA_SHIFT      0
+
+#define SQ_CONSTANT_3_ALPHA_MASK       0xffffffff
+
+#define SQ_CONSTANT_3_MASK \
+     (SQ_CONSTANT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_3(alpha) \
+     ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \
+     ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \
+     sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_3_t f;
+} sq_constant_3_u;
+
+
+/*
+ * SQ_FETCH_0 struct
+ */
+
+#define SQ_FETCH_0_VALUE_SIZE          32
+
+#define SQ_FETCH_0_VALUE_SHIFT         0
+
+#define SQ_FETCH_0_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_0_MASK \
+     (SQ_FETCH_0_VALUE_MASK)
+
+#define SQ_FETCH_0(value) \
+     ((value << SQ_FETCH_0_VALUE_SHIFT))
+
+#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \
+     ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT)
+
+#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \
+     sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_0_t f;
+} sq_fetch_0_u;
+
+
+/*
+ * SQ_FETCH_1 struct
+ */
+
+#define SQ_FETCH_1_VALUE_SIZE          32
+
+#define SQ_FETCH_1_VALUE_SHIFT         0
+
+#define SQ_FETCH_1_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_1_MASK \
+     (SQ_FETCH_1_VALUE_MASK)
+
+#define SQ_FETCH_1(value) \
+     ((value << SQ_FETCH_1_VALUE_SHIFT))
+
+#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \
+     ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT)
+
+#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \
+     sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_1_t f;
+} sq_fetch_1_u;
+
+
+/*
+ * SQ_FETCH_2 struct
+ */
+
+#define SQ_FETCH_2_VALUE_SIZE          32
+
+#define SQ_FETCH_2_VALUE_SHIFT         0
+
+#define SQ_FETCH_2_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_2_MASK \
+     (SQ_FETCH_2_VALUE_MASK)
+
+#define SQ_FETCH_2(value) \
+     ((value << SQ_FETCH_2_VALUE_SHIFT))
+
+#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \
+     ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT)
+
+#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \
+     sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_2_t f;
+} sq_fetch_2_u;
+
+
+/*
+ * SQ_FETCH_3 struct
+ */
+
+#define SQ_FETCH_3_VALUE_SIZE          32
+
+#define SQ_FETCH_3_VALUE_SHIFT         0
+
+#define SQ_FETCH_3_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_3_MASK \
+     (SQ_FETCH_3_VALUE_MASK)
+
+#define SQ_FETCH_3(value) \
+     ((value << SQ_FETCH_3_VALUE_SHIFT))
+
+#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \
+     ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT)
+
+#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \
+     sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_3_t f;
+} sq_fetch_3_u;
+
+
+/*
+ * SQ_FETCH_4 struct
+ */
+
+#define SQ_FETCH_4_VALUE_SIZE          32
+
+#define SQ_FETCH_4_VALUE_SHIFT         0
+
+#define SQ_FETCH_4_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_4_MASK \
+     (SQ_FETCH_4_VALUE_MASK)
+
+#define SQ_FETCH_4(value) \
+     ((value << SQ_FETCH_4_VALUE_SHIFT))
+
+#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \
+     ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT)
+
+#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \
+     sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_4_t f;
+} sq_fetch_4_u;
+
+
+/*
+ * SQ_FETCH_5 struct
+ */
+
+#define SQ_FETCH_5_VALUE_SIZE          32
+
+#define SQ_FETCH_5_VALUE_SHIFT         0
+
+#define SQ_FETCH_5_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_5_MASK \
+     (SQ_FETCH_5_VALUE_MASK)
+
+#define SQ_FETCH_5(value) \
+     ((value << SQ_FETCH_5_VALUE_SHIFT))
+
+#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \
+     ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT)
+
+#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \
+     sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_5_t f;
+} sq_fetch_5_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_0 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0
+#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001
+#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_0_MASK \
+     (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \
+      SQ_CONSTANT_VFETCH_0_STATE_MASK | \
+      SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \
+     ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \
+      (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \
+      (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_0_t f;
+} sq_constant_vfetch_0_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_1 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_1_MASK \
+     (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \
+      SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \
+     ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \
+      (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_1_t f;
+} sq_constant_vfetch_1_u;
+
+
+/*
+ * SQ_CONSTANT_T2 struct
+ */
+
+#define SQ_CONSTANT_T2_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T2_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T2_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T2_MASK \
+     (SQ_CONSTANT_T2_VALUE_MASK)
+
+#define SQ_CONSTANT_T2(value) \
+     ((value << SQ_CONSTANT_T2_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \
+     ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \
+     sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t2_t f;
+} sq_constant_t2_u;
+
+
+/*
+ * SQ_CONSTANT_T3 struct
+ */
+
+#define SQ_CONSTANT_T3_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T3_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T3_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T3_MASK \
+     (SQ_CONSTANT_T3_VALUE_MASK)
+
+#define SQ_CONSTANT_T3(value) \
+     ((value << SQ_CONSTANT_T3_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \
+     ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \
+     sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t3_t f;
+} sq_constant_t3_u;
+
+
+/*
+ * SQ_CF_BOOLEANS struct
+ */
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_BOOLEANS_MASK \
+     (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_booleans_t f;
+} sq_cf_booleans_u;
+
+
+/*
+ * SQ_CF_LOOP struct
+ */
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_START_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE   8
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT  16
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK  0x000000ff
+#define SQ_CF_LOOP_CF_LOOP_START_MASK  0x0000ff00
+#define SQ_CF_LOOP_CF_LOOP_STEP_MASK   0x00ff0000
+
+#define SQ_CF_LOOP_MASK \
+     (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_loop_t f;
+} sq_cf_loop_u;
+
+
+/*
+ * SQ_CONSTANT_RT_0 struct
+ */
+
+#define SQ_CONSTANT_RT_0_RED_SIZE      32
+
+#define SQ_CONSTANT_RT_0_RED_SHIFT     0
+
+#define SQ_CONSTANT_RT_0_RED_MASK      0xffffffff
+
+#define SQ_CONSTANT_RT_0_MASK \
+     (SQ_CONSTANT_RT_0_RED_MASK)
+
+#define SQ_CONSTANT_RT_0(red) \
+     ((red << SQ_CONSTANT_RT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \
+     ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \
+     sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_0_t f;
+} sq_constant_rt_0_u;
+
+
+/*
+ * SQ_CONSTANT_RT_1 struct
+ */
+
+#define SQ_CONSTANT_RT_1_GREEN_SIZE    32
+
+#define SQ_CONSTANT_RT_1_GREEN_SHIFT   0
+
+#define SQ_CONSTANT_RT_1_GREEN_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_1_MASK \
+     (SQ_CONSTANT_RT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_RT_1(green) \
+     ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \
+     ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \
+     sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_1_t f;
+} sq_constant_rt_1_u;
+
+
+/*
+ * SQ_CONSTANT_RT_2 struct
+ */
+
+#define SQ_CONSTANT_RT_2_BLUE_SIZE     32
+
+#define SQ_CONSTANT_RT_2_BLUE_SHIFT    0
+
+#define SQ_CONSTANT_RT_2_BLUE_MASK     0xffffffff
+
+#define SQ_CONSTANT_RT_2_MASK \
+     (SQ_CONSTANT_RT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_RT_2(blue) \
+     ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \
+     ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \
+     sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_2_t f;
+} sq_constant_rt_2_u;
+
+
+/*
+ * SQ_CONSTANT_RT_3 struct
+ */
+
+#define SQ_CONSTANT_RT_3_ALPHA_SIZE    32
+
+#define SQ_CONSTANT_RT_3_ALPHA_SHIFT   0
+
+#define SQ_CONSTANT_RT_3_ALPHA_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_3_MASK \
+     (SQ_CONSTANT_RT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_RT_3(alpha) \
+     ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \
+     ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \
+     sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_3_t f;
+} sq_constant_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_0 struct
+ */
+
+#define SQ_FETCH_RT_0_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_0_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_0_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_0_MASK \
+     (SQ_FETCH_RT_0_VALUE_MASK)
+
+#define SQ_FETCH_RT_0(value) \
+     ((value << SQ_FETCH_RT_0_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \
+     ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \
+     sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_0_t f;
+} sq_fetch_rt_0_u;
+
+
+/*
+ * SQ_FETCH_RT_1 struct
+ */
+
+#define SQ_FETCH_RT_1_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_1_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_1_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_1_MASK \
+     (SQ_FETCH_RT_1_VALUE_MASK)
+
+#define SQ_FETCH_RT_1(value) \
+     ((value << SQ_FETCH_RT_1_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \
+     ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \
+     sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_1_t f;
+} sq_fetch_rt_1_u;
+
+
+/*
+ * SQ_FETCH_RT_2 struct
+ */
+
+#define SQ_FETCH_RT_2_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_2_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_2_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_2_MASK \
+     (SQ_FETCH_RT_2_VALUE_MASK)
+
+#define SQ_FETCH_RT_2(value) \
+     ((value << SQ_FETCH_RT_2_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \
+     ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \
+     sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_2_t f;
+} sq_fetch_rt_2_u;
+
+
+/*
+ * SQ_FETCH_RT_3 struct
+ */
+
+#define SQ_FETCH_RT_3_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_3_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_3_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_3_MASK \
+     (SQ_FETCH_RT_3_VALUE_MASK)
+
+#define SQ_FETCH_RT_3(value) \
+     ((value << SQ_FETCH_RT_3_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \
+     ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \
+     sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_3_t f;
+} sq_fetch_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_4 struct
+ */
+
+#define SQ_FETCH_RT_4_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_4_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_4_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_4_MASK \
+     (SQ_FETCH_RT_4_VALUE_MASK)
+
+#define SQ_FETCH_RT_4(value) \
+     ((value << SQ_FETCH_RT_4_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \
+     ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \
+     sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_4_t f;
+} sq_fetch_rt_4_u;
+
+
+/*
+ * SQ_FETCH_RT_5 struct
+ */
+
+#define SQ_FETCH_RT_5_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_5_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_5_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_5_MASK \
+     (SQ_FETCH_RT_5_VALUE_MASK)
+
+#define SQ_FETCH_RT_5(value) \
+     ((value << SQ_FETCH_RT_5_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \
+     ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \
+     sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_5_t f;
+} sq_fetch_rt_5_u;
+
+
+/*
+ * SQ_CF_RT_BOOLEANS struct
+ */
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_RT_BOOLEANS_MASK \
+     (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_booleans_t f;
+} sq_cf_rt_booleans_u;
+
+
+/*
+ * SQ_CF_RT_LOOP struct
+ */
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff
+#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000
+
+#define SQ_CF_RT_LOOP_MASK \
+     (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_rt_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_rt_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_loop_t f;
+} sq_cf_rt_loop_u;
+
+
+/*
+ * SQ_VS_PROGRAM struct
+ */
+
+#define SQ_VS_PROGRAM_BASE_SIZE        12
+#define SQ_VS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_VS_PROGRAM_BASE_SHIFT       0
+#define SQ_VS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_VS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_VS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_VS_PROGRAM_MASK \
+     (SQ_VS_PROGRAM_BASE_MASK | \
+      SQ_VS_PROGRAM_SIZE_MASK)
+
+#define SQ_VS_PROGRAM(base, size) \
+     ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_VS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_vs_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+     } sq_vs_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_program_t f;
+} sq_vs_program_u;
+
+
+/*
+ * SQ_PS_PROGRAM struct
+ */
+
+#define SQ_PS_PROGRAM_BASE_SIZE        12
+#define SQ_PS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_PS_PROGRAM_BASE_SHIFT       0
+#define SQ_PS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_PS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_PS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_PS_PROGRAM_MASK \
+     (SQ_PS_PROGRAM_BASE_MASK | \
+      SQ_PS_PROGRAM_SIZE_MASK)
+
+#define SQ_PS_PROGRAM(base, size) \
+     ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_PS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_ps_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+     } sq_ps_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_program_t f;
+} sq_ps_program_u;
+
+
+/*
+ * SQ_CF_PROGRAM_SIZE struct
+ */
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000
+
+#define SQ_CF_PROGRAM_SIZE_MASK \
+     (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \
+      SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK)
+
+#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \
+     ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \
+      (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT))
+
+#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 9;
+     } sq_cf_program_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int                                : 9;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+     } sq_cf_program_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_program_size_t f;
+} sq_cf_program_size_u;
+
+
+/*
+ * SQ_INTERPOLATOR_CNTL struct
+ */
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000
+
+#define SQ_INTERPOLATOR_CNTL_MASK \
+     (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \
+      SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK)
+
+#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \
+     ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \
+      (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT))
+
+#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+     } sq_interpolator_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+     } sq_interpolator_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_interpolator_cntl_t f;
+} sq_interpolator_cntl_u;
+
+
+/*
+ * SQ_PROGRAM_CNTL struct
+ */
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000
+#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000
+
+#define SQ_PROGRAM_CNTL_MASK \
+     (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK)
+
+#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \
+     ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \
+      (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \
+      (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \
+      (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \
+      (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \
+      (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \
+      (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \
+      (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \
+      (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \
+      (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT))
+
+#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+     } sq_program_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+     } sq_program_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_program_cntl_t f;
+} sq_program_cntl_u;
+
+
+/*
+ * SQ_WRAPPING_0 struct
+ */
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f
+#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0
+#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00
+#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000
+#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000
+#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000
+#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000
+#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000
+
+#define SQ_WRAPPING_0_MASK \
+     (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_7_MASK)
+
+#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \
+     ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \
+      (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \
+      (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \
+      (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \
+      (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \
+      (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \
+      (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \
+      (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT))
+
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+     } sq_wrapping_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+     } sq_wrapping_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_0_t f;
+} sq_wrapping_0_u;
+
+
+/*
+ * SQ_WRAPPING_1 struct
+ */
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f
+#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0
+#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00
+#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000
+#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000
+#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000
+#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000
+#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000
+
+#define SQ_WRAPPING_1_MASK \
+     (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_15_MASK)
+
+#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \
+     ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \
+      (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \
+      (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \
+      (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \
+      (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \
+      (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \
+      (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \
+      (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT))
+
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+     } sq_wrapping_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+     } sq_wrapping_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_1_t f;
+} sq_wrapping_1_u;
+
+
+/*
+ * SQ_VS_CONST struct
+ */
+
+#define SQ_VS_CONST_BASE_SIZE          9
+#define SQ_VS_CONST_SIZE_SIZE          9
+
+#define SQ_VS_CONST_BASE_SHIFT         0
+#define SQ_VS_CONST_SIZE_SHIFT         12
+
+#define SQ_VS_CONST_BASE_MASK          0x000001ff
+#define SQ_VS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_VS_CONST_MASK \
+     (SQ_VS_CONST_BASE_MASK | \
+      SQ_VS_CONST_SIZE_MASK)
+
+#define SQ_VS_CONST(base, size) \
+     ((base << SQ_VS_CONST_BASE_SHIFT) | \
+      (size << SQ_VS_CONST_SIZE_SHIFT))
+
+#define SQ_VS_CONST_GET_BASE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT)
+
+#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_vs_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+     } sq_vs_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_const_t f;
+} sq_vs_const_u;
+
+
+/*
+ * SQ_PS_CONST struct
+ */
+
+#define SQ_PS_CONST_BASE_SIZE          9
+#define SQ_PS_CONST_SIZE_SIZE          9
+
+#define SQ_PS_CONST_BASE_SHIFT         0
+#define SQ_PS_CONST_SIZE_SHIFT         12
+
+#define SQ_PS_CONST_BASE_MASK          0x000001ff
+#define SQ_PS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_PS_CONST_MASK \
+     (SQ_PS_CONST_BASE_MASK | \
+      SQ_PS_CONST_SIZE_MASK)
+
+#define SQ_PS_CONST(base, size) \
+     ((base << SQ_PS_CONST_BASE_SHIFT) | \
+      (size << SQ_PS_CONST_SIZE_SHIFT))
+
+#define SQ_PS_CONST_GET_BASE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT)
+
+#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_ps_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+     } sq_ps_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_const_t f;
+} sq_ps_const_u;
+
+
+/*
+ * SQ_CONTEXT_MISC struct
+ */
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000
+
+#define SQ_CONTEXT_MISC_MASK \
+     (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \
+      SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \
+      SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \
+      SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \
+      SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK)
+
+#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \
+     ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \
+      (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \
+      (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \
+      (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \
+      (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \
+      (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \
+      (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT))
+
+#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int                                : 4;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int                                : 13;
+     } sq_context_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int                                : 13;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int                                : 4;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+     } sq_context_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_context_misc_t f;
+} sq_context_misc_u;
+
+
+/*
+ * SQ_CF_RD_BASE struct
+ */
+
+#define SQ_CF_RD_BASE_RD_BASE_SIZE     3
+
+#define SQ_CF_RD_BASE_RD_BASE_SHIFT    0
+
+#define SQ_CF_RD_BASE_RD_BASE_MASK     0x00000007
+
+#define SQ_CF_RD_BASE_MASK \
+     (SQ_CF_RD_BASE_RD_BASE_MASK)
+
+#define SQ_CF_RD_BASE(rd_base) \
+     ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT))
+
+#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \
+     ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \
+     sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+          unsigned int                                : 29;
+     } sq_cf_rd_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int                                : 29;
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+     } sq_cf_rd_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rd_base_t f;
+} sq_cf_rd_base_u;
+
+
+/*
+ * SQ_DEBUG_MISC_0 struct
+ */
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000
+
+#define SQ_DEBUG_MISC_0_MASK \
+     (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK)
+
+#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \
+     ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \
+      (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \
+      (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \
+      (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT))
+
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+     } sq_debug_misc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+     } sq_debug_misc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_0_t f;
+} sq_debug_misc_0_u;
+
+
+/*
+ * SQ_DEBUG_MISC_1 struct
+ */
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000
+
+#define SQ_DEBUG_MISC_1_MASK \
+     (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \
+      SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \
+      SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \
+      SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK)
+
+#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \
+     ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \
+      (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \
+      (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \
+      (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT))
+
+#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int                                : 5;
+     } sq_debug_misc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int                                : 5;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+     } sq_debug_misc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_1_t f;
+} sq_debug_misc_1_u;
+
+
+#endif
+
+
+#if !defined (_SX_FIDDLE_H)
+#define _SX_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sx_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_TP_FIDDLE_H)
+#define _TP_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  tp_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * TC_CNTL_STATUS struct
+ */
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2
+#define TC_CNTL_STATUS_TC_BUSY_SIZE    1
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18
+#define TC_CNTL_STATUS_TC_BUSY_SHIFT   31
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000
+#define TC_CNTL_STATUS_TC_BUSY_MASK    0x80000000
+
+#define TC_CNTL_STATUS_MASK \
+     (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \
+      TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \
+      TC_CNTL_STATUS_TC_BUSY_MASK)
+
+#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \
+     ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \
+      (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \
+      (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT))
+
+#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+          unsigned int                                : 17;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+     } tc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 17;
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+     } tc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tc_cntl_status_t f;
+} tc_cntl_status_u;
+
+
+/*
+ * TCR_CHICKEN struct
+ */
+
+#define TCR_CHICKEN_SPARE_SIZE         32
+
+#define TCR_CHICKEN_SPARE_SHIFT        0
+
+#define TCR_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCR_CHICKEN_MASK \
+     (TCR_CHICKEN_SPARE_MASK)
+
+#define TCR_CHICKEN(spare) \
+     ((spare << TCR_CHICKEN_SPARE_SHIFT))
+
+#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \
+     ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT)
+
+#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \
+     tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_chicken_t f;
+} tcr_chicken_u;
+
+
+/*
+ * TCF_CHICKEN struct
+ */
+
+#define TCF_CHICKEN_SPARE_SIZE         32
+
+#define TCF_CHICKEN_SPARE_SHIFT        0
+
+#define TCF_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCF_CHICKEN_MASK \
+     (TCF_CHICKEN_SPARE_MASK)
+
+#define TCF_CHICKEN(spare) \
+     ((spare << TCF_CHICKEN_SPARE_SHIFT))
+
+#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \
+     ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT)
+
+#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \
+     tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_chicken_t f;
+} tcf_chicken_u;
+
+
+/*
+ * TCM_CHICKEN struct
+ */
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1
+#define TCM_CHICKEN_SPARE_SIZE         23
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8
+#define TCM_CHICKEN_SPARE_SHIFT        9
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100
+#define TCM_CHICKEN_SPARE_MASK         0xfffffe00
+
+#define TCM_CHICKEN_MASK \
+     (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \
+      TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \
+      TCM_CHICKEN_SPARE_MASK)
+
+#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \
+     ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \
+      (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \
+      (spare << TCM_CHICKEN_SPARE_SHIFT))
+
+#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT)
+
+#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+     } tcm_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+     } tcm_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_chicken_t f;
+} tcm_chicken_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER0_SELECT_MASK \
+     (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \
+     ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \
+     tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_select_t f;
+} tcr_perfcounter0_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER1_SELECT_MASK \
+     (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \
+     ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \
+     tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_select_t f;
+} tcr_perfcounter1_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_HI struct
+ */
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER0_HI_MASK \
+     (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \
+     ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \
+     tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_hi_t f;
+} tcr_perfcounter0_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_HI struct
+ */
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER1_HI_MASK \
+     (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \
+     ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \
+     tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_hi_t f;
+} tcr_perfcounter1_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_LOW struct
+ */
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER0_LOW_MASK \
+     (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \
+     ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \
+     tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_low_t f;
+} tcr_perfcounter0_low_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_LOW struct
+ */
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER1_LOW_MASK \
+     (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \
+     ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \
+     tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_low_t f;
+} tcr_perfcounter1_low_u;
+
+
+/*
+ * TP_TC_CLKGATE_CNTL struct
+ */
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038
+
+#define TP_TC_CLKGATE_CNTL_MASK \
+     (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \
+      TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK)
+
+#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \
+     ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \
+      (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT))
+
+#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int                                : 26;
+     } tp_tc_clkgate_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int                                : 26;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+     } tp_tc_clkgate_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp_tc_clkgate_cntl_t f;
+} tp_tc_clkgate_cntl_u;
+
+
+/*
+ * TPC_CNTL_STATUS struct
+ */
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BUSY_SIZE  1
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15
+#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17
+#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19
+#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22
+#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23
+#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25
+#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27
+#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30
+#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000
+#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000
+#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000
+#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000
+#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000
+#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000
+#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000
+#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000
+#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000
+#define TPC_CNTL_STATUS_TPC_BUSY_MASK  0x80000000
+
+#define TPC_CNTL_STATUS_MASK \
+     (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTR_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TF_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \
+      TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \
+      TPC_CNTL_STATUS_TPC_BUSY_MASK)
+
+#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \
+     ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \
+      (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \
+      (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \
+      (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \
+      (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \
+      (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \
+      (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \
+      (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \
+      (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \
+      (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \
+      (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \
+      (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \
+      (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \
+      (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \
+      (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \
+      (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \
+      (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \
+      (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \
+      (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \
+      (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \
+      (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \
+      (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \
+      (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT))
+
+#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_cntl_status_t f;
+} tpc_cntl_status_u;
+
+
+/*
+ * TPC_DEBUG0 struct
+ */
+
+#define TPC_DEBUG0_LOD_CNTL_SIZE       2
+#define TPC_DEBUG0_IC_CTR_SIZE         2
+#define TPC_DEBUG0_WALKER_CNTL_SIZE    4
+#define TPC_DEBUG0_ALIGNER_CNTL_SIZE   3
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1
+#define TPC_DEBUG0_WALKER_STATE_SIZE   10
+#define TPC_DEBUG0_ALIGNER_STATE_SIZE  2
+#define TPC_DEBUG0_REG_CLK_EN_SIZE     1
+#define TPC_DEBUG0_TPC_CLK_EN_SIZE     1
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE   1
+
+#define TPC_DEBUG0_LOD_CNTL_SHIFT      0
+#define TPC_DEBUG0_IC_CTR_SHIFT        2
+#define TPC_DEBUG0_WALKER_CNTL_SHIFT   4
+#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT  8
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12
+#define TPC_DEBUG0_WALKER_STATE_SHIFT  16
+#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26
+#define TPC_DEBUG0_REG_CLK_EN_SHIFT    29
+#define TPC_DEBUG0_TPC_CLK_EN_SHIFT    30
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT  31
+
+#define TPC_DEBUG0_LOD_CNTL_MASK       0x00000003
+#define TPC_DEBUG0_IC_CTR_MASK         0x0000000c
+#define TPC_DEBUG0_WALKER_CNTL_MASK    0x000000f0
+#define TPC_DEBUG0_ALIGNER_CNTL_MASK   0x00000700
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000
+#define TPC_DEBUG0_WALKER_STATE_MASK   0x03ff0000
+#define TPC_DEBUG0_ALIGNER_STATE_MASK  0x0c000000
+#define TPC_DEBUG0_REG_CLK_EN_MASK     0x20000000
+#define TPC_DEBUG0_TPC_CLK_EN_MASK     0x40000000
+#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK   0x80000000
+
+#define TPC_DEBUG0_MASK \
+     (TPC_DEBUG0_LOD_CNTL_MASK | \
+      TPC_DEBUG0_IC_CTR_MASK | \
+      TPC_DEBUG0_WALKER_CNTL_MASK | \
+      TPC_DEBUG0_ALIGNER_CNTL_MASK | \
+      TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \
+      TPC_DEBUG0_WALKER_STATE_MASK | \
+      TPC_DEBUG0_ALIGNER_STATE_MASK | \
+      TPC_DEBUG0_REG_CLK_EN_MASK | \
+      TPC_DEBUG0_TPC_CLK_EN_MASK | \
+      TPC_DEBUG0_SQ_TP_WAKEUP_MASK)
+
+#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \
+     ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \
+      (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \
+      (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \
+      (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \
+      (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \
+      (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \
+      (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \
+      (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \
+      (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \
+      (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT))
+
+#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 3;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+     } tpc_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+     } tpc_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug0_t f;
+} tpc_debug0_u;
+
+
+/*
+ * TPC_DEBUG1 struct
+ */
+
+#define TPC_DEBUG1_UNUSED_SIZE         1
+
+#define TPC_DEBUG1_UNUSED_SHIFT        0
+
+#define TPC_DEBUG1_UNUSED_MASK         0x00000001
+
+#define TPC_DEBUG1_MASK \
+     (TPC_DEBUG1_UNUSED_MASK)
+
+#define TPC_DEBUG1(unused) \
+     ((unused << TPC_DEBUG1_UNUSED_SHIFT))
+
+#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \
+     ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT)
+
+#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \
+     tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+          unsigned int                                : 31;
+     } tpc_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int                                : 31;
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+     } tpc_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug1_t f;
+} tpc_debug1_u;
+
+
+/*
+ * TPC_CHICKEN struct
+ */
+
+#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1
+#define TPC_CHICKEN_SPARE_SIZE         31
+
+#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0
+#define TPC_CHICKEN_SPARE_SHIFT        1
+
+#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001
+#define TPC_CHICKEN_SPARE_MASK         0xfffffffe
+
+#define TPC_CHICKEN_MASK \
+     (TPC_CHICKEN_BLEND_PRECISION_MASK | \
+      TPC_CHICKEN_SPARE_MASK)
+
+#define TPC_CHICKEN(blend_precision, spare) \
+     ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \
+      (spare << TPC_CHICKEN_SPARE_SHIFT))
+
+#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT)
+
+#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+     } tpc_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+     } tpc_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_chicken_t f;
+} tpc_chicken_u;
+
+
+/*
+ * TP0_CNTL_STATUS struct
+ */
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1
+#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TP_BUSY_SIZE   1
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14
+#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16
+#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17
+#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18
+#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19
+#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21
+#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23
+#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25
+#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27
+#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29
+#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30
+#define TP0_CNTL_STATUS_TP_BUSY_SHIFT  31
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200
+#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000
+#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000
+#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000
+#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000
+#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000
+#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000
+#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000
+#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000
+#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000
+#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000
+#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000
+#define TP0_CNTL_STATUS_TP_BUSY_MASK   0x80000000
+
+#define TP0_CNTL_STATUS_MASK \
+     (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_IN_LC_RTS_MASK | \
+      TP0_CNTL_STATUS_LC_LA_RTS_MASK | \
+      TP0_CNTL_STATUS_LA_FL_RTS_MASK | \
+      TP0_CNTL_STATUS_FL_TA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \
+      TP0_CNTL_STATUS_TB_TO_RTS_MASK | \
+      TP0_CNTL_STATUS_TP_BUSY_MASK)
+
+#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \
+     ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \
+      (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \
+      (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \
+      (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \
+      (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \
+      (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \
+      (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \
+      (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \
+      (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \
+      (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \
+      (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \
+      (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \
+      (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \
+      (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \
+      (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \
+      (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \
+      (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \
+      (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \
+      (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \
+      (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \
+      (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \
+      (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \
+      (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \
+      (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \
+      (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \
+      (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \
+      (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \
+      (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \
+      (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \
+      (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT))
+
+#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_cntl_status_t f;
+} tp0_cntl_status_u;
+
+
+/*
+ * TP0_DEBUG struct
+ */
+
+#define TP0_DEBUG_Q_LOD_CNTL_SIZE      2
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE  1
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17
+#define TP0_DEBUG_REG_CLK_EN_SIZE      1
+#define TP0_DEBUG_PERF_CLK_EN_SIZE     1
+#define TP0_DEBUG_TP_CLK_EN_SIZE       1
+#define TP0_DEBUG_Q_WALKER_CNTL_SIZE   4
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE  3
+
+#define TP0_DEBUG_Q_LOD_CNTL_SHIFT     0
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4
+#define TP0_DEBUG_REG_CLK_EN_SHIFT     21
+#define TP0_DEBUG_PERF_CLK_EN_SHIFT    22
+#define TP0_DEBUG_TP_CLK_EN_SHIFT      23
+#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT  24
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28
+
+#define TP0_DEBUG_Q_LOD_CNTL_MASK      0x00000003
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK  0x00000008
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0
+#define TP0_DEBUG_REG_CLK_EN_MASK      0x00200000
+#define TP0_DEBUG_PERF_CLK_EN_MASK     0x00400000
+#define TP0_DEBUG_TP_CLK_EN_MASK       0x00800000
+#define TP0_DEBUG_Q_WALKER_CNTL_MASK   0x0f000000
+#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK  0x70000000
+
+#define TP0_DEBUG_MASK \
+     (TP0_DEBUG_Q_LOD_CNTL_MASK | \
+      TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \
+      TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \
+      TP0_DEBUG_REG_CLK_EN_MASK | \
+      TP0_DEBUG_PERF_CLK_EN_MASK | \
+      TP0_DEBUG_TP_CLK_EN_MASK | \
+      TP0_DEBUG_Q_WALKER_CNTL_MASK | \
+      TP0_DEBUG_Q_ALIGNER_CNTL_MASK)
+
+#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \
+     ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \
+      (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \
+      (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \
+      (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \
+      (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \
+      (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \
+      (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \
+      (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT))
+
+#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+     } tp0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int                                : 1;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+     } tp0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_debug_t f;
+} tp0_debug_u;
+
+
+/*
+ * TP0_CHICKEN struct
+ */
+
+#define TP0_CHICKEN_TT_MODE_SIZE       1
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1
+#define TP0_CHICKEN_SPARE_SIZE         30
+
+#define TP0_CHICKEN_TT_MODE_SHIFT      0
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1
+#define TP0_CHICKEN_SPARE_SHIFT        2
+
+#define TP0_CHICKEN_TT_MODE_MASK       0x00000001
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002
+#define TP0_CHICKEN_SPARE_MASK         0xfffffffc
+
+#define TP0_CHICKEN_MASK \
+     (TP0_CHICKEN_TT_MODE_MASK | \
+      TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \
+      TP0_CHICKEN_SPARE_MASK)
+
+#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \
+     ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \
+      (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \
+      (spare << TP0_CHICKEN_SPARE_SHIFT))
+
+#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT)
+
+#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+     } tp0_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+     } tp0_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_chicken_t f;
+} tp0_chicken_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER0_SELECT_MASK \
+     (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \
+     ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \
+     tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_select_t f;
+} tp0_perfcounter0_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_HI struct
+ */
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER0_HI_MASK \
+     (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \
+     ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \
+     tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_hi_t f;
+} tp0_perfcounter0_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_LOW struct
+ */
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER0_LOW_MASK \
+     (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \
+     ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \
+     tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_low_t f;
+} tp0_perfcounter0_low_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER1_SELECT_MASK \
+     (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \
+     ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \
+     tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_select_t f;
+} tp0_perfcounter1_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_HI struct
+ */
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER1_HI_MASK \
+     (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \
+     ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \
+     tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_hi_t f;
+} tp0_perfcounter1_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_LOW struct
+ */
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER1_LOW_MASK \
+     (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \
+     ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \
+     tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_low_t f;
+} tp0_perfcounter1_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER0_SELECT_MASK \
+     (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \
+     ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \
+     tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_select_t f;
+} tcm_perfcounter0_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER1_SELECT_MASK \
+     (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \
+     ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \
+     tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_select_t f;
+} tcm_perfcounter1_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_HI struct
+ */
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER0_HI_MASK \
+     (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \
+     ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \
+     tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_hi_t f;
+} tcm_perfcounter0_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_HI struct
+ */
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER1_HI_MASK \
+     (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \
+     ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \
+     tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_hi_t f;
+} tcm_perfcounter1_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_LOW struct
+ */
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER0_LOW_MASK \
+     (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \
+     ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \
+     tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_low_t f;
+} tcm_perfcounter0_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_LOW struct
+ */
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER1_LOW_MASK \
+     (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \
+     ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \
+     tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_low_t f;
+} tcm_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER0_SELECT_MASK \
+     (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \
+     ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \
+     tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_select_t f;
+} tcf_perfcounter0_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER1_SELECT_MASK \
+     (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \
+     ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \
+     tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_select_t f;
+} tcf_perfcounter1_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER2_SELECT_MASK \
+     (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \
+     ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \
+     tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_select_t f;
+} tcf_perfcounter2_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER3_SELECT_MASK \
+     (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \
+     ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \
+     tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_select_t f;
+} tcf_perfcounter3_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER4_SELECT_MASK \
+     (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \
+     ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \
+     tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter4_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter4_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_select_t f;
+} tcf_perfcounter4_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER5_SELECT_MASK \
+     (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \
+     ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \
+     tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter5_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter5_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_select_t f;
+} tcf_perfcounter5_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER6_SELECT_MASK \
+     (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \
+     ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \
+     tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter6_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter6_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_select_t f;
+} tcf_perfcounter6_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER7_SELECT_MASK \
+     (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \
+     ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \
+     tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter7_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter7_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_select_t f;
+} tcf_perfcounter7_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER8_SELECT_MASK \
+     (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \
+     ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \
+     tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter8_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter8_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_select_t f;
+} tcf_perfcounter8_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER9_SELECT_MASK \
+     (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \
+     ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \
+     tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter9_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter9_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_select_t f;
+} tcf_perfcounter9_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER10_SELECT_MASK \
+     (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \
+     ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \
+     tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter10_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter10_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_select_t f;
+} tcf_perfcounter10_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER11_SELECT_MASK \
+     (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \
+     ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \
+     tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter11_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter11_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_select_t f;
+} tcf_perfcounter11_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_HI struct
+ */
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER0_HI_MASK \
+     (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \
+     ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \
+     tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_hi_t f;
+} tcf_perfcounter0_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_HI struct
+ */
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER1_HI_MASK \
+     (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \
+     ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \
+     tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_hi_t f;
+} tcf_perfcounter1_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_HI struct
+ */
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER2_HI_MASK \
+     (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \
+     ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \
+     tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_hi_t f;
+} tcf_perfcounter2_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_HI struct
+ */
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER3_HI_MASK \
+     (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \
+     ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \
+     tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_hi_t f;
+} tcf_perfcounter3_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_HI struct
+ */
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER4_HI_MASK \
+     (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \
+     ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \
+     tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter4_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter4_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_hi_t f;
+} tcf_perfcounter4_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_HI struct
+ */
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER5_HI_MASK \
+     (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \
+     ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \
+     tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter5_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter5_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_hi_t f;
+} tcf_perfcounter5_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_HI struct
+ */
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER6_HI_MASK \
+     (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \
+     ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \
+     tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter6_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter6_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_hi_t f;
+} tcf_perfcounter6_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_HI struct
+ */
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER7_HI_MASK \
+     (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \
+     ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \
+     tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter7_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter7_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_hi_t f;
+} tcf_perfcounter7_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_HI struct
+ */
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER8_HI_MASK \
+     (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \
+     ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \
+     tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter8_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter8_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_hi_t f;
+} tcf_perfcounter8_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_HI struct
+ */
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER9_HI_MASK \
+     (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \
+     ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \
+     tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter9_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter9_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_hi_t f;
+} tcf_perfcounter9_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_HI struct
+ */
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER10_HI_MASK \
+     (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \
+     ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \
+     tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter10_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter10_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_hi_t f;
+} tcf_perfcounter10_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_HI struct
+ */
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER11_HI_MASK \
+     (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \
+     ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \
+     tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter11_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter11_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_hi_t f;
+} tcf_perfcounter11_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_LOW struct
+ */
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER0_LOW_MASK \
+     (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \
+     ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \
+     tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_low_t f;
+} tcf_perfcounter0_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_LOW struct
+ */
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER1_LOW_MASK \
+     (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \
+     ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \
+     tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_low_t f;
+} tcf_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_LOW struct
+ */
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER2_LOW_MASK \
+     (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \
+     ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \
+     tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_low_t f;
+} tcf_perfcounter2_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_LOW struct
+ */
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER3_LOW_MASK \
+     (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \
+     ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \
+     tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_low_t f;
+} tcf_perfcounter3_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_LOW struct
+ */
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER4_LOW_MASK \
+     (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \
+     ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \
+     tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_low_t f;
+} tcf_perfcounter4_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_LOW struct
+ */
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER5_LOW_MASK \
+     (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \
+     ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \
+     tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_low_t f;
+} tcf_perfcounter5_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_LOW struct
+ */
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER6_LOW_MASK \
+     (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \
+     ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \
+     tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_low_t f;
+} tcf_perfcounter6_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_LOW struct
+ */
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER7_LOW_MASK \
+     (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \
+     ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \
+     tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_low_t f;
+} tcf_perfcounter7_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_LOW struct
+ */
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER8_LOW_MASK \
+     (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \
+     ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \
+     tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_low_t f;
+} tcf_perfcounter8_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_LOW struct
+ */
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER9_LOW_MASK \
+     (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \
+     ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \
+     tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_low_t f;
+} tcf_perfcounter9_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_LOW struct
+ */
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER10_LOW_MASK \
+     (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \
+     ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \
+     tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_low_t f;
+} tcf_perfcounter10_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_LOW struct
+ */
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER11_LOW_MASK \
+     (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \
+     ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \
+     tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_low_t f;
+} tcf_perfcounter11_low_u;
+
+
+/*
+ * TCF_DEBUG struct
+ */
+
+#define TCF_DEBUG_not_MH_TC_rtr_SIZE   1
+#define TCF_DEBUG_TC_MH_send_SIZE      1
+#define TCF_DEBUG_not_FG0_rtr_SIZE     1
+#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1
+#define TCF_DEBUG_TCB_ff_stall_SIZE    1
+#define TCF_DEBUG_TCB_miss_stall_SIZE  1
+#define TCF_DEBUG_TCA_TCB_stall_SIZE   1
+#define TCF_DEBUG_PF0_stall_SIZE       1
+#define TCF_DEBUG_TP0_full_SIZE        1
+#define TCF_DEBUG_TPC_full_SIZE        1
+#define TCF_DEBUG_not_TPC_rtr_SIZE     1
+#define TCF_DEBUG_tca_state_rts_SIZE   1
+#define TCF_DEBUG_tca_rts_SIZE         1
+
+#define TCF_DEBUG_not_MH_TC_rtr_SHIFT  6
+#define TCF_DEBUG_TC_MH_send_SHIFT     7
+#define TCF_DEBUG_not_FG0_rtr_SHIFT    8
+#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12
+#define TCF_DEBUG_TCB_ff_stall_SHIFT   13
+#define TCF_DEBUG_TCB_miss_stall_SHIFT 14
+#define TCF_DEBUG_TCA_TCB_stall_SHIFT  15
+#define TCF_DEBUG_PF0_stall_SHIFT      16
+#define TCF_DEBUG_TP0_full_SHIFT       20
+#define TCF_DEBUG_TPC_full_SHIFT       24
+#define TCF_DEBUG_not_TPC_rtr_SHIFT    25
+#define TCF_DEBUG_tca_state_rts_SHIFT  26
+#define TCF_DEBUG_tca_rts_SHIFT        27
+
+#define TCF_DEBUG_not_MH_TC_rtr_MASK   0x00000040
+#define TCF_DEBUG_TC_MH_send_MASK      0x00000080
+#define TCF_DEBUG_not_FG0_rtr_MASK     0x00000100
+#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000
+#define TCF_DEBUG_TCB_ff_stall_MASK    0x00002000
+#define TCF_DEBUG_TCB_miss_stall_MASK  0x00004000
+#define TCF_DEBUG_TCA_TCB_stall_MASK   0x00008000
+#define TCF_DEBUG_PF0_stall_MASK       0x00010000
+#define TCF_DEBUG_TP0_full_MASK        0x00100000
+#define TCF_DEBUG_TPC_full_MASK        0x01000000
+#define TCF_DEBUG_not_TPC_rtr_MASK     0x02000000
+#define TCF_DEBUG_tca_state_rts_MASK   0x04000000
+#define TCF_DEBUG_tca_rts_MASK         0x08000000
+
+#define TCF_DEBUG_MASK \
+     (TCF_DEBUG_not_MH_TC_rtr_MASK | \
+      TCF_DEBUG_TC_MH_send_MASK | \
+      TCF_DEBUG_not_FG0_rtr_MASK | \
+      TCF_DEBUG_not_TCB_TCO_rtr_MASK | \
+      TCF_DEBUG_TCB_ff_stall_MASK | \
+      TCF_DEBUG_TCB_miss_stall_MASK | \
+      TCF_DEBUG_TCA_TCB_stall_MASK | \
+      TCF_DEBUG_PF0_stall_MASK | \
+      TCF_DEBUG_TP0_full_MASK | \
+      TCF_DEBUG_TPC_full_MASK | \
+      TCF_DEBUG_not_TPC_rtr_MASK | \
+      TCF_DEBUG_tca_state_rts_MASK | \
+      TCF_DEBUG_tca_rts_MASK)
+
+#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \
+     ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \
+      (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \
+      (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \
+      (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \
+      (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \
+      (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \
+      (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \
+      (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \
+      (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \
+      (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \
+      (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \
+      (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \
+      (tca_rts << TCF_DEBUG_tca_rts_SHIFT))
+
+#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_GET_TP0_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_GET_TPC_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_GET_tca_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT)
+
+#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 6;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int                                : 4;
+     } tcf_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 4;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int                                : 6;
+     } tcf_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_debug_t f;
+} tcf_debug_u;
+
+
+/*
+ * TCA_FIFO_DEBUG struct
+ */
+
+#define TCA_FIFO_DEBUG_tp0_full_SIZE   1
+#define TCA_FIFO_DEBUG_tpc_full_SIZE   1
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1
+#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1
+#define TCA_FIFO_DEBUG_FW_full_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1
+#define TCA_FIFO_DEBUG_FW_rts0_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1
+
+#define TCA_FIFO_DEBUG_tp0_full_SHIFT  0
+#define TCA_FIFO_DEBUG_tpc_full_SHIFT  4
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5
+#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6
+#define TCA_FIFO_DEBUG_FW_full_SHIFT   7
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8
+#define TCA_FIFO_DEBUG_FW_rts0_SHIFT   12
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17
+
+#define TCA_FIFO_DEBUG_tp0_full_MASK   0x00000001
+#define TCA_FIFO_DEBUG_tpc_full_MASK   0x00000010
+#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020
+#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040
+#define TCA_FIFO_DEBUG_FW_full_MASK    0x00000080
+#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100
+#define TCA_FIFO_DEBUG_FW_rts0_MASK    0x00001000
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000
+#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000
+
+#define TCA_FIFO_DEBUG_MASK \
+     (TCA_FIFO_DEBUG_tp0_full_MASK | \
+      TCA_FIFO_DEBUG_tpc_full_MASK | \
+      TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \
+      TCA_FIFO_DEBUG_load_tp_fifos_MASK | \
+      TCA_FIFO_DEBUG_FW_full_MASK | \
+      TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \
+      TCA_FIFO_DEBUG_FW_rts0_MASK | \
+      TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \
+      TCA_FIFO_DEBUG_FW_tpc_rts_MASK)
+
+#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \
+     ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \
+      (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \
+      (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \
+      (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \
+      (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \
+      (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \
+      (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \
+      (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \
+      (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT))
+
+#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int                                : 14;
+     } tca_fifo_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int                                : 14;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+     } tca_fifo_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_fifo_debug_t f;
+} tca_fifo_debug_u;
+
+
+/*
+ * TCA_PROBE_DEBUG struct
+ */
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001
+
+#define TCA_PROBE_DEBUG_MASK \
+     (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK)
+
+#define TCA_PROBE_DEBUG(probefilter_stall) \
+     ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT))
+
+#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \
+     ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \
+     tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+          unsigned int                                : 31;
+     } tca_probe_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int                                : 31;
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+     } tca_probe_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_probe_debug_t f;
+} tca_probe_debug_u;
+
+
+/*
+ * TCA_TPC_DEBUG struct
+ */
+
+#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1
+#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1
+
+#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12
+#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13
+
+#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000
+#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000
+
+#define TCA_TPC_DEBUG_MASK \
+     (TCA_TPC_DEBUG_captue_state_rts_MASK | \
+      TCA_TPC_DEBUG_capture_tca_rts_MASK)
+
+#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \
+     ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \
+      (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT))
+
+#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 12;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int                                : 18;
+     } tca_tpc_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 18;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int                                : 12;
+     } tca_tpc_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_tpc_debug_t f;
+} tca_tpc_debug_u;
+
+
+/*
+ * TCB_CORE_DEBUG struct
+ */
+
+#define TCB_CORE_DEBUG_access512_SIZE  1
+#define TCB_CORE_DEBUG_tiled_SIZE      1
+#define TCB_CORE_DEBUG_opcode_SIZE     3
+#define TCB_CORE_DEBUG_format_SIZE     6
+#define TCB_CORE_DEBUG_sector_format_SIZE 5
+#define TCB_CORE_DEBUG_sector_format512_SIZE 3
+
+#define TCB_CORE_DEBUG_access512_SHIFT 0
+#define TCB_CORE_DEBUG_tiled_SHIFT     1
+#define TCB_CORE_DEBUG_opcode_SHIFT    4
+#define TCB_CORE_DEBUG_format_SHIFT    8
+#define TCB_CORE_DEBUG_sector_format_SHIFT 16
+#define TCB_CORE_DEBUG_sector_format512_SHIFT 24
+
+#define TCB_CORE_DEBUG_access512_MASK  0x00000001
+#define TCB_CORE_DEBUG_tiled_MASK      0x00000002
+#define TCB_CORE_DEBUG_opcode_MASK     0x00000070
+#define TCB_CORE_DEBUG_format_MASK     0x00003f00
+#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000
+#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000
+
+#define TCB_CORE_DEBUG_MASK \
+     (TCB_CORE_DEBUG_access512_MASK | \
+      TCB_CORE_DEBUG_tiled_MASK | \
+      TCB_CORE_DEBUG_opcode_MASK | \
+      TCB_CORE_DEBUG_format_MASK | \
+      TCB_CORE_DEBUG_sector_format_MASK | \
+      TCB_CORE_DEBUG_sector_format512_MASK)
+
+#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \
+     ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \
+      (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \
+      (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \
+      (format << TCB_CORE_DEBUG_format_SHIFT) | \
+      (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \
+      (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT))
+
+#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int                                : 2;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 1;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 5;
+     } tcb_core_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int                                : 5;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 2;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+     } tcb_core_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_core_debug_t f;
+} tcb_core_debug_u;
+
+
+/*
+ * TCB_TAG0_DEBUG struct
+ */
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG0_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG0_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG0_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG0_DEBUG_MASK \
+     (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG0_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG0_DEBUG_miss_stall_MASK | \
+      TCB_TAG0_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG0_DEBUG_max_misses_MASK)
+
+#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+     } tcb_tag0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag0_debug_t f;
+} tcb_tag0_debug_u;
+
+
+/*
+ * TCB_TAG1_DEBUG struct
+ */
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG1_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG1_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG1_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG1_DEBUG_MASK \
+     (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG1_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG1_DEBUG_miss_stall_MASK | \
+      TCB_TAG1_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG1_DEBUG_max_misses_MASK)
+
+#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+     } tcb_tag1_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag1_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag1_debug_t f;
+} tcb_tag1_debug_u;
+
+
+/*
+ * TCB_TAG2_DEBUG struct
+ */
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG2_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG2_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG2_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG2_DEBUG_MASK \
+     (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG2_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG2_DEBUG_miss_stall_MASK | \
+      TCB_TAG2_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG2_DEBUG_max_misses_MASK)
+
+#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+     } tcb_tag2_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag2_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag2_debug_t f;
+} tcb_tag2_debug_u;
+
+
+/*
+ * TCB_TAG3_DEBUG struct
+ */
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG3_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG3_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG3_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG3_DEBUG_MASK \
+     (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG3_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG3_DEBUG_miss_stall_MASK | \
+      TCB_TAG3_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG3_DEBUG_max_misses_MASK)
+
+#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+     } tcb_tag3_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag3_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag3_debug_t f;
+} tcb_tag3_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \
+     (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \
+     ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \
+      (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \
+      (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \
+      (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \
+      (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \
+      (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \
+      (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \
+      (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT))
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int                                : 3;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int                                : 3;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_sector_walker0_debug_t f;
+} tcb_fetch_gen_sector_walker0_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_WALKER_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \
+     (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \
+     ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \
+      (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \
+      (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \
+      (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \
+      (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \
+      (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT))
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 4;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int                                : 12;
+     } tcb_fetch_gen_walker_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 12;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int                                : 4;
+     } tcb_fetch_gen_walker_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_walker_debug_t f;
+} tcb_fetch_gen_walker_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_PIPE0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \
+     (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \
+     ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \
+      (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \
+      (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \
+      (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \
+      (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \
+      (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \
+      (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \
+      (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \
+      (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \
+      (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \
+      (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT))
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_pipe0_debug_t f;
+} tcb_fetch_gen_pipe0_debug_u;
+
+
+/*
+ * TCD_INPUT0_DEBUG struct
+ */
+
+#define TCD_INPUT0_DEBUG_empty_SIZE    1
+#define TCD_INPUT0_DEBUG_full_SIZE     1
+#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_cnt_q1_SIZE   2
+#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_ip_send_SIZE  1
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1
+
+#define TCD_INPUT0_DEBUG_empty_SHIFT   16
+#define TCD_INPUT0_DEBUG_full_SHIFT    17
+#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20
+#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT  21
+#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23
+#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26
+
+#define TCD_INPUT0_DEBUG_empty_MASK    0x00010000
+#define TCD_INPUT0_DEBUG_full_MASK     0x00020000
+#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000
+#define TCD_INPUT0_DEBUG_cnt_q1_MASK   0x00600000
+#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000
+#define TCD_INPUT0_DEBUG_ip_send_MASK  0x01000000
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000
+#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000
+
+#define TCD_INPUT0_DEBUG_MASK \
+     (TCD_INPUT0_DEBUG_empty_MASK | \
+      TCD_INPUT0_DEBUG_full_MASK | \
+      TCD_INPUT0_DEBUG_valid_q1_MASK | \
+      TCD_INPUT0_DEBUG_cnt_q1_MASK | \
+      TCD_INPUT0_DEBUG_last_send_q1_MASK | \
+      TCD_INPUT0_DEBUG_ip_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_busy_MASK)
+
+#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \
+     ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \
+      (full << TCD_INPUT0_DEBUG_full_SHIFT) | \
+      (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \
+      (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \
+      (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \
+      (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \
+      (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \
+      (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT))
+
+#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 16;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int                                : 2;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int                                : 5;
+     } tcd_input0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 5;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int                                : 2;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int                                : 16;
+     } tcd_input0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_input0_debug_t f;
+} tcd_input0_debug_u;
+
+
+/*
+ * TCD_DEGAMMA_DEBUG struct
+ */
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040
+
+#define TCD_DEGAMMA_DEBUG_MASK \
+     (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK)
+
+#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \
+     ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \
+      (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \
+      (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \
+      (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \
+      (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \
+      (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT))
+
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int                                : 25;
+     } tcd_degamma_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int                                : 25;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+     } tcd_degamma_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_degamma_debug_t f;
+} tcd_degamma_debug_u;
+
+
+/*
+ * TCD_DXTMUX_SCTARB_DEBUG struct
+ */
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000
+
+#define TCD_DXTMUX_SCTARB_DEBUG_MASK \
+     (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK)
+
+#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \
+     ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \
+      (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \
+      (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \
+      (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \
+      (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \
+      (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \
+      (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \
+      (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \
+      (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT))
+
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 9;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int                                : 2;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 2;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int                                : 9;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtmux_sctarb_debug_t f;
+} tcd_dxtmux_sctarb_debug_u;
+
+
+/*
+ * TCD_DXTC_ARB_DEBUG struct
+ */
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4
+#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010
+#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000
+
+#define TCD_DXTC_ARB_DEBUG_MASK \
+     (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \
+      TCD_DXTC_ARB_DEBUG_pstate_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK)
+
+#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \
+     ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \
+      (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \
+      (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \
+      (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \
+      (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \
+      (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \
+      (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \
+      (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \
+      (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT))
+
+#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int                                : 4;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+     } tcd_dxtc_arb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int                                : 4;
+     } tcd_dxtc_arb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtc_arb_debug_t f;
+} tcd_dxtc_arb_debug_u;
+
+
+/*
+ * TCD_STALLS_DEBUG struct
+ */
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000
+#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000
+
+#define TCD_STALLS_DEBUG_MASK \
+     (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_incoming_rtr_MASK)
+
+#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \
+     ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \
+      (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \
+      (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \
+      (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \
+      (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \
+      (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT))
+
+#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int                                : 10;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+     } tcd_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int                                : 10;
+     } tcd_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_stalls_debug_t f;
+} tcd_stalls_debug_u;
+
+
+/*
+ * TCO_STALLS_DEBUG struct
+ */
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080
+
+#define TCO_STALLS_DEBUG_MASK \
+     (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK)
+
+#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \
+     ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \
+      (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \
+      (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT))
+
+#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 5;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int                                : 24;
+     } tco_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 24;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int                                : 5;
+     } tco_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_stalls_debug_t f;
+} tco_stalls_debug_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG0 struct
+ */
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1
+#define TCO_QUAD0_DEBUG0_busy_SIZE     1
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16
+#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29
+#define TCO_QUAD0_DEBUG0_busy_SHIFT    30
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000
+#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000
+#define TCO_QUAD0_DEBUG0_busy_MASK     0x40000000
+
+#define TCO_QUAD0_DEBUG0_MASK \
+     (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \
+      TCO_QUAD0_DEBUG0_read_cache_q_MASK | \
+      TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \
+      TCO_QUAD0_DEBUG0_busy_MASK)
+
+#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \
+     ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \
+      (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \
+      (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \
+      (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \
+      (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \
+      (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \
+      (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \
+      (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \
+      (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \
+      (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \
+      (busy << TCO_QUAD0_DEBUG0_busy_SHIFT))
+
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int                                : 2;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int                                : 1;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 2;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+     } tco_quad0_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug0_t f;
+} tco_quad0_debug0_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG1 struct
+ */
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_empty_SIZE    1
+#define TCO_QUAD0_DEBUG1_full_SIZE     1
+#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0
+#define TCO_QUAD0_DEBUG1_empty_SHIFT   1
+#define TCO_QUAD0_DEBUG1_full_SHIFT    2
+#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001
+#define TCO_QUAD0_DEBUG1_empty_MASK    0x00000002
+#define TCO_QUAD0_DEBUG1_full_MASK     0x00000004
+#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800
+#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000
+#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000
+
+#define TCO_QUAD0_DEBUG1_MASK \
+     (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_empty_MASK | \
+      TCO_QUAD0_DEBUG1_full_MASK | \
+      TCO_QUAD0_DEBUG1_write_enable_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \
+      TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \
+      TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK)
+
+#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \
+     ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \
+      (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \
+      (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \
+      (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \
+      (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \
+      (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \
+      (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \
+      (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \
+      (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \
+      (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \
+      (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \
+      (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \
+      (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT))
+
+#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int                                : 2;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int                                : 1;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int                                : 2;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+     } tco_quad0_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug1_t f;
+} tco_quad0_debug1_u;
+
+
+#endif
+
+
+#if !defined (_TC_FIDDLE_H)
+#define _TC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  tc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_SC_FIDDLE_H)
+#define _SC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_BC_FIDDLE_H)
+#define _BC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  bc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * RB_SURFACE_INFO struct
+ */
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff
+#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000
+
+#define RB_SURFACE_INFO_MASK \
+     (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \
+      RB_SURFACE_INFO_MSAA_SAMPLES_MASK)
+
+#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \
+     ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \
+      (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT))
+
+#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int                                : 16;
+     } rb_surface_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int                                : 16;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+     } rb_surface_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_surface_info_t f;
+} rb_surface_info_u;
+
+
+/*
+ * RB_COLOR_INFO struct
+ */
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2
+#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1
+#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2
+#define RB_COLOR_INFO_COLOR_SWAP_SIZE  2
+#define RB_COLOR_INFO_COLOR_BASE_SIZE  20
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4
+#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6
+#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7
+#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9
+#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12
+
+#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030
+#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040
+#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180
+#define RB_COLOR_INFO_COLOR_SWAP_MASK  0x00000600
+#define RB_COLOR_INFO_COLOR_BASE_MASK  0xfffff000
+
+#define RB_COLOR_INFO_MASK \
+     (RB_COLOR_INFO_COLOR_FORMAT_MASK | \
+      RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \
+      RB_COLOR_INFO_COLOR_LINEAR_MASK | \
+      RB_COLOR_INFO_COLOR_ENDIAN_MASK | \
+      RB_COLOR_INFO_COLOR_SWAP_MASK | \
+      RB_COLOR_INFO_COLOR_BASE_MASK)
+
+#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \
+     ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \
+      (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \
+      (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \
+      (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \
+      (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \
+      (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT))
+
+#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+     } rb_color_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+     } rb_color_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_info_t f;
+} rb_color_info_u;
+
+
+/*
+ * RB_DEPTH_INFO struct
+ */
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1
+#define RB_DEPTH_INFO_DEPTH_BASE_SIZE  20
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0
+#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001
+#define RB_DEPTH_INFO_DEPTH_BASE_MASK  0xfffff000
+
+#define RB_DEPTH_INFO_MASK \
+     (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \
+      RB_DEPTH_INFO_DEPTH_BASE_MASK)
+
+#define RB_DEPTH_INFO(depth_format, depth_base) \
+     ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \
+      (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT))
+
+#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+     } rb_depth_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+     } rb_depth_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_info_t f;
+} rb_depth_info_u;
+
+
+/*
+ * RB_STENCILREFMASK struct
+ */
+
+#define RB_STENCILREFMASK_STENCILREF_SIZE 8
+#define RB_STENCILREFMASK_STENCILMASK_SIZE 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8
+#define RB_STENCILREFMASK_RESERVED0_SIZE 1
+#define RB_STENCILREFMASK_RESERVED1_SIZE 1
+
+#define RB_STENCILREFMASK_STENCILREF_SHIFT 0
+#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16
+#define RB_STENCILREFMASK_RESERVED0_SHIFT 24
+#define RB_STENCILREFMASK_RESERVED1_SHIFT 25
+
+#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff
+#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00
+#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000
+#define RB_STENCILREFMASK_RESERVED0_MASK 0x01000000
+#define RB_STENCILREFMASK_RESERVED1_MASK 0x02000000
+
+#define RB_STENCILREFMASK_MASK \
+     (RB_STENCILREFMASK_STENCILREF_MASK | \
+      RB_STENCILREFMASK_STENCILMASK_MASK | \
+      RB_STENCILREFMASK_STENCILWRITEMASK_MASK | \
+      RB_STENCILREFMASK_RESERVED0_MASK | \
+      RB_STENCILREFMASK_RESERVED1_MASK)
+
+#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask, reserved0, reserved1) \
+     ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \
+      (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \
+      (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) | \
+      (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) | \
+      (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT))
+
+#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_RESERVED0(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED0_MASK) >> RB_STENCILREFMASK_RESERVED0_SHIFT)
+#define RB_STENCILREFMASK_GET_RESERVED1(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED1_MASK) >> RB_STENCILREFMASK_RESERVED1_SHIFT)
+
+#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_RESERVED0(rb_stencilrefmask_reg, reserved0) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED0_MASK) | (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT)
+#define RB_STENCILREFMASK_SET_RESERVED1(rb_stencilrefmask_reg, reserved1) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED1_MASK) | (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int reserved0                      : RB_STENCILREFMASK_RESERVED0_SIZE;
+          unsigned int reserved1                      : RB_STENCILREFMASK_RESERVED1_SIZE;
+          unsigned int                                : 6;
+     } rb_stencilrefmask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int                                : 6;
+          unsigned int reserved1                      : RB_STENCILREFMASK_RESERVED1_SIZE;
+          unsigned int reserved0                      : RB_STENCILREFMASK_RESERVED0_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+     } rb_stencilrefmask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_t f;
+} rb_stencilrefmask_u;
+
+
+/*
+ * RB_ALPHA_REF struct
+ */
+
+#define RB_ALPHA_REF_ALPHA_REF_SIZE    32
+
+#define RB_ALPHA_REF_ALPHA_REF_SHIFT   0
+
+#define RB_ALPHA_REF_ALPHA_REF_MASK    0xffffffff
+
+#define RB_ALPHA_REF_MASK \
+     (RB_ALPHA_REF_ALPHA_REF_MASK)
+
+#define RB_ALPHA_REF(alpha_ref) \
+     ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT))
+
+#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \
+     ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \
+     rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_alpha_ref_t f;
+} rb_alpha_ref_u;
+
+
+/*
+ * RB_COLOR_MASK struct
+ */
+
+#define RB_COLOR_MASK_WRITE_RED_SIZE   1
+#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1
+#define RB_COLOR_MASK_WRITE_BLUE_SIZE  1
+#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1
+#define RB_COLOR_MASK_RESERVED2_SIZE   1
+#define RB_COLOR_MASK_RESERVED3_SIZE   1
+
+#define RB_COLOR_MASK_WRITE_RED_SHIFT  0
+#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1
+#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2
+#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3
+#define RB_COLOR_MASK_RESERVED2_SHIFT  4
+#define RB_COLOR_MASK_RESERVED3_SHIFT  5
+
+#define RB_COLOR_MASK_WRITE_RED_MASK   0x00000001
+#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002
+#define RB_COLOR_MASK_WRITE_BLUE_MASK  0x00000004
+#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008
+#define RB_COLOR_MASK_RESERVED2_MASK   0x00000010
+#define RB_COLOR_MASK_RESERVED3_MASK   0x00000020
+
+#define RB_COLOR_MASK_MASK \
+     (RB_COLOR_MASK_WRITE_RED_MASK | \
+      RB_COLOR_MASK_WRITE_GREEN_MASK | \
+      RB_COLOR_MASK_WRITE_BLUE_MASK | \
+      RB_COLOR_MASK_WRITE_ALPHA_MASK | \
+      RB_COLOR_MASK_RESERVED2_MASK | \
+      RB_COLOR_MASK_RESERVED3_MASK)
+
+#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha, reserved2, reserved3) \
+     ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \
+      (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \
+      (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \
+      (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) | \
+      (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) | \
+      (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT))
+
+#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+#define RB_COLOR_MASK_GET_RESERVED2(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_RESERVED2_MASK) >> RB_COLOR_MASK_RESERVED2_SHIFT)
+#define RB_COLOR_MASK_GET_RESERVED3(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_RESERVED3_MASK) >> RB_COLOR_MASK_RESERVED3_SHIFT)
+
+#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+#define RB_COLOR_MASK_SET_RESERVED2(rb_color_mask_reg, reserved2) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED2_MASK) | (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT)
+#define RB_COLOR_MASK_SET_RESERVED3(rb_color_mask_reg, reserved3) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED3_MASK) | (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int reserved2                      : RB_COLOR_MASK_RESERVED2_SIZE;
+          unsigned int reserved3                      : RB_COLOR_MASK_RESERVED3_SIZE;
+          unsigned int                                : 26;
+     } rb_color_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int                                : 26;
+          unsigned int reserved3                      : RB_COLOR_MASK_RESERVED3_SIZE;
+          unsigned int reserved2                      : RB_COLOR_MASK_RESERVED2_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+     } rb_color_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_mask_t f;
+} rb_color_mask_u;
+
+
+/*
+ * RB_BLEND_RED struct
+ */
+
+#define RB_BLEND_RED_BLEND_RED_SIZE    8
+
+#define RB_BLEND_RED_BLEND_RED_SHIFT   0
+
+#define RB_BLEND_RED_BLEND_RED_MASK    0x000000ff
+
+#define RB_BLEND_RED_MASK \
+     (RB_BLEND_RED_BLEND_RED_MASK)
+
+#define RB_BLEND_RED(blend_red) \
+     ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT))
+
+#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \
+     ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \
+     rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_red_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int                                : 24;
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+     } rb_blend_red_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_red_t f;
+} rb_blend_red_u;
+
+
+/*
+ * RB_BLEND_GREEN struct
+ */
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0
+
+#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff
+
+#define RB_BLEND_GREEN_MASK \
+     (RB_BLEND_GREEN_BLEND_GREEN_MASK)
+
+#define RB_BLEND_GREEN(blend_green) \
+     ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT))
+
+#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \
+     ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \
+     rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_green_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int                                : 24;
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+     } rb_blend_green_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_green_t f;
+} rb_blend_green_u;
+
+
+/*
+ * RB_BLEND_BLUE struct
+ */
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SIZE  8
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0
+
+#define RB_BLEND_BLUE_BLEND_BLUE_MASK  0x000000ff
+
+#define RB_BLEND_BLUE_MASK \
+     (RB_BLEND_BLUE_BLEND_BLUE_MASK)
+
+#define RB_BLEND_BLUE(blend_blue) \
+     ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT))
+
+#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \
+     ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \
+     rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_blue_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int                                : 24;
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+     } rb_blend_blue_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_blue_t f;
+} rb_blend_blue_u;
+
+
+/*
+ * RB_BLEND_ALPHA struct
+ */
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff
+
+#define RB_BLEND_ALPHA_MASK \
+     (RB_BLEND_ALPHA_BLEND_ALPHA_MASK)
+
+#define RB_BLEND_ALPHA(blend_alpha) \
+     ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT))
+
+#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \
+     ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \
+     rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_alpha_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int                                : 24;
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+     } rb_blend_alpha_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_alpha_t f;
+} rb_blend_alpha_u;
+
+
+/*
+ * RB_FOG_COLOR struct
+ */
+
+#define RB_FOG_COLOR_FOG_RED_SIZE      8
+#define RB_FOG_COLOR_FOG_GREEN_SIZE    8
+#define RB_FOG_COLOR_FOG_BLUE_SIZE     8
+
+#define RB_FOG_COLOR_FOG_RED_SHIFT     0
+#define RB_FOG_COLOR_FOG_GREEN_SHIFT   8
+#define RB_FOG_COLOR_FOG_BLUE_SHIFT    16
+
+#define RB_FOG_COLOR_FOG_RED_MASK      0x000000ff
+#define RB_FOG_COLOR_FOG_GREEN_MASK    0x0000ff00
+#define RB_FOG_COLOR_FOG_BLUE_MASK     0x00ff0000
+
+#define RB_FOG_COLOR_MASK \
+     (RB_FOG_COLOR_FOG_RED_MASK | \
+      RB_FOG_COLOR_FOG_GREEN_MASK | \
+      RB_FOG_COLOR_FOG_BLUE_MASK)
+
+#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \
+     ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \
+      (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \
+      (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT))
+
+#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int                                : 8;
+     } rb_fog_color_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int                                : 8;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+     } rb_fog_color_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_fog_color_t f;
+} rb_fog_color_u;
+
+
+/*
+ * RB_STENCILREFMASK_BF struct
+ */
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_RESERVED4_SIZE 1
+#define RB_STENCILREFMASK_BF_RESERVED5_SIZE 1
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16
+#define RB_STENCILREFMASK_BF_RESERVED4_SHIFT 24
+#define RB_STENCILREFMASK_BF_RESERVED5_SHIFT 25
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000
+#define RB_STENCILREFMASK_BF_RESERVED4_MASK 0x01000000
+#define RB_STENCILREFMASK_BF_RESERVED5_MASK 0x02000000
+
+#define RB_STENCILREFMASK_BF_MASK \
+     (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_RESERVED4_MASK | \
+      RB_STENCILREFMASK_BF_RESERVED5_MASK)
+
+#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf, reserved4, reserved5) \
+     ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \
+      (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \
+      (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) | \
+      (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) | \
+      (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT))
+
+#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_RESERVED4(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED4_MASK) >> RB_STENCILREFMASK_BF_RESERVED4_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_RESERVED5(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED5_MASK) >> RB_STENCILREFMASK_BF_RESERVED5_SHIFT)
+
+#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_RESERVED4(rb_stencilrefmask_bf_reg, reserved4) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED4_MASK) | (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_RESERVED5(rb_stencilrefmask_bf_reg, reserved5) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED5_MASK) | (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int reserved4                      : RB_STENCILREFMASK_BF_RESERVED4_SIZE;
+          unsigned int reserved5                      : RB_STENCILREFMASK_BF_RESERVED5_SIZE;
+          unsigned int                                : 6;
+     } rb_stencilrefmask_bf_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int                                : 6;
+          unsigned int reserved5                      : RB_STENCILREFMASK_BF_RESERVED5_SIZE;
+          unsigned int reserved4                      : RB_STENCILREFMASK_BF_RESERVED4_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+     } rb_stencilrefmask_bf_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_bf_t f;
+} rb_stencilrefmask_bf_u;
+
+
+/*
+ * RB_DEPTHCONTROL struct
+ */
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_Z_ENABLE_SIZE  1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_ZFUNC_SIZE     3
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0
+#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3
+#define RB_DEPTHCONTROL_ZFUNC_SHIFT    4
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7
+#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8
+#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11
+#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14
+#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001
+#define RB_DEPTHCONTROL_Z_ENABLE_MASK  0x00000002
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008
+#define RB_DEPTHCONTROL_ZFUNC_MASK     0x00000070
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080
+#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700
+#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800
+#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000
+#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000
+
+#define RB_DEPTHCONTROL_MASK \
+     (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_ZFUNC_MASK | \
+      RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK)
+
+#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \
+     ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \
+      (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \
+      (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \
+      (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \
+      (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \
+      (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \
+      (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \
+      (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \
+      (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \
+      (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \
+      (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \
+      (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \
+      (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \
+      (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT))
+
+#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+     } rb_depthcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+     } rb_depthcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depthcontrol_t f;
+} rb_depthcontrol_u;
+
+
+/*
+ * RB_BLENDCONTROL struct
+ */
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1
+#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29
+#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000
+#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000
+
+#define RB_BLENDCONTROL_MASK \
+     (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_MASK)
+
+#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \
+     ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \
+      (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \
+      (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \
+      (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \
+      (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \
+      (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \
+      (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \
+      (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT))
+
+#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int                                : 1;
+     } rb_blendcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int                                : 1;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+     } rb_blendcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blendcontrol_t f;
+} rb_blendcontrol_u;
+
+
+/*
+ * RB_COLORCONTROL struct
+ */
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1
+#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1
+#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1
+#define RB_COLORCONTROL_ROP_CODE_SIZE  4
+#define RB_COLORCONTROL_DITHER_MODE_SIZE 2
+#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2
+#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4
+#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5
+#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7
+#define RB_COLORCONTROL_ROP_CODE_SHIFT 8
+#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12
+#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14
+#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30
+
+#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010
+#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020
+#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080
+#define RB_COLORCONTROL_ROP_CODE_MASK  0x00000f00
+#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000
+#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000
+#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000
+
+#define RB_COLORCONTROL_MASK \
+     (RB_COLORCONTROL_ALPHA_FUNC_MASK | \
+      RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \
+      RB_COLORCONTROL_BLEND_DISABLE_MASK | \
+      RB_COLORCONTROL_FOG_ENABLE_MASK | \
+      RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \
+      RB_COLORCONTROL_ROP_CODE_MASK | \
+      RB_COLORCONTROL_DITHER_MODE_MASK | \
+      RB_COLORCONTROL_DITHER_TYPE_MASK | \
+      RB_COLORCONTROL_PIXEL_FOG_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK)
+
+#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \
+     ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \
+      (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \
+      (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \
+      (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \
+      (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \
+      (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \
+      (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \
+      (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \
+      (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \
+      (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \
+      (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \
+      (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \
+      (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \
+      (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT))
+
+#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int                                : 7;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+     } rb_colorcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int                                : 7;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+     } rb_colorcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_colorcontrol_t f;
+} rb_colorcontrol_u;
+
+
+/*
+ * RB_MODECONTROL struct
+ */
+
+#define RB_MODECONTROL_EDRAM_MODE_SIZE 3
+
+#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0
+
+#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007
+
+#define RB_MODECONTROL_MASK \
+     (RB_MODECONTROL_EDRAM_MODE_MASK)
+
+#define RB_MODECONTROL(edram_mode) \
+     ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT))
+
+#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \
+     ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \
+     rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+          unsigned int                                : 29;
+     } rb_modecontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int                                : 29;
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+     } rb_modecontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_modecontrol_t f;
+} rb_modecontrol_u;
+
+
+/*
+ * RB_COLOR_DEST_MASK struct
+ */
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff
+
+#define RB_COLOR_DEST_MASK_MASK \
+     (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK)
+
+#define RB_COLOR_DEST_MASK(color_dest_mask) \
+     ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT))
+
+#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \
+     ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \
+     rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_dest_mask_t f;
+} rb_color_dest_mask_u;
+
+
+/*
+ * RB_COPY_CONTROL struct
+ */
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1
+#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3
+#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008
+#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0
+
+#define RB_COPY_CONTROL_MASK \
+     (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \
+      RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \
+      RB_COPY_CONTROL_CLEAR_MASK_MASK)
+
+#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \
+     ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \
+      (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \
+      (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT))
+
+#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int                                : 24;
+     } rb_copy_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int                                : 24;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+     } rb_copy_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_control_t f;
+} rb_copy_control_u;
+
+
+/*
+ * RB_COPY_DEST_BASE struct
+ */
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000
+
+#define RB_COPY_DEST_BASE_MASK \
+     (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK)
+
+#define RB_COPY_DEST_BASE(copy_dest_base) \
+     ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT))
+
+#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \
+     ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \
+     rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int                                : 12;
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+     } rb_copy_dest_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+          unsigned int                                : 12;
+     } rb_copy_dest_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_base_t f;
+} rb_copy_dest_base_u;
+
+
+/*
+ * RB_COPY_DEST_PITCH struct
+ */
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff
+
+#define RB_COPY_DEST_PITCH_MASK \
+     (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK)
+
+#define RB_COPY_DEST_PITCH(copy_dest_pitch) \
+     ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT))
+
+#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \
+     ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \
+     rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+          unsigned int                                : 23;
+     } rb_copy_dest_pitch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int                                : 23;
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+     } rb_copy_dest_pitch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pitch_t f;
+} rb_copy_dest_pitch_u;
+
+
+/*
+ * RB_COPY_DEST_INFO struct
+ */
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000
+
+#define RB_COPY_DEST_INFO_MASK \
+     (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK)
+
+#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \
+     ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \
+      (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \
+      (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \
+      (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \
+      (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \
+      (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \
+      (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \
+      (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \
+      (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \
+      (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT))
+
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int                                : 14;
+     } rb_copy_dest_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int                                : 14;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+     } rb_copy_dest_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_info_t f;
+} rb_copy_dest_info_u;
+
+
+/*
+ * RB_COPY_DEST_PIXEL_OFFSET struct
+ */
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000
+
+#define RB_COPY_DEST_PIXEL_OFFSET_MASK \
+     (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \
+      RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK)
+
+#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \
+     ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \
+      (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT))
+
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int                                : 6;
+     } rb_copy_dest_pixel_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int                                : 6;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+     } rb_copy_dest_pixel_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pixel_offset_t f;
+} rb_copy_dest_pixel_offset_u;
+
+
+/*
+ * RB_DEPTH_CLEAR struct
+ */
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff
+
+#define RB_DEPTH_CLEAR_MASK \
+     (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK)
+
+#define RB_DEPTH_CLEAR(depth_clear) \
+     ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT))
+
+#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \
+     ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \
+     rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_clear_t f;
+} rb_depth_clear_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_CTL struct
+ */
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002
+
+#define RB_SAMPLE_COUNT_CTL_MASK \
+     (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \
+      RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK)
+
+#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \
+     ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \
+      (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT))
+
+#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int                                : 30;
+     } rb_sample_count_ctl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int                                : 30;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+     } rb_sample_count_ctl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_ctl_t f;
+} rb_sample_count_ctl_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_ADDR struct
+ */
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff
+
+#define RB_SAMPLE_COUNT_ADDR_MASK \
+     (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK)
+
+#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \
+     ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT))
+
+#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \
+     ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \
+     rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_addr_t f;
+} rb_sample_count_addr_u;
+
+
+/*
+ * RB_BC_CONTROL struct
+ */
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1
+#define RB_BC_CONTROL_CRC_MODE_SIZE    1
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1
+#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_CRC_SYSTEM_SIZE  1
+#define RB_BC_CONTROL_RESERVED6_SIZE   1
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14
+#define RB_BC_CONTROL_CRC_MODE_SHIFT   15
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16
+#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29
+#define RB_BC_CONTROL_CRC_SYSTEM_SHIFT 30
+#define RB_BC_CONTROL_RESERVED6_SHIFT  31
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000
+#define RB_BC_CONTROL_CRC_MODE_MASK    0x00008000
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000
+#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000
+#define RB_BC_CONTROL_CRC_SYSTEM_MASK  0x40000000
+#define RB_BC_CONTROL_RESERVED6_MASK   0x80000000
+
+#define RB_BC_CONTROL_MASK \
+     (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \
+      RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \
+      RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \
+      RB_BC_CONTROL_CRC_MODE_MASK | \
+      RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \
+      RB_BC_CONTROL_DISABLE_ACCUM_MASK | \
+      RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \
+      RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_CRC_SYSTEM_MASK | \
+      RB_BC_CONTROL_RESERVED6_MASK)
+
+#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, crc_system, reserved6) \
+     ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \
+      (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \
+      (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \
+      (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \
+      (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \
+      (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \
+      (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \
+      (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \
+      (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \
+      (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \
+      (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \
+      (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \
+      (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \
+      (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \
+      (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \
+      (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \
+      (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \
+      (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) | \
+      (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT))
+
+#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_SYSTEM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_SYSTEM_MASK) >> RB_BC_CONTROL_CRC_SYSTEM_SHIFT)
+#define RB_BC_CONTROL_GET_RESERVED6(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_RESERVED6_MASK) >> RB_BC_CONTROL_RESERVED6_SHIFT)
+
+#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_SYSTEM(rb_bc_control_reg, crc_system) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_SYSTEM_MASK) | (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT)
+#define RB_BC_CONTROL_SET_RESERVED6(rb_bc_control_reg, reserved6) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED6_MASK) | (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int                                : 1;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int crc_system                     : RB_BC_CONTROL_CRC_SYSTEM_SIZE;
+          unsigned int reserved6                      : RB_BC_CONTROL_RESERVED6_SIZE;
+     } rb_bc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int reserved6                      : RB_BC_CONTROL_RESERVED6_SIZE;
+          unsigned int crc_system                     : RB_BC_CONTROL_CRC_SYSTEM_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+     } rb_bc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_control_t f;
+} rb_bc_control_u;
+
+
+/*
+ * RB_EDRAM_INFO struct
+ */
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE  4
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2
+#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4
+#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_MASK  0x0000000f
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030
+#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000
+
+#define RB_EDRAM_INFO_MASK \
+     (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \
+      RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \
+      RB_EDRAM_INFO_EDRAM_RANGE_MASK)
+
+#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \
+     ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \
+      (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \
+      (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT))
+
+#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+     } rb_edram_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+     } rb_edram_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_edram_info_t f;
+} rb_edram_info_u;
+
+
+/*
+ * RB_CRC_RD_PORT struct
+ */
+
+#define RB_CRC_RD_PORT_CRC_DATA_SIZE   32
+
+#define RB_CRC_RD_PORT_CRC_DATA_SHIFT  0
+
+#define RB_CRC_RD_PORT_CRC_DATA_MASK   0xffffffff
+
+#define RB_CRC_RD_PORT_MASK \
+     (RB_CRC_RD_PORT_CRC_DATA_MASK)
+
+#define RB_CRC_RD_PORT(crc_data) \
+     ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT))
+
+#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \
+     ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \
+     rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_rd_port_t f;
+} rb_crc_rd_port_u;
+
+
+/*
+ * RB_CRC_CONTROL struct
+ */
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001
+
+#define RB_CRC_CONTROL_MASK \
+     (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK)
+
+#define RB_CRC_CONTROL(crc_rd_advance) \
+     ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT))
+
+#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \
+     ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \
+     rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+          unsigned int                                : 31;
+     } rb_crc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int                                : 31;
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+     } rb_crc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_control_t f;
+} rb_crc_control_u;
+
+
+/*
+ * RB_CRC_MASK struct
+ */
+
+#define RB_CRC_MASK_CRC_MASK_SIZE      32
+
+#define RB_CRC_MASK_CRC_MASK_SHIFT     0
+
+#define RB_CRC_MASK_CRC_MASK_MASK      0xffffffff
+
+#define RB_CRC_MASK_MASK \
+     (RB_CRC_MASK_CRC_MASK_MASK)
+
+#define RB_CRC_MASK(crc_mask) \
+     ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT))
+
+#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \
+     ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \
+     rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_mask_t f;
+} rb_crc_mask_u;
+
+
+/*
+ * RB_PERFCOUNTER0_SELECT struct
+ */
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define RB_PERFCOUNTER0_SELECT_MASK \
+     (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define RB_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \
+     ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \
+     rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } rb_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } rb_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_select_t f;
+} rb_perfcounter0_select_u;
+
+
+/*
+ * RB_PERFCOUNTER0_LOW struct
+ */
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define RB_PERFCOUNTER0_LOW_MASK \
+     (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \
+     ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \
+     rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_low_t f;
+} rb_perfcounter0_low_u;
+
+
+/*
+ * RB_PERFCOUNTER0_HI struct
+ */
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define RB_PERFCOUNTER0_HI_MASK \
+     (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \
+     ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \
+     rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } rb_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } rb_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_hi_t f;
+} rb_perfcounter0_hi_u;
+
+
+/*
+ * RB_TOTAL_SAMPLES struct
+ */
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff
+
+#define RB_TOTAL_SAMPLES_MASK \
+     (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK)
+
+#define RB_TOTAL_SAMPLES(total_samples) \
+     ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT))
+
+#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \
+     ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \
+     rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_total_samples_t f;
+} rb_total_samples_u;
+
+
+/*
+ * RB_ZPASS_SAMPLES struct
+ */
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff
+
+#define RB_ZPASS_SAMPLES_MASK \
+     (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK)
+
+#define RB_ZPASS_SAMPLES(zpass_samples) \
+     ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT))
+
+#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \
+     ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \
+     rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zpass_samples_t f;
+} rb_zpass_samples_u;
+
+
+/*
+ * RB_ZFAIL_SAMPLES struct
+ */
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_ZFAIL_SAMPLES_MASK \
+     (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK)
+
+#define RB_ZFAIL_SAMPLES(zfail_samples) \
+     ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT))
+
+#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \
+     ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \
+     rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zfail_samples_t f;
+} rb_zfail_samples_u;
+
+
+/*
+ * RB_SFAIL_SAMPLES struct
+ */
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_SFAIL_SAMPLES_MASK \
+     (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK)
+
+#define RB_SFAIL_SAMPLES(sfail_samples) \
+     ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT))
+
+#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \
+     ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \
+     rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sfail_samples_t f;
+} rb_sfail_samples_u;
+
+
+/*
+ * RB_DEBUG_0 struct
+ */
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE  1
+#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE  1
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1
+#define RB_DEBUG_0_C_REQ_FULL_SIZE     1
+#define RB_DEBUG_0_C_MASK_FULL_SIZE    1
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7
+#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8
+#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17
+#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18
+#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25
+#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26
+#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28
+#define RB_DEBUG_0_C_REQ_FULL_SHIFT    29
+#define RB_DEBUG_0_C_MASK_FULL_SHIFT   30
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020
+#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK  0x00000040
+#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK  0x00000080
+#define RB_DEBUG_0_RDREQ_C1_FULL_MASK  0x00000100
+#define RB_DEBUG_0_RDREQ_C0_FULL_MASK  0x00000200
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000
+#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK  0x00010000
+#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK  0x00020000
+#define RB_DEBUG_0_WRREQ_C1_FULL_MASK  0x00040000
+#define RB_DEBUG_0_WRREQ_C0_FULL_MASK  0x00080000
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000
+#define RB_DEBUG_0_C_SX_LAT_FULL_MASK  0x04000000
+#define RB_DEBUG_0_C_SX_CMD_FULL_MASK  0x08000000
+#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000
+#define RB_DEBUG_0_C_REQ_FULL_MASK     0x20000000
+#define RB_DEBUG_0_C_MASK_FULL_MASK    0x40000000
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000
+
+#define RB_DEBUG_0_MASK \
+     (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_C_SX_LAT_FULL_MASK | \
+      RB_DEBUG_0_C_SX_CMD_FULL_MASK | \
+      RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \
+      RB_DEBUG_0_C_REQ_FULL_MASK | \
+      RB_DEBUG_0_C_MASK_FULL_MASK | \
+      RB_DEBUG_0_EZ_INFSAMP_FULL_MASK)
+
+#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \
+     ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \
+      (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \
+      (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \
+      (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \
+      (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \
+      (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \
+      (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \
+      (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \
+      (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \
+      (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \
+      (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \
+      (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \
+      (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \
+      (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \
+      (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \
+      (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \
+      (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \
+      (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \
+      (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \
+      (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \
+      (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT))
+
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+     } rb_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+     } rb_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_0_t f;
+} rb_debug_0_u;
+
+
+/*
+ * RB_DEBUG_1 struct
+ */
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_REQ_EMPTY_SIZE    1
+#define RB_DEBUG_1_C_MASK_EMPTY_SIZE   1
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28
+#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT   29
+#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT  30
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000
+#define RB_DEBUG_1_C_REQ_EMPTY_MASK    0x20000000
+#define RB_DEBUG_1_C_MASK_EMPTY_MASK   0x40000000
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000
+
+#define RB_DEBUG_1_MASK \
+     (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \
+      RB_DEBUG_1_C_REQ_EMPTY_MASK | \
+      RB_DEBUG_1_C_MASK_EMPTY_MASK | \
+      RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK)
+
+#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \
+     ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \
+      (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \
+      (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \
+      (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \
+      (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \
+      (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \
+      (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \
+      (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \
+      (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \
+      (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \
+      (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \
+      (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \
+      (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \
+      (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \
+      (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \
+      (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \
+      (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \
+      (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \
+      (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \
+      (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \
+      (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT))
+
+#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_1_t f;
+} rb_debug_1_u;
+
+
+/*
+ * RB_DEBUG_2 struct
+ */
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z1_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z0_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z1_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z_SAMP_FULL_SIZE    1
+#define RB_DEBUG_2_Z_TILE_FULL_SIZE    1
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE   1
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16
+#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT  17
+#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT  18
+#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT   19
+#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT   20
+#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT   21
+#define RB_DEBUG_2_Z_TILE_FULL_SHIFT   22
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT  28
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT  29
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT  30
+#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT  31
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000
+#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000
+#define RB_DEBUG_2_Z0_MASK_FULL_MASK   0x00020000
+#define RB_DEBUG_2_Z1_MASK_FULL_MASK   0x00040000
+#define RB_DEBUG_2_Z0_REQ_FULL_MASK    0x00080000
+#define RB_DEBUG_2_Z1_REQ_FULL_MASK    0x00100000
+#define RB_DEBUG_2_Z_SAMP_FULL_MASK    0x00200000
+#define RB_DEBUG_2_Z_TILE_FULL_MASK    0x00400000
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK  0x04000000
+#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK  0x08000000
+#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK   0x10000000
+#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK   0x20000000
+#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK   0x40000000
+#define RB_DEBUG_2_Z_TILE_EMPTY_MASK   0x80000000
+
+#define RB_DEBUG_2_MASK \
+     (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \
+      RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \
+      RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \
+      RB_DEBUG_2_Z0_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z1_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z0_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z1_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z_SAMP_FULL_MASK | \
+      RB_DEBUG_2_Z_TILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \
+      RB_DEBUG_2_Z_TILE_EMPTY_MASK)
+
+#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \
+     ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \
+      (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \
+      (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \
+      (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \
+      (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \
+      (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \
+      (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \
+      (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \
+      (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \
+      (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \
+      (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \
+      (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \
+      (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \
+      (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \
+      (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \
+      (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \
+      (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \
+      (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \
+      (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \
+      (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \
+      (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \
+      (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \
+      (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT))
+
+#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+     } rb_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+     } rb_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_2_t f;
+} rb_debug_2_u;
+
+
+/*
+ * RB_DEBUG_3 struct
+ */
+
+#define RB_DEBUG_3_ACCUM_VALID_SIZE    4
+#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4
+#define RB_DEBUG_3_SHD_FULL_SIZE       1
+#define RB_DEBUG_3_SHD_EMPTY_SIZE      1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1
+
+#define RB_DEBUG_3_ACCUM_VALID_SHIFT   0
+#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15
+#define RB_DEBUG_3_SHD_FULL_SHIFT      19
+#define RB_DEBUG_3_SHD_EMPTY_SHIFT     20
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28
+
+#define RB_DEBUG_3_ACCUM_VALID_MASK    0x0000000f
+#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000
+#define RB_DEBUG_3_SHD_FULL_MASK       0x00080000
+#define RB_DEBUG_3_SHD_EMPTY_MASK      0x00100000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000
+
+#define RB_DEBUG_3_MASK \
+     (RB_DEBUG_3_ACCUM_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_FLUSHING_MASK | \
+      RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \
+      RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \
+      RB_DEBUG_3_SHD_FULL_MASK | \
+      RB_DEBUG_3_SHD_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_FULL_MASK)
+
+#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \
+     ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \
+      (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \
+      (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \
+      (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \
+      (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \
+      (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \
+      (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \
+      (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \
+      (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \
+      (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \
+      (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \
+      (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \
+      (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \
+      (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \
+      (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT))
+
+#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int                                : 3;
+     } rb_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int                                : 3;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+     } rb_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_3_t f;
+} rb_debug_3_u;
+
+
+/*
+ * RB_DEBUG_4 struct
+ */
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00
+
+#define RB_DEBUG_4_MASK \
+     (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \
+      RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \
+      RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK)
+
+#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \
+     ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \
+      (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \
+      (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \
+      (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \
+      (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \
+      (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT))
+
+#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int                                : 19;
+     } rb_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int                                : 19;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+     } rb_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_4_t f;
+} rb_debug_4_u;
+
+
+/*
+ * RB_FLAG_CONTROL struct
+ */
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001
+
+#define RB_FLAG_CONTROL_MASK \
+     (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK)
+
+#define RB_FLAG_CONTROL(debug_flag_clear) \
+     ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT))
+
+#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \
+     ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \
+     rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+          unsigned int                                : 31;
+     } rb_flag_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int                                : 31;
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+     } rb_flag_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_flag_control_t f;
+} rb_flag_control_u;
+
+
+/*
+ * RB_BC_SPARES struct
+ */
+
+#define RB_BC_SPARES_RESERVED_SIZE     32
+
+#define RB_BC_SPARES_RESERVED_SHIFT    0
+
+#define RB_BC_SPARES_RESERVED_MASK     0xffffffff
+
+#define RB_BC_SPARES_MASK \
+     (RB_BC_SPARES_RESERVED_MASK)
+
+#define RB_BC_SPARES(reserved) \
+     ((reserved << RB_BC_SPARES_RESERVED_SHIFT))
+
+#define RB_BC_SPARES_GET_RESERVED(rb_bc_spares) \
+     ((rb_bc_spares & RB_BC_SPARES_RESERVED_MASK) >> RB_BC_SPARES_RESERVED_SHIFT)
+
+#define RB_BC_SPARES_SET_RESERVED(rb_bc_spares_reg, reserved) \
+     rb_bc_spares_reg = (rb_bc_spares_reg & ~RB_BC_SPARES_RESERVED_MASK) | (reserved << RB_BC_SPARES_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_spares_t {
+          unsigned int reserved                       : RB_BC_SPARES_RESERVED_SIZE;
+     } rb_bc_spares_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_spares_t {
+          unsigned int reserved                       : RB_BC_SPARES_RESERVED_SIZE;
+     } rb_bc_spares_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_spares_t f;
+} rb_bc_spares_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_ENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000
+
+#define BC_DUMMY_CRAYRB_ENUMS_MASK \
+     (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK)
+
+#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \
+     ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \
+      (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \
+      (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \
+      (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \
+      (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \
+      (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \
+      (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT))
+
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_enums_t f;
+} bc_dummy_crayrb_enums_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_MOREENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \
+     (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \
+     ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT))
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \
+     ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \
+     bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+          unsigned int                                : 30;
+     } bc_dummy_crayrb_moreenums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int                                : 30;
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+     } bc_dummy_crayrb_moreenums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_moreenums_t f;
+} bc_dummy_crayrb_moreenums_u;
+
+
+#endif
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h
new file mode 100644
index 000000000000..6968abb48bd7
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h
@@ -0,0 +1,550 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_TYPEDEF_HEADER)
+#define _yamato_TYPEDEF_HEADER
+
+#include "yamato_registers.h"
+
+typedef union PA_CL_VPORT_XSCALE                regPA_CL_VPORT_XSCALE;
+typedef union PA_CL_VPORT_XOFFSET               regPA_CL_VPORT_XOFFSET;
+typedef union PA_CL_VPORT_YSCALE                regPA_CL_VPORT_YSCALE;
+typedef union PA_CL_VPORT_YOFFSET               regPA_CL_VPORT_YOFFSET;
+typedef union PA_CL_VPORT_ZSCALE                regPA_CL_VPORT_ZSCALE;
+typedef union PA_CL_VPORT_ZOFFSET               regPA_CL_VPORT_ZOFFSET;
+typedef union PA_CL_VTE_CNTL                    regPA_CL_VTE_CNTL;
+typedef union PA_CL_CLIP_CNTL                   regPA_CL_CLIP_CNTL;
+typedef union PA_CL_GB_VERT_CLIP_ADJ            regPA_CL_GB_VERT_CLIP_ADJ;
+typedef union PA_CL_GB_VERT_DISC_ADJ            regPA_CL_GB_VERT_DISC_ADJ;
+typedef union PA_CL_GB_HORZ_CLIP_ADJ            regPA_CL_GB_HORZ_CLIP_ADJ;
+typedef union PA_CL_GB_HORZ_DISC_ADJ            regPA_CL_GB_HORZ_DISC_ADJ;
+typedef union PA_CL_ENHANCE                     regPA_CL_ENHANCE;
+typedef union PA_SC_ENHANCE                     regPA_SC_ENHANCE;
+typedef union PA_SU_VTX_CNTL                    regPA_SU_VTX_CNTL;
+typedef union PA_SU_POINT_SIZE                  regPA_SU_POINT_SIZE;
+typedef union PA_SU_POINT_MINMAX                regPA_SU_POINT_MINMAX;
+typedef union PA_SU_LINE_CNTL                   regPA_SU_LINE_CNTL;
+typedef union PA_SU_FACE_DATA                   regPA_SU_FACE_DATA;
+typedef union PA_SU_SC_MODE_CNTL                regPA_SU_SC_MODE_CNTL;
+typedef union PA_SU_POLY_OFFSET_FRONT_SCALE     regPA_SU_POLY_OFFSET_FRONT_SCALE;
+typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET    regPA_SU_POLY_OFFSET_FRONT_OFFSET;
+typedef union PA_SU_POLY_OFFSET_BACK_SCALE      regPA_SU_POLY_OFFSET_BACK_SCALE;
+typedef union PA_SU_POLY_OFFSET_BACK_OFFSET     regPA_SU_POLY_OFFSET_BACK_OFFSET;
+typedef union PA_SU_PERFCOUNTER0_SELECT         regPA_SU_PERFCOUNTER0_SELECT;
+typedef union PA_SU_PERFCOUNTER1_SELECT         regPA_SU_PERFCOUNTER1_SELECT;
+typedef union PA_SU_PERFCOUNTER2_SELECT         regPA_SU_PERFCOUNTER2_SELECT;
+typedef union PA_SU_PERFCOUNTER3_SELECT         regPA_SU_PERFCOUNTER3_SELECT;
+typedef union PA_SU_PERFCOUNTER0_LOW            regPA_SU_PERFCOUNTER0_LOW;
+typedef union PA_SU_PERFCOUNTER0_HI             regPA_SU_PERFCOUNTER0_HI;
+typedef union PA_SU_PERFCOUNTER1_LOW            regPA_SU_PERFCOUNTER1_LOW;
+typedef union PA_SU_PERFCOUNTER1_HI             regPA_SU_PERFCOUNTER1_HI;
+typedef union PA_SU_PERFCOUNTER2_LOW            regPA_SU_PERFCOUNTER2_LOW;
+typedef union PA_SU_PERFCOUNTER2_HI             regPA_SU_PERFCOUNTER2_HI;
+typedef union PA_SU_PERFCOUNTER3_LOW            regPA_SU_PERFCOUNTER3_LOW;
+typedef union PA_SU_PERFCOUNTER3_HI             regPA_SU_PERFCOUNTER3_HI;
+typedef union PA_SC_WINDOW_OFFSET               regPA_SC_WINDOW_OFFSET;
+typedef union PA_SC_AA_CONFIG                   regPA_SC_AA_CONFIG;
+typedef union PA_SC_AA_MASK                     regPA_SC_AA_MASK;
+typedef union PA_SC_LINE_STIPPLE                regPA_SC_LINE_STIPPLE;
+typedef union PA_SC_LINE_CNTL                   regPA_SC_LINE_CNTL;
+typedef union PA_SC_WINDOW_SCISSOR_TL           regPA_SC_WINDOW_SCISSOR_TL;
+typedef union PA_SC_WINDOW_SCISSOR_BR           regPA_SC_WINDOW_SCISSOR_BR;
+typedef union PA_SC_SCREEN_SCISSOR_TL           regPA_SC_SCREEN_SCISSOR_TL;
+typedef union PA_SC_SCREEN_SCISSOR_BR           regPA_SC_SCREEN_SCISSOR_BR;
+typedef union PA_SC_VIZ_QUERY                   regPA_SC_VIZ_QUERY;
+typedef union PA_SC_VIZ_QUERY_STATUS            regPA_SC_VIZ_QUERY_STATUS;
+typedef union PA_SC_LINE_STIPPLE_STATE          regPA_SC_LINE_STIPPLE_STATE;
+typedef union PA_SC_PERFCOUNTER0_SELECT         regPA_SC_PERFCOUNTER0_SELECT;
+typedef union PA_SC_PERFCOUNTER0_LOW            regPA_SC_PERFCOUNTER0_LOW;
+typedef union PA_SC_PERFCOUNTER0_HI             regPA_SC_PERFCOUNTER0_HI;
+typedef union PA_CL_CNTL_STATUS                 regPA_CL_CNTL_STATUS;
+typedef union PA_SU_CNTL_STATUS                 regPA_SU_CNTL_STATUS;
+typedef union PA_SC_CNTL_STATUS                 regPA_SC_CNTL_STATUS;
+typedef union PA_SU_DEBUG_CNTL                  regPA_SU_DEBUG_CNTL;
+typedef union PA_SU_DEBUG_DATA                  regPA_SU_DEBUG_DATA;
+typedef union PA_SC_DEBUG_CNTL                  regPA_SC_DEBUG_CNTL;
+typedef union PA_SC_DEBUG_DATA                  regPA_SC_DEBUG_DATA;
+typedef union GFX_COPY_STATE                    regGFX_COPY_STATE;
+typedef union VGT_DRAW_INITIATOR                regVGT_DRAW_INITIATOR;
+typedef union VGT_EVENT_INITIATOR               regVGT_EVENT_INITIATOR;
+typedef union VGT_DMA_BASE                      regVGT_DMA_BASE;
+typedef union VGT_DMA_SIZE                      regVGT_DMA_SIZE;
+typedef union VGT_BIN_BASE                      regVGT_BIN_BASE;
+typedef union VGT_BIN_SIZE                      regVGT_BIN_SIZE;
+typedef union VGT_CURRENT_BIN_ID_MIN            regVGT_CURRENT_BIN_ID_MIN;
+typedef union VGT_CURRENT_BIN_ID_MAX            regVGT_CURRENT_BIN_ID_MAX;
+typedef union VGT_IMMED_DATA                    regVGT_IMMED_DATA;
+typedef union VGT_MAX_VTX_INDX                  regVGT_MAX_VTX_INDX;
+typedef union VGT_MIN_VTX_INDX                  regVGT_MIN_VTX_INDX;
+typedef union VGT_INDX_OFFSET                   regVGT_INDX_OFFSET;
+typedef union VGT_VERTEX_REUSE_BLOCK_CNTL       regVGT_VERTEX_REUSE_BLOCK_CNTL;
+typedef union VGT_OUT_DEALLOC_CNTL              regVGT_OUT_DEALLOC_CNTL;
+typedef union VGT_MULTI_PRIM_IB_RESET_INDX      regVGT_MULTI_PRIM_IB_RESET_INDX;
+typedef union VGT_ENHANCE                       regVGT_ENHANCE;
+typedef union VGT_VTX_VECT_EJECT_REG            regVGT_VTX_VECT_EJECT_REG;
+typedef union VGT_LAST_COPY_STATE               regVGT_LAST_COPY_STATE;
+typedef union VGT_DEBUG_CNTL                    regVGT_DEBUG_CNTL;
+typedef union VGT_DEBUG_DATA                    regVGT_DEBUG_DATA;
+typedef union VGT_CNTL_STATUS                   regVGT_CNTL_STATUS;
+typedef union VGT_CRC_SQ_DATA                   regVGT_CRC_SQ_DATA;
+typedef union VGT_CRC_SQ_CTRL                   regVGT_CRC_SQ_CTRL;
+typedef union VGT_PERFCOUNTER0_SELECT           regVGT_PERFCOUNTER0_SELECT;
+typedef union VGT_PERFCOUNTER1_SELECT           regVGT_PERFCOUNTER1_SELECT;
+typedef union VGT_PERFCOUNTER2_SELECT           regVGT_PERFCOUNTER2_SELECT;
+typedef union VGT_PERFCOUNTER3_SELECT           regVGT_PERFCOUNTER3_SELECT;
+typedef union VGT_PERFCOUNTER0_LOW              regVGT_PERFCOUNTER0_LOW;
+typedef union VGT_PERFCOUNTER1_LOW              regVGT_PERFCOUNTER1_LOW;
+typedef union VGT_PERFCOUNTER2_LOW              regVGT_PERFCOUNTER2_LOW;
+typedef union VGT_PERFCOUNTER3_LOW              regVGT_PERFCOUNTER3_LOW;
+typedef union VGT_PERFCOUNTER0_HI               regVGT_PERFCOUNTER0_HI;
+typedef union VGT_PERFCOUNTER1_HI               regVGT_PERFCOUNTER1_HI;
+typedef union VGT_PERFCOUNTER2_HI               regVGT_PERFCOUNTER2_HI;
+typedef union VGT_PERFCOUNTER3_HI               regVGT_PERFCOUNTER3_HI;
+typedef union TC_CNTL_STATUS                    regTC_CNTL_STATUS;
+typedef union TCR_CHICKEN                       regTCR_CHICKEN;
+typedef union TCF_CHICKEN                       regTCF_CHICKEN;
+typedef union TCM_CHICKEN                       regTCM_CHICKEN;
+typedef union TCR_PERFCOUNTER0_SELECT           regTCR_PERFCOUNTER0_SELECT;
+typedef union TCR_PERFCOUNTER1_SELECT           regTCR_PERFCOUNTER1_SELECT;
+typedef union TCR_PERFCOUNTER0_HI               regTCR_PERFCOUNTER0_HI;
+typedef union TCR_PERFCOUNTER1_HI               regTCR_PERFCOUNTER1_HI;
+typedef union TCR_PERFCOUNTER0_LOW              regTCR_PERFCOUNTER0_LOW;
+typedef union TCR_PERFCOUNTER1_LOW              regTCR_PERFCOUNTER1_LOW;
+typedef union TP_TC_CLKGATE_CNTL                regTP_TC_CLKGATE_CNTL;
+typedef union TPC_CNTL_STATUS                   regTPC_CNTL_STATUS;
+typedef union TPC_DEBUG0                        regTPC_DEBUG0;
+typedef union TPC_DEBUG1                        regTPC_DEBUG1;
+typedef union TPC_CHICKEN                       regTPC_CHICKEN;
+typedef union TP0_CNTL_STATUS                   regTP0_CNTL_STATUS;
+typedef union TP0_DEBUG                         regTP0_DEBUG;
+typedef union TP0_CHICKEN                       regTP0_CHICKEN;
+typedef union TP0_PERFCOUNTER0_SELECT           regTP0_PERFCOUNTER0_SELECT;
+typedef union TP0_PERFCOUNTER0_HI               regTP0_PERFCOUNTER0_HI;
+typedef union TP0_PERFCOUNTER0_LOW              regTP0_PERFCOUNTER0_LOW;
+typedef union TP0_PERFCOUNTER1_SELECT           regTP0_PERFCOUNTER1_SELECT;
+typedef union TP0_PERFCOUNTER1_HI               regTP0_PERFCOUNTER1_HI;
+typedef union TP0_PERFCOUNTER1_LOW              regTP0_PERFCOUNTER1_LOW;
+typedef union TCM_PERFCOUNTER0_SELECT           regTCM_PERFCOUNTER0_SELECT;
+typedef union TCM_PERFCOUNTER1_SELECT           regTCM_PERFCOUNTER1_SELECT;
+typedef union TCM_PERFCOUNTER0_HI               regTCM_PERFCOUNTER0_HI;
+typedef union TCM_PERFCOUNTER1_HI               regTCM_PERFCOUNTER1_HI;
+typedef union TCM_PERFCOUNTER0_LOW              regTCM_PERFCOUNTER0_LOW;
+typedef union TCM_PERFCOUNTER1_LOW              regTCM_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER0_SELECT           regTCF_PERFCOUNTER0_SELECT;
+typedef union TCF_PERFCOUNTER1_SELECT           regTCF_PERFCOUNTER1_SELECT;
+typedef union TCF_PERFCOUNTER2_SELECT           regTCF_PERFCOUNTER2_SELECT;
+typedef union TCF_PERFCOUNTER3_SELECT           regTCF_PERFCOUNTER3_SELECT;
+typedef union TCF_PERFCOUNTER4_SELECT           regTCF_PERFCOUNTER4_SELECT;
+typedef union TCF_PERFCOUNTER5_SELECT           regTCF_PERFCOUNTER5_SELECT;
+typedef union TCF_PERFCOUNTER6_SELECT           regTCF_PERFCOUNTER6_SELECT;
+typedef union TCF_PERFCOUNTER7_SELECT           regTCF_PERFCOUNTER7_SELECT;
+typedef union TCF_PERFCOUNTER8_SELECT           regTCF_PERFCOUNTER8_SELECT;
+typedef union TCF_PERFCOUNTER9_SELECT           regTCF_PERFCOUNTER9_SELECT;
+typedef union TCF_PERFCOUNTER10_SELECT          regTCF_PERFCOUNTER10_SELECT;
+typedef union TCF_PERFCOUNTER11_SELECT          regTCF_PERFCOUNTER11_SELECT;
+typedef union TCF_PERFCOUNTER0_HI               regTCF_PERFCOUNTER0_HI;
+typedef union TCF_PERFCOUNTER1_HI               regTCF_PERFCOUNTER1_HI;
+typedef union TCF_PERFCOUNTER2_HI               regTCF_PERFCOUNTER2_HI;
+typedef union TCF_PERFCOUNTER3_HI               regTCF_PERFCOUNTER3_HI;
+typedef union TCF_PERFCOUNTER4_HI               regTCF_PERFCOUNTER4_HI;
+typedef union TCF_PERFCOUNTER5_HI               regTCF_PERFCOUNTER5_HI;
+typedef union TCF_PERFCOUNTER6_HI               regTCF_PERFCOUNTER6_HI;
+typedef union TCF_PERFCOUNTER7_HI               regTCF_PERFCOUNTER7_HI;
+typedef union TCF_PERFCOUNTER8_HI               regTCF_PERFCOUNTER8_HI;
+typedef union TCF_PERFCOUNTER9_HI               regTCF_PERFCOUNTER9_HI;
+typedef union TCF_PERFCOUNTER10_HI              regTCF_PERFCOUNTER10_HI;
+typedef union TCF_PERFCOUNTER11_HI              regTCF_PERFCOUNTER11_HI;
+typedef union TCF_PERFCOUNTER0_LOW              regTCF_PERFCOUNTER0_LOW;
+typedef union TCF_PERFCOUNTER1_LOW              regTCF_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER2_LOW              regTCF_PERFCOUNTER2_LOW;
+typedef union TCF_PERFCOUNTER3_LOW              regTCF_PERFCOUNTER3_LOW;
+typedef union TCF_PERFCOUNTER4_LOW              regTCF_PERFCOUNTER4_LOW;
+typedef union TCF_PERFCOUNTER5_LOW              regTCF_PERFCOUNTER5_LOW;
+typedef union TCF_PERFCOUNTER6_LOW              regTCF_PERFCOUNTER6_LOW;
+typedef union TCF_PERFCOUNTER7_LOW              regTCF_PERFCOUNTER7_LOW;
+typedef union TCF_PERFCOUNTER8_LOW              regTCF_PERFCOUNTER8_LOW;
+typedef union TCF_PERFCOUNTER9_LOW              regTCF_PERFCOUNTER9_LOW;
+typedef union TCF_PERFCOUNTER10_LOW             regTCF_PERFCOUNTER10_LOW;
+typedef union TCF_PERFCOUNTER11_LOW             regTCF_PERFCOUNTER11_LOW;
+typedef union TCF_DEBUG                         regTCF_DEBUG;
+typedef union TCA_FIFO_DEBUG                    regTCA_FIFO_DEBUG;
+typedef union TCA_PROBE_DEBUG                   regTCA_PROBE_DEBUG;
+typedef union TCA_TPC_DEBUG                     regTCA_TPC_DEBUG;
+typedef union TCB_CORE_DEBUG                    regTCB_CORE_DEBUG;
+typedef union TCB_TAG0_DEBUG                    regTCB_TAG0_DEBUG;
+typedef union TCB_TAG1_DEBUG                    regTCB_TAG1_DEBUG;
+typedef union TCB_TAG2_DEBUG                    regTCB_TAG2_DEBUG;
+typedef union TCB_TAG3_DEBUG                    regTCB_TAG3_DEBUG;
+typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG;
+typedef union TCB_FETCH_GEN_WALKER_DEBUG        regTCB_FETCH_GEN_WALKER_DEBUG;
+typedef union TCB_FETCH_GEN_PIPE0_DEBUG         regTCB_FETCH_GEN_PIPE0_DEBUG;
+typedef union TCD_INPUT0_DEBUG                  regTCD_INPUT0_DEBUG;
+typedef union TCD_DEGAMMA_DEBUG                 regTCD_DEGAMMA_DEBUG;
+typedef union TCD_DXTMUX_SCTARB_DEBUG           regTCD_DXTMUX_SCTARB_DEBUG;
+typedef union TCD_DXTC_ARB_DEBUG                regTCD_DXTC_ARB_DEBUG;
+typedef union TCD_STALLS_DEBUG                  regTCD_STALLS_DEBUG;
+typedef union TCO_STALLS_DEBUG                  regTCO_STALLS_DEBUG;
+typedef union TCO_QUAD0_DEBUG0                  regTCO_QUAD0_DEBUG0;
+typedef union TCO_QUAD0_DEBUG1                  regTCO_QUAD0_DEBUG1;
+typedef union SQ_GPR_MANAGEMENT                 regSQ_GPR_MANAGEMENT;
+typedef union SQ_FLOW_CONTROL                   regSQ_FLOW_CONTROL;
+typedef union SQ_INST_STORE_MANAGMENT           regSQ_INST_STORE_MANAGMENT;
+typedef union SQ_RESOURCE_MANAGMENT             regSQ_RESOURCE_MANAGMENT;
+typedef union SQ_EO_RT                          regSQ_EO_RT;
+typedef union SQ_DEBUG_MISC                     regSQ_DEBUG_MISC;
+typedef union SQ_ACTIVITY_METER_CNTL            regSQ_ACTIVITY_METER_CNTL;
+typedef union SQ_ACTIVITY_METER_STATUS          regSQ_ACTIVITY_METER_STATUS;
+typedef union SQ_INPUT_ARB_PRIORITY             regSQ_INPUT_ARB_PRIORITY;
+typedef union SQ_THREAD_ARB_PRIORITY            regSQ_THREAD_ARB_PRIORITY;
+typedef union SQ_VS_WATCHDOG_TIMER              regSQ_VS_WATCHDOG_TIMER;
+typedef union SQ_PS_WATCHDOG_TIMER              regSQ_PS_WATCHDOG_TIMER;
+typedef union SQ_INT_CNTL                       regSQ_INT_CNTL;
+typedef union SQ_INT_STATUS                     regSQ_INT_STATUS;
+typedef union SQ_INT_ACK                        regSQ_INT_ACK;
+typedef union SQ_DEBUG_INPUT_FSM                regSQ_DEBUG_INPUT_FSM;
+typedef union SQ_DEBUG_CONST_MGR_FSM            regSQ_DEBUG_CONST_MGR_FSM;
+typedef union SQ_DEBUG_TP_FSM                   regSQ_DEBUG_TP_FSM;
+typedef union SQ_DEBUG_FSM_ALU_0                regSQ_DEBUG_FSM_ALU_0;
+typedef union SQ_DEBUG_FSM_ALU_1                regSQ_DEBUG_FSM_ALU_1;
+typedef union SQ_DEBUG_EXP_ALLOC                regSQ_DEBUG_EXP_ALLOC;
+typedef union SQ_DEBUG_PTR_BUFF                 regSQ_DEBUG_PTR_BUFF;
+typedef union SQ_DEBUG_GPR_VTX                  regSQ_DEBUG_GPR_VTX;
+typedef union SQ_DEBUG_GPR_PIX                  regSQ_DEBUG_GPR_PIX;
+typedef union SQ_DEBUG_TB_STATUS_SEL            regSQ_DEBUG_TB_STATUS_SEL;
+typedef union SQ_DEBUG_VTX_TB_0                 regSQ_DEBUG_VTX_TB_0;
+typedef union SQ_DEBUG_VTX_TB_1                 regSQ_DEBUG_VTX_TB_1;
+typedef union SQ_DEBUG_VTX_TB_STATUS_REG        regSQ_DEBUG_VTX_TB_STATUS_REG;
+typedef union SQ_DEBUG_VTX_TB_STATE_MEM         regSQ_DEBUG_VTX_TB_STATE_MEM;
+typedef union SQ_DEBUG_PIX_TB_0                 regSQ_DEBUG_PIX_TB_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0      regSQ_DEBUG_PIX_TB_STATUS_REG_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1      regSQ_DEBUG_PIX_TB_STATUS_REG_1;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2      regSQ_DEBUG_PIX_TB_STATUS_REG_2;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3      regSQ_DEBUG_PIX_TB_STATUS_REG_3;
+typedef union SQ_DEBUG_PIX_TB_STATE_MEM         regSQ_DEBUG_PIX_TB_STATE_MEM;
+typedef union SQ_PERFCOUNTER0_SELECT            regSQ_PERFCOUNTER0_SELECT;
+typedef union SQ_PERFCOUNTER1_SELECT            regSQ_PERFCOUNTER1_SELECT;
+typedef union SQ_PERFCOUNTER2_SELECT            regSQ_PERFCOUNTER2_SELECT;
+typedef union SQ_PERFCOUNTER3_SELECT            regSQ_PERFCOUNTER3_SELECT;
+typedef union SQ_PERFCOUNTER0_LOW               regSQ_PERFCOUNTER0_LOW;
+typedef union SQ_PERFCOUNTER0_HI                regSQ_PERFCOUNTER0_HI;
+typedef union SQ_PERFCOUNTER1_LOW               regSQ_PERFCOUNTER1_LOW;
+typedef union SQ_PERFCOUNTER1_HI                regSQ_PERFCOUNTER1_HI;
+typedef union SQ_PERFCOUNTER2_LOW               regSQ_PERFCOUNTER2_LOW;
+typedef union SQ_PERFCOUNTER2_HI                regSQ_PERFCOUNTER2_HI;
+typedef union SQ_PERFCOUNTER3_LOW               regSQ_PERFCOUNTER3_LOW;
+typedef union SQ_PERFCOUNTER3_HI                regSQ_PERFCOUNTER3_HI;
+typedef union SX_PERFCOUNTER0_SELECT            regSX_PERFCOUNTER0_SELECT;
+typedef union SX_PERFCOUNTER0_LOW               regSX_PERFCOUNTER0_LOW;
+typedef union SX_PERFCOUNTER0_HI                regSX_PERFCOUNTER0_HI;
+typedef union SQ_INSTRUCTION_ALU_0              regSQ_INSTRUCTION_ALU_0;
+typedef union SQ_INSTRUCTION_ALU_1              regSQ_INSTRUCTION_ALU_1;
+typedef union SQ_INSTRUCTION_ALU_2              regSQ_INSTRUCTION_ALU_2;
+typedef union SQ_INSTRUCTION_CF_EXEC_0          regSQ_INSTRUCTION_CF_EXEC_0;
+typedef union SQ_INSTRUCTION_CF_EXEC_1          regSQ_INSTRUCTION_CF_EXEC_1;
+typedef union SQ_INSTRUCTION_CF_EXEC_2          regSQ_INSTRUCTION_CF_EXEC_2;
+typedef union SQ_INSTRUCTION_CF_LOOP_0          regSQ_INSTRUCTION_CF_LOOP_0;
+typedef union SQ_INSTRUCTION_CF_LOOP_1          regSQ_INSTRUCTION_CF_LOOP_1;
+typedef union SQ_INSTRUCTION_CF_LOOP_2          regSQ_INSTRUCTION_CF_LOOP_2;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_0      regSQ_INSTRUCTION_CF_JMP_CALL_0;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_1      regSQ_INSTRUCTION_CF_JMP_CALL_1;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_2      regSQ_INSTRUCTION_CF_JMP_CALL_2;
+typedef union SQ_INSTRUCTION_CF_ALLOC_0         regSQ_INSTRUCTION_CF_ALLOC_0;
+typedef union SQ_INSTRUCTION_CF_ALLOC_1         regSQ_INSTRUCTION_CF_ALLOC_1;
+typedef union SQ_INSTRUCTION_CF_ALLOC_2         regSQ_INSTRUCTION_CF_ALLOC_2;
+typedef union SQ_INSTRUCTION_TFETCH_0           regSQ_INSTRUCTION_TFETCH_0;
+typedef union SQ_INSTRUCTION_TFETCH_1           regSQ_INSTRUCTION_TFETCH_1;
+typedef union SQ_INSTRUCTION_TFETCH_2           regSQ_INSTRUCTION_TFETCH_2;
+typedef union SQ_INSTRUCTION_VFETCH_0           regSQ_INSTRUCTION_VFETCH_0;
+typedef union SQ_INSTRUCTION_VFETCH_1           regSQ_INSTRUCTION_VFETCH_1;
+typedef union SQ_INSTRUCTION_VFETCH_2           regSQ_INSTRUCTION_VFETCH_2;
+typedef union SQ_CONSTANT_0                     regSQ_CONSTANT_0;
+typedef union SQ_CONSTANT_1                     regSQ_CONSTANT_1;
+typedef union SQ_CONSTANT_2                     regSQ_CONSTANT_2;
+typedef union SQ_CONSTANT_3                     regSQ_CONSTANT_3;
+typedef union SQ_FETCH_0                        regSQ_FETCH_0;
+typedef union SQ_FETCH_1                        regSQ_FETCH_1;
+typedef union SQ_FETCH_2                        regSQ_FETCH_2;
+typedef union SQ_FETCH_3                        regSQ_FETCH_3;
+typedef union SQ_FETCH_4                        regSQ_FETCH_4;
+typedef union SQ_FETCH_5                        regSQ_FETCH_5;
+typedef union SQ_CONSTANT_VFETCH_0              regSQ_CONSTANT_VFETCH_0;
+typedef union SQ_CONSTANT_VFETCH_1              regSQ_CONSTANT_VFETCH_1;
+typedef union SQ_CONSTANT_T2                    regSQ_CONSTANT_T2;
+typedef union SQ_CONSTANT_T3                    regSQ_CONSTANT_T3;
+typedef union SQ_CF_BOOLEANS                    regSQ_CF_BOOLEANS;
+typedef union SQ_CF_LOOP                        regSQ_CF_LOOP;
+typedef union SQ_CONSTANT_RT_0                  regSQ_CONSTANT_RT_0;
+typedef union SQ_CONSTANT_RT_1                  regSQ_CONSTANT_RT_1;
+typedef union SQ_CONSTANT_RT_2                  regSQ_CONSTANT_RT_2;
+typedef union SQ_CONSTANT_RT_3                  regSQ_CONSTANT_RT_3;
+typedef union SQ_FETCH_RT_0                     regSQ_FETCH_RT_0;
+typedef union SQ_FETCH_RT_1                     regSQ_FETCH_RT_1;
+typedef union SQ_FETCH_RT_2                     regSQ_FETCH_RT_2;
+typedef union SQ_FETCH_RT_3                     regSQ_FETCH_RT_3;
+typedef union SQ_FETCH_RT_4                     regSQ_FETCH_RT_4;
+typedef union SQ_FETCH_RT_5                     regSQ_FETCH_RT_5;
+typedef union SQ_CF_RT_BOOLEANS                 regSQ_CF_RT_BOOLEANS;
+typedef union SQ_CF_RT_LOOP                     regSQ_CF_RT_LOOP;
+typedef union SQ_VS_PROGRAM                     regSQ_VS_PROGRAM;
+typedef union SQ_PS_PROGRAM                     regSQ_PS_PROGRAM;
+typedef union SQ_CF_PROGRAM_SIZE                regSQ_CF_PROGRAM_SIZE;
+typedef union SQ_INTERPOLATOR_CNTL              regSQ_INTERPOLATOR_CNTL;
+typedef union SQ_PROGRAM_CNTL                   regSQ_PROGRAM_CNTL;
+typedef union SQ_WRAPPING_0                     regSQ_WRAPPING_0;
+typedef union SQ_WRAPPING_1                     regSQ_WRAPPING_1;
+typedef union SQ_VS_CONST                       regSQ_VS_CONST;
+typedef union SQ_PS_CONST                       regSQ_PS_CONST;
+typedef union SQ_CONTEXT_MISC                   regSQ_CONTEXT_MISC;
+typedef union SQ_CF_RD_BASE                     regSQ_CF_RD_BASE;
+typedef union SQ_DEBUG_MISC_0                   regSQ_DEBUG_MISC_0;
+typedef union SQ_DEBUG_MISC_1                   regSQ_DEBUG_MISC_1;
+typedef union MH_ARBITER_CONFIG                 regMH_ARBITER_CONFIG;
+typedef union MH_CLNT_AXI_ID_REUSE              regMH_CLNT_AXI_ID_REUSE;
+typedef union MH_INTERRUPT_MASK                 regMH_INTERRUPT_MASK;
+typedef union MH_INTERRUPT_STATUS               regMH_INTERRUPT_STATUS;
+typedef union MH_INTERRUPT_CLEAR                regMH_INTERRUPT_CLEAR;
+typedef union MH_AXI_ERROR                      regMH_AXI_ERROR;
+typedef union MH_PERFCOUNTER0_SELECT            regMH_PERFCOUNTER0_SELECT;
+typedef union MH_PERFCOUNTER1_SELECT            regMH_PERFCOUNTER1_SELECT;
+typedef union MH_PERFCOUNTER0_CONFIG            regMH_PERFCOUNTER0_CONFIG;
+typedef union MH_PERFCOUNTER1_CONFIG            regMH_PERFCOUNTER1_CONFIG;
+typedef union MH_PERFCOUNTER0_LOW               regMH_PERFCOUNTER0_LOW;
+typedef union MH_PERFCOUNTER1_LOW               regMH_PERFCOUNTER1_LOW;
+typedef union MH_PERFCOUNTER0_HI                regMH_PERFCOUNTER0_HI;
+typedef union MH_PERFCOUNTER1_HI                regMH_PERFCOUNTER1_HI;
+typedef union MH_DEBUG_CTRL                     regMH_DEBUG_CTRL;
+typedef union MH_DEBUG_DATA                     regMH_DEBUG_DATA;
+typedef union MH_AXI_HALT_CONTROL               regMH_AXI_HALT_CONTROL;
+typedef union MH_MMU_CONFIG                     regMH_MMU_CONFIG;
+typedef union MH_MMU_VA_RANGE                   regMH_MMU_VA_RANGE;
+typedef union MH_MMU_PT_BASE                    regMH_MMU_PT_BASE;
+typedef union MH_MMU_PAGE_FAULT                 regMH_MMU_PAGE_FAULT;
+typedef union MH_MMU_TRAN_ERROR                 regMH_MMU_TRAN_ERROR;
+typedef union MH_MMU_INVALIDATE                 regMH_MMU_INVALIDATE;
+typedef union MH_MMU_MPU_BASE                   regMH_MMU_MPU_BASE;
+typedef union MH_MMU_MPU_END                    regMH_MMU_MPU_END;
+typedef union WAIT_UNTIL                        regWAIT_UNTIL;
+typedef union RBBM_ISYNC_CNTL                   regRBBM_ISYNC_CNTL;
+typedef union RBBM_STATUS                       regRBBM_STATUS;
+typedef union RBBM_DSPLY                        regRBBM_DSPLY;
+typedef union RBBM_RENDER_LATEST                regRBBM_RENDER_LATEST;
+typedef union RBBM_RTL_RELEASE                  regRBBM_RTL_RELEASE;
+typedef union RBBM_PATCH_RELEASE                regRBBM_PATCH_RELEASE;
+typedef union RBBM_AUXILIARY_CONFIG             regRBBM_AUXILIARY_CONFIG;
+typedef union RBBM_PERIPHID0                    regRBBM_PERIPHID0;
+typedef union RBBM_PERIPHID1                    regRBBM_PERIPHID1;
+typedef union RBBM_PERIPHID2                    regRBBM_PERIPHID2;
+typedef union RBBM_PERIPHID3                    regRBBM_PERIPHID3;
+typedef union RBBM_CNTL                         regRBBM_CNTL;
+typedef union RBBM_SKEW_CNTL                    regRBBM_SKEW_CNTL;
+typedef union RBBM_SOFT_RESET                   regRBBM_SOFT_RESET;
+typedef union RBBM_PM_OVERRIDE1                 regRBBM_PM_OVERRIDE1;
+typedef union RBBM_PM_OVERRIDE2                 regRBBM_PM_OVERRIDE2;
+typedef union GC_SYS_IDLE                       regGC_SYS_IDLE;
+typedef union NQWAIT_UNTIL                      regNQWAIT_UNTIL;
+typedef union RBBM_DEBUG_OUT                    regRBBM_DEBUG_OUT;
+typedef union RBBM_DEBUG_CNTL                   regRBBM_DEBUG_CNTL;
+typedef union RBBM_DEBUG                        regRBBM_DEBUG;
+typedef union RBBM_READ_ERROR                   regRBBM_READ_ERROR;
+typedef union RBBM_WAIT_IDLE_CLOCKS             regRBBM_WAIT_IDLE_CLOCKS;
+typedef union RBBM_INT_CNTL                     regRBBM_INT_CNTL;
+typedef union RBBM_INT_STATUS                   regRBBM_INT_STATUS;
+typedef union RBBM_INT_ACK                      regRBBM_INT_ACK;
+typedef union MASTER_INT_SIGNAL                 regMASTER_INT_SIGNAL;
+typedef union RBBM_PERFCOUNTER1_SELECT          regRBBM_PERFCOUNTER1_SELECT;
+typedef union RBBM_PERFCOUNTER1_LO              regRBBM_PERFCOUNTER1_LO;
+typedef union RBBM_PERFCOUNTER1_HI              regRBBM_PERFCOUNTER1_HI;
+typedef union CP_RB_BASE                        regCP_RB_BASE;
+typedef union CP_RB_CNTL                        regCP_RB_CNTL;
+typedef union CP_RB_RPTR_ADDR                   regCP_RB_RPTR_ADDR;
+typedef union CP_RB_RPTR                        regCP_RB_RPTR;
+typedef union CP_RB_RPTR_WR                     regCP_RB_RPTR_WR;
+typedef union CP_RB_WPTR                        regCP_RB_WPTR;
+typedef union CP_RB_WPTR_DELAY                  regCP_RB_WPTR_DELAY;
+typedef union CP_RB_WPTR_BASE                   regCP_RB_WPTR_BASE;
+typedef union CP_IB1_BASE                       regCP_IB1_BASE;
+typedef union CP_IB1_BUFSZ                      regCP_IB1_BUFSZ;
+typedef union CP_IB2_BASE                       regCP_IB2_BASE;
+typedef union CP_IB2_BUFSZ                      regCP_IB2_BUFSZ;
+typedef union CP_ST_BASE                        regCP_ST_BASE;
+typedef union CP_ST_BUFSZ                       regCP_ST_BUFSZ;
+typedef union CP_QUEUE_THRESHOLDS               regCP_QUEUE_THRESHOLDS;
+typedef union CP_MEQ_THRESHOLDS                 regCP_MEQ_THRESHOLDS;
+typedef union CP_CSQ_AVAIL                      regCP_CSQ_AVAIL;
+typedef union CP_STQ_AVAIL                      regCP_STQ_AVAIL;
+typedef union CP_MEQ_AVAIL                      regCP_MEQ_AVAIL;
+typedef union CP_CSQ_RB_STAT                    regCP_CSQ_RB_STAT;
+typedef union CP_CSQ_IB1_STAT                   regCP_CSQ_IB1_STAT;
+typedef union CP_CSQ_IB2_STAT                   regCP_CSQ_IB2_STAT;
+typedef union CP_NON_PREFETCH_CNTRS             regCP_NON_PREFETCH_CNTRS;
+typedef union CP_STQ_ST_STAT                    regCP_STQ_ST_STAT;
+typedef union CP_MEQ_STAT                       regCP_MEQ_STAT;
+typedef union CP_MIU_TAG_STAT                   regCP_MIU_TAG_STAT;
+typedef union CP_CMD_INDEX                      regCP_CMD_INDEX;
+typedef union CP_CMD_DATA                       regCP_CMD_DATA;
+typedef union CP_ME_CNTL                        regCP_ME_CNTL;
+typedef union CP_ME_STATUS                      regCP_ME_STATUS;
+typedef union CP_ME_RAM_WADDR                   regCP_ME_RAM_WADDR;
+typedef union CP_ME_RAM_RADDR                   regCP_ME_RAM_RADDR;
+typedef union CP_ME_RAM_DATA                    regCP_ME_RAM_DATA;
+typedef union CP_ME_RDADDR                      regCP_ME_RDADDR;
+typedef union CP_DEBUG                          regCP_DEBUG;
+typedef union SCRATCH_REG0                      regSCRATCH_REG0;
+typedef union GUI_SCRATCH_REG0                  regGUI_SCRATCH_REG0;
+typedef union SCRATCH_REG1                      regSCRATCH_REG1;
+typedef union GUI_SCRATCH_REG1                  regGUI_SCRATCH_REG1;
+typedef union SCRATCH_REG2                      regSCRATCH_REG2;
+typedef union GUI_SCRATCH_REG2                  regGUI_SCRATCH_REG2;
+typedef union SCRATCH_REG3                      regSCRATCH_REG3;
+typedef union GUI_SCRATCH_REG3                  regGUI_SCRATCH_REG3;
+typedef union SCRATCH_REG4                      regSCRATCH_REG4;
+typedef union GUI_SCRATCH_REG4                  regGUI_SCRATCH_REG4;
+typedef union SCRATCH_REG5                      regSCRATCH_REG5;
+typedef union GUI_SCRATCH_REG5                  regGUI_SCRATCH_REG5;
+typedef union SCRATCH_REG6                      regSCRATCH_REG6;
+typedef union GUI_SCRATCH_REG6                  regGUI_SCRATCH_REG6;
+typedef union SCRATCH_REG7                      regSCRATCH_REG7;
+typedef union GUI_SCRATCH_REG7                  regGUI_SCRATCH_REG7;
+typedef union SCRATCH_UMSK                      regSCRATCH_UMSK;
+typedef union SCRATCH_ADDR                      regSCRATCH_ADDR;
+typedef union CP_ME_VS_EVENT_SRC                regCP_ME_VS_EVENT_SRC;
+typedef union CP_ME_VS_EVENT_ADDR               regCP_ME_VS_EVENT_ADDR;
+typedef union CP_ME_VS_EVENT_DATA               regCP_ME_VS_EVENT_DATA;
+typedef union CP_ME_VS_EVENT_ADDR_SWM           regCP_ME_VS_EVENT_ADDR_SWM;
+typedef union CP_ME_VS_EVENT_DATA_SWM           regCP_ME_VS_EVENT_DATA_SWM;
+typedef union CP_ME_PS_EVENT_SRC                regCP_ME_PS_EVENT_SRC;
+typedef union CP_ME_PS_EVENT_ADDR               regCP_ME_PS_EVENT_ADDR;
+typedef union CP_ME_PS_EVENT_DATA               regCP_ME_PS_EVENT_DATA;
+typedef union CP_ME_PS_EVENT_ADDR_SWM           regCP_ME_PS_EVENT_ADDR_SWM;
+typedef union CP_ME_PS_EVENT_DATA_SWM           regCP_ME_PS_EVENT_DATA_SWM;
+typedef union CP_ME_CF_EVENT_SRC                regCP_ME_CF_EVENT_SRC;
+typedef union CP_ME_CF_EVENT_ADDR               regCP_ME_CF_EVENT_ADDR;
+typedef union CP_ME_CF_EVENT_DATA               regCP_ME_CF_EVENT_DATA;
+typedef union CP_ME_NRT_ADDR                    regCP_ME_NRT_ADDR;
+typedef union CP_ME_NRT_DATA                    regCP_ME_NRT_DATA;
+typedef union CP_ME_VS_FETCH_DONE_SRC           regCP_ME_VS_FETCH_DONE_SRC;
+typedef union CP_ME_VS_FETCH_DONE_ADDR          regCP_ME_VS_FETCH_DONE_ADDR;
+typedef union CP_ME_VS_FETCH_DONE_DATA          regCP_ME_VS_FETCH_DONE_DATA;
+typedef union CP_INT_CNTL                       regCP_INT_CNTL;
+typedef union CP_INT_STATUS                     regCP_INT_STATUS;
+typedef union CP_INT_ACK                        regCP_INT_ACK;
+typedef union CP_PFP_UCODE_ADDR                 regCP_PFP_UCODE_ADDR;
+typedef union CP_PFP_UCODE_DATA                 regCP_PFP_UCODE_DATA;
+typedef union CP_PERFMON_CNTL                   regCP_PERFMON_CNTL;
+typedef union CP_PERFCOUNTER_SELECT             regCP_PERFCOUNTER_SELECT;
+typedef union CP_PERFCOUNTER_LO                 regCP_PERFCOUNTER_LO;
+typedef union CP_PERFCOUNTER_HI                 regCP_PERFCOUNTER_HI;
+typedef union CP_BIN_MASK_LO                    regCP_BIN_MASK_LO;
+typedef union CP_BIN_MASK_HI                    regCP_BIN_MASK_HI;
+typedef union CP_BIN_SELECT_LO                  regCP_BIN_SELECT_LO;
+typedef union CP_BIN_SELECT_HI                  regCP_BIN_SELECT_HI;
+typedef union CP_NV_FLAGS_0                     regCP_NV_FLAGS_0;
+typedef union CP_NV_FLAGS_1                     regCP_NV_FLAGS_1;
+typedef union CP_NV_FLAGS_2                     regCP_NV_FLAGS_2;
+typedef union CP_NV_FLAGS_3                     regCP_NV_FLAGS_3;
+typedef union CP_STATE_DEBUG_INDEX              regCP_STATE_DEBUG_INDEX;
+typedef union CP_STATE_DEBUG_DATA               regCP_STATE_DEBUG_DATA;
+typedef union CP_PROG_COUNTER                   regCP_PROG_COUNTER;
+typedef union CP_STAT                           regCP_STAT;
+typedef union BIOS_0_SCRATCH                    regBIOS_0_SCRATCH;
+typedef union BIOS_1_SCRATCH                    regBIOS_1_SCRATCH;
+typedef union BIOS_2_SCRATCH                    regBIOS_2_SCRATCH;
+typedef union BIOS_3_SCRATCH                    regBIOS_3_SCRATCH;
+typedef union BIOS_4_SCRATCH                    regBIOS_4_SCRATCH;
+typedef union BIOS_5_SCRATCH                    regBIOS_5_SCRATCH;
+typedef union BIOS_6_SCRATCH                    regBIOS_6_SCRATCH;
+typedef union BIOS_7_SCRATCH                    regBIOS_7_SCRATCH;
+typedef union BIOS_8_SCRATCH                    regBIOS_8_SCRATCH;
+typedef union BIOS_9_SCRATCH                    regBIOS_9_SCRATCH;
+typedef union BIOS_10_SCRATCH                   regBIOS_10_SCRATCH;
+typedef union BIOS_11_SCRATCH                   regBIOS_11_SCRATCH;
+typedef union BIOS_12_SCRATCH                   regBIOS_12_SCRATCH;
+typedef union BIOS_13_SCRATCH                   regBIOS_13_SCRATCH;
+typedef union BIOS_14_SCRATCH                   regBIOS_14_SCRATCH;
+typedef union BIOS_15_SCRATCH                   regBIOS_15_SCRATCH;
+typedef union COHER_SIZE_PM4                    regCOHER_SIZE_PM4;
+typedef union COHER_BASE_PM4                    regCOHER_BASE_PM4;
+typedef union COHER_STATUS_PM4                  regCOHER_STATUS_PM4;
+typedef union COHER_SIZE_HOST                   regCOHER_SIZE_HOST;
+typedef union COHER_BASE_HOST                   regCOHER_BASE_HOST;
+typedef union COHER_STATUS_HOST                 regCOHER_STATUS_HOST;
+typedef union COHER_DEST_BASE_0                 regCOHER_DEST_BASE_0;
+typedef union COHER_DEST_BASE_1                 regCOHER_DEST_BASE_1;
+typedef union COHER_DEST_BASE_2                 regCOHER_DEST_BASE_2;
+typedef union COHER_DEST_BASE_3                 regCOHER_DEST_BASE_3;
+typedef union COHER_DEST_BASE_4                 regCOHER_DEST_BASE_4;
+typedef union COHER_DEST_BASE_5                 regCOHER_DEST_BASE_5;
+typedef union COHER_DEST_BASE_6                 regCOHER_DEST_BASE_6;
+typedef union COHER_DEST_BASE_7                 regCOHER_DEST_BASE_7;
+typedef union RB_SURFACE_INFO                   regRB_SURFACE_INFO;
+typedef union RB_COLOR_INFO                     regRB_COLOR_INFO;
+typedef union RB_DEPTH_INFO                     regRB_DEPTH_INFO;
+typedef union RB_STENCILREFMASK                 regRB_STENCILREFMASK;
+typedef union RB_ALPHA_REF                      regRB_ALPHA_REF;
+typedef union RB_COLOR_MASK                     regRB_COLOR_MASK;
+typedef union RB_BLEND_RED                      regRB_BLEND_RED;
+typedef union RB_BLEND_GREEN                    regRB_BLEND_GREEN;
+typedef union RB_BLEND_BLUE                     regRB_BLEND_BLUE;
+typedef union RB_BLEND_ALPHA                    regRB_BLEND_ALPHA;
+typedef union RB_FOG_COLOR                      regRB_FOG_COLOR;
+typedef union RB_STENCILREFMASK_BF              regRB_STENCILREFMASK_BF;
+typedef union RB_DEPTHCONTROL                   regRB_DEPTHCONTROL;
+typedef union RB_BLENDCONTROL                   regRB_BLENDCONTROL;
+typedef union RB_COLORCONTROL                   regRB_COLORCONTROL;
+typedef union RB_MODECONTROL                    regRB_MODECONTROL;
+typedef union RB_COLOR_DEST_MASK                regRB_COLOR_DEST_MASK;
+typedef union RB_COPY_CONTROL                   regRB_COPY_CONTROL;
+typedef union RB_COPY_DEST_BASE                 regRB_COPY_DEST_BASE;
+typedef union RB_COPY_DEST_PITCH                regRB_COPY_DEST_PITCH;
+typedef union RB_COPY_DEST_INFO                 regRB_COPY_DEST_INFO;
+typedef union RB_COPY_DEST_PIXEL_OFFSET         regRB_COPY_DEST_PIXEL_OFFSET;
+typedef union RB_DEPTH_CLEAR                    regRB_DEPTH_CLEAR;
+typedef union RB_SAMPLE_COUNT_CTL               regRB_SAMPLE_COUNT_CTL;
+typedef union RB_SAMPLE_COUNT_ADDR              regRB_SAMPLE_COUNT_ADDR;
+typedef union RB_BC_CONTROL                     regRB_BC_CONTROL;
+typedef union RB_EDRAM_INFO                     regRB_EDRAM_INFO;
+typedef union RB_CRC_RD_PORT                    regRB_CRC_RD_PORT;
+typedef union RB_CRC_CONTROL                    regRB_CRC_CONTROL;
+typedef union RB_CRC_MASK                       regRB_CRC_MASK;
+typedef union RB_PERFCOUNTER0_SELECT            regRB_PERFCOUNTER0_SELECT;
+typedef union RB_PERFCOUNTER0_LOW               regRB_PERFCOUNTER0_LOW;
+typedef union RB_PERFCOUNTER0_HI                regRB_PERFCOUNTER0_HI;
+typedef union RB_TOTAL_SAMPLES                  regRB_TOTAL_SAMPLES;
+typedef union RB_ZPASS_SAMPLES                  regRB_ZPASS_SAMPLES;
+typedef union RB_ZFAIL_SAMPLES                  regRB_ZFAIL_SAMPLES;
+typedef union RB_SFAIL_SAMPLES                  regRB_SFAIL_SAMPLES;
+typedef union RB_DEBUG_0                        regRB_DEBUG_0;
+typedef union RB_DEBUG_1                        regRB_DEBUG_1;
+typedef union RB_DEBUG_2                        regRB_DEBUG_2;
+typedef union RB_DEBUG_3                        regRB_DEBUG_3;
+typedef union RB_DEBUG_4                        regRB_DEBUG_4;
+typedef union RB_FLAG_CONTROL                   regRB_FLAG_CONTROL;
+typedef union RB_BC_SPARES                      regRB_BC_SPARES;
+typedef union BC_DUMMY_CRAYRB_ENUMS             regBC_DUMMY_CRAYRB_ENUMS;
+typedef union BC_DUMMY_CRAYRB_MOREENUMS         regBC_DUMMY_CRAYRB_MOREENUMS;
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h
new file mode 100644
index 000000000000..ba259a6c9d5f
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h
@@ -0,0 +1,169 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _yamatoix_h
+#define _yamatoix_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
+
+// [SUDEBUGIND] : Indirect Registers
+
+#define ixCLIPPER_DEBUG_REG00                      0x0000
+#define ixCLIPPER_DEBUG_REG01                      0x0001
+#define ixCLIPPER_DEBUG_REG02                      0x0002
+#define ixCLIPPER_DEBUG_REG03                      0x0003
+#define ixCLIPPER_DEBUG_REG04                      0x0004
+#define ixCLIPPER_DEBUG_REG05                      0x0005
+#define ixCLIPPER_DEBUG_REG09                      0x0009
+#define ixCLIPPER_DEBUG_REG10                      0x000A
+#define ixCLIPPER_DEBUG_REG11                      0x000B
+#define ixCLIPPER_DEBUG_REG12                      0x000C
+#define ixCLIPPER_DEBUG_REG13                      0x000D
+#define ixSXIFCCG_DEBUG_REG0                       0x0011
+#define ixSXIFCCG_DEBUG_REG1                       0x0012
+#define ixSXIFCCG_DEBUG_REG2                       0x0013
+#define ixSXIFCCG_DEBUG_REG3                       0x0014
+#define ixSETUP_DEBUG_REG0                         0x0015
+#define ixSETUP_DEBUG_REG1                         0x0016
+#define ixSETUP_DEBUG_REG2                         0x0017
+#define ixSETUP_DEBUG_REG3                         0x0018
+#define ixSETUP_DEBUG_REG4                         0x0019
+#define ixSETUP_DEBUG_REG5                         0x001A
+
+// [SCDEBUGIND] : Indirect Registers
+
+#define ixSC_DEBUG_0                               0x0000
+#define ixSC_DEBUG_1                               0x0001
+#define ixSC_DEBUG_2                               0x0002
+#define ixSC_DEBUG_3                               0x0003
+#define ixSC_DEBUG_4                               0x0004
+#define ixSC_DEBUG_5                               0x0005
+#define ixSC_DEBUG_6                               0x0006
+#define ixSC_DEBUG_7                               0x0007
+#define ixSC_DEBUG_8                               0x0008
+#define ixSC_DEBUG_9                               0x0009
+#define ixSC_DEBUG_10                              0x000A
+#define ixSC_DEBUG_11                              0x000B
+#define ixSC_DEBUG_12                              0x000C
+
+// [VGTDEBUGIND] : Indirect Registers
+
+#define ixVGT_DEBUG_REG0                           0x0000
+#define ixVGT_DEBUG_REG1                           0x0001
+#define ixVGT_DEBUG_REG3                           0x0003
+#define ixVGT_DEBUG_REG6                           0x0006
+#define ixVGT_DEBUG_REG7                           0x0007
+#define ixVGT_DEBUG_REG8                           0x0008
+#define ixVGT_DEBUG_REG9                           0x0009
+#define ixVGT_DEBUG_REG10                          0x000A
+#define ixVGT_DEBUG_REG12                          0x000C
+#define ixVGT_DEBUG_REG13                          0x000D
+#define ixVGT_DEBUG_REG14                          0x000E
+#define ixVGT_DEBUG_REG15                          0x000F
+#define ixVGT_DEBUG_REG16                          0x0010
+#define ixVGT_DEBUG_REG17                          0x0011
+#define ixVGT_DEBUG_REG18                          0x0012
+#define ixVGT_DEBUG_REG20                          0x0014
+#define ixVGT_DEBUG_REG21                          0x0015
+
+// [MHDEBUGIND] : Indirect Registers
+
+#define ixMH_DEBUG_REG00                           0x0000
+#define ixMH_DEBUG_REG01                           0x0001
+#define ixMH_DEBUG_REG02                           0x0002
+#define ixMH_DEBUG_REG03                           0x0003
+#define ixMH_DEBUG_REG04                           0x0004
+#define ixMH_DEBUG_REG05                           0x0005
+#define ixMH_DEBUG_REG06                           0x0006
+#define ixMH_DEBUG_REG07                           0x0007
+#define ixMH_DEBUG_REG08                           0x0008
+#define ixMH_DEBUG_REG09                           0x0009
+#define ixMH_DEBUG_REG10                           0x000A
+#define ixMH_DEBUG_REG11                           0x000B
+#define ixMH_DEBUG_REG12                           0x000C
+#define ixMH_DEBUG_REG13                           0x000D
+#define ixMH_DEBUG_REG14                           0x000E
+#define ixMH_DEBUG_REG15                           0x000F
+#define ixMH_DEBUG_REG16                           0x0010
+#define ixMH_DEBUG_REG17                           0x0011
+#define ixMH_DEBUG_REG18                           0x0012
+#define ixMH_DEBUG_REG19                           0x0013
+#define ixMH_DEBUG_REG20                           0x0014
+#define ixMH_DEBUG_REG21                           0x0015
+#define ixMH_DEBUG_REG22                           0x0016
+#define ixMH_DEBUG_REG23                           0x0017
+#define ixMH_DEBUG_REG24                           0x0018
+#define ixMH_DEBUG_REG25                           0x0019
+#define ixMH_DEBUG_REG26                           0x001A
+#define ixMH_DEBUG_REG27                           0x001B
+#define ixMH_DEBUG_REG28                           0x001C
+#define ixMH_DEBUG_REG29                           0x001D
+#define ixMH_DEBUG_REG30                           0x001E
+#define ixMH_DEBUG_REG31                           0x001F
+#define ixMH_DEBUG_REG32                           0x0020
+#define ixMH_DEBUG_REG33                           0x0021
+#define ixMH_DEBUG_REG34                           0x0022
+#define ixMH_DEBUG_REG35                           0x0023
+#define ixMH_DEBUG_REG36                           0x0024
+#define ixMH_DEBUG_REG37                           0x0025
+#define ixMH_DEBUG_REG38                           0x0026
+#define ixMH_DEBUG_REG39                           0x0027
+#define ixMH_DEBUG_REG40                           0x0028
+#define ixMH_DEBUG_REG41                           0x0029
+#define ixMH_DEBUG_REG42                           0x002A
+#define ixMH_DEBUG_REG43                           0x002B
+#define ixMH_DEBUG_REG44                           0x002C
+#define ixMH_DEBUG_REG45                           0x002D
+#define ixMH_DEBUG_REG46                           0x002E
+#define ixMH_DEBUG_REG47                           0x002F
+#define ixMH_DEBUG_REG48                           0x0030
+#define ixMH_DEBUG_REG49                           0x0031
+#define ixMH_DEBUG_REG50                           0x0032
+#define ixMH_DEBUG_REG51                           0x0033
+#define ixMH_DEBUG_REG52                           0x0034
+#define ixMH_DEBUG_REG53                           0x0035
+#define ixMH_DEBUG_REG54                           0x0036
+#define ixMH_DEBUG_REG55                           0x0037
+#define ixMH_DEBUG_REG56                           0x0038
+#define ixMH_DEBUG_REG57                           0x0039
+#define ixMH_DEBUG_REG58                           0x003A
+#define ixMH_DEBUG_REG59                           0x003B
+#define ixMH_DEBUG_REG60                           0x003C
+#define ixMH_DEBUG_REG61                           0x003D
+#define ixMH_DEBUG_REG62                           0x003E
+#define ixMH_DEBUG_REG63                           0x003F
+
+
+#ifdef __cplusplus
+}
+#endif  // __cplusplus
+
+#endif // _yamatob_h
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h
new file mode 100644
index 000000000000..ab11205f1092
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h
@@ -0,0 +1,1867 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_ENUM_HEADER)
+#define _yamato_ENUM_HEADER
+
+
+
+#ifndef _DRIVER_BUILD
+#ifndef GL_ZERO
+#define GL__ZERO                      BLEND_ZERO
+#define GL__ONE                       BLEND_ONE
+#define GL__SRC_COLOR                 BLEND_SRC_COLOR
+#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
+#define GL__DST_COLOR                 BLEND_DST_COLOR
+#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
+#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
+#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
+#define GL__DST_ALPHA                 BLEND_DST_ALPHA
+#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
+#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
+#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
+#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
+#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
+#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
+#endif
+#endif
+
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+#ifndef ENUMS_SU_PERFCNT_SELECT_H
+#define ENUMS_SU_PERFCNT_SELECT_H
+typedef enum SU_PERFCNT_SELECT {
+ PERF_PAPC_PASX_REQ = 0,
+ UNUSED1 = 1,
+ PERF_PAPC_PASX_FIRST_VECTOR = 2,
+ PERF_PAPC_PASX_SECOND_VECTOR = 3,
+ PERF_PAPC_PASX_FIRST_DEAD = 4,
+ PERF_PAPC_PASX_SECOND_DEAD = 5,
+ PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
+ PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
+ PERF_PAPC_PA_INPUT_PRIM = 8,
+ PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
+ PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
+ PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
+ PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
+ PERF_PAPC_CLPR_CULL_PRIM = 13,
+ UNUSED2 = 14,
+ PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
+ UNUSED3 = 16,
+ PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
+ PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
+ PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
+ UNUSED4 = 20,
+ PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
+ UNUSED5 = 22,
+ PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
+ PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
+ PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
+ PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
+ PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
+ PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
+ PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
+ PERF_PAPC_CLSM_NULL_PRIM = 36,
+ PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
+ PERF_PAPC_CLSM_CLIP_PRIM = 38,
+ PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
+ PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
+ PERF_PAPC_SU_INPUT_PRIM = 47,
+ PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
+ PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
+ PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
+ PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
+ PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
+ PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
+ PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
+ PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
+ PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
+ PERF_PAPC_SU_OUTPUT_PRIM = 57,
+ PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
+ PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
+ PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
+ PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
+ PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
+ PERF_PAPC_PASX_REQ_IDLE = 69,
+ PERF_PAPC_PASX_REQ_BUSY = 70,
+ PERF_PAPC_PASX_REQ_STALLED = 71,
+ PERF_PAPC_PASX_REC_IDLE = 72,
+ PERF_PAPC_PASX_REC_BUSY = 73,
+ PERF_PAPC_PASX_REC_STARVED_SX = 74,
+ PERF_PAPC_PASX_REC_STALLED = 75,
+ PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
+ PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
+ PERF_PAPC_CCGSM_IDLE = 78,
+ PERF_PAPC_CCGSM_BUSY = 79,
+ PERF_PAPC_CCGSM_STALLED = 80,
+ PERF_PAPC_CLPRIM_IDLE = 81,
+ PERF_PAPC_CLPRIM_BUSY = 82,
+ PERF_PAPC_CLPRIM_STALLED = 83,
+ PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
+ PERF_PAPC_CLIPSM_IDLE = 85,
+ PERF_PAPC_CLIPSM_BUSY = 86,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
+ PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
+ PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
+ PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
+ PERF_PAPC_CLIPGA_IDLE = 92,
+ PERF_PAPC_CLIPGA_BUSY = 93,
+ PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
+ PERF_PAPC_CLIPGA_STALLED = 95,
+ PERF_PAPC_CLIP_IDLE = 96,
+ PERF_PAPC_CLIP_BUSY = 97,
+ PERF_PAPC_SU_IDLE = 98,
+ PERF_PAPC_SU_BUSY = 99,
+ PERF_PAPC_SU_STARVED_CLIP = 100,
+ PERF_PAPC_SU_STALLED_SC = 101,
+} SU_PERFCNT_SELECT;
+#endif /*ENUMS_SU_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SC_PERFCNT_SELECT_H
+#define ENUMS_SC_PERFCNT_SELECT_H
+typedef enum SC_PERFCNT_SELECT {
+ SC_SR_WINDOW_VALID = 0,
+ SC_CW_WINDOW_VALID = 1,
+ SC_QM_WINDOW_VALID = 2,
+ SC_FW_WINDOW_VALID = 3,
+ SC_EZ_WINDOW_VALID = 4,
+ SC_IT_WINDOW_VALID = 5,
+ SC_STARVED_BY_PA = 6,
+ SC_STALLED_BY_RB_TILE = 7,
+ SC_STALLED_BY_RB_SAMP = 8,
+ SC_STARVED_BY_RB_EZ = 9,
+ SC_STALLED_BY_SAMPLE_FF = 10,
+ SC_STALLED_BY_SQ = 11,
+ SC_STALLED_BY_SP = 12,
+ SC_TOTAL_NO_PRIMS = 13,
+ SC_NON_EMPTY_PRIMS = 14,
+ SC_NO_TILES_PASSING_QM = 15,
+ SC_NO_PIXELS_PRE_EZ = 16,
+ SC_NO_PIXELS_POST_EZ = 17,
+} SC_PERFCNT_SELECT;
+#endif /*ENUMS_SC_PERFCNT_SELECT_H*/
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+#ifndef ENUMS_VGT_DI_PRIM_TYPE_H
+#define ENUMS_VGT_DI_PRIM_TYPE_H
+typedef enum VGT_DI_PRIM_TYPE {
+ DI_PT_NONE = 0,
+ DI_PT_POINTLIST = 1,
+ DI_PT_LINELIST = 2,
+ DI_PT_LINESTRIP = 3,
+ DI_PT_TRILIST = 4,
+ DI_PT_TRIFAN = 5,
+ DI_PT_TRISTRIP = 6,
+ DI_PT_UNUSED_1 = 7,
+ DI_PT_RECTLIST = 8,
+ DI_PT_UNUSED_2 = 9,
+ DI_PT_UNUSED_3 = 10,
+ DI_PT_UNUSED_4 = 11,
+ DI_PT_UNUSED_5 = 12,
+ DI_PT_QUADLIST = 13,
+ DI_PT_QUADSTRIP = 14,
+ DI_PT_POLYGON = 15,
+ DI_PT_2D_COPY_RECT_LIST_V0 = 16,
+ DI_PT_2D_COPY_RECT_LIST_V1 = 17,
+ DI_PT_2D_COPY_RECT_LIST_V2 = 18,
+ DI_PT_2D_COPY_RECT_LIST_V3 = 19,
+ DI_PT_2D_FILL_RECT_LIST = 20,
+ DI_PT_2D_LINE_STRIP = 21,
+ DI_PT_2D_TRI_STRIP = 22,
+} VGT_DI_PRIM_TYPE;
+#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/
+
+#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H
+#define ENUMS_VGT_DI_SOURCE_SELECT_H
+typedef enum VGT_DI_SOURCE_SELECT {
+ DI_SRC_SEL_DMA = 0,
+ DI_SRC_SEL_IMMEDIATE = 1,
+ DI_SRC_SEL_AUTO_INDEX = 2,
+ DI_SRC_SEL_RESERVED = 3
+} VGT_DI_SOURCE_SELECT;
+#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_INDEX_SIZE_H
+#define ENUMS_VGT_DI_INDEX_SIZE_H
+typedef enum VGT_DI_INDEX_SIZE {
+ DI_INDEX_SIZE_16_BIT = 0,
+ DI_INDEX_SIZE_32_BIT = 1
+} VGT_DI_INDEX_SIZE;
+#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/
+
+#ifndef ENUMS_VGT_DI_SMALL_INDEX_H
+#define ENUMS_VGT_DI_SMALL_INDEX_H
+typedef enum VGT_DI_SMALL_INDEX {
+ DI_USE_INDEX_SIZE = 0,
+ DI_INDEX_SIZE_8_BIT = 1
+} VGT_DI_SMALL_INDEX;
+#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/
+
+#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE {
+ DISABLE_PRE_FETCH_CULL_ENABLE = 0,
+ PRE_FETCH_CULL_ENABLE = 1
+} VGT_DI_PRE_FETCH_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+typedef enum VGT_DI_GRP_CULL_ENABLE {
+ DISABLE_GRP_CULL_ENABLE = 0,
+ GRP_CULL_ENABLE = 1
+} VGT_DI_GRP_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_EVENT_TYPE_H
+#define ENUMS_VGT_EVENT_TYPE_H
+typedef enum VGT_EVENT_TYPE {
+ VS_DEALLOC = 0,
+ PS_DEALLOC = 1,
+ VS_DONE_TS = 2,
+ PS_DONE_TS = 3,
+ CACHE_FLUSH_TS = 4,
+ CONTEXT_DONE = 5,
+ CACHE_FLUSH = 6,
+ VIZQUERY_START = 7,
+ VIZQUERY_END = 8,
+ SC_WAIT_WC = 9,
+ RST_PIX_CNT = 13,
+ RST_VTX_CNT = 14,
+ TILE_FLUSH = 15,
+ CACHE_FLUSH_AND_INV_TS_EVENT = 20,
+ ZPASS_DONE = 21,
+ CACHE_FLUSH_AND_INV_EVENT = 22,
+ PERFCOUNTER_START = 23,
+ PERFCOUNTER_STOP = 24,
+ VS_FETCH_DONE = 27,
+} VGT_EVENT_TYPE;
+#endif /*ENUMS_VGT_EVENT_TYPE_H*/
+
+#ifndef ENUMS_VGT_DMA_SWAP_MODE_H
+#define ENUMS_VGT_DMA_SWAP_MODE_H
+typedef enum VGT_DMA_SWAP_MODE {
+ VGT_DMA_SWAP_NONE = 0,
+ VGT_DMA_SWAP_16_BIT = 1,
+ VGT_DMA_SWAP_32_BIT = 2,
+ VGT_DMA_SWAP_WORD = 3
+} VGT_DMA_SWAP_MODE;
+#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/
+
+#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H
+#define ENUMS_VGT_PERFCOUNT_SELECT_H
+typedef enum VGT_PERFCOUNT_SELECT {
+ VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
+ VGT_SQ_SEND = 1,
+ VGT_SQ_STALLED = 2,
+ VGT_SQ_STARVED_BUSY = 3,
+ VGT_SQ_STARVED_IDLE = 4,
+ VGT_SQ_STATIC = 5,
+ VGT_PA_EVENT_WINDOW_ACTIVE = 6,
+ VGT_PA_CLIP_V_SEND = 7,
+ VGT_PA_CLIP_V_STALLED = 8,
+ VGT_PA_CLIP_V_STARVED_BUSY = 9,
+ VGT_PA_CLIP_V_STARVED_IDLE = 10,
+ VGT_PA_CLIP_V_STATIC = 11,
+ VGT_PA_CLIP_P_SEND = 12,
+ VGT_PA_CLIP_P_STALLED = 13,
+ VGT_PA_CLIP_P_STARVED_BUSY = 14,
+ VGT_PA_CLIP_P_STARVED_IDLE = 15,
+ VGT_PA_CLIP_P_STATIC = 16,
+ VGT_PA_CLIP_S_SEND = 17,
+ VGT_PA_CLIP_S_STALLED = 18,
+ VGT_PA_CLIP_S_STARVED_BUSY = 19,
+ VGT_PA_CLIP_S_STARVED_IDLE = 20,
+ VGT_PA_CLIP_S_STATIC = 21,
+ RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
+ RBIU_IMMED_DATA_FIFO_STARVED = 23,
+ RBIU_IMMED_DATA_FIFO_STALLED = 24,
+ RBIU_DMA_REQUEST_FIFO_STARVED = 25,
+ RBIU_DMA_REQUEST_FIFO_STALLED = 26,
+ RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
+ RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
+ BIN_PRIM_NEAR_CULL = 29,
+ BIN_PRIM_ZERO_CULL = 30,
+ BIN_PRIM_FAR_CULL = 31,
+ BIN_PRIM_BIN_CULL = 32,
+ SPARE33 = 33,
+ SPARE34 = 34,
+ SPARE35 = 35,
+ SPARE36 = 36,
+ SPARE37 = 37,
+ SPARE38 = 38,
+ SPARE39 = 39,
+ TE_SU_IN_VALID = 40,
+ TE_SU_IN_READ = 41,
+ TE_SU_IN_PRIM = 42,
+ TE_SU_IN_EOP = 43,
+ TE_SU_IN_NULL_PRIM = 44,
+ TE_WK_IN_VALID = 45,
+ TE_WK_IN_READ = 46,
+ TE_OUT_PRIM_VALID = 47,
+ TE_OUT_PRIM_READ = 48,
+} VGT_PERFCOUNT_SELECT;
+#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H
+#define ENUMS_TCR_PERFCOUNT_SELECT_H
+typedef enum TCR_PERFCOUNT_SELECT {
+ DGMMPD_IPMUX0_STALL = 0,
+ reserved_46 = 1,
+ reserved_47 = 2,
+ reserved_48 = 3,
+ DGMMPD_IPMUX_ALL_STALL = 4,
+ OPMUX0_L2_WRITES = 5,
+ reserved_49 = 6,
+ reserved_50 = 7,
+ reserved_51 = 8,
+} TCR_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TP_PERFCOUNT_SELECT_H
+#define ENUMS_TP_PERFCOUNT_SELECT_H
+typedef enum TP_PERFCOUNT_SELECT {
+ POINT_QUADS = 0,
+ BILIN_QUADS = 1,
+ ANISO_QUADS = 2,
+ MIP_QUADS = 3,
+ VOL_QUADS = 4,
+ MIP_VOL_QUADS = 5,
+ MIP_ANISO_QUADS = 6,
+ VOL_ANISO_QUADS = 7,
+ ANISO_2_1_QUADS = 8,
+ ANISO_4_1_QUADS = 9,
+ ANISO_6_1_QUADS = 10,
+ ANISO_8_1_QUADS = 11,
+ ANISO_10_1_QUADS = 12,
+ ANISO_12_1_QUADS = 13,
+ ANISO_14_1_QUADS = 14,
+ ANISO_16_1_QUADS = 15,
+ MIP_VOL_ANISO_QUADS = 16,
+ ALIGN_2_QUADS = 17,
+ ALIGN_4_QUADS = 18,
+ PIX_0_QUAD = 19,
+ PIX_1_QUAD = 20,
+ PIX_2_QUAD = 21,
+ PIX_3_QUAD = 22,
+ PIX_4_QUAD = 23,
+ TP_MIPMAP_LOD0 = 24,
+ TP_MIPMAP_LOD1 = 25,
+ TP_MIPMAP_LOD2 = 26,
+ TP_MIPMAP_LOD3 = 27,
+ TP_MIPMAP_LOD4 = 28,
+ TP_MIPMAP_LOD5 = 29,
+ TP_MIPMAP_LOD6 = 30,
+ TP_MIPMAP_LOD7 = 31,
+ TP_MIPMAP_LOD8 = 32,
+ TP_MIPMAP_LOD9 = 33,
+ TP_MIPMAP_LOD10 = 34,
+ TP_MIPMAP_LOD11 = 35,
+ TP_MIPMAP_LOD12 = 36,
+ TP_MIPMAP_LOD13 = 37,
+ TP_MIPMAP_LOD14 = 38,
+} TP_PERFCOUNT_SELECT;
+#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H
+#define ENUMS_TCM_PERFCOUNT_SELECT_H
+typedef enum TCM_PERFCOUNT_SELECT {
+ QUAD0_RD_LAT_FIFO_EMPTY = 0,
+ reserved_01 = 1,
+ reserved_02 = 2,
+ QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
+ QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
+ QUAD0_RD_LAT_FIFO_FULL = 5,
+ QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
+ reserved_07 = 7,
+ reserved_08 = 8,
+ reserved_09 = 9,
+ reserved_10 = 10,
+ reserved_11 = 11,
+ reserved_12 = 12,
+ reserved_13 = 13,
+ reserved_14 = 14,
+ reserved_15 = 15,
+ reserved_16 = 16,
+ reserved_17 = 17,
+ reserved_18 = 18,
+ reserved_19 = 19,
+ reserved_20 = 20,
+ reserved_21 = 21,
+ reserved_22 = 22,
+ reserved_23 = 23,
+ reserved_24 = 24,
+ reserved_25 = 25,
+ reserved_26 = 26,
+ reserved_27 = 27,
+ READ_STARVED_QUAD0 = 28,
+ reserved_29 = 29,
+ reserved_30 = 30,
+ reserved_31 = 31,
+ READ_STARVED = 32,
+ READ_STALLED_QUAD0 = 33,
+ reserved_34 = 34,
+ reserved_35 = 35,
+ reserved_36 = 36,
+ READ_STALLED = 37,
+ VALID_READ_QUAD0 = 38,
+ reserved_39 = 39,
+ reserved_40 = 40,
+ reserved_41 = 41,
+ TC_TP_STARVED_QUAD0 = 42,
+ reserved_43 = 43,
+ reserved_44 = 44,
+ reserved_45 = 45,
+ TC_TP_STARVED = 46,
+} TCM_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H
+#define ENUMS_TCF_PERFCOUNT_SELECT_H
+typedef enum TCF_PERFCOUNT_SELECT {
+ VALID_CYCLES = 0,
+ SINGLE_PHASES = 1,
+ ANISO_PHASES = 2,
+ MIP_PHASES = 3,
+ VOL_PHASES = 4,
+ MIP_VOL_PHASES = 5,
+ MIP_ANISO_PHASES = 6,
+ VOL_ANISO_PHASES = 7,
+ ANISO_2_1_PHASES = 8,
+ ANISO_4_1_PHASES = 9,
+ ANISO_6_1_PHASES = 10,
+ ANISO_8_1_PHASES = 11,
+ ANISO_10_1_PHASES = 12,
+ ANISO_12_1_PHASES = 13,
+ ANISO_14_1_PHASES = 14,
+ ANISO_16_1_PHASES = 15,
+ MIP_VOL_ANISO_PHASES = 16,
+ ALIGN_2_PHASES = 17,
+ ALIGN_4_PHASES = 18,
+ TPC_BUSY = 19,
+ TPC_STALLED = 20,
+ TPC_STARVED = 21,
+ TPC_WORKING = 22,
+ TPC_WALKER_BUSY = 23,
+ TPC_WALKER_STALLED = 24,
+ TPC_WALKER_WORKING = 25,
+ TPC_ALIGNER_BUSY = 26,
+ TPC_ALIGNER_STALLED = 27,
+ TPC_ALIGNER_STALLED_BY_BLEND = 28,
+ TPC_ALIGNER_STALLED_BY_CACHE = 29,
+ TPC_ALIGNER_WORKING = 30,
+ TPC_BLEND_BUSY = 31,
+ TPC_BLEND_SYNC = 32,
+ TPC_BLEND_STARVED = 33,
+ TPC_BLEND_WORKING = 34,
+ OPCODE_0x00 = 35,
+ OPCODE_0x01 = 36,
+ OPCODE_0x04 = 37,
+ OPCODE_0x10 = 38,
+ OPCODE_0x11 = 39,
+ OPCODE_0x12 = 40,
+ OPCODE_0x13 = 41,
+ OPCODE_0x18 = 42,
+ OPCODE_0x19 = 43,
+ OPCODE_0x1A = 44,
+ OPCODE_OTHER = 45,
+ IN_FIFO_0_EMPTY = 56,
+ IN_FIFO_0_LT_HALF_FULL = 57,
+ IN_FIFO_0_HALF_FULL = 58,
+ IN_FIFO_0_FULL = 59,
+ IN_FIFO_TPC_EMPTY = 72,
+ IN_FIFO_TPC_LT_HALF_FULL = 73,
+ IN_FIFO_TPC_HALF_FULL = 74,
+ IN_FIFO_TPC_FULL = 75,
+ TPC_TC_XFC = 76,
+ TPC_TC_STATE = 77,
+ TC_STALL = 78,
+ QUAD0_TAPS = 79,
+ QUADS = 83,
+ TCA_SYNC_STALL = 84,
+ TAG_STALL = 85,
+ TCB_SYNC_STALL = 88,
+ TCA_VALID = 89,
+ PROBES_VALID = 90,
+ MISS_STALL = 91,
+ FETCH_FIFO_STALL = 92,
+ TCO_STALL = 93,
+ ANY_STALL = 94,
+ TAG_MISSES = 95,
+ TAG_HITS = 96,
+ SUB_TAG_MISSES = 97,
+ SET0_INVALIDATES = 98,
+ SET1_INVALIDATES = 99,
+ SET2_INVALIDATES = 100,
+ SET3_INVALIDATES = 101,
+ SET0_TAG_MISSES = 102,
+ SET1_TAG_MISSES = 103,
+ SET2_TAG_MISSES = 104,
+ SET3_TAG_MISSES = 105,
+ SET0_TAG_HITS = 106,
+ SET1_TAG_HITS = 107,
+ SET2_TAG_HITS = 108,
+ SET3_TAG_HITS = 109,
+ SET0_SUB_TAG_MISSES = 110,
+ SET1_SUB_TAG_MISSES = 111,
+ SET2_SUB_TAG_MISSES = 112,
+ SET3_SUB_TAG_MISSES = 113,
+ SET0_EVICT1 = 114,
+ SET0_EVICT2 = 115,
+ SET0_EVICT3 = 116,
+ SET0_EVICT4 = 117,
+ SET0_EVICT5 = 118,
+ SET0_EVICT6 = 119,
+ SET0_EVICT7 = 120,
+ SET0_EVICT8 = 121,
+ SET1_EVICT1 = 130,
+ SET1_EVICT2 = 131,
+ SET1_EVICT3 = 132,
+ SET1_EVICT4 = 133,
+ SET1_EVICT5 = 134,
+ SET1_EVICT6 = 135,
+ SET1_EVICT7 = 136,
+ SET1_EVICT8 = 137,
+ SET2_EVICT1 = 146,
+ SET2_EVICT2 = 147,
+ SET2_EVICT3 = 148,
+ SET2_EVICT4 = 149,
+ SET2_EVICT5 = 150,
+ SET2_EVICT6 = 151,
+ SET2_EVICT7 = 152,
+ SET2_EVICT8 = 153,
+ SET3_EVICT1 = 162,
+ SET3_EVICT2 = 163,
+ SET3_EVICT3 = 164,
+ SET3_EVICT4 = 165,
+ SET3_EVICT5 = 166,
+ SET3_EVICT6 = 167,
+ SET3_EVICT7 = 168,
+ SET3_EVICT8 = 169,
+ FF_EMPTY = 178,
+ FF_LT_HALF_FULL = 179,
+ FF_HALF_FULL = 180,
+ FF_FULL = 181,
+ FF_XFC = 182,
+ FF_STALLED = 183,
+ FG_MASKS = 184,
+ FG_LEFT_MASKS = 185,
+ FG_LEFT_MASK_STALLED = 186,
+ FG_LEFT_NOT_DONE_STALL = 187,
+ FG_LEFT_FG_STALL = 188,
+ FG_LEFT_SECTORS = 189,
+ FG0_REQUESTS = 195,
+ FG0_STALLED = 196,
+ MEM_REQ512 = 199,
+ MEM_REQ_SENT = 200,
+ MEM_LOCAL_READ_REQ = 202,
+ TC0_MH_STALLED = 203,
+} TCF_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+#ifndef ENUMS_SQ_PERFCNT_SELECT_H
+#define ENUMS_SQ_PERFCNT_SELECT_H
+typedef enum SQ_PERFCNT_SELECT {
+ SQ_PIXEL_VECTORS_SUB = 0,
+ SQ_VERTEX_VECTORS_SUB = 1,
+ SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
+ SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
+ SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
+ SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
+ SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
+ SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
+ SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
+ SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
+ SQ_EXPORT_CYCLES = 10,
+ SQ_ALU_CST_WRITTEN = 11,
+ SQ_TEX_CST_WRITTEN = 12,
+ SQ_ALU_CST_STALL = 13,
+ SQ_ALU_TEX_STALL = 14,
+ SQ_INST_WRITTEN = 15,
+ SQ_BOOLEAN_WRITTEN = 16,
+ SQ_LOOPS_WRITTEN = 17,
+ SQ_PIXEL_SWAP_IN = 18,
+ SQ_PIXEL_SWAP_OUT = 19,
+ SQ_VERTEX_SWAP_IN = 20,
+ SQ_VERTEX_SWAP_OUT = 21,
+ SQ_ALU_VTX_INST_ISSUED = 22,
+ SQ_TEX_VTX_INST_ISSUED = 23,
+ SQ_VC_VTX_INST_ISSUED = 24,
+ SQ_CF_VTX_INST_ISSUED = 25,
+ SQ_ALU_PIX_INST_ISSUED = 26,
+ SQ_TEX_PIX_INST_ISSUED = 27,
+ SQ_VC_PIX_INST_ISSUED = 28,
+ SQ_CF_PIX_INST_ISSUED = 29,
+ SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
+ SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
+ SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
+ SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
+ SQ_ALU_NOPS = 34,
+ SQ_PRED_SKIP = 35,
+ SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
+ SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
+ SQ_SYNC_TEX_STALL_VTX = 38,
+ SQ_SYNC_VC_STALL_VTX = 39,
+ SQ_CONSTANTS_USED_SIMD0 = 40,
+ SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
+ SQ_GPR_STALL_VTX = 42,
+ SQ_GPR_STALL_PIX = 43,
+ SQ_VTX_RS_STALL = 44,
+ SQ_PIX_RS_STALL = 45,
+ SQ_SX_PC_FULL   = 46,
+ SQ_SX_EXP_BUFF_FULL = 47,
+ SQ_SX_POS_BUFF_FULL = 48,
+ SQ_INTERP_QUADS = 49,
+ SQ_INTERP_ACTIVE = 50,
+ SQ_IN_PIXEL_STALL = 51,
+ SQ_IN_VTX_STALL = 52,
+ SQ_VTX_CNT = 53,
+ SQ_VTX_VECTOR2 = 54,
+ SQ_VTX_VECTOR3 = 55,
+ SQ_VTX_VECTOR4 = 56,
+ SQ_PIXEL_VECTOR1 = 57,
+ SQ_PIXEL_VECTOR23 = 58,
+ SQ_PIXEL_VECTOR4 = 59,
+ SQ_CONSTANTS_USED_SIMD1 = 60,
+ SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
+ SQ_SX_MEM_EXP_FULL = 62,
+ SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
+ SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
+ SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
+ SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
+ SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
+ SQ_ALU1_ACTIVE_VTX_SIMD3 = 68,
+ SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
+ SQ_ALU1_ACTIVE_PIX_SIMD3 = 70,
+ SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
+ SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
+ SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
+ SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
+ SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
+ SQ_SYNC_ALU_STALL_SIMD3_VTX = 76,
+ SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
+ SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
+ SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
+ SQ_SYNC_ALU_STALL_SIMD3_PIX = 80,
+ SQ_SYNC_TEX_STALL_PIX = 81,
+ SQ_SYNC_VC_STALL_PIX = 82,
+ SQ_CONSTANTS_USED_SIMD2 = 83,
+ SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
+ SQ_CONSTANTS_USED_SIMD3 = 85,
+ SQ_CONSTANTS_SENT_SP_SIMD3 = 86,
+ SQ_ALU0_FIFO_FULL_SIMD0 = 87,
+ SQ_ALU1_FIFO_FULL_SIMD0 = 88,
+ SQ_ALU0_FIFO_FULL_SIMD1 = 89,
+ SQ_ALU1_FIFO_FULL_SIMD1 = 90,
+ SQ_ALU0_FIFO_FULL_SIMD2 = 91,
+ SQ_ALU1_FIFO_FULL_SIMD2 = 92,
+ SQ_ALU0_FIFO_FULL_SIMD3 = 93,
+ SQ_ALU1_FIFO_FULL_SIMD3 = 94,
+ VC_PERF_STATIC = 95,
+ VC_PERF_STALLED = 96,
+ VC_PERF_STARVED = 97,
+ VC_PERF_SEND = 98,
+ VC_PERF_ACTUAL_STARVED = 99,
+ PIXEL_THREAD_0_ACTIVE   = 100,
+ VERTEX_THREAD_0_ACTIVE  = 101,
+ PIXEL_THREAD_0_NUMBER   = 102,
+ VERTEX_THREAD_0_NUMBER  = 103,
+ VERTEX_EVENT_NUMBER     = 104,
+ PIXEL_EVENT_NUMBER  = 105,
+ PTRBUFF_EF_PUSH = 106,
+ PTRBUFF_EF_POP_EVENT = 107,
+ PTRBUFF_EF_POP_NEW_VTX = 108,
+ PTRBUFF_EF_POP_DEALLOC = 109,
+ PTRBUFF_EF_POP_PVECTOR = 110,
+ PTRBUFF_EF_POP_PVECTOR_X = 111,
+ PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
+ PTRBUFF_PB_DEALLOC = 113,
+ PTRBUFF_PI_STATE_PPB_POP = 114,
+ PTRBUFF_PI_RTR = 115,
+ PTRBUFF_PI_READ_EN = 116,
+ PTRBUFF_PI_BUFF_SWAP = 117,
+ PTRBUFF_SQ_FREE_BUFF = 118,
+ PTRBUFF_SQ_DEC = 119,
+ PTRBUFF_SC_VALID_CNTL_EVENT = 120,
+ PTRBUFF_SC_VALID_IJ_XFER = 121,
+ PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
+ PTRBUFF_QUAL_NEW_VECTOR = 123,
+ PTRBUFF_QUAL_EVENT = 124,
+ PTRBUFF_END_BUFFER = 125,
+ PTRBUFF_FILL_QUAD = 126,
+ VERTS_WRITTEN_SPI = 127,
+ TP_FETCH_INSTR_EXEC = 128,
+ TP_FETCH_INSTR_REQ = 129,
+ TP_DATA_RETURN = 130,
+ SPI_WRITE_CYCLES_SP = 131,
+ SPI_WRITES_SP = 132,
+ SP_ALU_INSTR_EXEC = 133,
+ SP_CONST_ADDR_TO_SQ = 134,
+ SP_PRED_KILLS_TO_SQ = 135,
+ SP_EXPORT_CYCLES_TO_SX = 136,
+ SP_EXPORTS_TO_SX = 137,
+ SQ_CYCLES_ELAPSED = 138,
+ SQ_TCFS_OPT_ALLOC_EXEC = 139,
+ SQ_TCFS_NO_OPT_ALLOC = 140,
+ SQ_ALU0_NO_OPT_ALLOC = 141,
+ SQ_ALU1_NO_OPT_ALLOC = 142,
+ SQ_TCFS_ARB_XFC_CNT = 143,
+ SQ_ALU0_ARB_XFC_CNT = 144,
+ SQ_ALU1_ARB_XFC_CNT = 145,
+ SQ_TCFS_CFS_UPDATE_CNT = 146,
+ SQ_ALU0_CFS_UPDATE_CNT = 147,
+ SQ_ALU1_CFS_UPDATE_CNT = 148,
+ SQ_VTX_PUSH_THREAD_CNT = 149,
+ SQ_VTX_POP_THREAD_CNT = 150,
+ SQ_PIX_PUSH_THREAD_CNT = 151,
+ SQ_PIX_POP_THREAD_CNT = 152,
+ SQ_PIX_TOTAL = 153,
+ SQ_PIX_KILLED = 154,
+} SQ_PERFCNT_SELECT;
+#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SX_PERFCNT_SELECT_H
+#define ENUMS_SX_PERFCNT_SELECT_H
+typedef enum SX_PERFCNT_SELECT {
+ SX_EXPORT_VECTORS = 0,
+ SX_DUMMY_QUADS  = 1,
+ SX_ALPHA_FAIL = 2,
+ SX_RB_QUAD_BUSY = 3,
+ SX_RB_COLOR_BUSY = 4,
+ SX_RB_QUAD_STALL = 5,
+ SX_RB_COLOR_STALL = 6,
+} SX_PERFCNT_SELECT;
+#endif /*ENUMS_SX_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_Abs_modifier_H
+#define ENUMS_Abs_modifier_H
+typedef enum Abs_modifier {
+ NO_ABS_MOD = 0,
+ ABS_MOD = 1
+} Abs_modifier;
+#endif /*ENUMS_Abs_modifier_H*/
+
+#ifndef ENUMS_Exporting_H
+#define ENUMS_Exporting_H
+typedef enum Exporting {
+ NOT_EXPORTING = 0,
+ EXPORTING = 1
+} Exporting;
+#endif /*ENUMS_Exporting_H*/
+
+#ifndef ENUMS_ScalarOpcode_H
+#define ENUMS_ScalarOpcode_H
+typedef enum ScalarOpcode {
+ ADDs = 0,
+ ADD_PREVs = 1,
+ MULs = 2,
+ MUL_PREVs = 3,
+ MUL_PREV2s = 4,
+ MAXs = 5,
+ MINs = 6,
+ SETEs = 7,
+ SETGTs = 8,
+ SETGTEs = 9,
+ SETNEs = 10,
+ FRACs = 11,
+ TRUNCs = 12,
+ FLOORs = 13,
+ EXP_IEEE = 14,
+ LOG_CLAMP = 15,
+ LOG_IEEE = 16,
+ RECIP_CLAMP = 17,
+ RECIP_FF = 18,
+ RECIP_IEEE = 19,
+ RECIPSQ_CLAMP = 20,
+ RECIPSQ_FF = 21,
+ RECIPSQ_IEEE = 22,
+ MOVAs = 23,
+ MOVA_FLOORs = 24,
+ SUBs = 25,
+ SUB_PREVs = 26,
+ PRED_SETEs = 27,
+ PRED_SETNEs = 28,
+ PRED_SETGTs = 29,
+ PRED_SETGTEs = 30,
+ PRED_SET_INVs = 31,
+ PRED_SET_POPs = 32,
+ PRED_SET_CLRs = 33,
+ PRED_SET_RESTOREs = 34,
+ KILLEs = 35,
+ KILLGTs = 36,
+ KILLGTEs = 37,
+ KILLNEs = 38,
+ KILLONEs = 39,
+ SQRT_IEEE = 40,
+ MUL_CONST_0 = 42,
+ MUL_CONST_1 = 43,
+ ADD_CONST_0 = 44,
+ ADD_CONST_1 = 45,
+ SUB_CONST_0 = 46,
+ SUB_CONST_1 = 47,
+ SIN = 48,
+ COS = 49,
+ RETAIN_PREV = 50,
+} ScalarOpcode;
+#endif /*ENUMS_ScalarOpcode_H*/
+
+#ifndef ENUMS_SwizzleType_H
+#define ENUMS_SwizzleType_H
+typedef enum SwizzleType {
+ NO_SWIZZLE = 0,
+ SHIFT_RIGHT_1 = 1,
+ SHIFT_RIGHT_2 = 2,
+ SHIFT_RIGHT_3 = 3
+} SwizzleType;
+#endif /*ENUMS_SwizzleType_H*/
+
+#ifndef ENUMS_InputModifier_H
+#define ENUMS_InputModifier_H
+typedef enum InputModifier {
+ NIL = 0,
+ NEGATE = 1
+} InputModifier;
+#endif /*ENUMS_InputModifier_H*/
+
+#ifndef ENUMS_PredicateSelect_H
+#define ENUMS_PredicateSelect_H
+typedef enum PredicateSelect {
+ NO_PREDICATION = 0,
+ PREDICATE_QUAD = 1,
+ PREDICATED_2 = 2,
+ PREDICATED_3 = 3
+} PredicateSelect;
+#endif /*ENUMS_PredicateSelect_H*/
+
+#ifndef ENUMS_OperandSelect1_H
+#define ENUMS_OperandSelect1_H
+typedef enum OperandSelect1 {
+ ABSOLUTE_REG = 0,
+ RELATIVE_REG = 1
+} OperandSelect1;
+#endif /*ENUMS_OperandSelect1_H*/
+
+#ifndef ENUMS_VectorOpcode_H
+#define ENUMS_VectorOpcode_H
+typedef enum VectorOpcode {
+ ADDv = 0,
+ MULv = 1,
+ MAXv = 2,
+ MINv = 3,
+ SETEv = 4,
+ SETGTv = 5,
+ SETGTEv = 6,
+ SETNEv = 7,
+ FRACv = 8,
+ TRUNCv = 9,
+ FLOORv = 10,
+ MULADDv = 11,
+ CNDEv = 12,
+ CNDGTEv = 13,
+ CNDGTv = 14,
+ DOT4v = 15,
+ DOT3v = 16,
+ DOT2ADDv = 17,
+ CUBEv = 18,
+ MAX4v = 19,
+ PRED_SETE_PUSHv = 20,
+ PRED_SETNE_PUSHv = 21,
+ PRED_SETGT_PUSHv = 22,
+ PRED_SETGTE_PUSHv = 23,
+ KILLEv = 24,
+ KILLGTv = 25,
+ KILLGTEv = 26,
+ KILLNEv = 27,
+ DSTv = 28,
+ MOVAv = 29,
+} VectorOpcode;
+#endif /*ENUMS_VectorOpcode_H*/
+
+#ifndef ENUMS_OperandSelect0_H
+#define ENUMS_OperandSelect0_H
+typedef enum OperandSelect0 {
+ CONSTANT = 0,
+ NON_CONSTANT = 1
+} OperandSelect0;
+#endif /*ENUMS_OperandSelect0_H*/
+
+#ifndef ENUMS_Ressource_type_H
+#define ENUMS_Ressource_type_H
+typedef enum Ressource_type {
+ ALU = 0,
+ TEXTURE = 1
+} Ressource_type;
+#endif /*ENUMS_Ressource_type_H*/
+
+#ifndef ENUMS_Instruction_serial_H
+#define ENUMS_Instruction_serial_H
+typedef enum Instruction_serial {
+ NOT_SERIAL = 0,
+ SERIAL = 1
+} Instruction_serial;
+#endif /*ENUMS_Instruction_serial_H*/
+
+#ifndef ENUMS_VC_type_H
+#define ENUMS_VC_type_H
+typedef enum VC_type {
+ ALU_TP_REQUEST = 0,
+ VC_REQUEST = 1
+} VC_type;
+#endif /*ENUMS_VC_type_H*/
+
+#ifndef ENUMS_Addressing_H
+#define ENUMS_Addressing_H
+typedef enum Addressing {
+ RELATIVE_ADDR = 0,
+ ABSOLUTE_ADDR = 1
+} Addressing;
+#endif /*ENUMS_Addressing_H*/
+
+#ifndef ENUMS_CFOpcode_H
+#define ENUMS_CFOpcode_H
+typedef enum CFOpcode {
+ NOP = 0,
+ EXECUTE = 1,
+ EXECUTE_END = 2,
+ COND_EXECUTE = 3,
+ COND_EXECUTE_END = 4,
+ COND_PRED_EXECUTE = 5,
+ COND_PRED_EXECUTE_END = 6,
+ LOOP_START = 7,
+ LOOP_END = 8,
+ COND_CALL = 9,
+ RETURN = 10,
+ COND_JMP = 11,
+ ALLOCATE = 12,
+ COND_EXECUTE_PRED_CLEAN = 13,
+ COND_EXECUTE_PRED_CLEAN_END = 14,
+ MARK_VS_FETCH_DONE = 15
+} CFOpcode;
+#endif /*ENUMS_CFOpcode_H*/
+
+#ifndef ENUMS_Allocation_type_H
+#define ENUMS_Allocation_type_H
+typedef enum Allocation_type {
+ SQ_NO_ALLOC = 0,
+ SQ_POSITION = 1,
+ SQ_PARAMETER_PIXEL = 2,
+ SQ_MEMORY = 3
+} Allocation_type;
+#endif /*ENUMS_Allocation_type_H*/
+
+#ifndef ENUMS_TexInstOpcode_H
+#define ENUMS_TexInstOpcode_H
+typedef enum TexInstOpcode {
+ TEX_INST_FETCH = 1,
+ TEX_INST_RESERVED_1 = 2,
+ TEX_INST_RESERVED_2 = 3,
+ TEX_INST_RESERVED_3 = 4,
+ TEX_INST_GET_BORDER_COLOR_FRAC = 16,
+ TEX_INST_GET_COMP_TEX_LOD = 17,
+ TEX_INST_GET_GRADIENTS = 18,
+ TEX_INST_GET_WEIGHTS = 19,
+ TEX_INST_SET_TEX_LOD = 24,
+ TEX_INST_SET_GRADIENTS_H = 25,
+ TEX_INST_SET_GRADIENTS_V = 26,
+ TEX_INST_RESERVED_4 = 27,
+} TexInstOpcode;
+#endif /*ENUMS_TexInstOpcode_H*/
+
+#ifndef ENUMS_Addressmode_H
+#define ENUMS_Addressmode_H
+typedef enum Addressmode {
+ LOGICAL = 0,
+ LOOP_RELATIVE = 1
+} Addressmode;
+#endif /*ENUMS_Addressmode_H*/
+
+#ifndef ENUMS_TexCoordDenorm_H
+#define ENUMS_TexCoordDenorm_H
+typedef enum TexCoordDenorm {
+ TEX_COORD_NORMALIZED = 0,
+ TEX_COORD_UNNORMALIZED = 1
+} TexCoordDenorm;
+#endif /*ENUMS_TexCoordDenorm_H*/
+
+#ifndef ENUMS_SrcSel_H
+#define ENUMS_SrcSel_H
+typedef enum SrcSel {
+ SRC_SEL_X = 0,
+ SRC_SEL_Y = 1,
+ SRC_SEL_Z = 2,
+ SRC_SEL_W = 3
+} SrcSel;
+#endif /*ENUMS_SrcSel_H*/
+
+#ifndef ENUMS_DstSel_H
+#define ENUMS_DstSel_H
+typedef enum DstSel {
+ DST_SEL_X = 0,
+ DST_SEL_Y = 1,
+ DST_SEL_Z = 2,
+ DST_SEL_W = 3,
+ DST_SEL_0 = 4,
+ DST_SEL_1 = 5,
+ DST_SEL_RSVD = 6,
+ DST_SEL_MASK = 7
+} DstSel;
+#endif /*ENUMS_DstSel_H*/
+
+#ifndef ENUMS_MagFilter_H
+#define ENUMS_MagFilter_H
+typedef enum MagFilter {
+ MAG_FILTER_POINT = 0,
+ MAG_FILTER_LINEAR = 1,
+ MAG_FILTER_RESERVED_0 = 2,
+ MAG_FILTER_USE_FETCH_CONST = 3
+} MagFilter;
+#endif /*ENUMS_MagFilter_H*/
+
+#ifndef ENUMS_MinFilter_H
+#define ENUMS_MinFilter_H
+typedef enum MinFilter {
+ MIN_FILTER_POINT = 0,
+ MIN_FILTER_LINEAR = 1,
+ MIN_FILTER_RESERVED_0 = 2,
+ MIN_FILTER_USE_FETCH_CONST = 3
+} MinFilter;
+#endif /*ENUMS_MinFilter_H*/
+
+#ifndef ENUMS_MipFilter_H
+#define ENUMS_MipFilter_H
+typedef enum MipFilter {
+ MIP_FILTER_POINT = 0,
+ MIP_FILTER_LINEAR = 1,
+ MIP_FILTER_BASEMAP = 2,
+ MIP_FILTER_USE_FETCH_CONST = 3
+} MipFilter;
+#endif /*ENUMS_MipFilter_H*/
+
+#ifndef ENUMS_AnisoFilter_H
+#define ENUMS_AnisoFilter_H
+typedef enum AnisoFilter {
+ ANISO_FILTER_DISABLED = 0,
+ ANISO_FILTER_MAX_1_1 = 1,
+ ANISO_FILTER_MAX_2_1 = 2,
+ ANISO_FILTER_MAX_4_1 = 3,
+ ANISO_FILTER_MAX_8_1 = 4,
+ ANISO_FILTER_MAX_16_1 = 5,
+ ANISO_FILTER_USE_FETCH_CONST = 7
+} AnisoFilter;
+#endif /*ENUMS_AnisoFilter_H*/
+
+#ifndef ENUMS_ArbitraryFilter_H
+#define ENUMS_ArbitraryFilter_H
+typedef enum ArbitraryFilter {
+ ARBITRARY_FILTER_2X4_SYM = 0,
+ ARBITRARY_FILTER_2X4_ASYM = 1,
+ ARBITRARY_FILTER_4X2_SYM = 2,
+ ARBITRARY_FILTER_4X2_ASYM = 3,
+ ARBITRARY_FILTER_4X4_SYM = 4,
+ ARBITRARY_FILTER_4X4_ASYM = 5,
+ ARBITRARY_FILTER_USE_FETCH_CONST = 7
+} ArbitraryFilter;
+#endif /*ENUMS_ArbitraryFilter_H*/
+
+#ifndef ENUMS_VolMagFilter_H
+#define ENUMS_VolMagFilter_H
+typedef enum VolMagFilter {
+ VOL_MAG_FILTER_POINT = 0,
+ VOL_MAG_FILTER_LINEAR = 1,
+ VOL_MAG_FILTER_USE_FETCH_CONST = 3
+} VolMagFilter;
+#endif /*ENUMS_VolMagFilter_H*/
+
+#ifndef ENUMS_VolMinFilter_H
+#define ENUMS_VolMinFilter_H
+typedef enum VolMinFilter {
+ VOL_MIN_FILTER_POINT = 0,
+ VOL_MIN_FILTER_LINEAR = 1,
+ VOL_MIN_FILTER_USE_FETCH_CONST = 3
+} VolMinFilter;
+#endif /*ENUMS_VolMinFilter_H*/
+
+#ifndef ENUMS_PredSelect_H
+#define ENUMS_PredSelect_H
+typedef enum PredSelect {
+ NOT_PREDICATED = 0,
+ PREDICATED = 1
+} PredSelect;
+#endif /*ENUMS_PredSelect_H*/
+
+#ifndef ENUMS_SampleLocation_H
+#define ENUMS_SampleLocation_H
+typedef enum SampleLocation {
+ SAMPLE_CENTROID = 0,
+ SAMPLE_CENTER = 1
+} SampleLocation;
+#endif /*ENUMS_SampleLocation_H*/
+
+#ifndef ENUMS_VertexMode_H
+#define ENUMS_VertexMode_H
+typedef enum VertexMode {
+ POSITION_1_VECTOR = 0,
+ POSITION_2_VECTORS_UNUSED = 1,
+ POSITION_2_VECTORS_SPRITE = 2,
+ POSITION_2_VECTORS_EDGE = 3,
+ POSITION_2_VECTORS_KILL = 4,
+ POSITION_2_VECTORS_SPRITE_KILL = 5,
+ POSITION_2_VECTORS_EDGE_KILL = 6,
+ MULTIPASS = 7
+} VertexMode;
+#endif /*ENUMS_VertexMode_H*/
+
+#ifndef ENUMS_Sample_Cntl_H
+#define ENUMS_Sample_Cntl_H
+typedef enum Sample_Cntl {
+ CENTROIDS_ONLY = 0,
+ CENTERS_ONLY = 1,
+ CENTROIDS_AND_CENTERS = 2,
+ UNDEF = 3
+} Sample_Cntl;
+#endif /*ENUMS_Sample_Cntl_H*/
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+#ifndef ENUMS_MhPerfEncode_H
+#define ENUMS_MhPerfEncode_H
+typedef enum MhPerfEncode {
+ CP_R0_REQUESTS = 0,
+ CP_R1_REQUESTS = 1,
+ CP_R2_REQUESTS = 2,
+ CP_R3_REQUESTS = 3,
+ CP_R4_REQUESTS = 4,
+ CP_TOTAL_READ_REQUESTS = 5,
+ CP_W_REQUESTS = 6,
+ CP_TOTAL_REQUESTS = 7,
+ CP_DATA_BYTES_WRITTEN = 8,
+ CP_WRITE_CLEAN_RESPONSES = 9,
+ CP_R0_READ_BURSTS_RECEIVED = 10,
+ CP_R1_READ_BURSTS_RECEIVED = 11,
+ CP_R2_READ_BURSTS_RECEIVED = 12,
+ CP_R3_READ_BURSTS_RECEIVED = 13,
+ CP_R4_READ_BURSTS_RECEIVED = 14,
+ CP_TOTAL_READ_BURSTS_RECEIVED = 15,
+ CP_R0_DATA_BEATS_READ = 16,
+ CP_R1_DATA_BEATS_READ = 17,
+ CP_R2_DATA_BEATS_READ = 18,
+ CP_R3_DATA_BEATS_READ = 19,
+ CP_R4_DATA_BEATS_READ = 20,
+ CP_TOTAL_DATA_BEATS_READ = 21,
+ VGT_R0_REQUESTS = 22,
+ VGT_R1_REQUESTS = 23,
+ VGT_TOTAL_REQUESTS = 24,
+ VGT_R0_READ_BURSTS_RECEIVED = 25,
+ VGT_R1_READ_BURSTS_RECEIVED = 26,
+ VGT_TOTAL_READ_BURSTS_RECEIVED = 27,
+ VGT_R0_DATA_BEATS_READ = 28,
+ VGT_R1_DATA_BEATS_READ = 29,
+ VGT_TOTAL_DATA_BEATS_READ = 30,
+ TC_REQUESTS = 31,
+ TC_ROQ_REQUESTS = 32,
+ TC_INFO_SENT = 33,
+ TC_READ_BURSTS_RECEIVED = 34,
+ TC_DATA_BEATS_READ = 35,
+ TCD_BURSTS_READ = 36,
+ RB_REQUESTS = 37,
+ RB_DATA_BYTES_WRITTEN = 38,
+ RB_WRITE_CLEAN_RESPONSES = 39,
+ AXI_READ_REQUESTS_ID_0 = 40,
+ AXI_READ_REQUESTS_ID_1 = 41,
+ AXI_READ_REQUESTS_ID_2 = 42,
+ AXI_READ_REQUESTS_ID_3 = 43,
+ AXI_READ_REQUESTS_ID_4 = 44,
+ AXI_READ_REQUESTS_ID_5 = 45,
+ AXI_READ_REQUESTS_ID_6 = 46,
+ AXI_READ_REQUESTS_ID_7 = 47,
+ AXI_TOTAL_READ_REQUESTS = 48,
+ AXI_WRITE_REQUESTS_ID_0 = 49,
+ AXI_WRITE_REQUESTS_ID_1 = 50,
+ AXI_WRITE_REQUESTS_ID_2 = 51,
+ AXI_WRITE_REQUESTS_ID_3 = 52,
+ AXI_WRITE_REQUESTS_ID_4 = 53,
+ AXI_WRITE_REQUESTS_ID_5 = 54,
+ AXI_WRITE_REQUESTS_ID_6 = 55,
+ AXI_WRITE_REQUESTS_ID_7 = 56,
+ AXI_TOTAL_WRITE_REQUESTS = 57,
+ AXI_TOTAL_REQUESTS_ID_0 = 58,
+ AXI_TOTAL_REQUESTS_ID_1 = 59,
+ AXI_TOTAL_REQUESTS_ID_2 = 60,
+ AXI_TOTAL_REQUESTS_ID_3 = 61,
+ AXI_TOTAL_REQUESTS_ID_4 = 62,
+ AXI_TOTAL_REQUESTS_ID_5 = 63,
+ AXI_TOTAL_REQUESTS_ID_6 = 64,
+ AXI_TOTAL_REQUESTS_ID_7 = 65,
+ AXI_TOTAL_REQUESTS = 66,
+ AXI_READ_CHANNEL_BURSTS_ID_0 = 67,
+ AXI_READ_CHANNEL_BURSTS_ID_1 = 68,
+ AXI_READ_CHANNEL_BURSTS_ID_2 = 69,
+ AXI_READ_CHANNEL_BURSTS_ID_3 = 70,
+ AXI_READ_CHANNEL_BURSTS_ID_4 = 71,
+ AXI_READ_CHANNEL_BURSTS_ID_5 = 72,
+ AXI_READ_CHANNEL_BURSTS_ID_6 = 73,
+ AXI_READ_CHANNEL_BURSTS_ID_7 = 74,
+ AXI_READ_CHANNEL_TOTAL_BURSTS = 75,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83,
+ AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84,
+ AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85,
+ AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86,
+ AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87,
+ AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88,
+ AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89,
+ AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90,
+ AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91,
+ AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92,
+ AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101,
+ AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110,
+ AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111,
+ TOTAL_MMU_MISSES = 112,
+ MMU_READ_MISSES = 113,
+ MMU_WRITE_MISSES = 114,
+ TOTAL_MMU_HITS = 115,
+ MMU_READ_HITS = 116,
+ MMU_WRITE_HITS = 117,
+ SPLIT_MODE_TC_HITS = 118,
+ SPLIT_MODE_TC_MISSES = 119,
+ SPLIT_MODE_NON_TC_HITS = 120,
+ SPLIT_MODE_NON_TC_MISSES = 121,
+ STALL_AWAITING_TLB_MISS_FETCH = 122,
+ MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123,
+ MMU_TLB_MISS_DATA_BEATS_READ = 124,
+ CP_CYCLES_HELD_OFF = 125,
+ VGT_CYCLES_HELD_OFF = 126,
+ TC_CYCLES_HELD_OFF = 127,
+ TC_ROQ_CYCLES_HELD_OFF = 128,
+ TC_CYCLES_HELD_OFF_TCD_FULL = 129,
+ RB_CYCLES_HELD_OFF = 130,
+ TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131,
+ TLB_MISS_CYCLES_HELD_OFF = 132,
+ AXI_READ_REQUEST_HELD_OFF = 133,
+ AXI_WRITE_REQUEST_HELD_OFF = 134,
+ AXI_REQUEST_HELD_OFF = 135,
+ AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136,
+ AXI_WRITE_DATA_HELD_OFF = 137,
+ CP_SAME_PAGE_BANK_REQUESTS = 138,
+ VGT_SAME_PAGE_BANK_REQUESTS = 139,
+ TC_SAME_PAGE_BANK_REQUESTS = 140,
+ TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141,
+ RB_SAME_PAGE_BANK_REQUESTS = 142,
+ TOTAL_SAME_PAGE_BANK_REQUESTS = 143,
+ CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144,
+ VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145,
+ TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146,
+ RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147,
+ TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148,
+ TOTAL_MH_READ_REQUESTS = 149,
+ TOTAL_MH_WRITE_REQUESTS = 150,
+ TOTAL_MH_REQUESTS = 151,
+ MH_BUSY = 152,
+ CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153,
+ VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154,
+ TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155,
+ RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156,
+ TC_ROQ_N_VALID_ENTRIES = 157,
+ ARQ_N_ENTRIES = 158,
+ WDB_N_ENTRIES = 159,
+ MH_READ_LATENCY_OUTST_REQ_SUM = 160,
+ MC_READ_LATENCY_OUTST_REQ_SUM = 161,
+ MC_TOTAL_READ_REQUESTS = 162,
+ ELAPSED_CYCLES_MH_GATED_CLK = 163,
+} MhPerfEncode;
+#endif /*ENUMS_MhPerfEncode_H*/
+
+#ifndef ENUMS_MmuClntBeh_H
+#define ENUMS_MmuClntBeh_H
+typedef enum MmuClntBeh {
+ BEH_NEVR = 0,
+ BEH_TRAN_RNG = 1,
+ BEH_TRAN_FLT = 2,
+} MmuClntBeh;
+#endif /*ENUMS_MmuClntBeh_H*/
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H
+#define ENUMS_RBBM_PERFCOUNT1_SEL_H
+typedef enum RBBM_PERFCOUNT1_SEL {
+ RBBM1_COUNT = 0,
+ RBBM1_NRT_BUSY = 1,
+ RBBM1_RB_BUSY = 2,
+ RBBM1_SQ_CNTX0_BUSY = 3,
+ RBBM1_SQ_CNTX17_BUSY = 4,
+ RBBM1_VGT_BUSY = 5,
+ RBBM1_VGT_NODMA_BUSY = 6,
+ RBBM1_PA_BUSY = 7,
+ RBBM1_SC_CNTX_BUSY = 8,
+ RBBM1_TPC_BUSY = 9,
+ RBBM1_TC_BUSY = 10,
+ RBBM1_SX_BUSY = 11,
+ RBBM1_CP_COHER_BUSY = 12,
+ RBBM1_CP_NRT_BUSY = 13,
+ RBBM1_GFX_IDLE_STALL = 14,
+ RBBM1_INTERRUPT = 15,
+} RBBM_PERFCOUNT1_SEL;
+#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+#ifndef ENUMS_CP_PERFCOUNT_SEL_H
+#define ENUMS_CP_PERFCOUNT_SEL_H
+typedef enum CP_PERFCOUNT_SEL {
+ ALWAYS_COUNT = 0,
+ TRANS_FIFO_FULL = 1,
+ TRANS_FIFO_AF = 2,
+ RCIU_PFPTRANS_WAIT = 3,
+ Reserved_04 = 4,
+ Reserved_05 = 5,
+ RCIU_NRTTRANS_WAIT = 6,
+ Reserved_07 = 7,
+ CSF_NRT_READ_WAIT = 8,
+ CSF_I1_FIFO_FULL = 9,
+ CSF_I2_FIFO_FULL = 10,
+ CSF_ST_FIFO_FULL = 11,
+ Reserved_12 = 12,
+ CSF_RING_ROQ_FULL = 13,
+ CSF_I1_ROQ_FULL = 14,
+ CSF_I2_ROQ_FULL = 15,
+ CSF_ST_ROQ_FULL = 16,
+ Reserved_17 = 17,
+ MIU_TAG_MEM_FULL = 18,
+ MIU_WRITECLEAN = 19,
+ Reserved_20 = 20,
+ Reserved_21 = 21,
+ MIU_NRT_WRITE_STALLED = 22,
+ MIU_NRT_READ_STALLED = 23,
+ ME_WRITE_CONFIRM_FIFO_FULL = 24,
+ ME_VS_DEALLOC_FIFO_FULL = 25,
+ ME_PS_DEALLOC_FIFO_FULL = 26,
+ ME_REGS_VS_EVENT_FIFO_FULL = 27,
+ ME_REGS_PS_EVENT_FIFO_FULL = 28,
+ ME_REGS_CF_EVENT_FIFO_FULL = 29,
+ ME_MICRO_RB_STARVED = 30,
+ ME_MICRO_I1_STARVED = 31,
+ ME_MICRO_I2_STARVED = 32,
+ ME_MICRO_ST_STARVED = 33,
+ Reserved_34 = 34,
+ Reserved_35 = 35,
+ Reserved_36 = 36,
+ Reserved_37 = 37,
+ Reserved_38 = 38,
+ Reserved_39 = 39,
+ RCIU_RBBM_DWORD_SENT = 40,
+ ME_BUSY_CLOCKS = 41,
+ ME_WAIT_CONTEXT_AVAIL = 42,
+ PFP_TYPE0_PACKET = 43,
+ PFP_TYPE3_PACKET = 44,
+ CSF_RB_WPTR_NEQ_RPTR = 45,
+ CSF_I1_SIZE_NEQ_ZERO = 46,
+ CSF_I2_SIZE_NEQ_ZERO = 47,
+ CSF_RBI1I2_FETCHING = 48,
+ Reserved_49 = 49,
+ Reserved_50 = 50,
+ Reserved_51 = 51,
+ Reserved_52 = 52,
+ Reserved_53 = 53,
+ Reserved_54 = 54,
+ Reserved_55 = 55,
+ Reserved_56 = 56,
+ Reserved_57 = 57,
+ Reserved_58 = 58,
+ Reserved_59 = 59,
+ Reserved_60 = 60,
+ Reserved_61 = 61,
+ Reserved_62 = 62,
+ Reserved_63 = 63
+} CP_PERFCOUNT_SEL;
+#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+#ifndef ENUMS_ColorformatX_H
+#define ENUMS_ColorformatX_H
+typedef enum ColorformatX {
+ COLORX_4_4_4_4 = 0,
+ COLORX_1_5_5_5 = 1,
+ COLORX_5_6_5 = 2,
+ COLORX_8 = 3,
+ COLORX_8_8 = 4,
+ COLORX_8_8_8_8 = 5,
+ COLORX_S8_8_8_8 = 6,
+ COLORX_16_FLOAT = 7,
+ COLORX_16_16_FLOAT = 8,
+ COLORX_16_16_16_16_FLOAT = 9,
+ COLORX_32_FLOAT = 10,
+ COLORX_32_32_FLOAT = 11,
+ COLORX_32_32_32_32_FLOAT = 12,
+ COLORX_2_3_3 = 13,
+ COLORX_8_8_8 = 14,
+} ColorformatX;
+#endif /*ENUMS_ColorformatX_H*/
+
+#ifndef ENUMS_DepthformatX_H
+#define ENUMS_DepthformatX_H
+typedef enum DepthformatX {
+ DEPTHX_16 = 0,
+ DEPTHX_24_8 = 1
+} DepthformatX;
+#endif /*ENUMS_DepthformatX_H*/
+
+#ifndef ENUMS_CompareFrag_H
+#define ENUMS_CompareFrag_H
+typedef enum CompareFrag {
+ FRAG_NEVER = 0,
+ FRAG_LESS = 1,
+ FRAG_EQUAL = 2,
+ FRAG_LEQUAL = 3,
+ FRAG_GREATER = 4,
+ FRAG_NOTEQUAL = 5,
+ FRAG_GEQUAL = 6,
+ FRAG_ALWAYS = 7
+} CompareFrag;
+#endif /*ENUMS_CompareFrag_H*/
+
+#ifndef ENUMS_CompareRef_H
+#define ENUMS_CompareRef_H
+typedef enum CompareRef {
+ REF_NEVER = 0,
+ REF_LESS = 1,
+ REF_EQUAL = 2,
+ REF_LEQUAL = 3,
+ REF_GREATER = 4,
+ REF_NOTEQUAL = 5,
+ REF_GEQUAL = 6,
+ REF_ALWAYS = 7
+} CompareRef;
+#endif /*ENUMS_CompareRef_H*/
+
+#ifndef ENUMS_StencilOp_H
+#define ENUMS_StencilOp_H
+typedef enum StencilOp {
+ STENCIL_KEEP = 0,
+ STENCIL_ZERO = 1,
+ STENCIL_REPLACE = 2,
+ STENCIL_INCR_CLAMP = 3,
+ STENCIL_DECR_CLAMP = 4,
+ STENCIL_INVERT = 5,
+ STENCIL_INCR_WRAP = 6,
+ STENCIL_DECR_WRAP = 7
+} StencilOp;
+#endif /*ENUMS_StencilOp_H*/
+
+#ifndef ENUMS_BlendOpX_H
+#define ENUMS_BlendOpX_H
+typedef enum BlendOpX {
+ BLENDX_ZERO = 0,
+ BLENDX_ONE = 1,
+ BLENDX_SRC_COLOR = 4,
+ BLENDX_ONE_MINUS_SRC_COLOR = 5,
+ BLENDX_SRC_ALPHA = 6,
+ BLENDX_ONE_MINUS_SRC_ALPHA = 7,
+ BLENDX_DST_COLOR = 8,
+ BLENDX_ONE_MINUS_DST_COLOR = 9,
+ BLENDX_DST_ALPHA = 10,
+ BLENDX_ONE_MINUS_DST_ALPHA = 11,
+ BLENDX_CONSTANT_COLOR = 12,
+ BLENDX_ONE_MINUS_CONSTANT_COLOR = 13,
+ BLENDX_CONSTANT_ALPHA = 14,
+ BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15,
+ BLENDX_SRC_ALPHA_SATURATE = 16,
+} BlendOpX;
+#endif /*ENUMS_BlendOpX_H*/
+
+#ifndef ENUMS_CombFuncX_H
+#define ENUMS_CombFuncX_H
+typedef enum CombFuncX {
+ COMB_DST_PLUS_SRC = 0,
+ COMB_SRC_MINUS_DST = 1,
+ COMB_MIN_DST_SRC = 2,
+ COMB_MAX_DST_SRC = 3,
+ COMB_DST_MINUS_SRC = 4,
+ COMB_DST_PLUS_SRC_BIAS = 5,
+} CombFuncX;
+#endif /*ENUMS_CombFuncX_H*/
+
+#ifndef ENUMS_DitherModeX_H
+#define ENUMS_DitherModeX_H
+typedef enum DitherModeX {
+ DITHER_DISABLE = 0,
+ DITHER_ALWAYS = 1,
+ DITHER_IF_ALPHA_OFF = 2,
+} DitherModeX;
+#endif /*ENUMS_DitherModeX_H*/
+
+#ifndef ENUMS_DitherTypeX_H
+#define ENUMS_DitherTypeX_H
+typedef enum DitherTypeX {
+ DITHER_PIXEL = 0,
+ DITHER_SUBPIXEL = 1,
+} DitherTypeX;
+#endif /*ENUMS_DitherTypeX_H*/
+
+#ifndef ENUMS_EdramMode_H
+#define ENUMS_EdramMode_H
+typedef enum EdramMode {
+ EDRAM_NOP = 0,
+ COLOR_DEPTH = 4,
+ DEPTH_ONLY = 5,
+ EDRAM_COPY = 6,
+} EdramMode;
+#endif /*ENUMS_EdramMode_H*/
+
+#ifndef ENUMS_SurfaceEndian_H
+#define ENUMS_SurfaceEndian_H
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0,
+ ENDIAN_8IN16 = 1,
+ ENDIAN_8IN32 = 2,
+ ENDIAN_16IN32 = 3,
+ ENDIAN_8IN64 = 4,
+ ENDIAN_8IN128 = 5,
+} SurfaceEndian;
+#endif /*ENUMS_SurfaceEndian_H*/
+
+#ifndef ENUMS_EdramSizeX_H
+#define ENUMS_EdramSizeX_H
+typedef enum EdramSizeX {
+ EDRAMSIZE_16KB = 0,
+ EDRAMSIZE_32KB = 1,
+ EDRAMSIZE_64KB = 2,
+ EDRAMSIZE_128KB = 3,
+ EDRAMSIZE_256KB = 4,
+ EDRAMSIZE_512KB = 5,
+ EDRAMSIZE_1MB = 6,
+ EDRAMSIZE_2MB = 7,
+ EDRAMSIZE_4MB = 8,
+ EDRAMSIZE_8MB = 9,
+ EDRAMSIZE_16MB = 10,
+} EdramSizeX;
+#endif /*ENUMS_EdramSizeX_H*/
+
+#ifndef ENUMS_RB_PERFCNT_SELECT_H
+#define ENUMS_RB_PERFCNT_SELECT_H
+typedef enum RB_PERFCNT_SELECT {
+ RBPERF_CNTX_BUSY = 0,
+ RBPERF_CNTX_BUSY_MAX = 1,
+ RBPERF_SX_QUAD_STARVED = 2,
+ RBPERF_SX_QUAD_STARVED_MAX = 3,
+ RBPERF_GA_GC_CH0_SYS_REQ = 4,
+ RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
+ RBPERF_GA_GC_CH1_SYS_REQ = 6,
+ RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
+ RBPERF_MH_STARVED = 8,
+ RBPERF_MH_STARVED_MAX = 9,
+ RBPERF_AZ_BC_COLOR_BUSY = 10,
+ RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
+ RBPERF_AZ_BC_Z_BUSY = 12,
+ RBPERF_AZ_BC_Z_BUSY_MAX = 13,
+ RBPERF_RB_SC_TILE_RTR_N = 14,
+ RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
+ RBPERF_RB_SC_SAMP_RTR_N = 16,
+ RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
+ RBPERF_RB_SX_QUAD_RTR_N = 18,
+ RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
+ RBPERF_RB_SX_COLOR_RTR_N = 20,
+ RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
+ RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
+ RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
+ RBPERF_ZXP_STALL = 24,
+ RBPERF_ZXP_STALL_MAX = 25,
+ RBPERF_EVENT_PENDING = 26,
+ RBPERF_EVENT_PENDING_MAX = 27,
+ RBPERF_RB_MH_VALID = 28,
+ RBPERF_RB_MH_VALID_MAX = 29,
+ RBPERF_SX_RB_QUAD_SEND = 30,
+ RBPERF_SX_RB_COLOR_SEND = 31,
+ RBPERF_SC_RB_TILE_SEND = 32,
+ RBPERF_SC_RB_SAMPLE_SEND = 33,
+ RBPERF_SX_RB_MEM_EXPORT = 34,
+ RBPERF_SX_RB_QUAD_EVENT = 35,
+ RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
+ RBPERF_SC_RB_TILE_EVENT_ALL = 37,
+ RBPERF_RB_SC_EZ_SEND = 38,
+ RBPERF_RB_SX_INDEX_SEND = 39,
+ RBPERF_GMEM_INTFO_RD = 40,
+ RBPERF_GMEM_INTF1_RD = 41,
+ RBPERF_GMEM_INTFO_WR = 42,
+ RBPERF_GMEM_INTF1_WR = 43,
+ RBPERF_RB_CP_CONTEXT_DONE = 44,
+ RBPERF_RB_CP_CACHE_FLUSH = 45,
+ RBPERF_ZPASS_DONE = 46,
+ RBPERF_ZCMD_VALID = 47,
+ RBPERF_CCMD_VALID = 48,
+ RBPERF_ACCUM_GRANT = 49,
+ RBPERF_ACCUM_C0_GRANT = 50,
+ RBPERF_ACCUM_C1_GRANT = 51,
+ RBPERF_ACCUM_FULL_BE_WR = 52,
+ RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
+ RBPERF_ACCUM_TIMEOUT_PULSE = 54,
+ RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
+ RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
+} RB_PERFCNT_SELECT;
+#endif /*ENUMS_RB_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_DepthFormat_H
+#define ENUMS_DepthFormat_H
+typedef enum DepthFormat {
+ DEPTH_24_8 = 22,
+ DEPTH_24_8_FLOAT = 23,
+ DEPTH_16 = 24,
+} DepthFormat;
+#endif /*ENUMS_DepthFormat_H*/
+
+#ifndef ENUMS_SurfaceSwap_H
+#define ENUMS_SurfaceSwap_H
+typedef enum SurfaceSwap {
+ SWAP_LOWRED = 0,
+ SWAP_LOWBLUE = 1
+} SurfaceSwap;
+#endif /*ENUMS_SurfaceSwap_H*/
+
+#ifndef ENUMS_DepthArray_H
+#define ENUMS_DepthArray_H
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0,
+ ARRAY_2D_DEPTH = 1,
+} DepthArray;
+#endif /*ENUMS_DepthArray_H*/
+
+#ifndef ENUMS_ColorArray_H
+#define ENUMS_ColorArray_H
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0,
+ ARRAY_2D_COLOR = 1,
+ ARRAY_3D_SLICE_COLOR = 3
+} ColorArray;
+#endif /*ENUMS_ColorArray_H*/
+
+#ifndef ENUMS_ColorFormat_H
+#define ENUMS_ColorFormat_H
+typedef enum ColorFormat {
+ COLOR_8 = 2,
+ COLOR_1_5_5_5 = 3,
+ COLOR_5_6_5 = 4,
+ COLOR_6_5_5 = 5,
+ COLOR_8_8_8_8 = 6,
+ COLOR_2_10_10_10 = 7,
+ COLOR_8_A = 8,
+ COLOR_8_B = 9,
+ COLOR_8_8 = 10,
+ COLOR_8_8_8 = 11,
+ COLOR_8_8_8_8_A = 14,
+ COLOR_4_4_4_4 = 15,
+ COLOR_10_11_11 = 16,
+ COLOR_11_11_10 = 17,
+ COLOR_16 = 24,
+ COLOR_16_16 = 25,
+ COLOR_16_16_16_16 = 26,
+ COLOR_16_FLOAT = 30,
+ COLOR_16_16_FLOAT = 31,
+ COLOR_16_16_16_16_FLOAT = 32,
+ COLOR_32_FLOAT = 36,
+ COLOR_32_32_FLOAT = 37,
+ COLOR_32_32_32_32_FLOAT = 38,
+ COLOR_2_3_3 = 39,
+} ColorFormat;
+#endif /*ENUMS_ColorFormat_H*/
+
+#ifndef ENUMS_SurfaceNumber_H
+#define ENUMS_SurfaceNumber_H
+typedef enum SurfaceNumber {
+ NUMBER_UREPEAT = 0,
+ NUMBER_SREPEAT = 1,
+ NUMBER_UINTEGER = 2,
+ NUMBER_SINTEGER = 3,
+ NUMBER_GAMMA = 4,
+ NUMBER_FIXED = 5,
+ NUMBER_FLOAT = 7
+} SurfaceNumber;
+#endif /*ENUMS_SurfaceNumber_H*/
+
+#ifndef ENUMS_SurfaceFormat_H
+#define ENUMS_SurfaceFormat_H
+typedef enum SurfaceFormat {
+ FMT_1_REVERSE = 0,
+ FMT_1 = 1,
+ FMT_8 = 2,
+ FMT_1_5_5_5 = 3,
+ FMT_5_6_5 = 4,
+ FMT_6_5_5 = 5,
+ FMT_8_8_8_8 = 6,
+ FMT_2_10_10_10 = 7,
+ FMT_8_A = 8,
+ FMT_8_B = 9,
+ FMT_8_8 = 10,
+ FMT_Cr_Y1_Cb_Y0 = 11,
+ FMT_Y1_Cr_Y0_Cb = 12,
+ FMT_5_5_5_1 = 13,
+ FMT_8_8_8_8_A = 14,
+ FMT_4_4_4_4 = 15,
+ FMT_8_8_8 = 16,
+ FMT_DXT1 = 18,
+ FMT_DXT2_3 = 19,
+ FMT_DXT4_5 = 20,
+ FMT_10_10_10_2 = 21,
+ FMT_24_8 = 22,
+ FMT_16 = 24,
+ FMT_16_16 = 25,
+ FMT_16_16_16_16 = 26,
+ FMT_16_EXPAND = 27,
+ FMT_16_16_EXPAND = 28,
+ FMT_16_16_16_16_EXPAND = 29,
+ FMT_16_FLOAT = 30,
+ FMT_16_16_FLOAT = 31,
+ FMT_16_16_16_16_FLOAT = 32,
+ FMT_32 = 33,
+ FMT_32_32 = 34,
+ FMT_32_32_32_32 = 35,
+ FMT_32_FLOAT = 36,
+ FMT_32_32_FLOAT = 37,
+ FMT_32_32_32_32_FLOAT = 38,
+ FMT_ATI_TC_RGB = 39,
+ FMT_ATI_TC_RGBA = 40,
+ FMT_ATI_TC_555_565_RGB = 41,
+ FMT_ATI_TC_555_565_RGBA = 42,
+ FMT_ATI_TC_RGBA_INTERP = 43,
+ FMT_ATI_TC_555_565_RGBA_INTERP = 44,
+ FMT_ETC1_RGBA_INTERP = 46,
+ FMT_ETC1_RGB = 47,
+ FMT_ETC1_RGBA = 48,
+ FMT_DXN = 49,
+ FMT_2_3_3 = 51,
+ FMT_2_10_10_10_AS_16_16_16_16 = 54,
+ FMT_10_10_10_2_AS_16_16_16_16 = 55,
+ FMT_32_32_32_FLOAT = 57,
+ FMT_DXT3A = 58,
+ FMT_DXT5A = 59,
+ FMT_CTX1 = 60,
+} SurfaceFormat;
+#endif /*ENUMS_SurfaceFormat_H*/
+
+#ifndef ENUMS_SurfaceTiling_H
+#define ENUMS_SurfaceTiling_H
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0,
+ ARRAY_TILED = 1
+} SurfaceTiling;
+#endif /*ENUMS_SurfaceTiling_H*/
+
+#ifndef ENUMS_SurfaceArray_H
+#define ENUMS_SurfaceArray_H
+typedef enum SurfaceArray {
+ ARRAY_1D = 0,
+ ARRAY_2D = 1,
+ ARRAY_3D = 2,
+ ARRAY_3D_SLICE = 3
+} SurfaceArray;
+#endif /*ENUMS_SurfaceArray_H*/
+
+#ifndef ENUMS_SurfaceNumberX_H
+#define ENUMS_SurfaceNumberX_H
+typedef enum SurfaceNumberX {
+ NUMBERX_UREPEAT = 0,
+ NUMBERX_SREPEAT = 1,
+ NUMBERX_UINTEGER = 2,
+ NUMBERX_SINTEGER = 3,
+ NUMBERX_FLOAT = 7
+} SurfaceNumberX;
+#endif /*ENUMS_SurfaceNumberX_H*/
+
+#ifndef ENUMS_ColorArrayX_H
+#define ENUMS_ColorArrayX_H
+typedef enum ColorArrayX {
+ ARRAYX_2D_COLOR = 0,
+ ARRAYX_3D_SLICE_COLOR = 1,
+} ColorArrayX;
+#endif /*ENUMS_ColorArrayX_H*/
+
+#endif /*_yamato_ENUM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h
new file mode 100644
index 000000000000..f2f4dec63daa
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h
@@ -0,0 +1,1674 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_ENUMTYPE(SU_PERFCNT_SELECT)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0)
+    GENERATE_ENUM(UNUSED1, 1)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13)
+    GENERATE_ENUM(UNUSED2, 14)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15)
+    GENERATE_ENUM(UNUSED3, 16)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19)
+    GENERATE_ENUM(UNUSED4, 20)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21)
+    GENERATE_ENUM(UNUSED5, 22)
+    GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36)
+    GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49)
+    GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50)
+    GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51)
+    GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95)
+    GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96)
+    GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97)
+    GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98)
+    GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99)
+    GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100)
+    GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101)
+END_ENUMTYPE(SU_PERFCNT_SELECT)
+
+START_ENUMTYPE(SC_PERFCNT_SELECT)
+    GENERATE_ENUM(SC_SR_WINDOW_VALID, 0)
+    GENERATE_ENUM(SC_CW_WINDOW_VALID, 1)
+    GENERATE_ENUM(SC_QM_WINDOW_VALID, 2)
+    GENERATE_ENUM(SC_FW_WINDOW_VALID, 3)
+    GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4)
+    GENERATE_ENUM(SC_IT_WINDOW_VALID, 5)
+    GENERATE_ENUM(SC_STARVED_BY_PA, 6)
+    GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7)
+    GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8)
+    GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9)
+    GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10)
+    GENERATE_ENUM(SC_STALLED_BY_SQ, 11)
+    GENERATE_ENUM(SC_STALLED_BY_SP, 12)
+    GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13)
+    GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14)
+    GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15)
+    GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16)
+    GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17)
+END_ENUMTYPE(SC_PERFCNT_SELECT)
+
+START_ENUMTYPE(VGT_DI_PRIM_TYPE)
+    GENERATE_ENUM(DI_PT_NONE, 0)
+    GENERATE_ENUM(DI_PT_POINTLIST, 1)
+    GENERATE_ENUM(DI_PT_LINELIST, 2)
+    GENERATE_ENUM(DI_PT_LINESTRIP, 3)
+    GENERATE_ENUM(DI_PT_TRILIST, 4)
+    GENERATE_ENUM(DI_PT_TRIFAN, 5)
+    GENERATE_ENUM(DI_PT_TRISTRIP, 6)
+    GENERATE_ENUM(DI_PT_UNUSED_1, 7)
+    GENERATE_ENUM(DI_PT_RECTLIST, 8)
+    GENERATE_ENUM(DI_PT_UNUSED_2, 9)
+    GENERATE_ENUM(DI_PT_UNUSED_3, 10)
+    GENERATE_ENUM(DI_PT_UNUSED_4, 11)
+    GENERATE_ENUM(DI_PT_UNUSED_5, 12)
+    GENERATE_ENUM(DI_PT_QUADLIST, 13)
+    GENERATE_ENUM(DI_PT_QUADSTRIP, 14)
+    GENERATE_ENUM(DI_PT_POLYGON, 15)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19)
+    GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20)
+    GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21)
+    GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22)
+END_ENUMTYPE(VGT_DI_PRIM_TYPE)
+
+START_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+    GENERATE_ENUM(DI_SRC_SEL_DMA, 0)
+    GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1)
+    GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2)
+    GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3)
+END_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+
+START_ENUMTYPE(VGT_DI_INDEX_SIZE)
+    GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1)
+END_ENUMTYPE(VGT_DI_INDEX_SIZE)
+
+START_ENUMTYPE(VGT_DI_SMALL_INDEX)
+    GENERATE_ENUM(DI_USE_INDEX_SIZE, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1)
+END_ENUMTYPE(VGT_DI_SMALL_INDEX)
+
+START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0)
+    GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0)
+    GENERATE_ENUM(GRP_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_EVENT_TYPE)
+    GENERATE_ENUM(VS_DEALLOC, 0)
+    GENERATE_ENUM(PS_DEALLOC, 1)
+    GENERATE_ENUM(VS_DONE_TS, 2)
+    GENERATE_ENUM(PS_DONE_TS, 3)
+    GENERATE_ENUM(CACHE_FLUSH_TS, 4)
+    GENERATE_ENUM(CONTEXT_DONE, 5)
+    GENERATE_ENUM(CACHE_FLUSH, 6)
+    GENERATE_ENUM(VIZQUERY_START, 7)
+    GENERATE_ENUM(VIZQUERY_END, 8)
+    GENERATE_ENUM(SC_WAIT_WC, 9)
+    GENERATE_ENUM(RST_PIX_CNT, 13)
+    GENERATE_ENUM(RST_VTX_CNT, 14)
+    GENERATE_ENUM(TILE_FLUSH, 15)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20)
+    GENERATE_ENUM(ZPASS_DONE, 21)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22)
+    GENERATE_ENUM(PERFCOUNTER_START, 23)
+    GENERATE_ENUM(PERFCOUNTER_STOP, 24)
+    GENERATE_ENUM(VS_FETCH_DONE, 27)
+END_ENUMTYPE(VGT_EVENT_TYPE)
+
+START_ENUMTYPE(VGT_DMA_SWAP_MODE)
+    GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0)
+    GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1)
+    GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2)
+    GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3)
+END_ENUMTYPE(VGT_DMA_SWAP_MODE)
+
+START_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0)
+    GENERATE_ENUM(VGT_SQ_SEND, 1)
+    GENERATE_ENUM(VGT_SQ_STALLED, 2)
+    GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3)
+    GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4)
+    GENERATE_ENUM(VGT_SQ_STATIC, 5)
+    GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6)
+    GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11)
+    GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16)
+    GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21)
+    GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28)
+    GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29)
+    GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30)
+    GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31)
+    GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32)
+    GENERATE_ENUM(SPARE33, 33)
+    GENERATE_ENUM(SPARE34, 34)
+    GENERATE_ENUM(SPARE35, 35)
+    GENERATE_ENUM(SPARE36, 36)
+    GENERATE_ENUM(SPARE37, 37)
+    GENERATE_ENUM(SPARE38, 38)
+    GENERATE_ENUM(SPARE39, 39)
+    GENERATE_ENUM(TE_SU_IN_VALID, 40)
+    GENERATE_ENUM(TE_SU_IN_READ, 41)
+    GENERATE_ENUM(TE_SU_IN_PRIM, 42)
+    GENERATE_ENUM(TE_SU_IN_EOP, 43)
+    GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44)
+    GENERATE_ENUM(TE_WK_IN_VALID, 45)
+    GENERATE_ENUM(TE_WK_IN_READ, 46)
+    GENERATE_ENUM(TE_OUT_PRIM_VALID, 47)
+    GENERATE_ENUM(TE_OUT_PRIM_READ, 48)
+END_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+    GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0)
+    GENERATE_ENUM(reserved_46, 1)
+    GENERATE_ENUM(reserved_47, 2)
+    GENERATE_ENUM(reserved_48, 3)
+    GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4)
+    GENERATE_ENUM(OPMUX0_L2_WRITES, 5)
+    GENERATE_ENUM(reserved_49, 6)
+    GENERATE_ENUM(reserved_50, 7)
+    GENERATE_ENUM(reserved_51, 8)
+END_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TP_PERFCOUNT_SELECT)
+    GENERATE_ENUM(POINT_QUADS, 0)
+    GENERATE_ENUM(BILIN_QUADS, 1)
+    GENERATE_ENUM(ANISO_QUADS, 2)
+    GENERATE_ENUM(MIP_QUADS, 3)
+    GENERATE_ENUM(VOL_QUADS, 4)
+    GENERATE_ENUM(MIP_VOL_QUADS, 5)
+    GENERATE_ENUM(MIP_ANISO_QUADS, 6)
+    GENERATE_ENUM(VOL_ANISO_QUADS, 7)
+    GENERATE_ENUM(ANISO_2_1_QUADS, 8)
+    GENERATE_ENUM(ANISO_4_1_QUADS, 9)
+    GENERATE_ENUM(ANISO_6_1_QUADS, 10)
+    GENERATE_ENUM(ANISO_8_1_QUADS, 11)
+    GENERATE_ENUM(ANISO_10_1_QUADS, 12)
+    GENERATE_ENUM(ANISO_12_1_QUADS, 13)
+    GENERATE_ENUM(ANISO_14_1_QUADS, 14)
+    GENERATE_ENUM(ANISO_16_1_QUADS, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16)
+    GENERATE_ENUM(ALIGN_2_QUADS, 17)
+    GENERATE_ENUM(ALIGN_4_QUADS, 18)
+    GENERATE_ENUM(PIX_0_QUAD, 19)
+    GENERATE_ENUM(PIX_1_QUAD, 20)
+    GENERATE_ENUM(PIX_2_QUAD, 21)
+    GENERATE_ENUM(PIX_3_QUAD, 22)
+    GENERATE_ENUM(PIX_4_QUAD, 23)
+    GENERATE_ENUM(TP_MIPMAP_LOD0, 24)
+    GENERATE_ENUM(TP_MIPMAP_LOD1, 25)
+    GENERATE_ENUM(TP_MIPMAP_LOD2, 26)
+    GENERATE_ENUM(TP_MIPMAP_LOD3, 27)
+    GENERATE_ENUM(TP_MIPMAP_LOD4, 28)
+    GENERATE_ENUM(TP_MIPMAP_LOD5, 29)
+    GENERATE_ENUM(TP_MIPMAP_LOD6, 30)
+    GENERATE_ENUM(TP_MIPMAP_LOD7, 31)
+    GENERATE_ENUM(TP_MIPMAP_LOD8, 32)
+    GENERATE_ENUM(TP_MIPMAP_LOD9, 33)
+    GENERATE_ENUM(TP_MIPMAP_LOD10, 34)
+    GENERATE_ENUM(TP_MIPMAP_LOD11, 35)
+    GENERATE_ENUM(TP_MIPMAP_LOD12, 36)
+    GENERATE_ENUM(TP_MIPMAP_LOD13, 37)
+    GENERATE_ENUM(TP_MIPMAP_LOD14, 38)
+END_ENUMTYPE(TP_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0)
+    GENERATE_ENUM(reserved_01, 1)
+    GENERATE_ENUM(reserved_02, 2)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6)
+    GENERATE_ENUM(reserved_07, 7)
+    GENERATE_ENUM(reserved_08, 8)
+    GENERATE_ENUM(reserved_09, 9)
+    GENERATE_ENUM(reserved_10, 10)
+    GENERATE_ENUM(reserved_11, 11)
+    GENERATE_ENUM(reserved_12, 12)
+    GENERATE_ENUM(reserved_13, 13)
+    GENERATE_ENUM(reserved_14, 14)
+    GENERATE_ENUM(reserved_15, 15)
+    GENERATE_ENUM(reserved_16, 16)
+    GENERATE_ENUM(reserved_17, 17)
+    GENERATE_ENUM(reserved_18, 18)
+    GENERATE_ENUM(reserved_19, 19)
+    GENERATE_ENUM(reserved_20, 20)
+    GENERATE_ENUM(reserved_21, 21)
+    GENERATE_ENUM(reserved_22, 22)
+    GENERATE_ENUM(reserved_23, 23)
+    GENERATE_ENUM(reserved_24, 24)
+    GENERATE_ENUM(reserved_25, 25)
+    GENERATE_ENUM(reserved_26, 26)
+    GENERATE_ENUM(reserved_27, 27)
+    GENERATE_ENUM(READ_STARVED_QUAD0, 28)
+    GENERATE_ENUM(reserved_29, 29)
+    GENERATE_ENUM(reserved_30, 30)
+    GENERATE_ENUM(reserved_31, 31)
+    GENERATE_ENUM(READ_STARVED, 32)
+    GENERATE_ENUM(READ_STALLED_QUAD0, 33)
+    GENERATE_ENUM(reserved_34, 34)
+    GENERATE_ENUM(reserved_35, 35)
+    GENERATE_ENUM(reserved_36, 36)
+    GENERATE_ENUM(READ_STALLED, 37)
+    GENERATE_ENUM(VALID_READ_QUAD0, 38)
+    GENERATE_ENUM(reserved_39, 39)
+    GENERATE_ENUM(reserved_40, 40)
+    GENERATE_ENUM(reserved_41, 41)
+    GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42)
+    GENERATE_ENUM(reserved_43, 43)
+    GENERATE_ENUM(reserved_44, 44)
+    GENERATE_ENUM(reserved_45, 45)
+    GENERATE_ENUM(TC_TP_STARVED, 46)
+END_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VALID_CYCLES, 0)
+    GENERATE_ENUM(SINGLE_PHASES, 1)
+    GENERATE_ENUM(ANISO_PHASES, 2)
+    GENERATE_ENUM(MIP_PHASES, 3)
+    GENERATE_ENUM(VOL_PHASES, 4)
+    GENERATE_ENUM(MIP_VOL_PHASES, 5)
+    GENERATE_ENUM(MIP_ANISO_PHASES, 6)
+    GENERATE_ENUM(VOL_ANISO_PHASES, 7)
+    GENERATE_ENUM(ANISO_2_1_PHASES, 8)
+    GENERATE_ENUM(ANISO_4_1_PHASES, 9)
+    GENERATE_ENUM(ANISO_6_1_PHASES, 10)
+    GENERATE_ENUM(ANISO_8_1_PHASES, 11)
+    GENERATE_ENUM(ANISO_10_1_PHASES, 12)
+    GENERATE_ENUM(ANISO_12_1_PHASES, 13)
+    GENERATE_ENUM(ANISO_14_1_PHASES, 14)
+    GENERATE_ENUM(ANISO_16_1_PHASES, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16)
+    GENERATE_ENUM(ALIGN_2_PHASES, 17)
+    GENERATE_ENUM(ALIGN_4_PHASES, 18)
+    GENERATE_ENUM(TPC_BUSY, 19)
+    GENERATE_ENUM(TPC_STALLED, 20)
+    GENERATE_ENUM(TPC_STARVED, 21)
+    GENERATE_ENUM(TPC_WORKING, 22)
+    GENERATE_ENUM(TPC_WALKER_BUSY, 23)
+    GENERATE_ENUM(TPC_WALKER_STALLED, 24)
+    GENERATE_ENUM(TPC_WALKER_WORKING, 25)
+    GENERATE_ENUM(TPC_ALIGNER_BUSY, 26)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED, 27)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29)
+    GENERATE_ENUM(TPC_ALIGNER_WORKING, 30)
+    GENERATE_ENUM(TPC_BLEND_BUSY, 31)
+    GENERATE_ENUM(TPC_BLEND_SYNC, 32)
+    GENERATE_ENUM(TPC_BLEND_STARVED, 33)
+    GENERATE_ENUM(TPC_BLEND_WORKING, 34)
+    GENERATE_ENUM(OPCODE_0x00, 35)
+    GENERATE_ENUM(OPCODE_0x01, 36)
+    GENERATE_ENUM(OPCODE_0x04, 37)
+    GENERATE_ENUM(OPCODE_0x10, 38)
+    GENERATE_ENUM(OPCODE_0x11, 39)
+    GENERATE_ENUM(OPCODE_0x12, 40)
+    GENERATE_ENUM(OPCODE_0x13, 41)
+    GENERATE_ENUM(OPCODE_0x18, 42)
+    GENERATE_ENUM(OPCODE_0x19, 43)
+    GENERATE_ENUM(OPCODE_0x1A, 44)
+    GENERATE_ENUM(OPCODE_OTHER, 45)
+    GENERATE_ENUM(IN_FIFO_0_EMPTY, 56)
+    GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57)
+    GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58)
+    GENERATE_ENUM(IN_FIFO_0_FULL, 59)
+    GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72)
+    GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73)
+    GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74)
+    GENERATE_ENUM(IN_FIFO_TPC_FULL, 75)
+    GENERATE_ENUM(TPC_TC_XFC, 76)
+    GENERATE_ENUM(TPC_TC_STATE, 77)
+    GENERATE_ENUM(TC_STALL, 78)
+    GENERATE_ENUM(QUAD0_TAPS, 79)
+    GENERATE_ENUM(QUADS, 83)
+    GENERATE_ENUM(TCA_SYNC_STALL, 84)
+    GENERATE_ENUM(TAG_STALL, 85)
+    GENERATE_ENUM(TCB_SYNC_STALL, 88)
+    GENERATE_ENUM(TCA_VALID, 89)
+    GENERATE_ENUM(PROBES_VALID, 90)
+    GENERATE_ENUM(MISS_STALL, 91)
+    GENERATE_ENUM(FETCH_FIFO_STALL, 92)
+    GENERATE_ENUM(TCO_STALL, 93)
+    GENERATE_ENUM(ANY_STALL, 94)
+    GENERATE_ENUM(TAG_MISSES, 95)
+    GENERATE_ENUM(TAG_HITS, 96)
+    GENERATE_ENUM(SUB_TAG_MISSES, 97)
+    GENERATE_ENUM(SET0_INVALIDATES, 98)
+    GENERATE_ENUM(SET1_INVALIDATES, 99)
+    GENERATE_ENUM(SET2_INVALIDATES, 100)
+    GENERATE_ENUM(SET3_INVALIDATES, 101)
+    GENERATE_ENUM(SET0_TAG_MISSES, 102)
+    GENERATE_ENUM(SET1_TAG_MISSES, 103)
+    GENERATE_ENUM(SET2_TAG_MISSES, 104)
+    GENERATE_ENUM(SET3_TAG_MISSES, 105)
+    GENERATE_ENUM(SET0_TAG_HITS, 106)
+    GENERATE_ENUM(SET1_TAG_HITS, 107)
+    GENERATE_ENUM(SET2_TAG_HITS, 108)
+    GENERATE_ENUM(SET3_TAG_HITS, 109)
+    GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110)
+    GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111)
+    GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112)
+    GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113)
+    GENERATE_ENUM(SET0_EVICT1, 114)
+    GENERATE_ENUM(SET0_EVICT2, 115)
+    GENERATE_ENUM(SET0_EVICT3, 116)
+    GENERATE_ENUM(SET0_EVICT4, 117)
+    GENERATE_ENUM(SET0_EVICT5, 118)
+    GENERATE_ENUM(SET0_EVICT6, 119)
+    GENERATE_ENUM(SET0_EVICT7, 120)
+    GENERATE_ENUM(SET0_EVICT8, 121)
+    GENERATE_ENUM(SET1_EVICT1, 130)
+    GENERATE_ENUM(SET1_EVICT2, 131)
+    GENERATE_ENUM(SET1_EVICT3, 132)
+    GENERATE_ENUM(SET1_EVICT4, 133)
+    GENERATE_ENUM(SET1_EVICT5, 134)
+    GENERATE_ENUM(SET1_EVICT6, 135)
+    GENERATE_ENUM(SET1_EVICT7, 136)
+    GENERATE_ENUM(SET1_EVICT8, 137)
+    GENERATE_ENUM(SET2_EVICT1, 146)
+    GENERATE_ENUM(SET2_EVICT2, 147)
+    GENERATE_ENUM(SET2_EVICT3, 148)
+    GENERATE_ENUM(SET2_EVICT4, 149)
+    GENERATE_ENUM(SET2_EVICT5, 150)
+    GENERATE_ENUM(SET2_EVICT6, 151)
+    GENERATE_ENUM(SET2_EVICT7, 152)
+    GENERATE_ENUM(SET2_EVICT8, 153)
+    GENERATE_ENUM(SET3_EVICT1, 162)
+    GENERATE_ENUM(SET3_EVICT2, 163)
+    GENERATE_ENUM(SET3_EVICT3, 164)
+    GENERATE_ENUM(SET3_EVICT4, 165)
+    GENERATE_ENUM(SET3_EVICT5, 166)
+    GENERATE_ENUM(SET3_EVICT6, 167)
+    GENERATE_ENUM(SET3_EVICT7, 168)
+    GENERATE_ENUM(SET3_EVICT8, 169)
+    GENERATE_ENUM(FF_EMPTY, 178)
+    GENERATE_ENUM(FF_LT_HALF_FULL, 179)
+    GENERATE_ENUM(FF_HALF_FULL, 180)
+    GENERATE_ENUM(FF_FULL, 181)
+    GENERATE_ENUM(FF_XFC, 182)
+    GENERATE_ENUM(FF_STALLED, 183)
+    GENERATE_ENUM(FG_MASKS, 184)
+    GENERATE_ENUM(FG_LEFT_MASKS, 185)
+    GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186)
+    GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187)
+    GENERATE_ENUM(FG_LEFT_FG_STALL, 188)
+    GENERATE_ENUM(FG_LEFT_SECTORS, 189)
+    GENERATE_ENUM(FG0_REQUESTS, 195)
+    GENERATE_ENUM(FG0_STALLED, 196)
+    GENERATE_ENUM(MEM_REQ512, 199)
+    GENERATE_ENUM(MEM_REQ_SENT, 200)
+    GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202)
+    GENERATE_ENUM(TC0_MH_STALLED, 203)
+END_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(SQ_PERFCNT_SELECT)
+    GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0)
+    GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9)
+    GENERATE_ENUM(SQ_EXPORT_CYCLES, 10)
+    GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11)
+    GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12)
+    GENERATE_ENUM(SQ_ALU_CST_STALL, 13)
+    GENERATE_ENUM(SQ_ALU_TEX_STALL, 14)
+    GENERATE_ENUM(SQ_INST_WRITTEN, 15)
+    GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16)
+    GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21)
+    GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22)
+    GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23)
+    GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24)
+    GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25)
+    GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26)
+    GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27)
+    GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28)
+    GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33)
+    GENERATE_ENUM(SQ_ALU_NOPS, 34)
+    GENERATE_ENUM(SQ_PRED_SKIP, 35)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41)
+    GENERATE_ENUM(SQ_GPR_STALL_VTX, 42)
+    GENERATE_ENUM(SQ_GPR_STALL_PIX, 43)
+    GENERATE_ENUM(SQ_VTX_RS_STALL, 44)
+    GENERATE_ENUM(SQ_PIX_RS_STALL, 45)
+    GENERATE_ENUM(SQ_SX_PC_FULL, 46)
+    GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47)
+    GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48)
+    GENERATE_ENUM(SQ_INTERP_QUADS, 49)
+    GENERATE_ENUM(SQ_INTERP_ACTIVE, 50)
+    GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51)
+    GENERATE_ENUM(SQ_IN_VTX_STALL, 52)
+    GENERATE_ENUM(SQ_VTX_CNT, 53)
+    GENERATE_ENUM(SQ_VTX_VECTOR2, 54)
+    GENERATE_ENUM(SQ_VTX_VECTOR3, 55)
+    GENERATE_ENUM(SQ_VTX_VECTOR4, 56)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61)
+    GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD3, 68)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD3, 70)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD3_VTX, 76)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD3_PIX, 80)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD3, 85)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD3, 86)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94)
+    GENERATE_ENUM(VC_PERF_STATIC, 95)
+    GENERATE_ENUM(VC_PERF_STALLED, 96)
+    GENERATE_ENUM(VC_PERF_STARVED, 97)
+    GENERATE_ENUM(VC_PERF_SEND, 98)
+    GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99)
+    GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100)
+    GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101)
+    GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102)
+    GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103)
+    GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104)
+    GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105)
+    GENERATE_ENUM(PTRBUFF_EF_PUSH, 106)
+    GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107)
+    GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108)
+    GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112)
+    GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113)
+    GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114)
+    GENERATE_ENUM(PTRBUFF_PI_RTR, 115)
+    GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116)
+    GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117)
+    GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118)
+    GENERATE_ENUM(PTRBUFF_SQ_DEC, 119)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121)
+    GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122)
+    GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123)
+    GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124)
+    GENERATE_ENUM(PTRBUFF_END_BUFFER, 125)
+    GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126)
+    GENERATE_ENUM(VERTS_WRITTEN_SPI, 127)
+    GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128)
+    GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129)
+    GENERATE_ENUM(TP_DATA_RETURN, 130)
+    GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131)
+    GENERATE_ENUM(SPI_WRITES_SP, 132)
+    GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133)
+    GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134)
+    GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135)
+    GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136)
+    GENERATE_ENUM(SP_EXPORTS_TO_SX, 137)
+    GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138)
+    GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139)
+    GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140)
+    GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141)
+    GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142)
+    GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143)
+    GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144)
+    GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145)
+    GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146)
+    GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147)
+    GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148)
+    GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149)
+    GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150)
+    GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151)
+    GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152)
+    GENERATE_ENUM(SQ_PIX_TOTAL, 153)
+    GENERATE_ENUM(SQ_PIX_KILLED, 154)
+END_ENUMTYPE(SQ_PERFCNT_SELECT)
+
+START_ENUMTYPE(SX_PERFCNT_SELECT)
+    GENERATE_ENUM(SX_EXPORT_VECTORS, 0)
+    GENERATE_ENUM(SX_DUMMY_QUADS, 1)
+    GENERATE_ENUM(SX_ALPHA_FAIL, 2)
+    GENERATE_ENUM(SX_RB_QUAD_BUSY, 3)
+    GENERATE_ENUM(SX_RB_COLOR_BUSY, 4)
+    GENERATE_ENUM(SX_RB_QUAD_STALL, 5)
+    GENERATE_ENUM(SX_RB_COLOR_STALL, 6)
+END_ENUMTYPE(SX_PERFCNT_SELECT)
+
+START_ENUMTYPE(Abs_modifier)
+    GENERATE_ENUM(NO_ABS_MOD, 0)
+    GENERATE_ENUM(ABS_MOD, 1)
+END_ENUMTYPE(Abs_modifier)
+
+START_ENUMTYPE(Exporting)
+    GENERATE_ENUM(NOT_EXPORTING, 0)
+    GENERATE_ENUM(EXPORTING, 1)
+END_ENUMTYPE(Exporting)
+
+START_ENUMTYPE(ScalarOpcode)
+    GENERATE_ENUM(ADDs, 0)
+    GENERATE_ENUM(ADD_PREVs, 1)
+    GENERATE_ENUM(MULs, 2)
+    GENERATE_ENUM(MUL_PREVs, 3)
+    GENERATE_ENUM(MUL_PREV2s, 4)
+    GENERATE_ENUM(MAXs, 5)
+    GENERATE_ENUM(MINs, 6)
+    GENERATE_ENUM(SETEs, 7)
+    GENERATE_ENUM(SETGTs, 8)
+    GENERATE_ENUM(SETGTEs, 9)
+    GENERATE_ENUM(SETNEs, 10)
+    GENERATE_ENUM(FRACs, 11)
+    GENERATE_ENUM(TRUNCs, 12)
+    GENERATE_ENUM(FLOORs, 13)
+    GENERATE_ENUM(EXP_IEEE, 14)
+    GENERATE_ENUM(LOG_CLAMP, 15)
+    GENERATE_ENUM(LOG_IEEE, 16)
+    GENERATE_ENUM(RECIP_CLAMP, 17)
+    GENERATE_ENUM(RECIP_FF, 18)
+    GENERATE_ENUM(RECIP_IEEE, 19)
+    GENERATE_ENUM(RECIPSQ_CLAMP, 20)
+    GENERATE_ENUM(RECIPSQ_FF, 21)
+    GENERATE_ENUM(RECIPSQ_IEEE, 22)
+    GENERATE_ENUM(MOVAs, 23)
+    GENERATE_ENUM(MOVA_FLOORs, 24)
+    GENERATE_ENUM(SUBs, 25)
+    GENERATE_ENUM(SUB_PREVs, 26)
+    GENERATE_ENUM(PRED_SETEs, 27)
+    GENERATE_ENUM(PRED_SETNEs, 28)
+    GENERATE_ENUM(PRED_SETGTs, 29)
+    GENERATE_ENUM(PRED_SETGTEs, 30)
+    GENERATE_ENUM(PRED_SET_INVs, 31)
+    GENERATE_ENUM(PRED_SET_POPs, 32)
+    GENERATE_ENUM(PRED_SET_CLRs, 33)
+    GENERATE_ENUM(PRED_SET_RESTOREs, 34)
+    GENERATE_ENUM(KILLEs, 35)
+    GENERATE_ENUM(KILLGTs, 36)
+    GENERATE_ENUM(KILLGTEs, 37)
+    GENERATE_ENUM(KILLNEs, 38)
+    GENERATE_ENUM(KILLONEs, 39)
+    GENERATE_ENUM(SQRT_IEEE, 40)
+    GENERATE_ENUM(MUL_CONST_0, 42)
+    GENERATE_ENUM(MUL_CONST_1, 43)
+    GENERATE_ENUM(ADD_CONST_0, 44)
+    GENERATE_ENUM(ADD_CONST_1, 45)
+    GENERATE_ENUM(SUB_CONST_0, 46)
+    GENERATE_ENUM(SUB_CONST_1, 47)
+    GENERATE_ENUM(SIN, 48)
+    GENERATE_ENUM(COS, 49)
+    GENERATE_ENUM(RETAIN_PREV, 50)
+END_ENUMTYPE(ScalarOpcode)
+
+START_ENUMTYPE(SwizzleType)
+    GENERATE_ENUM(NO_SWIZZLE, 0)
+    GENERATE_ENUM(SHIFT_RIGHT_1, 1)
+    GENERATE_ENUM(SHIFT_RIGHT_2, 2)
+    GENERATE_ENUM(SHIFT_RIGHT_3, 3)
+END_ENUMTYPE(SwizzleType)
+
+START_ENUMTYPE(InputModifier)
+    GENERATE_ENUM(NIL, 0)
+    GENERATE_ENUM(NEGATE, 1)
+END_ENUMTYPE(InputModifier)
+
+START_ENUMTYPE(PredicateSelect)
+    GENERATE_ENUM(NO_PREDICATION, 0)
+    GENERATE_ENUM(PREDICATE_QUAD, 1)
+    GENERATE_ENUM(PREDICATED_2, 2)
+    GENERATE_ENUM(PREDICATED_3, 3)
+END_ENUMTYPE(PredicateSelect)
+
+START_ENUMTYPE(OperandSelect1)
+    GENERATE_ENUM(ABSOLUTE_REG, 0)
+    GENERATE_ENUM(RELATIVE_REG, 1)
+END_ENUMTYPE(OperandSelect1)
+
+START_ENUMTYPE(VectorOpcode)
+    GENERATE_ENUM(ADDv, 0)
+    GENERATE_ENUM(MULv, 1)
+    GENERATE_ENUM(MAXv, 2)
+    GENERATE_ENUM(MINv, 3)
+    GENERATE_ENUM(SETEv, 4)
+    GENERATE_ENUM(SETGTv, 5)
+    GENERATE_ENUM(SETGTEv, 6)
+    GENERATE_ENUM(SETNEv, 7)
+    GENERATE_ENUM(FRACv, 8)
+    GENERATE_ENUM(TRUNCv, 9)
+    GENERATE_ENUM(FLOORv, 10)
+    GENERATE_ENUM(MULADDv, 11)
+    GENERATE_ENUM(CNDEv, 12)
+    GENERATE_ENUM(CNDGTEv, 13)
+    GENERATE_ENUM(CNDGTv, 14)
+    GENERATE_ENUM(DOT4v, 15)
+    GENERATE_ENUM(DOT3v, 16)
+    GENERATE_ENUM(DOT2ADDv, 17)
+    GENERATE_ENUM(CUBEv, 18)
+    GENERATE_ENUM(MAX4v, 19)
+    GENERATE_ENUM(PRED_SETE_PUSHv, 20)
+    GENERATE_ENUM(PRED_SETNE_PUSHv, 21)
+    GENERATE_ENUM(PRED_SETGT_PUSHv, 22)
+    GENERATE_ENUM(PRED_SETGTE_PUSHv, 23)
+    GENERATE_ENUM(KILLEv, 24)
+    GENERATE_ENUM(KILLGTv, 25)
+    GENERATE_ENUM(KILLGTEv, 26)
+    GENERATE_ENUM(KILLNEv, 27)
+    GENERATE_ENUM(DSTv, 28)
+    GENERATE_ENUM(MOVAv, 29)
+END_ENUMTYPE(VectorOpcode)
+
+START_ENUMTYPE(OperandSelect0)
+    GENERATE_ENUM(CONSTANT, 0)
+    GENERATE_ENUM(NON_CONSTANT, 1)
+END_ENUMTYPE(OperandSelect0)
+
+START_ENUMTYPE(Ressource_type)
+    GENERATE_ENUM(ALU, 0)
+    GENERATE_ENUM(TEXTURE, 1)
+END_ENUMTYPE(Ressource_type)
+
+START_ENUMTYPE(Instruction_serial)
+    GENERATE_ENUM(NOT_SERIAL, 0)
+    GENERATE_ENUM(SERIAL, 1)
+END_ENUMTYPE(Instruction_serial)
+
+START_ENUMTYPE(VC_type)
+    GENERATE_ENUM(ALU_TP_REQUEST, 0)
+    GENERATE_ENUM(VC_REQUEST, 1)
+END_ENUMTYPE(VC_type)
+
+START_ENUMTYPE(Addressing)
+    GENERATE_ENUM(RELATIVE_ADDR, 0)
+    GENERATE_ENUM(ABSOLUTE_ADDR, 1)
+END_ENUMTYPE(Addressing)
+
+START_ENUMTYPE(CFOpcode)
+    GENERATE_ENUM(NOP, 0)
+    GENERATE_ENUM(EXECUTE, 1)
+    GENERATE_ENUM(EXECUTE_END, 2)
+    GENERATE_ENUM(COND_EXECUTE, 3)
+    GENERATE_ENUM(COND_EXECUTE_END, 4)
+    GENERATE_ENUM(COND_PRED_EXECUTE, 5)
+    GENERATE_ENUM(COND_PRED_EXECUTE_END, 6)
+    GENERATE_ENUM(LOOP_START, 7)
+    GENERATE_ENUM(LOOP_END, 8)
+    GENERATE_ENUM(COND_CALL, 9)
+    GENERATE_ENUM(RETURN, 10)
+    GENERATE_ENUM(COND_JMP, 11)
+    GENERATE_ENUM(ALLOCATE, 12)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14)
+    GENERATE_ENUM(MARK_VS_FETCH_DONE, 15)
+END_ENUMTYPE(CFOpcode)
+
+START_ENUMTYPE(Allocation_type)
+    GENERATE_ENUM(SQ_NO_ALLOC, 0)
+    GENERATE_ENUM(SQ_POSITION, 1)
+    GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2)
+    GENERATE_ENUM(SQ_MEMORY, 3)
+END_ENUMTYPE(Allocation_type)
+
+START_ENUMTYPE(TexInstOpcode)
+    GENERATE_ENUM(TEX_INST_FETCH, 1)
+    GENERATE_ENUM(TEX_INST_RESERVED_1, 2)
+    GENERATE_ENUM(TEX_INST_RESERVED_2, 3)
+    GENERATE_ENUM(TEX_INST_RESERVED_3, 4)
+    GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16)
+    GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17)
+    GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18)
+    GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19)
+    GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26)
+    GENERATE_ENUM(TEX_INST_RESERVED_4, 27)
+END_ENUMTYPE(TexInstOpcode)
+
+START_ENUMTYPE(Addressmode)
+    GENERATE_ENUM(LOGICAL, 0)
+    GENERATE_ENUM(LOOP_RELATIVE, 1)
+END_ENUMTYPE(Addressmode)
+
+START_ENUMTYPE(TexCoordDenorm)
+    GENERATE_ENUM(TEX_COORD_NORMALIZED, 0)
+    GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1)
+END_ENUMTYPE(TexCoordDenorm)
+
+START_ENUMTYPE(SrcSel)
+    GENERATE_ENUM(SRC_SEL_X, 0)
+    GENERATE_ENUM(SRC_SEL_Y, 1)
+    GENERATE_ENUM(SRC_SEL_Z, 2)
+    GENERATE_ENUM(SRC_SEL_W, 3)
+END_ENUMTYPE(SrcSel)
+
+START_ENUMTYPE(DstSel)
+    GENERATE_ENUM(DST_SEL_X, 0)
+    GENERATE_ENUM(DST_SEL_Y, 1)
+    GENERATE_ENUM(DST_SEL_Z, 2)
+    GENERATE_ENUM(DST_SEL_W, 3)
+    GENERATE_ENUM(DST_SEL_0, 4)
+    GENERATE_ENUM(DST_SEL_1, 5)
+    GENERATE_ENUM(DST_SEL_RSVD, 6)
+    GENERATE_ENUM(DST_SEL_MASK, 7)
+END_ENUMTYPE(DstSel)
+
+START_ENUMTYPE(MagFilter)
+    GENERATE_ENUM(MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MagFilter)
+
+START_ENUMTYPE(MinFilter)
+    GENERATE_ENUM(MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MinFilter)
+
+START_ENUMTYPE(MipFilter)
+    GENERATE_ENUM(MIP_FILTER_POINT, 0)
+    GENERATE_ENUM(MIP_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIP_FILTER_BASEMAP, 2)
+    GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MipFilter)
+
+START_ENUMTYPE(AnisoFilter)
+    GENERATE_ENUM(ANISO_FILTER_DISABLED, 0)
+    GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1)
+    GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2)
+    GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3)
+    GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4)
+    GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5)
+    GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(AnisoFilter)
+
+START_ENUMTYPE(ArbitraryFilter)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5)
+    GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(ArbitraryFilter)
+
+START_ENUMTYPE(VolMagFilter)
+    GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMagFilter)
+
+START_ENUMTYPE(VolMinFilter)
+    GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMinFilter)
+
+START_ENUMTYPE(PredSelect)
+    GENERATE_ENUM(NOT_PREDICATED, 0)
+    GENERATE_ENUM(PREDICATED, 1)
+END_ENUMTYPE(PredSelect)
+
+START_ENUMTYPE(SampleLocation)
+    GENERATE_ENUM(SAMPLE_CENTROID, 0)
+    GENERATE_ENUM(SAMPLE_CENTER, 1)
+END_ENUMTYPE(SampleLocation)
+
+START_ENUMTYPE(VertexMode)
+    GENERATE_ENUM(POSITION_1_VECTOR, 0)
+    GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3)
+    GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6)
+    GENERATE_ENUM(MULTIPASS, 7)
+END_ENUMTYPE(VertexMode)
+
+START_ENUMTYPE(Sample_Cntl)
+    GENERATE_ENUM(CENTROIDS_ONLY, 0)
+    GENERATE_ENUM(CENTERS_ONLY, 1)
+    GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2)
+    GENERATE_ENUM(UNDEF, 3)
+END_ENUMTYPE(Sample_Cntl)
+
+START_ENUMTYPE(MhPerfEncode)
+    GENERATE_ENUM(CP_R0_REQUESTS, 0)
+    GENERATE_ENUM(CP_R1_REQUESTS, 1)
+    GENERATE_ENUM(CP_R2_REQUESTS, 2)
+    GENERATE_ENUM(CP_R3_REQUESTS, 3)
+    GENERATE_ENUM(CP_R4_REQUESTS, 4)
+    GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5)
+    GENERATE_ENUM(CP_W_REQUESTS, 6)
+    GENERATE_ENUM(CP_TOTAL_REQUESTS, 7)
+    GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8)
+    GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9)
+    GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10)
+    GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11)
+    GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12)
+    GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13)
+    GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14)
+    GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15)
+    GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16)
+    GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17)
+    GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18)
+    GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19)
+    GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20)
+    GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21)
+    GENERATE_ENUM(VGT_R0_REQUESTS, 22)
+    GENERATE_ENUM(VGT_R1_REQUESTS, 23)
+    GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24)
+    GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25)
+    GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26)
+    GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27)
+    GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28)
+    GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29)
+    GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30)
+    GENERATE_ENUM(TC_REQUESTS, 31)
+    GENERATE_ENUM(TC_ROQ_REQUESTS, 32)
+    GENERATE_ENUM(TC_INFO_SENT, 33)
+    GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34)
+    GENERATE_ENUM(TC_DATA_BEATS_READ, 35)
+    GENERATE_ENUM(TCD_BURSTS_READ, 36)
+    GENERATE_ENUM(RB_REQUESTS, 37)
+    GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38)
+    GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56)
+    GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111)
+    GENERATE_ENUM(TOTAL_MMU_MISSES, 112)
+    GENERATE_ENUM(MMU_READ_MISSES, 113)
+    GENERATE_ENUM(MMU_WRITE_MISSES, 114)
+    GENERATE_ENUM(TOTAL_MMU_HITS, 115)
+    GENERATE_ENUM(MMU_READ_HITS, 116)
+    GENERATE_ENUM(MMU_WRITE_HITS, 117)
+    GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118)
+    GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121)
+    GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122)
+    GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123)
+    GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124)
+    GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125)
+    GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127)
+    GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129)
+    GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130)
+    GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131)
+    GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132)
+    GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133)
+    GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136)
+    GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140)
+    GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148)
+    GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149)
+    GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150)
+    GENERATE_ENUM(TOTAL_MH_REQUESTS, 151)
+    GENERATE_ENUM(MH_BUSY, 152)
+    GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153)
+    GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154)
+    GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155)
+    GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156)
+    GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157)
+    GENERATE_ENUM(ARQ_N_ENTRIES, 158)
+    GENERATE_ENUM(WDB_N_ENTRIES, 159)
+    GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160)
+    GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161)
+    GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162)
+    GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163)
+END_ENUMTYPE(MhPerfEncode)
+
+START_ENUMTYPE(MmuClntBeh)
+    GENERATE_ENUM(BEH_NEVR, 0)
+    GENERATE_ENUM(BEH_TRAN_RNG, 1)
+    GENERATE_ENUM(BEH_TRAN_FLT, 2)
+END_ENUMTYPE(MmuClntBeh)
+
+START_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+    GENERATE_ENUM(RBBM1_COUNT, 0)
+    GENERATE_ENUM(RBBM1_NRT_BUSY, 1)
+    GENERATE_ENUM(RBBM1_RB_BUSY, 2)
+    GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3)
+    GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4)
+    GENERATE_ENUM(RBBM1_VGT_BUSY, 5)
+    GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6)
+    GENERATE_ENUM(RBBM1_PA_BUSY, 7)
+    GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8)
+    GENERATE_ENUM(RBBM1_TPC_BUSY, 9)
+    GENERATE_ENUM(RBBM1_TC_BUSY, 10)
+    GENERATE_ENUM(RBBM1_SX_BUSY, 11)
+    GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12)
+    GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13)
+    GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14)
+    GENERATE_ENUM(RBBM1_INTERRUPT, 15)
+END_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+
+START_ENUMTYPE(CP_PERFCOUNT_SEL)
+    GENERATE_ENUM(ALWAYS_COUNT, 0)
+    GENERATE_ENUM(TRANS_FIFO_FULL, 1)
+    GENERATE_ENUM(TRANS_FIFO_AF, 2)
+    GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3)
+    GENERATE_ENUM(Reserved_04, 4)
+    GENERATE_ENUM(Reserved_05, 5)
+    GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6)
+    GENERATE_ENUM(Reserved_07, 7)
+    GENERATE_ENUM(CSF_NRT_READ_WAIT, 8)
+    GENERATE_ENUM(CSF_I1_FIFO_FULL, 9)
+    GENERATE_ENUM(CSF_I2_FIFO_FULL, 10)
+    GENERATE_ENUM(CSF_ST_FIFO_FULL, 11)
+    GENERATE_ENUM(Reserved_12, 12)
+    GENERATE_ENUM(CSF_RING_ROQ_FULL, 13)
+    GENERATE_ENUM(CSF_I1_ROQ_FULL, 14)
+    GENERATE_ENUM(CSF_I2_ROQ_FULL, 15)
+    GENERATE_ENUM(CSF_ST_ROQ_FULL, 16)
+    GENERATE_ENUM(Reserved_17, 17)
+    GENERATE_ENUM(MIU_TAG_MEM_FULL, 18)
+    GENERATE_ENUM(MIU_WRITECLEAN, 19)
+    GENERATE_ENUM(Reserved_20, 20)
+    GENERATE_ENUM(Reserved_21, 21)
+    GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22)
+    GENERATE_ENUM(MIU_NRT_READ_STALLED, 23)
+    GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24)
+    GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25)
+    GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26)
+    GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27)
+    GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28)
+    GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29)
+    GENERATE_ENUM(ME_MICRO_RB_STARVED, 30)
+    GENERATE_ENUM(ME_MICRO_I1_STARVED, 31)
+    GENERATE_ENUM(ME_MICRO_I2_STARVED, 32)
+    GENERATE_ENUM(ME_MICRO_ST_STARVED, 33)
+    GENERATE_ENUM(Reserved_34, 34)
+    GENERATE_ENUM(Reserved_35, 35)
+    GENERATE_ENUM(Reserved_36, 36)
+    GENERATE_ENUM(Reserved_37, 37)
+    GENERATE_ENUM(Reserved_38, 38)
+    GENERATE_ENUM(Reserved_39, 39)
+    GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40)
+    GENERATE_ENUM(ME_BUSY_CLOCKS, 41)
+    GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42)
+    GENERATE_ENUM(PFP_TYPE0_PACKET, 43)
+    GENERATE_ENUM(PFP_TYPE3_PACKET, 44)
+    GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45)
+    GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46)
+    GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47)
+    GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48)
+    GENERATE_ENUM(Reserved_49, 49)
+    GENERATE_ENUM(Reserved_50, 50)
+    GENERATE_ENUM(Reserved_51, 51)
+    GENERATE_ENUM(Reserved_52, 52)
+    GENERATE_ENUM(Reserved_53, 53)
+    GENERATE_ENUM(Reserved_54, 54)
+    GENERATE_ENUM(Reserved_55, 55)
+    GENERATE_ENUM(Reserved_56, 56)
+    GENERATE_ENUM(Reserved_57, 57)
+    GENERATE_ENUM(Reserved_58, 58)
+    GENERATE_ENUM(Reserved_59, 59)
+    GENERATE_ENUM(Reserved_60, 60)
+    GENERATE_ENUM(Reserved_61, 61)
+    GENERATE_ENUM(Reserved_62, 62)
+    GENERATE_ENUM(Reserved_63, 63)
+END_ENUMTYPE(CP_PERFCOUNT_SEL)
+
+START_ENUMTYPE(ColorformatX)
+    GENERATE_ENUM(COLORX_4_4_4_4, 0)
+    GENERATE_ENUM(COLORX_1_5_5_5, 1)
+    GENERATE_ENUM(COLORX_5_6_5, 2)
+    GENERATE_ENUM(COLORX_8, 3)
+    GENERATE_ENUM(COLORX_8_8, 4)
+    GENERATE_ENUM(COLORX_8_8_8_8, 5)
+    GENERATE_ENUM(COLORX_S8_8_8_8, 6)
+    GENERATE_ENUM(COLORX_16_FLOAT, 7)
+    GENERATE_ENUM(COLORX_16_16_FLOAT, 8)
+    GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9)
+    GENERATE_ENUM(COLORX_32_FLOAT, 10)
+    GENERATE_ENUM(COLORX_32_32_FLOAT, 11)
+    GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12)
+    GENERATE_ENUM(COLORX_2_3_3, 13)
+    GENERATE_ENUM(COLORX_8_8_8, 14)
+END_ENUMTYPE(ColorformatX)
+
+START_ENUMTYPE(DepthformatX)
+    GENERATE_ENUM(DEPTHX_16, 0)
+    GENERATE_ENUM(DEPTHX_24_8, 1)
+END_ENUMTYPE(DepthformatX)
+
+START_ENUMTYPE(CompareFrag)
+    GENERATE_ENUM(FRAG_NEVER, 0)
+    GENERATE_ENUM(FRAG_LESS, 1)
+    GENERATE_ENUM(FRAG_EQUAL, 2)
+    GENERATE_ENUM(FRAG_LEQUAL, 3)
+    GENERATE_ENUM(FRAG_GREATER, 4)
+    GENERATE_ENUM(FRAG_NOTEQUAL, 5)
+    GENERATE_ENUM(FRAG_GEQUAL, 6)
+    GENERATE_ENUM(FRAG_ALWAYS, 7)
+END_ENUMTYPE(CompareFrag)
+
+START_ENUMTYPE(CompareRef)
+    GENERATE_ENUM(REF_NEVER, 0)
+    GENERATE_ENUM(REF_LESS, 1)
+    GENERATE_ENUM(REF_EQUAL, 2)
+    GENERATE_ENUM(REF_LEQUAL, 3)
+    GENERATE_ENUM(REF_GREATER, 4)
+    GENERATE_ENUM(REF_NOTEQUAL, 5)
+    GENERATE_ENUM(REF_GEQUAL, 6)
+    GENERATE_ENUM(REF_ALWAYS, 7)
+END_ENUMTYPE(CompareRef)
+
+START_ENUMTYPE(StencilOp)
+    GENERATE_ENUM(STENCIL_KEEP, 0)
+    GENERATE_ENUM(STENCIL_ZERO, 1)
+    GENERATE_ENUM(STENCIL_REPLACE, 2)
+    GENERATE_ENUM(STENCIL_INCR_CLAMP, 3)
+    GENERATE_ENUM(STENCIL_DECR_CLAMP, 4)
+    GENERATE_ENUM(STENCIL_INVERT, 5)
+    GENERATE_ENUM(STENCIL_INCR_WRAP, 6)
+    GENERATE_ENUM(STENCIL_DECR_WRAP, 7)
+END_ENUMTYPE(StencilOp)
+
+START_ENUMTYPE(BlendOpX)
+    GENERATE_ENUM(BLENDX_ZERO, 0)
+    GENERATE_ENUM(BLENDX_ONE, 1)
+    GENERATE_ENUM(BLENDX_SRC_COLOR, 4)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA, 6)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7)
+    GENERATE_ENUM(BLENDX_DST_COLOR, 8)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9)
+    GENERATE_ENUM(BLENDX_DST_ALPHA, 10)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11)
+    GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13)
+    GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16)
+END_ENUMTYPE(BlendOpX)
+
+START_ENUMTYPE(CombFuncX)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC, 0)
+    GENERATE_ENUM(COMB_SRC_MINUS_DST, 1)
+    GENERATE_ENUM(COMB_MIN_DST_SRC, 2)
+    GENERATE_ENUM(COMB_MAX_DST_SRC, 3)
+    GENERATE_ENUM(COMB_DST_MINUS_SRC, 4)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5)
+END_ENUMTYPE(CombFuncX)
+
+START_ENUMTYPE(DitherModeX)
+    GENERATE_ENUM(DITHER_DISABLE, 0)
+    GENERATE_ENUM(DITHER_ALWAYS, 1)
+    GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2)
+END_ENUMTYPE(DitherModeX)
+
+START_ENUMTYPE(DitherTypeX)
+    GENERATE_ENUM(DITHER_PIXEL, 0)
+    GENERATE_ENUM(DITHER_SUBPIXEL, 1)
+END_ENUMTYPE(DitherTypeX)
+
+START_ENUMTYPE(EdramMode)
+    GENERATE_ENUM(EDRAM_NOP, 0)
+    GENERATE_ENUM(COLOR_DEPTH, 4)
+    GENERATE_ENUM(DEPTH_ONLY, 5)
+    GENERATE_ENUM(EDRAM_COPY, 6)
+END_ENUMTYPE(EdramMode)
+
+START_ENUMTYPE(SurfaceEndian)
+    GENERATE_ENUM(ENDIAN_NONE, 0)
+    GENERATE_ENUM(ENDIAN_8IN16, 1)
+    GENERATE_ENUM(ENDIAN_8IN32, 2)
+    GENERATE_ENUM(ENDIAN_16IN32, 3)
+    GENERATE_ENUM(ENDIAN_8IN64, 4)
+    GENERATE_ENUM(ENDIAN_8IN128, 5)
+END_ENUMTYPE(SurfaceEndian)
+
+START_ENUMTYPE(EdramSizeX)
+    GENERATE_ENUM(EDRAMSIZE_16KB, 0)
+    GENERATE_ENUM(EDRAMSIZE_32KB, 1)
+    GENERATE_ENUM(EDRAMSIZE_64KB, 2)
+    GENERATE_ENUM(EDRAMSIZE_128KB, 3)
+    GENERATE_ENUM(EDRAMSIZE_256KB, 4)
+    GENERATE_ENUM(EDRAMSIZE_512KB, 5)
+    GENERATE_ENUM(EDRAMSIZE_1MB, 6)
+    GENERATE_ENUM(EDRAMSIZE_2MB, 7)
+    GENERATE_ENUM(EDRAMSIZE_4MB, 8)
+    GENERATE_ENUM(EDRAMSIZE_8MB, 9)
+    GENERATE_ENUM(EDRAMSIZE_16MB, 10)
+END_ENUMTYPE(EdramSizeX)
+
+START_ENUMTYPE(RB_PERFCNT_SELECT)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY, 0)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7)
+    GENERATE_ENUM(RBPERF_MH_STARVED, 8)
+    GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23)
+    GENERATE_ENUM(RBPERF_ZXP_STALL, 24)
+    GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING, 26)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID, 28)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30)
+    GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32)
+    GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33)
+    GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37)
+    GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38)
+    GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43)
+    GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44)
+    GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45)
+    GENERATE_ENUM(RBPERF_ZPASS_DONE, 46)
+    GENERATE_ENUM(RBPERF_ZCMD_VALID, 47)
+    GENERATE_ENUM(RBPERF_CCMD_VALID, 48)
+    GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49)
+    GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50)
+    GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51)
+    GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52)
+    GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53)
+    GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54)
+    GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55)
+    GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56)
+END_ENUMTYPE(RB_PERFCNT_SELECT)
+
+START_ENUMTYPE(DepthFormat)
+    GENERATE_ENUM(DEPTH_24_8, 22)
+    GENERATE_ENUM(DEPTH_24_8_FLOAT, 23)
+    GENERATE_ENUM(DEPTH_16, 24)
+END_ENUMTYPE(DepthFormat)
+
+START_ENUMTYPE(SurfaceSwap)
+    GENERATE_ENUM(SWAP_LOWRED, 0)
+    GENERATE_ENUM(SWAP_LOWBLUE, 1)
+END_ENUMTYPE(SurfaceSwap)
+
+START_ENUMTYPE(DepthArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0)
+    GENERATE_ENUM(ARRAY_2D_DEPTH, 1)
+END_ENUMTYPE(DepthArray)
+
+START_ENUMTYPE(ColorArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0)
+    GENERATE_ENUM(ARRAY_2D_COLOR, 1)
+    GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3)
+END_ENUMTYPE(ColorArray)
+
+START_ENUMTYPE(ColorFormat)
+    GENERATE_ENUM(COLOR_8, 2)
+    GENERATE_ENUM(COLOR_1_5_5_5, 3)
+    GENERATE_ENUM(COLOR_5_6_5, 4)
+    GENERATE_ENUM(COLOR_6_5_5, 5)
+    GENERATE_ENUM(COLOR_8_8_8_8, 6)
+    GENERATE_ENUM(COLOR_2_10_10_10, 7)
+    GENERATE_ENUM(COLOR_8_A, 8)
+    GENERATE_ENUM(COLOR_8_B, 9)
+    GENERATE_ENUM(COLOR_8_8, 10)
+    GENERATE_ENUM(COLOR_8_8_8, 11)
+    GENERATE_ENUM(COLOR_8_8_8_8_A, 14)
+    GENERATE_ENUM(COLOR_4_4_4_4, 15)
+    GENERATE_ENUM(COLOR_10_11_11, 16)
+    GENERATE_ENUM(COLOR_11_11_10, 17)
+    GENERATE_ENUM(COLOR_16, 24)
+    GENERATE_ENUM(COLOR_16_16, 25)
+    GENERATE_ENUM(COLOR_16_16_16_16, 26)
+    GENERATE_ENUM(COLOR_16_FLOAT, 30)
+    GENERATE_ENUM(COLOR_16_16_FLOAT, 31)
+    GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(COLOR_32_FLOAT, 36)
+    GENERATE_ENUM(COLOR_32_32_FLOAT, 37)
+    GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(COLOR_2_3_3, 39)
+END_ENUMTYPE(ColorFormat)
+
+START_ENUMTYPE(SurfaceNumber)
+    GENERATE_ENUM(NUMBER_UREPEAT, 0)
+    GENERATE_ENUM(NUMBER_SREPEAT, 1)
+    GENERATE_ENUM(NUMBER_UINTEGER, 2)
+    GENERATE_ENUM(NUMBER_SINTEGER, 3)
+    GENERATE_ENUM(NUMBER_GAMMA, 4)
+    GENERATE_ENUM(NUMBER_FIXED, 5)
+    GENERATE_ENUM(NUMBER_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumber)
+
+START_ENUMTYPE(SurfaceFormat)
+    GENERATE_ENUM(FMT_1_REVERSE, 0)
+    GENERATE_ENUM(FMT_1, 1)
+    GENERATE_ENUM(FMT_8, 2)
+    GENERATE_ENUM(FMT_1_5_5_5, 3)
+    GENERATE_ENUM(FMT_5_6_5, 4)
+    GENERATE_ENUM(FMT_6_5_5, 5)
+    GENERATE_ENUM(FMT_8_8_8_8, 6)
+    GENERATE_ENUM(FMT_2_10_10_10, 7)
+    GENERATE_ENUM(FMT_8_A, 8)
+    GENERATE_ENUM(FMT_8_B, 9)
+    GENERATE_ENUM(FMT_8_8, 10)
+    GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11)
+    GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12)
+    GENERATE_ENUM(FMT_5_5_5_1, 13)
+    GENERATE_ENUM(FMT_8_8_8_8_A, 14)
+    GENERATE_ENUM(FMT_4_4_4_4, 15)
+    GENERATE_ENUM(FMT_8_8_8, 16)
+    GENERATE_ENUM(FMT_DXT1, 18)
+    GENERATE_ENUM(FMT_DXT2_3, 19)
+    GENERATE_ENUM(FMT_DXT4_5, 20)
+    GENERATE_ENUM(FMT_10_10_10_2, 21)
+    GENERATE_ENUM(FMT_24_8, 22)
+    GENERATE_ENUM(FMT_16, 24)
+    GENERATE_ENUM(FMT_16_16, 25)
+    GENERATE_ENUM(FMT_16_16_16_16, 26)
+    GENERATE_ENUM(FMT_16_EXPAND, 27)
+    GENERATE_ENUM(FMT_16_16_EXPAND, 28)
+    GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29)
+    GENERATE_ENUM(FMT_16_FLOAT, 30)
+    GENERATE_ENUM(FMT_16_16_FLOAT, 31)
+    GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(FMT_32, 33)
+    GENERATE_ENUM(FMT_32_32, 34)
+    GENERATE_ENUM(FMT_32_32_32_32, 35)
+    GENERATE_ENUM(FMT_32_FLOAT, 36)
+    GENERATE_ENUM(FMT_32_32_FLOAT, 37)
+    GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(FMT_ATI_TC_RGB, 39)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA, 40)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44)
+    GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46)
+    GENERATE_ENUM(FMT_ETC1_RGB, 47)
+    GENERATE_ENUM(FMT_ETC1_RGBA, 48)
+    GENERATE_ENUM(FMT_DXN, 49)
+    GENERATE_ENUM(FMT_2_3_3, 51)
+    GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54)
+    GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55)
+    GENERATE_ENUM(FMT_32_32_32_FLOAT, 57)
+    GENERATE_ENUM(FMT_DXT3A, 58)
+    GENERATE_ENUM(FMT_DXT5A, 59)
+    GENERATE_ENUM(FMT_CTX1, 60)
+END_ENUMTYPE(SurfaceFormat)
+
+START_ENUMTYPE(SurfaceTiling)
+    GENERATE_ENUM(ARRAY_LINEAR, 0)
+    GENERATE_ENUM(ARRAY_TILED, 1)
+END_ENUMTYPE(SurfaceTiling)
+
+START_ENUMTYPE(SurfaceArray)
+    GENERATE_ENUM(ARRAY_1D, 0)
+    GENERATE_ENUM(ARRAY_2D, 1)
+    GENERATE_ENUM(ARRAY_3D, 2)
+    GENERATE_ENUM(ARRAY_3D_SLICE, 3)
+END_ENUMTYPE(SurfaceArray)
+
+START_ENUMTYPE(SurfaceNumberX)
+    GENERATE_ENUM(NUMBERX_UREPEAT, 0)
+    GENERATE_ENUM(NUMBERX_SREPEAT, 1)
+    GENERATE_ENUM(NUMBERX_UINTEGER, 2)
+    GENERATE_ENUM(NUMBERX_SINTEGER, 3)
+    GENERATE_ENUM(NUMBERX_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumberX)
+
+START_ENUMTYPE(ColorArrayX)
+    GENERATE_ENUM(ARRAYX_2D_COLOR, 0)
+    GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1)
+END_ENUMTYPE(ColorArrayX)
+
+
+
+
+// **************************************************************************
+// These are ones that had to be added in addition to what's generated
+// by the autoreg (in CSIM)
+// **************************************************************************
+START_ENUMTYPE(DXClipSpaceDef)
+    GENERATE_ENUM(DXCLIP_OPENGL, 0)
+    GENERATE_ENUM(DXCLIP_DIRECTX, 1)
+END_ENUMTYPE(DXClipSpaceDef)
+
+START_ENUMTYPE(PixCenter)
+    GENERATE_ENUM(PIXCENTER_D3D, 0)
+    GENERATE_ENUM(PIXCENTER_OGL, 1)
+END_ENUMTYPE(PixCenter)
+
+START_ENUMTYPE(RoundMode)
+    GENERATE_ENUM(TRUNCATE,   0)
+    GENERATE_ENUM(ROUND,      1)
+    GENERATE_ENUM(ROUNDTOEVEN,    2)
+    GENERATE_ENUM(ROUNDTOODD,     3)
+END_ENUMTYPE(RoundMode)
+
+START_ENUMTYPE(QuantMode)
+    GENERATE_ENUM(ONE_SIXTEENTH,   0)
+    GENERATE_ENUM(ONE_EIGHTH,      1)
+    GENERATE_ENUM(ONE_QUARTER,     2)
+    GENERATE_ENUM(ONE_HALF,    3)
+    GENERATE_ENUM(ONE,         4)
+END_ENUMTYPE(QuantMode)
+
+START_ENUMTYPE(FrontFace)
+    GENERATE_ENUM(FRONT_CCW,        0)
+    GENERATE_ENUM(FRONT_CW,     1)
+END_ENUMTYPE(FrontFace)
+
+START_ENUMTYPE(PolyMode)
+    GENERATE_ENUM(DISABLED,    0)
+    GENERATE_ENUM(DUALMODE,    1)
+END_ENUMTYPE(PolyMode)
+
+START_ENUMTYPE(PType)
+    GENERATE_ENUM(DRAW_POINTS,      0)
+    GENERATE_ENUM(DRAW_LINES,       1)
+    GENERATE_ENUM(DRAW_TRIANGLES,   2)
+END_ENUMTYPE(PType)
+
+START_ENUMTYPE(MSAANumSamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     3)
+END_ENUMTYPE(MSAANumSamples)
+
+START_ENUMTYPE(PatternBitOrder)
+    GENERATE_ENUM(LITTLE,   0)
+    GENERATE_ENUM(BIG,      1)
+END_ENUMTYPE(PatternBitOrder)
+
+START_ENUMTYPE(AutoResetCntl)
+    GENERATE_ENUM(NEVER,        0)
+    GENERATE_ENUM(EACHPRIMITIVE,    1)
+    GENERATE_ENUM(EACHPACKET,       2)
+END_ENUMTYPE(AutoResetCntl)
+
+START_ENUMTYPE(ParamShade)
+    GENERATE_ENUM(FLAT,     0)
+    GENERATE_ENUM(GOURAUD,  1)
+END_ENUMTYPE(ParamShade)
+
+START_ENUMTYPE(SamplingPattern)
+    GENERATE_ENUM(CENTROID, 0)
+    GENERATE_ENUM(PIXCENTER, 1)
+END_ENUMTYPE(SamplingPattern)
+
+START_ENUMTYPE(MSAASamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     2)
+END_ENUMTYPE(MSAASamples)
+
+START_ENUMTYPE(CopySampleSelect)
+    GENERATE_ENUM(SAMPLE_0, 0)
+    GENERATE_ENUM(SAMPLE_1, 1)
+    GENERATE_ENUM(SAMPLE_2, 2)
+    GENERATE_ENUM(SAMPLE_3, 3)
+    GENERATE_ENUM(SAMPLE_01,    4)
+    GENERATE_ENUM(SAMPLE_23,    5)
+    GENERATE_ENUM(SAMPLE_0123,  6)
+END_ENUMTYPE(CopySampleSelect)
+
+
+#undef START_ENUMTYPE
+#undef GENERATE_ENUM
+#undef END_ENUMTYPE
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h
new file mode 100644
index 000000000000..d44be483e953
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h
@@ -0,0 +1,3310 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_REGISTER(PA_CL_VPORT_XSCALE)
+    GENERATE_FIELD(VPORT_XSCALE, float)
+END_REGISTER(PA_CL_VPORT_XSCALE)
+
+START_REGISTER(PA_CL_VPORT_XOFFSET)
+    GENERATE_FIELD(VPORT_XOFFSET, float)
+END_REGISTER(PA_CL_VPORT_XOFFSET)
+
+START_REGISTER(PA_CL_VPORT_YSCALE)
+    GENERATE_FIELD(VPORT_YSCALE, float)
+END_REGISTER(PA_CL_VPORT_YSCALE)
+
+START_REGISTER(PA_CL_VPORT_YOFFSET)
+    GENERATE_FIELD(VPORT_YOFFSET, float)
+END_REGISTER(PA_CL_VPORT_YOFFSET)
+
+START_REGISTER(PA_CL_VPORT_ZSCALE)
+    GENERATE_FIELD(VPORT_ZSCALE, float)
+END_REGISTER(PA_CL_VPORT_ZSCALE)
+
+START_REGISTER(PA_CL_VPORT_ZOFFSET)
+    GENERATE_FIELD(VPORT_ZOFFSET, float)
+END_REGISTER(PA_CL_VPORT_ZOFFSET)
+
+START_REGISTER(PA_CL_VTE_CNTL)
+    GENERATE_FIELD(VPORT_X_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool)
+    GENERATE_FIELD(VTX_XY_FMT, bool)
+    GENERATE_FIELD(VTX_Z_FMT, bool)
+    GENERATE_FIELD(VTX_W0_FMT, bool)
+    GENERATE_FIELD(PERFCOUNTER_REF, bool)
+END_REGISTER(PA_CL_VTE_CNTL)
+
+START_REGISTER(PA_CL_CLIP_CNTL)
+    GENERATE_FIELD(CLIP_DISABLE, bool)
+    GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool)
+    GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef)
+    GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool)
+    GENERATE_FIELD(VTX_KILL_OR, bool)
+    GENERATE_FIELD(XY_NAN_RETAIN, bool)
+    GENERATE_FIELD(Z_NAN_RETAIN, bool)
+    GENERATE_FIELD(W_NAN_RETAIN, bool)
+END_REGISTER(PA_CL_CLIP_CNTL)
+
+START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+
+START_REGISTER(PA_CL_ENHANCE)
+    GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE0, int)
+END_REGISTER(PA_CL_ENHANCE)
+
+START_REGISTER(PA_SC_ENHANCE)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE0, int)
+END_REGISTER(PA_SC_ENHANCE)
+
+START_REGISTER(PA_SU_VTX_CNTL)
+    GENERATE_FIELD(PIX_CENTER, PixCenter)
+    GENERATE_FIELD(ROUND_MODE, RoundMode)
+    GENERATE_FIELD(QUANT_MODE, QuantMode)
+END_REGISTER(PA_SU_VTX_CNTL)
+
+START_REGISTER(PA_SU_POINT_SIZE)
+    GENERATE_FIELD(HEIGHT, fixed12_4)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_POINT_SIZE)
+
+START_REGISTER(PA_SU_POINT_MINMAX)
+    GENERATE_FIELD(MIN_SIZE, fixed12_4)
+    GENERATE_FIELD(MAX_SIZE, fixed12_4)
+END_REGISTER(PA_SU_POINT_MINMAX)
+
+START_REGISTER(PA_SU_LINE_CNTL)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_LINE_CNTL)
+
+START_REGISTER(PA_SU_SC_MODE_CNTL)
+    GENERATE_FIELD(CULL_FRONT, bool)
+    GENERATE_FIELD(CULL_BACK, bool)
+    GENERATE_FIELD(FACE, FrontFace)
+    GENERATE_FIELD(POLY_MODE, PolyMode)
+    GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType)
+    GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType)
+    GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool)
+    GENERATE_FIELD(MSAA_ENABLE, bool)
+    GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool)
+    GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool)
+    GENERATE_FIELD(PROVOKING_VTX_LAST, bool)
+    GENERATE_FIELD(PERSP_CORR_DIS, bool)
+    GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool)
+    GENERATE_FIELD(QUAD_ORDER_ENABLE, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool)
+END_REGISTER(PA_SU_SC_MODE_CNTL)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT)
+END_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_HI)
+
+START_REGISTER(PA_SC_WINDOW_OFFSET)
+    GENERATE_FIELD(WINDOW_X_OFFSET, signedint15)
+    GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15)
+END_REGISTER(PA_SC_WINDOW_OFFSET)
+
+START_REGISTER(PA_SC_AA_CONFIG)
+    GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples)
+    GENERATE_FIELD(MAX_SAMPLE_DIST, int)
+END_REGISTER(PA_SC_AA_CONFIG)
+
+START_REGISTER(PA_SC_AA_MASK)
+    GENERATE_FIELD(AA_MASK, hex)
+END_REGISTER(PA_SC_AA_MASK)
+
+START_REGISTER(PA_SC_LINE_STIPPLE)
+    GENERATE_FIELD(LINE_PATTERN, hex)
+    GENERATE_FIELD(REPEAT_COUNT, intMinusOne)
+    GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder)
+    GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl)
+END_REGISTER(PA_SC_LINE_STIPPLE)
+
+START_REGISTER(PA_SC_LINE_CNTL)
+    GENERATE_FIELD(BRES_CNTL, int)
+    GENERATE_FIELD(USE_BRES_CNTL, bool)
+    GENERATE_FIELD(EXPAND_LINE_WIDTH, bool)
+    GENERATE_FIELD(LAST_PIXEL, bool)
+END_REGISTER(PA_SC_LINE_CNTL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+    GENERATE_FIELD(TL_X, int)
+    GENERATE_FIELD(TL_Y, int)
+    GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+    GENERATE_FIELD(BR_X, int)
+    GENERATE_FIELD(BR_Y, int)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+    GENERATE_FIELD(TL_X, int)
+    GENERATE_FIELD(TL_Y, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+    GENERATE_FIELD(BR_X, int)
+    GENERATE_FIELD(BR_Y, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+
+START_REGISTER(PA_SC_VIZ_QUERY)
+    GENERATE_FIELD(VIZ_QUERY_ENA, bool)
+    GENERATE_FIELD(VIZ_QUERY_ID, int)
+    GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool)
+END_REGISTER(PA_SC_VIZ_QUERY)
+
+START_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+    GENERATE_FIELD(STATUS_BITS, hex)
+END_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+
+START_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+    GENERATE_FIELD(CURRENT_PTR, int)
+    GENERATE_FIELD(CURRENT_COUNT, int)
+END_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT)
+END_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_CL_CNTL_STATUS)
+    GENERATE_FIELD(CL_BUSY, int)
+END_REGISTER(PA_CL_CNTL_STATUS)
+
+START_REGISTER(PA_SU_CNTL_STATUS)
+    GENERATE_FIELD(SU_BUSY, int)
+END_REGISTER(PA_SU_CNTL_STATUS)
+
+START_REGISTER(PA_SC_CNTL_STATUS)
+    GENERATE_FIELD(SC_BUSY, int)
+END_REGISTER(PA_SC_CNTL_STATUS)
+
+START_REGISTER(PA_SU_DEBUG_CNTL)
+    GENERATE_FIELD(SU_DEBUG_INDX, int)
+END_REGISTER(PA_SU_DEBUG_CNTL)
+
+START_REGISTER(PA_SU_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(PA_SU_DEBUG_DATA)
+
+START_REGISTER(PA_SC_DEBUG_CNTL)
+    GENERATE_FIELD(SC_DEBUG_INDX, int)
+END_REGISTER(PA_SC_DEBUG_CNTL)
+
+START_REGISTER(PA_SC_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(PA_SC_DEBUG_DATA)
+
+START_REGISTER(GFX_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+END_REGISTER(GFX_COPY_STATE)
+
+START_REGISTER(VGT_DRAW_INITIATOR)
+    GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE)
+    GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT)
+    GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE)
+    GENERATE_FIELD(NOT_EOP, bool)
+    GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX)
+    GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_FIELD(NUM_INDICES, uint)
+END_REGISTER(VGT_DRAW_INITIATOR)
+
+START_REGISTER(VGT_EVENT_INITIATOR)
+    GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE)
+END_REGISTER(VGT_EVENT_INITIATOR)
+
+START_REGISTER(VGT_DMA_BASE)
+    GENERATE_FIELD(BASE_ADDR, uint)
+END_REGISTER(VGT_DMA_BASE)
+
+START_REGISTER(VGT_DMA_SIZE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+    GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE)
+END_REGISTER(VGT_DMA_SIZE)
+
+START_REGISTER(VGT_BIN_BASE)
+    GENERATE_FIELD(BIN_BASE_ADDR, uint)
+END_REGISTER(VGT_BIN_BASE)
+
+START_REGISTER(VGT_BIN_SIZE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+END_REGISTER(VGT_BIN_SIZE)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+    GENERATE_FIELD(COLUMN, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(GUARD_BAND, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+    GENERATE_FIELD(COLUMN, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(GUARD_BAND, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+
+START_REGISTER(VGT_IMMED_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_IMMED_DATA)
+
+START_REGISTER(VGT_MAX_VTX_INDX)
+    GENERATE_FIELD(MAX_INDX, int)
+END_REGISTER(VGT_MAX_VTX_INDX)
+
+START_REGISTER(VGT_MIN_VTX_INDX)
+    GENERATE_FIELD(MIN_INDX, int)
+END_REGISTER(VGT_MIN_VTX_INDX)
+
+START_REGISTER(VGT_INDX_OFFSET)
+    GENERATE_FIELD(INDX_OFFSET, int)
+END_REGISTER(VGT_INDX_OFFSET)
+
+START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+    GENERATE_FIELD(VTX_REUSE_DEPTH, int)
+END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+
+START_REGISTER(VGT_OUT_DEALLOC_CNTL)
+    GENERATE_FIELD(DEALLOC_DIST, int)
+END_REGISTER(VGT_OUT_DEALLOC_CNTL)
+
+START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+    GENERATE_FIELD(RESET_INDX, int)
+END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+
+START_REGISTER(VGT_ENHANCE)
+    GENERATE_FIELD(MISC, hex)
+END_REGISTER(VGT_ENHANCE)
+
+START_REGISTER(VGT_VTX_VECT_EJECT_REG)
+    GENERATE_FIELD(PRIM_COUNT, int)
+END_REGISTER(VGT_VTX_VECT_EJECT_REG)
+
+START_REGISTER(VGT_LAST_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+    GENERATE_FIELD(DST_STATE_ID, int)
+END_REGISTER(VGT_LAST_COPY_STATE)
+
+START_REGISTER(VGT_DEBUG_CNTL)
+    GENERATE_FIELD(VGT_DEBUG_INDX, int)
+END_REGISTER(VGT_DEBUG_CNTL)
+
+START_REGISTER(VGT_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_DEBUG_DATA)
+
+START_REGISTER(VGT_CNTL_STATUS)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_REQ_BUSY, int)
+    GENERATE_FIELD(VGT_GRP_BUSY, int)
+    GENERATE_FIELD(VGT_VR_BUSY, int)
+    GENERATE_FIELD(VGT_BIN_BUSY, int)
+    GENERATE_FIELD(VGT_PT_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_INDX_BUSY, int)
+END_REGISTER(VGT_CNTL_STATUS)
+
+START_REGISTER(VGT_CRC_SQ_DATA)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_DATA)
+
+START_REGISTER(VGT_CRC_SQ_CTRL)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_CTRL)
+
+START_REGISTER(VGT_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER0_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER1_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER2_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER3_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_HI)
+
+START_REGISTER(VGT_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_HI)
+
+START_REGISTER(VGT_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_HI)
+
+START_REGISTER(VGT_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_HI)
+
+START_REGISTER(TC_CNTL_STATUS)
+    GENERATE_FIELD(L2_INVALIDATE, int)
+    GENERATE_FIELD(TC_L2_HIT_MISS, int)
+    GENERATE_FIELD(TC_BUSY, int)
+END_REGISTER(TC_CNTL_STATUS)
+
+START_REGISTER(TCR_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCR_CHICKEN)
+
+START_REGISTER(TCF_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCF_CHICKEN)
+
+START_REGISTER(TCM_CHICKEN)
+    GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int)
+    GENERATE_FIELD(ETC_COLOR_ENDIAN, int)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCM_CHICKEN)
+
+START_REGISTER(TCR_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER0_HI)
+
+START_REGISTER(TCR_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER1_HI)
+
+START_REGISTER(TCR_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCR_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER1_LOW)
+
+START_REGISTER(TP_TC_CLKGATE_CNTL)
+    GENERATE_FIELD(TP_BUSY_EXTEND, int)
+    GENERATE_FIELD(TC_BUSY_EXTEND, int)
+END_REGISTER(TP_TC_CLKGATE_CNTL)
+
+START_REGISTER(TPC_CNTL_STATUS)
+    GENERATE_FIELD(TPC_INPUT_BUSY, int)
+    GENERATE_FIELD(TPC_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TPC_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_BUSY, int)
+    GENERATE_FIELD(TF_TW_RTS, int)
+    GENERATE_FIELD(TF_TW_STATE_RTS, int)
+    GENERATE_FIELD(TF_TW_RTR, int)
+    GENERATE_FIELD(TW_TA_RTS, int)
+    GENERATE_FIELD(TW_TA_TT_RTS, int)
+    GENERATE_FIELD(TW_TA_LAST_RTS, int)
+    GENERATE_FIELD(TW_TA_RTR, int)
+    GENERATE_FIELD(TA_TB_RTS, int)
+    GENERATE_FIELD(TA_TB_TT_RTS, int)
+    GENERATE_FIELD(TA_TB_RTR, int)
+    GENERATE_FIELD(TA_TF_RTS, int)
+    GENERATE_FIELD(TA_TF_TC_FIFO_REN, int)
+    GENERATE_FIELD(TP_SQ_DEC, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+END_REGISTER(TPC_CNTL_STATUS)
+
+START_REGISTER(TPC_DEBUG0)
+    GENERATE_FIELD(LOD_CNTL, int)
+    GENERATE_FIELD(IC_CTR, int)
+    GENERATE_FIELD(WALKER_CNTL, int)
+    GENERATE_FIELD(ALIGNER_CNTL, int)
+    GENERATE_FIELD(PREV_TC_STATE_VALID, int)
+    GENERATE_FIELD(WALKER_STATE, int)
+    GENERATE_FIELD(ALIGNER_STATE, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(TPC_CLK_EN, int)
+    GENERATE_FIELD(SQ_TP_WAKEUP, int)
+END_REGISTER(TPC_DEBUG0)
+
+START_REGISTER(TPC_DEBUG1)
+    GENERATE_FIELD(UNUSED, int)
+END_REGISTER(TPC_DEBUG1)
+
+START_REGISTER(TPC_CHICKEN)
+    GENERATE_FIELD(BLEND_PRECISION, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(TPC_CHICKEN)
+
+START_REGISTER(TP0_CNTL_STATUS)
+    GENERATE_FIELD(TP_INPUT_BUSY, int)
+    GENERATE_FIELD(TP_LOD_BUSY, int)
+    GENERATE_FIELD(TP_LOD_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ADDR_BUSY, int)
+    GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TP_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_FETCH_BUSY, int)
+    GENERATE_FIELD(TP_CH_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_TT_BUSY, int)
+    GENERATE_FIELD(TP_HICOLOR_BUSY, int)
+    GENERATE_FIELD(TP_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_OUTPUT_BUSY, int)
+    GENERATE_FIELD(IN_LC_RTS, int)
+    GENERATE_FIELD(LC_LA_RTS, int)
+    GENERATE_FIELD(LA_FL_RTS, int)
+    GENERATE_FIELD(FL_TA_RTS, int)
+    GENERATE_FIELD(TA_FA_RTS, int)
+    GENERATE_FIELD(TA_FA_TT_RTS, int)
+    GENERATE_FIELD(FA_AL_RTS, int)
+    GENERATE_FIELD(FA_AL_TT_RTS, int)
+    GENERATE_FIELD(AL_TF_RTS, int)
+    GENERATE_FIELD(AL_TF_TT_RTS, int)
+    GENERATE_FIELD(TF_TB_RTS, int)
+    GENERATE_FIELD(TF_TB_TT_RTS, int)
+    GENERATE_FIELD(TB_TT_RTS, int)
+    GENERATE_FIELD(TB_TT_TT_RESET, int)
+    GENERATE_FIELD(TB_TO_RTS, int)
+    GENERATE_FIELD(TP_BUSY, int)
+END_REGISTER(TP0_CNTL_STATUS)
+
+START_REGISTER(TP0_DEBUG)
+    GENERATE_FIELD(Q_LOD_CNTL, int)
+    GENERATE_FIELD(Q_SQ_TP_WAKEUP, int)
+    GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(PERF_CLK_EN, int)
+    GENERATE_FIELD(TP_CLK_EN, int)
+    GENERATE_FIELD(Q_WALKER_CNTL, int)
+    GENERATE_FIELD(Q_ALIGNER_CNTL, int)
+END_REGISTER(TP0_DEBUG)
+
+START_REGISTER(TP0_CHICKEN)
+    GENERATE_FIELD(TT_MODE, int)
+    GENERATE_FIELD(VFETCH_ADDRESS_MODE, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(TP0_CHICKEN)
+
+START_REGISTER(TP0_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT)
+END_REGISTER(TP0_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER0_HI)
+
+START_REGISTER(TP0_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER0_LOW)
+
+START_REGISTER(TP0_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, int)
+END_REGISTER(TP0_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER1_HI)
+
+START_REGISTER(TP0_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER0_HI)
+
+START_REGISTER(TCM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER1_HI)
+
+START_REGISTER(TCM_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER2_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER3_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER4_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER4_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER5_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER5_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER6_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER6_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER7_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER7_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER8_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER8_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER9_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER9_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER10_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER10_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER11_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER11_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER0_HI)
+
+START_REGISTER(TCF_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER1_HI)
+
+START_REGISTER(TCF_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER2_HI)
+
+START_REGISTER(TCF_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER3_HI)
+
+START_REGISTER(TCF_PERFCOUNTER4_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER4_HI)
+
+START_REGISTER(TCF_PERFCOUNTER5_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER5_HI)
+
+START_REGISTER(TCF_PERFCOUNTER6_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER6_HI)
+
+START_REGISTER(TCF_PERFCOUNTER7_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER7_HI)
+
+START_REGISTER(TCF_PERFCOUNTER8_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER8_HI)
+
+START_REGISTER(TCF_PERFCOUNTER9_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER9_HI)
+
+START_REGISTER(TCF_PERFCOUNTER10_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER10_HI)
+
+START_REGISTER(TCF_PERFCOUNTER11_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER11_HI)
+
+START_REGISTER(TCF_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER2_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER3_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER4_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER4_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER5_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER5_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER6_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER6_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER7_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER7_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER8_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER8_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER9_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER9_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER10_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER10_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER11_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER11_LOW)
+
+START_REGISTER(TCF_DEBUG)
+    GENERATE_FIELD(not_MH_TC_rtr, int)
+    GENERATE_FIELD(TC_MH_send, int)
+    GENERATE_FIELD(not_FG0_rtr, int)
+    GENERATE_FIELD(not_TCB_TCO_rtr, int)
+    GENERATE_FIELD(TCB_ff_stall, int)
+    GENERATE_FIELD(TCB_miss_stall, int)
+    GENERATE_FIELD(TCA_TCB_stall, int)
+    GENERATE_FIELD(PF0_stall, int)
+    GENERATE_FIELD(TP0_full, int)
+    GENERATE_FIELD(TPC_full, int)
+    GENERATE_FIELD(not_TPC_rtr, int)
+    GENERATE_FIELD(tca_state_rts, int)
+    GENERATE_FIELD(tca_rts, int)
+END_REGISTER(TCF_DEBUG)
+
+START_REGISTER(TCA_FIFO_DEBUG)
+    GENERATE_FIELD(tp0_full, int)
+    GENERATE_FIELD(tpc_full, int)
+    GENERATE_FIELD(load_tpc_fifo, int)
+    GENERATE_FIELD(load_tp_fifos, int)
+    GENERATE_FIELD(FW_full, int)
+    GENERATE_FIELD(not_FW_rtr0, int)
+    GENERATE_FIELD(FW_rts0, int)
+    GENERATE_FIELD(not_FW_tpc_rtr, int)
+    GENERATE_FIELD(FW_tpc_rts, int)
+END_REGISTER(TCA_FIFO_DEBUG)
+
+START_REGISTER(TCA_PROBE_DEBUG)
+    GENERATE_FIELD(ProbeFilter_stall, int)
+END_REGISTER(TCA_PROBE_DEBUG)
+
+START_REGISTER(TCA_TPC_DEBUG)
+    GENERATE_FIELD(captue_state_rts, int)
+    GENERATE_FIELD(capture_tca_rts, int)
+END_REGISTER(TCA_TPC_DEBUG)
+
+START_REGISTER(TCB_CORE_DEBUG)
+    GENERATE_FIELD(access512, int)
+    GENERATE_FIELD(tiled, int)
+    GENERATE_FIELD(opcode, int)
+    GENERATE_FIELD(format, int)
+    GENERATE_FIELD(sector_format, int)
+    GENERATE_FIELD(sector_format512, int)
+END_REGISTER(TCB_CORE_DEBUG)
+
+START_REGISTER(TCB_TAG0_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG0_DEBUG)
+
+START_REGISTER(TCB_TAG1_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG1_DEBUG)
+
+START_REGISTER(TCB_TAG2_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG2_DEBUG)
+
+START_REGISTER(TCB_TAG3_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG3_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+    GENERATE_FIELD(left_done, int)
+    GENERATE_FIELD(fg0_sends_left, int)
+    GENERATE_FIELD(one_sector_to_go_left_q, int)
+    GENERATE_FIELD(no_sectors_to_go, int)
+    GENERATE_FIELD(update_left, int)
+    GENERATE_FIELD(sector_mask_left_count_q, int)
+    GENERATE_FIELD(sector_mask_left_q, int)
+    GENERATE_FIELD(valid_left_q, int)
+END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+    GENERATE_FIELD(quad_sel_left, int)
+    GENERATE_FIELD(set_sel_left, int)
+    GENERATE_FIELD(right_eq_left, int)
+    GENERATE_FIELD(ff_fg_type512, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(setquads_to_send, int)
+END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+    GENERATE_FIELD(tc0_arb_rts, int)
+    GENERATE_FIELD(ga_out_rts, int)
+    GENERATE_FIELD(tc_arb_format, int)
+    GENERATE_FIELD(tc_arb_fmsopcode, int)
+    GENERATE_FIELD(tc_arb_request_type, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(fgo_busy, int)
+    GENERATE_FIELD(ga_busy, int)
+    GENERATE_FIELD(mc_sel_q, int)
+    GENERATE_FIELD(valid_q, int)
+    GENERATE_FIELD(arb_RTR, int)
+END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+
+START_REGISTER(TCD_INPUT0_DEBUG)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(valid_q1, int)
+    GENERATE_FIELD(cnt_q1, int)
+    GENERATE_FIELD(last_send_q1, int)
+    GENERATE_FIELD(ip_send, int)
+    GENERATE_FIELD(ipbuf_dxt_send, int)
+    GENERATE_FIELD(ipbuf_busy, int)
+END_REGISTER(TCD_INPUT0_DEBUG)
+
+START_REGISTER(TCD_DEGAMMA_DEBUG)
+    GENERATE_FIELD(dgmm_ftfconv_dgmmen, int)
+    GENERATE_FIELD(dgmm_ctrl_dgmm8, int)
+    GENERATE_FIELD(dgmm_ctrl_last_send, int)
+    GENERATE_FIELD(dgmm_ctrl_send, int)
+    GENERATE_FIELD(dgmm_stall, int)
+    GENERATE_FIELD(dgmm_pstate, int)
+END_REGISTER(TCD_DEGAMMA_DEBUG)
+
+START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(sctrmx_rtr, int)
+    GENERATE_FIELD(dxtc_rtr, int)
+    GENERATE_FIELD(sctrarb_multcyl_send, int)
+    GENERATE_FIELD(sctrmx0_sctrarb_rts, int)
+    GENERATE_FIELD(dxtc_sctrarb_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_last_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_send, int)
+    GENERATE_FIELD(dcmp_mux_send, int)
+END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+
+START_REGISTER(TCD_DXTC_ARB_DEBUG)
+    GENERATE_FIELD(n0_stall, int)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(arb_dcmp01_last_send, int)
+    GENERATE_FIELD(arb_dcmp01_cnt, int)
+    GENERATE_FIELD(arb_dcmp01_sector, int)
+    GENERATE_FIELD(arb_dcmp01_cacheline, int)
+    GENERATE_FIELD(arb_dcmp01_format, int)
+    GENERATE_FIELD(arb_dcmp01_send, int)
+    GENERATE_FIELD(n0_dxt2_4_types, int)
+END_REGISTER(TCD_DXTC_ARB_DEBUG)
+
+START_REGISTER(TCD_STALLS_DEBUG)
+    GENERATE_FIELD(not_multcyl_sctrarb_rtr, int)
+    GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int)
+    GENERATE_FIELD(not_dcmp0_arb_rtr, int)
+    GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int)
+    GENERATE_FIELD(not_mux_dcmp_rtr, int)
+    GENERATE_FIELD(not_incoming_rtr, int)
+END_REGISTER(TCD_STALLS_DEBUG)
+
+START_REGISTER(TCO_STALLS_DEBUG)
+    GENERATE_FIELD(quad0_sg_crd_RTR, int)
+    GENERATE_FIELD(quad0_rl_sg_RTR, int)
+    GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int)
+END_REGISTER(TCO_STALLS_DEBUG)
+
+START_REGISTER(TCO_QUAD0_DEBUG0)
+    GENERATE_FIELD(rl_sg_sector_format, int)
+    GENERATE_FIELD(rl_sg_end_of_sample, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(sg_crd_end_of_sample, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(stageN1_valid_q, int)
+    GENERATE_FIELD(read_cache_q, int)
+    GENERATE_FIELD(cache_read_RTR, int)
+    GENERATE_FIELD(all_sectors_written_set3, int)
+    GENERATE_FIELD(all_sectors_written_set2, int)
+    GENERATE_FIELD(all_sectors_written_set1, int)
+    GENERATE_FIELD(all_sectors_written_set0, int)
+    GENERATE_FIELD(busy, int)
+END_REGISTER(TCO_QUAD0_DEBUG0)
+
+START_REGISTER(TCO_QUAD0_DEBUG1)
+    GENERATE_FIELD(fifo_busy, int)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(write_enable, int)
+    GENERATE_FIELD(fifo_write_ptr, int)
+    GENERATE_FIELD(fifo_read_ptr, int)
+    GENERATE_FIELD(cache_read_busy, int)
+    GENERATE_FIELD(latency_fifo_busy, int)
+    GENERATE_FIELD(input_quad_busy, int)
+    GENERATE_FIELD(tco_quad_pipe_busy, int)
+    GENERATE_FIELD(TCB_TCO_rtr_d, int)
+    GENERATE_FIELD(TCB_TCO_xfc_q, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(TCO_TCB_read_xfc, int)
+END_REGISTER(TCO_QUAD0_DEBUG1)
+
+START_REGISTER(SQ_GPR_MANAGEMENT)
+    GENERATE_FIELD(REG_DYNAMIC, int)
+    GENERATE_FIELD(REG_SIZE_PIX, int)
+    GENERATE_FIELD(REG_SIZE_VTX, int)
+END_REGISTER(SQ_GPR_MANAGEMENT)
+
+START_REGISTER(SQ_FLOW_CONTROL)
+    GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(ONE_THREAD, int)
+    GENERATE_FIELD(ONE_ALU, int)
+    GENERATE_FIELD(CF_WR_BASE, hex)
+    GENERATE_FIELD(NO_PV_PS, int)
+    GENERATE_FIELD(NO_LOOP_EXIT, int)
+    GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int)
+    GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(VC_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(ALU_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(NO_ARB_EJECT, int)
+    GENERATE_FIELD(NO_CFS_EJECT, int)
+    GENERATE_FIELD(POS_EXP_PRIORITY, int)
+    GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int)
+    GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int)
+END_REGISTER(SQ_FLOW_CONTROL)
+
+START_REGISTER(SQ_INST_STORE_MANAGMENT)
+    GENERATE_FIELD(INST_BASE_PIX, int)
+    GENERATE_FIELD(INST_BASE_VTX, int)
+END_REGISTER(SQ_INST_STORE_MANAGMENT)
+
+START_REGISTER(SQ_RESOURCE_MANAGMENT)
+    GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(EXPORT_BUF_ENTRIES, int)
+END_REGISTER(SQ_RESOURCE_MANAGMENT)
+
+START_REGISTER(SQ_EO_RT)
+    GENERATE_FIELD(EO_CONSTANTS_RT, int)
+    GENERATE_FIELD(EO_TSTATE_RT, int)
+END_REGISTER(SQ_EO_RT)
+
+START_REGISTER(SQ_DEBUG_MISC)
+    GENERATE_FIELD(DB_ALUCST_SIZE, int)
+    GENERATE_FIELD(DB_TSTATE_SIZE, int)
+    GENERATE_FIELD(DB_READ_CTX, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DB_READ_MEMORY, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_0, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_1, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_2, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_3, int)
+END_REGISTER(SQ_DEBUG_MISC)
+
+START_REGISTER(SQ_ACTIVITY_METER_CNTL)
+    GENERATE_FIELD(TIMEBASE, int)
+    GENERATE_FIELD(THRESHOLD_LOW, int)
+    GENERATE_FIELD(THRESHOLD_HIGH, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(SQ_ACTIVITY_METER_CNTL)
+
+START_REGISTER(SQ_ACTIVITY_METER_STATUS)
+    GENERATE_FIELD(PERCENT_BUSY, int)
+END_REGISTER(SQ_ACTIVITY_METER_STATUS)
+
+START_REGISTER(SQ_INPUT_ARB_PRIORITY)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(THRESHOLD, int)
+END_REGISTER(SQ_INPUT_ARB_PRIORITY)
+
+START_REGISTER(SQ_THREAD_ARB_PRIORITY)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(THRESHOLD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int)
+END_REGISTER(SQ_THREAD_ARB_PRIORITY)
+
+START_REGISTER(SQ_DEBUG_INPUT_FSM)
+    GENERATE_FIELD(VC_VSR_LD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VC_GPR_LD, int)
+    GENERATE_FIELD(PC_PISM, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PC_AS, int)
+    GENERATE_FIELD(PC_INTERP_CNT, int)
+    GENERATE_FIELD(PC_GPR_SIZE, int)
+END_REGISTER(SQ_DEBUG_INPUT_FSM)
+
+START_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+    GENERATE_FIELD(TEX_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(ALU_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(ALU_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(TEX_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int)
+END_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+
+START_REGISTER(SQ_DEBUG_TP_FSM)
+    GENERATE_FIELD(EX_TP, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_TP, int)
+    GENERATE_FIELD(IF_TP, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(TIS_TP, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(GS_TP, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(FCR_TP, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(FCS_TP, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_TP, int)
+END_REGISTER(SQ_DEBUG_TP_FSM)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_0)
+    GENERATE_FIELD(EX_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_0)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_1)
+    GENERATE_FIELD(EX_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_1)
+
+START_REGISTER(SQ_DEBUG_EXP_ALLOC)
+    GENERATE_FIELD(POS_BUF_AVAIL, int)
+    GENERATE_FIELD(COLOR_BUF_AVAIL, int)
+    GENERATE_FIELD(EA_BUF_AVAIL, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int)
+END_REGISTER(SQ_DEBUG_EXP_ALLOC)
+
+START_REGISTER(SQ_DEBUG_PTR_BUFF)
+    GENERATE_FIELD(END_OF_BUFFER, int)
+    GENERATE_FIELD(DEALLOC_CNT, int)
+    GENERATE_FIELD(QUAL_NEW_VECTOR, int)
+    GENERATE_FIELD(EVENT_CONTEXT_ID, int)
+    GENERATE_FIELD(SC_EVENT_ID, int)
+    GENERATE_FIELD(QUAL_EVENT, int)
+    GENERATE_FIELD(PRIM_TYPE_POLYGON, int)
+    GENERATE_FIELD(EF_EMPTY, int)
+    GENERATE_FIELD(VTX_SYNC_CNT, int)
+END_REGISTER(SQ_DEBUG_PTR_BUFF)
+
+START_REGISTER(SQ_DEBUG_GPR_VTX)
+    GENERATE_FIELD(VTX_TAIL_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VTX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(VTX_MAX, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(VTX_FREE, int)
+END_REGISTER(SQ_DEBUG_GPR_VTX)
+
+START_REGISTER(SQ_DEBUG_GPR_PIX)
+    GENERATE_FIELD(PIX_TAIL_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PIX_MAX, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(PIX_FREE, int)
+END_REGISTER(SQ_DEBUG_GPR_PIX)
+
+START_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+    GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VC_THREAD_BUF_DLY, int)
+    GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int)
+END_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_0)
+    GENERATE_FIELD(VTX_HEAD_PTR_Q, int)
+    GENERATE_FIELD(TAIL_PTR_Q, int)
+    GENERATE_FIELD(FULL_CNT_Q, int)
+    GENERATE_FIELD(NXT_POS_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_PC_ALLOC_CNT, int)
+    GENERATE_FIELD(SX_EVENT_FULL, int)
+    GENERATE_FIELD(BUSY_Q, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_0)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_1)
+    GENERATE_FIELD(VS_DONE_PTR, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_1)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+    GENERATE_FIELD(VS_STATUS_REG, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+    GENERATE_FIELD(VS_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_0)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(TAIL_PTR, int)
+    GENERATE_FIELD(FULL_CNT, int)
+    GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_PIX_EXP_CNT, int)
+    GENERATE_FIELD(BUSY, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_0, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_1, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_2, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_3, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+    GENERATE_FIELD(PIX_TB_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+
+START_REGISTER(SQ_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT)
+END_REGISTER(SQ_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER1_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER2_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER3_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_HI)
+
+START_REGISTER(SQ_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_HI)
+
+START_REGISTER(SQ_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_HI)
+
+START_REGISTER(SX_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT)
+END_REGISTER(SX_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SX_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_LOW)
+
+START_REGISTER(SX_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_0)
+    GENERATE_FIELD(VECTOR_RESULT, int)
+    GENERATE_FIELD(CST_0_ABS_MOD, Abs_modifier)
+    GENERATE_FIELD(LOW_PRECISION_16B_FP, int)
+    GENERATE_FIELD(SCALAR_RESULT, int)
+    GENERATE_FIELD(SST_0_ABS_MOD, int)
+    GENERATE_FIELD(EXPORT_DATA, Exporting)
+    GENERATE_FIELD(VECTOR_WRT_MSK, int)
+    GENERATE_FIELD(SCALAR_WRT_MSK, int)
+    GENERATE_FIELD(VECTOR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode)
+END_REGISTER(SQ_INSTRUCTION_ALU_0)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_1)
+    GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier)
+    GENERATE_FIELD(PRED_SELECT, PredicateSelect)
+    GENERATE_FIELD(RELATIVE_ADDR, int)
+    GENERATE_FIELD(CONST_1_REL_ABS, int)
+    GENERATE_FIELD(CONST_0_REL_ABS, int)
+END_REGISTER(SQ_INSTRUCTION_ALU_1)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_2)
+    GENERATE_FIELD(SRC_C_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_C, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier)
+    GENERATE_FIELD(SRC_B_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_B, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier)
+    GENERATE_FIELD(SRC_A_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_A, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier)
+    GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode)
+    GENERATE_FIELD(SRC_C_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_B_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_A_SEL, OperandSelect0)
+END_REGISTER(SQ_INSTRUCTION_ALU_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(YIELD, int)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(YIELD, int)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(PREDICATED_JMP, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(RESERVED_2, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+    GENERATE_FIELD(OPCODE, TexInstOpcode)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, Addressmode)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(DST_GPR_AM, Addressmode)
+    GENERATE_FIELD(FETCH_VALID_ONLY, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm)
+    GENERATE_FIELD(SRC_SEL_X, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Y, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Z, SrcSel)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+    GENERATE_FIELD(DST_SEL_X, DstSel)
+    GENERATE_FIELD(DST_SEL_Y, DstSel)
+    GENERATE_FIELD(DST_SEL_Z, DstSel)
+    GENERATE_FIELD(DST_SEL_W, DstSel)
+    GENERATE_FIELD(MAG_FILTER, MagFilter)
+    GENERATE_FIELD(MIN_FILTER, MinFilter)
+    GENERATE_FIELD(MIP_FILTER, MipFilter)
+    GENERATE_FIELD(ANISO_FILTER, AnisoFilter)
+    GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter)
+    GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter)
+    GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter)
+    GENERATE_FIELD(USE_COMP_LOD, int)
+    GENERATE_FIELD(USE_REG_LOD, int)
+    GENERATE_FIELD(PRED_SELECT, PredSelect)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+    GENERATE_FIELD(USE_REG_GRADIENTS, int)
+    GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation)
+    GENERATE_FIELD(LOD_BIAS, int)
+    GENERATE_FIELD(UNUSED, int)
+    GENERATE_FIELD(OFFSET_X, int)
+    GENERATE_FIELD(OFFSET_Y, int)
+    GENERATE_FIELD(OFFSET_Z, int)
+    GENERATE_FIELD(PRED_CONDITION, int)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+    GENERATE_FIELD(OPCODE, int)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, int)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(DST_GPR_AM, int)
+    GENERATE_FIELD(MUST_BE_ONE, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(CONST_INDEX_SEL, int)
+    GENERATE_FIELD(SRC_SEL, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+    GENERATE_FIELD(DST_SEL_X, int)
+    GENERATE_FIELD(DST_SEL_Y, int)
+    GENERATE_FIELD(DST_SEL_Z, int)
+    GENERATE_FIELD(DST_SEL_W, int)
+    GENERATE_FIELD(FORMAT_COMP_ALL, int)
+    GENERATE_FIELD(NUM_FORMAT_ALL, int)
+    GENERATE_FIELD(SIGNED_RF_MODE_ALL, int)
+    GENERATE_FIELD(DATA_FORMAT, int)
+    GENERATE_FIELD(EXP_ADJUST_ALL, int)
+    GENERATE_FIELD(PRED_SELECT, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+    GENERATE_FIELD(STRIDE, int)
+    GENERATE_FIELD(OFFSET, int)
+    GENERATE_FIELD(PRED_CONDITION, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+
+START_REGISTER(SQ_CONSTANT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_0)
+
+START_REGISTER(SQ_CONSTANT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_1)
+
+START_REGISTER(SQ_CONSTANT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_2)
+
+START_REGISTER(SQ_CONSTANT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_3)
+
+START_REGISTER(SQ_FETCH_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_0)
+
+START_REGISTER(SQ_FETCH_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_1)
+
+START_REGISTER(SQ_FETCH_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_2)
+
+START_REGISTER(SQ_FETCH_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_3)
+
+START_REGISTER(SQ_FETCH_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_4)
+
+START_REGISTER(SQ_FETCH_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_5)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_0)
+    GENERATE_FIELD(TYPE, int)
+    GENERATE_FIELD(STATE, int)
+    GENERATE_FIELD(BASE_ADDRESS, hex)
+END_REGISTER(SQ_CONSTANT_VFETCH_0)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_1)
+    GENERATE_FIELD(ENDIAN_SWAP, int)
+    GENERATE_FIELD(LIMIT_ADDRESS, hex)
+END_REGISTER(SQ_CONSTANT_VFETCH_1)
+
+START_REGISTER(SQ_CONSTANT_T2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T2)
+
+START_REGISTER(SQ_CONSTANT_T3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T3)
+
+START_REGISTER(SQ_CF_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+END_REGISTER(SQ_CF_BOOLEANS)
+
+START_REGISTER(SQ_CF_LOOP)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+END_REGISTER(SQ_CF_LOOP)
+
+START_REGISTER(SQ_CONSTANT_RT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_RT_0)
+
+START_REGISTER(SQ_CONSTANT_RT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_RT_1)
+
+START_REGISTER(SQ_CONSTANT_RT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_RT_2)
+
+START_REGISTER(SQ_CONSTANT_RT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_0)
+
+START_REGISTER(SQ_FETCH_RT_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_1)
+
+START_REGISTER(SQ_FETCH_RT_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_2)
+
+START_REGISTER(SQ_FETCH_RT_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_4)
+
+START_REGISTER(SQ_FETCH_RT_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_5)
+
+START_REGISTER(SQ_CF_RT_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+END_REGISTER(SQ_CF_RT_BOOLEANS)
+
+START_REGISTER(SQ_CF_RT_LOOP)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+END_REGISTER(SQ_CF_RT_LOOP)
+
+START_REGISTER(SQ_VS_PROGRAM)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_VS_PROGRAM)
+
+START_REGISTER(SQ_PS_PROGRAM)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_PS_PROGRAM)
+
+START_REGISTER(SQ_CF_PROGRAM_SIZE)
+    GENERATE_FIELD(VS_CF_SIZE, int)
+    GENERATE_FIELD(PS_CF_SIZE, int)
+END_REGISTER(SQ_CF_PROGRAM_SIZE)
+
+START_REGISTER(SQ_INTERPOLATOR_CNTL)
+    GENERATE_FIELD(PARAM_SHADE, ParamShade)
+    GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern)
+END_REGISTER(SQ_INTERPOLATOR_CNTL)
+
+START_REGISTER(SQ_PROGRAM_CNTL)
+    GENERATE_FIELD(VS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(PS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(VS_RESOURCE, int)
+    GENERATE_FIELD(PS_RESOURCE, int)
+    GENERATE_FIELD(PARAM_GEN, int)
+    GENERATE_FIELD(GEN_INDEX_PIX, int)
+    GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne)
+    GENERATE_FIELD(VS_EXPORT_MODE, VertexMode)
+    GENERATE_FIELD(PS_EXPORT_MODE, int)
+    GENERATE_FIELD(GEN_INDEX_VTX, int)
+END_REGISTER(SQ_PROGRAM_CNTL)
+
+START_REGISTER(SQ_WRAPPING_0)
+    GENERATE_FIELD(PARAM_WRAP_0, hex)
+    GENERATE_FIELD(PARAM_WRAP_1, hex)
+    GENERATE_FIELD(PARAM_WRAP_2, hex)
+    GENERATE_FIELD(PARAM_WRAP_3, hex)
+    GENERATE_FIELD(PARAM_WRAP_4, hex)
+    GENERATE_FIELD(PARAM_WRAP_5, hex)
+    GENERATE_FIELD(PARAM_WRAP_6, hex)
+    GENERATE_FIELD(PARAM_WRAP_7, hex)
+END_REGISTER(SQ_WRAPPING_0)
+
+START_REGISTER(SQ_WRAPPING_1)
+    GENERATE_FIELD(PARAM_WRAP_8, hex)
+    GENERATE_FIELD(PARAM_WRAP_9, hex)
+    GENERATE_FIELD(PARAM_WRAP_10, hex)
+    GENERATE_FIELD(PARAM_WRAP_11, hex)
+    GENERATE_FIELD(PARAM_WRAP_12, hex)
+    GENERATE_FIELD(PARAM_WRAP_13, hex)
+    GENERATE_FIELD(PARAM_WRAP_14, hex)
+    GENERATE_FIELD(PARAM_WRAP_15, hex)
+END_REGISTER(SQ_WRAPPING_1)
+
+START_REGISTER(SQ_VS_CONST)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_VS_CONST)
+
+START_REGISTER(SQ_PS_CONST)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_PS_CONST)
+
+START_REGISTER(SQ_CONTEXT_MISC)
+    GENERATE_FIELD(INST_PRED_OPTIMIZE, int)
+    GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int)
+    GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl)
+    GENERATE_FIELD(PARAM_GEN_POS, int)
+    GENERATE_FIELD(PERFCOUNTER_REF, int)
+    GENERATE_FIELD(YEILD_OPTIMIZE, int)
+    GENERATE_FIELD(TX_CACHE_SEL, int)
+END_REGISTER(SQ_CONTEXT_MISC)
+
+START_REGISTER(SQ_CF_RD_BASE)
+    GENERATE_FIELD(RD_BASE, hex)
+END_REGISTER(SQ_CF_RD_BASE)
+
+START_REGISTER(SQ_DEBUG_MISC_0)
+    GENERATE_FIELD(DB_PROB_ON, int)
+    GENERATE_FIELD(DB_PROB_BREAK, int)
+    GENERATE_FIELD(DB_PROB_ADDR, int)
+    GENERATE_FIELD(DB_PROB_COUNT, int)
+END_REGISTER(SQ_DEBUG_MISC_0)
+
+START_REGISTER(SQ_DEBUG_MISC_1)
+    GENERATE_FIELD(DB_ON_PIX, int)
+    GENERATE_FIELD(DB_ON_VTX, int)
+    GENERATE_FIELD(DB_INST_COUNT, int)
+    GENERATE_FIELD(DB_BREAK_ADDR, int)
+END_REGISTER(SQ_DEBUG_MISC_1)
+
+START_REGISTER(MH_ARBITER_CONFIG)
+    GENERATE_FIELD(SAME_PAGE_LIMIT, int)
+    GENERATE_FIELD(SAME_PAGE_GRANULARITY, int)
+    GENERATE_FIELD(L1_ARB_ENABLE, bool)
+    GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int)
+    GENERATE_FIELD(L2_ARB_CONTROL, int)
+    GENERATE_FIELD(PAGE_SIZE, int)
+    GENERATE_FIELD(TC_REORDER_ENABLE, bool)
+    GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT, int)
+    GENERATE_FIELD(CP_CLNT_ENABLE, bool)
+    GENERATE_FIELD(VGT_CLNT_ENABLE, bool)
+    GENERATE_FIELD(TC_CLNT_ENABLE, bool)
+    GENERATE_FIELD(RB_CLNT_ENABLE, bool)
+END_REGISTER(MH_ARBITER_CONFIG)
+
+START_REGISTER(MH_CLNT_AXI_ID_REUSE)
+    GENERATE_FIELD(CPw_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(RBw_ID, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(MMUr_ID, int)
+END_REGISTER(MH_CLNT_AXI_ID_REUSE)
+
+START_REGISTER(MH_INTERRUPT_MASK)
+    GENERATE_FIELD(AXI_READ_ERROR, bool)
+    GENERATE_FIELD(AXI_WRITE_ERROR, bool)
+    GENERATE_FIELD(MMU_PAGE_FAULT, bool)
+END_REGISTER(MH_INTERRUPT_MASK)
+
+START_REGISTER(MH_INTERRUPT_STATUS)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+END_REGISTER(MH_INTERRUPT_STATUS)
+
+START_REGISTER(MH_INTERRUPT_CLEAR)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+END_REGISTER(MH_INTERRUPT_CLEAR)
+
+START_REGISTER(MH_AXI_ERROR)
+    GENERATE_FIELD(AXI_READ_ID, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ID, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+END_REGISTER(MH_AXI_ERROR)
+
+START_REGISTER(MH_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER0_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER1_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER0_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER0_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER1_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER1_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER0_LOW)
+
+START_REGISTER(MH_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER1_LOW)
+
+START_REGISTER(MH_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER0_HI)
+
+START_REGISTER(MH_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER1_HI)
+
+START_REGISTER(MH_DEBUG_CTRL)
+    GENERATE_FIELD(INDEX, int)
+END_REGISTER(MH_DEBUG_CTRL)
+
+START_REGISTER(MH_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(MH_DEBUG_DATA)
+
+START_REGISTER(MH_MMU_CONFIG)
+    GENERATE_FIELD(MMU_ENABLE, bool)
+    GENERATE_FIELD(SPLIT_MODE_ENABLE, bool)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh)
+END_REGISTER(MH_MMU_CONFIG)
+
+START_REGISTER(MH_MMU_VA_RANGE)
+    GENERATE_FIELD(NUM_64KB_REGIONS, int)
+    GENERATE_FIELD(VA_BASE, int)
+END_REGISTER(MH_MMU_VA_RANGE)
+
+START_REGISTER(MH_MMU_PT_BASE)
+    GENERATE_FIELD(PT_BASE, int)
+END_REGISTER(MH_MMU_PT_BASE)
+
+START_REGISTER(MH_MMU_PAGE_FAULT)
+    GENERATE_FIELD(PAGE_FAULT, int)
+    GENERATE_FIELD(OP_TYPE, int)
+    GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(AXI_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(READ_PROTECTION_ERROR, int)
+    GENERATE_FIELD(WRITE_PROTECTION_ERROR, int)
+    GENERATE_FIELD(REQ_VA, int)
+END_REGISTER(MH_MMU_PAGE_FAULT)
+
+START_REGISTER(MH_MMU_TRAN_ERROR)
+    GENERATE_FIELD(TRAN_ERROR, int)
+END_REGISTER(MH_MMU_TRAN_ERROR)
+
+START_REGISTER(MH_MMU_INVALIDATE)
+    GENERATE_FIELD(INVALIDATE_ALL, int)
+    GENERATE_FIELD(INVALIDATE_TC, int)
+END_REGISTER(MH_MMU_INVALIDATE)
+
+START_REGISTER(MH_MMU_MPU_BASE)
+    GENERATE_FIELD(MPU_BASE, int)
+END_REGISTER(MH_MMU_MPU_BASE)
+
+START_REGISTER(MH_MMU_MPU_END)
+    GENERATE_FIELD(MPU_END, int)
+END_REGISTER(MH_MMU_MPU_END)
+
+START_REGISTER(WAIT_UNTIL)
+    GENERATE_FIELD(WAIT_RE_VSYNC, int)
+    GENERATE_FIELD(WAIT_FE_VSYNC, int)
+    GENERATE_FIELD(WAIT_VSYNC, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID0, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID1, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID2, int)
+    GENERATE_FIELD(WAIT_CMDFIFO, int)
+    GENERATE_FIELD(WAIT_2D_IDLE, int)
+    GENERATE_FIELD(WAIT_3D_IDLE, int)
+    GENERATE_FIELD(WAIT_2D_IDLECLEAN, int)
+    GENERATE_FIELD(WAIT_3D_IDLECLEAN, int)
+    GENERATE_FIELD(CMDFIFO_ENTRIES, int)
+END_REGISTER(WAIT_UNTIL)
+
+START_REGISTER(RBBM_ISYNC_CNTL)
+    GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int)
+    GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int)
+END_REGISTER(RBBM_ISYNC_CNTL)
+
+START_REGISTER(RBBM_STATUS)
+    GENERATE_FIELD(CMDFIFO_AVAIL, int)
+    GENERATE_FIELD(TC_BUSY, int)
+    GENERATE_FIELD(HIRQ_PENDING, int)
+    GENERATE_FIELD(CPRQ_PENDING, int)
+    GENERATE_FIELD(CFRQ_PENDING, int)
+    GENERATE_FIELD(PFRQ_PENDING, int)
+    GENERATE_FIELD(VGT_BUSY_NO_DMA, int)
+    GENERATE_FIELD(RBBM_WU_BUSY, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(MH_BUSY, int)
+    GENERATE_FIELD(MH_COHERENCY_BUSY, int)
+    GENERATE_FIELD(SX_BUSY, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+    GENERATE_FIELD(SC_CNTX_BUSY, int)
+    GENERATE_FIELD(PA_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX17_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX0_BUSY, int)
+    GENERATE_FIELD(RB_CNTX_BUSY, int)
+    GENERATE_FIELD(GUI_ACTIVE, int)
+END_REGISTER(RBBM_STATUS)
+
+START_REGISTER(RBBM_DSPLY)
+    GENERATE_FIELD(DISPLAY_ID0_ACTIVE, int)
+    GENERATE_FIELD(DISPLAY_ID1_ACTIVE, int)
+    GENERATE_FIELD(DISPLAY_ID2_ACTIVE, int)
+    GENERATE_FIELD(VSYNC_ACTIVE, int)
+    GENERATE_FIELD(USE_DISPLAY_ID0, int)
+    GENERATE_FIELD(USE_DISPLAY_ID1, int)
+    GENERATE_FIELD(USE_DISPLAY_ID2, int)
+    GENERATE_FIELD(SW_CNTL, int)
+    GENERATE_FIELD(NUM_BUFS, int)
+END_REGISTER(RBBM_DSPLY)
+
+START_REGISTER(RBBM_RENDER_LATEST)
+    GENERATE_FIELD(BUFFER_ID, int)
+END_REGISTER(RBBM_RENDER_LATEST)
+
+START_REGISTER(RBBM_RTL_RELEASE)
+    GENERATE_FIELD(CHANGELIST, int)
+END_REGISTER(RBBM_RTL_RELEASE)
+
+START_REGISTER(RBBM_PATCH_RELEASE)
+    GENERATE_FIELD(PATCH_REVISION, int)
+    GENERATE_FIELD(PATCH_SELECTION, int)
+    GENERATE_FIELD(CUSTOMER_ID, int)
+END_REGISTER(RBBM_PATCH_RELEASE)
+
+START_REGISTER(RBBM_AUXILIARY_CONFIG)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(RBBM_AUXILIARY_CONFIG)
+
+START_REGISTER(RBBM_PERIPHID0)
+    GENERATE_FIELD(PARTNUMBER0, int)
+END_REGISTER(RBBM_PERIPHID0)
+
+START_REGISTER(RBBM_PERIPHID1)
+    GENERATE_FIELD(PARTNUMBER1, int)
+    GENERATE_FIELD(DESIGNER0, int)
+END_REGISTER(RBBM_PERIPHID1)
+
+START_REGISTER(RBBM_PERIPHID2)
+    GENERATE_FIELD(DESIGNER1, int)
+    GENERATE_FIELD(REVISION, int)
+END_REGISTER(RBBM_PERIPHID2)
+
+START_REGISTER(RBBM_PERIPHID3)
+    GENERATE_FIELD(RBBM_HOST_INTERFACE, int)
+    GENERATE_FIELD(GARB_SLAVE_INTERFACE, int)
+    GENERATE_FIELD(MH_INTERFACE, int)
+    GENERATE_FIELD(CONTINUATION, int)
+END_REGISTER(RBBM_PERIPHID3)
+
+START_REGISTER(RBBM_CNTL)
+    GENERATE_FIELD(READ_TIMEOUT, int)
+    GENERATE_FIELD(REGCLK_DEASSERT_TIME, int)
+END_REGISTER(RBBM_CNTL)
+
+START_REGISTER(RBBM_SKEW_CNTL)
+    GENERATE_FIELD(SKEW_TOP_THRESHOLD, int)
+    GENERATE_FIELD(SKEW_COUNT, int)
+END_REGISTER(RBBM_SKEW_CNTL)
+
+START_REGISTER(RBBM_SOFT_RESET)
+    GENERATE_FIELD(SOFT_RESET_CP, int)
+    GENERATE_FIELD(SOFT_RESET_PA, int)
+    GENERATE_FIELD(SOFT_RESET_MH, int)
+    GENERATE_FIELD(SOFT_RESET_BC, int)
+    GENERATE_FIELD(SOFT_RESET_SQ, int)
+    GENERATE_FIELD(SOFT_RESET_SX, int)
+    GENERATE_FIELD(SOFT_RESET_CIB, int)
+    GENERATE_FIELD(SOFT_RESET_SC, int)
+    GENERATE_FIELD(SOFT_RESET_VGT, int)
+END_REGISTER(RBBM_SOFT_RESET)
+
+START_REGISTER(RBBM_PM_OVERRIDE1)
+    GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE1)
+
+START_REGISTER(RBBM_PM_OVERRIDE2)
+    GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE2)
+
+START_REGISTER(GC_SYS_IDLE)
+    GENERATE_FIELD(GC_SYS_IDLE_DELAY, int)
+    GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int)
+END_REGISTER(GC_SYS_IDLE)
+
+START_REGISTER(NQWAIT_UNTIL)
+    GENERATE_FIELD(WAIT_GUI_IDLE, int)
+END_REGISTER(NQWAIT_UNTIL)
+
+START_REGISTER(RBBM_DEBUG)
+    GENERATE_FIELD(IGNORE_RTR, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_WU, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int)
+    GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int)
+    GENERATE_FIELD(IGNORE_RTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(CP_RBBM_NRTRTR, int)
+    GENERATE_FIELD(VGT_RBBM_NRTRTR, int)
+    GENERATE_FIELD(SQ_RBBM_NRTRTR, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int)
+    GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int)
+END_REGISTER(RBBM_DEBUG)
+
+START_REGISTER(RBBM_READ_ERROR)
+    GENERATE_FIELD(READ_ADDRESS, int)
+    GENERATE_FIELD(READ_REQUESTER, int)
+    GENERATE_FIELD(READ_ERROR, int)
+END_REGISTER(RBBM_READ_ERROR)
+
+START_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+    GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int)
+END_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+
+START_REGISTER(RBBM_INT_CNTL)
+    GENERATE_FIELD(RDERR_INT_MASK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int)
+    GENERATE_FIELD(GUI_IDLE_INT_MASK, int)
+END_REGISTER(RBBM_INT_CNTL)
+
+START_REGISTER(RBBM_INT_STATUS)
+    GENERATE_FIELD(RDERR_INT_STAT, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int)
+    GENERATE_FIELD(GUI_IDLE_INT_STAT, int)
+END_REGISTER(RBBM_INT_STATUS)
+
+START_REGISTER(RBBM_INT_ACK)
+    GENERATE_FIELD(RDERR_INT_ACK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int)
+    GENERATE_FIELD(GUI_IDLE_INT_ACK, int)
+END_REGISTER(RBBM_INT_ACK)
+
+START_REGISTER(MASTER_INT_SIGNAL)
+    GENERATE_FIELD(MH_INT_STAT, int)
+    GENERATE_FIELD(CP_INT_STAT, int)
+    GENERATE_FIELD(RBBM_INT_STAT, int)
+END_REGISTER(MASTER_INT_SIGNAL)
+
+START_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL)
+END_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(RBBM_PERFCOUNTER1_LO)
+    GENERATE_FIELD(PERF_COUNT1_LO, int)
+END_REGISTER(RBBM_PERFCOUNTER1_LO)
+
+START_REGISTER(RBBM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT1_HI, int)
+END_REGISTER(RBBM_PERFCOUNTER1_HI)
+
+START_REGISTER(CP_RB_BASE)
+    GENERATE_FIELD(RB_BASE, int)
+END_REGISTER(CP_RB_BASE)
+
+START_REGISTER(CP_RB_CNTL)
+    GENERATE_FIELD(RB_BUFSZ, int)
+    GENERATE_FIELD(RB_BLKSZ, int)
+    GENERATE_FIELD(BUF_SWAP, int)
+    GENERATE_FIELD(RB_POLL_EN, int)
+    GENERATE_FIELD(RB_NO_UPDATE, int)
+    GENERATE_FIELD(RB_RPTR_WR_ENA, int)
+END_REGISTER(CP_RB_CNTL)
+
+START_REGISTER(CP_RB_RPTR_ADDR)
+    GENERATE_FIELD(RB_RPTR_SWAP, int)
+    GENERATE_FIELD(RB_RPTR_ADDR, int)
+END_REGISTER(CP_RB_RPTR_ADDR)
+
+START_REGISTER(CP_RB_RPTR)
+    GENERATE_FIELD(RB_RPTR, int)
+END_REGISTER(CP_RB_RPTR)
+
+START_REGISTER(CP_RB_RPTR_WR)
+    GENERATE_FIELD(RB_RPTR_WR, int)
+END_REGISTER(CP_RB_RPTR_WR)
+
+START_REGISTER(CP_RB_WPTR)
+    GENERATE_FIELD(RB_WPTR, int)
+END_REGISTER(CP_RB_WPTR)
+
+START_REGISTER(CP_RB_WPTR_DELAY)
+    GENERATE_FIELD(PRE_WRITE_TIMER, int)
+    GENERATE_FIELD(PRE_WRITE_LIMIT, int)
+END_REGISTER(CP_RB_WPTR_DELAY)
+
+START_REGISTER(CP_RB_WPTR_BASE)
+    GENERATE_FIELD(RB_WPTR_SWAP, int)
+    GENERATE_FIELD(RB_WPTR_BASE, int)
+END_REGISTER(CP_RB_WPTR_BASE)
+
+START_REGISTER(CP_IB1_BASE)
+    GENERATE_FIELD(IB1_BASE, int)
+END_REGISTER(CP_IB1_BASE)
+
+START_REGISTER(CP_IB1_BUFSZ)
+    GENERATE_FIELD(IB1_BUFSZ, int)
+END_REGISTER(CP_IB1_BUFSZ)
+
+START_REGISTER(CP_IB2_BASE)
+    GENERATE_FIELD(IB2_BASE, int)
+END_REGISTER(CP_IB2_BASE)
+
+START_REGISTER(CP_IB2_BUFSZ)
+    GENERATE_FIELD(IB2_BUFSZ, int)
+END_REGISTER(CP_IB2_BUFSZ)
+
+START_REGISTER(CP_ST_BASE)
+    GENERATE_FIELD(ST_BASE, int)
+END_REGISTER(CP_ST_BASE)
+
+START_REGISTER(CP_ST_BUFSZ)
+    GENERATE_FIELD(ST_BUFSZ, int)
+END_REGISTER(CP_ST_BUFSZ)
+
+START_REGISTER(CP_QUEUE_THRESHOLDS)
+    GENERATE_FIELD(CSQ_IB1_START, int)
+    GENERATE_FIELD(CSQ_IB2_START, int)
+    GENERATE_FIELD(CSQ_ST_START, int)
+END_REGISTER(CP_QUEUE_THRESHOLDS)
+
+START_REGISTER(CP_MEQ_THRESHOLDS)
+    GENERATE_FIELD(MEQ_END, int)
+    GENERATE_FIELD(ROQ_END, int)
+END_REGISTER(CP_MEQ_THRESHOLDS)
+
+START_REGISTER(CP_CSQ_AVAIL)
+    GENERATE_FIELD(CSQ_CNT_RING, int)
+    GENERATE_FIELD(CSQ_CNT_IB1, int)
+    GENERATE_FIELD(CSQ_CNT_IB2, int)
+END_REGISTER(CP_CSQ_AVAIL)
+
+START_REGISTER(CP_STQ_AVAIL)
+    GENERATE_FIELD(STQ_CNT_ST, int)
+END_REGISTER(CP_STQ_AVAIL)
+
+START_REGISTER(CP_MEQ_AVAIL)
+    GENERATE_FIELD(MEQ_CNT, int)
+END_REGISTER(CP_MEQ_AVAIL)
+
+START_REGISTER(CP_CSQ_RB_STAT)
+    GENERATE_FIELD(CSQ_RPTR_PRIMARY, int)
+    GENERATE_FIELD(CSQ_WPTR_PRIMARY, int)
+END_REGISTER(CP_CSQ_RB_STAT)
+
+START_REGISTER(CP_CSQ_IB1_STAT)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int)
+END_REGISTER(CP_CSQ_IB1_STAT)
+
+START_REGISTER(CP_CSQ_IB2_STAT)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int)
+END_REGISTER(CP_CSQ_IB2_STAT)
+
+START_REGISTER(CP_NON_PREFETCH_CNTRS)
+    GENERATE_FIELD(IB1_COUNTER, int)
+    GENERATE_FIELD(IB2_COUNTER, int)
+END_REGISTER(CP_NON_PREFETCH_CNTRS)
+
+START_REGISTER(CP_STQ_ST_STAT)
+    GENERATE_FIELD(STQ_RPTR_ST, int)
+    GENERATE_FIELD(STQ_WPTR_ST, int)
+END_REGISTER(CP_STQ_ST_STAT)
+
+START_REGISTER(CP_MEQ_STAT)
+    GENERATE_FIELD(MEQ_RPTR, int)
+    GENERATE_FIELD(MEQ_WPTR, int)
+END_REGISTER(CP_MEQ_STAT)
+
+START_REGISTER(CP_MIU_TAG_STAT)
+    GENERATE_FIELD(TAG_0_STAT, int)
+    GENERATE_FIELD(TAG_1_STAT, int)
+    GENERATE_FIELD(TAG_2_STAT, int)
+    GENERATE_FIELD(TAG_3_STAT, int)
+    GENERATE_FIELD(TAG_4_STAT, int)
+    GENERATE_FIELD(TAG_5_STAT, int)
+    GENERATE_FIELD(TAG_6_STAT, int)
+    GENERATE_FIELD(TAG_7_STAT, int)
+    GENERATE_FIELD(TAG_8_STAT, int)
+    GENERATE_FIELD(TAG_9_STAT, int)
+    GENERATE_FIELD(TAG_10_STAT, int)
+    GENERATE_FIELD(TAG_11_STAT, int)
+    GENERATE_FIELD(TAG_12_STAT, int)
+    GENERATE_FIELD(TAG_13_STAT, int)
+    GENERATE_FIELD(TAG_14_STAT, int)
+    GENERATE_FIELD(TAG_15_STAT, int)
+    GENERATE_FIELD(TAG_16_STAT, int)
+    GENERATE_FIELD(TAG_17_STAT, int)
+    GENERATE_FIELD(INVALID_RETURN_TAG, int)
+END_REGISTER(CP_MIU_TAG_STAT)
+
+START_REGISTER(CP_CMD_INDEX)
+    GENERATE_FIELD(CMD_INDEX, int)
+    GENERATE_FIELD(CMD_QUEUE_SEL, int)
+END_REGISTER(CP_CMD_INDEX)
+
+START_REGISTER(CP_CMD_DATA)
+    GENERATE_FIELD(CMD_DATA, int)
+END_REGISTER(CP_CMD_DATA)
+
+START_REGISTER(CP_ME_CNTL)
+    GENERATE_FIELD(ME_STATMUX, int)
+    GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(ME_HALT, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(PROG_CNT_SIZE, int)
+END_REGISTER(CP_ME_CNTL)
+
+START_REGISTER(CP_ME_STATUS)
+    GENERATE_FIELD(ME_DEBUG_DATA, int)
+END_REGISTER(CP_ME_STATUS)
+
+START_REGISTER(CP_ME_RAM_WADDR)
+    GENERATE_FIELD(ME_RAM_WADDR, int)
+END_REGISTER(CP_ME_RAM_WADDR)
+
+START_REGISTER(CP_ME_RAM_RADDR)
+    GENERATE_FIELD(ME_RAM_RADDR, int)
+END_REGISTER(CP_ME_RAM_RADDR)
+
+START_REGISTER(CP_ME_RAM_DATA)
+    GENERATE_FIELD(ME_RAM_DATA, int)
+END_REGISTER(CP_ME_RAM_DATA)
+
+START_REGISTER(CP_ME_RDADDR)
+    GENERATE_FIELD(ME_RDADDR, int)
+END_REGISTER(CP_ME_RDADDR)
+
+START_REGISTER(CP_DEBUG)
+    GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int)
+    GENERATE_FIELD(PREDICATE_DISABLE, int)
+    GENERATE_FIELD(PROG_END_PTR_ENABLE, int)
+    GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int)
+    GENERATE_FIELD(PREFETCH_PASS_NOPS, int)
+    GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int)
+    GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int)
+    GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int)
+    GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int)
+END_REGISTER(CP_DEBUG)
+
+START_REGISTER(SCRATCH_REG0)
+    GENERATE_FIELD(SCRATCH_REG0, int)
+END_REGISTER(SCRATCH_REG0)
+
+START_REGISTER(SCRATCH_REG1)
+    GENERATE_FIELD(SCRATCH_REG1, int)
+END_REGISTER(SCRATCH_REG1)
+
+START_REGISTER(SCRATCH_REG2)
+    GENERATE_FIELD(SCRATCH_REG2, int)
+END_REGISTER(SCRATCH_REG2)
+
+START_REGISTER(SCRATCH_REG3)
+    GENERATE_FIELD(SCRATCH_REG3, int)
+END_REGISTER(SCRATCH_REG3)
+
+START_REGISTER(SCRATCH_REG4)
+    GENERATE_FIELD(SCRATCH_REG4, int)
+END_REGISTER(SCRATCH_REG4)
+
+START_REGISTER(SCRATCH_REG5)
+    GENERATE_FIELD(SCRATCH_REG5, int)
+END_REGISTER(SCRATCH_REG5)
+
+START_REGISTER(SCRATCH_REG6)
+    GENERATE_FIELD(SCRATCH_REG6, int)
+END_REGISTER(SCRATCH_REG6)
+
+START_REGISTER(SCRATCH_REG7)
+    GENERATE_FIELD(SCRATCH_REG7, int)
+END_REGISTER(SCRATCH_REG7)
+
+START_REGISTER(SCRATCH_UMSK)
+    GENERATE_FIELD(SCRATCH_UMSK, int)
+    GENERATE_FIELD(SCRATCH_SWAP, int)
+END_REGISTER(SCRATCH_UMSK)
+
+START_REGISTER(SCRATCH_ADDR)
+    GENERATE_FIELD(SCRATCH_ADDR, hex)
+END_REGISTER(SCRATCH_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_SRC)
+    GENERATE_FIELD(VS_DONE_SWM, int)
+    GENERATE_FIELD(VS_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_EVENT_SRC)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR)
+    GENERATE_FIELD(VS_DONE_SWAP, int)
+    GENERATE_FIELD(VS_DONE_ADDR, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA)
+    GENERATE_FIELD(VS_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(VS_DONE_SWAP_SWM, int)
+    GENERATE_FIELD(VS_DONE_ADDR_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+    GENERATE_FIELD(VS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_SRC)
+    GENERATE_FIELD(PS_DONE_SWM, int)
+    GENERATE_FIELD(PS_DONE_CNTR, int)
+END_REGISTER(CP_ME_PS_EVENT_SRC)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR)
+    GENERATE_FIELD(PS_DONE_SWAP, int)
+    GENERATE_FIELD(PS_DONE_ADDR, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA)
+    GENERATE_FIELD(PS_DONE_DATA, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(PS_DONE_SWAP_SWM, int)
+    GENERATE_FIELD(PS_DONE_ADDR_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+    GENERATE_FIELD(PS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_CF_EVENT_SRC)
+    GENERATE_FIELD(CF_DONE_SRC, int)
+END_REGISTER(CP_ME_CF_EVENT_SRC)
+
+START_REGISTER(CP_ME_CF_EVENT_ADDR)
+    GENERATE_FIELD(CF_DONE_SWAP, int)
+    GENERATE_FIELD(CF_DONE_ADDR, int)
+END_REGISTER(CP_ME_CF_EVENT_ADDR)
+
+START_REGISTER(CP_ME_CF_EVENT_DATA)
+    GENERATE_FIELD(CF_DONE_DATA, int)
+END_REGISTER(CP_ME_CF_EVENT_DATA)
+
+START_REGISTER(CP_ME_NRT_ADDR)
+    GENERATE_FIELD(NRT_WRITE_SWAP, int)
+    GENERATE_FIELD(NRT_WRITE_ADDR, int)
+END_REGISTER(CP_ME_NRT_ADDR)
+
+START_REGISTER(CP_ME_NRT_DATA)
+    GENERATE_FIELD(NRT_WRITE_DATA, int)
+END_REGISTER(CP_ME_NRT_DATA)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+    GENERATE_FIELD(VS_FETCH_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+    GENERATE_FIELD(VS_FETCH_DONE_SWAP, int)
+    GENERATE_FIELD(VS_FETCH_DONE_ADDR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+    GENERATE_FIELD(VS_FETCH_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+
+START_REGISTER(CP_INT_CNTL)
+    GENERATE_FIELD(SW_INT_MASK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int)
+    GENERATE_FIELD(OPCODE_ERROR_MASK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int)
+    GENERATE_FIELD(IB_ERROR_MASK, int)
+    GENERATE_FIELD(IB2_INT_MASK, int)
+    GENERATE_FIELD(IB1_INT_MASK, int)
+    GENERATE_FIELD(RB_INT_MASK, int)
+END_REGISTER(CP_INT_CNTL)
+
+START_REGISTER(CP_INT_STATUS)
+    GENERATE_FIELD(SW_INT_STAT, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int)
+    GENERATE_FIELD(OPCODE_ERROR_STAT, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int)
+    GENERATE_FIELD(IB_ERROR_STAT, int)
+    GENERATE_FIELD(IB2_INT_STAT, int)
+    GENERATE_FIELD(IB1_INT_STAT, int)
+    GENERATE_FIELD(RB_INT_STAT, int)
+END_REGISTER(CP_INT_STATUS)
+
+START_REGISTER(CP_INT_ACK)
+    GENERATE_FIELD(SW_INT_ACK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int)
+    GENERATE_FIELD(OPCODE_ERROR_ACK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int)
+    GENERATE_FIELD(IB_ERROR_ACK, int)
+    GENERATE_FIELD(IB2_INT_ACK, int)
+    GENERATE_FIELD(IB1_INT_ACK, int)
+    GENERATE_FIELD(RB_INT_ACK, int)
+END_REGISTER(CP_INT_ACK)
+
+START_REGISTER(CP_PFP_UCODE_ADDR)
+    GENERATE_FIELD(UCODE_ADDR, hex)
+END_REGISTER(CP_PFP_UCODE_ADDR)
+
+START_REGISTER(CP_PFP_UCODE_DATA)
+    GENERATE_FIELD(UCODE_DATA, hex)
+END_REGISTER(CP_PFP_UCODE_DATA)
+
+START_REGISTER(CP_PERFMON_CNTL)
+    GENERATE_FIELD(PERFMON_STATE, int)
+    GENERATE_FIELD(PERFMON_ENABLE_MODE, int)
+END_REGISTER(CP_PERFMON_CNTL)
+
+START_REGISTER(CP_PERFCOUNTER_SELECT)
+    GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL)
+END_REGISTER(CP_PERFCOUNTER_SELECT)
+
+START_REGISTER(CP_PERFCOUNTER_LO)
+    GENERATE_FIELD(PERFCOUNT_LO, int)
+END_REGISTER(CP_PERFCOUNTER_LO)
+
+START_REGISTER(CP_PERFCOUNTER_HI)
+    GENERATE_FIELD(PERFCOUNT_HI, int)
+END_REGISTER(CP_PERFCOUNTER_HI)
+
+START_REGISTER(CP_BIN_MASK_LO)
+    GENERATE_FIELD(BIN_MASK_LO, int)
+END_REGISTER(CP_BIN_MASK_LO)
+
+START_REGISTER(CP_BIN_MASK_HI)
+    GENERATE_FIELD(BIN_MASK_HI, int)
+END_REGISTER(CP_BIN_MASK_HI)
+
+START_REGISTER(CP_BIN_SELECT_LO)
+    GENERATE_FIELD(BIN_SELECT_LO, int)
+END_REGISTER(CP_BIN_SELECT_LO)
+
+START_REGISTER(CP_BIN_SELECT_HI)
+    GENERATE_FIELD(BIN_SELECT_HI, int)
+END_REGISTER(CP_BIN_SELECT_HI)
+
+START_REGISTER(CP_NV_FLAGS_0)
+    GENERATE_FIELD(DISCARD_0, int)
+    GENERATE_FIELD(END_RCVD_0, int)
+    GENERATE_FIELD(DISCARD_1, int)
+    GENERATE_FIELD(END_RCVD_1, int)
+    GENERATE_FIELD(DISCARD_2, int)
+    GENERATE_FIELD(END_RCVD_2, int)
+    GENERATE_FIELD(DISCARD_3, int)
+    GENERATE_FIELD(END_RCVD_3, int)
+    GENERATE_FIELD(DISCARD_4, int)
+    GENERATE_FIELD(END_RCVD_4, int)
+    GENERATE_FIELD(DISCARD_5, int)
+    GENERATE_FIELD(END_RCVD_5, int)
+    GENERATE_FIELD(DISCARD_6, int)
+    GENERATE_FIELD(END_RCVD_6, int)
+    GENERATE_FIELD(DISCARD_7, int)
+    GENERATE_FIELD(END_RCVD_7, int)
+    GENERATE_FIELD(DISCARD_8, int)
+    GENERATE_FIELD(END_RCVD_8, int)
+    GENERATE_FIELD(DISCARD_9, int)
+    GENERATE_FIELD(END_RCVD_9, int)
+    GENERATE_FIELD(DISCARD_10, int)
+    GENERATE_FIELD(END_RCVD_10, int)
+    GENERATE_FIELD(DISCARD_11, int)
+    GENERATE_FIELD(END_RCVD_11, int)
+    GENERATE_FIELD(DISCARD_12, int)
+    GENERATE_FIELD(END_RCVD_12, int)
+    GENERATE_FIELD(DISCARD_13, int)
+    GENERATE_FIELD(END_RCVD_13, int)
+    GENERATE_FIELD(DISCARD_14, int)
+    GENERATE_FIELD(END_RCVD_14, int)
+    GENERATE_FIELD(DISCARD_15, int)
+    GENERATE_FIELD(END_RCVD_15, int)
+END_REGISTER(CP_NV_FLAGS_0)
+
+START_REGISTER(CP_NV_FLAGS_1)
+    GENERATE_FIELD(DISCARD_16, int)
+    GENERATE_FIELD(END_RCVD_16, int)
+    GENERATE_FIELD(DISCARD_17, int)
+    GENERATE_FIELD(END_RCVD_17, int)
+    GENERATE_FIELD(DISCARD_18, int)
+    GENERATE_FIELD(END_RCVD_18, int)
+    GENERATE_FIELD(DISCARD_19, int)
+    GENERATE_FIELD(END_RCVD_19, int)
+    GENERATE_FIELD(DISCARD_20, int)
+    GENERATE_FIELD(END_RCVD_20, int)
+    GENERATE_FIELD(DISCARD_21, int)
+    GENERATE_FIELD(END_RCVD_21, int)
+    GENERATE_FIELD(DISCARD_22, int)
+    GENERATE_FIELD(END_RCVD_22, int)
+    GENERATE_FIELD(DISCARD_23, int)
+    GENERATE_FIELD(END_RCVD_23, int)
+    GENERATE_FIELD(DISCARD_24, int)
+    GENERATE_FIELD(END_RCVD_24, int)
+    GENERATE_FIELD(DISCARD_25, int)
+    GENERATE_FIELD(END_RCVD_25, int)
+    GENERATE_FIELD(DISCARD_26, int)
+    GENERATE_FIELD(END_RCVD_26, int)
+    GENERATE_FIELD(DISCARD_27, int)
+    GENERATE_FIELD(END_RCVD_27, int)
+    GENERATE_FIELD(DISCARD_28, int)
+    GENERATE_FIELD(END_RCVD_28, int)
+    GENERATE_FIELD(DISCARD_29, int)
+    GENERATE_FIELD(END_RCVD_29, int)
+    GENERATE_FIELD(DISCARD_30, int)
+    GENERATE_FIELD(END_RCVD_30, int)
+    GENERATE_FIELD(DISCARD_31, int)
+    GENERATE_FIELD(END_RCVD_31, int)
+END_REGISTER(CP_NV_FLAGS_1)
+
+START_REGISTER(CP_NV_FLAGS_2)
+    GENERATE_FIELD(DISCARD_32, int)
+    GENERATE_FIELD(END_RCVD_32, int)
+    GENERATE_FIELD(DISCARD_33, int)
+    GENERATE_FIELD(END_RCVD_33, int)
+    GENERATE_FIELD(DISCARD_34, int)
+    GENERATE_FIELD(END_RCVD_34, int)
+    GENERATE_FIELD(DISCARD_35, int)
+    GENERATE_FIELD(END_RCVD_35, int)
+    GENERATE_FIELD(DISCARD_36, int)
+    GENERATE_FIELD(END_RCVD_36, int)
+    GENERATE_FIELD(DISCARD_37, int)
+    GENERATE_FIELD(END_RCVD_37, int)
+    GENERATE_FIELD(DISCARD_38, int)
+    GENERATE_FIELD(END_RCVD_38, int)
+    GENERATE_FIELD(DISCARD_39, int)
+    GENERATE_FIELD(END_RCVD_39, int)
+    GENERATE_FIELD(DISCARD_40, int)
+    GENERATE_FIELD(END_RCVD_40, int)
+    GENERATE_FIELD(DISCARD_41, int)
+    GENERATE_FIELD(END_RCVD_41, int)
+    GENERATE_FIELD(DISCARD_42, int)
+    GENERATE_FIELD(END_RCVD_42, int)
+    GENERATE_FIELD(DISCARD_43, int)
+    GENERATE_FIELD(END_RCVD_43, int)
+    GENERATE_FIELD(DISCARD_44, int)
+    GENERATE_FIELD(END_RCVD_44, int)
+    GENERATE_FIELD(DISCARD_45, int)
+    GENERATE_FIELD(END_RCVD_45, int)
+    GENERATE_FIELD(DISCARD_46, int)
+    GENERATE_FIELD(END_RCVD_46, int)
+    GENERATE_FIELD(DISCARD_47, int)
+    GENERATE_FIELD(END_RCVD_47, int)
+END_REGISTER(CP_NV_FLAGS_2)
+
+START_REGISTER(CP_NV_FLAGS_3)
+    GENERATE_FIELD(DISCARD_48, int)
+    GENERATE_FIELD(END_RCVD_48, int)
+    GENERATE_FIELD(DISCARD_49, int)
+    GENERATE_FIELD(END_RCVD_49, int)
+    GENERATE_FIELD(DISCARD_50, int)
+    GENERATE_FIELD(END_RCVD_50, int)
+    GENERATE_FIELD(DISCARD_51, int)
+    GENERATE_FIELD(END_RCVD_51, int)
+    GENERATE_FIELD(DISCARD_52, int)
+    GENERATE_FIELD(END_RCVD_52, int)
+    GENERATE_FIELD(DISCARD_53, int)
+    GENERATE_FIELD(END_RCVD_53, int)
+    GENERATE_FIELD(DISCARD_54, int)
+    GENERATE_FIELD(END_RCVD_54, int)
+    GENERATE_FIELD(DISCARD_55, int)
+    GENERATE_FIELD(END_RCVD_55, int)
+    GENERATE_FIELD(DISCARD_56, int)
+    GENERATE_FIELD(END_RCVD_56, int)
+    GENERATE_FIELD(DISCARD_57, int)
+    GENERATE_FIELD(END_RCVD_57, int)
+    GENERATE_FIELD(DISCARD_58, int)
+    GENERATE_FIELD(END_RCVD_58, int)
+    GENERATE_FIELD(DISCARD_59, int)
+    GENERATE_FIELD(END_RCVD_59, int)
+    GENERATE_FIELD(DISCARD_60, int)
+    GENERATE_FIELD(END_RCVD_60, int)
+    GENERATE_FIELD(DISCARD_61, int)
+    GENERATE_FIELD(END_RCVD_61, int)
+    GENERATE_FIELD(DISCARD_62, int)
+    GENERATE_FIELD(END_RCVD_62, int)
+    GENERATE_FIELD(DISCARD_63, int)
+    GENERATE_FIELD(END_RCVD_63, int)
+END_REGISTER(CP_NV_FLAGS_3)
+
+START_REGISTER(CP_STATE_DEBUG_INDEX)
+    GENERATE_FIELD(STATE_DEBUG_INDEX, int)
+END_REGISTER(CP_STATE_DEBUG_INDEX)
+
+START_REGISTER(CP_STATE_DEBUG_DATA)
+    GENERATE_FIELD(STATE_DEBUG_DATA, int)
+END_REGISTER(CP_STATE_DEBUG_DATA)
+
+START_REGISTER(CP_PROG_COUNTER)
+    GENERATE_FIELD(COUNTER, int)
+END_REGISTER(CP_PROG_COUNTER)
+
+START_REGISTER(CP_STAT)
+    GENERATE_FIELD(MIU_WR_BUSY, int)
+    GENERATE_FIELD(MIU_RD_REQ_BUSY, int)
+    GENERATE_FIELD(MIU_RD_RETURN_BUSY, int)
+    GENERATE_FIELD(RBIU_BUSY, int)
+    GENERATE_FIELD(RCIU_BUSY, int)
+    GENERATE_FIELD(CSF_RING_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(CSF_ST_BUSY, int)
+    GENERATE_FIELD(CSF_BUSY, int)
+    GENERATE_FIELD(RING_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int)
+    GENERATE_FIELD(ST_QUEUE_BUSY, int)
+    GENERATE_FIELD(PFP_BUSY, int)
+    GENERATE_FIELD(MEQ_RING_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(MIU_WC_STALL, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(_3D_BUSY, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(ME_WC_BUSY, int)
+    GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int)
+    GENERATE_FIELD(CP_BUSY, int)
+END_REGISTER(CP_STAT)
+
+START_REGISTER(BIOS_0_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_0_SCRATCH)
+
+START_REGISTER(BIOS_1_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_1_SCRATCH)
+
+START_REGISTER(BIOS_2_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_2_SCRATCH)
+
+START_REGISTER(BIOS_3_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_3_SCRATCH)
+
+START_REGISTER(BIOS_4_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_4_SCRATCH)
+
+START_REGISTER(BIOS_5_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_5_SCRATCH)
+
+START_REGISTER(BIOS_6_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_6_SCRATCH)
+
+START_REGISTER(BIOS_7_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_7_SCRATCH)
+
+START_REGISTER(BIOS_8_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_8_SCRATCH)
+
+START_REGISTER(BIOS_9_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_9_SCRATCH)
+
+START_REGISTER(BIOS_10_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_10_SCRATCH)
+
+START_REGISTER(BIOS_11_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_11_SCRATCH)
+
+START_REGISTER(BIOS_12_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_12_SCRATCH)
+
+START_REGISTER(BIOS_13_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_13_SCRATCH)
+
+START_REGISTER(BIOS_14_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_14_SCRATCH)
+
+START_REGISTER(BIOS_15_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_15_SCRATCH)
+
+START_REGISTER(COHER_SIZE_PM4)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_PM4)
+
+START_REGISTER(COHER_BASE_PM4)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(COHER_BASE_PM4)
+
+START_REGISTER(COHER_STATUS_PM4)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(STATUS, int)
+END_REGISTER(COHER_STATUS_PM4)
+
+START_REGISTER(COHER_SIZE_HOST)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_HOST)
+
+START_REGISTER(COHER_BASE_HOST)
+    GENERATE_FIELD(BASE, hex)
+END_REGISTER(COHER_BASE_HOST)
+
+START_REGISTER(COHER_STATUS_HOST)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(STATUS, int)
+END_REGISTER(COHER_STATUS_HOST)
+
+START_REGISTER(COHER_DEST_BASE_0)
+    GENERATE_FIELD(DEST_BASE_0, hex)
+END_REGISTER(COHER_DEST_BASE_0)
+
+START_REGISTER(COHER_DEST_BASE_1)
+    GENERATE_FIELD(DEST_BASE_1, hex)
+END_REGISTER(COHER_DEST_BASE_1)
+
+START_REGISTER(COHER_DEST_BASE_2)
+    GENERATE_FIELD(DEST_BASE_2, hex)
+END_REGISTER(COHER_DEST_BASE_2)
+
+START_REGISTER(COHER_DEST_BASE_3)
+    GENERATE_FIELD(DEST_BASE_3, hex)
+END_REGISTER(COHER_DEST_BASE_3)
+
+START_REGISTER(COHER_DEST_BASE_4)
+    GENERATE_FIELD(DEST_BASE_4, hex)
+END_REGISTER(COHER_DEST_BASE_4)
+
+START_REGISTER(COHER_DEST_BASE_5)
+    GENERATE_FIELD(DEST_BASE_5, hex)
+END_REGISTER(COHER_DEST_BASE_5)
+
+START_REGISTER(COHER_DEST_BASE_6)
+    GENERATE_FIELD(DEST_BASE_6, hex)
+END_REGISTER(COHER_DEST_BASE_6)
+
+START_REGISTER(COHER_DEST_BASE_7)
+    GENERATE_FIELD(DEST_BASE_7, hex)
+END_REGISTER(COHER_DEST_BASE_7)
+
+START_REGISTER(RB_SURFACE_INFO)
+    GENERATE_FIELD(SURFACE_PITCH, uint)
+    GENERATE_FIELD(MSAA_SAMPLES, MSAASamples)
+END_REGISTER(RB_SURFACE_INFO)
+
+START_REGISTER(RB_COLOR_INFO)
+    GENERATE_FIELD(COLOR_FORMAT, ColorformatX)
+    GENERATE_FIELD(COLOR_ROUND_MODE, uint)
+    GENERATE_FIELD(COLOR_LINEAR, bool)
+    GENERATE_FIELD(COLOR_ENDIAN, uint)
+    GENERATE_FIELD(COLOR_SWAP, uint)
+    GENERATE_FIELD(COLOR_BASE, uint)
+END_REGISTER(RB_COLOR_INFO)
+
+START_REGISTER(RB_DEPTH_INFO)
+    GENERATE_FIELD(DEPTH_FORMAT, DepthformatX)
+    GENERATE_FIELD(DEPTH_BASE, uint)
+END_REGISTER(RB_DEPTH_INFO)
+
+START_REGISTER(RB_STENCILREFMASK)
+    GENERATE_FIELD(STENCILREF, hex)
+    GENERATE_FIELD(STENCILMASK, hex)
+    GENERATE_FIELD(STENCILWRITEMASK, hex)
+END_REGISTER(RB_STENCILREFMASK)
+
+START_REGISTER(RB_ALPHA_REF)
+    GENERATE_FIELD(ALPHA_REF, float)
+END_REGISTER(RB_ALPHA_REF)
+
+START_REGISTER(RB_COLOR_MASK)
+    GENERATE_FIELD(WRITE_RED, bool)
+    GENERATE_FIELD(WRITE_GREEN, bool)
+    GENERATE_FIELD(WRITE_BLUE, bool)
+    GENERATE_FIELD(WRITE_ALPHA, bool)
+END_REGISTER(RB_COLOR_MASK)
+
+START_REGISTER(RB_BLEND_RED)
+    GENERATE_FIELD(BLEND_RED, uint)
+END_REGISTER(RB_BLEND_RED)
+
+START_REGISTER(RB_BLEND_GREEN)
+    GENERATE_FIELD(BLEND_GREEN, uint)
+END_REGISTER(RB_BLEND_GREEN)
+
+START_REGISTER(RB_BLEND_BLUE)
+    GENERATE_FIELD(BLEND_BLUE, uint)
+END_REGISTER(RB_BLEND_BLUE)
+
+START_REGISTER(RB_BLEND_ALPHA)
+    GENERATE_FIELD(BLEND_ALPHA, uint)
+END_REGISTER(RB_BLEND_ALPHA)
+
+START_REGISTER(RB_FOG_COLOR)
+    GENERATE_FIELD(FOG_RED, uint)
+    GENERATE_FIELD(FOG_GREEN, uint)
+    GENERATE_FIELD(FOG_BLUE, uint)
+END_REGISTER(RB_FOG_COLOR)
+
+START_REGISTER(RB_STENCILREFMASK_BF)
+    GENERATE_FIELD(STENCILREF_BF, hex)
+    GENERATE_FIELD(STENCILMASK_BF, hex)
+    GENERATE_FIELD(STENCILWRITEMASK_BF, hex)
+END_REGISTER(RB_STENCILREFMASK_BF)
+
+START_REGISTER(RB_DEPTHCONTROL)
+    GENERATE_FIELD(STENCIL_ENABLE, bool)
+    GENERATE_FIELD(Z_ENABLE, bool)
+    GENERATE_FIELD(Z_WRITE_ENABLE, bool)
+    GENERATE_FIELD(EARLY_Z_ENABLE, bool)
+    GENERATE_FIELD(ZFUNC, CompareFrag)
+    GENERATE_FIELD(BACKFACE_ENABLE, bool)
+    GENERATE_FIELD(STENCILFUNC, CompareRef)
+    GENERATE_FIELD(STENCILFAIL, StencilOp)
+    GENERATE_FIELD(STENCILZPASS, StencilOp)
+    GENERATE_FIELD(STENCILZFAIL, StencilOp)
+    GENERATE_FIELD(STENCILFUNC_BF, CompareRef)
+    GENERATE_FIELD(STENCILFAIL_BF, StencilOp)
+    GENERATE_FIELD(STENCILZPASS_BF, StencilOp)
+    GENERATE_FIELD(STENCILZFAIL_BF, StencilOp)
+END_REGISTER(RB_DEPTHCONTROL)
+
+START_REGISTER(RB_BLENDCONTROL)
+    GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(BLEND_FORCE_ENABLE, bool)
+    GENERATE_FIELD(BLEND_FORCE, bool)
+END_REGISTER(RB_BLENDCONTROL)
+
+START_REGISTER(RB_COLORCONTROL)
+    GENERATE_FIELD(ALPHA_FUNC, CompareRef)
+    GENERATE_FIELD(ALPHA_TEST_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool)
+    GENERATE_FIELD(BLEND_DISABLE, bool)
+    GENERATE_FIELD(FOG_ENABLE, bool)
+    GENERATE_FIELD(VS_EXPORTS_FOG, bool)
+    GENERATE_FIELD(ROP_CODE, uint)
+    GENERATE_FIELD(DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(PIXEL_FOG, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex)
+END_REGISTER(RB_COLORCONTROL)
+
+START_REGISTER(RB_MODECONTROL)
+    GENERATE_FIELD(EDRAM_MODE, EdramMode)
+END_REGISTER(RB_MODECONTROL)
+
+START_REGISTER(RB_COLOR_DEST_MASK)
+    GENERATE_FIELD(COLOR_DEST_MASK, uint)
+END_REGISTER(RB_COLOR_DEST_MASK)
+
+START_REGISTER(RB_COPY_CONTROL)
+    GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect)
+    GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool)
+    GENERATE_FIELD(CLEAR_MASK, uint)
+END_REGISTER(RB_COPY_CONTROL)
+
+START_REGISTER(RB_COPY_DEST_BASE)
+    GENERATE_FIELD(COPY_DEST_BASE, uint)
+END_REGISTER(RB_COPY_DEST_BASE)
+
+START_REGISTER(RB_COPY_DEST_PITCH)
+    GENERATE_FIELD(COPY_DEST_PITCH, uint)
+END_REGISTER(RB_COPY_DEST_PITCH)
+
+START_REGISTER(RB_COPY_DEST_INFO)
+    GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian)
+    GENERATE_FIELD(COPY_DEST_LINEAR, uint)
+    GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX)
+    GENERATE_FIELD(COPY_DEST_SWAP, uint)
+    GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(COPY_MASK_WRITE_RED, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex)
+END_REGISTER(RB_COPY_DEST_INFO)
+
+START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+    GENERATE_FIELD(OFFSET_X, uint)
+    GENERATE_FIELD(OFFSET_Y, uint)
+END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+
+START_REGISTER(RB_DEPTH_CLEAR)
+    GENERATE_FIELD(DEPTH_CLEAR, uint)
+END_REGISTER(RB_DEPTH_CLEAR)
+
+START_REGISTER(RB_SAMPLE_COUNT_CTL)
+    GENERATE_FIELD(RESET_SAMPLE_COUNT, bool)
+    GENERATE_FIELD(COPY_SAMPLE_COUNT, bool)
+END_REGISTER(RB_SAMPLE_COUNT_CTL)
+
+START_REGISTER(RB_SAMPLE_COUNT_ADDR)
+    GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint)
+END_REGISTER(RB_SAMPLE_COUNT_ADDR)
+
+START_REGISTER(RB_BC_CONTROL)
+    GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint)
+    GENERATE_FIELD(DISABLE_EDRAM_CAM, bool)
+    GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool)
+    GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool)
+    GENERATE_FIELD(AZ_THROTTLE_COUNT, uint)
+    GENERATE_FIELD(ENABLE_CRC_UPDATE, bool)
+    GENERATE_FIELD(CRC_MODE, bool)
+    GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool)
+    GENERATE_FIELD(DISABLE_ACCUM, bool)
+    GENERATE_FIELD(ACCUM_ALLOC_MASK, uint)
+    GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool)
+    GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int)
+    GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(RESERVED9, bool)
+    GENERATE_FIELD(RESERVED10, bool)
+END_REGISTER(RB_BC_CONTROL)
+
+START_REGISTER(RB_EDRAM_INFO)
+    GENERATE_FIELD(EDRAM_SIZE, EdramSizeX)
+    GENERATE_FIELD(EDRAM_MAPPING_MODE, uint)
+    GENERATE_FIELD(EDRAM_RANGE, hex)
+END_REGISTER(RB_EDRAM_INFO)
+
+START_REGISTER(RB_CRC_RD_PORT)
+    GENERATE_FIELD(CRC_DATA, hex)
+END_REGISTER(RB_CRC_RD_PORT)
+
+START_REGISTER(RB_CRC_CONTROL)
+    GENERATE_FIELD(CRC_RD_ADVANCE, bool)
+END_REGISTER(RB_CRC_CONTROL)
+
+START_REGISTER(RB_CRC_MASK)
+    GENERATE_FIELD(CRC_MASK, hex)
+END_REGISTER(RB_CRC_MASK)
+
+START_REGISTER(RB_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT)
+END_REGISTER(RB_PERFCOUNTER0_SELECT)
+
+START_REGISTER(RB_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_LOW)
+
+START_REGISTER(RB_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_HI)
+
+START_REGISTER(RB_TOTAL_SAMPLES)
+    GENERATE_FIELD(TOTAL_SAMPLES, int)
+END_REGISTER(RB_TOTAL_SAMPLES)
+
+START_REGISTER(RB_ZPASS_SAMPLES)
+    GENERATE_FIELD(ZPASS_SAMPLES, int)
+END_REGISTER(RB_ZPASS_SAMPLES)
+
+START_REGISTER(RB_ZFAIL_SAMPLES)
+    GENERATE_FIELD(ZFAIL_SAMPLES, int)
+END_REGISTER(RB_ZFAIL_SAMPLES)
+
+START_REGISTER(RB_SFAIL_SAMPLES)
+    GENERATE_FIELD(SFAIL_SAMPLES, int)
+END_REGISTER(RB_SFAIL_SAMPLES)
+
+START_REGISTER(RB_DEBUG_0)
+    GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z1_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z0_FULL, bool)
+    GENERATE_FIELD(RDREQ_C1_FULL, bool)
+    GENERATE_FIELD(RDREQ_C0_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z1_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z0_FULL, bool)
+    GENERATE_FIELD(WRREQ_C1_FULL, bool)
+    GENERATE_FIELD(WRREQ_C0_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool)
+    GENERATE_FIELD(C_SX_LAT_FULL, bool)
+    GENERATE_FIELD(C_SX_CMD_FULL, bool)
+    GENERATE_FIELD(C_EZ_TILE_FULL, bool)
+    GENERATE_FIELD(C_REQ_FULL, bool)
+    GENERATE_FIELD(C_MASK_FULL, bool)
+    GENERATE_FIELD(EZ_INFSAMP_FULL, bool)
+END_REGISTER(RB_DEBUG_0)
+
+START_REGISTER(RB_DEBUG_1)
+    GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(C_SX_LAT_EMPTY, bool)
+    GENERATE_FIELD(C_SX_CMD_EMPTY, bool)
+    GENERATE_FIELD(C_EZ_TILE_EMPTY, bool)
+    GENERATE_FIELD(C_REQ_EMPTY, bool)
+    GENERATE_FIELD(C_MASK_EMPTY, bool)
+    GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool)
+END_REGISTER(RB_DEBUG_1)
+
+START_REGISTER(RB_DEBUG_2)
+    GENERATE_FIELD(TILE_FIFO_COUNT, bool)
+    GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool)
+    GENERATE_FIELD(MEM_EXPORT_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool)
+    GENERATE_FIELD(CURRENT_TILE_EVENT, bool)
+    GENERATE_FIELD(EZ_INFTILE_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool)
+    GENERATE_FIELD(Z0_MASK_FULL, bool)
+    GENERATE_FIELD(Z1_MASK_FULL, bool)
+    GENERATE_FIELD(Z0_REQ_FULL, bool)
+    GENERATE_FIELD(Z1_REQ_FULL, bool)
+    GENERATE_FIELD(Z_SAMP_FULL, bool)
+    GENERATE_FIELD(Z_TILE_FULL, bool)
+    GENERATE_FIELD(EZ_INFTILE_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool)
+    GENERATE_FIELD(Z0_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z1_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z0_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z1_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z_SAMP_EMPTY, bool)
+    GENERATE_FIELD(Z_TILE_EMPTY, bool)
+END_REGISTER(RB_DEBUG_2)
+
+START_REGISTER(RB_DEBUG_3)
+    GENERATE_FIELD(ACCUM_VALID, bool)
+    GENERATE_FIELD(ACCUM_FLUSHING, bool)
+    GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool)
+    GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool)
+    GENERATE_FIELD(SHD_FULL, bool)
+    GENERATE_FIELD(SHD_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool)
+    GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_LOWER_FULL, bool)
+    GENERATE_FIELD(ZEXP_UPPER_FULL, bool)
+END_REGISTER(RB_DEBUG_3)
+
+START_REGISTER(RB_DEBUG_4)
+    GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool)
+    GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool)
+    GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool)
+END_REGISTER(RB_DEBUG_4)
+
+START_REGISTER(RB_FLAG_CONTROL)
+    GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool)
+END_REGISTER(RB_FLAG_CONTROL)
+
+START_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray)
+    GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX)
+END_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+
+START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX)
+END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h
new file mode 100644
index 000000000000..0e32e421d0a3
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h
@@ -0,0 +1,95 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _R400IPT_H_
+#define _R400IPT_H_
+
+// Hand-generated list from Yamato_PM4_Spec.doc
+
+#define PM4_PACKET0_NOP     0x00000000          // Empty type-0 packet header
+#define PM4_PACKET1_NOP     0x40000000          // Empty type-1 packet header
+#define PM4_PACKET2_NOP     0x80000000          // Empty type-2 packet header (reserved)
+
+#define PM4_COUNT_SHIFT     16  
+#define PM4_COUNT_MASK      
+#define PM4_PACKET_COUNT(__x)   ((((__x)-1) << PM4_COUNT_SHIFT) & 0x3fff0000)
+// Type 3 packet headers
+
+#define PM4_PACKET3_NOP                         0xC0001000  // Do nothing.
+#define PM4_PACKET3_IB_PREFETCH_END             0xC0001700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_SUBBLK_PREFETCH             0xC0001F00  // Internal Packet Used Only by CP
+
+#define PM4_PACKET3_INSTR_PREFETCH              0xC0002000  // Internal Packet Used Only by CP
+#define PM4_PACKET3_REG_RMW                     0xC0002100  // Register Read-Modify-Write                               New for R400
+#define PM4_PACKET3_DRAW_INDX                   0xC0002200  // Initiate fetch of index buffer                           New for R400
+#define PM4_PACKET3_VIZ_QUERY                   0xC0002300  // Begin/End initiator for Viz Query extent processing      New for R400
+#define PM4_PACKET3_SET_STATE                   0xC0002500  // Fetch State Sub-Blocks and Initiate Shader Code DMAs     New for R400
+#define PM4_PACKET3_WAIT_FOR_IDLE               0xC0002600  // Wait for the engine to be idle. 
+#define PM4_PACKET3_IM_LOAD                     0xC0002700  // Load Sequencer Instruction Memory for a Specific Shader  New for R400
+#define PM4_PACKET3_IM_LOAD_IMMEDIATE           0xC0002B00  // Load Sequencer Instruction Memory for a Specific Shader  New for R400
+#define PM4_PACKET3_SET_CONSTANT                0xC0002D00  // Load Constant Into Chip & Shadow to Memory               New for R400
+#define PM4_PACKET3_LOAD_CONSTANT_CONTEXT       0xC0002E00  // Load All Constants from a Location in Memory             New for R400
+#define PM4_PACKET3_LOAD_ALU_CONSTANT           0xC0002F00  // Load ALu constants from a location in memory - similar to SET_CONSTANT but tuned for performance when loading only ALU constants
+
+#define PM4_PACKET3_DRAW_INDX_BIN               0xC0003400  // Initiate fetch of index buffer and BIN info used for visibility test
+#define PM4_PACKET3_3D_DRAW_INDX_2_BIN          0xC0003500  // Draw using supplied indices and initiate fetch of BIN info for visibility test
+#define PM4_PACKET3_3D_DRAW_INDX_2              0xC0003600  // Draw primitives using vertex buf and Indices in this packet. Pkt does NOT contain vtx fmt
+#define PM4_PACKET3_INDIRECT_BUFFER_PFD         0xC0003700
+#define PM4_PACKET3_INVALIDATE_STATE            0xC0003B00  // Selective Invalidation of State Pointers                 New for R400
+#define PM4_PACKET3_WAIT_REG_MEM                0xC0003C00  // Wait Until a Register or Memory Location is a Specific Value.   New for R400
+#define PM4_PACKET3_MEM_WRITE                   0xC0003D00  // Write DWORD to Memory For Synchronization                New for R400
+#define PM4_PACKET3_REG_TO_MEM                  0xC0003E00  // Reads Register in Chip and Writes to Memory              New for R400
+#define PM4_PACKET3_INDIRECT_BUFFER             0xC0003F00  // Indirect Buffer Dispatch - Pre-fetch parser uses this packet type in determining to pre-fetch the indirect buffer.  Supported
+
+#define PM4_PACKET3_CP_INTERRUPT                0xC0004000  // Generate Interrupt from the Command Stream               New for R400
+#define PM4_PACKET3_COND_EXEC                   0xC0004400  // Conditional execution of a sequence of packets
+#define PM4_PACKET3_COND_WRITE                  0xC0004500  // Conditional Write to Memory                              New for R400
+#define PM4_PACKET3_EVENT_WRITE                 0xC0004600  // Generate An Event that Creates a Write to Memory when Completed  New for R400
+#define PM4_PACKET3_INSTR_MATCH                 0xC0004700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_ME_INIT                     0xC0004800  // Initialize CP's Micro Engine                             New for R400
+#define PM4_PACKET3_CONST_PREFETCH              0xC0004900  // Internal packet used only by CP
+#define PM4_PACKET3_MEM_WRITE_CNTR              0xC0004F00
+
+#define PM4_PACKET3_SET_BIN_MASK                0xC0005000  // Sets the 64-bit BIN_MASK register in the PFP
+#define PM4_PACKET3_SET_BIN_SELECT              0xC0005100  // Sets the 64-bit BIN_SELECT register in the PFP
+#define PM4_PACKET3_WAIT_REG_EQ                 0xC0005200  // Wait until a register location is equal to a specific value
+#define PM4_PACKET3_WAIT_REG_GTE                0xC0005300  // Wait until a register location is greater than or equal to a specific value
+#define PM4_PACKET3_INCR_UPDT_STATE             0xC0005500  // Internal Packet Used Only by CP  
+#define PM4_PACKET3_INCR_UPDT_CONST             0xC0005600  // Internal Packet Used Only by CP
+#define PM4_PACKET3_INCR_UPDT_INSTR             0xC0005700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_EVENT_WRITE_SHD             0xC0005800  // Generate a VS|PS_Done Event.
+#define PM4_PACKET3_EVENT_WRITE_CFL             0xC0005900  // Generate a Cach Flush Done Event
+#define PM4_PACKET3_EVENT_WRITE_ZPD             0xC0005B00  // Generate a Cach Flush Done Event
+#define PM4_PACKET3_WAIT_UNTIL_READ             0xC0005C00  // Wait Until a Read completes.
+#define PM4_PACKET3_WAIT_IB_PFD_COMPLETE        0xC0005D00  // Wait Until all Base/Size writes from an IB_PFD packet have completed.
+#define PM4_PACKET3_CONTEXT_UPDATE              0xC0005E00  // Updates the current context if needed.
+
+    /****** New Opcodes For R400 (all decode values are TBD) ******/
+
+
+#endif //  _R400IPT_H_
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h
new file mode 100644
index 000000000000..ad3d829bc94e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h
@@ -0,0 +1,5739 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_MASK_HEADER)
+#define _yamato_MASK_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK            0xffffffffL
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK             0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA                  0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK            0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA                 0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK             0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA                  0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK            0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA                 0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK             0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA                  0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK            0x00000020L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA                 0x00000020L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK                    0x00000100L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT                         0x00000100L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK                     0x00000200L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT                          0x00000200L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK                    0x00000400L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT                         0x00000400L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK               0x00000800L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF                    0x00000800L
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK                 0x00010000L
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE                      0x00010000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK       0x00040000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA            0x00040000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK            0x00080000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF                 0x00080000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK          0x00100000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT               0x00100000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK                  0x00200000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR                       0x00200000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK                0x00400000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN                     0x00400000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK                 0x00800000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN                      0x00800000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK                 0x01000000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN                      0x01000000L
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK           0x00000001L
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA                0x00000001L
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_CL_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_SC_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK                    0x00000001L
+#define PA_SU_VTX_CNTL__PIX_CENTER                         0x00000001L
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK                    0x00000006L
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK                    0x00000038L
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT_MASK                      0x0000ffffL
+#define PA_SU_POINT_SIZE__WIDTH_MASK                       0xffff0000L
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK                  0x0000ffffL
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK                  0xffff0000L
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH_MASK                        0x0000ffffL
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK                0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT                     0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK                 0x00000002L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK                      0x00000002L
+#define PA_SU_SC_MODE_CNTL__FACE_MASK                      0x00000004L
+#define PA_SU_SC_MODE_CNTL__FACE                           0x00000004L
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK                 0x00000018L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK      0x000000e0L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK       0x00000700L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK  0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE       0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK   0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE        0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK   0x00002000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE        0x00002000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK               0x00008000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE                    0x00008000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK  0x00010000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE       0x00010000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK       0x00040000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE            0x00040000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK        0x00080000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST             0x00080000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK            0x00100000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS                 0x00100000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK         0x00200000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA              0x00200000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK         0x00800000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE              0x00800000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK      0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI           0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK          0xffffffffL
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK        0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK           0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK         0xffffffffL
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK          0x00007fffL
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK          0x7fff0000L
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK             0x00000007L
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK              0x0001e000L
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK_MASK                        0x0000ffffL
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK              0x0000ffffL
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK              0x00ff0000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK         0x10000000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER              0x10000000L
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK           0x60000000L
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL_MASK                    0x000000ffL
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK                0x00000100L
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL                     0x00000100L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK            0x00000200L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH                 0x00000200L
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK                   0x00000400L
+#define PA_SC_LINE_CNTL__LAST_PIXEL                        0x00000400L
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK                 0x3fff0000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE     0x80000000L
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK                 0x3fff0000L
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK                 0x7fff0000L
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK                 0x7fff0000L
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK                0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA                     0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK                 0x0000003eL
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK        0x00000080L
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z             0x00000080L
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK           0xffffffffL
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK         0x0000000fL
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK       0x0000ff00L
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY_MASK                    0x80000000L
+#define PA_CL_CNTL_STATUS__CL_BUSY                         0x80000000L
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK                    0x80000000L
+#define PA_SU_CNTL_STATUS__SU_BUSY                         0x80000000L
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY_MASK                    0x80000000L
+#define PA_SC_CNTL_STATUS__SC_BUSY                         0x80000000L
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK    0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write         0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK     0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full          0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK    0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write         0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK     0x00000008L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full          0x00000008L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty   0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full    0x00000020L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty      0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK  0x00000080L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full       0x00000080L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK  0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty       0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK   0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full        0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK  0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty       0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK   0x00000800L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full        0x00000800L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty      0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK       0x00002000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full            0x00002000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty  0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full   0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty  0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full   0x00020000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty    0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full     0x00080000L
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK              0xfff00000L
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet   0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim    0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive  0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK      0x00380000L
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK              0xff000000L
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK             0x001fffffL
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK             0x7f000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK             0x000fff00L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK             0xfc000000L
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event  0x00000080L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK             0xffffff00L
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK             0x00000006L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK             0x00c00000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK             0xf0000000L
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK     0x00000001L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event          0x00000001L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK             0x000000c0L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK             0x00003000L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK             0x000c0000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK          0x00100000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid               0x00100000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait      0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK     0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty          0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK      0x20000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full           0x20000000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK             0x00000030L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK             0x00000c00L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK             0x00180000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet  0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK  0xfc000000L
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK              0xfffffff0L
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK             0x0000001cL
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK   0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty        0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK             0x00007800L
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK   0x00200000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid        0x00200000L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK             0xffc00000L
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK        0x0000000fL
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK       0x000007f0L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK             0x00003800L
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK      0x0003c000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1  0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0  0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK        0x07f00000L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK             0xf8000000L
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK             0x0000000fL
+#define SXIFCCG_DEBUG_REG0__position_address_MASK          0x00000070L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK              0x00000380L
+#define SXIFCCG_DEBUG_REG0__point_address_MASK             0x00001c00L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK              0x0000e000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx   0x00010000L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK              0x00060000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK    0x00780000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK         0x3f800000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK     0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc          0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK     0x80000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel          0x80000000L
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK              0x00000003L
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK            0x0000000cL
+#define SXIFCCG_DEBUG_REG1__available_positions_MASK       0x00000070L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK              0x00000780L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK        0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance             0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK           0x00007000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector  0x00008000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK              0x000f0000L
+#define SXIFCCG_DEBUG_REG1__aux_sel_MASK                   0x00100000L
+#define SXIFCCG_DEBUG_REG1__aux_sel                        0x00100000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK              0x00600000L
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK              0x01800000L
+#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK          0xfe000000L
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent_MASK                   0x00000001L
+#define SXIFCCG_DEBUG_REG2__sx_sent                        0x00000001L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK              0x00000002L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3                   0x00000002L
+#define SXIFCCG_DEBUG_REG2__sx_aux_MASK                    0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_aux                         0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK           0x000001f8L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK          0x0000fe00L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK              0x00010000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2                   0x00010000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx    0x00020000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK              0x000c0000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK              0x03c00000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK   0x04000000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded        0x04000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK     0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty          0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK      0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full           0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK  0xe0000000L
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK              0x00000010L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3                   0x00000010L
+#define SXIFCCG_DEBUG_REG3__available_positions_MASK       0x000000e0L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK              0x00000f00L
+#define SXIFCCG_DEBUG_REG3__current_state_MASK             0x00003000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK         0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty              0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK          0x00008000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full               0x00008000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK              0x00030000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK    0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty         0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK     0x00080000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full          0x00080000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK   0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty        0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK    0x00200000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full         0x00200000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK              0xffc00000L
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state_MASK               0x0000001fL
+#define SETUP_DEBUG_REG0__pmode_state_MASK                 0x000007e0L
+#define SETUP_DEBUG_REG0__ge_stallb_MASK                   0x00000800L
+#define SETUP_DEBUG_REG0__ge_stallb                        0x00000800L
+#define SETUP_DEBUG_REG0__geom_enable_MASK                 0x00001000L
+#define SETUP_DEBUG_REG0__geom_enable                      0x00001000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK           0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr                0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_rtr_MASK                 0x00004000L
+#define SETUP_DEBUG_REG0__su_clip_rtr                      0x00004000L
+#define SETUP_DEBUG_REG0__pfifo_busy_MASK                  0x00008000L
+#define SETUP_DEBUG_REG0__pfifo_busy                       0x00008000L
+#define SETUP_DEBUG_REG0__su_cntl_busy_MASK                0x00010000L
+#define SETUP_DEBUG_REG0__su_cntl_busy                     0x00010000L
+#define SETUP_DEBUG_REG0__geom_busy_MASK                   0x00020000L
+#define SETUP_DEBUG_REG0__geom_busy                        0x00020000L
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG4__null_prim_gated_MASK             0x00000800L
+#define SETUP_DEBUG_REG4__null_prim_gated                  0x00000800L
+#define SETUP_DEBUG_REG4__backfacing_gated_MASK            0x00001000L
+#define SETUP_DEBUG_REG4__backfacing_gated                 0x00001000L
+#define SETUP_DEBUG_REG4__st_indx_gated_MASK               0x0000e000L
+#define SETUP_DEBUG_REG4__clipped_gated_MASK               0x00010000L
+#define SETUP_DEBUG_REG4__clipped_gated                    0x00010000L
+#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK          0x000e0000L
+#define SETUP_DEBUG_REG4__xmajor_gated_MASK                0x00100000L
+#define SETUP_DEBUG_REG4__xmajor_gated                     0x00100000L
+#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK          0x00600000L
+#define SETUP_DEBUG_REG4__type_gated_MASK                  0x03800000L
+#define SETUP_DEBUG_REG4__fpov_gated_MASK                  0x04000000L
+#define SETUP_DEBUG_REG4__fpov_gated                       0x04000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK            0x08000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated                 0x08000000L
+#define SETUP_DEBUG_REG4__event_gated_MASK                 0x10000000L
+#define SETUP_DEBUG_REG4__event_gated                      0x10000000L
+#define SETUP_DEBUG_REG4__eop_gated_MASK                   0x20000000L
+#define SETUP_DEBUG_REG4__eop_gated                        0x20000000L
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK       0x003ff800L
+#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK         0x00c00000L
+#define SETUP_DEBUG_REG5__event_id_gated_MASK              0x1f000000L
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1_MASK                      0x00000001L
+#define SC_DEBUG_0__pa_freeze_b1                           0x00000001L
+#define SC_DEBUG_0__pa_sc_valid_MASK                       0x00000002L
+#define SC_DEBUG_0__pa_sc_valid                            0x00000002L
+#define SC_DEBUG_0__pa_sc_phase_MASK                       0x0000001cL
+#define SC_DEBUG_0__cntx_cnt_MASK                          0x00000fe0L
+#define SC_DEBUG_0__decr_cntx_cnt_MASK                     0x00001000L
+#define SC_DEBUG_0__decr_cntx_cnt                          0x00001000L
+#define SC_DEBUG_0__incr_cntx_cnt_MASK                     0x00002000L
+#define SC_DEBUG_0__incr_cntx_cnt                          0x00002000L
+#define SC_DEBUG_0__trigger_MASK                           0x80000000L
+#define SC_DEBUG_0__trigger                                0x80000000L
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state_MASK                          0x00000007L
+#define SC_DEBUG_1__em1_data_ready_MASK                    0x00000008L
+#define SC_DEBUG_1__em1_data_ready                         0x00000008L
+#define SC_DEBUG_1__em2_data_ready_MASK                    0x00000010L
+#define SC_DEBUG_1__em2_data_ready                         0x00000010L
+#define SC_DEBUG_1__move_em1_to_em2_MASK                   0x00000020L
+#define SC_DEBUG_1__move_em1_to_em2                        0x00000020L
+#define SC_DEBUG_1__ef_data_ready_MASK                     0x00000040L
+#define SC_DEBUG_1__ef_data_ready                          0x00000040L
+#define SC_DEBUG_1__ef_state_MASK                          0x00000180L
+#define SC_DEBUG_1__pipe_valid_MASK                        0x00000200L
+#define SC_DEBUG_1__pipe_valid                             0x00000200L
+#define SC_DEBUG_1__trigger_MASK                           0x80000000L
+#define SC_DEBUG_1__trigger                                0x80000000L
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly_MASK                        0x00000001L
+#define SC_DEBUG_2__rc_rtr_dly                             0x00000001L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK              0x00000002L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1                   0x00000002L
+#define SC_DEBUG_2__pipe_freeze_b_MASK                     0x00000008L
+#define SC_DEBUG_2__pipe_freeze_b                          0x00000008L
+#define SC_DEBUG_2__prim_rts_MASK                          0x00000010L
+#define SC_DEBUG_2__prim_rts                               0x00000010L
+#define SC_DEBUG_2__next_prim_rts_dly_MASK                 0x00000020L
+#define SC_DEBUG_2__next_prim_rts_dly                      0x00000020L
+#define SC_DEBUG_2__next_prim_rtr_dly_MASK                 0x00000040L
+#define SC_DEBUG_2__next_prim_rtr_dly                      0x00000040L
+#define SC_DEBUG_2__pre_stage1_rts_d1_MASK                 0x00000080L
+#define SC_DEBUG_2__pre_stage1_rts_d1                      0x00000080L
+#define SC_DEBUG_2__stage0_rts_MASK                        0x00000100L
+#define SC_DEBUG_2__stage0_rts                             0x00000100L
+#define SC_DEBUG_2__phase_rts_dly_MASK                     0x00000200L
+#define SC_DEBUG_2__phase_rts_dly                          0x00000200L
+#define SC_DEBUG_2__end_of_prim_s1_dly_MASK                0x00008000L
+#define SC_DEBUG_2__end_of_prim_s1_dly                     0x00008000L
+#define SC_DEBUG_2__pass_empty_prim_s1_MASK                0x00010000L
+#define SC_DEBUG_2__pass_empty_prim_s1                     0x00010000L
+#define SC_DEBUG_2__event_id_s1_MASK                       0x003e0000L
+#define SC_DEBUG_2__event_s1_MASK                          0x00400000L
+#define SC_DEBUG_2__event_s1                               0x00400000L
+#define SC_DEBUG_2__trigger_MASK                           0x80000000L
+#define SC_DEBUG_2__trigger                                0x80000000L
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1_MASK                         0x000007ffL
+#define SC_DEBUG_3__y_curr_s1_MASK                         0x003ff800L
+#define SC_DEBUG_3__trigger_MASK                           0x80000000L
+#define SC_DEBUG_3__trigger                                0x80000000L
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_4__y_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_4__y_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_4__y_dir_s1                               0x10000000L
+#define SC_DEBUG_4__trigger_MASK                           0x80000000L
+#define SC_DEBUG_4__trigger                                0x80000000L
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_5__x_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_5__x_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_5__x_dir_s1                               0x10000000L
+#define SC_DEBUG_5__trigger_MASK                           0x80000000L
+#define SC_DEBUG_5__trigger                                0x80000000L
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty_MASK                        0x00000001L
+#define SC_DEBUG_6__z_ff_empty                             0x00000001L
+#define SC_DEBUG_6__qmcntl_ff_empty_MASK                   0x00000002L
+#define SC_DEBUG_6__qmcntl_ff_empty                        0x00000002L
+#define SC_DEBUG_6__xy_ff_empty_MASK                       0x00000004L
+#define SC_DEBUG_6__xy_ff_empty                            0x00000004L
+#define SC_DEBUG_6__event_flag_MASK                        0x00000008L
+#define SC_DEBUG_6__event_flag                             0x00000008L
+#define SC_DEBUG_6__z_mask_needed_MASK                     0x00000010L
+#define SC_DEBUG_6__z_mask_needed                          0x00000010L
+#define SC_DEBUG_6__state_MASK                             0x000000e0L
+#define SC_DEBUG_6__state_delayed_MASK                     0x00000700L
+#define SC_DEBUG_6__data_valid_MASK                        0x00000800L
+#define SC_DEBUG_6__data_valid                             0x00000800L
+#define SC_DEBUG_6__data_valid_d_MASK                      0x00001000L
+#define SC_DEBUG_6__data_valid_d                           0x00001000L
+#define SC_DEBUG_6__tilex_delayed_MASK                     0x003fe000L
+#define SC_DEBUG_6__tiley_delayed_MASK                     0x7fc00000L
+#define SC_DEBUG_6__trigger_MASK                           0x80000000L
+#define SC_DEBUG_6__trigger                                0x80000000L
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag_MASK                        0x00000001L
+#define SC_DEBUG_7__event_flag                             0x00000001L
+#define SC_DEBUG_7__deallocate_MASK                        0x0000000eL
+#define SC_DEBUG_7__fpos_MASK                              0x00000010L
+#define SC_DEBUG_7__fpos                                   0x00000010L
+#define SC_DEBUG_7__sr_prim_we_MASK                        0x00000020L
+#define SC_DEBUG_7__sr_prim_we                             0x00000020L
+#define SC_DEBUG_7__last_tile_MASK                         0x00000040L
+#define SC_DEBUG_7__last_tile                              0x00000040L
+#define SC_DEBUG_7__tile_ff_we_MASK                        0x00000080L
+#define SC_DEBUG_7__tile_ff_we                             0x00000080L
+#define SC_DEBUG_7__qs_data_valid_MASK                     0x00000100L
+#define SC_DEBUG_7__qs_data_valid                          0x00000100L
+#define SC_DEBUG_7__qs_q0_y_MASK                           0x00000600L
+#define SC_DEBUG_7__qs_q0_x_MASK                           0x00001800L
+#define SC_DEBUG_7__qs_q0_valid_MASK                       0x00002000L
+#define SC_DEBUG_7__qs_q0_valid                            0x00002000L
+#define SC_DEBUG_7__prim_ff_we_MASK                        0x00004000L
+#define SC_DEBUG_7__prim_ff_we                             0x00004000L
+#define SC_DEBUG_7__tile_ff_re_MASK                        0x00008000L
+#define SC_DEBUG_7__tile_ff_re                             0x00008000L
+#define SC_DEBUG_7__fw_prim_data_valid_MASK                0x00010000L
+#define SC_DEBUG_7__fw_prim_data_valid                     0x00010000L
+#define SC_DEBUG_7__last_quad_of_tile_MASK                 0x00020000L
+#define SC_DEBUG_7__last_quad_of_tile                      0x00020000L
+#define SC_DEBUG_7__first_quad_of_tile_MASK                0x00040000L
+#define SC_DEBUG_7__first_quad_of_tile                     0x00040000L
+#define SC_DEBUG_7__first_quad_of_prim_MASK                0x00080000L
+#define SC_DEBUG_7__first_quad_of_prim                     0x00080000L
+#define SC_DEBUG_7__new_prim_MASK                          0x00100000L
+#define SC_DEBUG_7__new_prim                               0x00100000L
+#define SC_DEBUG_7__load_new_tile_data_MASK                0x00200000L
+#define SC_DEBUG_7__load_new_tile_data                     0x00200000L
+#define SC_DEBUG_7__state_MASK                             0x00c00000L
+#define SC_DEBUG_7__fifos_ready_MASK                       0x01000000L
+#define SC_DEBUG_7__fifos_ready                            0x01000000L
+#define SC_DEBUG_7__trigger_MASK                           0x80000000L
+#define SC_DEBUG_7__trigger                                0x80000000L
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last_MASK                       0x00000001L
+#define SC_DEBUG_8__sample_last                            0x00000001L
+#define SC_DEBUG_8__sample_mask_MASK                       0x0000001eL
+#define SC_DEBUG_8__sample_y_MASK                          0x00000060L
+#define SC_DEBUG_8__sample_x_MASK                          0x00000180L
+#define SC_DEBUG_8__sample_send_MASK                       0x00000200L
+#define SC_DEBUG_8__sample_send                            0x00000200L
+#define SC_DEBUG_8__next_cycle_MASK                        0x00000c00L
+#define SC_DEBUG_8__ez_sample_ff_full_MASK                 0x00001000L
+#define SC_DEBUG_8__ez_sample_ff_full                      0x00001000L
+#define SC_DEBUG_8__rb_sc_samp_rtr_MASK                    0x00002000L
+#define SC_DEBUG_8__rb_sc_samp_rtr                         0x00002000L
+#define SC_DEBUG_8__num_samples_MASK                       0x0000c000L
+#define SC_DEBUG_8__last_quad_of_tile_MASK                 0x00010000L
+#define SC_DEBUG_8__last_quad_of_tile                      0x00010000L
+#define SC_DEBUG_8__last_quad_of_prim_MASK                 0x00020000L
+#define SC_DEBUG_8__last_quad_of_prim                      0x00020000L
+#define SC_DEBUG_8__first_quad_of_prim_MASK                0x00040000L
+#define SC_DEBUG_8__first_quad_of_prim                     0x00040000L
+#define SC_DEBUG_8__sample_we_MASK                         0x00080000L
+#define SC_DEBUG_8__sample_we                              0x00080000L
+#define SC_DEBUG_8__fpos_MASK                              0x00100000L
+#define SC_DEBUG_8__fpos                                   0x00100000L
+#define SC_DEBUG_8__event_id_MASK                          0x03e00000L
+#define SC_DEBUG_8__event_flag_MASK                        0x04000000L
+#define SC_DEBUG_8__event_flag                             0x04000000L
+#define SC_DEBUG_8__fw_prim_data_valid_MASK                0x08000000L
+#define SC_DEBUG_8__fw_prim_data_valid                     0x08000000L
+#define SC_DEBUG_8__trigger_MASK                           0x80000000L
+#define SC_DEBUG_8__trigger                                0x80000000L
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send_MASK                        0x00000001L
+#define SC_DEBUG_9__rb_sc_send                             0x00000001L
+#define SC_DEBUG_9__rb_sc_ez_mask_MASK                     0x0000001eL
+#define SC_DEBUG_9__fifo_data_ready_MASK                   0x00000020L
+#define SC_DEBUG_9__fifo_data_ready                        0x00000020L
+#define SC_DEBUG_9__early_z_enable_MASK                    0x00000040L
+#define SC_DEBUG_9__early_z_enable                         0x00000040L
+#define SC_DEBUG_9__mask_state_MASK                        0x00000180L
+#define SC_DEBUG_9__next_ez_mask_MASK                      0x01fffe00L
+#define SC_DEBUG_9__mask_ready_MASK                        0x02000000L
+#define SC_DEBUG_9__mask_ready                             0x02000000L
+#define SC_DEBUG_9__drop_sample_MASK                       0x04000000L
+#define SC_DEBUG_9__drop_sample                            0x04000000L
+#define SC_DEBUG_9__fetch_new_sample_data_MASK             0x08000000L
+#define SC_DEBUG_9__fetch_new_sample_data                  0x08000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK          0x10000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask               0x10000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK         0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data              0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK           0x40000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data                0x40000000L
+#define SC_DEBUG_9__trigger_MASK                           0x80000000L
+#define SC_DEBUG_9__trigger                                0x80000000L
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask_MASK             0x0000ffffL
+#define SC_DEBUG_10__trigger_MASK                          0x80000000L
+#define SC_DEBUG_10__trigger                               0x80000000L
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready_MASK             0x00000001L
+#define SC_DEBUG_11__ez_sample_data_ready                  0x00000001L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK        0x00000002L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data             0x00000002L
+#define SC_DEBUG_11__ez_prim_data_ready_MASK               0x00000004L
+#define SC_DEBUG_11__ez_prim_data_ready                    0x00000004L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK          0x00000008L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data               0x00000008L
+#define SC_DEBUG_11__iterator_input_fz_MASK                0x00000010L
+#define SC_DEBUG_11__iterator_input_fz                     0x00000010L
+#define SC_DEBUG_11__packer_send_quads_MASK                0x00000020L
+#define SC_DEBUG_11__packer_send_quads                     0x00000020L
+#define SC_DEBUG_11__packer_send_cmd_MASK                  0x00000040L
+#define SC_DEBUG_11__packer_send_cmd                       0x00000040L
+#define SC_DEBUG_11__packer_send_event_MASK                0x00000080L
+#define SC_DEBUG_11__packer_send_event                     0x00000080L
+#define SC_DEBUG_11__next_state_MASK                       0x00000700L
+#define SC_DEBUG_11__state_MASK                            0x00003800L
+#define SC_DEBUG_11__stall_MASK                            0x00004000L
+#define SC_DEBUG_11__stall                                 0x00004000L
+#define SC_DEBUG_11__trigger_MASK                          0x80000000L
+#define SC_DEBUG_11__trigger                               0x80000000L
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff_MASK            0x00000001L
+#define SC_DEBUG_12__SQ_iterator_free_buff                 0x00000001L
+#define SC_DEBUG_12__event_id_MASK                         0x0000003eL
+#define SC_DEBUG_12__event_flag_MASK                       0x00000040L
+#define SC_DEBUG_12__event_flag                            0x00000040L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK          0x00000080L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly               0x00000080L
+#define SC_DEBUG_12__itercmdfifo_full_MASK                 0x00000100L
+#define SC_DEBUG_12__itercmdfifo_full                      0x00000100L
+#define SC_DEBUG_12__itercmdfifo_empty_MASK                0x00000200L
+#define SC_DEBUG_12__itercmdfifo_empty                     0x00000200L
+#define SC_DEBUG_12__iter_ds_one_clk_command_MASK          0x00000400L
+#define SC_DEBUG_12__iter_ds_one_clk_command               0x00000400L
+#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK             0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_prim0                  0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_vector_MASK            0x00001000L
+#define SC_DEBUG_12__iter_ds_end_of_vector                 0x00001000L
+#define SC_DEBUG_12__iter_qdhit0_MASK                      0x00002000L
+#define SC_DEBUG_12__iter_qdhit0                           0x00002000L
+#define SC_DEBUG_12__bc_use_centers_reg_MASK               0x00004000L
+#define SC_DEBUG_12__bc_use_centers_reg                    0x00004000L
+#define SC_DEBUG_12__bc_output_xy_reg_MASK                 0x00008000L
+#define SC_DEBUG_12__bc_output_xy_reg                      0x00008000L
+#define SC_DEBUG_12__iter_phase_out_MASK                   0x00030000L
+#define SC_DEBUG_12__iter_phase_reg_MASK                   0x000c0000L
+#define SC_DEBUG_12__iterator_SP_valid_MASK                0x00100000L
+#define SC_DEBUG_12__iterator_SP_valid                     0x00100000L
+#define SC_DEBUG_12__eopv_reg_MASK                         0x00200000L
+#define SC_DEBUG_12__eopv_reg                              0x00200000L
+#define SC_DEBUG_12__one_clk_cmd_reg_MASK                  0x00400000L
+#define SC_DEBUG_12__one_clk_cmd_reg                       0x00400000L
+#define SC_DEBUG_12__iter_dx_end_of_prim_MASK              0x00800000L
+#define SC_DEBUG_12__iter_dx_end_of_prim                   0x00800000L
+#define SC_DEBUG_12__trigger_MASK                          0x80000000L
+#define SC_DEBUG_12__trigger                               0x80000000L
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK                  0x00000001L
+#define GFX_COPY_STATE__SRC_STATE_ID                       0x00000001L
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK                 0x0000003fL
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK             0x000000c0L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK                0x00000800L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE                     0x00000800L
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK                   0x00001000L
+#define VGT_DRAW_INITIATOR__NOT_EOP                        0x00001000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK               0x00002000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX                    0x00002000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK     0x00004000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE          0x00004000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK           0x00008000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE                0x00008000L
+#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK               0xffff0000L
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK               0x0000003fL
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR_MASK                       0xffffffffL
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_DMA_SIZE__SWAP_MODE_MASK                       0xc0000000L
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK                   0xffffffffL
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK                    0x00ffffffL
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK                    0x00ffffffL
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK                  0x00ffffffL
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK  0x00000007L
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK            0x00000003L
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK      0x00ffffffL
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC_MASK                             0x0000ffffL
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK            0x0000001fL
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK             0x00000001L
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID                  0x00000001L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK             0x00010000L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID                  0x00010000L
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK                0x0000001fL
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK                     0x00000001L
+#define VGT_CNTL_STATUS__VGT_BUSY                          0x00000001L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK                 0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY                      0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK             0x00000004L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY                  0x00000004L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK                 0x00000008L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY                      0x00000008L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK                  0x00000010L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY                       0x00000010L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK                 0x00000020L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY                      0x00000020L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK                  0x00000040L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY                       0x00000040L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK                 0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY                      0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK            0x00000100L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY                 0x00000100L
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy_MASK                   0x00000001L
+#define VGT_DEBUG_REG0__te_grp_busy                        0x00000001L
+#define VGT_DEBUG_REG0__pt_grp_busy_MASK                   0x00000002L
+#define VGT_DEBUG_REG0__pt_grp_busy                        0x00000002L
+#define VGT_DEBUG_REG0__vr_grp_busy_MASK                   0x00000004L
+#define VGT_DEBUG_REG0__vr_grp_busy                        0x00000004L
+#define VGT_DEBUG_REG0__dma_request_busy_MASK              0x00000008L
+#define VGT_DEBUG_REG0__dma_request_busy                   0x00000008L
+#define VGT_DEBUG_REG0__out_busy_MASK                      0x00000010L
+#define VGT_DEBUG_REG0__out_busy                           0x00000010L
+#define VGT_DEBUG_REG0__grp_backend_busy_MASK              0x00000020L
+#define VGT_DEBUG_REG0__grp_backend_busy                   0x00000020L
+#define VGT_DEBUG_REG0__grp_busy_MASK                      0x00000040L
+#define VGT_DEBUG_REG0__grp_busy                           0x00000040L
+#define VGT_DEBUG_REG0__dma_busy_MASK                      0x00000080L
+#define VGT_DEBUG_REG0__dma_busy                           0x00000080L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK         0x00000100L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy              0x00000100L
+#define VGT_DEBUG_REG0__rbiu_busy_MASK                     0x00000200L
+#define VGT_DEBUG_REG0__rbiu_busy                          0x00000200L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK      0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended           0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK               0x00000800L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy                    0x00000800L
+#define VGT_DEBUG_REG0__vgt_busy_extended_MASK             0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_extended                  0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_MASK                      0x00002000L
+#define VGT_DEBUG_REG0__vgt_busy                           0x00002000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK       0x00004000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out            0x00004000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK          0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy               0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK                 0x00010000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy                      0x00010000L
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read_MASK              0x00000001L
+#define VGT_DEBUG_REG1__out_te_data_read                   0x00000001L
+#define VGT_DEBUG_REG1__te_out_data_valid_MASK             0x00000002L
+#define VGT_DEBUG_REG1__te_out_data_valid                  0x00000002L
+#define VGT_DEBUG_REG1__out_pt_prim_read_MASK              0x00000004L
+#define VGT_DEBUG_REG1__out_pt_prim_read                   0x00000004L
+#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK             0x00000008L
+#define VGT_DEBUG_REG1__pt_out_prim_valid                  0x00000008L
+#define VGT_DEBUG_REG1__out_pt_data_read_MASK              0x00000010L
+#define VGT_DEBUG_REG1__out_pt_data_read                   0x00000010L
+#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK             0x00000020L
+#define VGT_DEBUG_REG1__pt_out_indx_valid                  0x00000020L
+#define VGT_DEBUG_REG1__out_vr_prim_read_MASK              0x00000040L
+#define VGT_DEBUG_REG1__out_vr_prim_read                   0x00000040L
+#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK             0x00000080L
+#define VGT_DEBUG_REG1__vr_out_prim_valid                  0x00000080L
+#define VGT_DEBUG_REG1__out_vr_indx_read_MASK              0x00000100L
+#define VGT_DEBUG_REG1__out_vr_indx_read                   0x00000100L
+#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK             0x00000200L
+#define VGT_DEBUG_REG1__vr_out_indx_valid                  0x00000200L
+#define VGT_DEBUG_REG1__te_grp_read_MASK                   0x00000400L
+#define VGT_DEBUG_REG1__te_grp_read                        0x00000400L
+#define VGT_DEBUG_REG1__grp_te_valid_MASK                  0x00000800L
+#define VGT_DEBUG_REG1__grp_te_valid                       0x00000800L
+#define VGT_DEBUG_REG1__pt_grp_read_MASK                   0x00001000L
+#define VGT_DEBUG_REG1__pt_grp_read                        0x00001000L
+#define VGT_DEBUG_REG1__grp_pt_valid_MASK                  0x00002000L
+#define VGT_DEBUG_REG1__grp_pt_valid                       0x00002000L
+#define VGT_DEBUG_REG1__vr_grp_read_MASK                   0x00004000L
+#define VGT_DEBUG_REG1__vr_grp_read                        0x00004000L
+#define VGT_DEBUG_REG1__grp_vr_valid_MASK                  0x00008000L
+#define VGT_DEBUG_REG1__grp_vr_valid                       0x00008000L
+#define VGT_DEBUG_REG1__grp_dma_read_MASK                  0x00010000L
+#define VGT_DEBUG_REG1__grp_dma_read                       0x00010000L
+#define VGT_DEBUG_REG1__dma_grp_valid_MASK                 0x00020000L
+#define VGT_DEBUG_REG1__dma_grp_valid                      0x00020000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK              0x00040000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read                   0x00040000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK             0x00080000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid                  0x00080000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK                    0x00100000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr                         0x00100000L
+#define VGT_DEBUG_REG1__VGT_MH_send_MASK                   0x00200000L
+#define VGT_DEBUG_REG1__VGT_MH_send                        0x00200000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK             0x00400000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr                  0x00400000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK            0x00800000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send                 0x00800000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK             0x01000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr                  0x01000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK            0x02000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send                 0x02000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK             0x04000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr                  0x04000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK            0x08000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send                 0x08000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK                    0x10000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr                         0x10000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send_MASK                   0x20000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send                        0x20000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK                0x40000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q                     0x40000000L
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en_MASK                    0x00000001L
+#define VGT_DEBUG_REG3__vgt_clk_en                         0x00000001L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK              0x00000002L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en                   0x00000002L
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK          0x0000001fL
+#define VGT_DEBUG_REG6__right_word_indx_q_MASK             0x000003e0L
+#define VGT_DEBUG_REG6__input_data_valid_MASK              0x00000400L
+#define VGT_DEBUG_REG6__input_data_valid                   0x00000400L
+#define VGT_DEBUG_REG6__input_data_xfer_MASK               0x00000800L
+#define VGT_DEBUG_REG6__input_data_xfer                    0x00000800L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK        0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q             0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK        0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d             0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK    0x00004000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d         0x00004000L
+#define VGT_DEBUG_REG6__space_avail_from_shift_MASK        0x00008000L
+#define VGT_DEBUG_REG6__space_avail_from_shift             0x00008000L
+#define VGT_DEBUG_REG6__shifter_first_load_MASK            0x00010000L
+#define VGT_DEBUG_REG6__shifter_first_load                 0x00010000L
+#define VGT_DEBUG_REG6__di_state_sel_q_MASK                0x00020000L
+#define VGT_DEBUG_REG6__di_state_sel_q                     0x00020000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q   0x00040000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK         0x00080000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q              0x00080000L
+#define VGT_DEBUG_REG6__di_event_flag_q_MASK               0x00100000L
+#define VGT_DEBUG_REG6__di_event_flag_q                    0x00100000L
+#define VGT_DEBUG_REG6__read_draw_initiator_MASK           0x00200000L
+#define VGT_DEBUG_REG6__read_draw_initiator                0x00200000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK   0x00400000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter        0x00400000L
+#define VGT_DEBUG_REG6__last_shift_of_packet_MASK          0x00800000L
+#define VGT_DEBUG_REG6__last_shift_of_packet               0x00800000L
+#define VGT_DEBUG_REG6__last_decr_of_packet_MASK           0x01000000L
+#define VGT_DEBUG_REG6__last_decr_of_packet                0x01000000L
+#define VGT_DEBUG_REG6__extract_vector_MASK                0x02000000L
+#define VGT_DEBUG_REG6__extract_vector                     0x02000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr_MASK                0x04000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr                     0x04000000L
+#define VGT_DEBUG_REG6__destination_rtr_MASK               0x08000000L
+#define VGT_DEBUG_REG6__destination_rtr                    0x08000000L
+#define VGT_DEBUG_REG6__grp_trigger_MASK                   0x10000000L
+#define VGT_DEBUG_REG6__grp_trigger                        0x10000000L
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q_MASK            0x0000ffffL
+#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK       0x000f0000L
+#define VGT_DEBUG_REG7__shift_amount_extract_MASK          0x00f00000L
+#define VGT_DEBUG_REG7__di_prim_type_q_MASK                0x3f000000L
+#define VGT_DEBUG_REG7__current_source_sel_MASK            0xc0000000L
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel_MASK            0x00000003L
+#define VGT_DEBUG_REG8__left_word_indx_q_MASK              0x0000007cL
+#define VGT_DEBUG_REG8__input_data_cnt_MASK                0x00000f80L
+#define VGT_DEBUG_REG8__input_data_lsw_MASK                0x0001f000L
+#define VGT_DEBUG_REG8__input_data_msw_MASK                0x003e0000L
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q_MASK                 0x0000001fL
+#define VGT_DEBUG_REG9__next_stride_d_MASK                 0x000003e0L
+#define VGT_DEBUG_REG9__current_shift_q_MASK               0x00007c00L
+#define VGT_DEBUG_REG9__current_shift_d_MASK               0x000f8000L
+#define VGT_DEBUG_REG9__current_stride_q_MASK              0x01f00000L
+#define VGT_DEBUG_REG9__current_stride_d_MASK              0x3e000000L
+#define VGT_DEBUG_REG9__grp_trigger_MASK                   0x40000000L
+#define VGT_DEBUG_REG9__grp_trigger                        0x40000000L
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0      0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0    0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0    0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L
+#define VGT_DEBUG_REG10__di_state_sel_q_MASK               0x00000010L
+#define VGT_DEBUG_REG10__di_state_sel_q                    0x00000010L
+#define VGT_DEBUG_REG10__last_decr_of_packet_MASK          0x00000020L
+#define VGT_DEBUG_REG10__last_decr_of_packet               0x00000020L
+#define VGT_DEBUG_REG10__bin_valid_MASK                    0x00000040L
+#define VGT_DEBUG_REG10__bin_valid                         0x00000040L
+#define VGT_DEBUG_REG10__read_block_MASK                   0x00000080L
+#define VGT_DEBUG_REG10__read_block                        0x00000080L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK       0x00000100L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read            0x00000100L
+#define VGT_DEBUG_REG10__last_bit_enable_q_MASK            0x00000200L
+#define VGT_DEBUG_REG10__last_bit_enable_q                 0x00000200L
+#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK            0x00000400L
+#define VGT_DEBUG_REG10__last_bit_end_di_q                 0x00000400L
+#define VGT_DEBUG_REG10__selected_data_MASK                0x0007f800L
+#define VGT_DEBUG_REG10__mask_input_data_MASK              0x07f80000L
+#define VGT_DEBUG_REG10__gap_q_MASK                        0x08000000L
+#define VGT_DEBUG_REG10__gap_q                             0x08000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK            0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z                 0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK            0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y                 0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK            0x40000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x                 0x40000000L
+#define VGT_DEBUG_REG10__grp_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG10__grp_trigger                       0x80000000L
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK         0x0000001fL
+#define VGT_DEBUG_REG12__right_word_indx_q_MASK            0x000003e0L
+#define VGT_DEBUG_REG12__input_data_valid_MASK             0x00000400L
+#define VGT_DEBUG_REG12__input_data_valid                  0x00000400L
+#define VGT_DEBUG_REG12__input_data_xfer_MASK              0x00000800L
+#define VGT_DEBUG_REG12__input_data_xfer                   0x00000800L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK       0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q            0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK       0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d            0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK   0x00004000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d        0x00004000L
+#define VGT_DEBUG_REG12__space_avail_from_shift_MASK       0x00008000L
+#define VGT_DEBUG_REG12__space_avail_from_shift            0x00008000L
+#define VGT_DEBUG_REG12__shifter_first_load_MASK           0x00010000L
+#define VGT_DEBUG_REG12__shifter_first_load                0x00010000L
+#define VGT_DEBUG_REG12__di_state_sel_q_MASK               0x00020000L
+#define VGT_DEBUG_REG12__di_state_sel_q                    0x00020000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q  0x00040000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK        0x00080000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q             0x00080000L
+#define VGT_DEBUG_REG12__di_event_flag_q_MASK              0x00100000L
+#define VGT_DEBUG_REG12__di_event_flag_q                   0x00100000L
+#define VGT_DEBUG_REG12__read_draw_initiator_MASK          0x00200000L
+#define VGT_DEBUG_REG12__read_draw_initiator               0x00200000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK  0x00400000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter       0x00400000L
+#define VGT_DEBUG_REG12__last_shift_of_packet_MASK         0x00800000L
+#define VGT_DEBUG_REG12__last_shift_of_packet              0x00800000L
+#define VGT_DEBUG_REG12__last_decr_of_packet_MASK          0x01000000L
+#define VGT_DEBUG_REG12__last_decr_of_packet               0x01000000L
+#define VGT_DEBUG_REG12__extract_vector_MASK               0x02000000L
+#define VGT_DEBUG_REG12__extract_vector                    0x02000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr_MASK               0x04000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr                    0x04000000L
+#define VGT_DEBUG_REG12__destination_rtr_MASK              0x08000000L
+#define VGT_DEBUG_REG12__destination_rtr                   0x08000000L
+#define VGT_DEBUG_REG12__bgrp_trigger_MASK                 0x10000000L
+#define VGT_DEBUG_REG12__bgrp_trigger                      0x10000000L
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q_MASK           0x0000ffffL
+#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK      0x000f0000L
+#define VGT_DEBUG_REG13__shift_amount_extract_MASK         0x00f00000L
+#define VGT_DEBUG_REG13__di_prim_type_q_MASK               0x3f000000L
+#define VGT_DEBUG_REG13__current_source_sel_MASK           0xc0000000L
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel_MASK           0x00000003L
+#define VGT_DEBUG_REG14__left_word_indx_q_MASK             0x0000007cL
+#define VGT_DEBUG_REG14__input_data_cnt_MASK               0x00000f80L
+#define VGT_DEBUG_REG14__input_data_lsw_MASK               0x0001f000L
+#define VGT_DEBUG_REG14__input_data_msw_MASK               0x003e0000L
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q_MASK                0x0000001fL
+#define VGT_DEBUG_REG15__next_stride_d_MASK                0x000003e0L
+#define VGT_DEBUG_REG15__current_shift_q_MASK              0x00007c00L
+#define VGT_DEBUG_REG15__current_shift_d_MASK              0x000f8000L
+#define VGT_DEBUG_REG15__current_stride_q_MASK             0x01f00000L
+#define VGT_DEBUG_REG15__current_stride_d_MASK             0x3e000000L
+#define VGT_DEBUG_REG15__bgrp_trigger_MASK                 0x40000000L
+#define VGT_DEBUG_REG15__bgrp_trigger                      0x40000000L
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK    0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full         0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK   0x00000002L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty        0x00000002L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK     0x00000004L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read          0x00000004L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK      0x00000008L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we           0x00000008L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK     0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full          0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK    0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty         0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK     0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q          0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK       0x00000080L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we            0x00000080L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK           0x00000100L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill                0x00000100L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK           0x00000200L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid                0x00000200L
+#define VGT_DEBUG_REG16__rst_last_bit_MASK                 0x00000400L
+#define VGT_DEBUG_REG16__rst_last_bit                      0x00000400L
+#define VGT_DEBUG_REG16__current_state_q_MASK              0x00000800L
+#define VGT_DEBUG_REG16__current_state_q                   0x00000800L
+#define VGT_DEBUG_REG16__old_state_q_MASK                  0x00001000L
+#define VGT_DEBUG_REG16__old_state_q                       0x00001000L
+#define VGT_DEBUG_REG16__old_state_en_MASK                 0x00002000L
+#define VGT_DEBUG_REG16__old_state_en                      0x00002000L
+#define VGT_DEBUG_REG16__prev_last_bit_q_MASK              0x00004000L
+#define VGT_DEBUG_REG16__prev_last_bit_q                   0x00004000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK               0x00008000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q                    0x00008000L
+#define VGT_DEBUG_REG16__last_bit_block_q_MASK             0x00010000L
+#define VGT_DEBUG_REG16__last_bit_block_q                  0x00010000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK             0x00020000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q                  0x00020000L
+#define VGT_DEBUG_REG16__load_empty_reg_MASK               0x00040000L
+#define VGT_DEBUG_REG16__load_empty_reg                    0x00040000L
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK     0x07f80000L
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK  0x18000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable      0x20000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK     0x40000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q          0x40000000L
+#define VGT_DEBUG_REG16__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG16__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q_MASK                  0x00000001L
+#define VGT_DEBUG_REG17__save_read_q                       0x00000001L
+#define VGT_DEBUG_REG17__extend_read_q_MASK                0x00000002L
+#define VGT_DEBUG_REG17__extend_read_q                     0x00000002L
+#define VGT_DEBUG_REG17__grp_indx_size_MASK                0x0000000cL
+#define VGT_DEBUG_REG17__cull_prim_true_MASK               0x00000010L
+#define VGT_DEBUG_REG17__cull_prim_true                    0x00000010L
+#define VGT_DEBUG_REG17__reset_bit2_q_MASK                 0x00000020L
+#define VGT_DEBUG_REG17__reset_bit2_q                      0x00000020L
+#define VGT_DEBUG_REG17__reset_bit1_q_MASK                 0x00000040L
+#define VGT_DEBUG_REG17__reset_bit1_q                      0x00000040L
+#define VGT_DEBUG_REG17__first_reg_first_q_MASK            0x00000080L
+#define VGT_DEBUG_REG17__first_reg_first_q                 0x00000080L
+#define VGT_DEBUG_REG17__check_second_reg_MASK             0x00000100L
+#define VGT_DEBUG_REG17__check_second_reg                  0x00000100L
+#define VGT_DEBUG_REG17__check_first_reg_MASK              0x00000200L
+#define VGT_DEBUG_REG17__check_first_reg                   0x00000200L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK   0x00000400L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata        0x00000400L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK      0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q           0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK      0x00001000L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q           0x00001000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK       0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q            0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK       0x00004000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q            0x00004000L
+#define VGT_DEBUG_REG17__to_second_reg_q_MASK              0x00008000L
+#define VGT_DEBUG_REG17__to_second_reg_q                   0x00008000L
+#define VGT_DEBUG_REG17__roll_over_msk_q_MASK              0x00010000L
+#define VGT_DEBUG_REG17__roll_over_msk_q                   0x00010000L
+#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK                0x00fe0000L
+#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK                0x7f000000L
+#define VGT_DEBUG_REG17__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG17__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK      0x0000003fL
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK      0x00000fc0L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK   0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re        0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK  0x00006000L
+#define VGT_DEBUG_REG18__dma_mem_full_MASK                 0x00008000L
+#define VGT_DEBUG_REG18__dma_mem_full                      0x00008000L
+#define VGT_DEBUG_REG18__dma_ram_re_MASK                   0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_re                        0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_we_MASK                   0x00020000L
+#define VGT_DEBUG_REG18__dma_ram_we                        0x00020000L
+#define VGT_DEBUG_REG18__dma_mem_empty_MASK                0x00040000L
+#define VGT_DEBUG_REG18__dma_mem_empty                     0x00040000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK         0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re              0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK         0x00100000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we              0x00100000L
+#define VGT_DEBUG_REG18__bin_mem_full_MASK                 0x00200000L
+#define VGT_DEBUG_REG18__bin_mem_full                      0x00200000L
+#define VGT_DEBUG_REG18__bin_ram_we_MASK                   0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_we                        0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_re_MASK                   0x00800000L
+#define VGT_DEBUG_REG18__bin_ram_re                        0x00800000L
+#define VGT_DEBUG_REG18__bin_mem_empty_MASK                0x01000000L
+#define VGT_DEBUG_REG18__bin_mem_empty                     0x01000000L
+#define VGT_DEBUG_REG18__start_bin_req_MASK                0x02000000L
+#define VGT_DEBUG_REG18__start_bin_req                     0x02000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK          0x04000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used               0x04000000L
+#define VGT_DEBUG_REG18__dma_req_xfer_MASK                 0x08000000L
+#define VGT_DEBUG_REG18__dma_req_xfer                      0x08000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req_MASK           0x10000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req                0x10000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req_MASK           0x20000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req                0x20000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK  0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable       0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK         0x00000001L
+#define VGT_DEBUG_REG20__prim_side_indx_valid              0x00000001L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK         0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty              0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK            0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_re                 0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK            0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_we                 0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK          0x00000010L
+#define VGT_DEBUG_REG20__indx_side_fifo_full               0x00000010L
+#define VGT_DEBUG_REG20__prim_buffer_empty_MASK            0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_empty                 0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_re_MASK               0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_re                    0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_we_MASK               0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_we                    0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_full_MASK             0x00000100L
+#define VGT_DEBUG_REG20__prim_buffer_full                  0x00000100L
+#define VGT_DEBUG_REG20__indx_buffer_empty_MASK            0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_empty                 0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_re_MASK               0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_re                    0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_we_MASK               0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_we                    0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_full_MASK             0x00001000L
+#define VGT_DEBUG_REG20__indx_buffer_full                  0x00001000L
+#define VGT_DEBUG_REG20__hold_prim_MASK                    0x00002000L
+#define VGT_DEBUG_REG20__hold_prim                         0x00002000L
+#define VGT_DEBUG_REG20__sent_cnt_MASK                     0x0003c000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK          0x00040000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector               0x00040000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK         0x00080000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim              0x00080000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK         0x00100000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim              0x00100000L
+#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK     0x03e00000L
+#define VGT_DEBUG_REG20__out_trigger_MASK                  0x04000000L
+#define VGT_DEBUG_REG20__out_trigger                       0x04000000L
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK    0x00000001L
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector         0x00000001L
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK   0x0000000eL
+#define VGT_DEBUG_REG21__alloc_counter_q_MASK              0x00000070L
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK      0x00000380L
+#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK            0x00003c00L
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK      0x0003c000L
+#define VGT_DEBUG_REG21__new_packet_q_MASK                 0x00040000L
+#define VGT_DEBUG_REG21__new_packet_q                      0x00040000L
+#define VGT_DEBUG_REG21__new_allocate_q_MASK               0x00080000L
+#define VGT_DEBUG_REG21__new_allocate_q                    0x00080000L
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK      0x00300000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK         0x00400000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q              0x00400000L
+#define VGT_DEBUG_REG21__insert_null_prim_MASK             0x00800000L
+#define VGT_DEBUG_REG21__insert_null_prim                  0x00800000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK        0x01000000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux             0x01000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK        0x02000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux             0x02000000L
+#define VGT_DEBUG_REG21__buffered_thread_size_MASK         0x04000000L
+#define VGT_DEBUG_REG21__buffered_thread_size              0x04000000L
+#define VGT_DEBUG_REG21__out_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG21__out_trigger                       0x80000000L
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC_MASK                          0xffffffffL
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC_MASK                          0xffffffffL
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE_MASK                 0x00000001L
+#define TC_CNTL_STATUS__L2_INVALIDATE                      0x00000001L
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK                0x000c0000L
+#define TC_CNTL_STATUS__TC_BUSY_MASK                       0x80000000L
+#define TC_CNTL_STATUS__TC_BUSY                            0x80000000L
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK                 0x00000100L
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN                      0x00000100L
+#define TCM_CHICKEN__SPARE_MASK                            0xfffffe00L
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK            0x00000007L
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK            0x00000038L
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK               0x00000001L
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY                    0x00000001L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK             0x00000002L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY                  0x00000002L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK          0x00000004L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY               0x00000004L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK          0x00000008L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY               0x00000008L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK         0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY              0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK           0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY                0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK              0x00000040L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY                   0x00000040L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK        0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY             0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK          0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY               0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK             0x00000400L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY                  0x00000400L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK             0x00001000L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY                  0x00001000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK          0x00002000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY               0x00002000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK            0x00004000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY                 0x00004000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK               0x00008000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY                    0x00008000L
+#define TPC_CNTL_STATUS__TF_TW_RTS_MASK                    0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_RTS                         0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK              0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS                   0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_RTR_MASK                    0x00080000L
+#define TPC_CNTL_STATUS__TF_TW_RTR                         0x00080000L
+#define TPC_CNTL_STATUS__TW_TA_RTS_MASK                    0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_RTS                         0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK                 0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS                      0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK               0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS                    0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_RTR_MASK                    0x00800000L
+#define TPC_CNTL_STATUS__TW_TA_RTR                         0x00800000L
+#define TPC_CNTL_STATUS__TA_TB_RTS_MASK                    0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_RTS                         0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK                 0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS                      0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR_MASK                    0x08000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR                         0x08000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS_MASK                    0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS                         0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK            0x20000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN                 0x20000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK                    0x40000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC                         0x40000000L
+#define TPC_CNTL_STATUS__TPC_BUSY_MASK                     0x80000000L
+#define TPC_CNTL_STATUS__TPC_BUSY                          0x80000000L
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL_MASK                          0x00000003L
+#define TPC_DEBUG0__IC_CTR_MASK                            0x0000000cL
+#define TPC_DEBUG0__WALKER_CNTL_MASK                       0x000000f0L
+#define TPC_DEBUG0__ALIGNER_CNTL_MASK                      0x00000700L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK               0x00001000L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID                    0x00001000L
+#define TPC_DEBUG0__WALKER_STATE_MASK                      0x03ff0000L
+#define TPC_DEBUG0__ALIGNER_STATE_MASK                     0x0c000000L
+#define TPC_DEBUG0__REG_CLK_EN_MASK                        0x20000000L
+#define TPC_DEBUG0__REG_CLK_EN                             0x20000000L
+#define TPC_DEBUG0__TPC_CLK_EN_MASK                        0x40000000L
+#define TPC_DEBUG0__TPC_CLK_EN                             0x40000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK                      0x80000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP                           0x80000000L
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED_MASK                            0x00000001L
+#define TPC_DEBUG1__UNUSED                                 0x00000001L
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION_MASK                  0x00000001L
+#define TPC_CHICKEN__BLEND_PRECISION                       0x00000001L
+#define TPC_CHICKEN__SPARE_MASK                            0xfffffffeL
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK                0x00000001L
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY                     0x00000001L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK                  0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY                       0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK             0x00000004L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY                  0x00000004L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK                 0x00000008L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY                      0x00000008L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK           0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY                0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK              0x00000020L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY                   0x00000020L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK              0x00000040L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY                   0x00000040L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK              0x00000080L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY                   0x00000080L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK                0x00000100L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY                     0x00000100L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK             0x00000200L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY                  0x00000200L
+#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK                   0x00000400L
+#define TP0_CNTL_STATUS__TP_TT_BUSY                        0x00000400L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK              0x00000800L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY                   0x00000800L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK                0x00001000L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY                     0x00001000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK             0x00002000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY                  0x00002000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK               0x00004000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY                    0x00004000L
+#define TP0_CNTL_STATUS__IN_LC_RTS_MASK                    0x00010000L
+#define TP0_CNTL_STATUS__IN_LC_RTS                         0x00010000L
+#define TP0_CNTL_STATUS__LC_LA_RTS_MASK                    0x00020000L
+#define TP0_CNTL_STATUS__LC_LA_RTS                         0x00020000L
+#define TP0_CNTL_STATUS__LA_FL_RTS_MASK                    0x00040000L
+#define TP0_CNTL_STATUS__LA_FL_RTS                         0x00040000L
+#define TP0_CNTL_STATUS__FL_TA_RTS_MASK                    0x00080000L
+#define TP0_CNTL_STATUS__FL_TA_RTS                         0x00080000L
+#define TP0_CNTL_STATUS__TA_FA_RTS_MASK                    0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_RTS                         0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK                 0x00200000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS                      0x00200000L
+#define TP0_CNTL_STATUS__FA_AL_RTS_MASK                    0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_RTS                         0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK                 0x00800000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS                      0x00800000L
+#define TP0_CNTL_STATUS__AL_TF_RTS_MASK                    0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_RTS                         0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK                 0x02000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS                      0x02000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS_MASK                    0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS                         0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK                 0x08000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS                      0x08000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS_MASK                    0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS                         0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK               0x20000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET                    0x20000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS_MASK                    0x40000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS                         0x40000000L
+#define TP0_CNTL_STATUS__TP_BUSY_MASK                      0x80000000L
+#define TP0_CNTL_STATUS__TP_BUSY                           0x80000000L
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL_MASK                         0x00000003L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK                     0x00000008L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP                          0x00000008L
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK               0x001ffff0L
+#define TP0_DEBUG__REG_CLK_EN_MASK                         0x00200000L
+#define TP0_DEBUG__REG_CLK_EN                              0x00200000L
+#define TP0_DEBUG__PERF_CLK_EN_MASK                        0x00400000L
+#define TP0_DEBUG__PERF_CLK_EN                             0x00400000L
+#define TP0_DEBUG__TP_CLK_EN_MASK                          0x00800000L
+#define TP0_DEBUG__TP_CLK_EN                               0x00800000L
+#define TP0_DEBUG__Q_WALKER_CNTL_MASK                      0x0f000000L
+#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK                     0x70000000L
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE_MASK                          0x00000001L
+#define TP0_CHICKEN__TT_MODE                               0x00000001L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK              0x00000002L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE                   0x00000002L
+#define TP0_CHICKEN__SPARE_MASK                            0xfffffffcL
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr_MASK                      0x00000040L
+#define TCF_DEBUG__not_MH_TC_rtr                           0x00000040L
+#define TCF_DEBUG__TC_MH_send_MASK                         0x00000080L
+#define TCF_DEBUG__TC_MH_send                              0x00000080L
+#define TCF_DEBUG__not_FG0_rtr_MASK                        0x00000100L
+#define TCF_DEBUG__not_FG0_rtr                             0x00000100L
+#define TCF_DEBUG__not_TCB_TCO_rtr_MASK                    0x00001000L
+#define TCF_DEBUG__not_TCB_TCO_rtr                         0x00001000L
+#define TCF_DEBUG__TCB_ff_stall_MASK                       0x00002000L
+#define TCF_DEBUG__TCB_ff_stall                            0x00002000L
+#define TCF_DEBUG__TCB_miss_stall_MASK                     0x00004000L
+#define TCF_DEBUG__TCB_miss_stall                          0x00004000L
+#define TCF_DEBUG__TCA_TCB_stall_MASK                      0x00008000L
+#define TCF_DEBUG__TCA_TCB_stall                           0x00008000L
+#define TCF_DEBUG__PF0_stall_MASK                          0x00010000L
+#define TCF_DEBUG__PF0_stall                               0x00010000L
+#define TCF_DEBUG__TP0_full_MASK                           0x00100000L
+#define TCF_DEBUG__TP0_full                                0x00100000L
+#define TCF_DEBUG__TPC_full_MASK                           0x01000000L
+#define TCF_DEBUG__TPC_full                                0x01000000L
+#define TCF_DEBUG__not_TPC_rtr_MASK                        0x02000000L
+#define TCF_DEBUG__not_TPC_rtr                             0x02000000L
+#define TCF_DEBUG__tca_state_rts_MASK                      0x04000000L
+#define TCF_DEBUG__tca_state_rts                           0x04000000L
+#define TCF_DEBUG__tca_rts_MASK                            0x08000000L
+#define TCF_DEBUG__tca_rts                                 0x08000000L
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full_MASK                      0x00000001L
+#define TCA_FIFO_DEBUG__tp0_full                           0x00000001L
+#define TCA_FIFO_DEBUG__tpc_full_MASK                      0x00000010L
+#define TCA_FIFO_DEBUG__tpc_full                           0x00000010L
+#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK                 0x00000020L
+#define TCA_FIFO_DEBUG__load_tpc_fifo                      0x00000020L
+#define TCA_FIFO_DEBUG__load_tp_fifos_MASK                 0x00000040L
+#define TCA_FIFO_DEBUG__load_tp_fifos                      0x00000040L
+#define TCA_FIFO_DEBUG__FW_full_MASK                       0x00000080L
+#define TCA_FIFO_DEBUG__FW_full                            0x00000080L
+#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK                   0x00000100L
+#define TCA_FIFO_DEBUG__not_FW_rtr0                        0x00000100L
+#define TCA_FIFO_DEBUG__FW_rts0_MASK                       0x00001000L
+#define TCA_FIFO_DEBUG__FW_rts0                            0x00001000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK                0x00010000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr                     0x00010000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK                    0x00020000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts                         0x00020000L
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK            0x00000001L
+#define TCA_PROBE_DEBUG__ProbeFilter_stall                 0x00000001L
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts_MASK               0x00001000L
+#define TCA_TPC_DEBUG__captue_state_rts                    0x00001000L
+#define TCA_TPC_DEBUG__capture_tca_rts_MASK                0x00002000L
+#define TCA_TPC_DEBUG__capture_tca_rts                     0x00002000L
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512_MASK                     0x00000001L
+#define TCB_CORE_DEBUG__access512                          0x00000001L
+#define TCB_CORE_DEBUG__tiled_MASK                         0x00000002L
+#define TCB_CORE_DEBUG__tiled                              0x00000002L
+#define TCB_CORE_DEBUG__opcode_MASK                        0x00000070L
+#define TCB_CORE_DEBUG__format_MASK                        0x00003f00L
+#define TCB_CORE_DEBUG__sector_format_MASK                 0x001f0000L
+#define TCB_CORE_DEBUG__sector_format512_MASK              0x07000000L
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG0_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG0_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG0_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG0_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG0_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG1_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG1_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG1_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG1_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG1_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG2_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG2_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG2_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG2_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG2_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG3_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG3_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG3_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG3_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG3_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done      0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left    0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q   0x10000000L
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK     0x00000030L
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK      0x000000c0L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK     0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left          0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK     0x00007000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK              0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy                   0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK  0x000f0000L
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK        0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts             0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK         0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts              0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK      0x0000fff0L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK   0x001f0000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK               0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy                    0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK           0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy                0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK            0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy                 0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK           0x0c000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK            0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q                 0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK            0x40000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR                 0x40000000L
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty_MASK                       0x00010000L
+#define TCD_INPUT0_DEBUG__empty                            0x00010000L
+#define TCD_INPUT0_DEBUG__full_MASK                        0x00020000L
+#define TCD_INPUT0_DEBUG__full                             0x00020000L
+#define TCD_INPUT0_DEBUG__valid_q1_MASK                    0x00100000L
+#define TCD_INPUT0_DEBUG__valid_q1                         0x00100000L
+#define TCD_INPUT0_DEBUG__cnt_q1_MASK                      0x00600000L
+#define TCD_INPUT0_DEBUG__last_send_q1_MASK                0x00800000L
+#define TCD_INPUT0_DEBUG__last_send_q1                     0x00800000L
+#define TCD_INPUT0_DEBUG__ip_send_MASK                     0x01000000L
+#define TCD_INPUT0_DEBUG__ip_send                          0x01000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK              0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send                   0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK                  0x04000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy                       0x04000000L
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK        0x00000003L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK            0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8                 0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK        0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send             0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK             0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send                  0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK                 0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall                      0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK                0x00000040L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate                     0x00000040L
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK               0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate                    0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK           0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr                0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK             0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr                  0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send      0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK  0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts       0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK    0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send         0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send     0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK     0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send          0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK        0x20000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send             0x20000000L
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK                  0x00000010L
+#define TCD_DXTC_ARB_DEBUG__n0_stall                       0x00000010L
+#define TCD_DXTC_ARB_DEBUG__pstate_MASK                    0x00000020L
+#define TCD_DXTC_ARB_DEBUG__pstate                         0x00000020L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK      0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send           0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK            0x00000180L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK         0x00000e00L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK      0x0003f000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK         0x3ffc0000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK           0x40000000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send                0x40000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK           0x80000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types                0x80000000L
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK     0x00000400L
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr          0x00000400L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK     0x00000800L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr          0x00000800L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK           0x00020000L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr                0x00020000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK         0x00040000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr              0x00040000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK            0x00080000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr                 0x00080000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK            0x80000000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr                 0x80000000L
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK            0x00000020L
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR                 0x00000020L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK             0x00000040L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR                  0x00000040L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK         0x00000080L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d              0x00000080L
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK         0x000000ffL
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK         0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample              0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK                   0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr                        0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK                   0x00000400L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts                        0x00000400L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK        0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample             0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK                  0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr                       0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK                  0x00002000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts                       0x00002000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK             0x00010000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q                  0x00010000L
+#define TCO_QUAD0_DEBUG0__read_cache_q_MASK                0x01000000L
+#define TCO_QUAD0_DEBUG0__read_cache_q                     0x01000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK              0x02000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR                   0x02000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK    0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3         0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK    0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2         0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK    0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1         0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK    0x20000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0         0x20000000L
+#define TCO_QUAD0_DEBUG0__busy_MASK                        0x40000000L
+#define TCO_QUAD0_DEBUG0__busy                             0x40000000L
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy_MASK                   0x00000001L
+#define TCO_QUAD0_DEBUG1__fifo_busy                        0x00000001L
+#define TCO_QUAD0_DEBUG1__empty_MASK                       0x00000002L
+#define TCO_QUAD0_DEBUG1__empty                            0x00000002L
+#define TCO_QUAD0_DEBUG1__full_MASK                        0x00000004L
+#define TCO_QUAD0_DEBUG1__full                             0x00000004L
+#define TCO_QUAD0_DEBUG1__write_enable_MASK                0x00000008L
+#define TCO_QUAD0_DEBUG1__write_enable                     0x00000008L
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK              0x000007f0L
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK               0x0003f800L
+#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK             0x00100000L
+#define TCO_QUAD0_DEBUG1__cache_read_busy                  0x00100000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK           0x00200000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy                0x00200000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK             0x00400000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy                  0x00400000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK          0x00800000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy               0x00800000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK               0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d                    0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK               0x02000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q                    0x02000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK                   0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr                        0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK                   0x08000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts                        0x08000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK                  0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr                       0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK                  0x20000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts                       0x20000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK            0x40000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc                 0x40000000L
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK                0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC                     0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK               0x000007f0L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK               0x0007f000L
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK     0x00000003L
+#define SQ_FLOW_CONTROL__ONE_THREAD_MASK                   0x00000010L
+#define SQ_FLOW_CONTROL__ONE_THREAD                        0x00000010L
+#define SQ_FLOW_CONTROL__ONE_ALU_MASK                      0x00000100L
+#define SQ_FLOW_CONTROL__ONE_ALU                           0x00000100L
+#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK                   0x0000f000L
+#define SQ_FLOW_CONTROL__NO_PV_PS_MASK                     0x00010000L
+#define SQ_FLOW_CONTROL__NO_PV_PS                          0x00010000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK                 0x00020000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT                      0x00020000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK            0x00040000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE                 0x00040000L
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK   0x00180000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK        0x00200000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY             0x00200000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK       0x00400000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY            0x00400000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK                 0x00800000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT                      0x00800000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK                 0x01000000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT                      0x01000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK             0x02000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY                  0x02000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK  0x04000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION       0x04000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK      0x08000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC           0x08000000L
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK        0x00000fffL
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK        0x0fff0000L
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK     0x01ff0000L
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT_MASK                     0x000000ffL
+#define SQ_EO_RT__EO_TSTATE_RT_MASK                        0x00ff0000L
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK                 0x000007ffL
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK                 0x000ff000L
+#define SQ_DEBUG_MISC__DB_READ_CTX_MASK                    0x00100000L
+#define SQ_DEBUG_MISC__DB_READ_CTX                         0x00100000L
+#define SQ_DEBUG_MISC__RESERVED_MASK                       0x00600000L
+#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK                 0x01800000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK                0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0                     0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK                0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1                     0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK                0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2                     0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK                0x10000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3                     0x10000000L
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK              0x000000ffL
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK         0x0000ff00L
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK        0x00ff0000L
+#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK                 0xff000000L
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK        0x000000ffL
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK        0x00000007L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK          0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN               0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK        0x00000070L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK          0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN               0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK              0x0003ff00L
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK       0x00000007L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK         0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN              0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK       0x00000070L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK         0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN              0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK             0x0003ff00L
+#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK              0x000c0000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK  0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL       0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK  0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL       0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK                 0x00000007L
+#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK                  0x00000008L
+#define SQ_DEBUG_INPUT_FSM__RESERVED                       0x00000008L
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK                 0x000000f0L
+#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK                   0x00000700L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1                      0x00000800L
+#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK                     0x00007000L
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK             0x000f8000L
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK               0x0ff00000L
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK             0x000000e0L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK             0x0000e000L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK  0x00030000L
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK  0x000c0000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK  0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE       0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK  0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE       0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK  0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE       0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK  0x00800000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE       0x00800000L
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP_MASK                        0x00000007L
+#define SQ_DEBUG_TP_FSM__RESERVED0_MASK                    0x00000008L
+#define SQ_DEBUG_TP_FSM__RESERVED0                         0x00000008L
+#define SQ_DEBUG_TP_FSM__CF_TP_MASK                        0x000000f0L
+#define SQ_DEBUG_TP_FSM__IF_TP_MASK                        0x00000700L
+#define SQ_DEBUG_TP_FSM__RESERVED1_MASK                    0x00000800L
+#define SQ_DEBUG_TP_FSM__RESERVED1                         0x00000800L
+#define SQ_DEBUG_TP_FSM__TIS_TP_MASK                       0x00003000L
+#define SQ_DEBUG_TP_FSM__RESERVED2_MASK                    0x0000c000L
+#define SQ_DEBUG_TP_FSM__GS_TP_MASK                        0x00030000L
+#define SQ_DEBUG_TP_FSM__RESERVED3_MASK                    0x000c0000L
+#define SQ_DEBUG_TP_FSM__FCR_TP_MASK                       0x00300000L
+#define SQ_DEBUG_TP_FSM__RESERVED4_MASK                    0x00c00000L
+#define SQ_DEBUG_TP_FSM__FCS_TP_MASK                       0x03000000L
+#define SQ_DEBUG_TP_FSM__RESERVED5_MASK                    0x0c000000L
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK                    0x70000000L
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK             0x0000000fL
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK           0x00000ff0L
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK              0x00007000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK                  0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED                       0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK       0x003f0000L
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK              0x00000001L
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER                   0x00000001L
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK                0x0000001eL
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK            0x00000020L
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR                 0x00000020L
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK           0x000001c0L
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK                0x00003e00L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK                 0x00004000L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT                      0x00004000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK          0x00008000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON               0x00008000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK                   0x00010000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY                        0x00010000L
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK               0x0ffe0000L
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_VTX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_VTX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_VTX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_PIX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_PIX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_PIX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN     0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN     0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK     0x60000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC    0x80000000L
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK             0x0000000fL
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK                 0x000000f0L
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK                 0x00000f00L
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK          0x0000f000L
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK           0x000f0000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK              0x00100000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL                   0x00100000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK                     0x00200000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q                          0x00200000L
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK                0x0000ffffL
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK     0xffffffffL
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK       0xffffffffL
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK               0x0000003fL
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK                   0x00000fc0L
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK                   0x0007f000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK          0x01f80000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK            0x7e000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY_MASK                       0x80000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY                            0x80000000L
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK   0xffffffffL
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD_MASK           0x00000040L
+#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD                0x00000040L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK    0x00000080L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP         0x00000080L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD_MASK           0x00004000L
+#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD                0x00004000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK             0x00008000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA                  0x00008000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK          0x000f0000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK          0x00f00000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK            0x01000000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP                 0x01000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK            0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP                 0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK           0xfc000000L
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK         0x00000003L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK         0x0000000cL
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK         0x00000030L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK         0x000000c0L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK         0x00000300L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK         0x00000c00L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK         0x00003000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK         0x0000c000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK         0x00030000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK         0x000c0000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK         0x00300000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK         0x00c00000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK           0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD                0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK           0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD                0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK           0x04000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD                0x04000000L
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK             0x18000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK           0x20000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR                0x20000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK         0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS              0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK         0x80000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS              0x80000000L
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK            0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C                 0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK           0x00000080L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C                0x00000080L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK            0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B                 0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK           0x00008000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B                0x00008000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK           0x003f0000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK            0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A                 0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK           0x00800000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A                0x00800000L
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK           0x1f000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK               0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL                    0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK               0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL                    0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK               0x80000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK             0x000001ffL
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK            0x00000e00L
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK               0x00007000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK               0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD                    0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK         0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0              0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0            0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK         0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1              0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK       0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1            0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK         0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2              0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK       0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2            0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK         0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3              0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK       0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3            0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK         0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4              0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK       0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4            0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK         0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5              0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK       0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5            0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK           0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0                0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK           0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1                0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK           0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2                0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK           0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3                0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK           0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4                0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK           0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5                0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK           0x000003fcL
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK           0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION                0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK             0x01ff0000L
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK            0x0e000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK               0x70000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK               0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK         0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0              0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0            0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK         0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1              0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK       0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1            0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK         0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2              0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK       0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2            0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK         0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3              0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK       0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3            0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK         0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4              0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK       0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4            0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK         0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5              0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK       0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5            0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK           0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0                0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK           0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1                0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK           0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2                0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK           0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3                0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK           0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4                0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK           0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5                0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK           0x03fc0000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK           0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION                0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK             0x000003ffL
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK          0x0000fc00L
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK             0x001f0000L
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK          0xffe00000L
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK          0x000007ffL
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK             0x03ff0000L
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK          0xfc000000L
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK             0x0000001fL
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK            0x07ffffe0L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK         0x000003ffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK      0x00001c00L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK      0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL           0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK  0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP       0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK      0xffff8000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK      0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0           0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION            0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK       0x000003fcL
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK       0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION            0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK    0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE         0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK          0x0000f000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK         0x03ff0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK      0x1c000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK      0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL           0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK      0xc0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK        0x0001ffffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION            0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK       0x03fc0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK       0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION            0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK    0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE         0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK          0xf0000000L
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK               0x0000000fL
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK           0xfffffff0L
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK         0x000000ffL
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK          0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL               0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK      0x00000600L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK         0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE              0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK             0x0000f000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK               0x000f0000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK         0xfff00000L
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK           0x00ffffffL
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK          0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL               0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK      0x06000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK         0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE              0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK             0xf0000000L
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK     0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY          0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK      0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM           0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK            0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK            0x30000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK            0xc0000000L
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK           0x00003000L
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK           0x0000c000L
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK           0x00030000L
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK         0x001c0000L
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK     0x00e00000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK       0x03000000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK       0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK         0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD              0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK          0x60000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK    0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS         0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK      0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION           0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK             0x000001fcL
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK               0x0000fe00L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK             0x001f0000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK             0x03e00000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK             0x7c000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK          0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE               0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK      0x06000000L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK              0xc0000000L
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK      0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL           0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK       0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL            0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK   0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL        0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK          0x003f0000L
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK       0x3f800000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK               0x000000ffL
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK               0x00ff0000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED_MASK                            0xffffffffL
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN_MASK                          0xffffffffL
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE_MASK                           0xffffffffL
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA_MASK                          0xffffffffL
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE_MASK                             0xffffffffL
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE_MASK                    0x00000001L
+#define SQ_CONSTANT_VFETCH_0__TYPE                         0x00000001L
+#define SQ_CONSTANT_VFETCH_0__STATE_MASK                   0x00000002L
+#define SQ_CONSTANT_VFETCH_0__STATE                        0x00000002L
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK            0xfffffffcL
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK             0x00000003L
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK           0xfffffffcL
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE_MASK                         0xffffffffL
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE_MASK                         0xffffffffL
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK                 0x000000ffL
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK                 0x0000ff00L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK                 0x00ff0000L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK                 0xff000000L
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK                     0x000000ffL
+#define SQ_CF_LOOP__CF_LOOP_START_MASK                     0x0000ff00L
+#define SQ_CF_LOOP__CF_LOOP_STEP_MASK                      0x00ff0000L
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED_MASK                         0xffffffffL
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN_MASK                       0xffffffffL
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE_MASK                        0xffffffffL
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA_MASK                       0xffffffffL
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE_MASK                          0xffffffffL
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK              0x000000ffL
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK              0x0000ff00L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK              0x00ff0000L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK              0xff000000L
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK                  0x000000ffL
+#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK                  0x0000ff00L
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK                   0x00ff0000L
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_VS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_PS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK                0x000007ffL
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK                0x007ff000L
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK             0x0000ffffL
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK        0xffff0000L
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK                   0x0000003fL
+#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK                   0x00003f00L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK                  0x00010000L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE                       0x00010000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK                  0x00020000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE                       0x00020000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK                    0x00040000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN                         0x00040000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK                0x00080000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX                     0x00080000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK              0x00f00000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK               0x07000000L
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK               0x78000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK                0x80000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX                     0x80000000L
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK                   0x0000000fL
+#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK                   0x000000f0L
+#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK                   0x00000f00L
+#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK                   0x0000f000L
+#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK                   0x000f0000L
+#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK                   0x00f00000L
+#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK                   0x0f000000L
+#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK                   0xf0000000L
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK                   0x0000000fL
+#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK                   0x000000f0L
+#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK                  0x00000f00L
+#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK                  0x0000f000L
+#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK                  0x000f0000L
+#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK                  0x00f00000L
+#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK                  0x0f000000L
+#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK                  0xf0000000L
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_VS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_PS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK           0x00000001L
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE                0x00000001L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK          0x00000002L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY               0x00000002L
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK               0x0000000cL
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK                0x0000ff00L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK              0x00010000L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF                   0x00010000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK               0x00020000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE                    0x00020000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK                 0x00040000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL                      0x00040000L
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE_MASK                        0x00000007L
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK                   0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_ON                        0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK                0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK                     0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK                 0x0007ff00L
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK                0xff000000L
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK                    0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_PIX                         0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK                    0x00000002L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX                         0x00000002L
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK                0x0000ff00L
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK                0x07ff0000L
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK            0x0000003fL
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK      0x00000040L
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY           0x00000040L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK              0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE                   0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK         0x00000100L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE              0x00000100L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK             0x00000200L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL                  0x00000200L
+#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK                  0x00001c00L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK          0x00002000L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE               0x00002000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK         0x00004000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE              0x00004000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK     0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE          0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK            0x003f0000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK             0x00400000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE                  0x00400000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK            0x00800000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE                 0x00800000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK             0x01000000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE                  0x01000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK             0x02000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE                  0x02000000L
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK                  0x00000007L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK               0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1                    0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK                  0x00000070L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK               0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2                    0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK                 0x00000700L
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK             0x00000001L
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR                  0x00000001L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK            0x00000002L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR                 0x00000002L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK             0x00000004L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT                  0x00000004L
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK           0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR                0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK          0x00000002L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR               0x00000002L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK           0x00000004L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT                0x00000004L
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK            0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR                 0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK           0x00000002L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR                0x00000002L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK            0x00000004L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT                 0x00000004L
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID_MASK                     0x00000007L
+#define MH_AXI_ERROR__AXI_READ_ERROR_MASK                  0x00000008L
+#define MH_AXI_ERROR__AXI_READ_ERROR                       0x00000008L
+#define MH_AXI_ERROR__AXI_WRITE_ID_MASK                    0x00000070L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK                 0x00000080L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR                      0x00000080L
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX_MASK                          0x0000003fL
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA_MASK                           0xffffffffL
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY_MASK                       0x00000001L
+#define MH_DEBUG_REG00__MH_BUSY                            0x00000001L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK             0x00000002L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING                  0x00000002L
+#define MH_DEBUG_REG00__CP_REQUEST_MASK                    0x00000004L
+#define MH_DEBUG_REG00__CP_REQUEST                         0x00000004L
+#define MH_DEBUG_REG00__VGT_REQUEST_MASK                   0x00000008L
+#define MH_DEBUG_REG00__VGT_REQUEST                        0x00000008L
+#define MH_DEBUG_REG00__TC_REQUEST_MASK                    0x00000010L
+#define MH_DEBUG_REG00__TC_REQUEST                         0x00000010L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK                  0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY                       0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_FULL_MASK                   0x00000040L
+#define MH_DEBUG_REG00__TC_CAM_FULL                        0x00000040L
+#define MH_DEBUG_REG00__TCD_EMPTY_MASK                     0x00000080L
+#define MH_DEBUG_REG00__TCD_EMPTY                          0x00000080L
+#define MH_DEBUG_REG00__TCD_FULL_MASK                      0x00000100L
+#define MH_DEBUG_REG00__TCD_FULL                           0x00000100L
+#define MH_DEBUG_REG00__RB_REQUEST_MASK                    0x00000200L
+#define MH_DEBUG_REG00__RB_REQUEST                         0x00000200L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK               0x00000400L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE                    0x00000400L
+#define MH_DEBUG_REG00__ARQ_EMPTY_MASK                     0x00000800L
+#define MH_DEBUG_REG00__ARQ_EMPTY                          0x00000800L
+#define MH_DEBUG_REG00__ARQ_FULL_MASK                      0x00001000L
+#define MH_DEBUG_REG00__ARQ_FULL                           0x00001000L
+#define MH_DEBUG_REG00__WDB_EMPTY_MASK                     0x00002000L
+#define MH_DEBUG_REG00__WDB_EMPTY                          0x00002000L
+#define MH_DEBUG_REG00__WDB_FULL_MASK                      0x00004000L
+#define MH_DEBUG_REG00__WDB_FULL                           0x00004000L
+#define MH_DEBUG_REG00__AXI_AVALID_MASK                    0x00008000L
+#define MH_DEBUG_REG00__AXI_AVALID                         0x00008000L
+#define MH_DEBUG_REG00__AXI_AREADY_MASK                    0x00010000L
+#define MH_DEBUG_REG00__AXI_AREADY                         0x00010000L
+#define MH_DEBUG_REG00__AXI_ARVALID_MASK                   0x00020000L
+#define MH_DEBUG_REG00__AXI_ARVALID                        0x00020000L
+#define MH_DEBUG_REG00__AXI_ARREADY_MASK                   0x00040000L
+#define MH_DEBUG_REG00__AXI_ARREADY                        0x00040000L
+#define MH_DEBUG_REG00__AXI_WVALID_MASK                    0x00080000L
+#define MH_DEBUG_REG00__AXI_WVALID                         0x00080000L
+#define MH_DEBUG_REG00__AXI_WREADY_MASK                    0x00100000L
+#define MH_DEBUG_REG00__AXI_WREADY                         0x00100000L
+#define MH_DEBUG_REG00__AXI_RVALID_MASK                    0x00200000L
+#define MH_DEBUG_REG00__AXI_RVALID                         0x00200000L
+#define MH_DEBUG_REG00__AXI_RREADY_MASK                    0x00400000L
+#define MH_DEBUG_REG00__AXI_RREADY                         0x00400000L
+#define MH_DEBUG_REG00__AXI_BVALID_MASK                    0x00800000L
+#define MH_DEBUG_REG00__AXI_BVALID                         0x00800000L
+#define MH_DEBUG_REG00__AXI_BREADY_MASK                    0x01000000L
+#define MH_DEBUG_REG00__AXI_BREADY                         0x01000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK                  0x02000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ                       0x02000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK                  0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK                       0x04000000L
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q_MASK                     0x00000001L
+#define MH_DEBUG_REG01__CP_SEND_q                          0x00000001L
+#define MH_DEBUG_REG01__CP_RTR_q_MASK                      0x00000002L
+#define MH_DEBUG_REG01__CP_RTR_q                           0x00000002L
+#define MH_DEBUG_REG01__CP_WRITE_q_MASK                    0x00000004L
+#define MH_DEBUG_REG01__CP_WRITE_q                         0x00000004L
+#define MH_DEBUG_REG01__CP_TAG_q_MASK                      0x00000038L
+#define MH_DEBUG_REG01__CP_BE_q_MASK                       0x00003fc0L
+#define MH_DEBUG_REG01__VGT_SEND_q_MASK                    0x00004000L
+#define MH_DEBUG_REG01__VGT_SEND_q                         0x00004000L
+#define MH_DEBUG_REG01__VGT_RTR_q_MASK                     0x00008000L
+#define MH_DEBUG_REG01__VGT_RTR_q                          0x00008000L
+#define MH_DEBUG_REG01__VGT_TAG_q_MASK                     0x00010000L
+#define MH_DEBUG_REG01__VGT_TAG_q                          0x00010000L
+#define MH_DEBUG_REG01__TC_SEND_q_MASK                     0x00020000L
+#define MH_DEBUG_REG01__TC_SEND_q                          0x00020000L
+#define MH_DEBUG_REG01__TC_RTR_q_MASK                      0x00040000L
+#define MH_DEBUG_REG01__TC_RTR_q                           0x00040000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK                 0x00080000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q                      0x00080000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK                  0x00100000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q                       0x00100000L
+#define MH_DEBUG_REG01__TC_MH_written_MASK                 0x00200000L
+#define MH_DEBUG_REG01__TC_MH_written                      0x00200000L
+#define MH_DEBUG_REG01__RB_SEND_q_MASK                     0x00400000L
+#define MH_DEBUG_REG01__RB_SEND_q                          0x00400000L
+#define MH_DEBUG_REG01__RB_RTR_q_MASK                      0x00800000L
+#define MH_DEBUG_REG01__RB_RTR_q                           0x00800000L
+#define MH_DEBUG_REG01__RB_BE_q_MASK                       0xff000000L
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG02__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG02__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG02__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG02__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK                 0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_rlast                      0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_tag_MASK                   0x00000070L
+#define MH_DEBUG_REG02__RDC_RID_MASK                       0x00000380L
+#define MH_DEBUG_REG02__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG02__MH_CP_writeclean_MASK              0x00001000L
+#define MH_DEBUG_REG02__MH_CP_writeclean                   0x00001000L
+#define MH_DEBUG_REG02__MH_RB_writeclean_MASK              0x00002000L
+#define MH_DEBUG_REG02__MH_RB_writeclean                   0x00002000L
+#define MH_DEBUG_REG02__BRC_BID_MASK                       0x0001c000L
+#define MH_DEBUG_REG02__BRC_BRESP_MASK                     0x00060000L
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK             0xffffffffL
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK            0xffffffffL
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG05__CP_MH_send                         0x00000001L
+#define MH_DEBUG_REG05__CP_MH_write_MASK                   0x00000002L
+#define MH_DEBUG_REG05__CP_MH_write                        0x00000002L
+#define MH_DEBUG_REG05__CP_MH_tag_MASK                     0x0000001cL
+#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK                 0xffffffe0L
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__ALWAYS_ZERO_MASK                   0x00000007L
+#define MH_DEBUG_REG08__VGT_MH_send_MASK                   0x00000008L
+#define MH_DEBUG_REG08__VGT_MH_send                        0x00000008L
+#define MH_DEBUG_REG08__VGT_MH_tagbe_MASK                  0x00000010L
+#define MH_DEBUG_REG08__VGT_MH_tagbe                       0x00000010L
+#define MH_DEBUG_REG08__VGT_MH_ad_31_5_MASK                0xffffffe0L
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG09__TC_MH_send_MASK                    0x00000004L
+#define MH_DEBUG_REG09__TC_MH_send                         0x00000004L
+#define MH_DEBUG_REG09__TC_MH_mask_MASK                    0x00000018L
+#define MH_DEBUG_REG09__TC_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__TC_MH_info_MASK                    0x01ffffffL
+#define MH_DEBUG_REG10__TC_MH_send_MASK                    0x02000000L
+#define MH_DEBUG_REG10__TC_MH_send                         0x02000000L
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__MH_TC_mcinfo_MASK                  0x01ffffffL
+#define MH_DEBUG_REG11__MH_TC_mcinfo_send_MASK             0x02000000L
+#define MH_DEBUG_REG11__MH_TC_mcinfo_send                  0x02000000L
+#define MH_DEBUG_REG11__TC_MH_written_MASK                 0x04000000L
+#define MH_DEBUG_REG11__TC_MH_written                      0x04000000L
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG12__TC_ROQ_SEND_MASK                   0x00000004L
+#define MH_DEBUG_REG12__TC_ROQ_SEND                        0x00000004L
+#define MH_DEBUG_REG12__TC_ROQ_MASK_MASK                   0x00000018L
+#define MH_DEBUG_REG12__TC_ROQ_ADDR_31_5_MASK              0xffffffe0L
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__TC_ROQ_INFO_MASK                   0x01ffffffL
+#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK                   0x02000000L
+#define MH_DEBUG_REG13__TC_ROQ_SEND                        0x02000000L
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG14__RB_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG14__RB_MH_send                         0x00000010L
+#define MH_DEBUG_REG14__RB_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__RB_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG17__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG17__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG17__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG17__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG17__ALEN_q_2_0_MASK                    0x000000e0L
+#define MH_DEBUG_REG17__ARVALID_q_MASK                     0x00000100L
+#define MH_DEBUG_REG17__ARVALID_q                          0x00000100L
+#define MH_DEBUG_REG17__ARREADY_q_MASK                     0x00000200L
+#define MH_DEBUG_REG17__ARREADY_q                          0x00000200L
+#define MH_DEBUG_REG17__ARID_q_MASK                        0x00001c00L
+#define MH_DEBUG_REG17__ARLEN_q_1_0_MASK                   0x00006000L
+#define MH_DEBUG_REG17__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG17__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG17__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG17__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG17__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG17__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG17__RID_q_MASK                         0x001c0000L
+#define MH_DEBUG_REG17__WVALID_q_MASK                      0x00200000L
+#define MH_DEBUG_REG17__WVALID_q                           0x00200000L
+#define MH_DEBUG_REG17__WREADY_q_MASK                      0x00400000L
+#define MH_DEBUG_REG17__WREADY_q                           0x00400000L
+#define MH_DEBUG_REG17__WLAST_q_MASK                       0x00800000L
+#define MH_DEBUG_REG17__WLAST_q                            0x00800000L
+#define MH_DEBUG_REG17__WID_q_MASK                         0x07000000L
+#define MH_DEBUG_REG17__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG17__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG17__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG17__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG17__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG18__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG18__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG18__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG18__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG18__ALEN_q_1_0_MASK                    0x00000060L
+#define MH_DEBUG_REG18__ARVALID_q_MASK                     0x00000080L
+#define MH_DEBUG_REG18__ARVALID_q                          0x00000080L
+#define MH_DEBUG_REG18__ARREADY_q_MASK                     0x00000100L
+#define MH_DEBUG_REG18__ARREADY_q                          0x00000100L
+#define MH_DEBUG_REG18__ARID_q_MASK                        0x00000e00L
+#define MH_DEBUG_REG18__ARLEN_q_1_1_MASK                   0x00001000L
+#define MH_DEBUG_REG18__ARLEN_q_1_1                        0x00001000L
+#define MH_DEBUG_REG18__WVALID_q_MASK                      0x00002000L
+#define MH_DEBUG_REG18__WVALID_q                           0x00002000L
+#define MH_DEBUG_REG18__WREADY_q_MASK                      0x00004000L
+#define MH_DEBUG_REG18__WREADY_q                           0x00004000L
+#define MH_DEBUG_REG18__WLAST_q_MASK                       0x00008000L
+#define MH_DEBUG_REG18__WLAST_q                            0x00008000L
+#define MH_DEBUG_REG18__WID_q_MASK                         0x00070000L
+#define MH_DEBUG_REG18__WSTRB_q_MASK                       0x07f80000L
+#define MH_DEBUG_REG18__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG18__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG18__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG18__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG18__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__ARC_CTRL_RE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG19__ARC_CTRL_RE_q                      0x00000001L
+#define MH_DEBUG_REG19__CTRL_ARC_ID_MASK                   0x0000000eL
+#define MH_DEBUG_REG19__CTRL_ARC_PAD_MASK                  0xfffffff0L
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG20__REG_A_MASK                         0x0000fffcL
+#define MH_DEBUG_REG20__REG_RE_MASK                        0x00010000L
+#define MH_DEBUG_REG20__REG_RE                             0x00010000L
+#define MH_DEBUG_REG20__REG_WE_MASK                        0x00020000L
+#define MH_DEBUG_REG20__REG_WE                             0x00020000L
+#define MH_DEBUG_REG20__BLOCK_RS_MASK                      0x00040000L
+#define MH_DEBUG_REG20__BLOCK_RS                           0x00040000L
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__REG_WD_MASK                        0xffffffffL
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__CIB_MH_axi_halt_req_MASK           0x00000001L
+#define MH_DEBUG_REG22__CIB_MH_axi_halt_req                0x00000001L
+#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack_MASK           0x00000002L
+#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack                0x00000002L
+#define MH_DEBUG_REG22__MH_RBBM_busy_MASK                  0x00000004L
+#define MH_DEBUG_REG22__MH_RBBM_busy                       0x00000004L
+#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int_MASK          0x00000008L
+#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int               0x00000008L
+#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int_MASK         0x00000010L
+#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int              0x00000010L
+#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int_MASK       0x00000020L
+#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int            0x00000020L
+#define MH_DEBUG_REG22__GAT_CLK_ENA_MASK                   0x00000040L
+#define MH_DEBUG_REG22__GAT_CLK_ENA                        0x00000040L
+#define MH_DEBUG_REG22__AXI_RDY_ENA_MASK                   0x00000080L
+#define MH_DEBUG_REG22__AXI_RDY_ENA                        0x00000080L
+#define MH_DEBUG_REG22__RBBM_MH_clk_en_override_MASK       0x00000100L
+#define MH_DEBUG_REG22__RBBM_MH_clk_en_override            0x00000100L
+#define MH_DEBUG_REG22__CNT_q_MASK                         0x00007e00L
+#define MH_DEBUG_REG22__TCD_EMPTY_q_MASK                   0x00008000L
+#define MH_DEBUG_REG22__TCD_EMPTY_q                        0x00008000L
+#define MH_DEBUG_REG22__TC_ROQ_EMPTY_MASK                  0x00010000L
+#define MH_DEBUG_REG22__TC_ROQ_EMPTY                       0x00010000L
+#define MH_DEBUG_REG22__MH_BUSY_d_MASK                     0x00020000L
+#define MH_DEBUG_REG22__MH_BUSY_d                          0x00020000L
+#define MH_DEBUG_REG22__ANY_CLNT_BUSY_MASK                 0x00040000L
+#define MH_DEBUG_REG22__ANY_CLNT_BUSY                      0x00040000L
+#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00080000L
+#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL   0x00080000L
+#define MH_DEBUG_REG22__CP_SEND_q_MASK                     0x00100000L
+#define MH_DEBUG_REG22__CP_SEND_q                          0x00100000L
+#define MH_DEBUG_REG22__CP_RTR_q_MASK                      0x00200000L
+#define MH_DEBUG_REG22__CP_RTR_q                           0x00200000L
+#define MH_DEBUG_REG22__VGT_SEND_q_MASK                    0x00400000L
+#define MH_DEBUG_REG22__VGT_SEND_q                         0x00400000L
+#define MH_DEBUG_REG22__VGT_RTR_q_MASK                     0x00800000L
+#define MH_DEBUG_REG22__VGT_RTR_q                          0x00800000L
+#define MH_DEBUG_REG22__TC_ROQ_SEND_q_MASK                 0x01000000L
+#define MH_DEBUG_REG22__TC_ROQ_SEND_q                      0x01000000L
+#define MH_DEBUG_REG22__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG22__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG22__RB_SEND_q_MASK                     0x04000000L
+#define MH_DEBUG_REG22__RB_SEND_q                          0x04000000L
+#define MH_DEBUG_REG22__RB_RTR_q_MASK                      0x08000000L
+#define MH_DEBUG_REG22__RB_RTR_q                           0x08000000L
+#define MH_DEBUG_REG22__RDC_VALID_MASK                     0x10000000L
+#define MH_DEBUG_REG22__RDC_VALID                          0x10000000L
+#define MH_DEBUG_REG22__RDC_RLAST_MASK                     0x20000000L
+#define MH_DEBUG_REG22__RDC_RLAST                          0x20000000L
+#define MH_DEBUG_REG22__TLBMISS_VALID_MASK                 0x40000000L
+#define MH_DEBUG_REG22__TLBMISS_VALID                      0x40000000L
+#define MH_DEBUG_REG22__BRC_VALID_MASK                     0x80000000L
+#define MH_DEBUG_REG22__BRC_VALID                          0x80000000L
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__EFF2_FP_WINNER_MASK                0x00000007L
+#define MH_DEBUG_REG23__EFF2_LRU_WINNER_out_MASK           0x00000038L
+#define MH_DEBUG_REG23__EFF1_WINNER_MASK                   0x000001c0L
+#define MH_DEBUG_REG23__ARB_WINNER_MASK                    0x00000e00L
+#define MH_DEBUG_REG23__ARB_WINNER_q_MASK                  0x00007000L
+#define MH_DEBUG_REG23__EFF1_WIN_MASK                      0x00008000L
+#define MH_DEBUG_REG23__EFF1_WIN                           0x00008000L
+#define MH_DEBUG_REG23__KILL_EFF1_MASK                     0x00010000L
+#define MH_DEBUG_REG23__KILL_EFF1                          0x00010000L
+#define MH_DEBUG_REG23__ARB_HOLD_MASK                      0x00020000L
+#define MH_DEBUG_REG23__ARB_HOLD                           0x00020000L
+#define MH_DEBUG_REG23__ARB_RTR_q_MASK                     0x00040000L
+#define MH_DEBUG_REG23__ARB_RTR_q                          0x00040000L
+#define MH_DEBUG_REG23__CP_SEND_QUAL_MASK                  0x00080000L
+#define MH_DEBUG_REG23__CP_SEND_QUAL                       0x00080000L
+#define MH_DEBUG_REG23__VGT_SEND_QUAL_MASK                 0x00100000L
+#define MH_DEBUG_REG23__VGT_SEND_QUAL                      0x00100000L
+#define MH_DEBUG_REG23__TC_SEND_QUAL_MASK                  0x00200000L
+#define MH_DEBUG_REG23__TC_SEND_QUAL                       0x00200000L
+#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL_MASK             0x00400000L
+#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL                  0x00400000L
+#define MH_DEBUG_REG23__RB_SEND_QUAL_MASK                  0x00800000L
+#define MH_DEBUG_REG23__RB_SEND_QUAL                       0x00800000L
+#define MH_DEBUG_REG23__ARB_QUAL_MASK                      0x01000000L
+#define MH_DEBUG_REG23__ARB_QUAL                           0x01000000L
+#define MH_DEBUG_REG23__CP_EFF1_REQ_MASK                   0x02000000L
+#define MH_DEBUG_REG23__CP_EFF1_REQ                        0x02000000L
+#define MH_DEBUG_REG23__VGT_EFF1_REQ_MASK                  0x04000000L
+#define MH_DEBUG_REG23__VGT_EFF1_REQ                       0x04000000L
+#define MH_DEBUG_REG23__TC_EFF1_REQ_MASK                   0x08000000L
+#define MH_DEBUG_REG23__TC_EFF1_REQ                        0x08000000L
+#define MH_DEBUG_REG23__RB_EFF1_REQ_MASK                   0x10000000L
+#define MH_DEBUG_REG23__RB_EFF1_REQ                        0x10000000L
+#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK_MASK             0x20000000L
+#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK                  0x20000000L
+#define MH_DEBUG_REG23__TCD_NEARFULL_q_MASK                0x40000000L
+#define MH_DEBUG_REG23__TCD_NEARFULL_q                     0x40000000L
+#define MH_DEBUG_REG23__TCHOLD_IP_q_MASK                   0x80000000L
+#define MH_DEBUG_REG23__TCHOLD_IP_q                        0x80000000L
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__EFF1_WINNER_MASK                   0x00000007L
+#define MH_DEBUG_REG24__ARB_WINNER_MASK                    0x00000038L
+#define MH_DEBUG_REG24__CP_SEND_QUAL_MASK                  0x00000040L
+#define MH_DEBUG_REG24__CP_SEND_QUAL                       0x00000040L
+#define MH_DEBUG_REG24__VGT_SEND_QUAL_MASK                 0x00000080L
+#define MH_DEBUG_REG24__VGT_SEND_QUAL                      0x00000080L
+#define MH_DEBUG_REG24__TC_SEND_QUAL_MASK                  0x00000100L
+#define MH_DEBUG_REG24__TC_SEND_QUAL                       0x00000100L
+#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL_MASK             0x00000200L
+#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL                  0x00000200L
+#define MH_DEBUG_REG24__RB_SEND_QUAL_MASK                  0x00000400L
+#define MH_DEBUG_REG24__RB_SEND_QUAL                       0x00000400L
+#define MH_DEBUG_REG24__ARB_QUAL_MASK                      0x00000800L
+#define MH_DEBUG_REG24__ARB_QUAL                           0x00000800L
+#define MH_DEBUG_REG24__CP_EFF1_REQ_MASK                   0x00001000L
+#define MH_DEBUG_REG24__CP_EFF1_REQ                        0x00001000L
+#define MH_DEBUG_REG24__VGT_EFF1_REQ_MASK                  0x00002000L
+#define MH_DEBUG_REG24__VGT_EFF1_REQ                       0x00002000L
+#define MH_DEBUG_REG24__TC_EFF1_REQ_MASK                   0x00004000L
+#define MH_DEBUG_REG24__TC_EFF1_REQ                        0x00004000L
+#define MH_DEBUG_REG24__RB_EFF1_REQ_MASK                   0x00008000L
+#define MH_DEBUG_REG24__RB_EFF1_REQ                        0x00008000L
+#define MH_DEBUG_REG24__EFF1_WIN_MASK                      0x00010000L
+#define MH_DEBUG_REG24__EFF1_WIN                           0x00010000L
+#define MH_DEBUG_REG24__KILL_EFF1_MASK                     0x00020000L
+#define MH_DEBUG_REG24__KILL_EFF1                          0x00020000L
+#define MH_DEBUG_REG24__TCD_NEARFULL_q_MASK                0x00040000L
+#define MH_DEBUG_REG24__TCD_NEARFULL_q                     0x00040000L
+#define MH_DEBUG_REG24__TC_ARB_HOLD_MASK                   0x00080000L
+#define MH_DEBUG_REG24__TC_ARB_HOLD                        0x00080000L
+#define MH_DEBUG_REG24__ARB_HOLD_MASK                      0x00100000L
+#define MH_DEBUG_REG24__ARB_HOLD                           0x00100000L
+#define MH_DEBUG_REG24__ARB_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG24__ARB_RTR_q                          0x00200000L
+#define MH_DEBUG_REG24__SAME_PAGE_LIMIT_COUNT_q_MASK       0xffc00000L
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__EFF2_LRU_WINNER_out_MASK           0x00000007L
+#define MH_DEBUG_REG25__ARB_WINNER_MASK                    0x00000038L
+#define MH_DEBUG_REG25__LEAST_RECENT_INDEX_d_MASK          0x000001c0L
+#define MH_DEBUG_REG25__LEAST_RECENT_d_MASK                0x00000e00L
+#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d_MASK         0x00001000L
+#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d              0x00001000L
+#define MH_DEBUG_REG25__ARB_HOLD_MASK                      0x00002000L
+#define MH_DEBUG_REG25__ARB_HOLD                           0x00002000L
+#define MH_DEBUG_REG25__ARB_RTR_q_MASK                     0x00004000L
+#define MH_DEBUG_REG25__ARB_RTR_q                          0x00004000L
+#define MH_DEBUG_REG25__EFF1_WIN_MASK                      0x00008000L
+#define MH_DEBUG_REG25__EFF1_WIN                           0x00008000L
+#define MH_DEBUG_REG25__CLNT_REQ_MASK                      0x000f0000L
+#define MH_DEBUG_REG25__RECENT_d_0_MASK                    0x00700000L
+#define MH_DEBUG_REG25__RECENT_d_1_MASK                    0x03800000L
+#define MH_DEBUG_REG25__RECENT_d_2_MASK                    0x1c000000L
+#define MH_DEBUG_REG25__RECENT_d_3_MASK                    0xe0000000L
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__TC_ARB_HOLD_MASK                   0x00000001L
+#define MH_DEBUG_REG26__TC_ARB_HOLD                        0x00000001L
+#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK_MASK        0x00000002L
+#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK             0x00000002L
+#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK_MASK          0x00000004L
+#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK               0x00000004L
+#define MH_DEBUG_REG26__TCD_NEARFULL_q_MASK                0x00000008L
+#define MH_DEBUG_REG26__TCD_NEARFULL_q                     0x00000008L
+#define MH_DEBUG_REG26__TCHOLD_IP_q_MASK                   0x00000010L
+#define MH_DEBUG_REG26__TCHOLD_IP_q                        0x00000010L
+#define MH_DEBUG_REG26__TCHOLD_CNT_q_MASK                  0x000000e0L
+#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L
+#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK              0x00000200L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q                   0x00000200L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK                 0x00000400L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q                      0x00000400L
+#define MH_DEBUG_REG26__TC_MH_written_MASK                 0x00000800L
+#define MH_DEBUG_REG26__TC_MH_written                      0x00000800L
+#define MH_DEBUG_REG26__TCD_FULLNESS_CNT_q_MASK            0x0007f000L
+#define MH_DEBUG_REG26__WBURST_ACTIVE_MASK                 0x00080000L
+#define MH_DEBUG_REG26__WBURST_ACTIVE                      0x00080000L
+#define MH_DEBUG_REG26__WLAST_q_MASK                       0x00100000L
+#define MH_DEBUG_REG26__WLAST_q                            0x00100000L
+#define MH_DEBUG_REG26__WBURST_IP_q_MASK                   0x00200000L
+#define MH_DEBUG_REG26__WBURST_IP_q                        0x00200000L
+#define MH_DEBUG_REG26__WBURST_CNT_q_MASK                  0x01c00000L
+#define MH_DEBUG_REG26__CP_SEND_QUAL_MASK                  0x02000000L
+#define MH_DEBUG_REG26__CP_SEND_QUAL                       0x02000000L
+#define MH_DEBUG_REG26__CP_MH_write_MASK                   0x04000000L
+#define MH_DEBUG_REG26__CP_MH_write                        0x04000000L
+#define MH_DEBUG_REG26__RB_SEND_QUAL_MASK                  0x08000000L
+#define MH_DEBUG_REG26__RB_SEND_QUAL                       0x08000000L
+#define MH_DEBUG_REG26__ARB_WINNER_MASK                    0x70000000L
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__RF_ARBITER_CONFIG_q_MASK           0x03ffffffL
+#define MH_DEBUG_REG27__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0x1c000000L
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG28__ROQ_MARK_q_MASK                    0x0000ff00L
+#define MH_DEBUG_REG28__ROQ_VALID_q_MASK                   0x00ff0000L
+#define MH_DEBUG_REG28__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG28__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG28__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG28__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG28__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG28__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG28__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG28__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG28__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG28__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG28__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG28__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG29__ROQ_MARK_d_MASK                    0x0000ff00L
+#define MH_DEBUG_REG29__ROQ_VALID_d_MASK                   0x00ff0000L
+#define MH_DEBUG_REG29__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG29__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG29__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG29__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG29__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG29__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG29__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG29__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG29__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG29__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG29__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG29__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__SAME_ROW_BANK_WIN_MASK             0x000000ffL
+#define MH_DEBUG_REG30__SAME_ROW_BANK_REQ_MASK             0x0000ff00L
+#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_WIN_MASK         0x00ff0000L
+#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_REQ_MASK         0xff000000L
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG31__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG31__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG31__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG31__ROQ_MARK_q_0_MASK                  0x00000004L
+#define MH_DEBUG_REG31__ROQ_MARK_q_0                       0x00000004L
+#define MH_DEBUG_REG31__ROQ_VALID_q_0_MASK                 0x00000008L
+#define MH_DEBUG_REG31__ROQ_VALID_q_0                      0x00000008L
+#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0_MASK             0x00000010L
+#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0                  0x00000010L
+#define MH_DEBUG_REG31__ROQ_ADDR_0_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG32__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG32__ROQ_MARK_q_1_MASK                  0x00000004L
+#define MH_DEBUG_REG32__ROQ_MARK_q_1                       0x00000004L
+#define MH_DEBUG_REG32__ROQ_VALID_q_1_MASK                 0x00000008L
+#define MH_DEBUG_REG32__ROQ_VALID_q_1                      0x00000008L
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1_MASK             0x00000010L
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1                  0x00000010L
+#define MH_DEBUG_REG32__ROQ_ADDR_1_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG33__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG33__ROQ_MARK_q_2_MASK                  0x00000004L
+#define MH_DEBUG_REG33__ROQ_MARK_q_2                       0x00000004L
+#define MH_DEBUG_REG33__ROQ_VALID_q_2_MASK                 0x00000008L
+#define MH_DEBUG_REG33__ROQ_VALID_q_2                      0x00000008L
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2_MASK             0x00000010L
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2                  0x00000010L
+#define MH_DEBUG_REG33__ROQ_ADDR_2_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG34__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG34__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG34__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG34__ROQ_MARK_q_3_MASK                  0x00000004L
+#define MH_DEBUG_REG34__ROQ_MARK_q_3                       0x00000004L
+#define MH_DEBUG_REG34__ROQ_VALID_q_3_MASK                 0x00000008L
+#define MH_DEBUG_REG34__ROQ_VALID_q_3                      0x00000008L
+#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3_MASK             0x00000010L
+#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3                  0x00000010L
+#define MH_DEBUG_REG34__ROQ_ADDR_3_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG35__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG35__ROQ_MARK_q_4_MASK                  0x00000004L
+#define MH_DEBUG_REG35__ROQ_MARK_q_4                       0x00000004L
+#define MH_DEBUG_REG35__ROQ_VALID_q_4_MASK                 0x00000008L
+#define MH_DEBUG_REG35__ROQ_VALID_q_4                      0x00000008L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4_MASK             0x00000010L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4                  0x00000010L
+#define MH_DEBUG_REG35__ROQ_ADDR_4_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG36__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG36__ROQ_MARK_q_5_MASK                  0x00000004L
+#define MH_DEBUG_REG36__ROQ_MARK_q_5                       0x00000004L
+#define MH_DEBUG_REG36__ROQ_VALID_q_5_MASK                 0x00000008L
+#define MH_DEBUG_REG36__ROQ_VALID_q_5                      0x00000008L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5_MASK             0x00000010L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5                  0x00000010L
+#define MH_DEBUG_REG36__ROQ_ADDR_5_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG37__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG37__ROQ_MARK_q_6_MASK                  0x00000004L
+#define MH_DEBUG_REG37__ROQ_MARK_q_6                       0x00000004L
+#define MH_DEBUG_REG37__ROQ_VALID_q_6_MASK                 0x00000008L
+#define MH_DEBUG_REG37__ROQ_VALID_q_6                      0x00000008L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6_MASK             0x00000010L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6                  0x00000010L
+#define MH_DEBUG_REG37__ROQ_ADDR_6_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG38__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG38__ROQ_MARK_q_7_MASK                  0x00000004L
+#define MH_DEBUG_REG38__ROQ_MARK_q_7                       0x00000004L
+#define MH_DEBUG_REG38__ROQ_VALID_q_7_MASK                 0x00000008L
+#define MH_DEBUG_REG38__ROQ_VALID_q_7                      0x00000008L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7_MASK             0x00000010L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7                  0x00000010L
+#define MH_DEBUG_REG38__ROQ_ADDR_7_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__ARB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG39__ARB_WE                             0x00000001L
+#define MH_DEBUG_REG39__MMU_RTR_MASK                       0x00000002L
+#define MH_DEBUG_REG39__MMU_RTR                            0x00000002L
+#define MH_DEBUG_REG39__ARB_ID_q_MASK                      0x0000001cL
+#define MH_DEBUG_REG39__ARB_WRITE_q_MASK                   0x00000020L
+#define MH_DEBUG_REG39__ARB_WRITE_q                        0x00000020L
+#define MH_DEBUG_REG39__ARB_BLEN_q_MASK                    0x00000040L
+#define MH_DEBUG_REG39__ARB_BLEN_q                         0x00000040L
+#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY_MASK                0x00000080L
+#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY                     0x00000080L
+#define MH_DEBUG_REG39__ARQ_FIFO_CNT_q_MASK                0x00000700L
+#define MH_DEBUG_REG39__MMU_WE_MASK                        0x00000800L
+#define MH_DEBUG_REG39__MMU_WE                             0x00000800L
+#define MH_DEBUG_REG39__ARQ_RTR_MASK                       0x00001000L
+#define MH_DEBUG_REG39__ARQ_RTR                            0x00001000L
+#define MH_DEBUG_REG39__MMU_ID_MASK                        0x0000e000L
+#define MH_DEBUG_REG39__MMU_WRITE_MASK                     0x00010000L
+#define MH_DEBUG_REG39__MMU_WRITE                          0x00010000L
+#define MH_DEBUG_REG39__MMU_BLEN_MASK                      0x00020000L
+#define MH_DEBUG_REG39__MMU_BLEN                           0x00020000L
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__ARB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG40__ARB_WE                             0x00000001L
+#define MH_DEBUG_REG40__ARB_ID_q_MASK                      0x0000000eL
+#define MH_DEBUG_REG40__ARB_VAD_q_MASK                     0xfffffff0L
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__MMU_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG41__MMU_WE                             0x00000001L
+#define MH_DEBUG_REG41__MMU_ID_MASK                        0x0000000eL
+#define MH_DEBUG_REG41__MMU_PAD_MASK                       0xfffffff0L
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__WDB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG42__WDB_WE                             0x00000001L
+#define MH_DEBUG_REG42__WDB_RTR_SKID_MASK                  0x00000002L
+#define MH_DEBUG_REG42__WDB_RTR_SKID                       0x00000002L
+#define MH_DEBUG_REG42__ARB_WSTRB_q_MASK                   0x000003fcL
+#define MH_DEBUG_REG42__ARB_WLAST_MASK                     0x00000400L
+#define MH_DEBUG_REG42__ARB_WLAST                          0x00000400L
+#define MH_DEBUG_REG42__WDB_CTRL_EMPTY_MASK                0x00000800L
+#define MH_DEBUG_REG42__WDB_CTRL_EMPTY                     0x00000800L
+#define MH_DEBUG_REG42__WDB_FIFO_CNT_q_MASK                0x0001f000L
+#define MH_DEBUG_REG42__WDC_WDB_RE_q_MASK                  0x00020000L
+#define MH_DEBUG_REG42__WDC_WDB_RE_q                       0x00020000L
+#define MH_DEBUG_REG42__WDB_WDC_WID_MASK                   0x001c0000L
+#define MH_DEBUG_REG42__WDB_WDC_WLAST_MASK                 0x00200000L
+#define MH_DEBUG_REG42__WDB_WDC_WLAST                      0x00200000L
+#define MH_DEBUG_REG42__WDB_WDC_WSTRB_MASK                 0x3fc00000L
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_WDATA_q_31_0_MASK              0xffffffffL
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WDATA_q_63_32_MASK             0xffffffffL
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__WDB_WDC_WDATA_31_0_MASK            0xffffffffL
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDB_WDC_WDATA_63_32_MASK           0xffffffffL
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__CTRL_ARC_EMPTY_MASK                0x00000001L
+#define MH_DEBUG_REG47__CTRL_ARC_EMPTY                     0x00000001L
+#define MH_DEBUG_REG47__CTRL_RARC_EMPTY_MASK               0x00000002L
+#define MH_DEBUG_REG47__CTRL_RARC_EMPTY                    0x00000002L
+#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY_MASK                0x00000004L
+#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY                     0x00000004L
+#define MH_DEBUG_REG47__ARQ_CTRL_WRITE_MASK                0x00000008L
+#define MH_DEBUG_REG47__ARQ_CTRL_WRITE                     0x00000008L
+#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS_MASK              0x00000010L
+#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS                   0x00000010L
+#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q_MASK             0x00000020L
+#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q                  0x00000020L
+#define MH_DEBUG_REG47__INFLT_LIMIT_q_MASK                 0x00000040L
+#define MH_DEBUG_REG47__INFLT_LIMIT_q                      0x00000040L
+#define MH_DEBUG_REG47__INFLT_LIMIT_CNT_q_MASK             0x00001f80L
+#define MH_DEBUG_REG47__ARC_CTRL_RE_q_MASK                 0x00002000L
+#define MH_DEBUG_REG47__ARC_CTRL_RE_q                      0x00002000L
+#define MH_DEBUG_REG47__RARC_CTRL_RE_q_MASK                0x00004000L
+#define MH_DEBUG_REG47__RARC_CTRL_RE_q                     0x00004000L
+#define MH_DEBUG_REG47__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG47__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG47__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG47__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG47__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG47__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG47__BVALID_q_MASK                      0x00040000L
+#define MH_DEBUG_REG47__BVALID_q                           0x00040000L
+#define MH_DEBUG_REG47__BREADY_q_MASK                      0x00080000L
+#define MH_DEBUG_REG47__BREADY_q                           0x00080000L
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG48__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG48__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG48__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG48__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG48__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG48__MH_TLBMISS_SEND_MASK               0x00000008L
+#define MH_DEBUG_REG48__MH_TLBMISS_SEND                    0x00000008L
+#define MH_DEBUG_REG48__TLBMISS_VALID_MASK                 0x00000010L
+#define MH_DEBUG_REG48__TLBMISS_VALID                      0x00000010L
+#define MH_DEBUG_REG48__RDC_VALID_MASK                     0x00000020L
+#define MH_DEBUG_REG48__RDC_VALID                          0x00000020L
+#define MH_DEBUG_REG48__RDC_RID_MASK                       0x000001c0L
+#define MH_DEBUG_REG48__RDC_RLAST_MASK                     0x00000200L
+#define MH_DEBUG_REG48__RDC_RLAST                          0x00000200L
+#define MH_DEBUG_REG48__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS_MASK              0x00001000L
+#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS                   0x00001000L
+#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q_MASK             0x00002000L
+#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q                  0x00002000L
+#define MH_DEBUG_REG48__MMU_ID_REQUEST_q_MASK              0x00004000L
+#define MH_DEBUG_REG48__MMU_ID_REQUEST_q                   0x00004000L
+#define MH_DEBUG_REG48__OUTSTANDING_MMUID_CNT_q_MASK       0x001f8000L
+#define MH_DEBUG_REG48__MMU_ID_RESPONSE_MASK               0x00200000L
+#define MH_DEBUG_REG48__MMU_ID_RESPONSE                    0x00200000L
+#define MH_DEBUG_REG48__TLBMISS_RETURN_CNT_q_MASK          0x0fc00000L
+#define MH_DEBUG_REG48__CNT_HOLD_q1_MASK                   0x10000000L
+#define MH_DEBUG_REG48__CNT_HOLD_q1                        0x10000000L
+#define MH_DEBUG_REG48__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0xe0000000L
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__RF_MMU_PAGE_FAULT_MASK             0xffffffffL
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__RF_MMU_CONFIG_q_MASK               0x00ffffffL
+#define MH_DEBUG_REG50__ARB_ID_q_MASK                      0x07000000L
+#define MH_DEBUG_REG50__ARB_WRITE_q_MASK                   0x08000000L
+#define MH_DEBUG_REG50__ARB_WRITE_q                        0x08000000L
+#define MH_DEBUG_REG50__client_behavior_q_MASK             0x30000000L
+#define MH_DEBUG_REG50__ARB_WE_MASK                        0x40000000L
+#define MH_DEBUG_REG50__ARB_WE                             0x40000000L
+#define MH_DEBUG_REG50__MMU_RTR_MASK                       0x80000000L
+#define MH_DEBUG_REG50__MMU_RTR                            0x80000000L
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__stage1_valid_MASK                  0x00000001L
+#define MH_DEBUG_REG51__stage1_valid                       0x00000001L
+#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q_MASK             0x00000002L
+#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q                  0x00000002L
+#define MH_DEBUG_REG51__pa_in_mpu_range_MASK               0x00000004L
+#define MH_DEBUG_REG51__pa_in_mpu_range                    0x00000004L
+#define MH_DEBUG_REG51__tag_match_q_MASK                   0x00000008L
+#define MH_DEBUG_REG51__tag_match_q                        0x00000008L
+#define MH_DEBUG_REG51__tag_miss_q_MASK                    0x00000010L
+#define MH_DEBUG_REG51__tag_miss_q                         0x00000010L
+#define MH_DEBUG_REG51__va_in_range_q_MASK                 0x00000020L
+#define MH_DEBUG_REG51__va_in_range_q                      0x00000020L
+#define MH_DEBUG_REG51__MMU_MISS_MASK                      0x00000040L
+#define MH_DEBUG_REG51__MMU_MISS                           0x00000040L
+#define MH_DEBUG_REG51__MMU_READ_MISS_MASK                 0x00000080L
+#define MH_DEBUG_REG51__MMU_READ_MISS                      0x00000080L
+#define MH_DEBUG_REG51__MMU_WRITE_MISS_MASK                0x00000100L
+#define MH_DEBUG_REG51__MMU_WRITE_MISS                     0x00000100L
+#define MH_DEBUG_REG51__MMU_HIT_MASK                       0x00000200L
+#define MH_DEBUG_REG51__MMU_HIT                            0x00000200L
+#define MH_DEBUG_REG51__MMU_READ_HIT_MASK                  0x00000400L
+#define MH_DEBUG_REG51__MMU_READ_HIT                       0x00000400L
+#define MH_DEBUG_REG51__MMU_WRITE_HIT_MASK                 0x00000800L
+#define MH_DEBUG_REG51__MMU_WRITE_HIT                      0x00000800L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS_MASK        0x00001000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS             0x00001000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT_MASK         0x00002000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT              0x00002000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS_MASK     0x00004000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS          0x00004000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT_MASK      0x00008000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT           0x00008000L
+#define MH_DEBUG_REG51__REQ_VA_OFFSET_q_MASK               0xffff0000L
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__ARQ_RTR_MASK                       0x00000001L
+#define MH_DEBUG_REG52__ARQ_RTR                            0x00000001L
+#define MH_DEBUG_REG52__MMU_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG52__MMU_WE                             0x00000002L
+#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q_MASK             0x00000004L
+#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q                  0x00000004L
+#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS_MASK              0x00000008L
+#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS                   0x00000008L
+#define MH_DEBUG_REG52__MH_TLBMISS_SEND_MASK               0x00000010L
+#define MH_DEBUG_REG52__MH_TLBMISS_SEND                    0x00000010L
+#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L
+#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH  0x00000020L
+#define MH_DEBUG_REG52__pa_in_mpu_range_MASK               0x00000040L
+#define MH_DEBUG_REG52__pa_in_mpu_range                    0x00000040L
+#define MH_DEBUG_REG52__stage1_valid_MASK                  0x00000080L
+#define MH_DEBUG_REG52__stage1_valid                       0x00000080L
+#define MH_DEBUG_REG52__stage2_valid_MASK                  0x00000100L
+#define MH_DEBUG_REG52__stage2_valid                       0x00000100L
+#define MH_DEBUG_REG52__client_behavior_q_MASK             0x00000600L
+#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q_MASK             0x00000800L
+#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q                  0x00000800L
+#define MH_DEBUG_REG52__tag_match_q_MASK                   0x00001000L
+#define MH_DEBUG_REG52__tag_match_q                        0x00001000L
+#define MH_DEBUG_REG52__tag_miss_q_MASK                    0x00002000L
+#define MH_DEBUG_REG52__tag_miss_q                         0x00002000L
+#define MH_DEBUG_REG52__va_in_range_q_MASK                 0x00004000L
+#define MH_DEBUG_REG52__va_in_range_q                      0x00004000L
+#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q_MASK          0x00008000L
+#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q               0x00008000L
+#define MH_DEBUG_REG52__TAG_valid_q_MASK                   0xffff0000L
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__TAG0_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG53__TAG_valid_q_0_MASK                 0x00002000L
+#define MH_DEBUG_REG53__TAG_valid_q_0                      0x00002000L
+#define MH_DEBUG_REG53__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG53__TAG1_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG53__TAG_valid_q_1_MASK                 0x20000000L
+#define MH_DEBUG_REG53__TAG_valid_q_1                      0x20000000L
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__TAG2_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG54__TAG_valid_q_2_MASK                 0x00002000L
+#define MH_DEBUG_REG54__TAG_valid_q_2                      0x00002000L
+#define MH_DEBUG_REG54__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG54__TAG3_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG54__TAG_valid_q_3_MASK                 0x20000000L
+#define MH_DEBUG_REG54__TAG_valid_q_3                      0x20000000L
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG4_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG55__TAG_valid_q_4_MASK                 0x00002000L
+#define MH_DEBUG_REG55__TAG_valid_q_4                      0x00002000L
+#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG55__TAG5_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG55__TAG_valid_q_5_MASK                 0x20000000L
+#define MH_DEBUG_REG55__TAG_valid_q_5                      0x20000000L
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG6_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG56__TAG_valid_q_6_MASK                 0x00002000L
+#define MH_DEBUG_REG56__TAG_valid_q_6                      0x00002000L
+#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG56__TAG7_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG56__TAG_valid_q_7_MASK                 0x20000000L
+#define MH_DEBUG_REG56__TAG_valid_q_7                      0x20000000L
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG8_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG57__TAG_valid_q_8_MASK                 0x00002000L
+#define MH_DEBUG_REG57__TAG_valid_q_8                      0x00002000L
+#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG57__TAG9_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG57__TAG_valid_q_9_MASK                 0x20000000L
+#define MH_DEBUG_REG57__TAG_valid_q_9                      0x20000000L
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG10_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG58__TAG_valid_q_10_MASK                0x00002000L
+#define MH_DEBUG_REG58__TAG_valid_q_10                     0x00002000L
+#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG58__TAG11_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG58__TAG_valid_q_11_MASK                0x20000000L
+#define MH_DEBUG_REG58__TAG_valid_q_11                     0x20000000L
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG12_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG59__TAG_valid_q_12_MASK                0x00002000L
+#define MH_DEBUG_REG59__TAG_valid_q_12                     0x00002000L
+#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG59__TAG13_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG59__TAG_valid_q_13_MASK                0x20000000L
+#define MH_DEBUG_REG59__TAG_valid_q_13                     0x20000000L
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG14_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG60__TAG_valid_q_14_MASK                0x00002000L
+#define MH_DEBUG_REG60__TAG_valid_q_14                     0x00002000L
+#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG60__TAG15_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG60__TAG_valid_q_15_MASK                0x20000000L
+#define MH_DEBUG_REG60__TAG_valid_q_15                     0x20000000L
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE_MASK                     0x00000001L
+#define MH_MMU_CONFIG__MMU_ENABLE                          0x00000001L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK              0x00000002L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE                   0x00000002L
+#define MH_MMU_CONFIG__RESERVED1_MASK                      0x0000000cL
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK             0x00000030L
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK             0x000000c0L
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK            0x00000300L
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK            0x00000c00L
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK            0x00003000L
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK            0x0000c000L
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK            0x00030000L
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK           0x000c0000L
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK           0x00300000L
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK             0x00c00000L
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK             0x00000fffL
+#define MH_MMU_VA_RANGE__VA_BASE_MASK                      0xfffff000L
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE_MASK                       0xfffff000L
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK                 0x00000001L
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT                      0x00000001L
+#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK                    0x00000002L
+#define MH_MMU_PAGE_FAULT__OP_TYPE                         0x00000002L
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK              0x0000000cL
+#define MH_MMU_PAGE_FAULT__AXI_ID_MASK                     0x00000070L
+#define MH_MMU_PAGE_FAULT__RESERVED1_MASK                  0x00000080L
+#define MH_MMU_PAGE_FAULT__RESERVED1                       0x00000080L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK   0x00000100L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE        0x00000100L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK       0x00000200L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE            0x00000200L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK      0x00000400L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR           0x00000400L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK     0x00000800L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR          0x00000800L
+#define MH_MMU_PAGE_FAULT__REQ_VA_MASK                     0xfffff000L
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK                 0xffffffe0L
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK             0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL                  0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK              0x00000002L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC                   0x00000002L
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE_MASK                     0xfffff000L
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END_MASK                       0xfffff000L
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK                     0x00000002L
+#define WAIT_UNTIL__WAIT_RE_VSYNC                          0x00000002L
+#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK                     0x00000004L
+#define WAIT_UNTIL__WAIT_FE_VSYNC                          0x00000004L
+#define WAIT_UNTIL__WAIT_VSYNC_MASK                        0x00000008L
+#define WAIT_UNTIL__WAIT_VSYNC                             0x00000008L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK                    0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0                         0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK                    0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1                         0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK                    0x00000040L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2                         0x00000040L
+#define WAIT_UNTIL__WAIT_CMDFIFO_MASK                      0x00000400L
+#define WAIT_UNTIL__WAIT_CMDFIFO                           0x00000400L
+#define WAIT_UNTIL__WAIT_2D_IDLE_MASK                      0x00004000L
+#define WAIT_UNTIL__WAIT_2D_IDLE                           0x00004000L
+#define WAIT_UNTIL__WAIT_3D_IDLE_MASK                      0x00008000L
+#define WAIT_UNTIL__WAIT_3D_IDLE                           0x00008000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK                 0x00010000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN                      0x00010000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK                 0x00020000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN                      0x00020000L
+#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK                   0x00f00000L
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK           0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI                0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK      0x00000020L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI           0x00000020L
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL_MASK                    0x0000001fL
+#define RBBM_STATUS__TC_BUSY_MASK                          0x00000020L
+#define RBBM_STATUS__TC_BUSY                               0x00000020L
+#define RBBM_STATUS__HIRQ_PENDING_MASK                     0x00000100L
+#define RBBM_STATUS__HIRQ_PENDING                          0x00000100L
+#define RBBM_STATUS__CPRQ_PENDING_MASK                     0x00000200L
+#define RBBM_STATUS__CPRQ_PENDING                          0x00000200L
+#define RBBM_STATUS__CFRQ_PENDING_MASK                     0x00000400L
+#define RBBM_STATUS__CFRQ_PENDING                          0x00000400L
+#define RBBM_STATUS__PFRQ_PENDING_MASK                     0x00000800L
+#define RBBM_STATUS__PFRQ_PENDING                          0x00000800L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK                  0x00001000L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA                       0x00001000L
+#define RBBM_STATUS__RBBM_WU_BUSY_MASK                     0x00004000L
+#define RBBM_STATUS__RBBM_WU_BUSY                          0x00004000L
+#define RBBM_STATUS__CP_NRT_BUSY_MASK                      0x00010000L
+#define RBBM_STATUS__CP_NRT_BUSY                           0x00010000L
+#define RBBM_STATUS__MH_BUSY_MASK                          0x00040000L
+#define RBBM_STATUS__MH_BUSY                               0x00040000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK                0x00080000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY                     0x00080000L
+#define RBBM_STATUS__SX_BUSY_MASK                          0x00200000L
+#define RBBM_STATUS__SX_BUSY                               0x00200000L
+#define RBBM_STATUS__TPC_BUSY_MASK                         0x00400000L
+#define RBBM_STATUS__TPC_BUSY                              0x00400000L
+#define RBBM_STATUS__SC_CNTX_BUSY_MASK                     0x01000000L
+#define RBBM_STATUS__SC_CNTX_BUSY                          0x01000000L
+#define RBBM_STATUS__PA_BUSY_MASK                          0x02000000L
+#define RBBM_STATUS__PA_BUSY                               0x02000000L
+#define RBBM_STATUS__VGT_BUSY_MASK                         0x04000000L
+#define RBBM_STATUS__VGT_BUSY                              0x04000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK                   0x08000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY                        0x08000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK                    0x10000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY                         0x10000000L
+#define RBBM_STATUS__RB_CNTX_BUSY_MASK                     0x40000000L
+#define RBBM_STATUS__RB_CNTX_BUSY                          0x40000000L
+#define RBBM_STATUS__GUI_ACTIVE_MASK                       0x80000000L
+#define RBBM_STATUS__GUI_ACTIVE                            0x80000000L
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE_MASK                0x00000001L
+#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE                     0x00000001L
+#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE_MASK                0x00000002L
+#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE                     0x00000002L
+#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE_MASK                0x00000004L
+#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE                     0x00000004L
+#define RBBM_DSPLY__VSYNC_ACTIVE_MASK                      0x00000008L
+#define RBBM_DSPLY__VSYNC_ACTIVE                           0x00000008L
+#define RBBM_DSPLY__USE_DISPLAY_ID0_MASK                   0x00000010L
+#define RBBM_DSPLY__USE_DISPLAY_ID0                        0x00000010L
+#define RBBM_DSPLY__USE_DISPLAY_ID1_MASK                   0x00000020L
+#define RBBM_DSPLY__USE_DISPLAY_ID1                        0x00000020L
+#define RBBM_DSPLY__USE_DISPLAY_ID2_MASK                   0x00000040L
+#define RBBM_DSPLY__USE_DISPLAY_ID2                        0x00000040L
+#define RBBM_DSPLY__SW_CNTL_MASK                           0x00000080L
+#define RBBM_DSPLY__SW_CNTL                                0x00000080L
+#define RBBM_DSPLY__NUM_BUFS_MASK                          0x00000300L
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__BUFFER_ID_MASK                 0x00000003L
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST_MASK                  0xffffffffL
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK            0x0000ffffL
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK           0x00ff0000L
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK               0xff000000L
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK               0xffffffffL
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0_MASK                   0x000000ffL
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1_MASK                   0x0000000fL
+#define RBBM_PERIPHID1__DESIGNER0_MASK                     0x000000f0L
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1_MASK                     0x0000000fL
+#define RBBM_PERIPHID2__REVISION_MASK                      0x000000f0L
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK           0x00000003L
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK          0x0000000cL
+#define RBBM_PERIPHID3__MH_INTERFACE_MASK                  0x00000030L
+#define RBBM_PERIPHID3__CONTINUATION_MASK                  0x00000080L
+#define RBBM_PERIPHID3__CONTINUATION                       0x00000080L
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT_MASK                       0x000000ffL
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK               0x0001ff00L
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK            0x0000001fL
+#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK                    0x000003e0L
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK                0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_CP                     0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK                0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA                     0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK                0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH                     0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK                0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC                     0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK                0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ                     0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK                0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX                     0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK               0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB                    0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK                0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC                     0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK               0x00010000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT                    0x00010000L
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK    0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE         0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK        0x00000004L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE             0x00000004L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK    0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE         0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK     0x00000010L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE          0x00000010L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK    0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE         0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE   0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE   0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK     0x00000100L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE          0x00000100L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK        0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE             0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK   0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE        0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK   0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE        0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK   0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE        0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK   0x00004000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE        0x00004000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK   0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE        0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK   0x00010000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE        0x00010000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK   0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE        0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK   0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE        0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE   0x00080000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK     0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE          0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK    0x00200000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE         0x00200000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK      0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE           0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK    0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE         0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK  0x01000000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE       0x01000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK       0x02000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE            0x02000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK    0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE         0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK        0x08000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE             0x08000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK     0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE          0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK    0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE         0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK    0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE         0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK  0x80000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE       0x80000000L
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK     0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE          0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK     0x00000004L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE          0x00000004L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK   0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE        0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE      0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK   0x00000020L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE        0x00000020L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE     0x00000040L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK      0x00000080L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE           0x00000080L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK    0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE         0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK    0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE         0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK    0x00000800L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE         0x00000800L
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK                0x0000ffffL
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK             0x80000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE                  0x80000000L
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK                   0x00000001L
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE                        0x00000001L
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR_MASK                        0x00000002L
+#define RBBM_DEBUG__IGNORE_RTR                             0x00000002L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK                0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU                     0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK             0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC                  0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK             0x00000010L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI                  0x00000010L
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK         0x00000f00L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK                 0x00010000L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI                      0x00010000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK      0x00020000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI           0x00020000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK     0x00040000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI          0x00040000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK      0x00080000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI           0x00080000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK                    0x00100000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR                         0x00100000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK                   0x00200000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR                        0x00200000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK                    0x00400000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR                         0x00400000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK        0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI             0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK               0x01000000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR                    0x01000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK               0x80000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY                    0x80000000L
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS_MASK                 0x0001fffcL
+#define RBBM_READ_ERROR__READ_REQUESTER_MASK               0x40000000L
+#define RBBM_READ_ERROR__READ_REQUESTER                    0x40000000L
+#define RBBM_READ_ERROR__READ_ERROR_MASK                   0x80000000L
+#define RBBM_READ_ERROR__READ_ERROR                        0x80000000L
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK   0x000000ffL
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK                 0x00000001L
+#define RBBM_INT_CNTL__RDERR_INT_MASK                      0x00000001L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK        0x00000002L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK             0x00000002L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK              0x00080000L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK                   0x00080000L
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK               0x00000001L
+#define RBBM_INT_STATUS__RDERR_INT_STAT                    0x00000001L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK      0x00000002L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT           0x00000002L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK            0x00080000L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT                 0x00080000L
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK_MASK                   0x00000001L
+#define RBBM_INT_ACK__RDERR_INT_ACK                        0x00000001L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK          0x00000002L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK               0x00000002L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK                0x00080000L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK                     0x00080000L
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK                0x00000020L
+#define MASTER_INT_SIGNAL__MH_INT_STAT                     0x00000020L
+#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK                0x40000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT                     0x40000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK              0x80000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT                   0x80000000L
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK     0x0000003fL
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK          0xffffffffL
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK          0x0000ffffL
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE_MASK                           0xffffffe0L
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ_MASK                          0x0000003fL
+#define CP_RB_CNTL__RB_BLKSZ_MASK                          0x00003f00L
+#define CP_RB_CNTL__BUF_SWAP_MASK                          0x00030000L
+#define CP_RB_CNTL__RB_POLL_EN_MASK                        0x00100000L
+#define CP_RB_CNTL__RB_POLL_EN                             0x00100000L
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK                      0x08000000L
+#define CP_RB_CNTL__RB_NO_UPDATE                           0x08000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK                    0x80000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA                         0x80000000L
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                 0xfffffffcL
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR_MASK                           0x000fffffL
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK                     0x000fffffL
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR_MASK                           0x000fffffL
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK             0x0fffffffL
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK             0xf0000000L
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK                 0xfffffffcL
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE_MASK                         0xfffffffcL
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK                       0x000fffffL
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE_MASK                         0xfffffffcL
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK                       0x000fffffL
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE_MASK                           0xfffffffcL
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK                         0x000fffffL
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK            0x0000000fL
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK            0x00000f00L
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK             0x000f0000L
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END_MASK                    0x001f0000L
+#define CP_MEQ_THRESHOLDS__ROQ_END_MASK                    0x1f000000L
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK                    0x0000007fL
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK                     0x00007f00L
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK                     0x007f0000L
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST_MASK                      0x0000007fL
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK                         0x0000001fL
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK              0x0000007fL
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK              0x007f0000L
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK           0x0000007fL
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK           0x007f0000L
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK           0x0000007fL
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK           0x007f0000L
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK            0x00000007L
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK            0x00000700L
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK                   0x0000007fL
+#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK                   0x007f0000L
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR_MASK                         0x000003ffL
+#define CP_MEQ_STAT__MEQ_WPTR_MASK                         0x03ff0000L
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK                   0x00000001L
+#define CP_MIU_TAG_STAT__TAG_0_STAT                        0x00000001L
+#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK                   0x00000002L
+#define CP_MIU_TAG_STAT__TAG_1_STAT                        0x00000002L
+#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK                   0x00000004L
+#define CP_MIU_TAG_STAT__TAG_2_STAT                        0x00000004L
+#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK                   0x00000008L
+#define CP_MIU_TAG_STAT__TAG_3_STAT                        0x00000008L
+#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK                   0x00000010L
+#define CP_MIU_TAG_STAT__TAG_4_STAT                        0x00000010L
+#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK                   0x00000020L
+#define CP_MIU_TAG_STAT__TAG_5_STAT                        0x00000020L
+#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK                   0x00000040L
+#define CP_MIU_TAG_STAT__TAG_6_STAT                        0x00000040L
+#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK                   0x00000080L
+#define CP_MIU_TAG_STAT__TAG_7_STAT                        0x00000080L
+#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK                   0x00000100L
+#define CP_MIU_TAG_STAT__TAG_8_STAT                        0x00000100L
+#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK                   0x00000200L
+#define CP_MIU_TAG_STAT__TAG_9_STAT                        0x00000200L
+#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK                  0x00000400L
+#define CP_MIU_TAG_STAT__TAG_10_STAT                       0x00000400L
+#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK                  0x00000800L
+#define CP_MIU_TAG_STAT__TAG_11_STAT                       0x00000800L
+#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK                  0x00001000L
+#define CP_MIU_TAG_STAT__TAG_12_STAT                       0x00001000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK                  0x00002000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT                       0x00002000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK                  0x00004000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT                       0x00004000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK                  0x00008000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT                       0x00008000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK                  0x00010000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT                       0x00010000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK                  0x00020000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT                       0x00020000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK           0x80000000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG                0x80000000L
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX_MASK                       0x0000007fL
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK                   0x00030000L
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA_MASK                         0xffffffffL
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX_MASK                        0x0000ffffL
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK            0x02000000L
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY                 0x02000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK            0x04000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY                 0x04000000L
+#define CP_ME_CNTL__ME_HALT_MASK                           0x10000000L
+#define CP_ME_CNTL__ME_HALT                                0x10000000L
+#define CP_ME_CNTL__ME_BUSY_MASK                           0x20000000L
+#define CP_ME_CNTL__ME_BUSY                                0x20000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE_MASK                     0x80000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE                          0x80000000L
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA_MASK                   0xffffffffL
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK                   0xffffffffL
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR_MASK                       0xffffffffL
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK             0x007fffffL
+#define CP_DEBUG__PREDICATE_DISABLE_MASK                   0x00800000L
+#define CP_DEBUG__PREDICATE_DISABLE                        0x00800000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK                 0x01000000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE                      0x01000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK             0x02000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE                  0x02000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK                  0x04000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS                       0x04000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK                 0x08000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE                      0x08000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK              0x10000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE                   0x10000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK              0x40000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL                   0x40000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK              0x80000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE                   0x80000000L
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK                0xffffffffL
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK                0xffffffffL
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK                0xffffffffL
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK                0xffffffffL
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK                0xffffffffL
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK                0xffffffffL
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK                0xffffffffL
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK                0xffffffffL
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK_MASK                    0x000000ffL
+#define SCRATCH_UMSK__SCRATCH_SWAP_MASK                    0x00030000L
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR_MASK                    0xffffffe0L
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM                    0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR                   0x00000002L
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM                    0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR                   0x00000002L
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK               0x00000001L
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC                    0x00000001L
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK                0x00000003L
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK                0xfffffffcL
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK                0xffffffffL
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK   0x00000001L
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR        0x00000001L
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK  0x00000003L
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK  0xfffffffcL
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK  0xffffffffL
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK_MASK                      0x00080000L
+#define CP_INT_CNTL__SW_INT_MASK                           0x00080000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK             0x00800000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK                  0x00800000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK                0x01000000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK                     0x01000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK        0x02000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK             0x02000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK          0x04000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK               0x04000000L
+#define CP_INT_CNTL__IB_ERROR_MASK_MASK                    0x08000000L
+#define CP_INT_CNTL__IB_ERROR_MASK                         0x08000000L
+#define CP_INT_CNTL__IB2_INT_MASK_MASK                     0x20000000L
+#define CP_INT_CNTL__IB2_INT_MASK                          0x20000000L
+#define CP_INT_CNTL__IB1_INT_MASK_MASK                     0x40000000L
+#define CP_INT_CNTL__IB1_INT_MASK                          0x40000000L
+#define CP_INT_CNTL__RB_INT_MASK_MASK                      0x80000000L
+#define CP_INT_CNTL__RB_INT_MASK                           0x80000000L
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT_MASK                    0x00080000L
+#define CP_INT_STATUS__SW_INT_STAT                         0x00080000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK           0x00800000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT                0x00800000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK              0x01000000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT                   0x01000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK      0x02000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT           0x02000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK        0x04000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT             0x04000000L
+#define CP_INT_STATUS__IB_ERROR_STAT_MASK                  0x08000000L
+#define CP_INT_STATUS__IB_ERROR_STAT                       0x08000000L
+#define CP_INT_STATUS__IB2_INT_STAT_MASK                   0x20000000L
+#define CP_INT_STATUS__IB2_INT_STAT                        0x20000000L
+#define CP_INT_STATUS__IB1_INT_STAT_MASK                   0x40000000L
+#define CP_INT_STATUS__IB1_INT_STAT                        0x40000000L
+#define CP_INT_STATUS__RB_INT_STAT_MASK                    0x80000000L
+#define CP_INT_STATUS__RB_INT_STAT                         0x80000000L
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK_MASK                        0x00080000L
+#define CP_INT_ACK__SW_INT_ACK                             0x00080000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK               0x00800000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK                    0x00800000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK                  0x01000000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK                       0x01000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK          0x02000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK               0x02000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK            0x04000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK                 0x04000000L
+#define CP_INT_ACK__IB_ERROR_ACK_MASK                      0x08000000L
+#define CP_INT_ACK__IB_ERROR_ACK                           0x08000000L
+#define CP_INT_ACK__IB2_INT_ACK_MASK                       0x20000000L
+#define CP_INT_ACK__IB2_INT_ACK                            0x20000000L
+#define CP_INT_ACK__IB1_INT_ACK_MASK                       0x40000000L
+#define CP_INT_ACK__IB1_INT_ACK                            0x40000000L
+#define CP_INT_ACK__RB_INT_ACK_MASK                        0x80000000L
+#define CP_INT_ACK__RB_INT_ACK                             0x80000000L
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                 0x000001ffL
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK                 0x00ffffffL
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK                0x0000000fL
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK          0x00000300L
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK          0x0000003fL
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK               0xffffffffL
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK               0x0000ffffL
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK                   0xffffffffL
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK                   0xffffffffL
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK               0xffffffffL
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK               0xffffffffL
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0_MASK                      0x00000001L
+#define CP_NV_FLAGS_0__DISCARD_0                           0x00000001L
+#define CP_NV_FLAGS_0__END_RCVD_0_MASK                     0x00000002L
+#define CP_NV_FLAGS_0__END_RCVD_0                          0x00000002L
+#define CP_NV_FLAGS_0__DISCARD_1_MASK                      0x00000004L
+#define CP_NV_FLAGS_0__DISCARD_1                           0x00000004L
+#define CP_NV_FLAGS_0__END_RCVD_1_MASK                     0x00000008L
+#define CP_NV_FLAGS_0__END_RCVD_1                          0x00000008L
+#define CP_NV_FLAGS_0__DISCARD_2_MASK                      0x00000010L
+#define CP_NV_FLAGS_0__DISCARD_2                           0x00000010L
+#define CP_NV_FLAGS_0__END_RCVD_2_MASK                     0x00000020L
+#define CP_NV_FLAGS_0__END_RCVD_2                          0x00000020L
+#define CP_NV_FLAGS_0__DISCARD_3_MASK                      0x00000040L
+#define CP_NV_FLAGS_0__DISCARD_3                           0x00000040L
+#define CP_NV_FLAGS_0__END_RCVD_3_MASK                     0x00000080L
+#define CP_NV_FLAGS_0__END_RCVD_3                          0x00000080L
+#define CP_NV_FLAGS_0__DISCARD_4_MASK                      0x00000100L
+#define CP_NV_FLAGS_0__DISCARD_4                           0x00000100L
+#define CP_NV_FLAGS_0__END_RCVD_4_MASK                     0x00000200L
+#define CP_NV_FLAGS_0__END_RCVD_4                          0x00000200L
+#define CP_NV_FLAGS_0__DISCARD_5_MASK                      0x00000400L
+#define CP_NV_FLAGS_0__DISCARD_5                           0x00000400L
+#define CP_NV_FLAGS_0__END_RCVD_5_MASK                     0x00000800L
+#define CP_NV_FLAGS_0__END_RCVD_5                          0x00000800L
+#define CP_NV_FLAGS_0__DISCARD_6_MASK                      0x00001000L
+#define CP_NV_FLAGS_0__DISCARD_6                           0x00001000L
+#define CP_NV_FLAGS_0__END_RCVD_6_MASK                     0x00002000L
+#define CP_NV_FLAGS_0__END_RCVD_6                          0x00002000L
+#define CP_NV_FLAGS_0__DISCARD_7_MASK                      0x00004000L
+#define CP_NV_FLAGS_0__DISCARD_7                           0x00004000L
+#define CP_NV_FLAGS_0__END_RCVD_7_MASK                     0x00008000L
+#define CP_NV_FLAGS_0__END_RCVD_7                          0x00008000L
+#define CP_NV_FLAGS_0__DISCARD_8_MASK                      0x00010000L
+#define CP_NV_FLAGS_0__DISCARD_8                           0x00010000L
+#define CP_NV_FLAGS_0__END_RCVD_8_MASK                     0x00020000L
+#define CP_NV_FLAGS_0__END_RCVD_8                          0x00020000L
+#define CP_NV_FLAGS_0__DISCARD_9_MASK                      0x00040000L
+#define CP_NV_FLAGS_0__DISCARD_9                           0x00040000L
+#define CP_NV_FLAGS_0__END_RCVD_9_MASK                     0x00080000L
+#define CP_NV_FLAGS_0__END_RCVD_9                          0x00080000L
+#define CP_NV_FLAGS_0__DISCARD_10_MASK                     0x00100000L
+#define CP_NV_FLAGS_0__DISCARD_10                          0x00100000L
+#define CP_NV_FLAGS_0__END_RCVD_10_MASK                    0x00200000L
+#define CP_NV_FLAGS_0__END_RCVD_10                         0x00200000L
+#define CP_NV_FLAGS_0__DISCARD_11_MASK                     0x00400000L
+#define CP_NV_FLAGS_0__DISCARD_11                          0x00400000L
+#define CP_NV_FLAGS_0__END_RCVD_11_MASK                    0x00800000L
+#define CP_NV_FLAGS_0__END_RCVD_11                         0x00800000L
+#define CP_NV_FLAGS_0__DISCARD_12_MASK                     0x01000000L
+#define CP_NV_FLAGS_0__DISCARD_12                          0x01000000L
+#define CP_NV_FLAGS_0__END_RCVD_12_MASK                    0x02000000L
+#define CP_NV_FLAGS_0__END_RCVD_12                         0x02000000L
+#define CP_NV_FLAGS_0__DISCARD_13_MASK                     0x04000000L
+#define CP_NV_FLAGS_0__DISCARD_13                          0x04000000L
+#define CP_NV_FLAGS_0__END_RCVD_13_MASK                    0x08000000L
+#define CP_NV_FLAGS_0__END_RCVD_13                         0x08000000L
+#define CP_NV_FLAGS_0__DISCARD_14_MASK                     0x10000000L
+#define CP_NV_FLAGS_0__DISCARD_14                          0x10000000L
+#define CP_NV_FLAGS_0__END_RCVD_14_MASK                    0x20000000L
+#define CP_NV_FLAGS_0__END_RCVD_14                         0x20000000L
+#define CP_NV_FLAGS_0__DISCARD_15_MASK                     0x40000000L
+#define CP_NV_FLAGS_0__DISCARD_15                          0x40000000L
+#define CP_NV_FLAGS_0__END_RCVD_15_MASK                    0x80000000L
+#define CP_NV_FLAGS_0__END_RCVD_15                         0x80000000L
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16_MASK                     0x00000001L
+#define CP_NV_FLAGS_1__DISCARD_16                          0x00000001L
+#define CP_NV_FLAGS_1__END_RCVD_16_MASK                    0x00000002L
+#define CP_NV_FLAGS_1__END_RCVD_16                         0x00000002L
+#define CP_NV_FLAGS_1__DISCARD_17_MASK                     0x00000004L
+#define CP_NV_FLAGS_1__DISCARD_17                          0x00000004L
+#define CP_NV_FLAGS_1__END_RCVD_17_MASK                    0x00000008L
+#define CP_NV_FLAGS_1__END_RCVD_17                         0x00000008L
+#define CP_NV_FLAGS_1__DISCARD_18_MASK                     0x00000010L
+#define CP_NV_FLAGS_1__DISCARD_18                          0x00000010L
+#define CP_NV_FLAGS_1__END_RCVD_18_MASK                    0x00000020L
+#define CP_NV_FLAGS_1__END_RCVD_18                         0x00000020L
+#define CP_NV_FLAGS_1__DISCARD_19_MASK                     0x00000040L
+#define CP_NV_FLAGS_1__DISCARD_19                          0x00000040L
+#define CP_NV_FLAGS_1__END_RCVD_19_MASK                    0x00000080L
+#define CP_NV_FLAGS_1__END_RCVD_19                         0x00000080L
+#define CP_NV_FLAGS_1__DISCARD_20_MASK                     0x00000100L
+#define CP_NV_FLAGS_1__DISCARD_20                          0x00000100L
+#define CP_NV_FLAGS_1__END_RCVD_20_MASK                    0x00000200L
+#define CP_NV_FLAGS_1__END_RCVD_20                         0x00000200L
+#define CP_NV_FLAGS_1__DISCARD_21_MASK                     0x00000400L
+#define CP_NV_FLAGS_1__DISCARD_21                          0x00000400L
+#define CP_NV_FLAGS_1__END_RCVD_21_MASK                    0x00000800L
+#define CP_NV_FLAGS_1__END_RCVD_21                         0x00000800L
+#define CP_NV_FLAGS_1__DISCARD_22_MASK                     0x00001000L
+#define CP_NV_FLAGS_1__DISCARD_22                          0x00001000L
+#define CP_NV_FLAGS_1__END_RCVD_22_MASK                    0x00002000L
+#define CP_NV_FLAGS_1__END_RCVD_22                         0x00002000L
+#define CP_NV_FLAGS_1__DISCARD_23_MASK                     0x00004000L
+#define CP_NV_FLAGS_1__DISCARD_23                          0x00004000L
+#define CP_NV_FLAGS_1__END_RCVD_23_MASK                    0x00008000L
+#define CP_NV_FLAGS_1__END_RCVD_23                         0x00008000L
+#define CP_NV_FLAGS_1__DISCARD_24_MASK                     0x00010000L
+#define CP_NV_FLAGS_1__DISCARD_24                          0x00010000L
+#define CP_NV_FLAGS_1__END_RCVD_24_MASK                    0x00020000L
+#define CP_NV_FLAGS_1__END_RCVD_24                         0x00020000L
+#define CP_NV_FLAGS_1__DISCARD_25_MASK                     0x00040000L
+#define CP_NV_FLAGS_1__DISCARD_25                          0x00040000L
+#define CP_NV_FLAGS_1__END_RCVD_25_MASK                    0x00080000L
+#define CP_NV_FLAGS_1__END_RCVD_25                         0x00080000L
+#define CP_NV_FLAGS_1__DISCARD_26_MASK                     0x00100000L
+#define CP_NV_FLAGS_1__DISCARD_26                          0x00100000L
+#define CP_NV_FLAGS_1__END_RCVD_26_MASK                    0x00200000L
+#define CP_NV_FLAGS_1__END_RCVD_26                         0x00200000L
+#define CP_NV_FLAGS_1__DISCARD_27_MASK                     0x00400000L
+#define CP_NV_FLAGS_1__DISCARD_27                          0x00400000L
+#define CP_NV_FLAGS_1__END_RCVD_27_MASK                    0x00800000L
+#define CP_NV_FLAGS_1__END_RCVD_27                         0x00800000L
+#define CP_NV_FLAGS_1__DISCARD_28_MASK                     0x01000000L
+#define CP_NV_FLAGS_1__DISCARD_28                          0x01000000L
+#define CP_NV_FLAGS_1__END_RCVD_28_MASK                    0x02000000L
+#define CP_NV_FLAGS_1__END_RCVD_28                         0x02000000L
+#define CP_NV_FLAGS_1__DISCARD_29_MASK                     0x04000000L
+#define CP_NV_FLAGS_1__DISCARD_29                          0x04000000L
+#define CP_NV_FLAGS_1__END_RCVD_29_MASK                    0x08000000L
+#define CP_NV_FLAGS_1__END_RCVD_29                         0x08000000L
+#define CP_NV_FLAGS_1__DISCARD_30_MASK                     0x10000000L
+#define CP_NV_FLAGS_1__DISCARD_30                          0x10000000L
+#define CP_NV_FLAGS_1__END_RCVD_30_MASK                    0x20000000L
+#define CP_NV_FLAGS_1__END_RCVD_30                         0x20000000L
+#define CP_NV_FLAGS_1__DISCARD_31_MASK                     0x40000000L
+#define CP_NV_FLAGS_1__DISCARD_31                          0x40000000L
+#define CP_NV_FLAGS_1__END_RCVD_31_MASK                    0x80000000L
+#define CP_NV_FLAGS_1__END_RCVD_31                         0x80000000L
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32_MASK                     0x00000001L
+#define CP_NV_FLAGS_2__DISCARD_32                          0x00000001L
+#define CP_NV_FLAGS_2__END_RCVD_32_MASK                    0x00000002L
+#define CP_NV_FLAGS_2__END_RCVD_32                         0x00000002L
+#define CP_NV_FLAGS_2__DISCARD_33_MASK                     0x00000004L
+#define CP_NV_FLAGS_2__DISCARD_33                          0x00000004L
+#define CP_NV_FLAGS_2__END_RCVD_33_MASK                    0x00000008L
+#define CP_NV_FLAGS_2__END_RCVD_33                         0x00000008L
+#define CP_NV_FLAGS_2__DISCARD_34_MASK                     0x00000010L
+#define CP_NV_FLAGS_2__DISCARD_34                          0x00000010L
+#define CP_NV_FLAGS_2__END_RCVD_34_MASK                    0x00000020L
+#define CP_NV_FLAGS_2__END_RCVD_34                         0x00000020L
+#define CP_NV_FLAGS_2__DISCARD_35_MASK                     0x00000040L
+#define CP_NV_FLAGS_2__DISCARD_35                          0x00000040L
+#define CP_NV_FLAGS_2__END_RCVD_35_MASK                    0x00000080L
+#define CP_NV_FLAGS_2__END_RCVD_35                         0x00000080L
+#define CP_NV_FLAGS_2__DISCARD_36_MASK                     0x00000100L
+#define CP_NV_FLAGS_2__DISCARD_36                          0x00000100L
+#define CP_NV_FLAGS_2__END_RCVD_36_MASK                    0x00000200L
+#define CP_NV_FLAGS_2__END_RCVD_36                         0x00000200L
+#define CP_NV_FLAGS_2__DISCARD_37_MASK                     0x00000400L
+#define CP_NV_FLAGS_2__DISCARD_37                          0x00000400L
+#define CP_NV_FLAGS_2__END_RCVD_37_MASK                    0x00000800L
+#define CP_NV_FLAGS_2__END_RCVD_37                         0x00000800L
+#define CP_NV_FLAGS_2__DISCARD_38_MASK                     0x00001000L
+#define CP_NV_FLAGS_2__DISCARD_38                          0x00001000L
+#define CP_NV_FLAGS_2__END_RCVD_38_MASK                    0x00002000L
+#define CP_NV_FLAGS_2__END_RCVD_38                         0x00002000L
+#define CP_NV_FLAGS_2__DISCARD_39_MASK                     0x00004000L
+#define CP_NV_FLAGS_2__DISCARD_39                          0x00004000L
+#define CP_NV_FLAGS_2__END_RCVD_39_MASK                    0x00008000L
+#define CP_NV_FLAGS_2__END_RCVD_39                         0x00008000L
+#define CP_NV_FLAGS_2__DISCARD_40_MASK                     0x00010000L
+#define CP_NV_FLAGS_2__DISCARD_40                          0x00010000L
+#define CP_NV_FLAGS_2__END_RCVD_40_MASK                    0x00020000L
+#define CP_NV_FLAGS_2__END_RCVD_40                         0x00020000L
+#define CP_NV_FLAGS_2__DISCARD_41_MASK                     0x00040000L
+#define CP_NV_FLAGS_2__DISCARD_41                          0x00040000L
+#define CP_NV_FLAGS_2__END_RCVD_41_MASK                    0x00080000L
+#define CP_NV_FLAGS_2__END_RCVD_41                         0x00080000L
+#define CP_NV_FLAGS_2__DISCARD_42_MASK                     0x00100000L
+#define CP_NV_FLAGS_2__DISCARD_42                          0x00100000L
+#define CP_NV_FLAGS_2__END_RCVD_42_MASK                    0x00200000L
+#define CP_NV_FLAGS_2__END_RCVD_42                         0x00200000L
+#define CP_NV_FLAGS_2__DISCARD_43_MASK                     0x00400000L
+#define CP_NV_FLAGS_2__DISCARD_43                          0x00400000L
+#define CP_NV_FLAGS_2__END_RCVD_43_MASK                    0x00800000L
+#define CP_NV_FLAGS_2__END_RCVD_43                         0x00800000L
+#define CP_NV_FLAGS_2__DISCARD_44_MASK                     0x01000000L
+#define CP_NV_FLAGS_2__DISCARD_44                          0x01000000L
+#define CP_NV_FLAGS_2__END_RCVD_44_MASK                    0x02000000L
+#define CP_NV_FLAGS_2__END_RCVD_44                         0x02000000L
+#define CP_NV_FLAGS_2__DISCARD_45_MASK                     0x04000000L
+#define CP_NV_FLAGS_2__DISCARD_45                          0x04000000L
+#define CP_NV_FLAGS_2__END_RCVD_45_MASK                    0x08000000L
+#define CP_NV_FLAGS_2__END_RCVD_45                         0x08000000L
+#define CP_NV_FLAGS_2__DISCARD_46_MASK                     0x10000000L
+#define CP_NV_FLAGS_2__DISCARD_46                          0x10000000L
+#define CP_NV_FLAGS_2__END_RCVD_46_MASK                    0x20000000L
+#define CP_NV_FLAGS_2__END_RCVD_46                         0x20000000L
+#define CP_NV_FLAGS_2__DISCARD_47_MASK                     0x40000000L
+#define CP_NV_FLAGS_2__DISCARD_47                          0x40000000L
+#define CP_NV_FLAGS_2__END_RCVD_47_MASK                    0x80000000L
+#define CP_NV_FLAGS_2__END_RCVD_47                         0x80000000L
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48_MASK                     0x00000001L
+#define CP_NV_FLAGS_3__DISCARD_48                          0x00000001L
+#define CP_NV_FLAGS_3__END_RCVD_48_MASK                    0x00000002L
+#define CP_NV_FLAGS_3__END_RCVD_48                         0x00000002L
+#define CP_NV_FLAGS_3__DISCARD_49_MASK                     0x00000004L
+#define CP_NV_FLAGS_3__DISCARD_49                          0x00000004L
+#define CP_NV_FLAGS_3__END_RCVD_49_MASK                    0x00000008L
+#define CP_NV_FLAGS_3__END_RCVD_49                         0x00000008L
+#define CP_NV_FLAGS_3__DISCARD_50_MASK                     0x00000010L
+#define CP_NV_FLAGS_3__DISCARD_50                          0x00000010L
+#define CP_NV_FLAGS_3__END_RCVD_50_MASK                    0x00000020L
+#define CP_NV_FLAGS_3__END_RCVD_50                         0x00000020L
+#define CP_NV_FLAGS_3__DISCARD_51_MASK                     0x00000040L
+#define CP_NV_FLAGS_3__DISCARD_51                          0x00000040L
+#define CP_NV_FLAGS_3__END_RCVD_51_MASK                    0x00000080L
+#define CP_NV_FLAGS_3__END_RCVD_51                         0x00000080L
+#define CP_NV_FLAGS_3__DISCARD_52_MASK                     0x00000100L
+#define CP_NV_FLAGS_3__DISCARD_52                          0x00000100L
+#define CP_NV_FLAGS_3__END_RCVD_52_MASK                    0x00000200L
+#define CP_NV_FLAGS_3__END_RCVD_52                         0x00000200L
+#define CP_NV_FLAGS_3__DISCARD_53_MASK                     0x00000400L
+#define CP_NV_FLAGS_3__DISCARD_53                          0x00000400L
+#define CP_NV_FLAGS_3__END_RCVD_53_MASK                    0x00000800L
+#define CP_NV_FLAGS_3__END_RCVD_53                         0x00000800L
+#define CP_NV_FLAGS_3__DISCARD_54_MASK                     0x00001000L
+#define CP_NV_FLAGS_3__DISCARD_54                          0x00001000L
+#define CP_NV_FLAGS_3__END_RCVD_54_MASK                    0x00002000L
+#define CP_NV_FLAGS_3__END_RCVD_54                         0x00002000L
+#define CP_NV_FLAGS_3__DISCARD_55_MASK                     0x00004000L
+#define CP_NV_FLAGS_3__DISCARD_55                          0x00004000L
+#define CP_NV_FLAGS_3__END_RCVD_55_MASK                    0x00008000L
+#define CP_NV_FLAGS_3__END_RCVD_55                         0x00008000L
+#define CP_NV_FLAGS_3__DISCARD_56_MASK                     0x00010000L
+#define CP_NV_FLAGS_3__DISCARD_56                          0x00010000L
+#define CP_NV_FLAGS_3__END_RCVD_56_MASK                    0x00020000L
+#define CP_NV_FLAGS_3__END_RCVD_56                         0x00020000L
+#define CP_NV_FLAGS_3__DISCARD_57_MASK                     0x00040000L
+#define CP_NV_FLAGS_3__DISCARD_57                          0x00040000L
+#define CP_NV_FLAGS_3__END_RCVD_57_MASK                    0x00080000L
+#define CP_NV_FLAGS_3__END_RCVD_57                         0x00080000L
+#define CP_NV_FLAGS_3__DISCARD_58_MASK                     0x00100000L
+#define CP_NV_FLAGS_3__DISCARD_58                          0x00100000L
+#define CP_NV_FLAGS_3__END_RCVD_58_MASK                    0x00200000L
+#define CP_NV_FLAGS_3__END_RCVD_58                         0x00200000L
+#define CP_NV_FLAGS_3__DISCARD_59_MASK                     0x00400000L
+#define CP_NV_FLAGS_3__DISCARD_59                          0x00400000L
+#define CP_NV_FLAGS_3__END_RCVD_59_MASK                    0x00800000L
+#define CP_NV_FLAGS_3__END_RCVD_59                         0x00800000L
+#define CP_NV_FLAGS_3__DISCARD_60_MASK                     0x01000000L
+#define CP_NV_FLAGS_3__DISCARD_60                          0x01000000L
+#define CP_NV_FLAGS_3__END_RCVD_60_MASK                    0x02000000L
+#define CP_NV_FLAGS_3__END_RCVD_60                         0x02000000L
+#define CP_NV_FLAGS_3__DISCARD_61_MASK                     0x04000000L
+#define CP_NV_FLAGS_3__DISCARD_61                          0x04000000L
+#define CP_NV_FLAGS_3__END_RCVD_61_MASK                    0x08000000L
+#define CP_NV_FLAGS_3__END_RCVD_61                         0x08000000L
+#define CP_NV_FLAGS_3__DISCARD_62_MASK                     0x10000000L
+#define CP_NV_FLAGS_3__DISCARD_62                          0x10000000L
+#define CP_NV_FLAGS_3__END_RCVD_62_MASK                    0x20000000L
+#define CP_NV_FLAGS_3__END_RCVD_62                         0x20000000L
+#define CP_NV_FLAGS_3__DISCARD_63_MASK                     0x40000000L
+#define CP_NV_FLAGS_3__DISCARD_63                          0x40000000L
+#define CP_NV_FLAGS_3__END_RCVD_63_MASK                    0x80000000L
+#define CP_NV_FLAGS_3__END_RCVD_63                         0x80000000L
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK       0x0000001fL
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK         0xffffffffL
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER_MASK                      0xffffffffL
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY_MASK                          0x00000001L
+#define CP_STAT__MIU_WR_BUSY                               0x00000001L
+#define CP_STAT__MIU_RD_REQ_BUSY_MASK                      0x00000002L
+#define CP_STAT__MIU_RD_REQ_BUSY                           0x00000002L
+#define CP_STAT__MIU_RD_RETURN_BUSY_MASK                   0x00000004L
+#define CP_STAT__MIU_RD_RETURN_BUSY                        0x00000004L
+#define CP_STAT__RBIU_BUSY_MASK                            0x00000008L
+#define CP_STAT__RBIU_BUSY                                 0x00000008L
+#define CP_STAT__RCIU_BUSY_MASK                            0x00000010L
+#define CP_STAT__RCIU_BUSY                                 0x00000010L
+#define CP_STAT__CSF_RING_BUSY_MASK                        0x00000020L
+#define CP_STAT__CSF_RING_BUSY                             0x00000020L
+#define CP_STAT__CSF_INDIRECTS_BUSY_MASK                   0x00000040L
+#define CP_STAT__CSF_INDIRECTS_BUSY                        0x00000040L
+#define CP_STAT__CSF_INDIRECT2_BUSY_MASK                   0x00000080L
+#define CP_STAT__CSF_INDIRECT2_BUSY                        0x00000080L
+#define CP_STAT__CSF_ST_BUSY_MASK                          0x00000200L
+#define CP_STAT__CSF_ST_BUSY                               0x00000200L
+#define CP_STAT__CSF_BUSY_MASK                             0x00000400L
+#define CP_STAT__CSF_BUSY                                  0x00000400L
+#define CP_STAT__RING_QUEUE_BUSY_MASK                      0x00000800L
+#define CP_STAT__RING_QUEUE_BUSY                           0x00000800L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK                 0x00001000L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY                      0x00001000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK                 0x00002000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY                      0x00002000L
+#define CP_STAT__ST_QUEUE_BUSY_MASK                        0x00010000L
+#define CP_STAT__ST_QUEUE_BUSY                             0x00010000L
+#define CP_STAT__PFP_BUSY_MASK                             0x00020000L
+#define CP_STAT__PFP_BUSY                                  0x00020000L
+#define CP_STAT__MEQ_RING_BUSY_MASK                        0x00040000L
+#define CP_STAT__MEQ_RING_BUSY                             0x00040000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK                   0x00080000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY                        0x00080000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK                   0x00100000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY                        0x00100000L
+#define CP_STAT__MIU_WC_STALL_MASK                         0x00200000L
+#define CP_STAT__MIU_WC_STALL                              0x00200000L
+#define CP_STAT__CP_NRT_BUSY_MASK                          0x00400000L
+#define CP_STAT__CP_NRT_BUSY                               0x00400000L
+#define CP_STAT___3D_BUSY_MASK                             0x00800000L
+#define CP_STAT___3D_BUSY                                  0x00800000L
+#define CP_STAT__ME_BUSY_MASK                              0x04000000L
+#define CP_STAT__ME_BUSY                                   0x04000000L
+#define CP_STAT__ME_WC_BUSY_MASK                           0x20000000L
+#define CP_STAT__ME_WC_BUSY                                0x20000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK              0x40000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY                   0x40000000L
+#define CP_STAT__CP_BUSY_MASK                              0x80000000L
+#define CP_STAT__CP_BUSY                                   0x80000000L
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE_MASK                          0xffffffffL
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE_MASK                          0xffffffffL
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK           0x000000ffL
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK       0x00000100L
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA            0x00000100L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK             0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA                  0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK             0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA                  0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK             0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA                  0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK             0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA                  0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK             0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA                  0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK             0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA                  0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK             0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA                  0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK             0x00010000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA                  0x00010000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK               0x02000000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA                    0x02000000L
+#define COHER_STATUS_PM4__STATUS_MASK                      0x80000000L
+#define COHER_STATUS_PM4__STATUS                           0x80000000L
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE_MASK                         0xffffffffL
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE_MASK                         0xffffffffL
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK          0x000000ffL
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK      0x00000100L
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA           0x00000100L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK            0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA                 0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK            0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA                 0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK            0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA                 0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK            0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA                 0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK            0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA                 0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK            0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA                 0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK            0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA                 0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK            0x00010000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA                 0x00010000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK              0x02000000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA                   0x02000000L
+#define COHER_STATUS_HOST__STATUS_MASK                     0x80000000L
+#define COHER_STATUS_HOST__STATUS                          0x80000000L
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0_MASK                0xfffff000L
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1_MASK                0xfffff000L
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2_MASK                0xfffff000L
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3_MASK                0xfffff000L
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4_MASK                0xfffff000L
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5_MASK                0xfffff000L
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6_MASK                0xfffff000L
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7_MASK                0xfffff000L
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH_MASK                0x00003fffL
+#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK                 0x0000c000L
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT_MASK                   0x0000000fL
+#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK               0x00000030L
+#define RB_COLOR_INFO__COLOR_LINEAR_MASK                   0x00000040L
+#define RB_COLOR_INFO__COLOR_LINEAR                        0x00000040L
+#define RB_COLOR_INFO__COLOR_ENDIAN_MASK                   0x00000180L
+#define RB_COLOR_INFO__COLOR_SWAP_MASK                     0x00000600L
+#define RB_COLOR_INFO__COLOR_BASE_MASK                     0xfffff000L
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK                   0x00000001L
+#define RB_DEPTH_INFO__DEPTH_FORMAT                        0x00000001L
+#define RB_DEPTH_INFO__DEPTH_BASE_MASK                     0xfffff000L
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF_MASK                 0x000000ffL
+#define RB_STENCILREFMASK__STENCILMASK_MASK                0x0000ff00L
+#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK           0x00ff0000L
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF_MASK                       0xffffffffL
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED_MASK                      0x00000001L
+#define RB_COLOR_MASK__WRITE_RED                           0x00000001L
+#define RB_COLOR_MASK__WRITE_GREEN_MASK                    0x00000002L
+#define RB_COLOR_MASK__WRITE_GREEN                         0x00000002L
+#define RB_COLOR_MASK__WRITE_BLUE_MASK                     0x00000004L
+#define RB_COLOR_MASK__WRITE_BLUE                          0x00000004L
+#define RB_COLOR_MASK__WRITE_ALPHA_MASK                    0x00000008L
+#define RB_COLOR_MASK__WRITE_ALPHA                         0x00000008L
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED_MASK                       0x000000ffL
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN_MASK                   0x000000ffL
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE_MASK                     0x000000ffL
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK                   0x000000ffL
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED_MASK                         0x000000ffL
+#define RB_FOG_COLOR__FOG_GREEN_MASK                       0x0000ff00L
+#define RB_FOG_COLOR__FOG_BLUE_MASK                        0x00ff0000L
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK           0x000000ffL
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK          0x0000ff00L
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK     0x00ff0000L
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK               0x00000001L
+#define RB_DEPTHCONTROL__STENCIL_ENABLE                    0x00000001L
+#define RB_DEPTHCONTROL__Z_ENABLE_MASK                     0x00000002L
+#define RB_DEPTHCONTROL__Z_ENABLE                          0x00000002L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK               0x00000004L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE                    0x00000004L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK               0x00000008L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE                    0x00000008L
+#define RB_DEPTHCONTROL__ZFUNC_MASK                        0x00000070L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK              0x00000080L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE                   0x00000080L
+#define RB_DEPTHCONTROL__STENCILFUNC_MASK                  0x00000700L
+#define RB_DEPTHCONTROL__STENCILFAIL_MASK                  0x00003800L
+#define RB_DEPTHCONTROL__STENCILZPASS_MASK                 0x0001c000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_MASK                 0x000e0000L
+#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK               0x00700000L
+#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK               0x03800000L
+#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK              0x1c000000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK              0xe0000000L
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK               0x0000001fL
+#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK               0x000000e0L
+#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK              0x00001f00L
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK               0x001f0000L
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK               0x00e00000L
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK              0x1f000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK           0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE                0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_MASK                  0x40000000L
+#define RB_BLENDCONTROL__BLEND_FORCE                       0x40000000L
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC_MASK                   0x00000007L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK            0x00000008L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE                 0x00000008L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK         0x00000010L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE              0x00000010L
+#define RB_COLORCONTROL__BLEND_DISABLE_MASK                0x00000020L
+#define RB_COLORCONTROL__BLEND_DISABLE                     0x00000020L
+#define RB_COLORCONTROL__FOG_ENABLE_MASK                   0x00000040L
+#define RB_COLORCONTROL__FOG_ENABLE                        0x00000040L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK               0x00000080L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG                    0x00000080L
+#define RB_COLORCONTROL__ROP_CODE_MASK                     0x00000f00L
+#define RB_COLORCONTROL__DITHER_MODE_MASK                  0x00003000L
+#define RB_COLORCONTROL__DITHER_TYPE_MASK                  0x0000c000L
+#define RB_COLORCONTROL__PIXEL_FOG_MASK                    0x00010000L
+#define RB_COLORCONTROL__PIXEL_FOG                         0x00010000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK        0x03000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK        0x0c000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK        0x30000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK        0xc0000000L
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE_MASK                    0x00000007L
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK           0xffffffffL
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK           0x00000007L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK           0x00000008L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE                0x00000008L
+#define RB_COPY_CONTROL__CLEAR_MASK_MASK                   0x000000f0L
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK             0xfffff000L
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK           0x000001ffL
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK           0x00000007L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK           0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR                0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK           0x000000f0L
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK             0x00000300L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK      0x00000c00L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK      0x00003000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK        0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED             0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK      0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN           0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK       0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE            0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK      0x00020000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA           0x00020000L
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK           0x00001fffL
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK           0x03ffe000L
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK                   0xffffffffL
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK       0x00000001L
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT            0x00000001L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK        0x00000002L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT             0x00000002L
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK       0xffffffffL
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK       0x00000001L
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE            0x00000001L
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK           0x00000006L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK              0x00000008L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM                   0x00000008L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH      0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK      0x00000020L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP           0x00000020L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK      0x00000040L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP           0x00000040L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK             0x00000080L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE                  0x00000080L
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK              0x00001f00L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK              0x00004000L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE                   0x00004000L
+#define RB_BC_CONTROL__CRC_MODE_MASK                       0x00008000L
+#define RB_BC_CONTROL__CRC_MODE                            0x00008000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK        0x00010000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS             0x00010000L
+#define RB_BC_CONTROL__DISABLE_ACCUM_MASK                  0x00020000L
+#define RB_BC_CONTROL__DISABLE_ACCUM                       0x00020000L
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK               0x003c0000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK      0x00400000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE           0x00400000L
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK          0x07800000L
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK      0x18000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK  0x20000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE       0x20000000L
+#define RB_BC_CONTROL__RESERVED9_MASK                      0x40000000L
+#define RB_BC_CONTROL__RESERVED9                           0x40000000L
+#define RB_BC_CONTROL__RESERVED10_MASK                     0x80000000L
+#define RB_BC_CONTROL__RESERVED10                          0x80000000L
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE_MASK                     0x0000000fL
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK             0x00000030L
+#define RB_EDRAM_INFO__EDRAM_RANGE_MASK                    0xffffc000L
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA_MASK                      0xffffffffL
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK                0x00000001L
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE                     0x00000001L
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK_MASK                         0xffffffffL
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK               0xffffffffL
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK               0xffffffffL
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK             0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL                  0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK             0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL                  0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK             0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL                  0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK             0x00000008L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL                  0x00000008L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK            0x00000010L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL                 0x00000010L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK            0x00000020L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL                 0x00000020L
+#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK                     0x00000040L
+#define RB_DEBUG_0__RDREQ_Z1_FULL                          0x00000040L
+#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK                     0x00000080L
+#define RB_DEBUG_0__RDREQ_Z0_FULL                          0x00000080L
+#define RB_DEBUG_0__RDREQ_C1_FULL_MASK                     0x00000100L
+#define RB_DEBUG_0__RDREQ_C1_FULL                          0x00000100L
+#define RB_DEBUG_0__RDREQ_C0_FULL_MASK                     0x00000200L
+#define RB_DEBUG_0__RDREQ_C0_FULL                          0x00000200L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK            0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL                 0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK            0x00000800L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL                 0x00000800L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK            0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL                 0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK            0x00002000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL                 0x00002000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK                0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL                     0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK                0x00008000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL                     0x00008000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK                     0x00010000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL                          0x00010000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK                     0x00020000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL                          0x00020000L
+#define RB_DEBUG_0__WRREQ_C1_FULL_MASK                     0x00040000L
+#define RB_DEBUG_0__WRREQ_C1_FULL                          0x00040000L
+#define RB_DEBUG_0__WRREQ_C0_FULL_MASK                     0x00080000L
+#define RB_DEBUG_0__WRREQ_C0_FULL                          0x00080000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK              0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL                   0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK              0x00200000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL                   0x00200000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK              0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL                   0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK              0x00800000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL                   0x00800000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK           0x01000000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL                0x01000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK           0x02000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL                0x02000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL_MASK                     0x04000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL                          0x04000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL_MASK                     0x08000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL                          0x08000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK                    0x10000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL                         0x10000000L
+#define RB_DEBUG_0__C_REQ_FULL_MASK                        0x20000000L
+#define RB_DEBUG_0__C_REQ_FULL                             0x20000000L
+#define RB_DEBUG_0__C_MASK_FULL_MASK                       0x40000000L
+#define RB_DEBUG_0__C_MASK_FULL                            0x40000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK                   0x80000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL                        0x80000000L
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK                0x00000001L
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY                     0x00000001L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK                0x00000002L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY                     0x00000002L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK                0x00000004L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY                     0x00000004L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK                0x00000008L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY                     0x00000008L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK           0x00000010L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY                0x00000010L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK           0x00000020L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY                0x00000020L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK                    0x00000040L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY                         0x00000040L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK                    0x00000080L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY                         0x00000080L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK                    0x00000100L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY                         0x00000100L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK                    0x00000200L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY                         0x00000200L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK           0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY                0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK           0x00000800L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY                0x00000800L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK           0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY                0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK           0x00002000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY                0x00002000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK               0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY                    0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK               0x00008000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY                    0x00008000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK                    0x00010000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY                         0x00010000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK                    0x00020000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY                         0x00020000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK                0x00040000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY                     0x00040000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK                0x00080000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY                     0x00080000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK             0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY                  0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY                  0x00200000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY                  0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK             0x00800000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY                  0x00800000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK          0x01000000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY               0x01000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK          0x02000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY               0x02000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK                    0x04000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY                         0x04000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK                    0x08000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY                         0x08000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK                   0x10000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY                        0x10000000L
+#define RB_DEBUG_1__C_REQ_EMPTY_MASK                       0x20000000L
+#define RB_DEBUG_1__C_REQ_EMPTY                            0x20000000L
+#define RB_DEBUG_1__C_MASK_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_1__C_MASK_EMPTY                           0x40000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK                  0x80000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY                       0x80000000L
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK                   0x0000000fL
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK                 0x000007f0L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK                   0x00000800L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG                        0x00000800L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK                 0x00001000L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG                      0x00001000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK                0x00002000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT                     0x00002000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK                   0x00004000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL                        0x00004000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK                0x00008000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL                     0x00008000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK                0x00010000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL                     0x00010000L
+#define RB_DEBUG_2__Z0_MASK_FULL_MASK                      0x00020000L
+#define RB_DEBUG_2__Z0_MASK_FULL                           0x00020000L
+#define RB_DEBUG_2__Z1_MASK_FULL_MASK                      0x00040000L
+#define RB_DEBUG_2__Z1_MASK_FULL                           0x00040000L
+#define RB_DEBUG_2__Z0_REQ_FULL_MASK                       0x00080000L
+#define RB_DEBUG_2__Z0_REQ_FULL                            0x00080000L
+#define RB_DEBUG_2__Z1_REQ_FULL_MASK                       0x00100000L
+#define RB_DEBUG_2__Z1_REQ_FULL                            0x00100000L
+#define RB_DEBUG_2__Z_SAMP_FULL_MASK                       0x00200000L
+#define RB_DEBUG_2__Z_SAMP_FULL                            0x00200000L
+#define RB_DEBUG_2__Z_TILE_FULL_MASK                       0x00400000L
+#define RB_DEBUG_2__Z_TILE_FULL                            0x00400000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK                  0x00800000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY                       0x00800000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK               0x01000000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY                    0x01000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK               0x02000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY                    0x02000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK                     0x04000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY                          0x04000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK                     0x08000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY                          0x08000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK                      0x10000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY                           0x10000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK                      0x20000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY                           0x20000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY                           0x40000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY_MASK                      0x80000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY                           0x80000000L
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID_MASK                       0x0000000fL
+#define RB_DEBUG_3__ACCUM_FLUSHING_MASK                    0x000000f0L
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK           0x00003f00L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK             0x00004000L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID                  0x00004000L
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK               0x00078000L
+#define RB_DEBUG_3__SHD_FULL_MASK                          0x00080000L
+#define RB_DEBUG_3__SHD_FULL                               0x00080000L
+#define RB_DEBUG_3__SHD_EMPTY_MASK                         0x00100000L
+#define RB_DEBUG_3__SHD_EMPTY                              0x00100000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY                  0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY                  0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK              0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL                   0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK              0x01000000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL                   0x01000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK                  0x02000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY                       0x02000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK                  0x04000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY                       0x04000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK                   0x08000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL                        0x08000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK                   0x10000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL                        0x10000000L
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK               0x00000001L
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG                    0x00000001L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK               0x00000002L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG                    0x00000002L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK             0x00000004L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG                  0x00000004L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK             0x00000008L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG                  0x00000008L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK             0x00000010L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY                  0x00000010L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK            0x00000020L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY                 0x00000020L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK              0x00000040L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL                   0x00000040L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK             0x00000080L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL                  0x00000080L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK       0x00000100L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW            0x00000100L
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK               0x00001e00L
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK             0x00000001L
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR                  0x00000001L
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP   0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK     0x00000600L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h
new file mode 100644
index 000000000000..6a229a8e79e2
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h
@@ -0,0 +1,581 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _yamato_OFFSET_HEADER
+#define _yamato_OFFSET_HEADER
+
+
+// Registers from PA block
+
+#define mmPA_CL_VPORT_XSCALE           0x210F
+#define mmPA_CL_VPORT_XOFFSET          0x2110
+#define mmPA_CL_VPORT_YSCALE           0x2111
+#define mmPA_CL_VPORT_YOFFSET          0x2112
+#define mmPA_CL_VPORT_ZSCALE           0x2113
+#define mmPA_CL_VPORT_ZOFFSET          0x2114
+#define mmPA_CL_VTE_CNTL               0x2206
+#define mmPA_CL_CLIP_CNTL              0x2204
+#define mmPA_CL_GB_VERT_CLIP_ADJ       0x2303
+#define mmPA_CL_GB_VERT_DISC_ADJ       0x2304
+#define mmPA_CL_GB_HORZ_CLIP_ADJ       0x2305
+#define mmPA_CL_GB_HORZ_DISC_ADJ       0x2306
+#define mmPA_CL_ENHANCE                0x0C85
+#define mmPA_SC_ENHANCE                0x0CA5
+#define mmPA_SU_VTX_CNTL               0x2302
+#define mmPA_SU_POINT_SIZE             0x2280
+#define mmPA_SU_POINT_MINMAX           0x2281
+#define mmPA_SU_LINE_CNTL              0x2282
+#define mmPA_SU_SC_MODE_CNTL           0x2205
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383
+#define mmPA_SU_PERFCOUNTER0_SELECT    0x0C88
+#define mmPA_SU_PERFCOUNTER1_SELECT    0x0C89
+#define mmPA_SU_PERFCOUNTER2_SELECT    0x0C8A
+#define mmPA_SU_PERFCOUNTER3_SELECT    0x0C8B
+#define mmPA_SU_PERFCOUNTER0_LOW       0x0C8C
+#define mmPA_SU_PERFCOUNTER0_HI        0x0C8D
+#define mmPA_SU_PERFCOUNTER1_LOW       0x0C8E
+#define mmPA_SU_PERFCOUNTER1_HI        0x0C8F
+#define mmPA_SU_PERFCOUNTER2_LOW       0x0C90
+#define mmPA_SU_PERFCOUNTER2_HI        0x0C91
+#define mmPA_SU_PERFCOUNTER3_LOW       0x0C92
+#define mmPA_SU_PERFCOUNTER3_HI        0x0C93
+#define mmPA_SC_WINDOW_OFFSET          0x2080
+#define mmPA_SC_AA_CONFIG              0x2301
+#define mmPA_SC_AA_MASK                0x2312
+#define mmPA_SC_LINE_STIPPLE           0x2283
+#define mmPA_SC_LINE_CNTL              0x2300
+#define mmPA_SC_WINDOW_SCISSOR_TL      0x2081
+#define mmPA_SC_WINDOW_SCISSOR_BR      0x2082
+#define mmPA_SC_SCREEN_SCISSOR_TL      0x200E
+#define mmPA_SC_SCREEN_SCISSOR_BR      0x200F
+#define mmPA_SC_VIZ_QUERY              0x2293
+#define mmPA_SC_VIZ_QUERY_STATUS       0x0C44
+#define mmPA_SC_LINE_STIPPLE_STATE     0x0C40
+#define mmPA_SC_PERFCOUNTER0_SELECT    0x0C98
+#define mmPA_SC_PERFCOUNTER0_LOW       0x0C99
+#define mmPA_SC_PERFCOUNTER0_HI        0x0C9A
+#define mmPA_CL_CNTL_STATUS            0x0C84
+#define mmPA_SU_CNTL_STATUS            0x0C94
+#define mmPA_SC_CNTL_STATUS            0x0CA4
+#define mmPA_SU_DEBUG_CNTL             0x0C80
+#define mmPA_SU_DEBUG_DATA             0x0C81
+#define mmPA_SC_DEBUG_CNTL             0x0C82
+#define mmPA_SC_DEBUG_DATA             0x0C83
+
+
+// Registers from VGT block
+
+#define mmGFX_COPY_STATE               0x21F4
+#define mmVGT_DRAW_INITIATOR           0x21FC
+#define mmVGT_EVENT_INITIATOR          0x21F9
+#define mmVGT_DMA_BASE                 0x21FA
+#define mmVGT_DMA_SIZE                 0x21FB
+#define mmVGT_BIN_BASE                 0x21FE
+#define mmVGT_BIN_SIZE                 0x21FF
+#define mmVGT_CURRENT_BIN_ID_MIN       0x2207
+#define mmVGT_CURRENT_BIN_ID_MAX       0x2203
+#define mmVGT_IMMED_DATA               0x21FD
+#define mmVGT_MAX_VTX_INDX             0x2100
+#define mmVGT_MIN_VTX_INDX             0x2101
+#define mmVGT_INDX_OFFSET              0x2102
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL  0x2316
+#define mmVGT_OUT_DEALLOC_CNTL         0x2317
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103
+#define mmVGT_ENHANCE                  0x2294
+#define mmVGT_VTX_VECT_EJECT_REG       0x0C2C
+#define mmVGT_LAST_COPY_STATE          0x0C30
+#define mmVGT_DEBUG_CNTL               0x0C38
+#define mmVGT_DEBUG_DATA               0x0C39
+#define mmVGT_CNTL_STATUS              0x0C3C
+#define mmVGT_CRC_SQ_DATA              0x0C3A
+#define mmVGT_CRC_SQ_CTRL              0x0C3B
+#define mmVGT_PERFCOUNTER0_SELECT      0x0C48
+#define mmVGT_PERFCOUNTER1_SELECT      0x0C49
+#define mmVGT_PERFCOUNTER2_SELECT      0x0C4A
+#define mmVGT_PERFCOUNTER3_SELECT      0x0C4B
+#define mmVGT_PERFCOUNTER0_LOW         0x0C4C
+#define mmVGT_PERFCOUNTER1_LOW         0x0C4E
+#define mmVGT_PERFCOUNTER2_LOW         0x0C50
+#define mmVGT_PERFCOUNTER3_LOW         0x0C52
+#define mmVGT_PERFCOUNTER0_HI          0x0C4D
+#define mmVGT_PERFCOUNTER1_HI          0x0C4F
+#define mmVGT_PERFCOUNTER2_HI          0x0C51
+#define mmVGT_PERFCOUNTER3_HI          0x0C53
+
+
+// Registers from TP block
+
+#define mmTC_CNTL_STATUS               0x0E00
+#define mmTCR_CHICKEN                  0x0E02
+#define mmTCF_CHICKEN                  0x0E03
+#define mmTCM_CHICKEN                  0x0E04
+#define mmTCR_PERFCOUNTER0_SELECT      0x0E05
+#define mmTCR_PERFCOUNTER1_SELECT      0x0E08
+#define mmTCR_PERFCOUNTER0_HI          0x0E06
+#define mmTCR_PERFCOUNTER1_HI          0x0E09
+#define mmTCR_PERFCOUNTER0_LOW         0x0E07
+#define mmTCR_PERFCOUNTER1_LOW         0x0E0A
+#define mmTP_TC_CLKGATE_CNTL           0x0E17
+#define mmTPC_CNTL_STATUS              0x0E18
+#define mmTPC_DEBUG0                   0x0E19
+#define mmTPC_DEBUG1                   0x0E1A
+#define mmTPC_CHICKEN                  0x0E1B
+#define mmTP0_CNTL_STATUS              0x0E1C
+#define mmTP0_DEBUG                    0x0E1D
+#define mmTP0_CHICKEN                  0x0E1E
+#define mmTP0_PERFCOUNTER0_SELECT      0x0E1F
+#define mmTP0_PERFCOUNTER0_HI          0x0E20
+#define mmTP0_PERFCOUNTER0_LOW         0x0E21
+#define mmTP0_PERFCOUNTER1_SELECT      0x0E22
+#define mmTP0_PERFCOUNTER1_HI          0x0E23
+#define mmTP0_PERFCOUNTER1_LOW         0x0E24
+#define mmTCM_PERFCOUNTER0_SELECT      0x0E54
+#define mmTCM_PERFCOUNTER1_SELECT      0x0E57
+#define mmTCM_PERFCOUNTER0_HI          0x0E55
+#define mmTCM_PERFCOUNTER1_HI          0x0E58
+#define mmTCM_PERFCOUNTER0_LOW         0x0E56
+#define mmTCM_PERFCOUNTER1_LOW         0x0E59
+#define mmTCF_PERFCOUNTER0_SELECT      0x0E5A
+#define mmTCF_PERFCOUNTER1_SELECT      0x0E5D
+#define mmTCF_PERFCOUNTER2_SELECT      0x0E60
+#define mmTCF_PERFCOUNTER3_SELECT      0x0E63
+#define mmTCF_PERFCOUNTER4_SELECT      0x0E66
+#define mmTCF_PERFCOUNTER5_SELECT      0x0E69
+#define mmTCF_PERFCOUNTER6_SELECT      0x0E6C
+#define mmTCF_PERFCOUNTER7_SELECT      0x0E6F
+#define mmTCF_PERFCOUNTER8_SELECT      0x0E72
+#define mmTCF_PERFCOUNTER9_SELECT      0x0E75
+#define mmTCF_PERFCOUNTER10_SELECT     0x0E78
+#define mmTCF_PERFCOUNTER11_SELECT     0x0E7B
+#define mmTCF_PERFCOUNTER0_HI          0x0E5B
+#define mmTCF_PERFCOUNTER1_HI          0x0E5E
+#define mmTCF_PERFCOUNTER2_HI          0x0E61
+#define mmTCF_PERFCOUNTER3_HI          0x0E64
+#define mmTCF_PERFCOUNTER4_HI          0x0E67
+#define mmTCF_PERFCOUNTER5_HI          0x0E6A
+#define mmTCF_PERFCOUNTER6_HI          0x0E6D
+#define mmTCF_PERFCOUNTER7_HI          0x0E70
+#define mmTCF_PERFCOUNTER8_HI          0x0E73
+#define mmTCF_PERFCOUNTER9_HI          0x0E76
+#define mmTCF_PERFCOUNTER10_HI         0x0E79
+#define mmTCF_PERFCOUNTER11_HI         0x0E7C
+#define mmTCF_PERFCOUNTER0_LOW         0x0E5C
+#define mmTCF_PERFCOUNTER1_LOW         0x0E5F
+#define mmTCF_PERFCOUNTER2_LOW         0x0E62
+#define mmTCF_PERFCOUNTER3_LOW         0x0E65
+#define mmTCF_PERFCOUNTER4_LOW         0x0E68
+#define mmTCF_PERFCOUNTER5_LOW         0x0E6B
+#define mmTCF_PERFCOUNTER6_LOW         0x0E6E
+#define mmTCF_PERFCOUNTER7_LOW         0x0E71
+#define mmTCF_PERFCOUNTER8_LOW         0x0E74
+#define mmTCF_PERFCOUNTER9_LOW         0x0E77
+#define mmTCF_PERFCOUNTER10_LOW        0x0E7A
+#define mmTCF_PERFCOUNTER11_LOW        0x0E7D
+#define mmTCF_DEBUG                    0x0EC0
+#define mmTCA_FIFO_DEBUG               0x0EC1
+#define mmTCA_PROBE_DEBUG              0x0EC2
+#define mmTCA_TPC_DEBUG                0x0EC3
+#define mmTCB_CORE_DEBUG               0x0EC4
+#define mmTCB_TAG0_DEBUG               0x0EC5
+#define mmTCB_TAG1_DEBUG               0x0EC6
+#define mmTCB_TAG2_DEBUG               0x0EC7
+#define mmTCB_TAG3_DEBUG               0x0EC8
+#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9
+#define mmTCB_FETCH_GEN_WALKER_DEBUG   0x0ECB
+#define mmTCB_FETCH_GEN_PIPE0_DEBUG    0x0ECC
+#define mmTCD_INPUT0_DEBUG             0x0ED0
+#define mmTCD_DEGAMMA_DEBUG            0x0ED4
+#define mmTCD_DXTMUX_SCTARB_DEBUG      0x0ED5
+#define mmTCD_DXTC_ARB_DEBUG           0x0ED6
+#define mmTCD_STALLS_DEBUG             0x0ED7
+#define mmTCO_STALLS_DEBUG             0x0EE0
+#define mmTCO_QUAD0_DEBUG0             0x0EE1
+#define mmTCO_QUAD0_DEBUG1             0x0EE2
+
+
+// Registers from TC block
+
+
+
+// Registers from SQ block
+
+#define mmSQ_GPR_MANAGEMENT            0x0D00
+#define mmSQ_FLOW_CONTROL              0x0D01
+#define mmSQ_INST_STORE_MANAGMENT      0x0D02
+#define mmSQ_RESOURCE_MANAGMENT        0x0D03
+#define mmSQ_EO_RT                     0x0D04
+#define mmSQ_DEBUG_MISC                0x0D05
+#define mmSQ_ACTIVITY_METER_CNTL       0x0D06
+#define mmSQ_ACTIVITY_METER_STATUS     0x0D07
+#define mmSQ_INPUT_ARB_PRIORITY        0x0D08
+#define mmSQ_THREAD_ARB_PRIORITY       0x0D09
+#define mmSQ_DEBUG_INPUT_FSM           0x0DAE
+#define mmSQ_DEBUG_CONST_MGR_FSM       0x0DAF
+#define mmSQ_DEBUG_TP_FSM              0x0DB0
+#define mmSQ_DEBUG_FSM_ALU_0           0x0DB1
+#define mmSQ_DEBUG_FSM_ALU_1           0x0DB2
+#define mmSQ_DEBUG_EXP_ALLOC           0x0DB3
+#define mmSQ_DEBUG_PTR_BUFF            0x0DB4
+#define mmSQ_DEBUG_GPR_VTX             0x0DB5
+#define mmSQ_DEBUG_GPR_PIX             0x0DB6
+#define mmSQ_DEBUG_TB_STATUS_SEL       0x0DB7
+#define mmSQ_DEBUG_VTX_TB_0            0x0DB8
+#define mmSQ_DEBUG_VTX_TB_1            0x0DB9
+#define mmSQ_DEBUG_VTX_TB_STATUS_REG   0x0DBA
+#define mmSQ_DEBUG_VTX_TB_STATE_MEM    0x0DBB
+#define mmSQ_DEBUG_PIX_TB_0            0x0DBC
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0
+#define mmSQ_DEBUG_PIX_TB_STATE_MEM    0x0DC1
+#define mmSQ_PERFCOUNTER0_SELECT       0x0DC8
+#define mmSQ_PERFCOUNTER1_SELECT       0x0DC9
+#define mmSQ_PERFCOUNTER2_SELECT       0x0DCA
+#define mmSQ_PERFCOUNTER3_SELECT       0x0DCB
+#define mmSQ_PERFCOUNTER0_LOW          0x0DCC
+#define mmSQ_PERFCOUNTER0_HI           0x0DCD
+#define mmSQ_PERFCOUNTER1_LOW          0x0DCE
+#define mmSQ_PERFCOUNTER1_HI           0x0DCF
+#define mmSQ_PERFCOUNTER2_LOW          0x0DD0
+#define mmSQ_PERFCOUNTER2_HI           0x0DD1
+#define mmSQ_PERFCOUNTER3_LOW          0x0DD2
+#define mmSQ_PERFCOUNTER3_HI           0x0DD3
+#define mmSX_PERFCOUNTER0_SELECT       0x0DD4
+#define mmSX_PERFCOUNTER0_LOW          0x0DD8
+#define mmSX_PERFCOUNTER0_HI           0x0DD9
+#define mmSQ_INSTRUCTION_ALU_0         0x5000
+#define mmSQ_INSTRUCTION_ALU_1         0x5001
+#define mmSQ_INSTRUCTION_ALU_2         0x5002
+#define mmSQ_INSTRUCTION_CF_EXEC_0     0x5080
+#define mmSQ_INSTRUCTION_CF_EXEC_1     0x5081
+#define mmSQ_INSTRUCTION_CF_EXEC_2     0x5082
+#define mmSQ_INSTRUCTION_CF_LOOP_0     0x5083
+#define mmSQ_INSTRUCTION_CF_LOOP_1     0x5084
+#define mmSQ_INSTRUCTION_CF_LOOP_2     0x5085
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088
+#define mmSQ_INSTRUCTION_CF_ALLOC_0    0x5089
+#define mmSQ_INSTRUCTION_CF_ALLOC_1    0x508A
+#define mmSQ_INSTRUCTION_CF_ALLOC_2    0x508B
+#define mmSQ_INSTRUCTION_TFETCH_0      0x5043
+#define mmSQ_INSTRUCTION_TFETCH_1      0x5044
+#define mmSQ_INSTRUCTION_TFETCH_2      0x5045
+#define mmSQ_INSTRUCTION_VFETCH_0      0x5040
+#define mmSQ_INSTRUCTION_VFETCH_1      0x5041
+#define mmSQ_INSTRUCTION_VFETCH_2      0x5042
+#define mmSQ_CONSTANT_0                0x4000
+#define mmSQ_CONSTANT_1                0x4001
+#define mmSQ_CONSTANT_2                0x4002
+#define mmSQ_CONSTANT_3                0x4003
+#define mmSQ_FETCH_0                   0x4800
+#define mmSQ_FETCH_1                   0x4801
+#define mmSQ_FETCH_2                   0x4802
+#define mmSQ_FETCH_3                   0x4803
+#define mmSQ_FETCH_4                   0x4804
+#define mmSQ_FETCH_5                   0x4805
+#define mmSQ_CONSTANT_VFETCH_0         0x4806
+#define mmSQ_CONSTANT_VFETCH_1         0x4808
+#define mmSQ_CONSTANT_T2               0x480C
+#define mmSQ_CONSTANT_T3               0x4812
+#define mmSQ_CF_BOOLEANS               0x4900
+#define mmSQ_CF_LOOP                   0x4908
+#define mmSQ_CONSTANT_RT_0             0x4940
+#define mmSQ_CONSTANT_RT_1             0x4941
+#define mmSQ_CONSTANT_RT_2             0x4942
+#define mmSQ_CONSTANT_RT_3             0x4943
+#define mmSQ_FETCH_RT_0                0x4D40
+#define mmSQ_FETCH_RT_1                0x4D41
+#define mmSQ_FETCH_RT_2                0x4D42
+#define mmSQ_FETCH_RT_3                0x4D43
+#define mmSQ_FETCH_RT_4                0x4D44
+#define mmSQ_FETCH_RT_5                0x4D45
+#define mmSQ_CF_RT_BOOLEANS            0x4E00
+#define mmSQ_CF_RT_LOOP                0x4E14
+#define mmSQ_VS_PROGRAM                0x21F7
+#define mmSQ_PS_PROGRAM                0x21F6
+#define mmSQ_CF_PROGRAM_SIZE           0x2315
+#define mmSQ_INTERPOLATOR_CNTL         0x2182
+#define mmSQ_PROGRAM_CNTL              0x2180
+#define mmSQ_WRAPPING_0                0x2183
+#define mmSQ_WRAPPING_1                0x2184
+#define mmSQ_VS_CONST                  0x2307
+#define mmSQ_PS_CONST                  0x2308
+#define mmSQ_CONTEXT_MISC              0x2181
+#define mmSQ_CF_RD_BASE                0x21F5
+#define mmSQ_DEBUG_MISC_0              0x2309
+#define mmSQ_DEBUG_MISC_1              0x230A
+
+
+// Registers from SX block
+
+
+
+// Registers from MH block
+
+#define mmMH_ARBITER_CONFIG            0x0A40
+#define mmMH_CLNT_AXI_ID_REUSE         0x0A41
+#define mmMH_INTERRUPT_MASK            0x0A42
+#define mmMH_INTERRUPT_STATUS          0x0A43
+#define mmMH_INTERRUPT_CLEAR           0x0A44
+#define mmMH_AXI_ERROR                 0x0A45
+#define mmMH_PERFCOUNTER0_SELECT       0x0A46
+#define mmMH_PERFCOUNTER1_SELECT       0x0A4A
+#define mmMH_PERFCOUNTER0_CONFIG       0x0A47
+#define mmMH_PERFCOUNTER1_CONFIG       0x0A4B
+#define mmMH_PERFCOUNTER0_LOW          0x0A48
+#define mmMH_PERFCOUNTER1_LOW          0x0A4C
+#define mmMH_PERFCOUNTER0_HI           0x0A49
+#define mmMH_PERFCOUNTER1_HI           0x0A4D
+#define mmMH_DEBUG_CTRL                0x0A4E
+#define mmMH_DEBUG_DATA                0x0A4F
+#define mmMH_MMU_CONFIG                0x0040
+#define mmMH_MMU_VA_RANGE              0x0041
+#define mmMH_MMU_PT_BASE               0x0042
+#define mmMH_MMU_PAGE_FAULT            0x0043
+#define mmMH_MMU_TRAN_ERROR            0x0044
+#define mmMH_MMU_INVALIDATE            0x0045
+#define mmMH_MMU_MPU_BASE              0x0046
+#define mmMH_MMU_MPU_END               0x0047
+
+
+// Registers from RBBM block
+
+#define mmWAIT_UNTIL                   0x05C8
+#define mmRBBM_ISYNC_CNTL              0x05C9
+#define mmRBBM_STATUS                  0x05D0
+#define mmRBBM_DSPLY                   0x0391
+#define mmRBBM_RENDER_LATEST           0x0392
+#define mmRBBM_RTL_RELEASE             0x0000
+#define mmRBBM_PATCH_RELEASE           0x0001
+#define mmRBBM_AUXILIARY_CONFIG        0x0002
+#define mmRBBM_PERIPHID0               0x03F8
+#define mmRBBM_PERIPHID1               0x03F9
+#define mmRBBM_PERIPHID2               0x03FA
+#define mmRBBM_PERIPHID3               0x03FB
+#define mmRBBM_CNTL                    0x003B
+#define mmRBBM_SKEW_CNTL               0x003D
+#define mmRBBM_SOFT_RESET              0x003C
+#define mmRBBM_PM_OVERRIDE1            0x039C
+#define mmRBBM_PM_OVERRIDE2            0x039D
+#define mmGC_SYS_IDLE                  0x039E
+#define mmNQWAIT_UNTIL                 0x0394
+#define mmRBBM_DEBUG                   0x039B
+#define mmRBBM_READ_ERROR              0x03B3
+#define mmRBBM_WAIT_IDLE_CLOCKS        0x03B2
+#define mmRBBM_INT_CNTL                0x03B4
+#define mmRBBM_INT_STATUS              0x03B5
+#define mmRBBM_INT_ACK                 0x03B6
+#define mmMASTER_INT_SIGNAL            0x03B7
+#define mmRBBM_PERFCOUNTER1_SELECT     0x0395
+#define mmRBBM_PERFCOUNTER1_LO         0x0397
+#define mmRBBM_PERFCOUNTER1_HI         0x0398
+
+
+// Registers from CP block
+
+#define mmCP_RB_BASE                   0x01C0
+#define mmCP_RB_CNTL                   0x01C1
+#define mmCP_RB_RPTR_ADDR              0x01C3
+#define mmCP_RB_RPTR                   0x01C4
+#define mmCP_RB_RPTR_WR                0x01C7
+#define mmCP_RB_WPTR                   0x01C5
+#define mmCP_RB_WPTR_DELAY             0x01C6
+#define mmCP_RB_WPTR_BASE              0x01C8
+#define mmCP_IB1_BASE                  0x01CC
+#define mmCP_IB1_BUFSZ                 0x01CD
+#define mmCP_IB2_BASE                  0x01CE
+#define mmCP_IB2_BUFSZ                 0x01CF
+#define mmCP_ST_BASE                   0x044D
+#define mmCP_ST_BUFSZ                  0x044E
+#define mmCP_QUEUE_THRESHOLDS          0x01D5
+#define mmCP_MEQ_THRESHOLDS            0x01D6
+#define mmCP_CSQ_AVAIL                 0x01D7
+#define mmCP_STQ_AVAIL                 0x01D8
+#define mmCP_MEQ_AVAIL                 0x01D9
+#define mmCP_CSQ_RB_STAT               0x01FD
+#define mmCP_CSQ_IB1_STAT              0x01FE
+#define mmCP_CSQ_IB2_STAT              0x01FF
+#define mmCP_NON_PREFETCH_CNTRS        0x0440
+#define mmCP_STQ_ST_STAT               0x0443
+#define mmCP_MEQ_STAT                  0x044F
+#define mmCP_MIU_TAG_STAT              0x0452
+#define mmCP_CMD_INDEX                 0x01DA
+#define mmCP_CMD_DATA                  0x01DB
+#define mmCP_ME_CNTL                   0x01F6
+#define mmCP_ME_STATUS                 0x01F7
+#define mmCP_ME_RAM_WADDR              0x01F8
+#define mmCP_ME_RAM_RADDR              0x01F9
+#define mmCP_ME_RAM_DATA               0x01FA
+#define mmCP_ME_RDADDR                 0x01EA
+#define mmCP_DEBUG                     0x01FC
+#define mmSCRATCH_REG0                 0x0578
+#define mmGUI_SCRATCH_REG0             0x0578
+#define mmSCRATCH_REG1                 0x0579
+#define mmGUI_SCRATCH_REG1             0x0579
+#define mmSCRATCH_REG2                 0x057A
+#define mmGUI_SCRATCH_REG2             0x057A
+#define mmSCRATCH_REG3                 0x057B
+#define mmGUI_SCRATCH_REG3             0x057B
+#define mmSCRATCH_REG4                 0x057C
+#define mmGUI_SCRATCH_REG4             0x057C
+#define mmSCRATCH_REG5                 0x057D
+#define mmGUI_SCRATCH_REG5             0x057D
+#define mmSCRATCH_REG6                 0x057E
+#define mmGUI_SCRATCH_REG6             0x057E
+#define mmSCRATCH_REG7                 0x057F
+#define mmGUI_SCRATCH_REG7             0x057F
+#define mmSCRATCH_UMSK                 0x01DC
+#define mmSCRATCH_ADDR                 0x01DD
+#define mmCP_ME_VS_EVENT_SRC           0x0600
+#define mmCP_ME_VS_EVENT_ADDR          0x0601
+#define mmCP_ME_VS_EVENT_DATA          0x0602
+#define mmCP_ME_VS_EVENT_ADDR_SWM      0x0603
+#define mmCP_ME_VS_EVENT_DATA_SWM      0x0604
+#define mmCP_ME_PS_EVENT_SRC           0x0605
+#define mmCP_ME_PS_EVENT_ADDR          0x0606
+#define mmCP_ME_PS_EVENT_DATA          0x0607
+#define mmCP_ME_PS_EVENT_ADDR_SWM      0x0608
+#define mmCP_ME_PS_EVENT_DATA_SWM      0x0609
+#define mmCP_ME_CF_EVENT_SRC           0x060A
+#define mmCP_ME_CF_EVENT_ADDR          0x060B
+#define mmCP_ME_CF_EVENT_DATA          0x060C
+#define mmCP_ME_NRT_ADDR               0x060D
+#define mmCP_ME_NRT_DATA               0x060E
+#define mmCP_ME_VS_FETCH_DONE_SRC      0x0612
+#define mmCP_ME_VS_FETCH_DONE_ADDR     0x0613
+#define mmCP_ME_VS_FETCH_DONE_DATA     0x0614
+#define mmCP_INT_CNTL                  0x01F2
+#define mmCP_INT_STATUS                0x01F3
+#define mmCP_INT_ACK                   0x01F4
+#define mmCP_PFP_UCODE_ADDR            0x045F
+#define mmCP_PFP_UCODE_DATA            0x0460
+#define mmCP_PERFMON_CNTL              0x01F5
+#define mmCP_PERFCOUNTER_SELECT        0x01E6
+#define mmCP_PERFCOUNTER_LO            0x01E7
+#define mmCP_PERFCOUNTER_HI            0x01E8
+#define mmCP_BIN_MASK_LO               0x0454
+#define mmCP_BIN_MASK_HI               0x0455
+#define mmCP_BIN_SELECT_LO             0x0456
+#define mmCP_BIN_SELECT_HI             0x0457
+#define mmCP_NV_FLAGS_0                0x01EE
+#define mmCP_NV_FLAGS_1                0x01EF
+#define mmCP_NV_FLAGS_2                0x01F0
+#define mmCP_NV_FLAGS_3                0x01F1
+#define mmCP_STATE_DEBUG_INDEX         0x01EC
+#define mmCP_STATE_DEBUG_DATA          0x01ED
+#define mmCP_PROG_COUNTER              0x044B
+#define mmCP_STAT                      0x047F
+#define mmBIOS_0_SCRATCH               0x0004
+#define mmBIOS_1_SCRATCH               0x0005
+#define mmBIOS_2_SCRATCH               0x0006
+#define mmBIOS_3_SCRATCH               0x0007
+#define mmBIOS_4_SCRATCH               0x0008
+#define mmBIOS_5_SCRATCH               0x0009
+#define mmBIOS_6_SCRATCH               0x000A
+#define mmBIOS_7_SCRATCH               0x000B
+#define mmBIOS_8_SCRATCH               0x0580
+#define mmBIOS_9_SCRATCH               0x0581
+#define mmBIOS_10_SCRATCH              0x0582
+#define mmBIOS_11_SCRATCH              0x0583
+#define mmBIOS_12_SCRATCH              0x0584
+#define mmBIOS_13_SCRATCH              0x0585
+#define mmBIOS_14_SCRATCH              0x0586
+#define mmBIOS_15_SCRATCH              0x0587
+#define mmCOHER_SIZE_PM4               0x0A29
+#define mmCOHER_BASE_PM4               0x0A2A
+#define mmCOHER_STATUS_PM4             0x0A2B
+#define mmCOHER_SIZE_HOST              0x0A2F
+#define mmCOHER_BASE_HOST              0x0A30
+#define mmCOHER_STATUS_HOST            0x0A31
+#define mmCOHER_DEST_BASE_0            0x2006
+#define mmCOHER_DEST_BASE_1            0x2007
+#define mmCOHER_DEST_BASE_2            0x2008
+#define mmCOHER_DEST_BASE_3            0x2009
+#define mmCOHER_DEST_BASE_4            0x200A
+#define mmCOHER_DEST_BASE_5            0x200B
+#define mmCOHER_DEST_BASE_6            0x200C
+#define mmCOHER_DEST_BASE_7            0x200D
+
+
+// Registers from SC block
+
+
+
+// Registers from BC block
+
+#define mmRB_SURFACE_INFO              0x2000
+#define mmRB_COLOR_INFO                0x2001
+#define mmRB_DEPTH_INFO                0x2002
+#define mmRB_STENCILREFMASK            0x210D
+#define mmRB_ALPHA_REF                 0x210E
+#define mmRB_COLOR_MASK                0x2104
+#define mmRB_BLEND_RED                 0x2105
+#define mmRB_BLEND_GREEN               0x2106
+#define mmRB_BLEND_BLUE                0x2107
+#define mmRB_BLEND_ALPHA               0x2108
+#define mmRB_FOG_COLOR                 0x2109
+#define mmRB_STENCILREFMASK_BF         0x210C
+#define mmRB_DEPTHCONTROL              0x2200
+#define mmRB_BLENDCONTROL              0x2201
+#define mmRB_COLORCONTROL              0x2202
+#define mmRB_MODECONTROL               0x2208
+#define mmRB_COLOR_DEST_MASK           0x2326
+#define mmRB_COPY_CONTROL              0x2318
+#define mmRB_COPY_DEST_BASE            0x2319
+#define mmRB_COPY_DEST_PITCH           0x231A
+#define mmRB_COPY_DEST_INFO            0x231B
+#define mmRB_COPY_DEST_PIXEL_OFFSET    0x231C
+#define mmRB_DEPTH_CLEAR               0x231D
+#define mmRB_SAMPLE_COUNT_CTL          0x2324
+#define mmRB_SAMPLE_COUNT_ADDR         0x2325
+#define mmRB_BC_CONTROL                0x0F01
+#define mmRB_EDRAM_INFO                0x0F02
+#define mmRB_CRC_RD_PORT               0x0F0C
+#define mmRB_CRC_CONTROL               0x0F0D
+#define mmRB_CRC_MASK                  0x0F0E
+#define mmRB_PERFCOUNTER0_SELECT       0x0F04
+#define mmRB_PERFCOUNTER0_LOW          0x0F08
+#define mmRB_PERFCOUNTER0_HI           0x0F09
+#define mmRB_TOTAL_SAMPLES             0x0F0F
+#define mmRB_ZPASS_SAMPLES             0x0F10
+#define mmRB_ZFAIL_SAMPLES             0x0F11
+#define mmRB_SFAIL_SAMPLES             0x0F12
+#define mmRB_DEBUG_0                   0x0F26
+#define mmRB_DEBUG_1                   0x0F27
+#define mmRB_DEBUG_2                   0x0F28
+#define mmRB_DEBUG_3                   0x0F29
+#define mmRB_DEBUG_4                   0x0F2A
+#define mmRB_FLAG_CONTROL              0x0F2B
+#define mmBC_DUMMY_CRAYRB_ENUMS        0x0F15
+#define mmBC_DUMMY_CRAYRB_MOREENUMS    0x0F16
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h
new file mode 100644
index 000000000000..7e293b371bcd
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h
@@ -0,0 +1,221 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_RANDOM_HEADER)
+#define _yamato_RANDOM_HEADER
+
+/*************************************************************
+ * THIS FILE IS AUTOMATICALLY CREATED.  DO NOT EDIT THIS FILE.
+ *************************************************************/
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SU_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SC_PERFCNT_SELECT>;
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRIM_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SOURCE_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_INDEX_SIZE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SMALL_INDEX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRE_FETCH_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_GRP_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_EVENT_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DMA_SWAP_MODE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCR_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TP_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCM_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCF_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SQ_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SX_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Abs_modifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Exporting>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ScalarOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SwizzleType>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<InputModifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredicateSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect1>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VectorOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect0>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Ressource_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Instruction_serial>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VC_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressing>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CFOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Allocation_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexInstOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressmode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexCoordDenorm>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SrcSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DstSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MipFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<AnisoFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ArbitraryFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SampleLocation>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VertexMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Sample_Cntl>;
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MhPerfEncode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MmuClntBeh>;
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RBBM_PERFCOUNT1_SEL>;
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CP_PERFCOUNT_SEL>;
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareFrag>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareRef>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<StencilOp>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<BlendOpX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CombFuncX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherModeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherTypeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceEndian>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramSizeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RB_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceSwap>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumber>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceTiling>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumberX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArrayX>;
+
+#endif /*_yamato_RANDOM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h
new file mode 100644
index 000000000000..b021d446a229
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h
@@ -0,0 +1,13962 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_REG_HEADER)
+#define _yamato_REG_HEADER
+
+    union PA_CL_VPORT_XSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_XSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_XSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_XOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_XOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_XOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_YSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_YSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_YOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_YOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_ZSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_ZSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_ZOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_ZOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VTE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int                                 : 2;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                                 : 2;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CLIP_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+        unsigned int                                 : 27;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 27;
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 28;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_VTX_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PIX_CENTER : 1;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      PIX_CENTER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          HEIGHT : 16;
+        unsigned int                           WIDTH : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           WIDTH : 16;
+        unsigned int                          HEIGHT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_MINMAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_SIZE : 16;
+        unsigned int                        MAX_SIZE : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MAX_SIZE : 16;
+        unsigned int                        MIN_SIZE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           WIDTH : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                           WIDTH : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_SC_MODE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CULL_FRONT : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                            FACE : 1;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int                            FACE : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                      CULL_FRONT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 WINDOW_X_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_X_OFFSET : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+        unsigned int                                 : 10;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 10;
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         AA_MASK : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                         AA_MASK : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    LINE_PATTERN : 16;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                                 : 4;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                    LINE_PATTERN : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BRES_CNTL : 8;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int                       BRES_CNTL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 1;
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VIZ_QUERY_ENA : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                                 : 1;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                   VIZ_QUERY_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STATUS_BITS : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     STATUS_BITS : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CURRENT_PTR : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int                     CURRENT_PTR : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         CL_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CL_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SU_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SU_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SC_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SU_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SU_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           clip_ga_bc_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int                     ALWAYS_ZERO : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 12;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_ga_bc_fifo_write : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int                     ALWAYS_ZERO : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 8;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO1 : 21;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO1 : 21;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO0 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 6;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO3 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO0 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 24;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            clprim_in_back_event : 1;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int     clip_priority_seq_indx_load : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int     clip_priority_seq_indx_load : 2;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int            clprim_in_back_event : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int         clprim_in_back_event_id : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         clprim_in_back_event_id : 6;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+        unsigned int                     ALWAYS_ZERO : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 28;
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clip_priority_available_vte_out_clip : 2;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clip_priority_available_vte_out_clip : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               sm0_clip_vert_cnt : 4;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int               sm0_current_state : 7;
+        unsigned int                    ALWAYS_ZERO0 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 5;
+        unsigned int               sm0_current_state : 7;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int               sm0_clip_vert_cnt : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   nan_kill_flag : 4;
+        unsigned int                position_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int           sx_pending_rd_aux_sel : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           sx_pending_rd_aux_sel : 1;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                position_address : 3;
+        unsigned int                   nan_kill_flag : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                param_cache_base : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                param_cache_base : 7;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         sx_sent : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                          sx_aux : 1;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                req_active_verts : 7;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int        sx_pending_fifo_contents : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int        sx_pending_fifo_contents : 3;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int                req_active_verts : 7;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                          sx_aux : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                         sx_sent : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    vertex_fifo_entriesavailable : 4;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int                   current_state : 2;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                   current_state : 2;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int    vertex_fifo_entriesavailable : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   su_cntl_state : 5;
+        unsigned int                     pmode_state : 6;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                       geom_busy : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       geom_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     pmode_state : 6;
+        unsigned int                   su_cntl_state : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort0_gated_17_4 : 14;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int              y_sort0_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort1_gated_17_4 : 14;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int              y_sort1_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort2_gated_17_4 : 14;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int              y_sort2_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort0_gated : 11;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                      type_gated : 3;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                       eop_gated : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                       eop_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                      type_gated : 3;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int           attr_indx_sort0_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort2_gated : 11;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int                  event_id_gated : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                  event_id_gated : 5;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int           attr_indx_sort2_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SC_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SC_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    pa_freeze_b1 : 1;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                                 : 17;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 17;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                    pa_freeze_b1 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        em_state : 3;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                                 : 21;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 21;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                        em_state : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rc_rtr_dly : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                                 : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int                        event_s1 : 1;
+        unsigned int                                 : 8;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 8;
+        unsigned int                        event_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                                 : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                      rc_rtr_dly : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       x_curr_s1 : 11;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                                 : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 9;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                       x_curr_s1 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        y_end_s1 : 14;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        x_end_s1 : 14;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      z_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                           state : 3;
+        unsigned int                   state_delayed : 3;
+        unsigned int                      data_valid : 1;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                      data_valid : 1;
+        unsigned int                   state_delayed : 3;
+        unsigned int                           state : 3;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                      z_ff_empty : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      event_flag : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                            fpos : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                           state : 2;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                                 : 6;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 6;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                           state : 2;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                            fpos : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                      event_flag : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     sample_last : 1;
+        unsigned int                     sample_mask : 4;
+        unsigned int                        sample_y : 2;
+        unsigned int                        sample_x : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int                            fpos : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                                 : 3;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 3;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                            fpos : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                        sample_x : 2;
+        unsigned int                        sample_y : 2;
+        unsigned int                     sample_mask : 4;
+        unsigned int                     sample_last : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rb_sc_send : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                      mask_state : 2;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_ready : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int                      mask_ready : 1;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_state : 2;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                      rb_sc_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            combined_sample_mask : 16;
+        unsigned int                                 : 15;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 15;
+        unsigned int            combined_sample_mask : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            ez_sample_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_event : 1;
+        unsigned int                      next_state : 3;
+        unsigned int                           state : 3;
+        unsigned int                           stall : 1;
+        unsigned int                                 : 16;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 16;
+        unsigned int                           stall : 1;
+        unsigned int                           state : 3;
+        unsigned int                      next_state : 3;
+        unsigned int               packer_send_event : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int            ez_sample_data_ready : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SQ_iterator_free_buff : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                                 : 7;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 7;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int           SQ_iterator_free_buff : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GFX_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DRAW_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       PRIM_TYPE : 6;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int                                 : 3;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int                     NUM_INDICES : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     NUM_INDICES : 16;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                                 : 3;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int                       PRIM_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_EVENT_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EVENT_TYPE : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      EVENT_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                       SWAP_MODE : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SWAP_MODE : 2;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MIN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_IMMED_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MAX_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MAX_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MAX_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MIN_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MIN_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_INDX_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INDX_OFFSET : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                     INDX_OFFSET : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VERTEX_REUSE_BLOCK_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_OUT_DEALLOC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEALLOC_DIST : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    DEALLOC_DIST : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MULTI_PRIM_IB_RESET_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESET_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      RESET_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            MISC : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                            MISC : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VTX_VECT_EJECT_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PRIM_COUNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                      PRIM_COUNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_LAST_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VGT_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                  VGT_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     te_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     te_grp_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                out_te_data_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_te_data_read : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      vgt_clk_en : 1;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                      vgt_clk_en : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int                      read_block : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int                   selected_data : 8;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                           gap_q : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int                     grp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     grp_trigger : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int                           gap_q : 1;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                   selected_data : 8;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int                      read_block : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     save_read_q : 1;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                     save_read_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            prim_side_indx_valid : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                       hold_prim : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int                       hold_prim : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int            prim_side_indx_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       null_terminate_vtx_vector : 1;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int                    new_packet_q : 1;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int                                 : 4;
+        unsigned int                     out_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 4;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int                    new_packet_q : 1;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int       null_terminate_vtx_vector : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   L2_INVALIDATE : 1;
+        unsigned int                                 : 17;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 11;
+        unsigned int                         TC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 11;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 17;
+        unsigned int                   L2_INVALIDATE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int                           SPARE : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 23;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP_TC_CLKGATE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TP_BUSY_EXTEND : 3;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                  TP_BUSY_EXTEND : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TPC_INPUT_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int                        TPC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int                  TPC_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        LOD_CNTL : 2;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                                 : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                    SQ_TP_WAKEUP : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SQ_TP_WAKEUP : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                                 : 3;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 1;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                        LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          UNUSED : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                          UNUSED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 BLEND_PRECISION : 1;
+        unsigned int                           SPARE : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 31;
+        unsigned int                 BLEND_PRECISION : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TP_INPUT_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                         TP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TP_BUSY : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                   TP_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      Q_LOD_CNTL : 2;
+        unsigned int                                 : 1;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int                                 : 1;
+        unsigned int                      Q_LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TT_MODE : 1;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                           SPARE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 30;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                         TT_MODE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 6;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TPC_full : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                         tca_rts : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                         tca_rts : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                        TPC_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                                 : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_FIFO_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        tp0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tpc_full : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                        tpc_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tp0_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_PROBE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               ProbeFilter_stall : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int               ProbeFilter_stall : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_TPC_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                                 : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 18;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_CORE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       access512 : 1;
+        unsigned int                           tiled : 1;
+        unsigned int                                 : 2;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 1;
+        unsigned int                          format : 6;
+        unsigned int                                 : 2;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 3;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 3;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 2;
+        unsigned int                          format : 6;
+        unsigned int                                 : 1;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 2;
+        unsigned int                           tiled : 1;
+        unsigned int                       access512 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG1_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG2_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG3_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       left_done : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int                     update_left : 1;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int                    valid_left_q : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    valid_left_q : 1;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int                     update_left : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int                       left_done : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_WALKER_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                                 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                            busy : 1;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                            busy : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                                 : 3;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_PIPE0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     tc0_arb_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                            busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         valid_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                         valid_q : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                            busy : 1;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                     tc0_arb_rts : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_INPUT0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                                 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DEGAMMA_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTMUX_SCTARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 9;
+        unsigned int                          pstate : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int                                 : 3;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 6;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                                 : 6;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 3;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int                                 : 3;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                                 : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTC_ARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                        n0_stall : 1;
+        unsigned int                          pstate : 1;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int                 n0_dxt2_4_types : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 n0_dxt2_4_types : 1;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                        n0_stall : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 10;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_incoming_rtr : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                not_incoming_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int                                 : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             rl_sg_sector_format : 8;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                                 : 2;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int                            busy : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            busy : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 2;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int             rl_sg_sector_format : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       fifo_busy : 1;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                    write_enable : 1;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                                 : 2;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int                                 : 2;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                    write_enable : 1;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                       fifo_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_GPR_MANAGEMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     REG_DYNAMIC : 1;
+        unsigned int                                 : 3;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 3;
+        unsigned int                     REG_DYNAMIC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FLOW_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+        unsigned int                                 : 2;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 2;
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INST_STORE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   INST_BASE_PIX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_PIX : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_RESOURCE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_EO_RT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 EO_CONSTANTS_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                 EO_CONSTANTS_RT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  DB_ALUCST_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                        RESERVED : 2;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                                 : 1;
+        unsigned int                  DB_ALUCST_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TIMEBASE : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                           SPARE : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                        TIMEBASE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERCENT_BUSY : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    PERCENT_BUSY : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INPUT_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_THREAD_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                        RESERVED : 2;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_INPUT_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       VC_VSR_LD : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           PC_AS : 3;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                           PC_AS : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_VSR_LD : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_CONST_MGR_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TP_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           EX_TP : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           CF_TP : 4;
+        unsigned int                           IF_TP : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           IF_TP : 3;
+        unsigned int                           CF_TP : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           EX_TP : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_EXP_ALLOC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   POS_BUF_AVAIL : 4;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                   POS_BUF_AVAIL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PTR_BUFF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   END_OF_BUFFER : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                   END_OF_BUFFER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_VTX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VTX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_PIX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TB_STATUS_SEL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int                                 : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_PTR : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                     VS_DONE_PTR : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATUS_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VS_STATUS_REG : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VS_STATUS_REG : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_HEAD_PTR : 6;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int                            BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BUSY : 1;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                    PIX_HEAD_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VECTOR_RESULT : 6;
+        unsigned int                   CST_0_ABS_MOD : 1;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int                   SST_0_ABS_MOD : 1;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                   SCALAR_OPCODE : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SCALAR_OPCODE : 6;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                   SST_0_ABS_MOD : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                   CST_0_ABS_MOD : 1;
+        unsigned int                   VECTOR_RESULT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                 CONST_0_REL_ABS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CONST_0_REL_ABS : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SRC_C_REG_PTR : 6;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_A_SEL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_A_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   SRC_C_REG_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_1 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 11;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 11;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 6;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                      RESERVED_0 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                        RESERVED : 22;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                        RESERVED : 22;
+        unsigned int                         LOOP_ID : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      RESERVED_1 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 17;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 1;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_2 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_2 : 2;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                      RESERVED_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 17;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                        RESERVED : 17;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 4;
+        unsigned int                        RESERVED : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 28;
+        unsigned int                            SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 8;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                            SIZE : 4;
+        unsigned int                      RESERVED_1 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 12;
+        unsigned int                            SIZE : 4;
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                      RESERVED_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 24;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                        RESERVED : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_Z : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_SEL_Z : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               USE_REG_GRADIENTS : 1;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int               USE_REG_GRADIENTS : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                         SRC_SEL : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SRC_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          STRIDE : 8;
+        unsigned int                                 : 8;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 7;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                                 : 7;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 8;
+        unsigned int                          STRIDE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TYPE : 1;
+        unsigned int                           STATE : 1;
+        unsigned int                    BASE_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BASE_ADDRESS : 30;
+        unsigned int                           STATE : 1;
+        unsigned int                            TYPE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ENDIAN_SWAP : 2;
+        unsigned int                   LIMIT_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   LIMIT_ADDRESS : 30;
+        unsigned int                     ENDIAN_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_PROGRAM_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      VS_CF_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INTERPOLATOR_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARAM_SHADE : 16;
+        unsigned int                SAMPLING_PATTERN : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                SAMPLING_PATTERN : 16;
+        unsigned int                     PARAM_SHADE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PROGRAM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                   GEN_INDEX_VTX : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   GEN_INDEX_VTX : 1;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      VS_NUM_REG : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_0 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_7 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PARAM_WRAP_7 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_0 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_8 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_15 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PARAM_WRAP_15 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                    PARAM_WRAP_8 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONTEXT_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                                 : 4;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RD_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RD_BASE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                         RD_BASE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DB_PROB_ON : 1;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 5;
+        unsigned int                   DB_PROB_COUNT : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DB_PROB_COUNT : 8;
+        unsigned int                                 : 5;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      DB_PROB_ON : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DB_ON_PIX : 1;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                                 : 6;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                                 : 6;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                       DB_ON_PIX : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_ARBITER_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_CLNT_AXI_ID_REUSE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          CPw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          CPw_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     AXI_READ_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                     AXI_READ_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           INDEX : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                           INDEX : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                         MH_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                         CP_BE_q : 8;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                         RB_BE_q : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         RB_BE_q : 8;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                         CP_BE_q : 8;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CP_MH_send : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                   CP_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CP_MH_ad_31_5 : 27;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                      CP_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG06 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 CP_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CP_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG07 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CP_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                CP_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG08 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 3;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                 TC_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 TC_MH_addr_31_5 : 27;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_info : 25;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_info : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_TC_mcinfo : 25;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                    MH_TC_mcinfo : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ROQ_INFO : 25;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_INFO : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                 RB_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_addr_31_5 : 27;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 RB_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                RB_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                RB_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG19 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                    CTRL_ARC_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CTRL_ARC_PAD : 28;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                           REG_A : 14;
+        unsigned int                          REG_RE : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                          REG_RE : 1;
+        unsigned int                           REG_A : 14;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          REG_WD : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REG_WD : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG22 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             CIB_MH_axi_halt_req : 1;
+        unsigned int             MH_CIB_axi_halt_ack : 1;
+        unsigned int                    MH_RBBM_busy : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       BRC_VALID : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BRC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int                    MH_RBBM_busy : 1;
+        unsigned int             MH_CIB_axi_halt_ack : 1;
+        unsigned int             CIB_MH_axi_halt_req : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG23 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  EFF2_FP_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                  EFF2_FP_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG24 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG25 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                        CLNT_REQ : 4;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                        CLNT_REQ : 4;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG26 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG27 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG28 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG29 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG30 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG31 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                      ROQ_ADDR_0 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_0 : 27;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG32 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                      ROQ_ADDR_1 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_1 : 27;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG33 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                      ROQ_ADDR_2 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_2 : 27;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG34 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                      ROQ_ADDR_3 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_3 : 27;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG35 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                      ROQ_ADDR_4 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_4 : 27;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG36 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                      ROQ_ADDR_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_5 : 27;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG37 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                      ROQ_ADDR_6 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_6 : 27;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG38 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                      ROQ_ADDR_7 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_7 : 27;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG39 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ARB_WE : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                          ARB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG40 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ARB_WE : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                       ARB_VAD_q : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ARB_VAD_q : 28;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                          ARB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG41 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          MMU_WE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         MMU_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MMU_PAD : 28;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                          MMU_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG42 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          WDB_WE : 1;
+        unsigned int                    WDB_RTR_SKID : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                   WDB_WDC_WSTRB : 8;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   WDB_WDC_WSTRB : 8;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                    WDB_RTR_SKID : 1;
+        unsigned int                          WDB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG43 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                ARB_WDATA_q_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                ARB_WDATA_q_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG44 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               ARB_WDATA_q_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               ARB_WDATA_q_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG45 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG46 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG47 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG48 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG49 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG50 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 RF_MMU_CONFIG_q : 24;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                         MMU_RTR : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                 RF_MMU_CONFIG_q : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG51 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    stage1_valid : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                    stage1_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG52 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                    stage2_valid : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                     TAG_valid_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TAG_valid_q : 16;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                    stage2_valid : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG53 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG0_VA : 13;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                         TAG0_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG54 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG2_VA : 13;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                         TAG2_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG55 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG4_VA : 13;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                         TAG4_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG56 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG6_VA : 13;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                         TAG6_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG57 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG8_VA : 13;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                         TAG8_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG58 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG10_VA : 13;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                        TAG10_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG59 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG12_VA : 13;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                        TAG12_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG60 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG14_VA : 13;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                        TAG14_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG61 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG62 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG63 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      MMU_ENABLE : 1;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                      MMU_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_VA_RANGE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                NUM_64KB_REGIONS : 12;
+        unsigned int                         VA_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         VA_BASE : 20;
+        unsigned int                NUM_64KB_REGIONS : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PT_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         PT_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         PT_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PAGE_FAULT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PAGE_FAULT : 1;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int                          REQ_VA : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REQ_VA : 20;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                      PAGE_FAULT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_TRAN_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                      TRAN_ERROR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      TRAN_ERROR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_INVALIDATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  INVALIDATE_ALL : 1;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                  INVALIDATE_ALL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                        MPU_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MPU_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_END {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         MPU_END : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MPU_END : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union WAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int                                 : 2;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 2;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_ISYNC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CMDFIFO_AVAIL : 5;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                      GUI_ACTIVE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      GUI_ACTIVE : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                                 : 2;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                   CMDFIFO_AVAIL : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DSPLY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              DISPLAY_ID0_ACTIVE : 1;
+        unsigned int              DISPLAY_ID1_ACTIVE : 1;
+        unsigned int              DISPLAY_ID2_ACTIVE : 1;
+        unsigned int                    VSYNC_ACTIVE : 1;
+        unsigned int                 USE_DISPLAY_ID0 : 1;
+        unsigned int                 USE_DISPLAY_ID1 : 1;
+        unsigned int                 USE_DISPLAY_ID2 : 1;
+        unsigned int                         SW_CNTL : 1;
+        unsigned int                        NUM_BUFS : 2;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                        NUM_BUFS : 2;
+        unsigned int                         SW_CNTL : 1;
+        unsigned int                 USE_DISPLAY_ID2 : 1;
+        unsigned int                 USE_DISPLAY_ID1 : 1;
+        unsigned int                 USE_DISPLAY_ID0 : 1;
+        unsigned int                    VSYNC_ACTIVE : 1;
+        unsigned int              DISPLAY_ID2_ACTIVE : 1;
+        unsigned int              DISPLAY_ID1_ACTIVE : 1;
+        unsigned int              DISPLAY_ID0_ACTIVE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RENDER_LATEST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BUFFER_ID : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                       BUFFER_ID : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RTL_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CHANGELIST : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      CHANGELIST : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PATCH_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PATCH_REVISION : 16;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                     CUSTOMER_ID : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     CUSTOMER_ID : 8;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                  PATCH_REVISION : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_AUXILIARY_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER0 : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     PARTNUMBER0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER1 : 4;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                     PARTNUMBER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DESIGNER1 : 4;
+        unsigned int                        REVISION : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        REVISION : 4;
+        unsigned int                       DESIGNER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int                                 : 1;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 1;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    READ_TIMEOUT : 8;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                    READ_TIMEOUT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SKEW_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SOFT_RESET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SOFT_RESET_CP : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                                 : 5;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 2;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                                 : 2;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 5;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_CP : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GC_SYS_IDLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+        unsigned int                                 : 15;
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+        unsigned int                                 : 15;
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union NQWAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WAIT_GUI_IDLE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                   WAIT_GUI_IDLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int                                 : 3;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 4;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int                                 : 6;
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+        unsigned int                                 : 6;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int                                 : 4;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 3;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_READ_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 13;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                      READ_ERROR : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      READ_ERROR : 1;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                                 : 13;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_WAIT_IDLE_CLOCKS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_MASK : 1;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                  RDERR_INT_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_STAT : 1;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                  RDERR_INT_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   RDERR_INT_ACK : 1;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                   RDERR_INT_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MASTER_INT_SIGNAL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 24;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                   RBBM_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   RBBM_INT_STAT : 1;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                                 : 24;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNT1_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                 PERF_COUNT1_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PERF_COUNT1_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERF_COUNT1_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                         RB_BASE : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         RB_BASE : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RB_BUFSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 6;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 3;
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+        unsigned int                                 : 3;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 6;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BUFSZ : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_RPTR_SWAP : 2;
+        unsigned int                    RB_RPTR_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_RPTR_ADDR : 30;
+        unsigned int                    RB_RPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_RPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_RPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_WR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RB_RPTR_WR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                      RB_RPTR_WR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_WPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_WPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_DELAY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PRE_WRITE_TIMER : 28;
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+        unsigned int                 PRE_WRITE_TIMER : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_WPTR_SWAP : 2;
+        unsigned int                    RB_WPTR_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_WPTR_BASE : 30;
+        unsigned int                    RB_WPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB1_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB1_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB1_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB1_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB2_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB2_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB2_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB2_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                         ST_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         ST_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        ST_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        ST_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_QUEUE_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CSQ_IB1_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB1_START : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CSQ_CNT_RING : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                    CSQ_CNT_RING : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STQ_CNT_ST : 7;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                      STQ_CNT_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MEQ_CNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                         MEQ_CNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_RB_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB1_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB2_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NON_PREFETCH_CNTRS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     IB1_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB1_COUNTER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_ST_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STQ_RPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_RPTR_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MEQ_RPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_RPTR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MIU_TAG_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TAG_0_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                                 : 13;
+        unsigned int              INVALID_RETURN_TAG : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              INVALID_RETURN_TAG : 1;
+        unsigned int                                 : 13;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_0_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CMD_INDEX : 7;
+        unsigned int                                 : 9;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 9;
+        unsigned int                       CMD_INDEX : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CMD_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CMD_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ME_STATMUX : 16;
+        unsigned int                                 : 9;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   PROG_CNT_SIZE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PROG_CNT_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                                 : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 9;
+        unsigned int                      ME_STATMUX : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ME_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ME_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_WADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_WADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_WADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_RADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_RADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_RADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ME_RAM_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ME_RAM_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RDADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ME_RDADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ME_RDADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int                                 : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG4 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG4 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG5 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG5 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG6 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG6 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG7 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG7 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_UMSK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_UMSK : 8;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_UMSK : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                    SCRATCH_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_SWM : 1;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                     VS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_SWAP : 2;
+        unsigned int                    VS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_ADDR : 30;
+        unsigned int                    VS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PS_DONE_SWM : 1;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                     PS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_SWAP : 2;
+        unsigned int                    PS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_ADDR : 30;
+        unsigned int                    PS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CF_DONE_SRC : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                     CF_DONE_SRC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_SWAP : 2;
+        unsigned int                    CF_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_ADDR : 30;
+        unsigned int                    CF_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_SWAP : 2;
+        unsigned int                  NRT_WRITE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_ADDR : 30;
+        unsigned int                  NRT_WRITE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                     RB_INT_MASK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                     RB_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                      RB_INT_ACK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RB_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_ADDR : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      UCODE_ADDR : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_DATA : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      UCODE_DATA : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFMON_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFMON_STATE : 4;
+        unsigned int                                 : 4;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PERFMON_STATE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFCOUNT_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                   PERFCOUNT_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PERFCOUNT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    PERFCOUNT_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DISCARD_0 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_15 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_15 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_16 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_31 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_31 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_16 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_32 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_47 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_47 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_32 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_48 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_63 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_63 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_48 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               STATE_DEBUG_INDEX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int               STATE_DEBUG_INDEX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                STATE_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                STATE_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PROG_COUNTER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         COUNTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         COUNTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     MIU_WR_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                         CP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CP_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int                     MIU_WR_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_0_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_1_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_2_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_3_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_4_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_5_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_6_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_7_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_8_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_9_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_10_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_11_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_12_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_13_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_14_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_15_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                                 : 8;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 8;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                                 : 8;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 8;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_0 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_0 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_1 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_1 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_2 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_2 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_3 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_3 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_4 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_4 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_5 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_5 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_6 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_6 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_7 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_7 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SURFACE_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SURFACE_PITCH : 14;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                   SURFACE_PITCH : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    COLOR_FORMAT : 4;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      COLOR_BASE : 20;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_FORMAT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEPTH_FORMAT : 1;
+        unsigned int                                 : 11;
+        unsigned int                      DEPTH_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      DEPTH_BASE : 20;
+        unsigned int                                 : 11;
+        unsigned int                    DEPTH_FORMAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STENCILREF : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                      STENCILREF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ALPHA_REF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ALPHA_REF : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ALPHA_REF : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       WRITE_RED : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                                 : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 28;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                       WRITE_RED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_RED {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BLEND_RED : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       BLEND_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_GREEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_GREEN : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_GREEN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_BLUE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      BLEND_BLUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      BLEND_BLUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_ALPHA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_ALPHA : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_ALPHA : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FOG_COLOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         FOG_RED : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                         FOG_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK_BF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   STENCILREF_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int                   STENCILREF_BF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTHCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  STENCIL_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                 STENCILZFAIL_BF : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 STENCILZFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  STENCIL_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLENDCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  COLOR_SRCBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                  COLOR_SRCBLEND : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLORCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ALPHA_FUNC : 3;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                                 : 7;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int                                 : 7;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int                      ALPHA_FUNC : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_MODECONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_MODE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                      EDRAM_MODE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_DEST_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COLOR_DEST_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 COLOR_DEST_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                  COPY_DEST_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  COPY_DEST_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PITCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COPY_DEST_PITCH : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                 COPY_DEST_PITCH : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                COPY_DEST_ENDIAN : 3;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_ENDIAN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PIXEL_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        OFFSET_X : 13;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                        OFFSET_X : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     DEPTH_CLEAR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEPTH_CLEAR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_CTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int                                 : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int                       RESERVED9 : 1;
+        unsigned int                      RESERVED10 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED10 : 1;
+        unsigned int                       RESERVED9 : 1;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                                 : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_EDRAM_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_SIZE : 4;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                                 : 8;
+        unsigned int                     EDRAM_RANGE : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     EDRAM_RANGE : 18;
+        unsigned int                                 : 8;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                      EDRAM_SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_RD_PORT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CRC_RD_ADVANCE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                  CRC_RD_ADVANCE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_TOTAL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TOTAL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TOTAL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZPASS_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZPASS_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZPASS_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 TILE_FIFO_COUNT : 4;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z_TILE_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    Z_TILE_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 TILE_FIFO_COUNT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ACCUM_VALID : 4;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int                     ACCUM_VALID : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int                                 : 19;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 19;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FLAG_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_ENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_MOREENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h
new file mode 100644
index 000000000000..2049d0f7bd14
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h
@@ -0,0 +1,4078 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_SHIFT_HEADER)
+#define _yamato_SHIFT_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT          0x00000000
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT           0x00000000
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT          0x00000001
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT           0x00000002
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT          0x00000003
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT           0x00000004
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT          0x00000005
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT                  0x00000008
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT                   0x00000009
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT                  0x0000000a
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT             0x0000000b
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT               0x00000010
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT     0x00000012
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT          0x00000013
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT        0x00000014
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT                0x00000015
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT              0x00000016
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT               0x00000017
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT               0x00000018
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT         0x00000000
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT                  0x00000000
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT                  0x00000001
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT                  0x00000003
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT                    0x00000000
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT                     0x00000010
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT                0x00000000
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT                0x00000010
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT                      0x00000000
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT              0x00000000
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT               0x00000001
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT                    0x00000002
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT               0x00000003
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT    0x00000005
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT     0x00000008
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT             0x0000000f
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT     0x00000012
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT      0x00000013
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT          0x00000014
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT       0x00000015
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT       0x00000017
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT    0x00000019
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT        0x00000000
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT      0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT         0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT       0x00000000
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT        0x00000000
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT        0x00000010
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT           0x00000000
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT            0x0000000d
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK__SHIFT                      0x00000000
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT            0x00000000
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT            0x00000010
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT       0x0000001c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT         0x0000001d
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT                  0x00000000
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT              0x00000008
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT          0x00000009
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT                 0x0000000a
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT              0x00000000
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT               0x00000001
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT      0x00000007
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT         0x00000000
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT       0x00000000
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT     0x00000008
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT                  0x0000001f
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT  0x00000000
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT   0x00000001
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT  0x00000002
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT   0x00000003
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT     0x0000000d
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT            0x00000014
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT    0x00000013
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT            0x00000018
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT           0x00000018
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT           0x00000008
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT           0x0000001a
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT           0x00000008
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT           0x00000001
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT           0x00000016
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT           0x0000001c
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT   0x00000000
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT           0x00000006
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT           0x0000000c
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT           0x00000012
+#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT        0x00000014
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT   0x0000001c
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT    0x0000001d
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT           0x0000000a
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT           0x00000013
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT            0x00000004
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT           0x00000002
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT           0x00000016
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT      0x00000000
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT     0x00000004
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT    0x0000000e
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT      0x00000014
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT           0x0000001b
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT           0x00000000
+#define SXIFCCG_DEBUG_REG0__position_address__SHIFT        0x00000004
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG0__point_address__SHIFT           0x0000000a
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT            0x0000000d
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT            0x00000011
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT  0x00000013
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT       0x00000017
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT   0x0000001e
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT   0x0000001f
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT            0x00000000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT          0x00000002
+#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT     0x00000004
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT      0x0000000b
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT         0x0000000c
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT                 0x00000014
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT            0x00000015
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT            0x00000017
+#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT        0x00000019
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT                 0x00000000
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT            0x00000001
+#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT                  0x00000002
+#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT         0x00000003
+#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT        0x00000009
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT            0x00000012
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT            0x00000016
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT   0x0000001b
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT    0x0000001c
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT            0x00000004
+#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT     0x00000005
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT            0x00000008
+#define SXIFCCG_DEBUG_REG3__current_state__SHIFT           0x0000000c
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT       0x0000000e
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT        0x0000000f
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT  0x00000012
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT   0x00000013
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT  0x00000015
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT            0x00000016
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT             0x00000000
+#define SETUP_DEBUG_REG0__pmode_state__SHIFT               0x00000005
+#define SETUP_DEBUG_REG0__ge_stallb__SHIFT                 0x0000000b
+#define SETUP_DEBUG_REG0__geom_enable__SHIFT               0x0000000c
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT         0x0000000d
+#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT               0x0000000e
+#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT                0x0000000f
+#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT              0x00000010
+#define SETUP_DEBUG_REG0__geom_busy__SHIFT                 0x00000011
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT           0x0000000b
+#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT          0x0000000c
+#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT             0x0000000d
+#define SETUP_DEBUG_REG4__clipped_gated__SHIFT             0x00000010
+#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT        0x00000011
+#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT              0x00000014
+#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT        0x00000015
+#define SETUP_DEBUG_REG4__type_gated__SHIFT                0x00000017
+#define SETUP_DEBUG_REG4__fpov_gated__SHIFT                0x0000001a
+#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT          0x0000001b
+#define SETUP_DEBUG_REG4__event_gated__SHIFT               0x0000001c
+#define SETUP_DEBUG_REG4__eop_gated__SHIFT                 0x0000001d
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT     0x0000000b
+#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT       0x00000016
+#define SETUP_DEBUG_REG5__event_id_gated__SHIFT            0x00000018
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1__SHIFT                    0x00000000
+#define SC_DEBUG_0__pa_sc_valid__SHIFT                     0x00000001
+#define SC_DEBUG_0__pa_sc_phase__SHIFT                     0x00000002
+#define SC_DEBUG_0__cntx_cnt__SHIFT                        0x00000005
+#define SC_DEBUG_0__decr_cntx_cnt__SHIFT                   0x0000000c
+#define SC_DEBUG_0__incr_cntx_cnt__SHIFT                   0x0000000d
+#define SC_DEBUG_0__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state__SHIFT                        0x00000000
+#define SC_DEBUG_1__em1_data_ready__SHIFT                  0x00000003
+#define SC_DEBUG_1__em2_data_ready__SHIFT                  0x00000004
+#define SC_DEBUG_1__move_em1_to_em2__SHIFT                 0x00000005
+#define SC_DEBUG_1__ef_data_ready__SHIFT                   0x00000006
+#define SC_DEBUG_1__ef_state__SHIFT                        0x00000007
+#define SC_DEBUG_1__pipe_valid__SHIFT                      0x00000009
+#define SC_DEBUG_1__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly__SHIFT                      0x00000000
+#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT            0x00000001
+#define SC_DEBUG_2__pipe_freeze_b__SHIFT                   0x00000003
+#define SC_DEBUG_2__prim_rts__SHIFT                        0x00000004
+#define SC_DEBUG_2__next_prim_rts_dly__SHIFT               0x00000005
+#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT               0x00000006
+#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT               0x00000007
+#define SC_DEBUG_2__stage0_rts__SHIFT                      0x00000008
+#define SC_DEBUG_2__phase_rts_dly__SHIFT                   0x00000009
+#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT              0x0000000f
+#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT              0x00000010
+#define SC_DEBUG_2__event_id_s1__SHIFT                     0x00000011
+#define SC_DEBUG_2__event_s1__SHIFT                        0x00000016
+#define SC_DEBUG_2__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1__SHIFT                       0x00000000
+#define SC_DEBUG_3__y_curr_s1__SHIFT                       0x0000000b
+#define SC_DEBUG_3__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_4__y_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_4__y_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_4__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_5__x_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_5__x_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_5__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty__SHIFT                      0x00000000
+#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT                 0x00000001
+#define SC_DEBUG_6__xy_ff_empty__SHIFT                     0x00000002
+#define SC_DEBUG_6__event_flag__SHIFT                      0x00000003
+#define SC_DEBUG_6__z_mask_needed__SHIFT                   0x00000004
+#define SC_DEBUG_6__state__SHIFT                           0x00000005
+#define SC_DEBUG_6__state_delayed__SHIFT                   0x00000008
+#define SC_DEBUG_6__data_valid__SHIFT                      0x0000000b
+#define SC_DEBUG_6__data_valid_d__SHIFT                    0x0000000c
+#define SC_DEBUG_6__tilex_delayed__SHIFT                   0x0000000d
+#define SC_DEBUG_6__tiley_delayed__SHIFT                   0x00000016
+#define SC_DEBUG_6__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag__SHIFT                      0x00000000
+#define SC_DEBUG_7__deallocate__SHIFT                      0x00000001
+#define SC_DEBUG_7__fpos__SHIFT                            0x00000004
+#define SC_DEBUG_7__sr_prim_we__SHIFT                      0x00000005
+#define SC_DEBUG_7__last_tile__SHIFT                       0x00000006
+#define SC_DEBUG_7__tile_ff_we__SHIFT                      0x00000007
+#define SC_DEBUG_7__qs_data_valid__SHIFT                   0x00000008
+#define SC_DEBUG_7__qs_q0_y__SHIFT                         0x00000009
+#define SC_DEBUG_7__qs_q0_x__SHIFT                         0x0000000b
+#define SC_DEBUG_7__qs_q0_valid__SHIFT                     0x0000000d
+#define SC_DEBUG_7__prim_ff_we__SHIFT                      0x0000000e
+#define SC_DEBUG_7__tile_ff_re__SHIFT                      0x0000000f
+#define SC_DEBUG_7__fw_prim_data_valid__SHIFT              0x00000010
+#define SC_DEBUG_7__last_quad_of_tile__SHIFT               0x00000011
+#define SC_DEBUG_7__first_quad_of_tile__SHIFT              0x00000012
+#define SC_DEBUG_7__first_quad_of_prim__SHIFT              0x00000013
+#define SC_DEBUG_7__new_prim__SHIFT                        0x00000014
+#define SC_DEBUG_7__load_new_tile_data__SHIFT              0x00000015
+#define SC_DEBUG_7__state__SHIFT                           0x00000016
+#define SC_DEBUG_7__fifos_ready__SHIFT                     0x00000018
+#define SC_DEBUG_7__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last__SHIFT                     0x00000000
+#define SC_DEBUG_8__sample_mask__SHIFT                     0x00000001
+#define SC_DEBUG_8__sample_y__SHIFT                        0x00000005
+#define SC_DEBUG_8__sample_x__SHIFT                        0x00000007
+#define SC_DEBUG_8__sample_send__SHIFT                     0x00000009
+#define SC_DEBUG_8__next_cycle__SHIFT                      0x0000000a
+#define SC_DEBUG_8__ez_sample_ff_full__SHIFT               0x0000000c
+#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT                  0x0000000d
+#define SC_DEBUG_8__num_samples__SHIFT                     0x0000000e
+#define SC_DEBUG_8__last_quad_of_tile__SHIFT               0x00000010
+#define SC_DEBUG_8__last_quad_of_prim__SHIFT               0x00000011
+#define SC_DEBUG_8__first_quad_of_prim__SHIFT              0x00000012
+#define SC_DEBUG_8__sample_we__SHIFT                       0x00000013
+#define SC_DEBUG_8__fpos__SHIFT                            0x00000014
+#define SC_DEBUG_8__event_id__SHIFT                        0x00000015
+#define SC_DEBUG_8__event_flag__SHIFT                      0x0000001a
+#define SC_DEBUG_8__fw_prim_data_valid__SHIFT              0x0000001b
+#define SC_DEBUG_8__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send__SHIFT                      0x00000000
+#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT                   0x00000001
+#define SC_DEBUG_9__fifo_data_ready__SHIFT                 0x00000005
+#define SC_DEBUG_9__early_z_enable__SHIFT                  0x00000006
+#define SC_DEBUG_9__mask_state__SHIFT                      0x00000007
+#define SC_DEBUG_9__next_ez_mask__SHIFT                    0x00000009
+#define SC_DEBUG_9__mask_ready__SHIFT                      0x00000019
+#define SC_DEBUG_9__drop_sample__SHIFT                     0x0000001a
+#define SC_DEBUG_9__fetch_new_sample_data__SHIFT           0x0000001b
+#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT        0x0000001c
+#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT       0x0000001d
+#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT         0x0000001e
+#define SC_DEBUG_9__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask__SHIFT           0x00000000
+#define SC_DEBUG_10__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready__SHIFT           0x00000000
+#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT      0x00000001
+#define SC_DEBUG_11__ez_prim_data_ready__SHIFT             0x00000002
+#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT        0x00000003
+#define SC_DEBUG_11__iterator_input_fz__SHIFT              0x00000004
+#define SC_DEBUG_11__packer_send_quads__SHIFT              0x00000005
+#define SC_DEBUG_11__packer_send_cmd__SHIFT                0x00000006
+#define SC_DEBUG_11__packer_send_event__SHIFT              0x00000007
+#define SC_DEBUG_11__next_state__SHIFT                     0x00000008
+#define SC_DEBUG_11__state__SHIFT                          0x0000000b
+#define SC_DEBUG_11__stall__SHIFT                          0x0000000e
+#define SC_DEBUG_11__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT          0x00000000
+#define SC_DEBUG_12__event_id__SHIFT                       0x00000001
+#define SC_DEBUG_12__event_flag__SHIFT                     0x00000006
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT        0x00000007
+#define SC_DEBUG_12__itercmdfifo_full__SHIFT               0x00000008
+#define SC_DEBUG_12__itercmdfifo_empty__SHIFT              0x00000009
+#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT        0x0000000a
+#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT           0x0000000b
+#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT          0x0000000c
+#define SC_DEBUG_12__iter_qdhit0__SHIFT                    0x0000000d
+#define SC_DEBUG_12__bc_use_centers_reg__SHIFT             0x0000000e
+#define SC_DEBUG_12__bc_output_xy_reg__SHIFT               0x0000000f
+#define SC_DEBUG_12__iter_phase_out__SHIFT                 0x00000010
+#define SC_DEBUG_12__iter_phase_reg__SHIFT                 0x00000012
+#define SC_DEBUG_12__iterator_SP_valid__SHIFT              0x00000014
+#define SC_DEBUG_12__eopv_reg__SHIFT                       0x00000015
+#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT                0x00000016
+#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT            0x00000017
+#define SC_DEBUG_12__trigger__SHIFT                        0x0000001f
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT                0x00000000
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT               0x00000000
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT           0x00000006
+#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT              0x0000000b
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT                 0x0000000c
+#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT             0x0000000d
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT   0x0000000e
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT         0x0000000f
+#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT             0x00000010
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT             0x00000000
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT                     0x00000000
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_DMA_SIZE__SWAP_MODE__SHIFT                     0x0000001e
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT                 0x00000000
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS__SHIFT                     0x00000000
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT                  0x00000000
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT                  0x00000000
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT                0x00000000
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT          0x00000000
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT    0x00000000
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC__SHIFT                           0x00000000
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT          0x00000000
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT           0x00000000
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT           0x00000010
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT              0x00000000
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT                   0x00000000
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT               0x00000001
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT           0x00000002
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT               0x00000003
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT                0x00000004
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT               0x00000005
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT                0x00000006
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT               0x00000007
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT          0x00000008
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy__SHIFT                 0x00000000
+#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT                 0x00000001
+#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT                 0x00000002
+#define VGT_DEBUG_REG0__dma_request_busy__SHIFT            0x00000003
+#define VGT_DEBUG_REG0__out_busy__SHIFT                    0x00000004
+#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT            0x00000005
+#define VGT_DEBUG_REG0__grp_busy__SHIFT                    0x00000006
+#define VGT_DEBUG_REG0__dma_busy__SHIFT                    0x00000007
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT       0x00000008
+#define VGT_DEBUG_REG0__rbiu_busy__SHIFT                   0x00000009
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT    0x0000000a
+#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT             0x0000000b
+#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT           0x0000000c
+#define VGT_DEBUG_REG0__vgt_busy__SHIFT                    0x0000000d
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT     0x0000000e
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT        0x0000000f
+#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT               0x00000010
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read__SHIFT            0x00000000
+#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT           0x00000001
+#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT            0x00000002
+#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT           0x00000003
+#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT            0x00000004
+#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT           0x00000005
+#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT            0x00000006
+#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT           0x00000007
+#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT            0x00000008
+#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT           0x00000009
+#define VGT_DEBUG_REG1__te_grp_read__SHIFT                 0x0000000a
+#define VGT_DEBUG_REG1__grp_te_valid__SHIFT                0x0000000b
+#define VGT_DEBUG_REG1__pt_grp_read__SHIFT                 0x0000000c
+#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT                0x0000000d
+#define VGT_DEBUG_REG1__vr_grp_read__SHIFT                 0x0000000e
+#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT                0x0000000f
+#define VGT_DEBUG_REG1__grp_dma_read__SHIFT                0x00000010
+#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT               0x00000011
+#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT            0x00000012
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT           0x00000013
+#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT                  0x00000014
+#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT                 0x00000015
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT           0x00000016
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT          0x00000017
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT           0x00000018
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT          0x00000019
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT           0x0000001a
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT          0x0000001b
+#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT                  0x0000001c
+#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT                 0x0000001d
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT              0x0000001e
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT                  0x00000000
+#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT            0x00000001
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT        0x00000000
+#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT           0x00000005
+#define VGT_DEBUG_REG6__input_data_valid__SHIFT            0x0000000a
+#define VGT_DEBUG_REG6__input_data_xfer__SHIFT             0x0000000b
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT      0x0000000c
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT      0x0000000d
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT  0x0000000e
+#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT      0x0000000f
+#define VGT_DEBUG_REG6__shifter_first_load__SHIFT          0x00000010
+#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT       0x00000013
+#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT             0x00000014
+#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT         0x00000015
+#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT        0x00000017
+#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT         0x00000018
+#define VGT_DEBUG_REG6__extract_vector__SHIFT              0x00000019
+#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT              0x0000001a
+#define VGT_DEBUG_REG6__destination_rtr__SHIFT             0x0000001b
+#define VGT_DEBUG_REG6__grp_trigger__SHIFT                 0x0000001c
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT          0x00000000
+#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT     0x00000010
+#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT        0x00000014
+#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG7__current_source_sel__SHIFT          0x0000001e
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel__SHIFT          0x00000000
+#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT            0x00000002
+#define VGT_DEBUG_REG8__input_data_cnt__SHIFT              0x00000007
+#define VGT_DEBUG_REG8__input_data_lsw__SHIFT              0x0000000c
+#define VGT_DEBUG_REG8__input_data_msw__SHIFT              0x00000011
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q__SHIFT               0x00000000
+#define VGT_DEBUG_REG9__next_stride_d__SHIFT               0x00000005
+#define VGT_DEBUG_REG9__current_shift_q__SHIFT             0x0000000a
+#define VGT_DEBUG_REG9__current_shift_d__SHIFT             0x0000000f
+#define VGT_DEBUG_REG9__current_stride_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG9__current_stride_d__SHIFT            0x00000019
+#define VGT_DEBUG_REG9__grp_trigger__SHIFT                 0x0000001e
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003
+#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT             0x00000004
+#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT        0x00000005
+#define VGT_DEBUG_REG10__bin_valid__SHIFT                  0x00000006
+#define VGT_DEBUG_REG10__read_block__SHIFT                 0x00000007
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT     0x00000008
+#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT          0x00000009
+#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG10__selected_data__SHIFT              0x0000000b
+#define VGT_DEBUG_REG10__mask_input_data__SHIFT            0x00000013
+#define VGT_DEBUG_REG10__gap_q__SHIFT                      0x0000001b
+#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT          0x0000001c
+#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT          0x0000001d
+#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT          0x0000001e
+#define VGT_DEBUG_REG10__grp_trigger__SHIFT                0x0000001f
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT       0x00000000
+#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT          0x00000005
+#define VGT_DEBUG_REG12__input_data_valid__SHIFT           0x0000000a
+#define VGT_DEBUG_REG12__input_data_xfer__SHIFT            0x0000000b
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT     0x0000000c
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT     0x0000000d
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e
+#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT     0x0000000f
+#define VGT_DEBUG_REG12__shifter_first_load__SHIFT         0x00000010
+#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT             0x00000011
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT      0x00000013
+#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT        0x00000015
+#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT       0x00000017
+#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT        0x00000018
+#define VGT_DEBUG_REG12__extract_vector__SHIFT             0x00000019
+#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT             0x0000001a
+#define VGT_DEBUG_REG12__destination_rtr__SHIFT            0x0000001b
+#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT               0x0000001c
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT         0x00000000
+#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT    0x00000010
+#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT       0x00000014
+#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT             0x00000018
+#define VGT_DEBUG_REG13__current_source_sel__SHIFT         0x0000001e
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel__SHIFT         0x00000000
+#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT           0x00000002
+#define VGT_DEBUG_REG14__input_data_cnt__SHIFT             0x00000007
+#define VGT_DEBUG_REG14__input_data_lsw__SHIFT             0x0000000c
+#define VGT_DEBUG_REG14__input_data_msw__SHIFT             0x00000011
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q__SHIFT              0x00000000
+#define VGT_DEBUG_REG15__next_stride_d__SHIFT              0x00000005
+#define VGT_DEBUG_REG15__current_shift_q__SHIFT            0x0000000a
+#define VGT_DEBUG_REG15__current_shift_d__SHIFT            0x0000000f
+#define VGT_DEBUG_REG15__current_stride_q__SHIFT           0x00000014
+#define VGT_DEBUG_REG15__current_stride_d__SHIFT           0x00000019
+#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT               0x0000001e
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT  0x00000000
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT   0x00000002
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT    0x00000003
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT   0x00000004
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT  0x00000005
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT   0x00000006
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT     0x00000007
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT         0x00000008
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT         0x00000009
+#define VGT_DEBUG_REG16__rst_last_bit__SHIFT               0x0000000a
+#define VGT_DEBUG_REG16__current_state_q__SHIFT            0x0000000b
+#define VGT_DEBUG_REG16__old_state_q__SHIFT                0x0000000c
+#define VGT_DEBUG_REG16__old_state_en__SHIFT               0x0000000d
+#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT            0x0000000e
+#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT             0x0000000f
+#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT           0x00000010
+#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT           0x00000011
+#define VGT_DEBUG_REG16__load_empty_reg__SHIFT             0x00000012
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT   0x00000013
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT   0x0000001e
+#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q__SHIFT                0x00000000
+#define VGT_DEBUG_REG17__extend_read_q__SHIFT              0x00000001
+#define VGT_DEBUG_REG17__grp_indx_size__SHIFT              0x00000002
+#define VGT_DEBUG_REG17__cull_prim_true__SHIFT             0x00000004
+#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT               0x00000005
+#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT               0x00000006
+#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT          0x00000007
+#define VGT_DEBUG_REG17__check_second_reg__SHIFT           0x00000008
+#define VGT_DEBUG_REG17__check_first_reg__SHIFT            0x00000009
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT    0x0000000b
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT    0x0000000c
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT     0x0000000d
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT     0x0000000e
+#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT            0x0000000f
+#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT            0x00000010
+#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT    0x00000000
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT    0x00000006
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d
+#define VGT_DEBUG_REG18__dma_mem_full__SHIFT               0x0000000f
+#define VGT_DEBUG_REG18__dma_ram_re__SHIFT                 0x00000010
+#define VGT_DEBUG_REG18__dma_ram_we__SHIFT                 0x00000011
+#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT              0x00000012
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT       0x00000013
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT       0x00000014
+#define VGT_DEBUG_REG18__bin_mem_full__SHIFT               0x00000015
+#define VGT_DEBUG_REG18__bin_ram_we__SHIFT                 0x00000016
+#define VGT_DEBUG_REG18__bin_ram_re__SHIFT                 0x00000017
+#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT              0x00000018
+#define VGT_DEBUG_REG18__start_bin_req__SHIFT              0x00000019
+#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT        0x0000001a
+#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT               0x0000001b
+#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT         0x0000001c
+#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT         0x0000001d
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT       0x00000000
+#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT       0x00000001
+#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT          0x00000002
+#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT          0x00000003
+#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT        0x00000004
+#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT          0x00000005
+#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT             0x00000006
+#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT             0x00000007
+#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT           0x00000008
+#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT          0x00000009
+#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT             0x0000000a
+#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT             0x0000000b
+#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT           0x0000000c
+#define VGT_DEBUG_REG20__hold_prim__SHIFT                  0x0000000d
+#define VGT_DEBUG_REG20__sent_cnt__SHIFT                   0x0000000e
+#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT        0x00000012
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT       0x00000013
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT       0x00000014
+#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT   0x00000015
+#define VGT_DEBUG_REG20__out_trigger__SHIFT                0x0000001a
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT  0x00000000
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001
+#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT            0x00000004
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT    0x00000007
+#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT    0x0000000e
+#define VGT_DEBUG_REG21__new_packet_q__SHIFT               0x00000012
+#define VGT_DEBUG_REG21__new_allocate_q__SHIFT             0x00000013
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT    0x00000014
+#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT       0x00000016
+#define VGT_DEBUG_REG21__insert_null_prim__SHIFT           0x00000017
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT      0x00000018
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT      0x00000019
+#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT       0x0000001a
+#define VGT_DEBUG_REG21__out_trigger__SHIFT                0x0000001f
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC__SHIFT                        0x00000000
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC__SHIFT                        0x00000000
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT             0x00000000
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT               0x00000000
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT              0x00000012
+#define TC_CNTL_STATUS__TC_BUSY__SHIFT                     0x0000001f
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT               0x00000008
+#define TCM_CHICKEN__SPARE__SHIFT                          0x00000009
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT          0x00000000
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT          0x00000003
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT             0x00000000
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT           0x00000001
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT        0x00000002
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT        0x00000003
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT       0x00000004
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT         0x00000005
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT            0x00000006
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT      0x00000008
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT        0x00000009
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT           0x0000000a
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT           0x0000000c
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT        0x0000000d
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT          0x0000000e
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT             0x0000000f
+#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT                  0x00000010
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT            0x00000011
+#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT                  0x00000013
+#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT                  0x00000014
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT               0x00000015
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT             0x00000016
+#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT                  0x00000017
+#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT                  0x00000018
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT               0x00000019
+#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT                  0x0000001b
+#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT                  0x0000001c
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT          0x0000001d
+#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT                  0x0000001e
+#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT                   0x0000001f
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL__SHIFT                        0x00000000
+#define TPC_DEBUG0__IC_CTR__SHIFT                          0x00000002
+#define TPC_DEBUG0__WALKER_CNTL__SHIFT                     0x00000004
+#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT                    0x00000008
+#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT             0x0000000c
+#define TPC_DEBUG0__WALKER_STATE__SHIFT                    0x00000010
+#define TPC_DEBUG0__ALIGNER_STATE__SHIFT                   0x0000001a
+#define TPC_DEBUG0__REG_CLK_EN__SHIFT                      0x0000001d
+#define TPC_DEBUG0__TPC_CLK_EN__SHIFT                      0x0000001e
+#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT                    0x0000001f
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED__SHIFT                          0x00000000
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION__SHIFT                0x00000000
+#define TPC_CHICKEN__SPARE__SHIFT                          0x00000001
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT              0x00000000
+#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT                0x00000001
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT           0x00000002
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT               0x00000003
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT         0x00000004
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT            0x00000005
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT            0x00000006
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT            0x00000007
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT              0x00000008
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT           0x00000009
+#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT                 0x0000000a
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT            0x0000000b
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT              0x0000000c
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT           0x0000000d
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT             0x0000000e
+#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT                  0x00000010
+#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT                  0x00000011
+#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT                  0x00000012
+#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT                  0x00000013
+#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT                  0x00000014
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT               0x00000015
+#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT                  0x00000016
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT               0x00000017
+#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT                  0x00000018
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT               0x00000019
+#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT                  0x0000001a
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT               0x0000001b
+#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT                  0x0000001c
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT             0x0000001d
+#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT                  0x0000001e
+#define TP0_CNTL_STATUS__TP_BUSY__SHIFT                    0x0000001f
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL__SHIFT                       0x00000000
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT                   0x00000003
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT             0x00000004
+#define TP0_DEBUG__REG_CLK_EN__SHIFT                       0x00000015
+#define TP0_DEBUG__PERF_CLK_EN__SHIFT                      0x00000016
+#define TP0_DEBUG__TP_CLK_EN__SHIFT                        0x00000017
+#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT                    0x00000018
+#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT                   0x0000001c
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE__SHIFT                        0x00000000
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT            0x00000001
+#define TP0_CHICKEN__SPARE__SHIFT                          0x00000002
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr__SHIFT                    0x00000006
+#define TCF_DEBUG__TC_MH_send__SHIFT                       0x00000007
+#define TCF_DEBUG__not_FG0_rtr__SHIFT                      0x00000008
+#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT                  0x0000000c
+#define TCF_DEBUG__TCB_ff_stall__SHIFT                     0x0000000d
+#define TCF_DEBUG__TCB_miss_stall__SHIFT                   0x0000000e
+#define TCF_DEBUG__TCA_TCB_stall__SHIFT                    0x0000000f
+#define TCF_DEBUG__PF0_stall__SHIFT                        0x00000010
+#define TCF_DEBUG__TP0_full__SHIFT                         0x00000014
+#define TCF_DEBUG__TPC_full__SHIFT                         0x00000018
+#define TCF_DEBUG__not_TPC_rtr__SHIFT                      0x00000019
+#define TCF_DEBUG__tca_state_rts__SHIFT                    0x0000001a
+#define TCF_DEBUG__tca_rts__SHIFT                          0x0000001b
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full__SHIFT                    0x00000000
+#define TCA_FIFO_DEBUG__tpc_full__SHIFT                    0x00000004
+#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT               0x00000005
+#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT               0x00000006
+#define TCA_FIFO_DEBUG__FW_full__SHIFT                     0x00000007
+#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT                 0x00000008
+#define TCA_FIFO_DEBUG__FW_rts0__SHIFT                     0x0000000c
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT              0x00000010
+#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT                  0x00000011
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT          0x00000000
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts__SHIFT             0x0000000c
+#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT              0x0000000d
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512__SHIFT                   0x00000000
+#define TCB_CORE_DEBUG__tiled__SHIFT                       0x00000001
+#define TCB_CORE_DEBUG__opcode__SHIFT                      0x00000004
+#define TCB_CORE_DEBUG__format__SHIFT                      0x00000008
+#define TCB_CORE_DEBUG__sector_format__SHIFT               0x00000010
+#define TCB_CORE_DEBUG__sector_format512__SHIFT            0x00000018
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG0_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG0_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG1_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG1_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG2_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG2_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG3_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG3_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT   0x00000004
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT    0x00000006
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT   0x0000000b
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT   0x0000000c
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT            0x0000000f
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT      0x00000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT       0x00000002
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT    0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT             0x00000017
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT         0x00000018
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT          0x00000019
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT         0x0000001a
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT          0x0000001c
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT          0x0000001e
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty__SHIFT                     0x00000010
+#define TCD_INPUT0_DEBUG__full__SHIFT                      0x00000011
+#define TCD_INPUT0_DEBUG__valid_q1__SHIFT                  0x00000014
+#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT                    0x00000015
+#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT              0x00000017
+#define TCD_INPUT0_DEBUG__ip_send__SHIFT                   0x00000018
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT            0x00000019
+#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT                0x0000001a
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT      0x00000000
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT          0x00000002
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT      0x00000003
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT           0x00000004
+#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT               0x00000005
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT              0x00000006
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT             0x00000009
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT         0x0000000a
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT           0x0000000b
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT  0x00000014
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT   0x0000001c
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT      0x0000001d
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT                0x00000004
+#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT                  0x00000005
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT    0x00000006
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT          0x00000007
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT       0x00000009
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT    0x0000000c
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT       0x00000012
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT         0x0000001e
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT         0x0000001f
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT   0x0000000a
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT   0x0000000b
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT         0x00000011
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT       0x00000012
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT          0x00000013
+#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT          0x0000001f
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT          0x00000005
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT           0x00000006
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT       0x00000007
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT       0x00000000
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT       0x00000008
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT                 0x00000009
+#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT                 0x0000000a
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT      0x0000000b
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT                0x0000000c
+#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT                0x0000000d
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT           0x00000010
+#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT              0x00000018
+#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT            0x00000019
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT  0x0000001a
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT  0x0000001b
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT  0x0000001c
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT  0x0000001d
+#define TCO_QUAD0_DEBUG0__busy__SHIFT                      0x0000001e
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT                 0x00000000
+#define TCO_QUAD0_DEBUG1__empty__SHIFT                     0x00000001
+#define TCO_QUAD0_DEBUG1__full__SHIFT                      0x00000002
+#define TCO_QUAD0_DEBUG1__write_enable__SHIFT              0x00000003
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT            0x00000004
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT             0x0000000b
+#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT           0x00000014
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT         0x00000015
+#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT           0x00000016
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT        0x00000017
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT             0x00000018
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT             0x00000019
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT                 0x0000001a
+#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT                 0x0000001b
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT                0x0000001c
+#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT                0x0000001d
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT          0x0000001e
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT              0x00000000
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT             0x00000004
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT             0x0000000c
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT   0x00000000
+#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT                 0x00000004
+#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT                    0x00000008
+#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT                 0x0000000c
+#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT                   0x00000010
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT               0x00000011
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT          0x00000012
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT      0x00000015
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT     0x00000016
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT               0x00000017
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT               0x00000018
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT           0x00000019
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT    0x0000001b
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT      0x00000000
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT      0x00000010
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT   0x00000010
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT                   0x00000000
+#define SQ_EO_RT__EO_TSTATE_RT__SHIFT                      0x00000010
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT               0x00000000
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT               0x0000000c
+#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT                  0x00000014
+#define SQ_DEBUG_MISC__RESERVED__SHIFT                     0x00000015
+#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT               0x00000017
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT              0x00000019
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT              0x0000001a
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT              0x0000001b
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT              0x0000001c
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT            0x00000000
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT       0x00000008
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT      0x00000010
+#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT               0x00000018
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT      0x00000000
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT      0x00000000
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT        0x00000003
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT      0x00000004
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT        0x00000007
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT            0x00000008
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT     0x00000000
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT       0x00000003
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT     0x00000004
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT       0x00000007
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT           0x00000008
+#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT            0x00000012
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT               0x00000000
+#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT                0x00000003
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT               0x00000004
+#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT                 0x00000008
+#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT                   0x0000000c
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT           0x0000000f
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT             0x00000014
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT           0x00000005
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT           0x0000000d
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT                      0x00000000
+#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT                  0x00000003
+#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT                      0x00000004
+#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT                      0x00000008
+#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT                  0x0000000b
+#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT                     0x0000000c
+#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT                  0x0000000e
+#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT                      0x00000010
+#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT                  0x00000012
+#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT                     0x00000014
+#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT                  0x00000016
+#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT                     0x00000018
+#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT                  0x0000001a
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT                  0x0000001c
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT           0x00000000
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT         0x00000004
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT            0x0000000c
+#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT                0x0000000f
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT     0x00000010
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT            0x00000000
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT              0x00000001
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT          0x00000005
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT         0x00000006
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT              0x00000009
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT               0x0000000e
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT        0x0000000f
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT                 0x00000010
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT             0x00000011
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT   0x0000001d
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT           0x00000000
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT               0x00000004
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT               0x00000008
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT        0x0000000c
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT         0x00000010
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT            0x00000014
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT                   0x00000015
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT              0x00000000
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT   0x00000000
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT     0x00000000
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT             0x00000000
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT                 0x00000006
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT                 0x0000000c
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT        0x00000013
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT          0x00000019
+#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT                     0x0000001f
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD__SHIFT         0x00000006
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT  0x00000007
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT           0x0000000f
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT        0x00000010
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT        0x00000014
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT          0x00000018
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT          0x00000019
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT         0x0000001a
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT       0x00000000
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT       0x00000002
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT       0x00000004
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT       0x00000006
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT       0x00000008
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT       0x0000000c
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT       0x0000000e
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT       0x00000010
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT       0x00000012
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT       0x00000014
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT       0x00000016
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT         0x00000019
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT           0x0000001b
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT       0x0000001e
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT       0x0000001f
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT          0x00000006
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT         0x00000007
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT          0x0000000e
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT         0x00000010
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT          0x00000016
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT         0x00000017
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT             0x0000001d
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT             0x0000001e
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT          0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT             0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT             0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT       0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT     0x00000013
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT       0x00000014
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT     0x00000015
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT       0x00000016
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT     0x00000017
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT       0x00000018
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT     0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT       0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT     0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT         0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT         0x0000001e
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT         0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT         0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT         0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT         0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT          0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT             0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT       0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT     0x00000003
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT       0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT     0x00000005
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT       0x00000006
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT     0x00000007
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT       0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT     0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT     0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT         0x0000000d
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT         0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT         0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT         0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT        0x0000000a
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT        0x00000015
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT        0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT        0x0000001a
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT          0x00000005
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT    0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT    0x0000000d
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT    0x0000000f
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT    0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT     0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT     0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT  0x0000000b
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT        0x0000000c
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT    0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT    0x0000001d
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT    0x0000001e
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT      0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT     0x00000012
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT  0x0000001b
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT        0x0000001c
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT         0x00000004
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT        0x00000008
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT    0x00000009
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT       0x0000000b
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT           0x0000000c
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT             0x00000010
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT       0x00000014
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT        0x00000018
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT    0x00000019
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT       0x0000001b
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT           0x0000001c
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT   0x00000013
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT    0x00000019
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT          0x0000001a
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT          0x0000001c
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT          0x0000001e
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT         0x00000010
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT       0x00000012
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT   0x00000015
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT     0x00000018
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT       0x0000001c
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT        0x0000001d
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT  0x00000000
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT    0x00000001
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT           0x00000002
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT             0x00000009
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT           0x00000010
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT           0x00000015
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT           0x0000001a
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT        0x00000013
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT    0x00000019
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT            0x0000001e
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT    0x0000000c
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT     0x0000000d
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT        0x00000010
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT     0x00000017
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT             0x00000010
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED__SHIFT                          0x00000000
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN__SHIFT                        0x00000000
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE__SHIFT                         0x00000000
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA__SHIFT                        0x00000000
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE__SHIFT                           0x00000000
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT                  0x00000000
+#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT                 0x00000001
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT          0x00000002
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT           0x00000000
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT         0x00000002
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE__SHIFT                       0x00000000
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE__SHIFT                       0x00000000
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT               0x00000000
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT               0x00000008
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT               0x00000010
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT               0x00000018
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT                   0x00000000
+#define SQ_CF_LOOP__CF_LOOP_START__SHIFT                   0x00000008
+#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT                    0x00000010
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED__SHIFT                       0x00000000
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN__SHIFT                     0x00000000
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE__SHIFT                      0x00000000
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA__SHIFT                     0x00000000
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE__SHIFT                        0x00000000
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT            0x00000000
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT            0x00000008
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT            0x00000010
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT            0x00000018
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT                0x00000000
+#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT                0x00000008
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT                 0x00000010
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_VS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_PS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT              0x00000000
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT              0x0000000c
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT           0x00000000
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT      0x00000010
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT                 0x00000000
+#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT                 0x00000008
+#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT                0x00000010
+#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT                0x00000011
+#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT                  0x00000012
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT              0x00000013
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT            0x00000014
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT             0x00000018
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT             0x0000001b
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT              0x0000001f
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT                 0x00000000
+#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT                 0x00000004
+#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT                 0x00000008
+#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT                 0x0000000c
+#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT                 0x00000010
+#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT                 0x00000014
+#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT                 0x00000018
+#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT                 0x0000001c
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT                 0x00000000
+#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT                 0x00000004
+#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT                0x00000008
+#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT                0x0000000c
+#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT                0x00000010
+#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT                0x00000014
+#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT                0x00000018
+#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT                0x0000001c
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_VS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_PS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT         0x00000000
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT        0x00000001
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT             0x00000002
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT              0x00000008
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT            0x00000010
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT             0x00000011
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT               0x00000012
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE__SHIFT                      0x00000000
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT                 0x00000000
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT              0x00000004
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT               0x00000008
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT              0x00000018
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT                  0x00000000
+#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT                  0x00000001
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT              0x00000008
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT              0x00000010
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT          0x00000000
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT    0x00000006
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT            0x00000007
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT       0x00000008
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT           0x00000009
+#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT                0x0000000a
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT        0x0000000d
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT       0x0000000e
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT   0x0000000f
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT          0x00000010
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT           0x00000016
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT          0x00000017
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT           0x00000018
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT           0x00000019
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT                0x00000000
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT             0x00000003
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT                0x00000004
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT             0x00000007
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT               0x00000008
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT           0x00000000
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT          0x00000001
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT           0x00000002
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT         0x00000000
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT        0x00000001
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT         0x00000002
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT          0x00000000
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT         0x00000001
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT          0x00000002
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID__SHIFT                   0x00000000
+#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT                0x00000003
+#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT                  0x00000004
+#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT               0x00000007
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX__SHIFT                        0x00000000
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA__SHIFT                         0x00000000
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY__SHIFT                     0x00000000
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT           0x00000001
+#define MH_DEBUG_REG00__CP_REQUEST__SHIFT                  0x00000002
+#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT                 0x00000003
+#define MH_DEBUG_REG00__TC_REQUEST__SHIFT                  0x00000004
+#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT                0x00000005
+#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT                 0x00000006
+#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT                   0x00000007
+#define MH_DEBUG_REG00__TCD_FULL__SHIFT                    0x00000008
+#define MH_DEBUG_REG00__RB_REQUEST__SHIFT                  0x00000009
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT             0x0000000a
+#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT                   0x0000000b
+#define MH_DEBUG_REG00__ARQ_FULL__SHIFT                    0x0000000c
+#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT                   0x0000000d
+#define MH_DEBUG_REG00__WDB_FULL__SHIFT                    0x0000000e
+#define MH_DEBUG_REG00__AXI_AVALID__SHIFT                  0x0000000f
+#define MH_DEBUG_REG00__AXI_AREADY__SHIFT                  0x00000010
+#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT                 0x00000011
+#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT                 0x00000012
+#define MH_DEBUG_REG00__AXI_WVALID__SHIFT                  0x00000013
+#define MH_DEBUG_REG00__AXI_WREADY__SHIFT                  0x00000014
+#define MH_DEBUG_REG00__AXI_RVALID__SHIFT                  0x00000015
+#define MH_DEBUG_REG00__AXI_RREADY__SHIFT                  0x00000016
+#define MH_DEBUG_REG00__AXI_BVALID__SHIFT                  0x00000017
+#define MH_DEBUG_REG00__AXI_BREADY__SHIFT                  0x00000018
+#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT                0x00000019
+#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT                0x0000001a
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q__SHIFT                   0x00000000
+#define MH_DEBUG_REG01__CP_RTR_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT                  0x00000002
+#define MH_DEBUG_REG01__CP_TAG_q__SHIFT                    0x00000003
+#define MH_DEBUG_REG01__CP_BE_q__SHIFT                     0x00000006
+#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT                  0x0000000e
+#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT                   0x0000000f
+#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT                   0x00000010
+#define MH_DEBUG_REG01__TC_SEND_q__SHIFT                   0x00000011
+#define MH_DEBUG_REG01__TC_RTR_q__SHIFT                    0x00000012
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT               0x00000013
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT                0x00000014
+#define MH_DEBUG_REG01__TC_MH_written__SHIFT               0x00000015
+#define MH_DEBUG_REG01__RB_SEND_q__SHIFT                   0x00000016
+#define MH_DEBUG_REG01__RB_RTR_q__SHIFT                    0x00000017
+#define MH_DEBUG_REG01__RB_BE_q__SHIFT                     0x00000018
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT               0x00000003
+#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT                 0x00000004
+#define MH_DEBUG_REG02__RDC_RID__SHIFT                     0x00000007
+#define MH_DEBUG_REG02__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT            0x0000000c
+#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT            0x0000000d
+#define MH_DEBUG_REG02__BRC_BID__SHIFT                     0x0000000e
+#define MH_DEBUG_REG02__BRC_BRESP__SHIFT                   0x00000011
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT           0x00000000
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT          0x00000000
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG05__CP_MH_write__SHIFT                 0x00000001
+#define MH_DEBUG_REG05__CP_MH_tag__SHIFT                   0x00000002
+#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT               0x00000005
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG08__VGT_MH_send__SHIFT                 0x00000003
+#define MH_DEBUG_REG08__VGT_MH_tagbe__SHIFT                0x00000004
+#define MH_DEBUG_REG08__VGT_MH_ad_31_5__SHIFT              0x00000005
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG09__TC_MH_send__SHIFT                  0x00000002
+#define MH_DEBUG_REG09__TC_MH_mask__SHIFT                  0x00000003
+#define MH_DEBUG_REG09__TC_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__TC_MH_info__SHIFT                  0x00000000
+#define MH_DEBUG_REG10__TC_MH_send__SHIFT                  0x00000019
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__MH_TC_mcinfo__SHIFT                0x00000000
+#define MH_DEBUG_REG11__MH_TC_mcinfo_send__SHIFT           0x00000019
+#define MH_DEBUG_REG11__TC_MH_written__SHIFT               0x0000001a
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG12__TC_ROQ_SEND__SHIFT                 0x00000002
+#define MH_DEBUG_REG12__TC_ROQ_MASK__SHIFT                 0x00000003
+#define MH_DEBUG_REG12__TC_ROQ_ADDR_31_5__SHIFT            0x00000005
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__TC_ROQ_INFO__SHIFT                 0x00000000
+#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT                 0x00000019
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG14__RB_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG14__RB_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__RB_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG17__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG17__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG17__ALEN_q_2_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG17__ARVALID_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG17__ARREADY_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG17__ARID_q__SHIFT                      0x0000000a
+#define MH_DEBUG_REG17__ARLEN_q_1_0__SHIFT                 0x0000000d
+#define MH_DEBUG_REG17__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG17__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG17__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG17__RID_q__SHIFT                       0x00000012
+#define MH_DEBUG_REG17__WVALID_q__SHIFT                    0x00000015
+#define MH_DEBUG_REG17__WREADY_q__SHIFT                    0x00000016
+#define MH_DEBUG_REG17__WLAST_q__SHIFT                     0x00000017
+#define MH_DEBUG_REG17__WID_q__SHIFT                       0x00000018
+#define MH_DEBUG_REG17__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG17__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG17__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG18__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG18__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG18__ALEN_q_1_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG18__ARVALID_q__SHIFT                   0x00000007
+#define MH_DEBUG_REG18__ARREADY_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG18__ARID_q__SHIFT                      0x00000009
+#define MH_DEBUG_REG18__ARLEN_q_1_1__SHIFT                 0x0000000c
+#define MH_DEBUG_REG18__WVALID_q__SHIFT                    0x0000000d
+#define MH_DEBUG_REG18__WREADY_q__SHIFT                    0x0000000e
+#define MH_DEBUG_REG18__WLAST_q__SHIFT                     0x0000000f
+#define MH_DEBUG_REG18__WID_q__SHIFT                       0x00000010
+#define MH_DEBUG_REG18__WSTRB_q__SHIFT                     0x00000013
+#define MH_DEBUG_REG18__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG18__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG18__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__ARC_CTRL_RE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG19__CTRL_ARC_ID__SHIFT                 0x00000001
+#define MH_DEBUG_REG19__CTRL_ARC_PAD__SHIFT                0x00000004
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG20__REG_A__SHIFT                       0x00000002
+#define MH_DEBUG_REG20__REG_RE__SHIFT                      0x00000010
+#define MH_DEBUG_REG20__REG_WE__SHIFT                      0x00000011
+#define MH_DEBUG_REG20__BLOCK_RS__SHIFT                    0x00000012
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__REG_WD__SHIFT                      0x00000000
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__CIB_MH_axi_halt_req__SHIFT         0x00000000
+#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack__SHIFT         0x00000001
+#define MH_DEBUG_REG22__MH_RBBM_busy__SHIFT                0x00000002
+#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int__SHIFT        0x00000003
+#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int__SHIFT       0x00000004
+#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int__SHIFT     0x00000005
+#define MH_DEBUG_REG22__GAT_CLK_ENA__SHIFT                 0x00000006
+#define MH_DEBUG_REG22__AXI_RDY_ENA__SHIFT                 0x00000007
+#define MH_DEBUG_REG22__RBBM_MH_clk_en_override__SHIFT     0x00000008
+#define MH_DEBUG_REG22__CNT_q__SHIFT                       0x00000009
+#define MH_DEBUG_REG22__TCD_EMPTY_q__SHIFT                 0x0000000f
+#define MH_DEBUG_REG22__TC_ROQ_EMPTY__SHIFT                0x00000010
+#define MH_DEBUG_REG22__MH_BUSY_d__SHIFT                   0x00000011
+#define MH_DEBUG_REG22__ANY_CLNT_BUSY__SHIFT               0x00000012
+#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000013
+#define MH_DEBUG_REG22__CP_SEND_q__SHIFT                   0x00000014
+#define MH_DEBUG_REG22__CP_RTR_q__SHIFT                    0x00000015
+#define MH_DEBUG_REG22__VGT_SEND_q__SHIFT                  0x00000016
+#define MH_DEBUG_REG22__VGT_RTR_q__SHIFT                   0x00000017
+#define MH_DEBUG_REG22__TC_ROQ_SEND_q__SHIFT               0x00000018
+#define MH_DEBUG_REG22__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG22__RB_SEND_q__SHIFT                   0x0000001a
+#define MH_DEBUG_REG22__RB_RTR_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG22__RDC_VALID__SHIFT                   0x0000001c
+#define MH_DEBUG_REG22__RDC_RLAST__SHIFT                   0x0000001d
+#define MH_DEBUG_REG22__TLBMISS_VALID__SHIFT               0x0000001e
+#define MH_DEBUG_REG22__BRC_VALID__SHIFT                   0x0000001f
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__EFF2_FP_WINNER__SHIFT              0x00000000
+#define MH_DEBUG_REG23__EFF2_LRU_WINNER_out__SHIFT         0x00000003
+#define MH_DEBUG_REG23__EFF1_WINNER__SHIFT                 0x00000006
+#define MH_DEBUG_REG23__ARB_WINNER__SHIFT                  0x00000009
+#define MH_DEBUG_REG23__ARB_WINNER_q__SHIFT                0x0000000c
+#define MH_DEBUG_REG23__EFF1_WIN__SHIFT                    0x0000000f
+#define MH_DEBUG_REG23__KILL_EFF1__SHIFT                   0x00000010
+#define MH_DEBUG_REG23__ARB_HOLD__SHIFT                    0x00000011
+#define MH_DEBUG_REG23__ARB_RTR_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG23__CP_SEND_QUAL__SHIFT                0x00000013
+#define MH_DEBUG_REG23__VGT_SEND_QUAL__SHIFT               0x00000014
+#define MH_DEBUG_REG23__TC_SEND_QUAL__SHIFT                0x00000015
+#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL__SHIFT           0x00000016
+#define MH_DEBUG_REG23__RB_SEND_QUAL__SHIFT                0x00000017
+#define MH_DEBUG_REG23__ARB_QUAL__SHIFT                    0x00000018
+#define MH_DEBUG_REG23__CP_EFF1_REQ__SHIFT                 0x00000019
+#define MH_DEBUG_REG23__VGT_EFF1_REQ__SHIFT                0x0000001a
+#define MH_DEBUG_REG23__TC_EFF1_REQ__SHIFT                 0x0000001b
+#define MH_DEBUG_REG23__RB_EFF1_REQ__SHIFT                 0x0000001c
+#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK__SHIFT           0x0000001d
+#define MH_DEBUG_REG23__TCD_NEARFULL_q__SHIFT              0x0000001e
+#define MH_DEBUG_REG23__TCHOLD_IP_q__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__EFF1_WINNER__SHIFT                 0x00000000
+#define MH_DEBUG_REG24__ARB_WINNER__SHIFT                  0x00000003
+#define MH_DEBUG_REG24__CP_SEND_QUAL__SHIFT                0x00000006
+#define MH_DEBUG_REG24__VGT_SEND_QUAL__SHIFT               0x00000007
+#define MH_DEBUG_REG24__TC_SEND_QUAL__SHIFT                0x00000008
+#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL__SHIFT           0x00000009
+#define MH_DEBUG_REG24__RB_SEND_QUAL__SHIFT                0x0000000a
+#define MH_DEBUG_REG24__ARB_QUAL__SHIFT                    0x0000000b
+#define MH_DEBUG_REG24__CP_EFF1_REQ__SHIFT                 0x0000000c
+#define MH_DEBUG_REG24__VGT_EFF1_REQ__SHIFT                0x0000000d
+#define MH_DEBUG_REG24__TC_EFF1_REQ__SHIFT                 0x0000000e
+#define MH_DEBUG_REG24__RB_EFF1_REQ__SHIFT                 0x0000000f
+#define MH_DEBUG_REG24__EFF1_WIN__SHIFT                    0x00000010
+#define MH_DEBUG_REG24__KILL_EFF1__SHIFT                   0x00000011
+#define MH_DEBUG_REG24__TCD_NEARFULL_q__SHIFT              0x00000012
+#define MH_DEBUG_REG24__TC_ARB_HOLD__SHIFT                 0x00000013
+#define MH_DEBUG_REG24__ARB_HOLD__SHIFT                    0x00000014
+#define MH_DEBUG_REG24__ARB_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG24__SAME_PAGE_LIMIT_COUNT_q__SHIFT     0x00000016
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__EFF2_LRU_WINNER_out__SHIFT         0x00000000
+#define MH_DEBUG_REG25__ARB_WINNER__SHIFT                  0x00000003
+#define MH_DEBUG_REG25__LEAST_RECENT_INDEX_d__SHIFT        0x00000006
+#define MH_DEBUG_REG25__LEAST_RECENT_d__SHIFT              0x00000009
+#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d__SHIFT       0x0000000c
+#define MH_DEBUG_REG25__ARB_HOLD__SHIFT                    0x0000000d
+#define MH_DEBUG_REG25__ARB_RTR_q__SHIFT                   0x0000000e
+#define MH_DEBUG_REG25__EFF1_WIN__SHIFT                    0x0000000f
+#define MH_DEBUG_REG25__CLNT_REQ__SHIFT                    0x00000010
+#define MH_DEBUG_REG25__RECENT_d_0__SHIFT                  0x00000014
+#define MH_DEBUG_REG25__RECENT_d_1__SHIFT                  0x00000017
+#define MH_DEBUG_REG25__RECENT_d_2__SHIFT                  0x0000001a
+#define MH_DEBUG_REG25__RECENT_d_3__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__TC_ARB_HOLD__SHIFT                 0x00000000
+#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK__SHIFT      0x00000001
+#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK__SHIFT        0x00000002
+#define MH_DEBUG_REG26__TCD_NEARFULL_q__SHIFT              0x00000003
+#define MH_DEBUG_REG26__TCHOLD_IP_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG26__TCHOLD_CNT_q__SHIFT                0x00000005
+#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT            0x00000009
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT               0x0000000a
+#define MH_DEBUG_REG26__TC_MH_written__SHIFT               0x0000000b
+#define MH_DEBUG_REG26__TCD_FULLNESS_CNT_q__SHIFT          0x0000000c
+#define MH_DEBUG_REG26__WBURST_ACTIVE__SHIFT               0x00000013
+#define MH_DEBUG_REG26__WLAST_q__SHIFT                     0x00000014
+#define MH_DEBUG_REG26__WBURST_IP_q__SHIFT                 0x00000015
+#define MH_DEBUG_REG26__WBURST_CNT_q__SHIFT                0x00000016
+#define MH_DEBUG_REG26__CP_SEND_QUAL__SHIFT                0x00000019
+#define MH_DEBUG_REG26__CP_MH_write__SHIFT                 0x0000001a
+#define MH_DEBUG_REG26__RB_SEND_QUAL__SHIFT                0x0000001b
+#define MH_DEBUG_REG26__ARB_WINNER__SHIFT                  0x0000001c
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__RF_ARBITER_CONFIG_q__SHIFT         0x00000000
+#define MH_DEBUG_REG27__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG28__ROQ_MARK_q__SHIFT                  0x00000008
+#define MH_DEBUG_REG28__ROQ_VALID_q__SHIFT                 0x00000010
+#define MH_DEBUG_REG28__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG28__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG28__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG28__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG28__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG28__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG29__ROQ_MARK_d__SHIFT                  0x00000008
+#define MH_DEBUG_REG29__ROQ_VALID_d__SHIFT                 0x00000010
+#define MH_DEBUG_REG29__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG29__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG29__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG29__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG29__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG29__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__SAME_ROW_BANK_WIN__SHIFT           0x00000000
+#define MH_DEBUG_REG30__SAME_ROW_BANK_REQ__SHIFT           0x00000008
+#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_WIN__SHIFT       0x00000010
+#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_REQ__SHIFT       0x00000018
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG31__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG31__ROQ_MARK_q_0__SHIFT                0x00000002
+#define MH_DEBUG_REG31__ROQ_VALID_q_0__SHIFT               0x00000003
+#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0__SHIFT           0x00000004
+#define MH_DEBUG_REG31__ROQ_ADDR_0__SHIFT                  0x00000005
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG32__ROQ_MARK_q_1__SHIFT                0x00000002
+#define MH_DEBUG_REG32__ROQ_VALID_q_1__SHIFT               0x00000003
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1__SHIFT           0x00000004
+#define MH_DEBUG_REG32__ROQ_ADDR_1__SHIFT                  0x00000005
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG33__ROQ_MARK_q_2__SHIFT                0x00000002
+#define MH_DEBUG_REG33__ROQ_VALID_q_2__SHIFT               0x00000003
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2__SHIFT           0x00000004
+#define MH_DEBUG_REG33__ROQ_ADDR_2__SHIFT                  0x00000005
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG34__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG34__ROQ_MARK_q_3__SHIFT                0x00000002
+#define MH_DEBUG_REG34__ROQ_VALID_q_3__SHIFT               0x00000003
+#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3__SHIFT           0x00000004
+#define MH_DEBUG_REG34__ROQ_ADDR_3__SHIFT                  0x00000005
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG35__ROQ_MARK_q_4__SHIFT                0x00000002
+#define MH_DEBUG_REG35__ROQ_VALID_q_4__SHIFT               0x00000003
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4__SHIFT           0x00000004
+#define MH_DEBUG_REG35__ROQ_ADDR_4__SHIFT                  0x00000005
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG36__ROQ_MARK_q_5__SHIFT                0x00000002
+#define MH_DEBUG_REG36__ROQ_VALID_q_5__SHIFT               0x00000003
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5__SHIFT           0x00000004
+#define MH_DEBUG_REG36__ROQ_ADDR_5__SHIFT                  0x00000005
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG37__ROQ_MARK_q_6__SHIFT                0x00000002
+#define MH_DEBUG_REG37__ROQ_VALID_q_6__SHIFT               0x00000003
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6__SHIFT           0x00000004
+#define MH_DEBUG_REG37__ROQ_ADDR_6__SHIFT                  0x00000005
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG38__ROQ_MARK_q_7__SHIFT                0x00000002
+#define MH_DEBUG_REG38__ROQ_VALID_q_7__SHIFT               0x00000003
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7__SHIFT           0x00000004
+#define MH_DEBUG_REG38__ROQ_ADDR_7__SHIFT                  0x00000005
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__ARB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG39__MMU_RTR__SHIFT                     0x00000001
+#define MH_DEBUG_REG39__ARB_ID_q__SHIFT                    0x00000002
+#define MH_DEBUG_REG39__ARB_WRITE_q__SHIFT                 0x00000005
+#define MH_DEBUG_REG39__ARB_BLEN_q__SHIFT                  0x00000006
+#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY__SHIFT              0x00000007
+#define MH_DEBUG_REG39__ARQ_FIFO_CNT_q__SHIFT              0x00000008
+#define MH_DEBUG_REG39__MMU_WE__SHIFT                      0x0000000b
+#define MH_DEBUG_REG39__ARQ_RTR__SHIFT                     0x0000000c
+#define MH_DEBUG_REG39__MMU_ID__SHIFT                      0x0000000d
+#define MH_DEBUG_REG39__MMU_WRITE__SHIFT                   0x00000010
+#define MH_DEBUG_REG39__MMU_BLEN__SHIFT                    0x00000011
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__ARB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG40__ARB_ID_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG40__ARB_VAD_q__SHIFT                   0x00000004
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__MMU_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG41__MMU_ID__SHIFT                      0x00000001
+#define MH_DEBUG_REG41__MMU_PAD__SHIFT                     0x00000004
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__WDB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG42__WDB_RTR_SKID__SHIFT                0x00000001
+#define MH_DEBUG_REG42__ARB_WSTRB_q__SHIFT                 0x00000002
+#define MH_DEBUG_REG42__ARB_WLAST__SHIFT                   0x0000000a
+#define MH_DEBUG_REG42__WDB_CTRL_EMPTY__SHIFT              0x0000000b
+#define MH_DEBUG_REG42__WDB_FIFO_CNT_q__SHIFT              0x0000000c
+#define MH_DEBUG_REG42__WDC_WDB_RE_q__SHIFT                0x00000011
+#define MH_DEBUG_REG42__WDB_WDC_WID__SHIFT                 0x00000012
+#define MH_DEBUG_REG42__WDB_WDC_WLAST__SHIFT               0x00000015
+#define MH_DEBUG_REG42__WDB_WDC_WSTRB__SHIFT               0x00000016
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_WDATA_q_31_0__SHIFT            0x00000000
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WDATA_q_63_32__SHIFT           0x00000000
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__WDB_WDC_WDATA_31_0__SHIFT          0x00000000
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDB_WDC_WDATA_63_32__SHIFT         0x00000000
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__CTRL_ARC_EMPTY__SHIFT              0x00000000
+#define MH_DEBUG_REG47__CTRL_RARC_EMPTY__SHIFT             0x00000001
+#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY__SHIFT              0x00000002
+#define MH_DEBUG_REG47__ARQ_CTRL_WRITE__SHIFT              0x00000003
+#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS__SHIFT            0x00000004
+#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q__SHIFT           0x00000005
+#define MH_DEBUG_REG47__INFLT_LIMIT_q__SHIFT               0x00000006
+#define MH_DEBUG_REG47__INFLT_LIMIT_CNT_q__SHIFT           0x00000007
+#define MH_DEBUG_REG47__ARC_CTRL_RE_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG47__RARC_CTRL_RE_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG47__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG47__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG47__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG47__BVALID_q__SHIFT                    0x00000012
+#define MH_DEBUG_REG47__BREADY_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG48__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG48__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG48__MH_TLBMISS_SEND__SHIFT             0x00000003
+#define MH_DEBUG_REG48__TLBMISS_VALID__SHIFT               0x00000004
+#define MH_DEBUG_REG48__RDC_VALID__SHIFT                   0x00000005
+#define MH_DEBUG_REG48__RDC_RID__SHIFT                     0x00000006
+#define MH_DEBUG_REG48__RDC_RLAST__SHIFT                   0x00000009
+#define MH_DEBUG_REG48__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS__SHIFT            0x0000000c
+#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q__SHIFT           0x0000000d
+#define MH_DEBUG_REG48__MMU_ID_REQUEST_q__SHIFT            0x0000000e
+#define MH_DEBUG_REG48__OUTSTANDING_MMUID_CNT_q__SHIFT     0x0000000f
+#define MH_DEBUG_REG48__MMU_ID_RESPONSE__SHIFT             0x00000015
+#define MH_DEBUG_REG48__TLBMISS_RETURN_CNT_q__SHIFT        0x00000016
+#define MH_DEBUG_REG48__CNT_HOLD_q1__SHIFT                 0x0000001c
+#define MH_DEBUG_REG48__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__RF_MMU_PAGE_FAULT__SHIFT           0x00000000
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__RF_MMU_CONFIG_q__SHIFT             0x00000000
+#define MH_DEBUG_REG50__ARB_ID_q__SHIFT                    0x00000018
+#define MH_DEBUG_REG50__ARB_WRITE_q__SHIFT                 0x0000001b
+#define MH_DEBUG_REG50__client_behavior_q__SHIFT           0x0000001c
+#define MH_DEBUG_REG50__ARB_WE__SHIFT                      0x0000001e
+#define MH_DEBUG_REG50__MMU_RTR__SHIFT                     0x0000001f
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__stage1_valid__SHIFT                0x00000000
+#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q__SHIFT           0x00000001
+#define MH_DEBUG_REG51__pa_in_mpu_range__SHIFT             0x00000002
+#define MH_DEBUG_REG51__tag_match_q__SHIFT                 0x00000003
+#define MH_DEBUG_REG51__tag_miss_q__SHIFT                  0x00000004
+#define MH_DEBUG_REG51__va_in_range_q__SHIFT               0x00000005
+#define MH_DEBUG_REG51__MMU_MISS__SHIFT                    0x00000006
+#define MH_DEBUG_REG51__MMU_READ_MISS__SHIFT               0x00000007
+#define MH_DEBUG_REG51__MMU_WRITE_MISS__SHIFT              0x00000008
+#define MH_DEBUG_REG51__MMU_HIT__SHIFT                     0x00000009
+#define MH_DEBUG_REG51__MMU_READ_HIT__SHIFT                0x0000000a
+#define MH_DEBUG_REG51__MMU_WRITE_HIT__SHIFT               0x0000000b
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS__SHIFT      0x0000000c
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT__SHIFT       0x0000000d
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS__SHIFT   0x0000000e
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT__SHIFT    0x0000000f
+#define MH_DEBUG_REG51__REQ_VA_OFFSET_q__SHIFT             0x00000010
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__ARQ_RTR__SHIFT                     0x00000000
+#define MH_DEBUG_REG52__MMU_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q__SHIFT           0x00000002
+#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS__SHIFT            0x00000003
+#define MH_DEBUG_REG52__MH_TLBMISS_SEND__SHIFT             0x00000004
+#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005
+#define MH_DEBUG_REG52__pa_in_mpu_range__SHIFT             0x00000006
+#define MH_DEBUG_REG52__stage1_valid__SHIFT                0x00000007
+#define MH_DEBUG_REG52__stage2_valid__SHIFT                0x00000008
+#define MH_DEBUG_REG52__client_behavior_q__SHIFT           0x00000009
+#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q__SHIFT           0x0000000b
+#define MH_DEBUG_REG52__tag_match_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG52__tag_miss_q__SHIFT                  0x0000000d
+#define MH_DEBUG_REG52__va_in_range_q__SHIFT               0x0000000e
+#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q__SHIFT        0x0000000f
+#define MH_DEBUG_REG52__TAG_valid_q__SHIFT                 0x00000010
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__TAG0_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG53__TAG_valid_q_0__SHIFT               0x0000000d
+#define MH_DEBUG_REG53__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG53__TAG1_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG53__TAG_valid_q_1__SHIFT               0x0000001d
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__TAG2_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG54__TAG_valid_q_2__SHIFT               0x0000000d
+#define MH_DEBUG_REG54__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG54__TAG3_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG54__TAG_valid_q_3__SHIFT               0x0000001d
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG4_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG55__TAG_valid_q_4__SHIFT               0x0000000d
+#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG55__TAG5_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG55__TAG_valid_q_5__SHIFT               0x0000001d
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG6_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG56__TAG_valid_q_6__SHIFT               0x0000000d
+#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG56__TAG7_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG56__TAG_valid_q_7__SHIFT               0x0000001d
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG8_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG57__TAG_valid_q_8__SHIFT               0x0000000d
+#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG57__TAG9_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG57__TAG_valid_q_9__SHIFT               0x0000001d
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG10_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG58__TAG_valid_q_10__SHIFT              0x0000000d
+#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG58__TAG11_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG58__TAG_valid_q_11__SHIFT              0x0000001d
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG12_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG59__TAG_valid_q_12__SHIFT              0x0000000d
+#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG59__TAG13_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG59__TAG_valid_q_13__SHIFT              0x0000001d
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG14_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG60__TAG_valid_q_14__SHIFT              0x0000000d
+#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG60__TAG15_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG60__TAG_valid_q_15__SHIFT              0x0000001d
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT                   0x00000000
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT            0x00000001
+#define MH_MMU_CONFIG__RESERVED1__SHIFT                    0x00000002
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT           0x00000004
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT           0x00000006
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT          0x00000008
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT          0x0000000a
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT          0x0000000c
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT          0x0000000e
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT          0x00000010
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT         0x00000012
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT         0x00000014
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT           0x00000016
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT           0x00000000
+#define MH_MMU_VA_RANGE__VA_BASE__SHIFT                    0x0000000c
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE__SHIFT                     0x0000000c
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT               0x00000000
+#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT                  0x00000001
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT            0x00000002
+#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT                   0x00000004
+#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT                0x00000007
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT     0x00000009
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT    0x0000000a
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT   0x0000000b
+#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT                   0x0000000c
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT               0x00000005
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT           0x00000000
+#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT            0x00000001
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT                   0x0000000c
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END__SHIFT                     0x0000000c
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT                   0x00000001
+#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT                   0x00000002
+#define WAIT_UNTIL__WAIT_VSYNC__SHIFT                      0x00000003
+#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT                  0x00000004
+#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT                  0x00000005
+#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT                  0x00000006
+#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT                    0x0000000a
+#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT                    0x0000000e
+#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT                    0x0000000f
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT               0x00000010
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT               0x00000011
+#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT                 0x00000014
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT         0x00000004
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT    0x00000005
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT                  0x00000000
+#define RBBM_STATUS__TC_BUSY__SHIFT                        0x00000005
+#define RBBM_STATUS__HIRQ_PENDING__SHIFT                   0x00000008
+#define RBBM_STATUS__CPRQ_PENDING__SHIFT                   0x00000009
+#define RBBM_STATUS__CFRQ_PENDING__SHIFT                   0x0000000a
+#define RBBM_STATUS__PFRQ_PENDING__SHIFT                   0x0000000b
+#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT                0x0000000c
+#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT                   0x0000000e
+#define RBBM_STATUS__CP_NRT_BUSY__SHIFT                    0x00000010
+#define RBBM_STATUS__MH_BUSY__SHIFT                        0x00000012
+#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT              0x00000013
+#define RBBM_STATUS__SX_BUSY__SHIFT                        0x00000015
+#define RBBM_STATUS__TPC_BUSY__SHIFT                       0x00000016
+#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT                   0x00000018
+#define RBBM_STATUS__PA_BUSY__SHIFT                        0x00000019
+#define RBBM_STATUS__VGT_BUSY__SHIFT                       0x0000001a
+#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT                 0x0000001b
+#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT                  0x0000001c
+#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT                   0x0000001e
+#define RBBM_STATUS__GUI_ACTIVE__SHIFT                     0x0000001f
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE__SHIFT              0x00000000
+#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE__SHIFT              0x00000001
+#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE__SHIFT              0x00000002
+#define RBBM_DSPLY__VSYNC_ACTIVE__SHIFT                    0x00000003
+#define RBBM_DSPLY__USE_DISPLAY_ID0__SHIFT                 0x00000004
+#define RBBM_DSPLY__USE_DISPLAY_ID1__SHIFT                 0x00000005
+#define RBBM_DSPLY__USE_DISPLAY_ID2__SHIFT                 0x00000006
+#define RBBM_DSPLY__SW_CNTL__SHIFT                         0x00000007
+#define RBBM_DSPLY__NUM_BUFS__SHIFT                        0x00000008
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__BUFFER_ID__SHIFT               0x00000000
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT                0x00000000
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT          0x00000000
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT         0x00000010
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT             0x00000018
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT             0x00000000
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT                 0x00000000
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT                 0x00000000
+#define RBBM_PERIPHID1__DESIGNER0__SHIFT                   0x00000004
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1__SHIFT                   0x00000000
+#define RBBM_PERIPHID2__REVISION__SHIFT                    0x00000004
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT         0x00000000
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT        0x00000002
+#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT                0x00000004
+#define RBBM_PERIPHID3__CONTINUATION__SHIFT                0x00000007
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT__SHIFT                     0x00000000
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT             0x00000008
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT          0x00000000
+#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT                  0x00000005
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT              0x00000000
+#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT              0x00000002
+#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT              0x00000003
+#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT              0x00000004
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT              0x00000005
+#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT              0x00000006
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT             0x0000000c
+#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT              0x0000000f
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT             0x00000010
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000001
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT      0x00000002
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT  0x00000003
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT   0x00000004
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000005
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT   0x00000008
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT      0x00000009
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT   0x00000014
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000015
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT    0x00000016
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000017
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT     0x00000019
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001a
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT      0x0000001b
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT   0x0000001c
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001d
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT  0x0000001e
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT   0x00000001
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT   0x00000002
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT    0x00000007
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT  0x00000008
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT  0x00000009
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT  0x0000000b
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT              0x00000000
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT           0x0000001f
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT                 0x00000000
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR__SHIFT                      0x00000001
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT              0x00000002
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT           0x00000003
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT           0x00000004
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT       0x00000008
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT               0x00000010
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000011
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT   0x00000012
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000013
+#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT                  0x00000014
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT                 0x00000015
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT                  0x00000016
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT      0x00000017
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT             0x00000018
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT             0x0000001f
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT               0x00000002
+#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT             0x0000001e
+#define RBBM_READ_ERROR__READ_ERROR__SHIFT                 0x0000001f
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT               0x00000000
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT      0x00000001
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT            0x00000013
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT             0x00000000
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT    0x00000001
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT          0x00000013
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT                 0x00000000
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT        0x00000001
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT              0x00000013
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT              0x00000005
+#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT              0x0000001e
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT            0x0000001f
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT   0x00000000
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT        0x00000000
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT        0x00000000
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE__SHIFT                         0x00000005
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT                        0x00000000
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT                        0x00000008
+#define CP_RB_CNTL__BUF_SWAP__SHIFT                        0x00000010
+#define CP_RB_CNTL__RB_POLL_EN__SHIFT                      0x00000014
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT                    0x0000001b
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT                  0x0000001f
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT               0x00000002
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR__SHIFT                         0x00000000
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT                   0x00000000
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR__SHIFT                         0x00000000
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT           0x00000000
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT           0x0000001c
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT               0x00000002
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE__SHIFT                       0x00000002
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT                     0x00000000
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE__SHIFT                       0x00000002
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT                     0x00000000
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE__SHIFT                         0x00000002
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT                       0x00000000
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT          0x00000000
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT          0x00000008
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT           0x00000010
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT                  0x00000010
+#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT                  0x00000018
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT                  0x00000000
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT                   0x00000008
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT                   0x00000010
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT                    0x00000000
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT                       0x00000000
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT            0x00000000
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT            0x00000010
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT         0x00000000
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT         0x00000010
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT         0x00000000
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT         0x00000010
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT          0x00000000
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT          0x00000008
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT                 0x00000000
+#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT                 0x00000010
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT                       0x00000000
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT                       0x00000010
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT                 0x00000000
+#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT                 0x00000001
+#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT                 0x00000002
+#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT                 0x00000003
+#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT                 0x00000004
+#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT                 0x00000005
+#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT                 0x00000006
+#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT                 0x00000007
+#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT                 0x00000008
+#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT                 0x00000009
+#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT                0x0000000a
+#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT                0x0000000b
+#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT                0x0000000c
+#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT                0x0000000d
+#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT                0x0000000e
+#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT                0x0000000f
+#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT                0x00000010
+#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT                0x00000011
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT         0x0000001f
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT                     0x00000000
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT                 0x00000010
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA__SHIFT                       0x00000000
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX__SHIFT                      0x00000000
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT          0x00000019
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT          0x0000001a
+#define CP_ME_CNTL__ME_HALT__SHIFT                         0x0000001c
+#define CP_ME_CNTL__ME_BUSY__SHIFT                         0x0000001d
+#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT                   0x0000001f
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT                 0x00000000
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT                 0x00000000
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR__SHIFT                     0x00000000
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT           0x00000000
+#define CP_DEBUG__PREDICATE_DISABLE__SHIFT                 0x00000017
+#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT               0x00000018
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT           0x00000019
+#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT                0x0000001a
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT               0x0000001b
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT            0x0000001c
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT            0x0000001e
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT            0x0000001f
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT              0x00000000
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT              0x00000000
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT              0x00000000
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT              0x00000000
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT              0x00000000
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT              0x00000000
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT              0x00000000
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT              0x00000000
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT                  0x00000000
+#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT                  0x00000010
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT                  0x00000005
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT             0x00000000
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT              0x00000000
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT              0x00000002
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT              0x00000000
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK__SHIFT                    0x00000013
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT           0x00000017
+#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT              0x00000018
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT      0x00000019
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT        0x0000001a
+#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT                  0x0000001b
+#define CP_INT_CNTL__IB2_INT_MASK__SHIFT                   0x0000001d
+#define CP_INT_CNTL__IB1_INT_MASK__SHIFT                   0x0000001e
+#define CP_INT_CNTL__RB_INT_MASK__SHIFT                    0x0000001f
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT__SHIFT                  0x00000013
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT         0x00000017
+#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT            0x00000018
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT    0x00000019
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT      0x0000001a
+#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT                0x0000001b
+#define CP_INT_STATUS__IB2_INT_STAT__SHIFT                 0x0000001d
+#define CP_INT_STATUS__IB1_INT_STAT__SHIFT                 0x0000001e
+#define CP_INT_STATUS__RB_INT_STAT__SHIFT                  0x0000001f
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK__SHIFT                      0x00000013
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT             0x00000017
+#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT                0x00000018
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT        0x00000019
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT          0x0000001a
+#define CP_INT_ACK__IB_ERROR_ACK__SHIFT                    0x0000001b
+#define CP_INT_ACK__IB2_INT_ACK__SHIFT                     0x0000001d
+#define CP_INT_ACK__IB1_INT_ACK__SHIFT                     0x0000001e
+#define CP_INT_ACK__RB_INT_ACK__SHIFT                      0x0000001f
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT               0x00000000
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT               0x00000000
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT              0x00000000
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT        0x00000008
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT        0x00000000
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT             0x00000000
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT             0x00000000
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT                 0x00000000
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT                 0x00000000
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT             0x00000000
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT             0x00000000
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0__SHIFT                    0x00000000
+#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT                   0x00000001
+#define CP_NV_FLAGS_0__DISCARD_1__SHIFT                    0x00000002
+#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT                   0x00000003
+#define CP_NV_FLAGS_0__DISCARD_2__SHIFT                    0x00000004
+#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT                   0x00000005
+#define CP_NV_FLAGS_0__DISCARD_3__SHIFT                    0x00000006
+#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT                   0x00000007
+#define CP_NV_FLAGS_0__DISCARD_4__SHIFT                    0x00000008
+#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT                   0x00000009
+#define CP_NV_FLAGS_0__DISCARD_5__SHIFT                    0x0000000a
+#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT                   0x0000000b
+#define CP_NV_FLAGS_0__DISCARD_6__SHIFT                    0x0000000c
+#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT                   0x0000000d
+#define CP_NV_FLAGS_0__DISCARD_7__SHIFT                    0x0000000e
+#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT                   0x0000000f
+#define CP_NV_FLAGS_0__DISCARD_8__SHIFT                    0x00000010
+#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT                   0x00000011
+#define CP_NV_FLAGS_0__DISCARD_9__SHIFT                    0x00000012
+#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT                   0x00000013
+#define CP_NV_FLAGS_0__DISCARD_10__SHIFT                   0x00000014
+#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT                  0x00000015
+#define CP_NV_FLAGS_0__DISCARD_11__SHIFT                   0x00000016
+#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT                  0x00000017
+#define CP_NV_FLAGS_0__DISCARD_12__SHIFT                   0x00000018
+#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT                  0x00000019
+#define CP_NV_FLAGS_0__DISCARD_13__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_0__DISCARD_14__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_0__DISCARD_15__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16__SHIFT                   0x00000000
+#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT                  0x00000001
+#define CP_NV_FLAGS_1__DISCARD_17__SHIFT                   0x00000002
+#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT                  0x00000003
+#define CP_NV_FLAGS_1__DISCARD_18__SHIFT                   0x00000004
+#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT                  0x00000005
+#define CP_NV_FLAGS_1__DISCARD_19__SHIFT                   0x00000006
+#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT                  0x00000007
+#define CP_NV_FLAGS_1__DISCARD_20__SHIFT                   0x00000008
+#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT                  0x00000009
+#define CP_NV_FLAGS_1__DISCARD_21__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_1__DISCARD_22__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_1__DISCARD_23__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_1__DISCARD_24__SHIFT                   0x00000010
+#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT                  0x00000011
+#define CP_NV_FLAGS_1__DISCARD_25__SHIFT                   0x00000012
+#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT                  0x00000013
+#define CP_NV_FLAGS_1__DISCARD_26__SHIFT                   0x00000014
+#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT                  0x00000015
+#define CP_NV_FLAGS_1__DISCARD_27__SHIFT                   0x00000016
+#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT                  0x00000017
+#define CP_NV_FLAGS_1__DISCARD_28__SHIFT                   0x00000018
+#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT                  0x00000019
+#define CP_NV_FLAGS_1__DISCARD_29__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_1__DISCARD_30__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_1__DISCARD_31__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32__SHIFT                   0x00000000
+#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT                  0x00000001
+#define CP_NV_FLAGS_2__DISCARD_33__SHIFT                   0x00000002
+#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT                  0x00000003
+#define CP_NV_FLAGS_2__DISCARD_34__SHIFT                   0x00000004
+#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT                  0x00000005
+#define CP_NV_FLAGS_2__DISCARD_35__SHIFT                   0x00000006
+#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT                  0x00000007
+#define CP_NV_FLAGS_2__DISCARD_36__SHIFT                   0x00000008
+#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT                  0x00000009
+#define CP_NV_FLAGS_2__DISCARD_37__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_2__DISCARD_38__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_2__DISCARD_39__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_2__DISCARD_40__SHIFT                   0x00000010
+#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT                  0x00000011
+#define CP_NV_FLAGS_2__DISCARD_41__SHIFT                   0x00000012
+#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT                  0x00000013
+#define CP_NV_FLAGS_2__DISCARD_42__SHIFT                   0x00000014
+#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT                  0x00000015
+#define CP_NV_FLAGS_2__DISCARD_43__SHIFT                   0x00000016
+#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT                  0x00000017
+#define CP_NV_FLAGS_2__DISCARD_44__SHIFT                   0x00000018
+#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT                  0x00000019
+#define CP_NV_FLAGS_2__DISCARD_45__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_2__DISCARD_46__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_2__DISCARD_47__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48__SHIFT                   0x00000000
+#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT                  0x00000001
+#define CP_NV_FLAGS_3__DISCARD_49__SHIFT                   0x00000002
+#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT                  0x00000003
+#define CP_NV_FLAGS_3__DISCARD_50__SHIFT                   0x00000004
+#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT                  0x00000005
+#define CP_NV_FLAGS_3__DISCARD_51__SHIFT                   0x00000006
+#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT                  0x00000007
+#define CP_NV_FLAGS_3__DISCARD_52__SHIFT                   0x00000008
+#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT                  0x00000009
+#define CP_NV_FLAGS_3__DISCARD_53__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_3__DISCARD_54__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_3__DISCARD_55__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_3__DISCARD_56__SHIFT                   0x00000010
+#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT                  0x00000011
+#define CP_NV_FLAGS_3__DISCARD_57__SHIFT                   0x00000012
+#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT                  0x00000013
+#define CP_NV_FLAGS_3__DISCARD_58__SHIFT                   0x00000014
+#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT                  0x00000015
+#define CP_NV_FLAGS_3__DISCARD_59__SHIFT                   0x00000016
+#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT                  0x00000017
+#define CP_NV_FLAGS_3__DISCARD_60__SHIFT                   0x00000018
+#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT                  0x00000019
+#define CP_NV_FLAGS_3__DISCARD_61__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_3__DISCARD_62__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_3__DISCARD_63__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT                  0x0000001f
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT     0x00000000
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT       0x00000000
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER__SHIFT                    0x00000000
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY__SHIFT                        0x00000000
+#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT                    0x00000001
+#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT                 0x00000002
+#define CP_STAT__RBIU_BUSY__SHIFT                          0x00000003
+#define CP_STAT__RCIU_BUSY__SHIFT                          0x00000004
+#define CP_STAT__CSF_RING_BUSY__SHIFT                      0x00000005
+#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT                 0x00000006
+#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT                 0x00000007
+#define CP_STAT__CSF_ST_BUSY__SHIFT                        0x00000009
+#define CP_STAT__CSF_BUSY__SHIFT                           0x0000000a
+#define CP_STAT__RING_QUEUE_BUSY__SHIFT                    0x0000000b
+#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT               0x0000000c
+#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT               0x0000000d
+#define CP_STAT__ST_QUEUE_BUSY__SHIFT                      0x00000010
+#define CP_STAT__PFP_BUSY__SHIFT                           0x00000011
+#define CP_STAT__MEQ_RING_BUSY__SHIFT                      0x00000012
+#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT                 0x00000013
+#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT                 0x00000014
+#define CP_STAT__MIU_WC_STALL__SHIFT                       0x00000015
+#define CP_STAT__CP_NRT_BUSY__SHIFT                        0x00000016
+#define CP_STAT___3D_BUSY__SHIFT                           0x00000017
+#define CP_STAT__ME_BUSY__SHIFT                            0x0000001a
+#define CP_STAT__ME_WC_BUSY__SHIFT                         0x0000001d
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT            0x0000001e
+#define CP_STAT__CP_BUSY__SHIFT                            0x0000001f
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE__SHIFT                        0x00000000
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE__SHIFT                        0x00000000
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT         0x00000000
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT     0x00000008
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT           0x00000009
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT           0x0000000a
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT           0x0000000b
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT           0x0000000c
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT           0x0000000d
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT           0x0000000e
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT           0x0000000f
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT           0x00000010
+#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT             0x00000019
+#define COHER_STATUS_PM4__STATUS__SHIFT                    0x0000001f
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE__SHIFT                       0x00000000
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE__SHIFT                       0x00000000
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT        0x00000000
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT    0x00000008
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT          0x00000009
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT          0x0000000a
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT          0x0000000b
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT          0x0000000c
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT          0x0000000d
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT          0x0000000e
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT          0x0000000f
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT          0x00000010
+#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT            0x00000019
+#define COHER_STATUS_HOST__STATUS__SHIFT                   0x0000001f
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT              0x0000000c
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT              0x00000000
+#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT               0x0000000e
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT                 0x00000000
+#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT             0x00000004
+#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT                 0x00000006
+#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT                 0x00000007
+#define RB_COLOR_INFO__COLOR_SWAP__SHIFT                   0x00000009
+#define RB_COLOR_INFO__COLOR_BASE__SHIFT                   0x0000000c
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT                 0x00000000
+#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT                   0x0000000c
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF__SHIFT               0x00000000
+#define RB_STENCILREFMASK__STENCILMASK__SHIFT              0x00000008
+#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT         0x00000010
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF__SHIFT                     0x00000000
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED__SHIFT                    0x00000000
+#define RB_COLOR_MASK__WRITE_GREEN__SHIFT                  0x00000001
+#define RB_COLOR_MASK__WRITE_BLUE__SHIFT                   0x00000002
+#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT                  0x00000003
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED__SHIFT                     0x00000000
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT                 0x00000000
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT                   0x00000000
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT                 0x00000000
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED__SHIFT                       0x00000000
+#define RB_FOG_COLOR__FOG_GREEN__SHIFT                     0x00000008
+#define RB_FOG_COLOR__FOG_BLUE__SHIFT                      0x00000010
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT         0x00000000
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT        0x00000008
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT   0x00000010
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT             0x00000000
+#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT                   0x00000001
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT             0x00000002
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT             0x00000003
+#define RB_DEPTHCONTROL__ZFUNC__SHIFT                      0x00000004
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT            0x00000007
+#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT                0x00000008
+#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT                0x0000000b
+#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT               0x0000000e
+#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT               0x00000011
+#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT             0x00000014
+#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT             0x00000017
+#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT            0x0000001a
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT            0x0000001d
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT             0x00000000
+#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT             0x00000005
+#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT            0x00000008
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT             0x00000010
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT             0x00000015
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT            0x00000018
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT         0x0000001d
+#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT                0x0000001e
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT                 0x00000000
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT          0x00000003
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT       0x00000004
+#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT              0x00000005
+#define RB_COLORCONTROL__FOG_ENABLE__SHIFT                 0x00000006
+#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT             0x00000007
+#define RB_COLORCONTROL__ROP_CODE__SHIFT                   0x00000008
+#define RB_COLORCONTROL__DITHER_MODE__SHIFT                0x0000000c
+#define RB_COLORCONTROL__DITHER_TYPE__SHIFT                0x0000000e
+#define RB_COLORCONTROL__PIXEL_FOG__SHIFT                  0x00000010
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT      0x00000018
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT      0x0000001a
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT      0x0000001c
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT      0x0000001e
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE__SHIFT                  0x00000000
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT         0x00000000
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT         0x00000000
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT         0x00000003
+#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT                 0x00000004
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT           0x0000000c
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT         0x00000000
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT         0x00000000
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT         0x00000003
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT         0x00000004
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT           0x00000008
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT    0x0000000a
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT    0x0000000c
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT      0x0000000e
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT    0x0000000f
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT     0x00000010
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT    0x00000011
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT         0x00000000
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT         0x0000000d
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT                 0x00000000
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT     0x00000000
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT      0x00000001
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT     0x00000000
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT     0x00000000
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT         0x00000001
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT            0x00000003
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT    0x00000005
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT    0x00000006
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT           0x00000007
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT            0x00000008
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT            0x0000000e
+#define RB_BC_CONTROL__CRC_MODE__SHIFT                     0x0000000f
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT      0x00000010
+#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT                0x00000011
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT             0x00000012
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT    0x00000016
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT        0x00000017
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT    0x0000001b
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d
+#define RB_BC_CONTROL__RESERVED9__SHIFT                    0x0000001e
+#define RB_BC_CONTROL__RESERVED10__SHIFT                   0x0000001f
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT                   0x00000000
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT           0x00000004
+#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT                  0x0000000e
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA__SHIFT                    0x00000000
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT              0x00000000
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK__SHIFT                       0x00000000
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT             0x00000000
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT             0x00000000
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT           0x00000000
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT           0x00000001
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT           0x00000002
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT           0x00000003
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT          0x00000004
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT          0x00000005
+#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT                   0x00000006
+#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT                   0x00000007
+#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT                   0x00000008
+#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT                   0x00000009
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT          0x0000000a
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT          0x0000000b
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT          0x0000000c
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT          0x0000000d
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT              0x0000000e
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT                   0x00000010
+#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT                   0x00000011
+#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT                   0x00000012
+#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT                   0x00000013
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT            0x00000014
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT            0x00000015
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT            0x00000016
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT            0x00000017
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT         0x00000018
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT         0x00000019
+#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT                   0x0000001a
+#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT                   0x0000001b
+#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT                  0x0000001c
+#define RB_DEBUG_0__C_REQ_FULL__SHIFT                      0x0000001d
+#define RB_DEBUG_0__C_MASK_FULL__SHIFT                     0x0000001e
+#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT                 0x0000001f
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT              0x00000000
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT              0x00000001
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT              0x00000002
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT              0x00000003
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT         0x00000004
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT         0x00000005
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT                  0x00000006
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT                  0x00000007
+#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT                  0x00000008
+#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT                  0x00000009
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT         0x0000000a
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT         0x0000000b
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT         0x0000000c
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT         0x0000000d
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT             0x0000000e
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT             0x0000000f
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT                  0x00000010
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT                  0x00000011
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT              0x00000012
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT              0x00000013
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT           0x00000014
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT           0x00000017
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT        0x00000018
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT        0x00000019
+#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT                  0x0000001a
+#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT                  0x0000001b
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT                 0x0000001c
+#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT                     0x0000001d
+#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT                0x0000001f
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT                 0x00000000
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT               0x00000004
+#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT                 0x0000000b
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT               0x0000000c
+#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT              0x0000000d
+#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT                 0x0000000e
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT              0x00000010
+#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT                    0x00000011
+#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT                    0x00000012
+#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT                     0x00000013
+#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT                     0x00000014
+#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT                     0x00000015
+#define RB_DEBUG_2__Z_TILE_FULL__SHIFT                     0x00000016
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT                0x00000017
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT             0x00000018
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT             0x00000019
+#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT                   0x0000001a
+#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT                   0x0000001b
+#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT                    0x0000001c
+#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT                    0x0000001d
+#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT                    0x0000001f
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID__SHIFT                     0x00000000
+#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT                  0x00000004
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT         0x00000008
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT           0x0000000e
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT             0x0000000f
+#define RB_DEBUG_3__SHD_FULL__SHIFT                        0x00000013
+#define RB_DEBUG_3__SHD_EMPTY__SHIFT                       0x00000014
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT            0x00000017
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT            0x00000018
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT                0x00000019
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT                0x0000001a
+#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT                 0x0000001b
+#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT                 0x0000001c
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT             0x00000000
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT             0x00000001
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT           0x00000002
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT           0x00000003
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT           0x00000004
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT          0x00000005
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT            0x00000006
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT           0x00000007
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT     0x00000008
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT             0x00000009
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT           0x00000000
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT   0x00000009
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h
new file mode 100644
index 000000000000..80b9106759e3
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h
@@ -0,0 +1,51301 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_CP_FIDDLE_H)
+#define _CP_FIDDLE_H
+
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * CP_RB_BASE struct
+ */
+
+#define CP_RB_BASE_RB_BASE_SIZE        27
+
+#define CP_RB_BASE_RB_BASE_SHIFT       5
+
+#define CP_RB_BASE_RB_BASE_MASK        0xffffffe0
+
+#define CP_RB_BASE_MASK \
+     (CP_RB_BASE_RB_BASE_MASK)
+
+#define CP_RB_BASE(rb_base) \
+     ((rb_base << CP_RB_BASE_RB_BASE_SHIFT))
+
+#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \
+     ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT)
+
+#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \
+     cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int                                : 5;
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+     } cp_rb_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+          unsigned int                                : 5;
+     } cp_rb_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_base_t f;
+} cp_rb_base_u;
+
+
+/*
+ * CP_RB_CNTL struct
+ */
+
+#define CP_RB_CNTL_RB_BUFSZ_SIZE       6
+#define CP_RB_CNTL_RB_BLKSZ_SIZE       6
+#define CP_RB_CNTL_BUF_SWAP_SIZE       2
+#define CP_RB_CNTL_RB_POLL_EN_SIZE     1
+#define CP_RB_CNTL_RB_NO_UPDATE_SIZE   1
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1
+
+#define CP_RB_CNTL_RB_BUFSZ_SHIFT      0
+#define CP_RB_CNTL_RB_BLKSZ_SHIFT      8
+#define CP_RB_CNTL_BUF_SWAP_SHIFT      16
+#define CP_RB_CNTL_RB_POLL_EN_SHIFT    20
+#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT  27
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31
+
+#define CP_RB_CNTL_RB_BUFSZ_MASK       0x0000003f
+#define CP_RB_CNTL_RB_BLKSZ_MASK       0x00003f00
+#define CP_RB_CNTL_BUF_SWAP_MASK       0x00030000
+#define CP_RB_CNTL_RB_POLL_EN_MASK     0x00100000
+#define CP_RB_CNTL_RB_NO_UPDATE_MASK   0x08000000
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000
+
+#define CP_RB_CNTL_MASK \
+     (CP_RB_CNTL_RB_BUFSZ_MASK | \
+      CP_RB_CNTL_RB_BLKSZ_MASK | \
+      CP_RB_CNTL_BUF_SWAP_MASK | \
+      CP_RB_CNTL_RB_POLL_EN_MASK | \
+      CP_RB_CNTL_RB_NO_UPDATE_MASK | \
+      CP_RB_CNTL_RB_RPTR_WR_ENA_MASK)
+
+#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \
+     ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \
+      (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \
+      (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \
+      (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \
+      (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \
+      (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT))
+
+#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+     } cp_rb_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+     } cp_rb_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_cntl_t f;
+} cp_rb_cntl_u;
+
+
+/*
+ * CP_RB_RPTR_ADDR struct
+ */
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc
+
+#define CP_RB_RPTR_ADDR_MASK \
+     (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \
+      CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK)
+
+#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \
+     ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \
+      (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT))
+
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_addr_t f;
+} cp_rb_rptr_addr_u;
+
+
+/*
+ * CP_RB_RPTR struct
+ */
+
+#define CP_RB_RPTR_RB_RPTR_SIZE        20
+
+#define CP_RB_RPTR_RB_RPTR_SHIFT       0
+
+#define CP_RB_RPTR_RB_RPTR_MASK        0x000fffff
+
+#define CP_RB_RPTR_MASK \
+     (CP_RB_RPTR_RB_RPTR_MASK)
+
+#define CP_RB_RPTR(rb_rptr) \
+     ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT))
+
+#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \
+     ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \
+     cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+     } cp_rb_rptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_t f;
+} cp_rb_rptr_u;
+
+
+/*
+ * CP_RB_RPTR_WR struct
+ */
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE  20
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK  0x000fffff
+
+#define CP_RB_RPTR_WR_MASK \
+     (CP_RB_RPTR_WR_RB_RPTR_WR_MASK)
+
+#define CP_RB_RPTR_WR(rb_rptr_wr) \
+     ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT))
+
+#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \
+     ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \
+     cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_wr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+     } cp_rb_rptr_wr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_wr_t f;
+} cp_rb_rptr_wr_u;
+
+
+/*
+ * CP_RB_WPTR struct
+ */
+
+#define CP_RB_WPTR_RB_WPTR_SIZE        20
+
+#define CP_RB_WPTR_RB_WPTR_SHIFT       0
+
+#define CP_RB_WPTR_RB_WPTR_MASK        0x000fffff
+
+#define CP_RB_WPTR_MASK \
+     (CP_RB_WPTR_RB_WPTR_MASK)
+
+#define CP_RB_WPTR(rb_wptr) \
+     ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT))
+
+#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \
+     ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \
+     cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_wptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+     } cp_rb_wptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_t f;
+} cp_rb_wptr_u;
+
+
+/*
+ * CP_RB_WPTR_DELAY struct
+ */
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000
+
+#define CP_RB_WPTR_DELAY_MASK \
+     (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \
+      CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK)
+
+#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \
+     ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \
+      (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT))
+
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_delay_t f;
+} cp_rb_wptr_delay_u;
+
+
+/*
+ * CP_RB_WPTR_BASE struct
+ */
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc
+
+#define CP_RB_WPTR_BASE_MASK \
+     (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \
+      CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK)
+
+#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \
+     ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \
+      (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT))
+
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+     } cp_rb_wptr_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+     } cp_rb_wptr_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_base_t f;
+} cp_rb_wptr_base_u;
+
+
+/*
+ * CP_IB1_BASE struct
+ */
+
+#define CP_IB1_BASE_IB1_BASE_SIZE      30
+
+#define CP_IB1_BASE_IB1_BASE_SHIFT     2
+
+#define CP_IB1_BASE_IB1_BASE_MASK      0xfffffffc
+
+#define CP_IB1_BASE_MASK \
+     (CP_IB1_BASE_IB1_BASE_MASK)
+
+#define CP_IB1_BASE(ib1_base) \
+     ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT))
+
+#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \
+     ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \
+     cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int                                : 2;
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+     } cp_ib1_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib1_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_base_t f;
+} cp_ib1_base_u;
+
+
+/*
+ * CP_IB1_BUFSZ struct
+ */
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE    20
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT   0
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK    0x000fffff
+
+#define CP_IB1_BUFSZ_MASK \
+     (CP_IB1_BUFSZ_IB1_BUFSZ_MASK)
+
+#define CP_IB1_BUFSZ(ib1_bufsz) \
+     ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT))
+
+#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \
+     ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \
+     cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib1_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+     } cp_ib1_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_bufsz_t f;
+} cp_ib1_bufsz_u;
+
+
+/*
+ * CP_IB2_BASE struct
+ */
+
+#define CP_IB2_BASE_IB2_BASE_SIZE      30
+
+#define CP_IB2_BASE_IB2_BASE_SHIFT     2
+
+#define CP_IB2_BASE_IB2_BASE_MASK      0xfffffffc
+
+#define CP_IB2_BASE_MASK \
+     (CP_IB2_BASE_IB2_BASE_MASK)
+
+#define CP_IB2_BASE(ib2_base) \
+     ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT))
+
+#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \
+     ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \
+     cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int                                : 2;
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+     } cp_ib2_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib2_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_base_t f;
+} cp_ib2_base_u;
+
+
+/*
+ * CP_IB2_BUFSZ struct
+ */
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE    20
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT   0
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK    0x000fffff
+
+#define CP_IB2_BUFSZ_MASK \
+     (CP_IB2_BUFSZ_IB2_BUFSZ_MASK)
+
+#define CP_IB2_BUFSZ(ib2_bufsz) \
+     ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT))
+
+#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \
+     ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \
+     cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib2_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+     } cp_ib2_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_bufsz_t f;
+} cp_ib2_bufsz_u;
+
+
+/*
+ * CP_ST_BASE struct
+ */
+
+#define CP_ST_BASE_ST_BASE_SIZE        30
+
+#define CP_ST_BASE_ST_BASE_SHIFT       2
+
+#define CP_ST_BASE_ST_BASE_MASK        0xfffffffc
+
+#define CP_ST_BASE_MASK \
+     (CP_ST_BASE_ST_BASE_MASK)
+
+#define CP_ST_BASE(st_base) \
+     ((st_base << CP_ST_BASE_ST_BASE_SHIFT))
+
+#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \
+     ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT)
+
+#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \
+     cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int                                : 2;
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+     } cp_st_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_st_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_base_t f;
+} cp_st_base_u;
+
+
+/*
+ * CP_ST_BUFSZ struct
+ */
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SIZE      20
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT     0
+
+#define CP_ST_BUFSZ_ST_BUFSZ_MASK      0x000fffff
+
+#define CP_ST_BUFSZ_MASK \
+     (CP_ST_BUFSZ_ST_BUFSZ_MASK)
+
+#define CP_ST_BUFSZ(st_bufsz) \
+     ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT))
+
+#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \
+     ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \
+     cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_st_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+     } cp_st_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_bufsz_t f;
+} cp_st_bufsz_u;
+
+
+/*
+ * CP_QUEUE_THRESHOLDS struct
+ */
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000
+
+#define CP_QUEUE_THRESHOLDS_MASK \
+     (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK)
+
+#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \
+     ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \
+      (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \
+      (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT))
+
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 12;
+     } cp_queue_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int                                : 12;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+     } cp_queue_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_queue_thresholds_t f;
+} cp_queue_thresholds_u;
+
+
+/*
+ * CP_MEQ_THRESHOLDS struct
+ */
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5
+#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16
+#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000
+#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000
+
+#define CP_MEQ_THRESHOLDS_MASK \
+     (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \
+      CP_MEQ_THRESHOLDS_ROQ_END_MASK)
+
+#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \
+     ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \
+      (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT))
+
+#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 16;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+     } cp_meq_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 16;
+     } cp_meq_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_thresholds_t f;
+} cp_meq_thresholds_u;
+
+
+/*
+ * CP_CSQ_AVAIL struct
+ */
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE  7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE  7
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK  0x00007f00
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK  0x007f0000
+
+#define CP_CSQ_AVAIL_MASK \
+     (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK)
+
+#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \
+     ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \
+      (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \
+      (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT))
+
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int                                : 9;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+     } cp_csq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_avail_t f;
+} cp_csq_avail_u;
+
+
+/*
+ * CP_STQ_AVAIL struct
+ */
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE   7
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT  0
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_MASK   0x0000007f
+
+#define CP_STQ_AVAIL_MASK \
+     (CP_STQ_AVAIL_STQ_CNT_ST_MASK)
+
+#define CP_STQ_AVAIL(stq_cnt_st) \
+     ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT))
+
+#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \
+     ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \
+     cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+          unsigned int                                : 25;
+     } cp_stq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int                                : 25;
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+     } cp_stq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_avail_t f;
+} cp_stq_avail_u;
+
+
+/*
+ * CP_MEQ_AVAIL struct
+ */
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SIZE      5
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT     0
+
+#define CP_MEQ_AVAIL_MEQ_CNT_MASK      0x0000001f
+
+#define CP_MEQ_AVAIL_MASK \
+     (CP_MEQ_AVAIL_MEQ_CNT_MASK)
+
+#define CP_MEQ_AVAIL(meq_cnt) \
+     ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT))
+
+#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \
+     ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \
+     cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+          unsigned int                                : 27;
+     } cp_meq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int                                : 27;
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+     } cp_meq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_avail_t f;
+} cp_meq_avail_u;
+
+
+/*
+ * CP_CSQ_RB_STAT struct
+ */
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000
+
+#define CP_CSQ_RB_STAT_MASK \
+     (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \
+      CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK)
+
+#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \
+     ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \
+      (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT))
+
+#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_rb_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+     } cp_csq_rb_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_rb_stat_t f;
+} cp_csq_rb_stat_u;
+
+
+/*
+ * CP_CSQ_IB1_STAT struct
+ */
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000
+
+#define CP_CSQ_IB1_STAT_MASK \
+     (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \
+      CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK)
+
+#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \
+     ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \
+      (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT))
+
+#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib1_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+     } cp_csq_ib1_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib1_stat_t f;
+} cp_csq_ib1_stat_u;
+
+
+/*
+ * CP_CSQ_IB2_STAT struct
+ */
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000
+
+#define CP_CSQ_IB2_STAT_MASK \
+     (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \
+      CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK)
+
+#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \
+     ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \
+      (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT))
+
+#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib2_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+     } cp_csq_ib2_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib2_stat_t f;
+} cp_csq_ib2_stat_u;
+
+
+/*
+ * CP_NON_PREFETCH_CNTRS struct
+ */
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700
+
+#define CP_NON_PREFETCH_CNTRS_MASK \
+     (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \
+      CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK)
+
+#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \
+     ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \
+      (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT))
+
+#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 21;
+     } cp_non_prefetch_cntrs_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int                                : 21;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+     } cp_non_prefetch_cntrs_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_non_prefetch_cntrs_t f;
+} cp_non_prefetch_cntrs_u;
+
+
+/*
+ * CP_STQ_ST_STAT struct
+ */
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000
+
+#define CP_STQ_ST_STAT_MASK \
+     (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \
+      CP_STQ_ST_STAT_STQ_WPTR_ST_MASK)
+
+#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \
+     ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \
+      (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT))
+
+#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+     } cp_stq_st_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+     } cp_stq_st_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_st_stat_t f;
+} cp_stq_st_stat_u;
+
+
+/*
+ * CP_MEQ_STAT struct
+ */
+
+#define CP_MEQ_STAT_MEQ_RPTR_SIZE      10
+#define CP_MEQ_STAT_MEQ_WPTR_SIZE      10
+
+#define CP_MEQ_STAT_MEQ_RPTR_SHIFT     0
+#define CP_MEQ_STAT_MEQ_WPTR_SHIFT     16
+
+#define CP_MEQ_STAT_MEQ_RPTR_MASK      0x000003ff
+#define CP_MEQ_STAT_MEQ_WPTR_MASK      0x03ff0000
+
+#define CP_MEQ_STAT_MASK \
+     (CP_MEQ_STAT_MEQ_RPTR_MASK | \
+      CP_MEQ_STAT_MEQ_WPTR_MASK)
+
+#define CP_MEQ_STAT(meq_rptr, meq_wptr) \
+     ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \
+      (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT))
+
+#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+     } cp_meq_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+     } cp_meq_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_stat_t f;
+} cp_meq_stat_u;
+
+
+/*
+ * CP_MIU_TAG_STAT struct
+ */
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001
+#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002
+#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004
+#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008
+#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010
+#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020
+#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040
+#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080
+#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100
+#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200
+#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400
+#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800
+#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000
+#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000
+#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000
+#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000
+#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000
+#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000
+
+#define CP_MIU_TAG_STAT_MASK \
+     (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \
+      CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK)
+
+#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \
+     ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \
+      (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \
+      (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \
+      (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \
+      (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \
+      (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \
+      (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \
+      (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \
+      (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \
+      (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \
+      (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \
+      (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \
+      (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \
+      (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \
+      (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \
+      (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \
+      (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \
+      (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \
+      (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT))
+
+#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int                                : 13;
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+     } cp_miu_tag_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+          unsigned int                                : 13;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+     } cp_miu_tag_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_miu_tag_stat_t f;
+} cp_miu_tag_stat_u;
+
+
+/*
+ * CP_CMD_INDEX struct
+ */
+
+#define CP_CMD_INDEX_CMD_INDEX_SIZE    7
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2
+
+#define CP_CMD_INDEX_CMD_INDEX_SHIFT   0
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16
+
+#define CP_CMD_INDEX_CMD_INDEX_MASK    0x0000007f
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000
+
+#define CP_CMD_INDEX_MASK \
+     (CP_CMD_INDEX_CMD_INDEX_MASK | \
+      CP_CMD_INDEX_CMD_QUEUE_SEL_MASK)
+
+#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \
+     ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \
+      (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT))
+
+#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 14;
+     } cp_cmd_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int                                : 14;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+     } cp_cmd_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_index_t f;
+} cp_cmd_index_u;
+
+
+/*
+ * CP_CMD_DATA struct
+ */
+
+#define CP_CMD_DATA_CMD_DATA_SIZE      32
+
+#define CP_CMD_DATA_CMD_DATA_SHIFT     0
+
+#define CP_CMD_DATA_CMD_DATA_MASK      0xffffffff
+
+#define CP_CMD_DATA_MASK \
+     (CP_CMD_DATA_CMD_DATA_MASK)
+
+#define CP_CMD_DATA(cmd_data) \
+     ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT))
+
+#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \
+     ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \
+     cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_data_t f;
+} cp_cmd_data_u;
+
+
+/*
+ * CP_ME_CNTL struct
+ */
+
+#define CP_ME_CNTL_ME_STATMUX_SIZE     16
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_ME_HALT_SIZE        1
+#define CP_ME_CNTL_ME_BUSY_SIZE        1
+#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE  1
+
+#define CP_ME_CNTL_ME_STATMUX_SHIFT    0
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26
+#define CP_ME_CNTL_ME_HALT_SHIFT       28
+#define CP_ME_CNTL_ME_BUSY_SHIFT       29
+#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31
+
+#define CP_ME_CNTL_ME_STATMUX_MASK     0x0000ffff
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000
+#define CP_ME_CNTL_ME_HALT_MASK        0x10000000
+#define CP_ME_CNTL_ME_BUSY_MASK        0x20000000
+#define CP_ME_CNTL_PROG_CNT_SIZE_MASK  0x80000000
+
+#define CP_ME_CNTL_MASK \
+     (CP_ME_CNTL_ME_STATMUX_MASK | \
+      CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_ME_HALT_MASK | \
+      CP_ME_CNTL_ME_BUSY_MASK | \
+      CP_ME_CNTL_PROG_CNT_SIZE_MASK)
+
+#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \
+     ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \
+      (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \
+      (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \
+      (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT))
+
+#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+          unsigned int                                : 9;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+     } cp_me_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 9;
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+     } cp_me_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cntl_t f;
+} cp_me_cntl_u;
+
+
+/*
+ * CP_ME_STATUS struct
+ */
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_ME_STATUS_MASK \
+     (CP_ME_STATUS_ME_DEBUG_DATA_MASK)
+
+#define CP_ME_STATUS(me_debug_data) \
+     ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT))
+
+#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \
+     ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \
+     cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_status_t f;
+} cp_me_status_u;
+
+
+/*
+ * CP_ME_RAM_WADDR struct
+ */
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_WADDR_MASK \
+     (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK)
+
+#define CP_ME_RAM_WADDR(me_ram_waddr) \
+     ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT))
+
+#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \
+     ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \
+     cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_waddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+     } cp_me_ram_waddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_waddr_t f;
+} cp_me_ram_waddr_u;
+
+
+/*
+ * CP_ME_RAM_RADDR struct
+ */
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_RADDR_MASK \
+     (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK)
+
+#define CP_ME_RAM_RADDR(me_ram_raddr) \
+     ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT))
+
+#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \
+     ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \
+     cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_raddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+     } cp_me_ram_raddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_raddr_t f;
+} cp_me_ram_raddr_u;
+
+
+/*
+ * CP_ME_RAM_DATA struct
+ */
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff
+
+#define CP_ME_RAM_DATA_MASK \
+     (CP_ME_RAM_DATA_ME_RAM_DATA_MASK)
+
+#define CP_ME_RAM_DATA(me_ram_data) \
+     ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT))
+
+#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \
+     ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \
+     cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_data_t f;
+} cp_me_ram_data_u;
+
+
+/*
+ * CP_ME_RDADDR struct
+ */
+
+#define CP_ME_RDADDR_ME_RDADDR_SIZE    32
+
+#define CP_ME_RDADDR_ME_RDADDR_SHIFT   0
+
+#define CP_ME_RDADDR_ME_RDADDR_MASK    0xffffffff
+
+#define CP_ME_RDADDR_MASK \
+     (CP_ME_RDADDR_ME_RDADDR_MASK)
+
+#define CP_ME_RDADDR(me_rdaddr) \
+     ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT))
+
+#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \
+     ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \
+     cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_rdaddr_t f;
+} cp_me_rdaddr_u;
+
+
+/*
+ * CP_DEBUG struct
+ */
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23
+#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0
+#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff
+#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000
+#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000
+#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000
+
+#define CP_DEBUG_MASK \
+     (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \
+      CP_DEBUG_PREDICATE_DISABLE_MASK | \
+      CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \
+      CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \
+      CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \
+      CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \
+      CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \
+      CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \
+      CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK)
+
+#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \
+     ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \
+      (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \
+      (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \
+      (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \
+      (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \
+      (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \
+      (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \
+      (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \
+      (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT))
+
+#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \
+     ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \
+     ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+     } cp_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+     } cp_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_debug_t f;
+} cp_debug_u;
+
+
+/*
+ * SCRATCH_REG0 struct
+ */
+
+#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32
+
+#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0
+
+#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff
+
+#define SCRATCH_REG0_MASK \
+     (SCRATCH_REG0_SCRATCH_REG0_MASK)
+
+#define SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT))
+
+#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \
+     scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg0_t f;
+} scratch_reg0_u;
+
+
+/*
+ * SCRATCH_REG1 struct
+ */
+
+#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32
+
+#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0
+
+#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff
+
+#define SCRATCH_REG1_MASK \
+     (SCRATCH_REG1_SCRATCH_REG1_MASK)
+
+#define SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT))
+
+#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \
+     scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg1_t f;
+} scratch_reg1_u;
+
+
+/*
+ * SCRATCH_REG2 struct
+ */
+
+#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32
+
+#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0
+
+#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff
+
+#define SCRATCH_REG2_MASK \
+     (SCRATCH_REG2_SCRATCH_REG2_MASK)
+
+#define SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT))
+
+#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \
+     scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg2_t f;
+} scratch_reg2_u;
+
+
+/*
+ * SCRATCH_REG3 struct
+ */
+
+#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32
+
+#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0
+
+#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff
+
+#define SCRATCH_REG3_MASK \
+     (SCRATCH_REG3_SCRATCH_REG3_MASK)
+
+#define SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT))
+
+#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \
+     scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg3_t f;
+} scratch_reg3_u;
+
+
+/*
+ * SCRATCH_REG4 struct
+ */
+
+#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32
+
+#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0
+
+#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff
+
+#define SCRATCH_REG4_MASK \
+     (SCRATCH_REG4_SCRATCH_REG4_MASK)
+
+#define SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT))
+
+#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \
+     scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg4_t f;
+} scratch_reg4_u;
+
+
+/*
+ * SCRATCH_REG5 struct
+ */
+
+#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32
+
+#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0
+
+#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff
+
+#define SCRATCH_REG5_MASK \
+     (SCRATCH_REG5_SCRATCH_REG5_MASK)
+
+#define SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT))
+
+#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \
+     scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg5_t f;
+} scratch_reg5_u;
+
+
+/*
+ * SCRATCH_REG6 struct
+ */
+
+#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32
+
+#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0
+
+#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff
+
+#define SCRATCH_REG6_MASK \
+     (SCRATCH_REG6_SCRATCH_REG6_MASK)
+
+#define SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT))
+
+#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \
+     scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg6_t f;
+} scratch_reg6_u;
+
+
+/*
+ * SCRATCH_REG7 struct
+ */
+
+#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32
+
+#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0
+
+#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff
+
+#define SCRATCH_REG7_MASK \
+     (SCRATCH_REG7_SCRATCH_REG7_MASK)
+
+#define SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT))
+
+#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \
+     scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg7_t f;
+} scratch_reg7_u;
+
+
+/*
+ * SCRATCH_UMSK struct
+ */
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8
+#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0
+#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff
+#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000
+
+#define SCRATCH_UMSK_MASK \
+     (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \
+      SCRATCH_UMSK_SCRATCH_SWAP_MASK)
+
+#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \
+     ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \
+      (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT))
+
+#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 14;
+     } scratch_umsk_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int                                : 14;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+     } scratch_umsk_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_umsk_t f;
+} scratch_umsk_u;
+
+
+/*
+ * SCRATCH_ADDR struct
+ */
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0
+
+#define SCRATCH_ADDR_MASK \
+     (SCRATCH_ADDR_SCRATCH_ADDR_MASK)
+
+#define SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT))
+
+#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \
+     scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int                                : 5;
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+     } scratch_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+          unsigned int                                : 5;
+     } scratch_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_addr_t f;
+} scratch_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_SRC struct
+ */
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_VS_EVENT_SRC_MASK \
+     (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \
+      CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK)
+
+#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \
+     ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \
+      (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_vs_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int                                : 30;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+     } cp_me_vs_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_src_t f;
+} cp_me_vs_event_src_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_MASK \
+     (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \
+      CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK)
+
+#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \
+     ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \
+      (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_t f;
+} cp_me_vs_event_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_MASK \
+     (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK)
+
+#define CP_ME_VS_EVENT_DATA(vs_done_data) \
+     ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \
+     ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \
+     cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_t f;
+} cp_me_vs_event_data_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \
+      CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \
+     ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \
+      (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_swm_t f;
+} cp_me_vs_event_addr_swm_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_SWM_MASK \
+     (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \
+     ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \
+     ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \
+     cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_swm_t f;
+} cp_me_vs_event_data_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_SRC struct
+ */
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_PS_EVENT_SRC_MASK \
+     (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \
+      CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK)
+
+#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \
+     ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \
+      (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT))
+
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_ps_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int                                : 30;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+     } cp_me_ps_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_src_t f;
+} cp_me_ps_event_src_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_MASK \
+     (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \
+      CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK)
+
+#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \
+     ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \
+      (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_t f;
+} cp_me_ps_event_addr_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_MASK \
+     (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK)
+
+#define CP_ME_PS_EVENT_DATA(ps_done_data) \
+     ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \
+     ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \
+     cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_t f;
+} cp_me_ps_event_data_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \
+      CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \
+     ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \
+      (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_swm_t f;
+} cp_me_ps_event_addr_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_SWM_MASK \
+     (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \
+     ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \
+     ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \
+     cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_swm_t f;
+} cp_me_ps_event_data_swm_u;
+
+
+/*
+ * CP_ME_CF_EVENT_SRC struct
+ */
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001
+
+#define CP_ME_CF_EVENT_SRC_MASK \
+     (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK)
+
+#define CP_ME_CF_EVENT_SRC(cf_done_src) \
+     ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT))
+
+#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \
+     ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \
+     cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+          unsigned int                                : 31;
+     } cp_me_cf_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int                                : 31;
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+     } cp_me_cf_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_src_t f;
+} cp_me_cf_event_src_u;
+
+
+/*
+ * CP_ME_CF_EVENT_ADDR struct
+ */
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_CF_EVENT_ADDR_MASK \
+     (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \
+      CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK)
+
+#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \
+     ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \
+      (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT))
+
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_addr_t f;
+} cp_me_cf_event_addr_u;
+
+
+/*
+ * CP_ME_CF_EVENT_DATA struct
+ */
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_CF_EVENT_DATA_MASK \
+     (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK)
+
+#define CP_ME_CF_EVENT_DATA(cf_done_data) \
+     ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT))
+
+#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \
+     ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \
+     cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_data_t f;
+} cp_me_cf_event_data_u;
+
+
+/*
+ * CP_ME_NRT_ADDR struct
+ */
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_NRT_ADDR_MASK \
+     (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \
+      CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK)
+
+#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \
+     ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \
+      (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT))
+
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+     } cp_me_nrt_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+     } cp_me_nrt_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_addr_t f;
+} cp_me_nrt_addr_u;
+
+
+/*
+ * CP_ME_NRT_DATA struct
+ */
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff
+
+#define CP_ME_NRT_DATA_MASK \
+     (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK)
+
+#define CP_ME_NRT_DATA(nrt_write_data) \
+     ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT))
+
+#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \
+     ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \
+     cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_data_t f;
+} cp_me_nrt_data_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_SRC struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001
+
+#define CP_ME_VS_FETCH_DONE_SRC_MASK \
+     (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \
+     ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \
+     ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \
+     cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+          unsigned int                                : 31;
+     } cp_me_vs_fetch_done_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int                                : 31;
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+     } cp_me_vs_fetch_done_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_src_t f;
+} cp_me_vs_fetch_done_src_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_ADDR struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_FETCH_DONE_ADDR_MASK \
+     (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \
+      CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \
+     ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \
+      (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_addr_t f;
+} cp_me_vs_fetch_done_addr_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_DATA struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_FETCH_DONE_DATA_MASK \
+     (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK)
+
+#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \
+     ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \
+     ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \
+     cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_data_t f;
+} cp_me_vs_fetch_done_data_u;
+
+
+/*
+ * CP_INT_CNTL struct
+ */
+
+#define CP_INT_CNTL_SW_INT_MASK_SIZE   1
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB2_INT_MASK_SIZE  1
+#define CP_INT_CNTL_IB1_INT_MASK_SIZE  1
+#define CP_INT_CNTL_RB_INT_MASK_SIZE   1
+
+#define CP_INT_CNTL_SW_INT_MASK_SHIFT  19
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26
+#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27
+#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29
+#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30
+#define CP_INT_CNTL_RB_INT_MASK_SHIFT  31
+
+#define CP_INT_CNTL_SW_INT_MASK_MASK   0x00080000
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000
+#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000
+#define CP_INT_CNTL_IB2_INT_MASK_MASK  0x20000000
+#define CP_INT_CNTL_IB1_INT_MASK_MASK  0x40000000
+#define CP_INT_CNTL_RB_INT_MASK_MASK   0x80000000
+
+#define CP_INT_CNTL_MASK \
+     (CP_INT_CNTL_SW_INT_MASK_MASK | \
+      CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \
+      CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB2_INT_MASK_MASK | \
+      CP_INT_CNTL_IB1_INT_MASK_MASK | \
+      CP_INT_CNTL_RB_INT_MASK_MASK)
+
+#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \
+     ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \
+      (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \
+      (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \
+      (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \
+      (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \
+      (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \
+      (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \
+      (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \
+      (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT))
+
+#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+     } cp_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_cntl_t f;
+} cp_int_cntl_u;
+
+
+/*
+ * CP_INT_STATUS struct
+ */
+
+#define CP_INT_STATUS_SW_INT_STAT_SIZE 1
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1
+#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1
+#define CP_INT_STATUS_RB_INT_STAT_SIZE 1
+
+#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26
+#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27
+#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29
+#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30
+#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31
+
+#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000
+#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000
+#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000
+
+#define CP_INT_STATUS_MASK \
+     (CP_INT_STATUS_SW_INT_STAT_MASK | \
+      CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \
+      CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB2_INT_STAT_MASK | \
+      CP_INT_STATUS_IB1_INT_STAT_MASK | \
+      CP_INT_STATUS_RB_INT_STAT_MASK)
+
+#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \
+     ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \
+      (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \
+      (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \
+      (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \
+      (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \
+      (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \
+      (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \
+      (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \
+      (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT))
+
+#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+     } cp_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 19;
+     } cp_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_status_t f;
+} cp_int_status_u;
+
+
+/*
+ * CP_INT_ACK struct
+ */
+
+#define CP_INT_ACK_SW_INT_ACK_SIZE     1
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_IB_ERROR_ACK_SIZE   1
+#define CP_INT_ACK_IB2_INT_ACK_SIZE    1
+#define CP_INT_ACK_IB1_INT_ACK_SIZE    1
+#define CP_INT_ACK_RB_INT_ACK_SIZE     1
+
+#define CP_INT_ACK_SW_INT_ACK_SHIFT    19
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26
+#define CP_INT_ACK_IB_ERROR_ACK_SHIFT  27
+#define CP_INT_ACK_IB2_INT_ACK_SHIFT   29
+#define CP_INT_ACK_IB1_INT_ACK_SHIFT   30
+#define CP_INT_ACK_RB_INT_ACK_SHIFT    31
+
+#define CP_INT_ACK_SW_INT_ACK_MASK     0x00080000
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000
+#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000
+#define CP_INT_ACK_IB_ERROR_ACK_MASK   0x08000000
+#define CP_INT_ACK_IB2_INT_ACK_MASK    0x20000000
+#define CP_INT_ACK_IB1_INT_ACK_MASK    0x40000000
+#define CP_INT_ACK_RB_INT_ACK_MASK     0x80000000
+
+#define CP_INT_ACK_MASK \
+     (CP_INT_ACK_SW_INT_ACK_MASK | \
+      CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \
+      CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB2_INT_ACK_MASK | \
+      CP_INT_ACK_IB1_INT_ACK_MASK | \
+      CP_INT_ACK_RB_INT_ACK_MASK)
+
+#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \
+     ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \
+      (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \
+      (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \
+      (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \
+      (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \
+      (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \
+      (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \
+      (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \
+      (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT))
+
+#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+     } cp_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_ack_t f;
+} cp_int_ack_u;
+
+
+/*
+ * CP_PFP_UCODE_ADDR struct
+ */
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff
+
+#define CP_PFP_UCODE_ADDR_MASK \
+     (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK)
+
+#define CP_PFP_UCODE_ADDR(ucode_addr) \
+     ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT))
+
+#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \
+     ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \
+     cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+          unsigned int                                : 23;
+     } cp_pfp_ucode_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int                                : 23;
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+     } cp_pfp_ucode_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_addr_t f;
+} cp_pfp_ucode_addr_u;
+
+
+/*
+ * CP_PFP_UCODE_DATA struct
+ */
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff
+
+#define CP_PFP_UCODE_DATA_MASK \
+     (CP_PFP_UCODE_DATA_UCODE_DATA_MASK)
+
+#define CP_PFP_UCODE_DATA(ucode_data) \
+     ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT))
+
+#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \
+     ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \
+     cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+          unsigned int                                : 8;
+     } cp_pfp_ucode_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int                                : 8;
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+     } cp_pfp_ucode_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_data_t f;
+} cp_pfp_ucode_data_u;
+
+
+/*
+ * CP_PERFMON_CNTL struct
+ */
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300
+
+#define CP_PERFMON_CNTL_MASK \
+     (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \
+      CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK)
+
+#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \
+     ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \
+      (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT))
+
+#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 22;
+     } cp_perfmon_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int                                : 22;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+     } cp_perfmon_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfmon_cntl_t f;
+} cp_perfmon_cntl_u;
+
+
+/*
+ * CP_PERFCOUNTER_SELECT struct
+ */
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f
+
+#define CP_PERFCOUNTER_SELECT_MASK \
+     (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK)
+
+#define CP_PERFCOUNTER_SELECT(perfcount_sel) \
+     ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT))
+
+#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \
+     ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \
+     cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+          unsigned int                                : 26;
+     } cp_perfcounter_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int                                : 26;
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+     } cp_perfcounter_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_select_t f;
+} cp_perfcounter_select_u;
+
+
+/*
+ * CP_PERFCOUNTER_LO struct
+ */
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff
+
+#define CP_PERFCOUNTER_LO_MASK \
+     (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK)
+
+#define CP_PERFCOUNTER_LO(perfcount_lo) \
+     ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT))
+
+#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \
+     ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \
+     cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_lo_t f;
+} cp_perfcounter_lo_u;
+
+
+/*
+ * CP_PERFCOUNTER_HI struct
+ */
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff
+
+#define CP_PERFCOUNTER_HI_MASK \
+     (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK)
+
+#define CP_PERFCOUNTER_HI(perfcount_hi) \
+     ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT))
+
+#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \
+     ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \
+     cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+          unsigned int                                : 16;
+     } cp_perfcounter_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+     } cp_perfcounter_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_hi_t f;
+} cp_perfcounter_hi_u;
+
+
+/*
+ * CP_BIN_MASK_LO struct
+ */
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff
+
+#define CP_BIN_MASK_LO_MASK \
+     (CP_BIN_MASK_LO_BIN_MASK_LO_MASK)
+
+#define CP_BIN_MASK_LO(bin_mask_lo) \
+     ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT))
+
+#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \
+     ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \
+     cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_lo_t f;
+} cp_bin_mask_lo_u;
+
+
+/*
+ * CP_BIN_MASK_HI struct
+ */
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff
+
+#define CP_BIN_MASK_HI_MASK \
+     (CP_BIN_MASK_HI_BIN_MASK_HI_MASK)
+
+#define CP_BIN_MASK_HI(bin_mask_hi) \
+     ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT))
+
+#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \
+     ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \
+     cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_hi_t f;
+} cp_bin_mask_hi_u;
+
+
+/*
+ * CP_BIN_SELECT_LO struct
+ */
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff
+
+#define CP_BIN_SELECT_LO_MASK \
+     (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK)
+
+#define CP_BIN_SELECT_LO(bin_select_lo) \
+     ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT))
+
+#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \
+     ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \
+     cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_lo_t f;
+} cp_bin_select_lo_u;
+
+
+/*
+ * CP_BIN_SELECT_HI struct
+ */
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff
+
+#define CP_BIN_SELECT_HI_MASK \
+     (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK)
+
+#define CP_BIN_SELECT_HI(bin_select_hi) \
+     ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT))
+
+#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \
+     ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \
+     cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_hi_t f;
+} cp_bin_select_hi_u;
+
+
+/*
+ * CP_NV_FLAGS_0 struct
+ */
+
+#define CP_NV_FLAGS_0_DISCARD_0_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_0_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_1_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_1_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_2_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_2_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_3_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_3_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_4_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_4_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_5_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_5_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_6_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_6_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_7_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_7_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_8_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_8_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_9_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_9_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_10_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_11_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_12_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_13_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_14_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_15_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1
+
+#define CP_NV_FLAGS_0_DISCARD_0_SHIFT  0
+#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1
+#define CP_NV_FLAGS_0_DISCARD_1_SHIFT  2
+#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3
+#define CP_NV_FLAGS_0_DISCARD_2_SHIFT  4
+#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5
+#define CP_NV_FLAGS_0_DISCARD_3_SHIFT  6
+#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7
+#define CP_NV_FLAGS_0_DISCARD_4_SHIFT  8
+#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9
+#define CP_NV_FLAGS_0_DISCARD_5_SHIFT  10
+#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11
+#define CP_NV_FLAGS_0_DISCARD_6_SHIFT  12
+#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13
+#define CP_NV_FLAGS_0_DISCARD_7_SHIFT  14
+#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15
+#define CP_NV_FLAGS_0_DISCARD_8_SHIFT  16
+#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17
+#define CP_NV_FLAGS_0_DISCARD_9_SHIFT  18
+#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19
+#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20
+#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21
+#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22
+#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23
+#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24
+#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25
+#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26
+#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27
+#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28
+#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29
+#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30
+#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31
+
+#define CP_NV_FLAGS_0_DISCARD_0_MASK   0x00000001
+#define CP_NV_FLAGS_0_END_RCVD_0_MASK  0x00000002
+#define CP_NV_FLAGS_0_DISCARD_1_MASK   0x00000004
+#define CP_NV_FLAGS_0_END_RCVD_1_MASK  0x00000008
+#define CP_NV_FLAGS_0_DISCARD_2_MASK   0x00000010
+#define CP_NV_FLAGS_0_END_RCVD_2_MASK  0x00000020
+#define CP_NV_FLAGS_0_DISCARD_3_MASK   0x00000040
+#define CP_NV_FLAGS_0_END_RCVD_3_MASK  0x00000080
+#define CP_NV_FLAGS_0_DISCARD_4_MASK   0x00000100
+#define CP_NV_FLAGS_0_END_RCVD_4_MASK  0x00000200
+#define CP_NV_FLAGS_0_DISCARD_5_MASK   0x00000400
+#define CP_NV_FLAGS_0_END_RCVD_5_MASK  0x00000800
+#define CP_NV_FLAGS_0_DISCARD_6_MASK   0x00001000
+#define CP_NV_FLAGS_0_END_RCVD_6_MASK  0x00002000
+#define CP_NV_FLAGS_0_DISCARD_7_MASK   0x00004000
+#define CP_NV_FLAGS_0_END_RCVD_7_MASK  0x00008000
+#define CP_NV_FLAGS_0_DISCARD_8_MASK   0x00010000
+#define CP_NV_FLAGS_0_END_RCVD_8_MASK  0x00020000
+#define CP_NV_FLAGS_0_DISCARD_9_MASK   0x00040000
+#define CP_NV_FLAGS_0_END_RCVD_9_MASK  0x00080000
+#define CP_NV_FLAGS_0_DISCARD_10_MASK  0x00100000
+#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000
+#define CP_NV_FLAGS_0_DISCARD_11_MASK  0x00400000
+#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000
+#define CP_NV_FLAGS_0_DISCARD_12_MASK  0x01000000
+#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000
+#define CP_NV_FLAGS_0_DISCARD_13_MASK  0x04000000
+#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000
+#define CP_NV_FLAGS_0_DISCARD_14_MASK  0x10000000
+#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000
+#define CP_NV_FLAGS_0_DISCARD_15_MASK  0x40000000
+#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000
+
+#define CP_NV_FLAGS_0_MASK \
+     (CP_NV_FLAGS_0_DISCARD_0_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_0_MASK | \
+      CP_NV_FLAGS_0_DISCARD_1_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_1_MASK | \
+      CP_NV_FLAGS_0_DISCARD_2_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_2_MASK | \
+      CP_NV_FLAGS_0_DISCARD_3_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_3_MASK | \
+      CP_NV_FLAGS_0_DISCARD_4_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_4_MASK | \
+      CP_NV_FLAGS_0_DISCARD_5_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_5_MASK | \
+      CP_NV_FLAGS_0_DISCARD_6_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_6_MASK | \
+      CP_NV_FLAGS_0_DISCARD_7_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_7_MASK | \
+      CP_NV_FLAGS_0_DISCARD_8_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_8_MASK | \
+      CP_NV_FLAGS_0_DISCARD_9_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_9_MASK | \
+      CP_NV_FLAGS_0_DISCARD_10_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_10_MASK | \
+      CP_NV_FLAGS_0_DISCARD_11_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_11_MASK | \
+      CP_NV_FLAGS_0_DISCARD_12_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_12_MASK | \
+      CP_NV_FLAGS_0_DISCARD_13_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_13_MASK | \
+      CP_NV_FLAGS_0_DISCARD_14_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_14_MASK | \
+      CP_NV_FLAGS_0_DISCARD_15_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_15_MASK)
+
+#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \
+     ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \
+      (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \
+      (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \
+      (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \
+      (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \
+      (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \
+      (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \
+      (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \
+      (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \
+      (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \
+      (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \
+      (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \
+      (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \
+      (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \
+      (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \
+      (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \
+      (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \
+      (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \
+      (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \
+      (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \
+      (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \
+      (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \
+      (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \
+      (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \
+      (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \
+      (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \
+      (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \
+      (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \
+      (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \
+      (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \
+      (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \
+      (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT))
+
+#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+     } cp_nv_flags_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+     } cp_nv_flags_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_0_t f;
+} cp_nv_flags_0_u;
+
+
+/*
+ * CP_NV_FLAGS_1 struct
+ */
+
+#define CP_NV_FLAGS_1_DISCARD_16_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_17_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_18_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_19_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_20_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_21_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_22_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_23_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_24_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_25_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_26_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_27_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_28_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_29_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_30_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_31_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1
+
+#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0
+#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1
+#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2
+#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3
+#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4
+#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5
+#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6
+#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7
+#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8
+#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9
+#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10
+#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11
+#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12
+#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13
+#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14
+#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15
+#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16
+#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17
+#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18
+#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19
+#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20
+#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21
+#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22
+#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23
+#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24
+#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25
+#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26
+#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27
+#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28
+#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29
+#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30
+#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31
+
+#define CP_NV_FLAGS_1_DISCARD_16_MASK  0x00000001
+#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002
+#define CP_NV_FLAGS_1_DISCARD_17_MASK  0x00000004
+#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008
+#define CP_NV_FLAGS_1_DISCARD_18_MASK  0x00000010
+#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020
+#define CP_NV_FLAGS_1_DISCARD_19_MASK  0x00000040
+#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080
+#define CP_NV_FLAGS_1_DISCARD_20_MASK  0x00000100
+#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200
+#define CP_NV_FLAGS_1_DISCARD_21_MASK  0x00000400
+#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800
+#define CP_NV_FLAGS_1_DISCARD_22_MASK  0x00001000
+#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000
+#define CP_NV_FLAGS_1_DISCARD_23_MASK  0x00004000
+#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000
+#define CP_NV_FLAGS_1_DISCARD_24_MASK  0x00010000
+#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000
+#define CP_NV_FLAGS_1_DISCARD_25_MASK  0x00040000
+#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000
+#define CP_NV_FLAGS_1_DISCARD_26_MASK  0x00100000
+#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000
+#define CP_NV_FLAGS_1_DISCARD_27_MASK  0x00400000
+#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000
+#define CP_NV_FLAGS_1_DISCARD_28_MASK  0x01000000
+#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000
+#define CP_NV_FLAGS_1_DISCARD_29_MASK  0x04000000
+#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000
+#define CP_NV_FLAGS_1_DISCARD_30_MASK  0x10000000
+#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000
+#define CP_NV_FLAGS_1_DISCARD_31_MASK  0x40000000
+#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000
+
+#define CP_NV_FLAGS_1_MASK \
+     (CP_NV_FLAGS_1_DISCARD_16_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_16_MASK | \
+      CP_NV_FLAGS_1_DISCARD_17_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_17_MASK | \
+      CP_NV_FLAGS_1_DISCARD_18_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_18_MASK | \
+      CP_NV_FLAGS_1_DISCARD_19_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_19_MASK | \
+      CP_NV_FLAGS_1_DISCARD_20_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_20_MASK | \
+      CP_NV_FLAGS_1_DISCARD_21_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_21_MASK | \
+      CP_NV_FLAGS_1_DISCARD_22_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_22_MASK | \
+      CP_NV_FLAGS_1_DISCARD_23_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_23_MASK | \
+      CP_NV_FLAGS_1_DISCARD_24_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_24_MASK | \
+      CP_NV_FLAGS_1_DISCARD_25_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_25_MASK | \
+      CP_NV_FLAGS_1_DISCARD_26_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_26_MASK | \
+      CP_NV_FLAGS_1_DISCARD_27_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_27_MASK | \
+      CP_NV_FLAGS_1_DISCARD_28_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_28_MASK | \
+      CP_NV_FLAGS_1_DISCARD_29_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_29_MASK | \
+      CP_NV_FLAGS_1_DISCARD_30_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_30_MASK | \
+      CP_NV_FLAGS_1_DISCARD_31_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_31_MASK)
+
+#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \
+     ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \
+      (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \
+      (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \
+      (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \
+      (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \
+      (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \
+      (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \
+      (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \
+      (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \
+      (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \
+      (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \
+      (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \
+      (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \
+      (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \
+      (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \
+      (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \
+      (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \
+      (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \
+      (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \
+      (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \
+      (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \
+      (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \
+      (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \
+      (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \
+      (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \
+      (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \
+      (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \
+      (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \
+      (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \
+      (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \
+      (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \
+      (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT))
+
+#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+     } cp_nv_flags_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+     } cp_nv_flags_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_1_t f;
+} cp_nv_flags_1_u;
+
+
+/*
+ * CP_NV_FLAGS_2 struct
+ */
+
+#define CP_NV_FLAGS_2_DISCARD_32_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_33_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_34_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_35_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_36_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_37_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_38_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_39_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_40_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_41_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_42_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_43_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_44_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_45_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_46_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_47_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1
+
+#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0
+#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1
+#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2
+#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3
+#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4
+#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5
+#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6
+#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7
+#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8
+#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9
+#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10
+#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11
+#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12
+#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13
+#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14
+#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15
+#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16
+#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17
+#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18
+#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19
+#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20
+#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21
+#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22
+#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23
+#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24
+#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25
+#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26
+#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27
+#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28
+#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29
+#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30
+#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31
+
+#define CP_NV_FLAGS_2_DISCARD_32_MASK  0x00000001
+#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002
+#define CP_NV_FLAGS_2_DISCARD_33_MASK  0x00000004
+#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008
+#define CP_NV_FLAGS_2_DISCARD_34_MASK  0x00000010
+#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020
+#define CP_NV_FLAGS_2_DISCARD_35_MASK  0x00000040
+#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080
+#define CP_NV_FLAGS_2_DISCARD_36_MASK  0x00000100
+#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200
+#define CP_NV_FLAGS_2_DISCARD_37_MASK  0x00000400
+#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800
+#define CP_NV_FLAGS_2_DISCARD_38_MASK  0x00001000
+#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000
+#define CP_NV_FLAGS_2_DISCARD_39_MASK  0x00004000
+#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000
+#define CP_NV_FLAGS_2_DISCARD_40_MASK  0x00010000
+#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000
+#define CP_NV_FLAGS_2_DISCARD_41_MASK  0x00040000
+#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000
+#define CP_NV_FLAGS_2_DISCARD_42_MASK  0x00100000
+#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000
+#define CP_NV_FLAGS_2_DISCARD_43_MASK  0x00400000
+#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000
+#define CP_NV_FLAGS_2_DISCARD_44_MASK  0x01000000
+#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000
+#define CP_NV_FLAGS_2_DISCARD_45_MASK  0x04000000
+#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000
+#define CP_NV_FLAGS_2_DISCARD_46_MASK  0x10000000
+#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000
+#define CP_NV_FLAGS_2_DISCARD_47_MASK  0x40000000
+#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000
+
+#define CP_NV_FLAGS_2_MASK \
+     (CP_NV_FLAGS_2_DISCARD_32_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_32_MASK | \
+      CP_NV_FLAGS_2_DISCARD_33_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_33_MASK | \
+      CP_NV_FLAGS_2_DISCARD_34_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_34_MASK | \
+      CP_NV_FLAGS_2_DISCARD_35_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_35_MASK | \
+      CP_NV_FLAGS_2_DISCARD_36_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_36_MASK | \
+      CP_NV_FLAGS_2_DISCARD_37_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_37_MASK | \
+      CP_NV_FLAGS_2_DISCARD_38_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_38_MASK | \
+      CP_NV_FLAGS_2_DISCARD_39_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_39_MASK | \
+      CP_NV_FLAGS_2_DISCARD_40_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_40_MASK | \
+      CP_NV_FLAGS_2_DISCARD_41_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_41_MASK | \
+      CP_NV_FLAGS_2_DISCARD_42_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_42_MASK | \
+      CP_NV_FLAGS_2_DISCARD_43_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_43_MASK | \
+      CP_NV_FLAGS_2_DISCARD_44_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_44_MASK | \
+      CP_NV_FLAGS_2_DISCARD_45_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_45_MASK | \
+      CP_NV_FLAGS_2_DISCARD_46_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_46_MASK | \
+      CP_NV_FLAGS_2_DISCARD_47_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_47_MASK)
+
+#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \
+     ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \
+      (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \
+      (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \
+      (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \
+      (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \
+      (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \
+      (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \
+      (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \
+      (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \
+      (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \
+      (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \
+      (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \
+      (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \
+      (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \
+      (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \
+      (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \
+      (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \
+      (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \
+      (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \
+      (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \
+      (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \
+      (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \
+      (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \
+      (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \
+      (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \
+      (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \
+      (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \
+      (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \
+      (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \
+      (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \
+      (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \
+      (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT))
+
+#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+     } cp_nv_flags_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+     } cp_nv_flags_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_2_t f;
+} cp_nv_flags_2_u;
+
+
+/*
+ * CP_NV_FLAGS_3 struct
+ */
+
+#define CP_NV_FLAGS_3_DISCARD_48_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_49_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_50_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_51_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_52_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_53_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_54_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_55_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_56_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_57_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_58_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_59_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_60_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_61_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_62_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_63_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1
+
+#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0
+#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1
+#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2
+#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3
+#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4
+#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5
+#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6
+#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7
+#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8
+#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9
+#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10
+#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11
+#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12
+#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13
+#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14
+#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15
+#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16
+#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17
+#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18
+#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19
+#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20
+#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21
+#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22
+#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23
+#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24
+#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25
+#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26
+#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27
+#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28
+#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29
+#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30
+#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31
+
+#define CP_NV_FLAGS_3_DISCARD_48_MASK  0x00000001
+#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002
+#define CP_NV_FLAGS_3_DISCARD_49_MASK  0x00000004
+#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008
+#define CP_NV_FLAGS_3_DISCARD_50_MASK  0x00000010
+#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020
+#define CP_NV_FLAGS_3_DISCARD_51_MASK  0x00000040
+#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080
+#define CP_NV_FLAGS_3_DISCARD_52_MASK  0x00000100
+#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200
+#define CP_NV_FLAGS_3_DISCARD_53_MASK  0x00000400
+#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800
+#define CP_NV_FLAGS_3_DISCARD_54_MASK  0x00001000
+#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000
+#define CP_NV_FLAGS_3_DISCARD_55_MASK  0x00004000
+#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000
+#define CP_NV_FLAGS_3_DISCARD_56_MASK  0x00010000
+#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000
+#define CP_NV_FLAGS_3_DISCARD_57_MASK  0x00040000
+#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000
+#define CP_NV_FLAGS_3_DISCARD_58_MASK  0x00100000
+#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000
+#define CP_NV_FLAGS_3_DISCARD_59_MASK  0x00400000
+#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000
+#define CP_NV_FLAGS_3_DISCARD_60_MASK  0x01000000
+#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000
+#define CP_NV_FLAGS_3_DISCARD_61_MASK  0x04000000
+#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000
+#define CP_NV_FLAGS_3_DISCARD_62_MASK  0x10000000
+#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000
+#define CP_NV_FLAGS_3_DISCARD_63_MASK  0x40000000
+#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000
+
+#define CP_NV_FLAGS_3_MASK \
+     (CP_NV_FLAGS_3_DISCARD_48_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_48_MASK | \
+      CP_NV_FLAGS_3_DISCARD_49_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_49_MASK | \
+      CP_NV_FLAGS_3_DISCARD_50_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_50_MASK | \
+      CP_NV_FLAGS_3_DISCARD_51_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_51_MASK | \
+      CP_NV_FLAGS_3_DISCARD_52_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_52_MASK | \
+      CP_NV_FLAGS_3_DISCARD_53_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_53_MASK | \
+      CP_NV_FLAGS_3_DISCARD_54_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_54_MASK | \
+      CP_NV_FLAGS_3_DISCARD_55_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_55_MASK | \
+      CP_NV_FLAGS_3_DISCARD_56_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_56_MASK | \
+      CP_NV_FLAGS_3_DISCARD_57_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_57_MASK | \
+      CP_NV_FLAGS_3_DISCARD_58_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_58_MASK | \
+      CP_NV_FLAGS_3_DISCARD_59_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_59_MASK | \
+      CP_NV_FLAGS_3_DISCARD_60_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_60_MASK | \
+      CP_NV_FLAGS_3_DISCARD_61_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_61_MASK | \
+      CP_NV_FLAGS_3_DISCARD_62_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_62_MASK | \
+      CP_NV_FLAGS_3_DISCARD_63_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_63_MASK)
+
+#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \
+     ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \
+      (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \
+      (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \
+      (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \
+      (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \
+      (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \
+      (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \
+      (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \
+      (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \
+      (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \
+      (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \
+      (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \
+      (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \
+      (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \
+      (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \
+      (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \
+      (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \
+      (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \
+      (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \
+      (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \
+      (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \
+      (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \
+      (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \
+      (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \
+      (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \
+      (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \
+      (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \
+      (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \
+      (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \
+      (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \
+      (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \
+      (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT))
+
+#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+     } cp_nv_flags_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+     } cp_nv_flags_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_3_t f;
+} cp_nv_flags_3_u;
+
+
+/*
+ * CP_STATE_DEBUG_INDEX struct
+ */
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f
+
+#define CP_STATE_DEBUG_INDEX_MASK \
+     (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK)
+
+#define CP_STATE_DEBUG_INDEX(state_debug_index) \
+     ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT))
+
+#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \
+     ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \
+     cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+          unsigned int                                : 27;
+     } cp_state_debug_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int                                : 27;
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+     } cp_state_debug_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_index_t f;
+} cp_state_debug_index_u;
+
+
+/*
+ * CP_STATE_DEBUG_DATA struct
+ */
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_STATE_DEBUG_DATA_MASK \
+     (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK)
+
+#define CP_STATE_DEBUG_DATA(state_debug_data) \
+     ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT))
+
+#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \
+     ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \
+     cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_data_t f;
+} cp_state_debug_data_u;
+
+
+/*
+ * CP_PROG_COUNTER struct
+ */
+
+#define CP_PROG_COUNTER_COUNTER_SIZE   32
+
+#define CP_PROG_COUNTER_COUNTER_SHIFT  0
+
+#define CP_PROG_COUNTER_COUNTER_MASK   0xffffffff
+
+#define CP_PROG_COUNTER_MASK \
+     (CP_PROG_COUNTER_COUNTER_MASK)
+
+#define CP_PROG_COUNTER(counter) \
+     ((counter << CP_PROG_COUNTER_COUNTER_SHIFT))
+
+#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \
+     ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \
+     cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_prog_counter_t f;
+} cp_prog_counter_u;
+
+
+/*
+ * CP_STAT struct
+ */
+
+#define CP_STAT_MIU_WR_BUSY_SIZE       1
+#define CP_STAT_MIU_RD_REQ_BUSY_SIZE   1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1
+#define CP_STAT_RBIU_BUSY_SIZE         1
+#define CP_STAT_RCIU_BUSY_SIZE         1
+#define CP_STAT_CSF_RING_BUSY_SIZE     1
+#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_CSF_ST_BUSY_SIZE       1
+#define CP_STAT_CSF_BUSY_SIZE          1
+#define CP_STAT_RING_QUEUE_BUSY_SIZE   1
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1
+#define CP_STAT_ST_QUEUE_BUSY_SIZE     1
+#define CP_STAT_PFP_BUSY_SIZE          1
+#define CP_STAT_MEQ_RING_BUSY_SIZE     1
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_MIU_WC_STALL_SIZE      1
+#define CP_STAT_CP_NRT_BUSY_SIZE       1
+#define CP_STAT__3D_BUSY_SIZE          1
+#define CP_STAT_ME_BUSY_SIZE           1
+#define CP_STAT_ME_WC_BUSY_SIZE        1
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1
+#define CP_STAT_CP_BUSY_SIZE           1
+
+#define CP_STAT_MIU_WR_BUSY_SHIFT      0
+#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT  1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2
+#define CP_STAT_RBIU_BUSY_SHIFT        3
+#define CP_STAT_RCIU_BUSY_SHIFT        4
+#define CP_STAT_CSF_RING_BUSY_SHIFT    5
+#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6
+#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7
+#define CP_STAT_CSF_ST_BUSY_SHIFT      9
+#define CP_STAT_CSF_BUSY_SHIFT         10
+#define CP_STAT_RING_QUEUE_BUSY_SHIFT  11
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13
+#define CP_STAT_ST_QUEUE_BUSY_SHIFT    16
+#define CP_STAT_PFP_BUSY_SHIFT         17
+#define CP_STAT_MEQ_RING_BUSY_SHIFT    18
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20
+#define CP_STAT_MIU_WC_STALL_SHIFT     21
+#define CP_STAT_CP_NRT_BUSY_SHIFT      22
+#define CP_STAT__3D_BUSY_SHIFT         23
+#define CP_STAT_ME_BUSY_SHIFT          26
+#define CP_STAT_ME_WC_BUSY_SHIFT       29
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30
+#define CP_STAT_CP_BUSY_SHIFT          31
+
+#define CP_STAT_MIU_WR_BUSY_MASK       0x00000001
+#define CP_STAT_MIU_RD_REQ_BUSY_MASK   0x00000002
+#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004
+#define CP_STAT_RBIU_BUSY_MASK         0x00000008
+#define CP_STAT_RCIU_BUSY_MASK         0x00000010
+#define CP_STAT_CSF_RING_BUSY_MASK     0x00000020
+#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040
+#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080
+#define CP_STAT_CSF_ST_BUSY_MASK       0x00000200
+#define CP_STAT_CSF_BUSY_MASK          0x00000400
+#define CP_STAT_RING_QUEUE_BUSY_MASK   0x00000800
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000
+#define CP_STAT_ST_QUEUE_BUSY_MASK     0x00010000
+#define CP_STAT_PFP_BUSY_MASK          0x00020000
+#define CP_STAT_MEQ_RING_BUSY_MASK     0x00040000
+#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000
+#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000
+#define CP_STAT_MIU_WC_STALL_MASK      0x00200000
+#define CP_STAT_CP_NRT_BUSY_MASK       0x00400000
+#define CP_STAT__3D_BUSY_MASK          0x00800000
+#define CP_STAT_ME_BUSY_MASK           0x04000000
+#define CP_STAT_ME_WC_BUSY_MASK        0x20000000
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000
+#define CP_STAT_CP_BUSY_MASK           0x80000000
+
+#define CP_STAT_MASK \
+     (CP_STAT_MIU_WR_BUSY_MASK | \
+      CP_STAT_MIU_RD_REQ_BUSY_MASK | \
+      CP_STAT_MIU_RD_RETURN_BUSY_MASK | \
+      CP_STAT_RBIU_BUSY_MASK | \
+      CP_STAT_RCIU_BUSY_MASK | \
+      CP_STAT_CSF_RING_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECTS_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECT2_BUSY_MASK | \
+      CP_STAT_CSF_ST_BUSY_MASK | \
+      CP_STAT_CSF_BUSY_MASK | \
+      CP_STAT_RING_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \
+      CP_STAT_ST_QUEUE_BUSY_MASK | \
+      CP_STAT_PFP_BUSY_MASK | \
+      CP_STAT_MEQ_RING_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \
+      CP_STAT_MIU_WC_STALL_MASK | \
+      CP_STAT_CP_NRT_BUSY_MASK | \
+      CP_STAT__3D_BUSY_MASK | \
+      CP_STAT_ME_BUSY_MASK | \
+      CP_STAT_ME_WC_BUSY_MASK | \
+      CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \
+      CP_STAT_CP_BUSY_MASK)
+
+#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \
+     ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \
+      (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \
+      (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \
+      (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \
+      (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \
+      (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \
+      (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \
+      (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \
+      (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \
+      (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \
+      (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \
+      (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \
+      (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \
+      (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \
+      (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \
+      (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \
+      (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \
+      (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \
+      (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \
+      (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \
+      (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \
+      (me_busy << CP_STAT_ME_BUSY_SHIFT) | \
+      (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \
+      (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \
+      (cp_busy << CP_STAT_CP_BUSY_SHIFT))
+
+#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_GET_RBIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_GET_RCIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_PFP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_GET__3D_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_GET_ME_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_GET_CP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT)
+
+#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+     } cp_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+     } cp_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stat_t f;
+} cp_stat_u;
+
+
+/*
+ * BIOS_0_SCRATCH struct
+ */
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_0_SCRATCH_MASK \
+     (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_0_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \
+     ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \
+     bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_0_scratch_t f;
+} bios_0_scratch_u;
+
+
+/*
+ * BIOS_1_SCRATCH struct
+ */
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_1_SCRATCH_MASK \
+     (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_1_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \
+     ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \
+     bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_1_scratch_t f;
+} bios_1_scratch_u;
+
+
+/*
+ * BIOS_2_SCRATCH struct
+ */
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_2_SCRATCH_MASK \
+     (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_2_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \
+     ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \
+     bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_2_scratch_t f;
+} bios_2_scratch_u;
+
+
+/*
+ * BIOS_3_SCRATCH struct
+ */
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_3_SCRATCH_MASK \
+     (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_3_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \
+     ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \
+     bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_3_scratch_t f;
+} bios_3_scratch_u;
+
+
+/*
+ * BIOS_4_SCRATCH struct
+ */
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_4_SCRATCH_MASK \
+     (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_4_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \
+     ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \
+     bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_4_scratch_t f;
+} bios_4_scratch_u;
+
+
+/*
+ * BIOS_5_SCRATCH struct
+ */
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_5_SCRATCH_MASK \
+     (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_5_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \
+     ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \
+     bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_5_scratch_t f;
+} bios_5_scratch_u;
+
+
+/*
+ * BIOS_6_SCRATCH struct
+ */
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_6_SCRATCH_MASK \
+     (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_6_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \
+     ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \
+     bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_6_scratch_t f;
+} bios_6_scratch_u;
+
+
+/*
+ * BIOS_7_SCRATCH struct
+ */
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_7_SCRATCH_MASK \
+     (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_7_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \
+     ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \
+     bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_7_scratch_t f;
+} bios_7_scratch_u;
+
+
+/*
+ * BIOS_8_SCRATCH struct
+ */
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_8_SCRATCH_MASK \
+     (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_8_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \
+     ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \
+     bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_8_scratch_t f;
+} bios_8_scratch_u;
+
+
+/*
+ * BIOS_9_SCRATCH struct
+ */
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_9_SCRATCH_MASK \
+     (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_9_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \
+     ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \
+     bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_9_scratch_t f;
+} bios_9_scratch_u;
+
+
+/*
+ * BIOS_10_SCRATCH struct
+ */
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_10_SCRATCH_MASK \
+     (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_10_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \
+     ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \
+     bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_10_scratch_t f;
+} bios_10_scratch_u;
+
+
+/*
+ * BIOS_11_SCRATCH struct
+ */
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_11_SCRATCH_MASK \
+     (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_11_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \
+     ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \
+     bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_11_scratch_t f;
+} bios_11_scratch_u;
+
+
+/*
+ * BIOS_12_SCRATCH struct
+ */
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_12_SCRATCH_MASK \
+     (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_12_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \
+     ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \
+     bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_12_scratch_t f;
+} bios_12_scratch_u;
+
+
+/*
+ * BIOS_13_SCRATCH struct
+ */
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_13_SCRATCH_MASK \
+     (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_13_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \
+     ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \
+     bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_13_scratch_t f;
+} bios_13_scratch_u;
+
+
+/*
+ * BIOS_14_SCRATCH struct
+ */
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_14_SCRATCH_MASK \
+     (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_14_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \
+     ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \
+     bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_14_scratch_t f;
+} bios_14_scratch_u;
+
+
+/*
+ * BIOS_15_SCRATCH struct
+ */
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_15_SCRATCH_MASK \
+     (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_15_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \
+     ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \
+     bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_15_scratch_t f;
+} bios_15_scratch_u;
+
+
+/*
+ * COHER_SIZE_PM4 struct
+ */
+
+#define COHER_SIZE_PM4_SIZE_SIZE       32
+
+#define COHER_SIZE_PM4_SIZE_SHIFT      0
+
+#define COHER_SIZE_PM4_SIZE_MASK       0xffffffff
+
+#define COHER_SIZE_PM4_MASK \
+     (COHER_SIZE_PM4_SIZE_MASK)
+
+#define COHER_SIZE_PM4(size) \
+     ((size << COHER_SIZE_PM4_SIZE_SHIFT))
+
+#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \
+     ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT)
+
+#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \
+     coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_pm4_t f;
+} coher_size_pm4_u;
+
+
+/*
+ * COHER_BASE_PM4 struct
+ */
+
+#define COHER_BASE_PM4_BASE_SIZE       32
+
+#define COHER_BASE_PM4_BASE_SHIFT      0
+
+#define COHER_BASE_PM4_BASE_MASK       0xffffffff
+
+#define COHER_BASE_PM4_MASK \
+     (COHER_BASE_PM4_BASE_MASK)
+
+#define COHER_BASE_PM4(base) \
+     ((base << COHER_BASE_PM4_BASE_SHIFT))
+
+#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \
+     ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT)
+
+#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \
+     coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_pm4_t f;
+} coher_base_pm4_u;
+
+
+/*
+ * COHER_STATUS_PM4 struct
+ */
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_PM4_STATUS_SIZE   1
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_PM4_STATUS_SHIFT  31
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_PM4_STATUS_MASK   0x80000000
+
+#define COHER_STATUS_PM4_MASK \
+     (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_PM4_STATUS_MASK)
+
+#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_PM4_STATUS_SHIFT))
+
+#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT)
+
+#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int                                : 8;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+     } coher_status_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 8;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+     } coher_status_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_pm4_t f;
+} coher_status_pm4_u;
+
+
+/*
+ * COHER_SIZE_HOST struct
+ */
+
+#define COHER_SIZE_HOST_SIZE_SIZE      32
+
+#define COHER_SIZE_HOST_SIZE_SHIFT     0
+
+#define COHER_SIZE_HOST_SIZE_MASK      0xffffffff
+
+#define COHER_SIZE_HOST_MASK \
+     (COHER_SIZE_HOST_SIZE_MASK)
+
+#define COHER_SIZE_HOST(size) \
+     ((size << COHER_SIZE_HOST_SIZE_SHIFT))
+
+#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \
+     ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT)
+
+#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \
+     coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_host_t f;
+} coher_size_host_u;
+
+
+/*
+ * COHER_BASE_HOST struct
+ */
+
+#define COHER_BASE_HOST_BASE_SIZE      32
+
+#define COHER_BASE_HOST_BASE_SHIFT     0
+
+#define COHER_BASE_HOST_BASE_MASK      0xffffffff
+
+#define COHER_BASE_HOST_MASK \
+     (COHER_BASE_HOST_BASE_MASK)
+
+#define COHER_BASE_HOST(base) \
+     ((base << COHER_BASE_HOST_BASE_SHIFT))
+
+#define COHER_BASE_HOST_GET_BASE(coher_base_host) \
+     ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT)
+
+#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \
+     coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_host_t f;
+} coher_base_host_u;
+
+
+/*
+ * COHER_STATUS_HOST struct
+ */
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_HOST_STATUS_SIZE  1
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_HOST_STATUS_SHIFT 31
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_HOST_STATUS_MASK  0x80000000
+
+#define COHER_STATUS_HOST_MASK \
+     (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_HOST_STATUS_MASK)
+
+#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_HOST_STATUS_SHIFT))
+
+#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT)
+
+#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int                                : 8;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+     } coher_status_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 8;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+     } coher_status_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_host_t f;
+} coher_status_host_u;
+
+
+/*
+ * COHER_DEST_BASE_0 struct
+ */
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000
+
+#define COHER_DEST_BASE_0_MASK \
+     (COHER_DEST_BASE_0_DEST_BASE_0_MASK)
+
+#define COHER_DEST_BASE_0(dest_base_0) \
+     ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT))
+
+#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \
+     ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \
+     coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+     } coher_dest_base_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_0_t f;
+} coher_dest_base_0_u;
+
+
+/*
+ * COHER_DEST_BASE_1 struct
+ */
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000
+
+#define COHER_DEST_BASE_1_MASK \
+     (COHER_DEST_BASE_1_DEST_BASE_1_MASK)
+
+#define COHER_DEST_BASE_1(dest_base_1) \
+     ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT))
+
+#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \
+     ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \
+     coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+     } coher_dest_base_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_1_t f;
+} coher_dest_base_1_u;
+
+
+/*
+ * COHER_DEST_BASE_2 struct
+ */
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000
+
+#define COHER_DEST_BASE_2_MASK \
+     (COHER_DEST_BASE_2_DEST_BASE_2_MASK)
+
+#define COHER_DEST_BASE_2(dest_base_2) \
+     ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT))
+
+#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \
+     ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \
+     coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+     } coher_dest_base_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_2_t f;
+} coher_dest_base_2_u;
+
+
+/*
+ * COHER_DEST_BASE_3 struct
+ */
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000
+
+#define COHER_DEST_BASE_3_MASK \
+     (COHER_DEST_BASE_3_DEST_BASE_3_MASK)
+
+#define COHER_DEST_BASE_3(dest_base_3) \
+     ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT))
+
+#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \
+     ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \
+     coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+     } coher_dest_base_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_3_t f;
+} coher_dest_base_3_u;
+
+
+/*
+ * COHER_DEST_BASE_4 struct
+ */
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000
+
+#define COHER_DEST_BASE_4_MASK \
+     (COHER_DEST_BASE_4_DEST_BASE_4_MASK)
+
+#define COHER_DEST_BASE_4(dest_base_4) \
+     ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT))
+
+#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \
+     ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \
+     coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+     } coher_dest_base_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_4_t f;
+} coher_dest_base_4_u;
+
+
+/*
+ * COHER_DEST_BASE_5 struct
+ */
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000
+
+#define COHER_DEST_BASE_5_MASK \
+     (COHER_DEST_BASE_5_DEST_BASE_5_MASK)
+
+#define COHER_DEST_BASE_5(dest_base_5) \
+     ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT))
+
+#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \
+     ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \
+     coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+     } coher_dest_base_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_5_t f;
+} coher_dest_base_5_u;
+
+
+/*
+ * COHER_DEST_BASE_6 struct
+ */
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000
+
+#define COHER_DEST_BASE_6_MASK \
+     (COHER_DEST_BASE_6_DEST_BASE_6_MASK)
+
+#define COHER_DEST_BASE_6(dest_base_6) \
+     ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT))
+
+#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \
+     ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \
+     coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+     } coher_dest_base_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_6_t f;
+} coher_dest_base_6_u;
+
+
+/*
+ * COHER_DEST_BASE_7 struct
+ */
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000
+
+#define COHER_DEST_BASE_7_MASK \
+     (COHER_DEST_BASE_7_DEST_BASE_7_MASK)
+
+#define COHER_DEST_BASE_7(dest_base_7) \
+     ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT))
+
+#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \
+     ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \
+     coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+     } coher_dest_base_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_7_t f;
+} coher_dest_base_7_u;
+
+
+#endif
+
+
+#if !defined (_RBBM_FIDDLE_H)
+#define _RBBM_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  rbbm_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * WAIT_UNTIL struct
+ */
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_VSYNC_SIZE     1
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1
+#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2
+#define WAIT_UNTIL_WAIT_VSYNC_SHIFT    3
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6
+#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT  10
+#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT  14
+#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT  15
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK  0x00000002
+#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK  0x00000004
+#define WAIT_UNTIL_WAIT_VSYNC_MASK     0x00000008
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040
+#define WAIT_UNTIL_WAIT_CMDFIFO_MASK   0x00000400
+#define WAIT_UNTIL_WAIT_2D_IDLE_MASK   0x00004000
+#define WAIT_UNTIL_WAIT_3D_IDLE_MASK   0x00008000
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000
+
+#define WAIT_UNTIL_MASK \
+     (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \
+      WAIT_UNTIL_WAIT_CMDFIFO_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_CMDFIFO_ENTRIES_MASK)
+
+#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \
+     ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \
+      (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \
+      (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \
+      (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \
+      (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \
+      (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \
+      (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \
+      (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \
+      (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \
+      (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \
+      (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \
+      (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT))
+
+#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \
+     ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 1;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int                                : 2;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 8;
+     } wait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 8;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 2;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int                                : 1;
+     } wait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     wait_until_t f;
+} wait_until_u;
+
+
+/*
+ * RBBM_ISYNC_CNTL struct
+ */
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020
+
+#define RBBM_ISYNC_CNTL_MASK \
+     (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \
+      RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK)
+
+#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \
+     ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \
+      (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT))
+
+#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 4;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int                                : 26;
+     } rbbm_isync_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 26;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int                                : 4;
+     } rbbm_isync_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_isync_cntl_t f;
+} rbbm_isync_cntl_u;
+
+
+/*
+ * RBBM_STATUS struct
+ */
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5
+#define RBBM_STATUS_TC_BUSY_SIZE       1
+#define RBBM_STATUS_HIRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CPRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_PFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1
+#define RBBM_STATUS_RBBM_WU_BUSY_SIZE  1
+#define RBBM_STATUS_CP_NRT_BUSY_SIZE   1
+#define RBBM_STATUS_MH_BUSY_SIZE       1
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1
+#define RBBM_STATUS_SX_BUSY_SIZE       1
+#define RBBM_STATUS_TPC_BUSY_SIZE      1
+#define RBBM_STATUS_SC_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_PA_BUSY_SIZE       1
+#define RBBM_STATUS_VGT_BUSY_SIZE      1
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1
+#define RBBM_STATUS_RB_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_GUI_ACTIVE_SIZE    1
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0
+#define RBBM_STATUS_TC_BUSY_SHIFT      5
+#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8
+#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9
+#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10
+#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12
+#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14
+#define RBBM_STATUS_CP_NRT_BUSY_SHIFT  16
+#define RBBM_STATUS_MH_BUSY_SHIFT      18
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19
+#define RBBM_STATUS_SX_BUSY_SHIFT      21
+#define RBBM_STATUS_TPC_BUSY_SHIFT     22
+#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24
+#define RBBM_STATUS_PA_BUSY_SHIFT      25
+#define RBBM_STATUS_VGT_BUSY_SHIFT     26
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28
+#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30
+#define RBBM_STATUS_GUI_ACTIVE_SHIFT   31
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f
+#define RBBM_STATUS_TC_BUSY_MASK       0x00000020
+#define RBBM_STATUS_HIRQ_PENDING_MASK  0x00000100
+#define RBBM_STATUS_CPRQ_PENDING_MASK  0x00000200
+#define RBBM_STATUS_CFRQ_PENDING_MASK  0x00000400
+#define RBBM_STATUS_PFRQ_PENDING_MASK  0x00000800
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000
+#define RBBM_STATUS_RBBM_WU_BUSY_MASK  0x00004000
+#define RBBM_STATUS_CP_NRT_BUSY_MASK   0x00010000
+#define RBBM_STATUS_MH_BUSY_MASK       0x00040000
+#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000
+#define RBBM_STATUS_SX_BUSY_MASK       0x00200000
+#define RBBM_STATUS_TPC_BUSY_MASK      0x00400000
+#define RBBM_STATUS_SC_CNTX_BUSY_MASK  0x01000000
+#define RBBM_STATUS_PA_BUSY_MASK       0x02000000
+#define RBBM_STATUS_VGT_BUSY_MASK      0x04000000
+#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000
+#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000
+#define RBBM_STATUS_RB_CNTX_BUSY_MASK  0x40000000
+#define RBBM_STATUS_GUI_ACTIVE_MASK    0x80000000
+
+#define RBBM_STATUS_MASK \
+     (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \
+      RBBM_STATUS_TC_BUSY_MASK | \
+      RBBM_STATUS_HIRQ_PENDING_MASK | \
+      RBBM_STATUS_CPRQ_PENDING_MASK | \
+      RBBM_STATUS_CFRQ_PENDING_MASK | \
+      RBBM_STATUS_PFRQ_PENDING_MASK | \
+      RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \
+      RBBM_STATUS_RBBM_WU_BUSY_MASK | \
+      RBBM_STATUS_CP_NRT_BUSY_MASK | \
+      RBBM_STATUS_MH_BUSY_MASK | \
+      RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \
+      RBBM_STATUS_SX_BUSY_MASK | \
+      RBBM_STATUS_TPC_BUSY_MASK | \
+      RBBM_STATUS_SC_CNTX_BUSY_MASK | \
+      RBBM_STATUS_PA_BUSY_MASK | \
+      RBBM_STATUS_VGT_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \
+      RBBM_STATUS_RB_CNTX_BUSY_MASK | \
+      RBBM_STATUS_GUI_ACTIVE_MASK)
+
+#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \
+     ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \
+      (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \
+      (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \
+      (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \
+      (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \
+      (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \
+      (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \
+      (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \
+      (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \
+      (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \
+      (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \
+      (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \
+      (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \
+      (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \
+      (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \
+      (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \
+      (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \
+      (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \
+      (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \
+      (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT))
+
+#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+     } rbbm_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int                                : 2;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+     } rbbm_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_status_t f;
+} rbbm_status_u;
+
+
+/*
+ * RBBM_DSPLY struct
+ */
+
+#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE 1
+#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE 1
+#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE 1
+#define RBBM_DSPLY_VSYNC_ACTIVE_SIZE   1
+#define RBBM_DSPLY_USE_DISPLAY_ID0_SIZE 1
+#define RBBM_DSPLY_USE_DISPLAY_ID1_SIZE 1
+#define RBBM_DSPLY_USE_DISPLAY_ID2_SIZE 1
+#define RBBM_DSPLY_SW_CNTL_SIZE        1
+#define RBBM_DSPLY_NUM_BUFS_SIZE       2
+
+#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT 0
+#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT 1
+#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT 2
+#define RBBM_DSPLY_VSYNC_ACTIVE_SHIFT  3
+#define RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT 4
+#define RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT 5
+#define RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT 6
+#define RBBM_DSPLY_SW_CNTL_SHIFT       7
+#define RBBM_DSPLY_NUM_BUFS_SHIFT      8
+
+#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK 0x00000001
+#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK 0x00000002
+#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK 0x00000004
+#define RBBM_DSPLY_VSYNC_ACTIVE_MASK   0x00000008
+#define RBBM_DSPLY_USE_DISPLAY_ID0_MASK 0x00000010
+#define RBBM_DSPLY_USE_DISPLAY_ID1_MASK 0x00000020
+#define RBBM_DSPLY_USE_DISPLAY_ID2_MASK 0x00000040
+#define RBBM_DSPLY_SW_CNTL_MASK        0x00000080
+#define RBBM_DSPLY_NUM_BUFS_MASK       0x00000300
+
+#define RBBM_DSPLY_MASK \
+     (RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK | \
+      RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK | \
+      RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK | \
+      RBBM_DSPLY_VSYNC_ACTIVE_MASK | \
+      RBBM_DSPLY_USE_DISPLAY_ID0_MASK | \
+      RBBM_DSPLY_USE_DISPLAY_ID1_MASK | \
+      RBBM_DSPLY_USE_DISPLAY_ID2_MASK | \
+      RBBM_DSPLY_SW_CNTL_MASK | \
+      RBBM_DSPLY_NUM_BUFS_MASK)
+
+#define RBBM_DSPLY(display_id0_active, display_id1_active, display_id2_active, vsync_active, use_display_id0, use_display_id1, use_display_id2, sw_cntl, num_bufs) \
+     ((display_id0_active << RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT) | \
+      (display_id1_active << RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT) | \
+      (display_id2_active << RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT) | \
+      (vsync_active << RBBM_DSPLY_VSYNC_ACTIVE_SHIFT) | \
+      (use_display_id0 << RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT) | \
+      (use_display_id1 << RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT) | \
+      (use_display_id2 << RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT) | \
+      (sw_cntl << RBBM_DSPLY_SW_CNTL_SHIFT) | \
+      (num_bufs << RBBM_DSPLY_NUM_BUFS_SHIFT))
+
+#define RBBM_DSPLY_GET_DISPLAY_ID0_ACTIVE(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT)
+#define RBBM_DSPLY_GET_DISPLAY_ID1_ACTIVE(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT)
+#define RBBM_DSPLY_GET_DISPLAY_ID2_ACTIVE(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT)
+#define RBBM_DSPLY_GET_VSYNC_ACTIVE(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_VSYNC_ACTIVE_MASK) >> RBBM_DSPLY_VSYNC_ACTIVE_SHIFT)
+#define RBBM_DSPLY_GET_USE_DISPLAY_ID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID0_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT)
+#define RBBM_DSPLY_GET_USE_DISPLAY_ID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID1_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT)
+#define RBBM_DSPLY_GET_USE_DISPLAY_ID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID2_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT)
+#define RBBM_DSPLY_GET_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SW_CNTL_MASK) >> RBBM_DSPLY_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_NUM_BUFS_MASK) >> RBBM_DSPLY_NUM_BUFS_SHIFT)
+
+#define RBBM_DSPLY_SET_DISPLAY_ID0_ACTIVE(rbbm_dsply_reg, display_id0_active) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK) | (display_id0_active << RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT)
+#define RBBM_DSPLY_SET_DISPLAY_ID1_ACTIVE(rbbm_dsply_reg, display_id1_active) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK) | (display_id1_active << RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT)
+#define RBBM_DSPLY_SET_DISPLAY_ID2_ACTIVE(rbbm_dsply_reg, display_id2_active) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK) | (display_id2_active << RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT)
+#define RBBM_DSPLY_SET_VSYNC_ACTIVE(rbbm_dsply_reg, vsync_active) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_VSYNC_ACTIVE_MASK) | (vsync_active << RBBM_DSPLY_VSYNC_ACTIVE_SHIFT)
+#define RBBM_DSPLY_SET_USE_DISPLAY_ID0(rbbm_dsply_reg, use_display_id0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID0_MASK) | (use_display_id0 << RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT)
+#define RBBM_DSPLY_SET_USE_DISPLAY_ID1(rbbm_dsply_reg, use_display_id1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID1_MASK) | (use_display_id1 << RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT)
+#define RBBM_DSPLY_SET_USE_DISPLAY_ID2(rbbm_dsply_reg, use_display_id2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID2_MASK) | (use_display_id2 << RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT)
+#define RBBM_DSPLY_SET_SW_CNTL(rbbm_dsply_reg, sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SW_CNTL_MASK) | (sw_cntl << RBBM_DSPLY_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_NUM_BUFS(rbbm_dsply_reg, num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_NUM_BUFS_MASK) | (num_bufs << RBBM_DSPLY_NUM_BUFS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int display_id0_active             : RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE;
+          unsigned int display_id1_active             : RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE;
+          unsigned int display_id2_active             : RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE;
+          unsigned int vsync_active                   : RBBM_DSPLY_VSYNC_ACTIVE_SIZE;
+          unsigned int use_display_id0                : RBBM_DSPLY_USE_DISPLAY_ID0_SIZE;
+          unsigned int use_display_id1                : RBBM_DSPLY_USE_DISPLAY_ID1_SIZE;
+          unsigned int use_display_id2                : RBBM_DSPLY_USE_DISPLAY_ID2_SIZE;
+          unsigned int sw_cntl                        : RBBM_DSPLY_SW_CNTL_SIZE;
+          unsigned int num_bufs                       : RBBM_DSPLY_NUM_BUFS_SIZE;
+          unsigned int                                : 22;
+     } rbbm_dsply_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int                                : 22;
+          unsigned int num_bufs                       : RBBM_DSPLY_NUM_BUFS_SIZE;
+          unsigned int sw_cntl                        : RBBM_DSPLY_SW_CNTL_SIZE;
+          unsigned int use_display_id2                : RBBM_DSPLY_USE_DISPLAY_ID2_SIZE;
+          unsigned int use_display_id1                : RBBM_DSPLY_USE_DISPLAY_ID1_SIZE;
+          unsigned int use_display_id0                : RBBM_DSPLY_USE_DISPLAY_ID0_SIZE;
+          unsigned int vsync_active                   : RBBM_DSPLY_VSYNC_ACTIVE_SIZE;
+          unsigned int display_id2_active             : RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE;
+          unsigned int display_id1_active             : RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE;
+          unsigned int display_id0_active             : RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE;
+     } rbbm_dsply_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_dsply_t f;
+} rbbm_dsply_u;
+
+
+/*
+ * RBBM_RENDER_LATEST struct
+ */
+
+#define RBBM_RENDER_LATEST_BUFFER_ID_SIZE 2
+
+#define RBBM_RENDER_LATEST_BUFFER_ID_SHIFT 0
+
+#define RBBM_RENDER_LATEST_BUFFER_ID_MASK 0x00000003
+
+#define RBBM_RENDER_LATEST_MASK \
+     (RBBM_RENDER_LATEST_BUFFER_ID_MASK)
+
+#define RBBM_RENDER_LATEST(buffer_id) \
+     ((buffer_id << RBBM_RENDER_LATEST_BUFFER_ID_SHIFT))
+
+#define RBBM_RENDER_LATEST_GET_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_BUFFER_ID_SHIFT)
+
+#define RBBM_RENDER_LATEST_SET_BUFFER_ID(rbbm_render_latest_reg, buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_BUFFER_ID_MASK) | (buffer_id << RBBM_RENDER_LATEST_BUFFER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int buffer_id                      : RBBM_RENDER_LATEST_BUFFER_ID_SIZE;
+          unsigned int                                : 30;
+     } rbbm_render_latest_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int                                : 30;
+          unsigned int buffer_id                      : RBBM_RENDER_LATEST_BUFFER_ID_SIZE;
+     } rbbm_render_latest_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_render_latest_t f;
+} rbbm_render_latest_u;
+
+
+/*
+ * RBBM_RTL_RELEASE struct
+ */
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0
+
+#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff
+
+#define RBBM_RTL_RELEASE_MASK \
+     (RBBM_RTL_RELEASE_CHANGELIST_MASK)
+
+#define RBBM_RTL_RELEASE(changelist) \
+     ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT))
+
+#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \
+     ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \
+     rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_rtl_release_t f;
+} rbbm_rtl_release_u;
+
+
+/*
+ * RBBM_PATCH_RELEASE struct
+ */
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000
+
+#define RBBM_PATCH_RELEASE_MASK \
+     (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \
+      RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \
+      RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK)
+
+#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \
+     ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \
+      (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \
+      (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT))
+
+#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+     } rbbm_patch_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+     } rbbm_patch_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_patch_release_t f;
+} rbbm_patch_release_u;
+
+
+/*
+ * RBBM_AUXILIARY_CONFIG struct
+ */
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff
+
+#define RBBM_AUXILIARY_CONFIG_MASK \
+     (RBBM_AUXILIARY_CONFIG_RESERVED_MASK)
+
+#define RBBM_AUXILIARY_CONFIG(reserved) \
+     ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT))
+
+#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \
+     ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \
+     rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_auxiliary_config_t f;
+} rbbm_auxiliary_config_u;
+
+
+/*
+ * RBBM_PERIPHID0 struct
+ */
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0
+
+#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff
+
+#define RBBM_PERIPHID0_MASK \
+     (RBBM_PERIPHID0_PARTNUMBER0_MASK)
+
+#define RBBM_PERIPHID0(partnumber0) \
+     ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT))
+
+#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \
+     ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \
+     rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int                                : 24;
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+     } rbbm_periphid0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid0_t f;
+} rbbm_periphid0_u;
+
+
+/*
+ * RBBM_PERIPHID1 struct
+ */
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4
+#define RBBM_PERIPHID1_DESIGNER0_SIZE  4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0
+#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f
+#define RBBM_PERIPHID1_DESIGNER0_MASK  0x000000f0
+
+#define RBBM_PERIPHID1_MASK \
+     (RBBM_PERIPHID1_PARTNUMBER1_MASK | \
+      RBBM_PERIPHID1_DESIGNER0_MASK)
+
+#define RBBM_PERIPHID1(partnumber1, designer0) \
+     ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \
+      (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT))
+
+#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int                                : 24;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+     } rbbm_periphid1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid1_t f;
+} rbbm_periphid1_u;
+
+
+/*
+ * RBBM_PERIPHID2 struct
+ */
+
+#define RBBM_PERIPHID2_DESIGNER1_SIZE  4
+#define RBBM_PERIPHID2_REVISION_SIZE   4
+
+#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0
+#define RBBM_PERIPHID2_REVISION_SHIFT  4
+
+#define RBBM_PERIPHID2_DESIGNER1_MASK  0x0000000f
+#define RBBM_PERIPHID2_REVISION_MASK   0x000000f0
+
+#define RBBM_PERIPHID2_MASK \
+     (RBBM_PERIPHID2_DESIGNER1_MASK | \
+      RBBM_PERIPHID2_REVISION_MASK)
+
+#define RBBM_PERIPHID2(designer1, revision) \
+     ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \
+      (revision << RBBM_PERIPHID2_REVISION_SHIFT))
+
+#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT)
+
+#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int                                : 24;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+     } rbbm_periphid2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid2_t f;
+} rbbm_periphid2_u;
+
+
+/*
+ * RBBM_PERIPHID3 struct
+ */
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_CONTINUATION_SIZE 1
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4
+#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c
+#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030
+#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080
+
+#define RBBM_PERIPHID3_MASK \
+     (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \
+      RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \
+      RBBM_PERIPHID3_MH_INTERFACE_MASK | \
+      RBBM_PERIPHID3_CONTINUATION_MASK)
+
+#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \
+     ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \
+      (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \
+      (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \
+      (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT))
+
+#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int                                : 1;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int                                : 24;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+     } rbbm_periphid3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid3_t f;
+} rbbm_periphid3_u;
+
+
+/*
+ * RBBM_CNTL struct
+ */
+
+#define RBBM_CNTL_READ_TIMEOUT_SIZE    8
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9
+
+#define RBBM_CNTL_READ_TIMEOUT_SHIFT   0
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8
+
+#define RBBM_CNTL_READ_TIMEOUT_MASK    0x000000ff
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00
+
+#define RBBM_CNTL_MASK \
+     (RBBM_CNTL_READ_TIMEOUT_MASK | \
+      RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK)
+
+#define RBBM_CNTL(read_timeout, regclk_deassert_time) \
+     ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \
+      (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT))
+
+#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int                                : 15;
+     } rbbm_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int                                : 15;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+     } rbbm_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_cntl_t f;
+} rbbm_cntl_u;
+
+
+/*
+ * RBBM_SKEW_CNTL struct
+ */
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f
+#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0
+
+#define RBBM_SKEW_CNTL_MASK \
+     (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \
+      RBBM_SKEW_CNTL_SKEW_COUNT_MASK)
+
+#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \
+     ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \
+      (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT))
+
+#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int                                : 22;
+     } rbbm_skew_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int                                : 22;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+     } rbbm_skew_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_skew_cntl_t f;
+} rbbm_skew_cntl_u;
+
+
+/*
+ * RBBM_SOFT_RESET struct
+ */
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000
+
+#define RBBM_SOFT_RESET_MASK \
+     (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK)
+
+#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \
+     ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \
+      (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \
+      (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \
+      (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \
+      (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \
+      (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \
+      (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \
+      (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \
+      (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT))
+
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int                                : 15;
+     } rbbm_soft_reset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int                                : 15;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+     } rbbm_soft_reset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_soft_reset_t f;
+} rbbm_soft_reset_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE1 struct
+ */
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000
+
+#define RBBM_PM_OVERRIDE1_MASK \
+     (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \
+     ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override1_t f;
+} rbbm_pm_override1_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE2 struct
+ */
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800
+
+#define RBBM_PM_OVERRIDE2_MASK \
+     (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \
+     ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \
+      (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \
+      (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int                                : 20;
+     } rbbm_pm_override2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int                                : 20;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override2_t f;
+} rbbm_pm_override2_u;
+
+
+/*
+ * GC_SYS_IDLE struct
+ */
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000
+
+#define GC_SYS_IDLE_MASK \
+     (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \
+      GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK)
+
+#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_idle_override) \
+     ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \
+      (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT))
+
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+          unsigned int                                : 15;
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+     } gc_sys_idle_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+          unsigned int                                : 15;
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+     } gc_sys_idle_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gc_sys_idle_t f;
+} gc_sys_idle_u;
+
+
+/*
+ * NQWAIT_UNTIL struct
+ */
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001
+
+#define NQWAIT_UNTIL_MASK \
+     (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK)
+
+#define NQWAIT_UNTIL(wait_gui_idle) \
+     ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT))
+
+#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \
+     ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \
+     nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+          unsigned int                                : 31;
+     } nqwait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int                                : 31;
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+     } nqwait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     nqwait_until_t f;
+} nqwait_until_u;
+
+
+/*
+ * RBBM_DEBUG struct
+ */
+
+#define RBBM_DEBUG_IGNORE_RTR_SIZE     1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1
+
+#define RBBM_DEBUG_IGNORE_RTR_SHIFT    1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31
+
+#define RBBM_DEBUG_IGNORE_RTR_MASK     0x00000002
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000
+
+#define RBBM_DEBUG_MASK \
+     (RBBM_DEBUG_IGNORE_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \
+      RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \
+      RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK)
+
+#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \
+     ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \
+      (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \
+      (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \
+      (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \
+      (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \
+      (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \
+      (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \
+      (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \
+      (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \
+      (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \
+      (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \
+      (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT))
+
+#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int                                : 1;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int                                : 3;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 4;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+     } rbbm_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+          unsigned int                                : 6;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int                                : 4;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 3;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int                                : 1;
+     } rbbm_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_t f;
+} rbbm_debug_u;
+
+
+/*
+ * RBBM_READ_ERROR struct
+ */
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15
+#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1
+#define RBBM_READ_ERROR_READ_ERROR_SIZE 1
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2
+#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30
+#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31
+
+#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc
+#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000
+#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000
+
+#define RBBM_READ_ERROR_MASK \
+     (RBBM_READ_ERROR_READ_ADDRESS_MASK | \
+      RBBM_READ_ERROR_READ_REQUESTER_MASK | \
+      RBBM_READ_ERROR_READ_ERROR_MASK)
+
+#define RBBM_READ_ERROR(read_address, read_requester, read_error) \
+     ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \
+      (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \
+      (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT))
+
+#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int                                : 2;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+     } rbbm_read_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 2;
+     } rbbm_read_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_read_error_t f;
+} rbbm_read_error_u;
+
+
+/*
+ * RBBM_WAIT_IDLE_CLOCKS struct
+ */
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff
+
+#define RBBM_WAIT_IDLE_CLOCKS_MASK \
+     (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK)
+
+#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \
+     ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT))
+
+#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \
+     ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \
+     rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+          unsigned int                                : 24;
+     } rbbm_wait_idle_clocks_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int                                : 24;
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+     } rbbm_wait_idle_clocks_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_wait_idle_clocks_t f;
+} rbbm_wait_idle_clocks_u;
+
+
+/*
+ * RBBM_INT_CNTL struct
+ */
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000
+
+#define RBBM_INT_CNTL_MASK \
+     (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \
+      RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \
+      RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK)
+
+#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \
+     ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \
+      (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \
+      (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT))
+
+#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+     } rbbm_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_cntl_t f;
+} rbbm_int_cntl_u;
+
+
+/*
+ * RBBM_INT_STATUS struct
+ */
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000
+
+#define RBBM_INT_STATUS_MASK \
+     (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \
+      RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \
+      RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK)
+
+#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \
+     ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \
+      (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \
+      (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT))
+
+#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+     } rbbm_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_status_t f;
+} rbbm_int_status_u;
+
+
+/*
+ * RBBM_INT_ACK struct
+ */
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000
+
+#define RBBM_INT_ACK_MASK \
+     (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \
+      RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \
+      RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK)
+
+#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \
+     ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \
+      (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \
+      (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT))
+
+#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+     } rbbm_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_ack_t f;
+} rbbm_int_ack_u;
+
+
+/*
+ * MASTER_INT_SIGNAL struct
+ */
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020
+#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000
+
+#define MASTER_INT_SIGNAL_MASK \
+     (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK)
+
+#define MASTER_INT_SIGNAL(mh_int_stat, cp_int_stat, rbbm_int_stat) \
+     ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \
+      (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \
+      (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT))
+
+#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int                                : 5;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 24;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+     } master_int_signal_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int                                : 24;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 5;
+     } master_int_signal_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     master_int_signal_t f;
+} master_int_signal_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_SELECT struct
+ */
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f
+
+#define RBBM_PERFCOUNTER1_SELECT_MASK \
+     (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK)
+
+#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \
+     ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT))
+
+#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \
+     ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \
+     rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+          unsigned int                                : 26;
+     } rbbm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int                                : 26;
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+     } rbbm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_select_t f;
+} rbbm_perfcounter1_select_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_LO struct
+ */
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff
+
+#define RBBM_PERFCOUNTER1_LO_MASK \
+     (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK)
+
+#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \
+     ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT))
+
+#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \
+     ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \
+     rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_lo_t f;
+} rbbm_perfcounter1_lo_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_HI struct
+ */
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff
+
+#define RBBM_PERFCOUNTER1_HI_MASK \
+     (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK)
+
+#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \
+     ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT))
+
+#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \
+     ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \
+     rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+          unsigned int                                : 16;
+     } rbbm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+     } rbbm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_hi_t f;
+} rbbm_perfcounter1_hi_u;
+
+
+#endif
+
+
+#if !defined (_MH_FIDDLE_H)
+#define _MH_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  mh_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * MH_ARBITER_CONFIG struct
+ */
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200
+#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000
+
+#define MH_ARBITER_CONFIG_MASK \
+     (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \
+      MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \
+      MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK)
+
+#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable) \
+     ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \
+      (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \
+      (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \
+      (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \
+      (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \
+      (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \
+      (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \
+      (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \
+      (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \
+      (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \
+      (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \
+      (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \
+      (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT))
+
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int                                : 6;
+     } mh_arbiter_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int                                : 6;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+     } mh_arbiter_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_arbiter_config_t f;
+} mh_arbiter_config_u;
+
+
+/*
+ * MH_CLNT_AXI_ID_REUSE struct
+ */
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700
+
+#define MH_CLNT_AXI_ID_REUSE_MASK \
+     (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \
+      MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id) \
+     ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \
+      (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \
+      (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \
+      (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \
+      (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int                                : 21;
+     } mh_clnt_axi_id_reuse_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int                                : 21;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+     } mh_clnt_axi_id_reuse_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_clnt_axi_id_reuse_t f;
+} mh_clnt_axi_id_reuse_u;
+
+
+/*
+ * MH_INTERRUPT_MASK struct
+ */
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_MASK_MASK \
+     (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_mask_t f;
+} mh_interrupt_mask_u;
+
+
+/*
+ * MH_INTERRUPT_STATUS struct
+ */
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_STATUS_MASK \
+     (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_status_t f;
+} mh_interrupt_status_u;
+
+
+/*
+ * MH_INTERRUPT_CLEAR struct
+ */
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_CLEAR_MASK \
+     (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_clear_t f;
+} mh_interrupt_clear_u;
+
+
+/*
+ * MH_AXI_ERROR struct
+ */
+
+#define MH_AXI_ERROR_AXI_READ_ID_SIZE  3
+#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1
+#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1
+
+#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0
+#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3
+#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7
+
+#define MH_AXI_ERROR_AXI_READ_ID_MASK  0x00000007
+#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008
+#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080
+
+#define MH_AXI_ERROR_MASK \
+     (MH_AXI_ERROR_AXI_READ_ID_MASK | \
+      MH_AXI_ERROR_AXI_READ_ERROR_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ID_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ERROR_MASK)
+
+#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \
+     ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \
+      (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \
+      (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT))
+
+#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int                                : 24;
+     } mh_axi_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int                                : 24;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+     } mh_axi_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_error_t f;
+} mh_axi_error_u;
+
+
+/*
+ * MH_PERFCOUNTER0_SELECT struct
+ */
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_SELECT_MASK \
+     (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \
+     ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \
+     mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_select_t f;
+} mh_perfcounter0_select_u;
+
+
+/*
+ * MH_PERFCOUNTER1_SELECT struct
+ */
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_SELECT_MASK \
+     (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \
+     ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \
+     mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_select_t f;
+} mh_perfcounter1_select_u;
+
+
+/*
+ * MH_PERFCOUNTER0_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_CONFIG_MASK \
+     (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER0_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \
+     ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \
+     mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter0_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_config_t f;
+} mh_perfcounter0_config_u;
+
+
+/*
+ * MH_PERFCOUNTER1_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_CONFIG_MASK \
+     (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER1_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \
+     ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \
+     mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter1_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_config_t f;
+} mh_perfcounter1_config_u;
+
+
+/*
+ * MH_PERFCOUNTER0_LOW struct
+ */
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER0_LOW_MASK \
+     (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER0_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \
+     ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \
+     mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_low_t f;
+} mh_perfcounter0_low_u;
+
+
+/*
+ * MH_PERFCOUNTER1_LOW struct
+ */
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER1_LOW_MASK \
+     (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER1_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \
+     ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \
+     mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_low_t f;
+} mh_perfcounter1_low_u;
+
+
+/*
+ * MH_PERFCOUNTER0_HI struct
+ */
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER0_HI_MASK \
+     (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER0_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \
+     ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \
+     mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_hi_t f;
+} mh_perfcounter0_hi_u;
+
+
+/*
+ * MH_PERFCOUNTER1_HI struct
+ */
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER1_HI_MASK \
+     (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER1_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \
+     ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \
+     mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_hi_t f;
+} mh_perfcounter1_hi_u;
+
+
+/*
+ * MH_DEBUG_CTRL struct
+ */
+
+#define MH_DEBUG_CTRL_INDEX_SIZE       6
+
+#define MH_DEBUG_CTRL_INDEX_SHIFT      0
+
+#define MH_DEBUG_CTRL_INDEX_MASK       0x0000003f
+
+#define MH_DEBUG_CTRL_MASK \
+     (MH_DEBUG_CTRL_INDEX_MASK)
+
+#define MH_DEBUG_CTRL(index) \
+     ((index << MH_DEBUG_CTRL_INDEX_SHIFT))
+
+#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \
+     ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \
+     mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+          unsigned int                                : 26;
+     } mh_debug_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int                                : 26;
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+     } mh_debug_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_ctrl_t f;
+} mh_debug_ctrl_u;
+
+
+/*
+ * MH_DEBUG_DATA struct
+ */
+
+#define MH_DEBUG_DATA_DATA_SIZE        32
+
+#define MH_DEBUG_DATA_DATA_SHIFT       0
+
+#define MH_DEBUG_DATA_DATA_MASK        0xffffffff
+
+#define MH_DEBUG_DATA_MASK \
+     (MH_DEBUG_DATA_DATA_MASK)
+
+#define MH_DEBUG_DATA(data) \
+     ((data << MH_DEBUG_DATA_DATA_SHIFT))
+
+#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \
+     ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT)
+
+#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \
+     mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_data_t f;
+} mh_debug_data_u;
+
+
+/*
+ * MH_DEBUG_REG00 struct
+ */
+
+#define MH_DEBUG_REG00_MH_BUSY_SIZE    1
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1
+#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1
+#define MH_DEBUG_REG00_TCD_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_TCD_FULL_SIZE   1
+#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1
+#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_ARQ_FULL_SIZE   1
+#define MH_DEBUG_REG00_WDB_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_WDB_FULL_SIZE   1
+#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1
+
+#define MH_DEBUG_REG00_MH_BUSY_SHIFT   0
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1
+#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2
+#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3
+#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5
+#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6
+#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7
+#define MH_DEBUG_REG00_TCD_FULL_SHIFT  8
+#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 10
+#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 11
+#define MH_DEBUG_REG00_ARQ_FULL_SHIFT  12
+#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 13
+#define MH_DEBUG_REG00_WDB_FULL_SHIFT  14
+#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 15
+#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 16
+#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 17
+#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 18
+#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 19
+#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 20
+#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 21
+#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 22
+#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 23
+#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 24
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 25
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 26
+
+#define MH_DEBUG_REG00_MH_BUSY_MASK    0x00000001
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002
+#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004
+#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008
+#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020
+#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040
+#define MH_DEBUG_REG00_TCD_EMPTY_MASK  0x00000080
+#define MH_DEBUG_REG00_TCD_FULL_MASK   0x00000100
+#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000400
+#define MH_DEBUG_REG00_ARQ_EMPTY_MASK  0x00000800
+#define MH_DEBUG_REG00_ARQ_FULL_MASK   0x00001000
+#define MH_DEBUG_REG00_WDB_EMPTY_MASK  0x00002000
+#define MH_DEBUG_REG00_WDB_FULL_MASK   0x00004000
+#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00008000
+#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00010000
+#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00020000
+#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00040000
+#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00080000
+#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00100000
+#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00200000
+#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00400000
+#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x00800000
+#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x01000000
+#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x02000000
+#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x04000000
+
+#define MH_DEBUG_REG00_MASK \
+     (MH_DEBUG_REG00_MH_BUSY_MASK | \
+      MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \
+      MH_DEBUG_REG00_CP_REQUEST_MASK | \
+      MH_DEBUG_REG00_VGT_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \
+      MH_DEBUG_REG00_TC_CAM_FULL_MASK | \
+      MH_DEBUG_REG00_TCD_EMPTY_MASK | \
+      MH_DEBUG_REG00_TCD_FULL_MASK | \
+      MH_DEBUG_REG00_RB_REQUEST_MASK | \
+      MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \
+      MH_DEBUG_REG00_ARQ_EMPTY_MASK | \
+      MH_DEBUG_REG00_ARQ_FULL_MASK | \
+      MH_DEBUG_REG00_WDB_EMPTY_MASK | \
+      MH_DEBUG_REG00_WDB_FULL_MASK | \
+      MH_DEBUG_REG00_AXI_AVALID_MASK | \
+      MH_DEBUG_REG00_AXI_AREADY_MASK | \
+      MH_DEBUG_REG00_AXI_ARVALID_MASK | \
+      MH_DEBUG_REG00_AXI_ARREADY_MASK | \
+      MH_DEBUG_REG00_AXI_WVALID_MASK | \
+      MH_DEBUG_REG00_AXI_WREADY_MASK | \
+      MH_DEBUG_REG00_AXI_RVALID_MASK | \
+      MH_DEBUG_REG00_AXI_RREADY_MASK | \
+      MH_DEBUG_REG00_AXI_BVALID_MASK | \
+      MH_DEBUG_REG00_AXI_BREADY_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_ACK_MASK)
+
+#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack) \
+     ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \
+      (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \
+      (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \
+      (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \
+      (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \
+      (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \
+      (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \
+      (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \
+      (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \
+      (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \
+      (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \
+      (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \
+      (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \
+      (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \
+      (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \
+      (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \
+      (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \
+      (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \
+      (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \
+      (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \
+      (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \
+      (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \
+      (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \
+      (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \
+      (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \
+      (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \
+      (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT))
+
+#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+
+#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int                                : 5;
+     } mh_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int                                : 5;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+     } mh_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg00_t f;
+} mh_debug_reg00_u;
+
+
+/*
+ * MH_DEBUG_REG01 struct
+ */
+
+#define MH_DEBUG_REG01_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1
+#define MH_DEBUG_REG01_CP_TAG_q_SIZE   3
+#define MH_DEBUG_REG01_CP_BE_q_SIZE    8
+#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_TAG_q_SIZE  1
+#define MH_DEBUG_REG01_TC_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_TC_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG01_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG01_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_RB_BE_q_SIZE    8
+
+#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0
+#define MH_DEBUG_REG01_CP_RTR_q_SHIFT  1
+#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2
+#define MH_DEBUG_REG01_CP_TAG_q_SHIFT  3
+#define MH_DEBUG_REG01_CP_BE_q_SHIFT   6
+#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 14
+#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 15
+#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 16
+#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 17
+#define MH_DEBUG_REG01_TC_RTR_q_SHIFT  18
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 19
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 20
+#define MH_DEBUG_REG01_TC_MH_written_SHIFT 21
+#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 22
+#define MH_DEBUG_REG01_RB_RTR_q_SHIFT  23
+#define MH_DEBUG_REG01_RB_BE_q_SHIFT   24
+
+#define MH_DEBUG_REG01_CP_SEND_q_MASK  0x00000001
+#define MH_DEBUG_REG01_CP_RTR_q_MASK   0x00000002
+#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004
+#define MH_DEBUG_REG01_CP_TAG_q_MASK   0x00000038
+#define MH_DEBUG_REG01_CP_BE_q_MASK    0x00003fc0
+#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00004000
+#define MH_DEBUG_REG01_VGT_RTR_q_MASK  0x00008000
+#define MH_DEBUG_REG01_VGT_TAG_q_MASK  0x00010000
+#define MH_DEBUG_REG01_TC_SEND_q_MASK  0x00020000
+#define MH_DEBUG_REG01_TC_RTR_q_MASK   0x00040000
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00080000
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00100000
+#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00200000
+#define MH_DEBUG_REG01_RB_SEND_q_MASK  0x00400000
+#define MH_DEBUG_REG01_RB_RTR_q_MASK   0x00800000
+#define MH_DEBUG_REG01_RB_BE_q_MASK    0xff000000
+
+#define MH_DEBUG_REG01_MASK \
+     (MH_DEBUG_REG01_CP_SEND_q_MASK | \
+      MH_DEBUG_REG01_CP_RTR_q_MASK | \
+      MH_DEBUG_REG01_CP_WRITE_q_MASK | \
+      MH_DEBUG_REG01_CP_TAG_q_MASK | \
+      MH_DEBUG_REG01_CP_BE_q_MASK | \
+      MH_DEBUG_REG01_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG01_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG01_VGT_TAG_q_MASK | \
+      MH_DEBUG_REG01_TC_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_MH_written_MASK | \
+      MH_DEBUG_REG01_RB_SEND_q_MASK | \
+      MH_DEBUG_REG01_RB_RTR_q_MASK | \
+      MH_DEBUG_REG01_RB_BE_q_MASK)
+
+#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_be_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, rb_be_q) \
+     ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \
+      (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \
+      (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \
+      (cp_be_q << MH_DEBUG_REG01_CP_BE_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \
+      (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \
+      (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \
+      (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \
+      (rb_be_q << MH_DEBUG_REG01_RB_BE_q_SHIFT))
+
+#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_BE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BE_q_MASK) >> MH_DEBUG_REG01_CP_BE_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_BE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_BE_q_MASK) >> MH_DEBUG_REG01_RB_BE_q_SHIFT)
+
+#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_BE_q(mh_debug_reg01_reg, cp_be_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BE_q_MASK) | (cp_be_q << MH_DEBUG_REG01_CP_BE_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_BE_q(mh_debug_reg01_reg, rb_be_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_BE_q_MASK) | (rb_be_q << MH_DEBUG_REG01_RB_BE_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_be_q                        : MH_DEBUG_REG01_CP_BE_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int rb_be_q                        : MH_DEBUG_REG01_RB_BE_q_SIZE;
+     } mh_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int rb_be_q                        : MH_DEBUG_REG01_RB_BE_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int cp_be_q                        : MH_DEBUG_REG01_CP_BE_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+     } mh_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg01_t f;
+} mh_debug_reg01_u;
+
+
+/*
+ * MH_DEBUG_REG02 struct
+ */
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3
+#define MH_DEBUG_REG02_RDC_RID_SIZE    3
+#define MH_DEBUG_REG02_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1
+#define MH_DEBUG_REG02_BRC_BID_SIZE    3
+#define MH_DEBUG_REG02_BRC_BRESP_SIZE  2
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3
+#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4
+#define MH_DEBUG_REG02_RDC_RID_SHIFT   7
+#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12
+#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13
+#define MH_DEBUG_REG02_BRC_BID_SHIFT   14
+#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 17
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008
+#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070
+#define MH_DEBUG_REG02_RDC_RID_MASK    0x00000380
+#define MH_DEBUG_REG02_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000
+#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000
+#define MH_DEBUG_REG02_BRC_BID_MASK    0x0001c000
+#define MH_DEBUG_REG02_BRC_BRESP_MASK  0x00060000
+
+#define MH_DEBUG_REG02_MASK \
+     (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_tag_MASK | \
+      MH_DEBUG_REG02_RDC_RID_MASK | \
+      MH_DEBUG_REG02_RDC_RRESP_MASK | \
+      MH_DEBUG_REG02_MH_CP_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_RB_writeclean_MASK | \
+      MH_DEBUG_REG02_BRC_BID_MASK | \
+      MH_DEBUG_REG02_BRC_BRESP_MASK)
+
+#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, brc_bid, brc_bresp) \
+     ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \
+      (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \
+      (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \
+      (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \
+      (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \
+      (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \
+      (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT))
+
+#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int                                : 13;
+     } mh_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int                                : 13;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+     } mh_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg02_t f;
+} mh_debug_reg02_u;
+
+
+/*
+ * MH_DEBUG_REG03 struct
+ */
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG03_MASK \
+     (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK)
+
+#define MH_DEBUG_REG03(mh_clnt_data_31_0) \
+     ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \
+     ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \
+     mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg03_t f;
+} mh_debug_reg03_u;
+
+
+/*
+ * MH_DEBUG_REG04 struct
+ */
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG04_MASK \
+     (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK)
+
+#define MH_DEBUG_REG04(mh_clnt_data_63_32) \
+     ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \
+     ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \
+     mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg04_t f;
+} mh_debug_reg04_u;
+
+
+/*
+ * MH_DEBUG_REG05 struct
+ */
+
+#define MH_DEBUG_REG05_CP_MH_send_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_tag_SIZE  3
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0
+#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1
+#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002
+#define MH_DEBUG_REG05_CP_MH_tag_MASK  0x0000001c
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG05_MASK \
+     (MH_DEBUG_REG05_CP_MH_send_MASK | \
+      MH_DEBUG_REG05_CP_MH_write_MASK | \
+      MH_DEBUG_REG05_CP_MH_tag_MASK | \
+      MH_DEBUG_REG05_CP_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \
+     ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \
+      (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \
+      (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+     } mh_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+     } mh_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg05_t f;
+} mh_debug_reg05_u;
+
+
+/*
+ * MH_DEBUG_REG06 struct
+ */
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG06_MASK \
+     (MH_DEBUG_REG06_CP_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG06(cp_mh_data_31_0) \
+     ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \
+     ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \
+     mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg06_t f;
+} mh_debug_reg06_u;
+
+
+/*
+ * MH_DEBUG_REG07 struct
+ */
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG07_MASK \
+     (MH_DEBUG_REG07_CP_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG07(cp_mh_data_63_32) \
+     ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \
+     ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \
+     mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg07_t f;
+} mh_debug_reg07_u;
+
+
+/*
+ * MH_DEBUG_REG08 struct
+ */
+
+#define MH_DEBUG_REG08_ALWAYS_ZERO_SIZE 3
+#define MH_DEBUG_REG08_VGT_MH_send_SIZE 1
+#define MH_DEBUG_REG08_VGT_MH_tagbe_SIZE 1
+#define MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG08_VGT_MH_send_SHIFT 3
+#define MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT 4
+#define MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG08_ALWAYS_ZERO_MASK 0x00000007
+#define MH_DEBUG_REG08_VGT_MH_send_MASK 0x00000008
+#define MH_DEBUG_REG08_VGT_MH_tagbe_MASK 0x00000010
+#define MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG08_MASK \
+     (MH_DEBUG_REG08_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG08_VGT_MH_send_MASK | \
+      MH_DEBUG_REG08_VGT_MH_tagbe_MASK | \
+      MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG08(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \
+     ((always_zero << MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT) | \
+      (vgt_mh_send << MH_DEBUG_REG08_VGT_MH_send_SHIFT) | \
+      (vgt_mh_tagbe << MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT) | \
+      (vgt_mh_ad_31_5 << MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG08_GET_ALWAYS_ZERO(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG08_GET_VGT_MH_send(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_send_MASK) >> MH_DEBUG_REG08_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG08_GET_VGT_MH_tagbe(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG08_GET_VGT_MH_ad_31_5(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG08_SET_ALWAYS_ZERO(mh_debug_reg08_reg, always_zero) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG08_SET_VGT_MH_send(mh_debug_reg08_reg, vgt_mh_send) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG08_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG08_SET_VGT_MH_tagbe(mh_debug_reg08_reg, vgt_mh_tagbe) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG08_SET_VGT_MH_ad_31_5(mh_debug_reg08_reg, vgt_mh_ad_31_5) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int always_zero                    : MH_DEBUG_REG08_ALWAYS_ZERO_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG08_VGT_MH_send_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG08_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE;
+     } mh_debug_reg08_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG08_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG08_VGT_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG08_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg08_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg08_t f;
+} mh_debug_reg08_u;
+
+
+/*
+ * MH_DEBUG_REG09 struct
+ */
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG09_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG09_TC_MH_mask_SIZE 2
+#define MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG09_TC_MH_send_SHIFT 2
+#define MH_DEBUG_REG09_TC_MH_mask_SHIFT 3
+#define MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG09_TC_MH_send_MASK 0x00000004
+#define MH_DEBUG_REG09_TC_MH_mask_MASK 0x00000018
+#define MH_DEBUG_REG09_TC_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG09_MASK \
+     (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG09_TC_MH_send_MASK | \
+      MH_DEBUG_REG09_TC_MH_mask_MASK | \
+      MH_DEBUG_REG09_TC_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG09(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG09_TC_MH_send_SHIFT) | \
+      (tc_mh_mask << MH_DEBUG_REG09_TC_MH_mask_SHIFT) | \
+      (tc_mh_addr_31_5 << MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_GET_TC_MH_send(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_send_MASK) >> MH_DEBUG_REG09_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG09_GET_TC_MH_mask(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_mask_MASK) >> MH_DEBUG_REG09_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG09_GET_TC_MH_addr_31_5(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_SET_TC_MH_send(mh_debug_reg09_reg, tc_mh_send) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG09_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG09_SET_TC_MH_mask(mh_debug_reg09_reg, tc_mh_mask) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG09_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG09_SET_TC_MH_addr_31_5(mh_debug_reg09_reg, tc_mh_addr_31_5) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG09_TC_MH_send_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG09_TC_MH_mask_SIZE;
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE;
+     } mh_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG09_TC_MH_mask_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG09_TC_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg09_t f;
+} mh_debug_reg09_u;
+
+
+/*
+ * MH_DEBUG_REG10 struct
+ */
+
+#define MH_DEBUG_REG10_TC_MH_info_SIZE 25
+#define MH_DEBUG_REG10_TC_MH_send_SIZE 1
+
+#define MH_DEBUG_REG10_TC_MH_info_SHIFT 0
+#define MH_DEBUG_REG10_TC_MH_send_SHIFT 25
+
+#define MH_DEBUG_REG10_TC_MH_info_MASK 0x01ffffff
+#define MH_DEBUG_REG10_TC_MH_send_MASK 0x02000000
+
+#define MH_DEBUG_REG10_MASK \
+     (MH_DEBUG_REG10_TC_MH_info_MASK | \
+      MH_DEBUG_REG10_TC_MH_send_MASK)
+
+#define MH_DEBUG_REG10(tc_mh_info, tc_mh_send) \
+     ((tc_mh_info << MH_DEBUG_REG10_TC_MH_info_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT))
+
+#define MH_DEBUG_REG10_GET_TC_MH_info(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_info_MASK) >> MH_DEBUG_REG10_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT)
+
+#define MH_DEBUG_REG10_SET_TC_MH_info(mh_debug_reg10_reg, tc_mh_info) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG10_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int tc_mh_info                     : MH_DEBUG_REG10_TC_MH_info_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int                                : 6;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int tc_mh_info                     : MH_DEBUG_REG10_TC_MH_info_SIZE;
+     } mh_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg10_t f;
+} mh_debug_reg10_u;
+
+
+/*
+ * MH_DEBUG_REG11 struct
+ */
+
+#define MH_DEBUG_REG11_MH_TC_mcinfo_SIZE 25
+#define MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE 1
+#define MH_DEBUG_REG11_TC_MH_written_SIZE 1
+
+#define MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT 0
+#define MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT 25
+#define MH_DEBUG_REG11_TC_MH_written_SHIFT 26
+
+#define MH_DEBUG_REG11_MH_TC_mcinfo_MASK 0x01ffffff
+#define MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK 0x02000000
+#define MH_DEBUG_REG11_TC_MH_written_MASK 0x04000000
+
+#define MH_DEBUG_REG11_MASK \
+     (MH_DEBUG_REG11_MH_TC_mcinfo_MASK | \
+      MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK | \
+      MH_DEBUG_REG11_TC_MH_written_MASK)
+
+#define MH_DEBUG_REG11(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \
+     ((mh_tc_mcinfo << MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT) | \
+      (mh_tc_mcinfo_send << MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG11_TC_MH_written_SHIFT))
+
+#define MH_DEBUG_REG11_GET_MH_TC_mcinfo(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG11_GET_MH_TC_mcinfo_send(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG11_GET_TC_MH_written(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_written_MASK) >> MH_DEBUG_REG11_TC_MH_written_SHIFT)
+
+#define MH_DEBUG_REG11_SET_MH_TC_mcinfo(mh_debug_reg11_reg, mh_tc_mcinfo) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG11_SET_MH_TC_mcinfo_send(mh_debug_reg11_reg, mh_tc_mcinfo_send) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG11_SET_TC_MH_written(mh_debug_reg11_reg, tc_mh_written) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG11_TC_MH_written_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG11_MH_TC_mcinfo_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG11_TC_MH_written_SIZE;
+          unsigned int                                : 5;
+     } mh_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int                                : 5;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG11_TC_MH_written_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE;
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG11_MH_TC_mcinfo_SIZE;
+     } mh_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg11_t f;
+} mh_debug_reg11_u;
+
+
+/*
+ * MH_DEBUG_REG12 struct
+ */
+
+#define MH_DEBUG_REG12_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG12_TC_ROQ_SEND_SIZE 1
+#define MH_DEBUG_REG12_TC_ROQ_MASK_SIZE 2
+#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE 27
+
+#define MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT 2
+#define MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT 3
+#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT 5
+
+#define MH_DEBUG_REG12_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG12_TC_ROQ_SEND_MASK 0x00000004
+#define MH_DEBUG_REG12_TC_ROQ_MASK_MASK 0x00000018
+#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG12_MASK \
+     (MH_DEBUG_REG12_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG12_TC_ROQ_SEND_MASK | \
+      MH_DEBUG_REG12_TC_ROQ_MASK_MASK | \
+      MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK)
+
+#define MH_DEBUG_REG12(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT) | \
+      (tc_roq_mask << MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT) | \
+      (tc_roq_addr_31_5 << MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT))
+
+#define MH_DEBUG_REG12_GET_ALWAYS_ZERO(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_ROQ_SEND(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_ROQ_MASK(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_ROQ_ADDR_31_5(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT)
+
+#define MH_DEBUG_REG12_SET_ALWAYS_ZERO(mh_debug_reg12_reg, always_zero) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_ROQ_SEND(mh_debug_reg12_reg, tc_roq_send) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_ROQ_MASK(mh_debug_reg12_reg, tc_roq_mask) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_ROQ_ADDR_31_5(mh_debug_reg12_reg, tc_roq_addr_31_5) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int always_zero                    : MH_DEBUG_REG12_ALWAYS_ZERO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG12_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG12_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE;
+     } mh_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG12_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG12_TC_ROQ_SEND_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG12_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg12_t f;
+} mh_debug_reg12_u;
+
+
+/*
+ * MH_DEBUG_REG13 struct
+ */
+
+#define MH_DEBUG_REG13_TC_ROQ_INFO_SIZE 25
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1
+
+#define MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT 0
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 25
+
+#define MH_DEBUG_REG13_TC_ROQ_INFO_MASK 0x01ffffff
+#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x02000000
+
+#define MH_DEBUG_REG13_MASK \
+     (MH_DEBUG_REG13_TC_ROQ_INFO_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_SEND_MASK)
+
+#define MH_DEBUG_REG13(tc_roq_info, tc_roq_send) \
+     ((tc_roq_info << MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT))
+
+#define MH_DEBUG_REG13_GET_TC_ROQ_INFO(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+
+#define MH_DEBUG_REG13_SET_TC_ROQ_INFO(mh_debug_reg13_reg, tc_roq_info) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int tc_roq_info                    : MH_DEBUG_REG13_TC_ROQ_INFO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int                                : 6;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_info                    : MH_DEBUG_REG13_TC_ROQ_INFO_SIZE;
+     } mh_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg13_t f;
+} mh_debug_reg13_u;
+
+
+/*
+ * MH_DEBUG_REG14 struct
+ */
+
+#define MH_DEBUG_REG14_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG14_RB_MH_send_SIZE 1
+#define MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG14_RB_MH_send_SHIFT 4
+#define MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG14_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG14_RB_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG14_RB_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG14_MASK \
+     (MH_DEBUG_REG14_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG14_RB_MH_send_MASK | \
+      MH_DEBUG_REG14_RB_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG14(always_zero, rb_mh_send, rb_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT) | \
+      (rb_mh_send << MH_DEBUG_REG14_RB_MH_send_SHIFT) | \
+      (rb_mh_addr_31_5 << MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG14_GET_ALWAYS_ZERO(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG14_GET_RB_MH_send(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_RB_MH_send_MASK) >> MH_DEBUG_REG14_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG14_GET_RB_MH_addr_31_5(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG14_SET_ALWAYS_ZERO(mh_debug_reg14_reg, always_zero) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG14_SET_RB_MH_send(mh_debug_reg14_reg, rb_mh_send) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG14_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG14_SET_RB_MH_addr_31_5(mh_debug_reg14_reg, rb_mh_addr_31_5) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int always_zero                    : MH_DEBUG_REG14_ALWAYS_ZERO_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG14_RB_MH_send_SIZE;
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE;
+     } mh_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG14_RB_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG14_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg14_t f;
+} mh_debug_reg14_u;
+
+
+/*
+ * MH_DEBUG_REG15 struct
+ */
+
+#define MH_DEBUG_REG15_RB_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG15_RB_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG15_MASK \
+     (MH_DEBUG_REG15_RB_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG15(rb_mh_data_31_0) \
+     ((rb_mh_data_31_0 << MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG15_GET_RB_MH_data_31_0(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG15_SET_RB_MH_data_31_0(mh_debug_reg15_reg, rb_mh_data_31_0) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG15_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG15_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg15_t f;
+} mh_debug_reg15_u;
+
+
+/*
+ * MH_DEBUG_REG16 struct
+ */
+
+#define MH_DEBUG_REG16_RB_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG16_RB_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG16_MASK \
+     (MH_DEBUG_REG16_RB_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG16(rb_mh_data_63_32) \
+     ((rb_mh_data_63_32 << MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG16_GET_RB_MH_data_63_32(mh_debug_reg16) \
+     ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG16_SET_RB_MH_data_63_32(mh_debug_reg16_reg, rb_mh_data_63_32) \
+     mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG16_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG16_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg16_t f;
+} mh_debug_reg16_u;
+
+
+/*
+ * MH_DEBUG_REG17 struct
+ */
+
+#define MH_DEBUG_REG17_AVALID_q_SIZE   1
+#define MH_DEBUG_REG17_AREADY_q_SIZE   1
+#define MH_DEBUG_REG17_AID_q_SIZE      3
+#define MH_DEBUG_REG17_ALEN_q_2_0_SIZE 3
+#define MH_DEBUG_REG17_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG17_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG17_ARID_q_SIZE     3
+#define MH_DEBUG_REG17_ARLEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG17_RVALID_q_SIZE   1
+#define MH_DEBUG_REG17_RREADY_q_SIZE   1
+#define MH_DEBUG_REG17_RLAST_q_SIZE    1
+#define MH_DEBUG_REG17_RID_q_SIZE      3
+#define MH_DEBUG_REG17_WVALID_q_SIZE   1
+#define MH_DEBUG_REG17_WREADY_q_SIZE   1
+#define MH_DEBUG_REG17_WLAST_q_SIZE    1
+#define MH_DEBUG_REG17_WID_q_SIZE      3
+#define MH_DEBUG_REG17_BVALID_q_SIZE   1
+#define MH_DEBUG_REG17_BREADY_q_SIZE   1
+#define MH_DEBUG_REG17_BID_q_SIZE      3
+
+#define MH_DEBUG_REG17_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG17_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG17_AID_q_SHIFT     2
+#define MH_DEBUG_REG17_ALEN_q_2_0_SHIFT 5
+#define MH_DEBUG_REG17_ARVALID_q_SHIFT 8
+#define MH_DEBUG_REG17_ARREADY_q_SHIFT 9
+#define MH_DEBUG_REG17_ARID_q_SHIFT    10
+#define MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT 13
+#define MH_DEBUG_REG17_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG17_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG17_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG17_RID_q_SHIFT     18
+#define MH_DEBUG_REG17_WVALID_q_SHIFT  21
+#define MH_DEBUG_REG17_WREADY_q_SHIFT  22
+#define MH_DEBUG_REG17_WLAST_q_SHIFT   23
+#define MH_DEBUG_REG17_WID_q_SHIFT     24
+#define MH_DEBUG_REG17_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG17_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG17_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG17_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG17_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG17_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG17_ALEN_q_2_0_MASK 0x000000e0
+#define MH_DEBUG_REG17_ARVALID_q_MASK  0x00000100
+#define MH_DEBUG_REG17_ARREADY_q_MASK  0x00000200
+#define MH_DEBUG_REG17_ARID_q_MASK     0x00001c00
+#define MH_DEBUG_REG17_ARLEN_q_1_0_MASK 0x00006000
+#define MH_DEBUG_REG17_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG17_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG17_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG17_RID_q_MASK      0x001c0000
+#define MH_DEBUG_REG17_WVALID_q_MASK   0x00200000
+#define MH_DEBUG_REG17_WREADY_q_MASK   0x00400000
+#define MH_DEBUG_REG17_WLAST_q_MASK    0x00800000
+#define MH_DEBUG_REG17_WID_q_MASK      0x07000000
+#define MH_DEBUG_REG17_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG17_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG17_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG17_MASK \
+     (MH_DEBUG_REG17_AVALID_q_MASK | \
+      MH_DEBUG_REG17_AREADY_q_MASK | \
+      MH_DEBUG_REG17_AID_q_MASK | \
+      MH_DEBUG_REG17_ALEN_q_2_0_MASK | \
+      MH_DEBUG_REG17_ARVALID_q_MASK | \
+      MH_DEBUG_REG17_ARREADY_q_MASK | \
+      MH_DEBUG_REG17_ARID_q_MASK | \
+      MH_DEBUG_REG17_ARLEN_q_1_0_MASK | \
+      MH_DEBUG_REG17_RVALID_q_MASK | \
+      MH_DEBUG_REG17_RREADY_q_MASK | \
+      MH_DEBUG_REG17_RLAST_q_MASK | \
+      MH_DEBUG_REG17_RID_q_MASK | \
+      MH_DEBUG_REG17_WVALID_q_MASK | \
+      MH_DEBUG_REG17_WREADY_q_MASK | \
+      MH_DEBUG_REG17_WLAST_q_MASK | \
+      MH_DEBUG_REG17_WID_q_MASK | \
+      MH_DEBUG_REG17_BVALID_q_MASK | \
+      MH_DEBUG_REG17_BREADY_q_MASK | \
+      MH_DEBUG_REG17_BID_q_MASK)
+
+#define MH_DEBUG_REG17(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG17_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG17_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG17_AID_q_SHIFT) | \
+      (alen_q_2_0 << MH_DEBUG_REG17_ALEN_q_2_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG17_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG17_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG17_ARID_q_SHIFT) | \
+      (arlen_q_1_0 << MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG17_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG17_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG17_RLAST_q_SHIFT) | \
+      (rid_q << MH_DEBUG_REG17_RID_q_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG17_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG17_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG17_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG17_WID_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG17_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG17_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG17_BID_q_SHIFT))
+
+#define MH_DEBUG_REG17_GET_AVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_AVALID_q_MASK) >> MH_DEBUG_REG17_AVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_AREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_AREADY_q_MASK) >> MH_DEBUG_REG17_AREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_AID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_AID_q_MASK) >> MH_DEBUG_REG17_AID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_ALEN_q_2_0(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ALEN_q_2_0_MASK) >> MH_DEBUG_REG17_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG17_GET_ARVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ARVALID_q_MASK) >> MH_DEBUG_REG17_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_ARREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ARREADY_q_MASK) >> MH_DEBUG_REG17_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_ARID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ARID_q_MASK) >> MH_DEBUG_REG17_ARID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_ARLEN_q_1_0(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG17_GET_RVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RVALID_q_MASK) >> MH_DEBUG_REG17_RVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_RREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RREADY_q_MASK) >> MH_DEBUG_REG17_RREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_RLAST_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RLAST_q_MASK) >> MH_DEBUG_REG17_RLAST_q_SHIFT)
+#define MH_DEBUG_REG17_GET_RID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RID_q_MASK) >> MH_DEBUG_REG17_RID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_WVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_WVALID_q_MASK) >> MH_DEBUG_REG17_WVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_WREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_WREADY_q_MASK) >> MH_DEBUG_REG17_WREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_WLAST_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_WLAST_q_MASK) >> MH_DEBUG_REG17_WLAST_q_SHIFT)
+#define MH_DEBUG_REG17_GET_WID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_WID_q_MASK) >> MH_DEBUG_REG17_WID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_BVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_BVALID_q_MASK) >> MH_DEBUG_REG17_BVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_BREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_BREADY_q_MASK) >> MH_DEBUG_REG17_BREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_BID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_BID_q_MASK) >> MH_DEBUG_REG17_BID_q_SHIFT)
+
+#define MH_DEBUG_REG17_SET_AVALID_q(mh_debug_reg17_reg, avalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG17_AVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_AREADY_q(mh_debug_reg17_reg, aready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG17_AREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_AID_q(mh_debug_reg17_reg, aid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AID_q_MASK) | (aid_q << MH_DEBUG_REG17_AID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_ALEN_q_2_0(mh_debug_reg17_reg, alen_q_2_0) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG17_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG17_SET_ARVALID_q(mh_debug_reg17_reg, arvalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG17_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_ARREADY_q(mh_debug_reg17_reg, arready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG17_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_ARID_q(mh_debug_reg17_reg, arid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARID_q_MASK) | (arid_q << MH_DEBUG_REG17_ARID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_ARLEN_q_1_0(mh_debug_reg17_reg, arlen_q_1_0) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG17_SET_RVALID_q(mh_debug_reg17_reg, rvalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG17_RVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_RREADY_q(mh_debug_reg17_reg, rready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG17_RREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_RLAST_q(mh_debug_reg17_reg, rlast_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG17_RLAST_q_SHIFT)
+#define MH_DEBUG_REG17_SET_RID_q(mh_debug_reg17_reg, rid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RID_q_MASK) | (rid_q << MH_DEBUG_REG17_RID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_WVALID_q(mh_debug_reg17_reg, wvalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG17_WVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_WREADY_q(mh_debug_reg17_reg, wready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG17_WREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_WLAST_q(mh_debug_reg17_reg, wlast_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG17_WLAST_q_SHIFT)
+#define MH_DEBUG_REG17_SET_WID_q(mh_debug_reg17_reg, wid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WID_q_MASK) | (wid_q << MH_DEBUG_REG17_WID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_BVALID_q(mh_debug_reg17_reg, bvalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG17_BVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_BREADY_q(mh_debug_reg17_reg, bready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG17_BREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_BID_q(mh_debug_reg17_reg, bid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BID_q_MASK) | (bid_q << MH_DEBUG_REG17_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG17_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG17_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG17_AID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG17_ALEN_q_2_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG17_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG17_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG17_ARID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG17_ARLEN_q_1_0_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG17_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG17_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG17_RLAST_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG17_RID_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG17_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG17_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG17_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG17_WID_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG17_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG17_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG17_BID_q_SIZE;
+     } mh_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int bid_q                          : MH_DEBUG_REG17_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG17_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG17_BVALID_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG17_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG17_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG17_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG17_WVALID_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG17_RID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG17_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG17_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG17_RVALID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG17_ARLEN_q_1_0_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG17_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG17_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG17_ARVALID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG17_ALEN_q_2_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG17_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG17_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG17_AVALID_q_SIZE;
+     } mh_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg17_t f;
+} mh_debug_reg17_u;
+
+
+/*
+ * MH_DEBUG_REG18 struct
+ */
+
+#define MH_DEBUG_REG18_AVALID_q_SIZE   1
+#define MH_DEBUG_REG18_AREADY_q_SIZE   1
+#define MH_DEBUG_REG18_AID_q_SIZE      3
+#define MH_DEBUG_REG18_ALEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG18_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG18_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG18_ARID_q_SIZE     3
+#define MH_DEBUG_REG18_ARLEN_q_1_1_SIZE 1
+#define MH_DEBUG_REG18_WVALID_q_SIZE   1
+#define MH_DEBUG_REG18_WREADY_q_SIZE   1
+#define MH_DEBUG_REG18_WLAST_q_SIZE    1
+#define MH_DEBUG_REG18_WID_q_SIZE      3
+#define MH_DEBUG_REG18_WSTRB_q_SIZE    8
+#define MH_DEBUG_REG18_BVALID_q_SIZE   1
+#define MH_DEBUG_REG18_BREADY_q_SIZE   1
+#define MH_DEBUG_REG18_BID_q_SIZE      3
+
+#define MH_DEBUG_REG18_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG18_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG18_AID_q_SHIFT     2
+#define MH_DEBUG_REG18_ALEN_q_1_0_SHIFT 5
+#define MH_DEBUG_REG18_ARVALID_q_SHIFT 7
+#define MH_DEBUG_REG18_ARREADY_q_SHIFT 8
+#define MH_DEBUG_REG18_ARID_q_SHIFT    9
+#define MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT 12
+#define MH_DEBUG_REG18_WVALID_q_SHIFT  13
+#define MH_DEBUG_REG18_WREADY_q_SHIFT  14
+#define MH_DEBUG_REG18_WLAST_q_SHIFT   15
+#define MH_DEBUG_REG18_WID_q_SHIFT     16
+#define MH_DEBUG_REG18_WSTRB_q_SHIFT   19
+#define MH_DEBUG_REG18_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG18_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG18_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG18_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG18_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG18_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG18_ALEN_q_1_0_MASK 0x00000060
+#define MH_DEBUG_REG18_ARVALID_q_MASK  0x00000080
+#define MH_DEBUG_REG18_ARREADY_q_MASK  0x00000100
+#define MH_DEBUG_REG18_ARID_q_MASK     0x00000e00
+#define MH_DEBUG_REG18_ARLEN_q_1_1_MASK 0x00001000
+#define MH_DEBUG_REG18_WVALID_q_MASK   0x00002000
+#define MH_DEBUG_REG18_WREADY_q_MASK   0x00004000
+#define MH_DEBUG_REG18_WLAST_q_MASK    0x00008000
+#define MH_DEBUG_REG18_WID_q_MASK      0x00070000
+#define MH_DEBUG_REG18_WSTRB_q_MASK    0x07f80000
+#define MH_DEBUG_REG18_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG18_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG18_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG18_MASK \
+     (MH_DEBUG_REG18_AVALID_q_MASK | \
+      MH_DEBUG_REG18_AREADY_q_MASK | \
+      MH_DEBUG_REG18_AID_q_MASK | \
+      MH_DEBUG_REG18_ALEN_q_1_0_MASK | \
+      MH_DEBUG_REG18_ARVALID_q_MASK | \
+      MH_DEBUG_REG18_ARREADY_q_MASK | \
+      MH_DEBUG_REG18_ARID_q_MASK | \
+      MH_DEBUG_REG18_ARLEN_q_1_1_MASK | \
+      MH_DEBUG_REG18_WVALID_q_MASK | \
+      MH_DEBUG_REG18_WREADY_q_MASK | \
+      MH_DEBUG_REG18_WLAST_q_MASK | \
+      MH_DEBUG_REG18_WID_q_MASK | \
+      MH_DEBUG_REG18_WSTRB_q_MASK | \
+      MH_DEBUG_REG18_BVALID_q_MASK | \
+      MH_DEBUG_REG18_BREADY_q_MASK | \
+      MH_DEBUG_REG18_BID_q_MASK)
+
+#define MH_DEBUG_REG18(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG18_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG18_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG18_AID_q_SHIFT) | \
+      (alen_q_1_0 << MH_DEBUG_REG18_ALEN_q_1_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG18_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG18_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG18_ARID_q_SHIFT) | \
+      (arlen_q_1_1 << MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG18_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG18_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG18_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG18_WID_q_SHIFT) | \
+      (wstrb_q << MH_DEBUG_REG18_WSTRB_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG18_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG18_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG18_BID_q_SHIFT))
+
+#define MH_DEBUG_REG18_GET_AVALID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_AVALID_q_MASK) >> MH_DEBUG_REG18_AVALID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_AREADY_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_AREADY_q_MASK) >> MH_DEBUG_REG18_AREADY_q_SHIFT)
+#define MH_DEBUG_REG18_GET_AID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_AID_q_MASK) >> MH_DEBUG_REG18_AID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_ALEN_q_1_0(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ALEN_q_1_0_MASK) >> MH_DEBUG_REG18_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG18_GET_ARVALID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ARVALID_q_MASK) >> MH_DEBUG_REG18_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_ARREADY_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ARREADY_q_MASK) >> MH_DEBUG_REG18_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG18_GET_ARID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ARID_q_MASK) >> MH_DEBUG_REG18_ARID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_ARLEN_q_1_1(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG18_GET_WVALID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WVALID_q_MASK) >> MH_DEBUG_REG18_WVALID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_WREADY_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WREADY_q_MASK) >> MH_DEBUG_REG18_WREADY_q_SHIFT)
+#define MH_DEBUG_REG18_GET_WLAST_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WLAST_q_MASK) >> MH_DEBUG_REG18_WLAST_q_SHIFT)
+#define MH_DEBUG_REG18_GET_WID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WID_q_MASK) >> MH_DEBUG_REG18_WID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_WSTRB_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WSTRB_q_MASK) >> MH_DEBUG_REG18_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG18_GET_BVALID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_BVALID_q_MASK) >> MH_DEBUG_REG18_BVALID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_BREADY_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_BREADY_q_MASK) >> MH_DEBUG_REG18_BREADY_q_SHIFT)
+#define MH_DEBUG_REG18_GET_BID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_BID_q_MASK) >> MH_DEBUG_REG18_BID_q_SHIFT)
+
+#define MH_DEBUG_REG18_SET_AVALID_q(mh_debug_reg18_reg, avalid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG18_AVALID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_AREADY_q(mh_debug_reg18_reg, aready_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG18_AREADY_q_SHIFT)
+#define MH_DEBUG_REG18_SET_AID_q(mh_debug_reg18_reg, aid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AID_q_MASK) | (aid_q << MH_DEBUG_REG18_AID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_ALEN_q_1_0(mh_debug_reg18_reg, alen_q_1_0) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG18_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG18_SET_ARVALID_q(mh_debug_reg18_reg, arvalid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG18_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_ARREADY_q(mh_debug_reg18_reg, arready_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG18_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG18_SET_ARID_q(mh_debug_reg18_reg, arid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARID_q_MASK) | (arid_q << MH_DEBUG_REG18_ARID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_ARLEN_q_1_1(mh_debug_reg18_reg, arlen_q_1_1) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG18_SET_WVALID_q(mh_debug_reg18_reg, wvalid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG18_WVALID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_WREADY_q(mh_debug_reg18_reg, wready_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG18_WREADY_q_SHIFT)
+#define MH_DEBUG_REG18_SET_WLAST_q(mh_debug_reg18_reg, wlast_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG18_WLAST_q_SHIFT)
+#define MH_DEBUG_REG18_SET_WID_q(mh_debug_reg18_reg, wid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WID_q_MASK) | (wid_q << MH_DEBUG_REG18_WID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_WSTRB_q(mh_debug_reg18_reg, wstrb_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG18_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG18_SET_BVALID_q(mh_debug_reg18_reg, bvalid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG18_BVALID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_BREADY_q(mh_debug_reg18_reg, bready_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG18_BREADY_q_SHIFT)
+#define MH_DEBUG_REG18_SET_BID_q(mh_debug_reg18_reg, bid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BID_q_MASK) | (bid_q << MH_DEBUG_REG18_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG18_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG18_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG18_AID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG18_ALEN_q_1_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG18_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG18_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG18_ARID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG18_ARLEN_q_1_1_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG18_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG18_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG18_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG18_WID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG18_WSTRB_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG18_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG18_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG18_BID_q_SIZE;
+     } mh_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int bid_q                          : MH_DEBUG_REG18_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG18_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG18_BVALID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG18_WSTRB_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG18_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG18_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG18_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG18_WVALID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG18_ARLEN_q_1_1_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG18_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG18_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG18_ARVALID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG18_ALEN_q_1_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG18_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG18_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG18_AVALID_q_SIZE;
+     } mh_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg18_t f;
+} mh_debug_reg18_u;
+
+
+/*
+ * MH_DEBUG_REG19 struct
+ */
+
+#define MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG19_CTRL_ARC_ID_SIZE 3
+#define MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE 28
+
+#define MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT 0
+#define MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT 1
+#define MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT 4
+
+#define MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK 0x00000001
+#define MH_DEBUG_REG19_CTRL_ARC_ID_MASK 0x0000000e
+#define MH_DEBUG_REG19_CTRL_ARC_PAD_MASK 0xfffffff0
+
+#define MH_DEBUG_REG19_MASK \
+     (MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG19_CTRL_ARC_ID_MASK | \
+      MH_DEBUG_REG19_CTRL_ARC_PAD_MASK)
+
+#define MH_DEBUG_REG19(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \
+     ((arc_ctrl_re_q << MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT) | \
+      (ctrl_arc_id << MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT) | \
+      (ctrl_arc_pad << MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT))
+
+#define MH_DEBUG_REG19_GET_ARC_CTRL_RE_q(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG19_GET_CTRL_ARC_ID(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG19_GET_CTRL_ARC_PAD(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT)
+
+#define MH_DEBUG_REG19_SET_ARC_CTRL_RE_q(mh_debug_reg19_reg, arc_ctrl_re_q) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG19_SET_CTRL_ARC_ID(mh_debug_reg19_reg, ctrl_arc_id) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG19_SET_CTRL_ARC_PAD(mh_debug_reg19_reg, ctrl_arc_pad) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG19_CTRL_ARC_ID_SIZE;
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE;
+     } mh_debug_reg19_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG19_CTRL_ARC_ID_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE;
+     } mh_debug_reg19_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg19_t f;
+} mh_debug_reg19_u;
+
+
+/*
+ * MH_DEBUG_REG20 struct
+ */
+
+#define MH_DEBUG_REG20_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG20_REG_A_SIZE      14
+#define MH_DEBUG_REG20_REG_RE_SIZE     1
+#define MH_DEBUG_REG20_REG_WE_SIZE     1
+#define MH_DEBUG_REG20_BLOCK_RS_SIZE   1
+
+#define MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG20_REG_A_SHIFT     2
+#define MH_DEBUG_REG20_REG_RE_SHIFT    16
+#define MH_DEBUG_REG20_REG_WE_SHIFT    17
+#define MH_DEBUG_REG20_BLOCK_RS_SHIFT  18
+
+#define MH_DEBUG_REG20_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG20_REG_A_MASK      0x0000fffc
+#define MH_DEBUG_REG20_REG_RE_MASK     0x00010000
+#define MH_DEBUG_REG20_REG_WE_MASK     0x00020000
+#define MH_DEBUG_REG20_BLOCK_RS_MASK   0x00040000
+
+#define MH_DEBUG_REG20_MASK \
+     (MH_DEBUG_REG20_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG20_REG_A_MASK | \
+      MH_DEBUG_REG20_REG_RE_MASK | \
+      MH_DEBUG_REG20_REG_WE_MASK | \
+      MH_DEBUG_REG20_BLOCK_RS_MASK)
+
+#define MH_DEBUG_REG20(always_zero, reg_a, reg_re, reg_we, block_rs) \
+     ((always_zero << MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT) | \
+      (reg_a << MH_DEBUG_REG20_REG_A_SHIFT) | \
+      (reg_re << MH_DEBUG_REG20_REG_RE_SHIFT) | \
+      (reg_we << MH_DEBUG_REG20_REG_WE_SHIFT) | \
+      (block_rs << MH_DEBUG_REG20_BLOCK_RS_SHIFT))
+
+#define MH_DEBUG_REG20_GET_ALWAYS_ZERO(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG20_GET_REG_A(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_REG_A_MASK) >> MH_DEBUG_REG20_REG_A_SHIFT)
+#define MH_DEBUG_REG20_GET_REG_RE(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_REG_RE_MASK) >> MH_DEBUG_REG20_REG_RE_SHIFT)
+#define MH_DEBUG_REG20_GET_REG_WE(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_REG_WE_MASK) >> MH_DEBUG_REG20_REG_WE_SHIFT)
+#define MH_DEBUG_REG20_GET_BLOCK_RS(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_BLOCK_RS_MASK) >> MH_DEBUG_REG20_BLOCK_RS_SHIFT)
+
+#define MH_DEBUG_REG20_SET_ALWAYS_ZERO(mh_debug_reg20_reg, always_zero) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG20_SET_REG_A(mh_debug_reg20_reg, reg_a) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_A_MASK) | (reg_a << MH_DEBUG_REG20_REG_A_SHIFT)
+#define MH_DEBUG_REG20_SET_REG_RE(mh_debug_reg20_reg, reg_re) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_RE_MASK) | (reg_re << MH_DEBUG_REG20_REG_RE_SHIFT)
+#define MH_DEBUG_REG20_SET_REG_WE(mh_debug_reg20_reg, reg_we) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_WE_MASK) | (reg_we << MH_DEBUG_REG20_REG_WE_SHIFT)
+#define MH_DEBUG_REG20_SET_BLOCK_RS(mh_debug_reg20_reg, block_rs) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG20_BLOCK_RS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int always_zero                    : MH_DEBUG_REG20_ALWAYS_ZERO_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG20_REG_A_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG20_REG_RE_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG20_REG_WE_SIZE;
+          unsigned int block_rs                       : MH_DEBUG_REG20_BLOCK_RS_SIZE;
+          unsigned int                                : 13;
+     } mh_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int                                : 13;
+          unsigned int block_rs                       : MH_DEBUG_REG20_BLOCK_RS_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG20_REG_WE_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG20_REG_RE_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG20_REG_A_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG20_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg20_t f;
+} mh_debug_reg20_u;
+
+
+/*
+ * MH_DEBUG_REG21 struct
+ */
+
+#define MH_DEBUG_REG21_REG_WD_SIZE     32
+
+#define MH_DEBUG_REG21_REG_WD_SHIFT    0
+
+#define MH_DEBUG_REG21_REG_WD_MASK     0xffffffff
+
+#define MH_DEBUG_REG21_MASK \
+     (MH_DEBUG_REG21_REG_WD_MASK)
+
+#define MH_DEBUG_REG21(reg_wd) \
+     ((reg_wd << MH_DEBUG_REG21_REG_WD_SHIFT))
+
+#define MH_DEBUG_REG21_GET_REG_WD(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_REG_WD_MASK) >> MH_DEBUG_REG21_REG_WD_SHIFT)
+
+#define MH_DEBUG_REG21_SET_REG_WD(mh_debug_reg21_reg, reg_wd) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG21_REG_WD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG21_REG_WD_SIZE;
+     } mh_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG21_REG_WD_SIZE;
+     } mh_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg21_t f;
+} mh_debug_reg21_u;
+
+
+/*
+ * MH_DEBUG_REG22 struct
+ */
+
+#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE 1
+#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE 1
+#define MH_DEBUG_REG22_MH_RBBM_busy_SIZE 1
+#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE 1
+#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE 1
+#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE 1
+#define MH_DEBUG_REG22_GAT_CLK_ENA_SIZE 1
+#define MH_DEBUG_REG22_AXI_RDY_ENA_SIZE 1
+#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE 1
+#define MH_DEBUG_REG22_CNT_q_SIZE      6
+#define MH_DEBUG_REG22_TCD_EMPTY_q_SIZE 1
+#define MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG22_MH_BUSY_d_SIZE  1
+#define MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE 1
+#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_DEBUG_REG22_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG22_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG22_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG22_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG22_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG22_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG22_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG22_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG22_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG22_BRC_VALID_SIZE  1
+
+#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT 0
+#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT 1
+#define MH_DEBUG_REG22_MH_RBBM_busy_SHIFT 2
+#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT 3
+#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT 4
+#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT 5
+#define MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT 6
+#define MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT 7
+#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT 8
+#define MH_DEBUG_REG22_CNT_q_SHIFT     9
+#define MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT 15
+#define MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT 16
+#define MH_DEBUG_REG22_MH_BUSY_d_SHIFT 17
+#define MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT 18
+#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 19
+#define MH_DEBUG_REG22_CP_SEND_q_SHIFT 20
+#define MH_DEBUG_REG22_CP_RTR_q_SHIFT  21
+#define MH_DEBUG_REG22_VGT_SEND_q_SHIFT 22
+#define MH_DEBUG_REG22_VGT_RTR_q_SHIFT 23
+#define MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT 24
+#define MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG22_RB_SEND_q_SHIFT 26
+#define MH_DEBUG_REG22_RB_RTR_q_SHIFT  27
+#define MH_DEBUG_REG22_RDC_VALID_SHIFT 28
+#define MH_DEBUG_REG22_RDC_RLAST_SHIFT 29
+#define MH_DEBUG_REG22_TLBMISS_VALID_SHIFT 30
+#define MH_DEBUG_REG22_BRC_VALID_SHIFT 31
+
+#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK 0x00000001
+#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK 0x00000002
+#define MH_DEBUG_REG22_MH_RBBM_busy_MASK 0x00000004
+#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK 0x00000008
+#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK 0x00000010
+#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK 0x00000020
+#define MH_DEBUG_REG22_GAT_CLK_ENA_MASK 0x00000040
+#define MH_DEBUG_REG22_AXI_RDY_ENA_MASK 0x00000080
+#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK 0x00000100
+#define MH_DEBUG_REG22_CNT_q_MASK      0x00007e00
+#define MH_DEBUG_REG22_TCD_EMPTY_q_MASK 0x00008000
+#define MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK 0x00010000
+#define MH_DEBUG_REG22_MH_BUSY_d_MASK  0x00020000
+#define MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK 0x00040000
+#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00080000
+#define MH_DEBUG_REG22_CP_SEND_q_MASK  0x00100000
+#define MH_DEBUG_REG22_CP_RTR_q_MASK   0x00200000
+#define MH_DEBUG_REG22_VGT_SEND_q_MASK 0x00400000
+#define MH_DEBUG_REG22_VGT_RTR_q_MASK  0x00800000
+#define MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK 0x01000000
+#define MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG22_RB_SEND_q_MASK  0x04000000
+#define MH_DEBUG_REG22_RB_RTR_q_MASK   0x08000000
+#define MH_DEBUG_REG22_RDC_VALID_MASK  0x10000000
+#define MH_DEBUG_REG22_RDC_RLAST_MASK  0x20000000
+#define MH_DEBUG_REG22_TLBMISS_VALID_MASK 0x40000000
+#define MH_DEBUG_REG22_BRC_VALID_MASK  0x80000000
+
+#define MH_DEBUG_REG22_MASK \
+     (MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK | \
+      MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK | \
+      MH_DEBUG_REG22_MH_RBBM_busy_MASK | \
+      MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK | \
+      MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK | \
+      MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK | \
+      MH_DEBUG_REG22_GAT_CLK_ENA_MASK | \
+      MH_DEBUG_REG22_AXI_RDY_ENA_MASK | \
+      MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK | \
+      MH_DEBUG_REG22_CNT_q_MASK | \
+      MH_DEBUG_REG22_TCD_EMPTY_q_MASK | \
+      MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG22_MH_BUSY_d_MASK | \
+      MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK | \
+      MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_DEBUG_REG22_CP_SEND_q_MASK | \
+      MH_DEBUG_REG22_CP_RTR_q_MASK | \
+      MH_DEBUG_REG22_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG22_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG22_RB_SEND_q_MASK | \
+      MH_DEBUG_REG22_RB_RTR_q_MASK | \
+      MH_DEBUG_REG22_RDC_VALID_MASK | \
+      MH_DEBUG_REG22_RDC_RLAST_MASK | \
+      MH_DEBUG_REG22_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG22_BRC_VALID_MASK)
+
+#define MH_DEBUG_REG22(cib_mh_axi_halt_req, mh_cib_axi_halt_ack, mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, axi_rdy_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_q, rb_send_q, rb_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \
+     ((cib_mh_axi_halt_req << MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT) | \
+      (mh_cib_axi_halt_ack << MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT) | \
+      (mh_rbbm_busy << MH_DEBUG_REG22_MH_RBBM_busy_SHIFT) | \
+      (mh_cib_mh_clk_en_int << MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT) | \
+      (mh_cib_mmu_clk_en_int << MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT) | \
+      (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT) | \
+      (gat_clk_ena << MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT) | \
+      (axi_rdy_ena << MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT) | \
+      (rbbm_mh_clk_en_override << MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT) | \
+      (cnt_q << MH_DEBUG_REG22_CNT_q_SHIFT) | \
+      (tcd_empty_q << MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT) | \
+      (mh_busy_d << MH_DEBUG_REG22_MH_BUSY_d_SHIFT) | \
+      (any_clnt_busy << MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (cp_send_q << MH_DEBUG_REG22_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG22_CP_RTR_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG22_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG22_VGT_RTR_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG22_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG22_RB_RTR_q_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG22_RDC_VALID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG22_RDC_RLAST_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG22_TLBMISS_VALID_SHIFT) | \
+      (brc_valid << MH_DEBUG_REG22_BRC_VALID_SHIFT))
+
+#define MH_DEBUG_REG22_GET_CIB_MH_axi_halt_req(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK) >> MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_CIB_axi_halt_ack(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK) >> MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_RBBM_busy(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_RBBM_busy_MASK) >> MH_DEBUG_REG22_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_CIB_mh_clk_en_int(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_GET_GAT_CLK_ENA(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG22_GET_AXI_RDY_ENA(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT)
+#define MH_DEBUG_REG22_GET_RBBM_MH_clk_en_override(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG22_GET_CNT_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_CNT_q_MASK) >> MH_DEBUG_REG22_CNT_q_SHIFT)
+#define MH_DEBUG_REG22_GET_TCD_EMPTY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_TC_ROQ_EMPTY(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_BUSY_d(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_BUSY_d_MASK) >> MH_DEBUG_REG22_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG22_GET_ANY_CLNT_BUSY(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG22_GET_CP_SEND_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_CP_SEND_q_MASK) >> MH_DEBUG_REG22_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_GET_CP_RTR_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_CP_RTR_q_MASK) >> MH_DEBUG_REG22_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_GET_VGT_SEND_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_VGT_SEND_q_MASK) >> MH_DEBUG_REG22_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_GET_VGT_RTR_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_VGT_RTR_q_MASK) >> MH_DEBUG_REG22_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_GET_TC_ROQ_SEND_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_GET_TC_ROQ_RTR_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_GET_RB_SEND_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RB_SEND_q_MASK) >> MH_DEBUG_REG22_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_GET_RB_RTR_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RB_RTR_q_MASK) >> MH_DEBUG_REG22_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_GET_RDC_VALID(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RDC_VALID_MASK) >> MH_DEBUG_REG22_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG22_GET_RDC_RLAST(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RDC_RLAST_MASK) >> MH_DEBUG_REG22_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG22_GET_TLBMISS_VALID(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TLBMISS_VALID_MASK) >> MH_DEBUG_REG22_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG22_GET_BRC_VALID(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BRC_VALID_MASK) >> MH_DEBUG_REG22_BRC_VALID_SHIFT)
+
+#define MH_DEBUG_REG22_SET_CIB_MH_axi_halt_req(mh_debug_reg22_reg, cib_mh_axi_halt_req) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK) | (cib_mh_axi_halt_req << MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_CIB_axi_halt_ack(mh_debug_reg22_reg, mh_cib_axi_halt_ack) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK) | (mh_cib_axi_halt_ack << MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_RBBM_busy(mh_debug_reg22_reg, mh_rbbm_busy) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG22_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_CIB_mh_clk_en_int(mh_debug_reg22_reg, mh_cib_mh_clk_en_int) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg22_reg, mh_cib_mmu_clk_en_int) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg22_reg, mh_cib_tcroq_clk_en_int) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_SET_GAT_CLK_ENA(mh_debug_reg22_reg, gat_clk_ena) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG22_SET_AXI_RDY_ENA(mh_debug_reg22_reg, axi_rdy_ena) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT)
+#define MH_DEBUG_REG22_SET_RBBM_MH_clk_en_override(mh_debug_reg22_reg, rbbm_mh_clk_en_override) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG22_SET_CNT_q(mh_debug_reg22_reg, cnt_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG22_CNT_q_SHIFT)
+#define MH_DEBUG_REG22_SET_TCD_EMPTY_q(mh_debug_reg22_reg, tcd_empty_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_TC_ROQ_EMPTY(mh_debug_reg22_reg, tc_roq_empty) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_BUSY_d(mh_debug_reg22_reg, mh_busy_d) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG22_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG22_SET_ANY_CLNT_BUSY(mh_debug_reg22_reg, any_clnt_busy) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg22_reg, mh_mmu_invalidate_invalidate_all) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG22_SET_CP_SEND_q(mh_debug_reg22_reg, cp_send_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG22_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_SET_CP_RTR_q(mh_debug_reg22_reg, cp_rtr_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG22_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_SET_VGT_SEND_q(mh_debug_reg22_reg, vgt_send_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG22_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_SET_VGT_RTR_q(mh_debug_reg22_reg, vgt_rtr_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG22_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_SET_TC_ROQ_SEND_q(mh_debug_reg22_reg, tc_roq_send_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_SET_TC_ROQ_RTR_q(mh_debug_reg22_reg, tc_roq_rtr_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_SET_RB_SEND_q(mh_debug_reg22_reg, rb_send_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG22_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_SET_RB_RTR_q(mh_debug_reg22_reg, rb_rtr_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG22_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_SET_RDC_VALID(mh_debug_reg22_reg, rdc_valid) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG22_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG22_SET_RDC_RLAST(mh_debug_reg22_reg, rdc_rlast) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG22_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG22_SET_TLBMISS_VALID(mh_debug_reg22_reg, tlbmiss_valid) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG22_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG22_SET_BRC_VALID(mh_debug_reg22_reg, brc_valid) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG22_BRC_VALID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int cib_mh_axi_halt_req            : MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE;
+          unsigned int mh_cib_axi_halt_ack            : MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE;
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG22_MH_RBBM_busy_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG22_GAT_CLK_ENA_SIZE;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG22_AXI_RDY_ENA_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG22_CNT_q_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG22_TCD_EMPTY_q_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG22_MH_BUSY_d_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG22_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG22_CP_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG22_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG22_VGT_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG22_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG22_RB_RTR_q_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG22_RDC_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG22_RDC_RLAST_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG22_TLBMISS_VALID_SIZE;
+          unsigned int brc_valid                      : MH_DEBUG_REG22_BRC_VALID_SIZE;
+     } mh_debug_reg22_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int brc_valid                      : MH_DEBUG_REG22_BRC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG22_TLBMISS_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG22_RDC_RLAST_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG22_RDC_VALID_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG22_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG22_RB_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG22_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG22_VGT_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG22_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG22_CP_SEND_q_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG22_MH_BUSY_d_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG22_TCD_EMPTY_q_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG22_CNT_q_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG22_AXI_RDY_ENA_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG22_GAT_CLK_ENA_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG22_MH_RBBM_busy_SIZE;
+          unsigned int mh_cib_axi_halt_ack            : MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE;
+          unsigned int cib_mh_axi_halt_req            : MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE;
+     } mh_debug_reg22_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg22_t f;
+} mh_debug_reg22_u;
+
+
+/*
+ * MH_DEBUG_REG23 struct
+ */
+
+#define MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE 3
+#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG23_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG23_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG23_ARB_WINNER_q_SIZE 3
+#define MH_DEBUG_REG23_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG23_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG23_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG23_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG23_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG23_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG23_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG23_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG23_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG23_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG23_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG23_TCHOLD_IP_q_SIZE 1
+
+#define MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT 0
+#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT 3
+#define MH_DEBUG_REG23_EFF1_WINNER_SHIFT 6
+#define MH_DEBUG_REG23_ARB_WINNER_SHIFT 9
+#define MH_DEBUG_REG23_ARB_WINNER_q_SHIFT 12
+#define MH_DEBUG_REG23_EFF1_WIN_SHIFT  15
+#define MH_DEBUG_REG23_KILL_EFF1_SHIFT 16
+#define MH_DEBUG_REG23_ARB_HOLD_SHIFT  17
+#define MH_DEBUG_REG23_ARB_RTR_q_SHIFT 18
+#define MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT 19
+#define MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT 20
+#define MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT 21
+#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT 22
+#define MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT 23
+#define MH_DEBUG_REG23_ARB_QUAL_SHIFT  24
+#define MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT 25
+#define MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT 26
+#define MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT 27
+#define MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT 28
+#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT 29
+#define MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT 30
+#define MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT 31
+
+#define MH_DEBUG_REG23_EFF2_FP_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK 0x00000038
+#define MH_DEBUG_REG23_EFF1_WINNER_MASK 0x000001c0
+#define MH_DEBUG_REG23_ARB_WINNER_MASK 0x00000e00
+#define MH_DEBUG_REG23_ARB_WINNER_q_MASK 0x00007000
+#define MH_DEBUG_REG23_EFF1_WIN_MASK   0x00008000
+#define MH_DEBUG_REG23_KILL_EFF1_MASK  0x00010000
+#define MH_DEBUG_REG23_ARB_HOLD_MASK   0x00020000
+#define MH_DEBUG_REG23_ARB_RTR_q_MASK  0x00040000
+#define MH_DEBUG_REG23_CP_SEND_QUAL_MASK 0x00080000
+#define MH_DEBUG_REG23_VGT_SEND_QUAL_MASK 0x00100000
+#define MH_DEBUG_REG23_TC_SEND_QUAL_MASK 0x00200000
+#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK 0x00400000
+#define MH_DEBUG_REG23_RB_SEND_QUAL_MASK 0x00800000
+#define MH_DEBUG_REG23_ARB_QUAL_MASK   0x01000000
+#define MH_DEBUG_REG23_CP_EFF1_REQ_MASK 0x02000000
+#define MH_DEBUG_REG23_VGT_EFF1_REQ_MASK 0x04000000
+#define MH_DEBUG_REG23_TC_EFF1_REQ_MASK 0x08000000
+#define MH_DEBUG_REG23_RB_EFF1_REQ_MASK 0x10000000
+#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK 0x20000000
+#define MH_DEBUG_REG23_TCD_NEARFULL_q_MASK 0x40000000
+#define MH_DEBUG_REG23_TCHOLD_IP_q_MASK 0x80000000
+
+#define MH_DEBUG_REG23_MASK \
+     (MH_DEBUG_REG23_EFF2_FP_WINNER_MASK | \
+      MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG23_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG23_ARB_WINNER_MASK | \
+      MH_DEBUG_REG23_ARB_WINNER_q_MASK | \
+      MH_DEBUG_REG23_EFF1_WIN_MASK | \
+      MH_DEBUG_REG23_KILL_EFF1_MASK | \
+      MH_DEBUG_REG23_ARB_HOLD_MASK | \
+      MH_DEBUG_REG23_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG23_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG23_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG23_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG23_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG23_ARB_QUAL_MASK | \
+      MH_DEBUG_REG23_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG23_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG23_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG23_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG23_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG23_TCHOLD_IP_q_MASK)
+
+#define MH_DEBUG_REG23(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, any_same_row_bank, tcd_nearfull_q, tchold_ip_q) \
+     ((eff2_fp_winner << MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT) | \
+      (eff2_lru_winner_out << MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT) | \
+      (eff1_winner << MH_DEBUG_REG23_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG23_ARB_WINNER_SHIFT) | \
+      (arb_winner_q << MH_DEBUG_REG23_ARB_WINNER_q_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG23_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG23_KILL_EFF1_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG23_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG23_ARB_RTR_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG23_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT))
+
+#define MH_DEBUG_REG23_GET_EFF2_FP_WINNER(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG23_GET_EFF2_LRU_WINNER_out(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG23_GET_EFF1_WINNER(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_EFF1_WINNER_MASK) >> MH_DEBUG_REG23_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_WINNER(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_WINNER_MASK) >> MH_DEBUG_REG23_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_WINNER_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_WINNER_q_MASK) >> MH_DEBUG_REG23_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG23_GET_EFF1_WIN(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_EFF1_WIN_MASK) >> MH_DEBUG_REG23_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG23_GET_KILL_EFF1(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_KILL_EFF1_MASK) >> MH_DEBUG_REG23_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_HOLD(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_HOLD_MASK) >> MH_DEBUG_REG23_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_RTR_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_RTR_q_MASK) >> MH_DEBUG_REG23_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG23_GET_CP_SEND_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_VGT_SEND_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_TC_SEND_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_TC_SEND_EFF1_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_RB_SEND_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_QUAL_MASK) >> MH_DEBUG_REG23_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_CP_EFF1_REQ(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_GET_VGT_EFF1_REQ(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_GET_TC_EFF1_REQ(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_GET_RB_EFF1_REQ(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_GET_ANY_SAME_ROW_BANK(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG23_GET_TCD_NEARFULL_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG23_GET_TCHOLD_IP_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT)
+
+#define MH_DEBUG_REG23_SET_EFF2_FP_WINNER(mh_debug_reg23_reg, eff2_fp_winner) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG23_SET_EFF2_LRU_WINNER_out(mh_debug_reg23_reg, eff2_lru_winner_out) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG23_SET_EFF1_WINNER(mh_debug_reg23_reg, eff1_winner) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG23_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_WINNER(mh_debug_reg23_reg, arb_winner) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG23_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_WINNER_q(mh_debug_reg23_reg, arb_winner_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG23_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG23_SET_EFF1_WIN(mh_debug_reg23_reg, eff1_win) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG23_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG23_SET_KILL_EFF1(mh_debug_reg23_reg, kill_eff1) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG23_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_HOLD(mh_debug_reg23_reg, arb_hold) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG23_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_RTR_q(mh_debug_reg23_reg, arb_rtr_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG23_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG23_SET_CP_SEND_QUAL(mh_debug_reg23_reg, cp_send_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_VGT_SEND_QUAL(mh_debug_reg23_reg, vgt_send_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_TC_SEND_QUAL(mh_debug_reg23_reg, tc_send_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_TC_SEND_EFF1_QUAL(mh_debug_reg23_reg, tc_send_eff1_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_RB_SEND_QUAL(mh_debug_reg23_reg, rb_send_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_QUAL(mh_debug_reg23_reg, arb_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG23_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_CP_EFF1_REQ(mh_debug_reg23_reg, cp_eff1_req) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_SET_VGT_EFF1_REQ(mh_debug_reg23_reg, vgt_eff1_req) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_SET_TC_EFF1_REQ(mh_debug_reg23_reg, tc_eff1_req) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_SET_RB_EFF1_REQ(mh_debug_reg23_reg, rb_eff1_req) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_SET_ANY_SAME_ROW_BANK(mh_debug_reg23_reg, any_same_row_bank) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG23_SET_TCD_NEARFULL_q(mh_debug_reg23_reg, tcd_nearfull_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG23_SET_TCHOLD_IP_q(mh_debug_reg23_reg, tchold_ip_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG23_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG23_ARB_WINNER_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG23_ARB_WINNER_q_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG23_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG23_KILL_EFF1_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG23_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG23_ARB_RTR_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG23_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG23_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG23_RB_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG23_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG23_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG23_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG23_RB_EFF1_REQ_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG23_TCHOLD_IP_q_SIZE;
+     } mh_debug_reg23_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG23_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG23_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG23_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG23_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG23_ARB_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG23_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG23_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG23_CP_SEND_QUAL_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG23_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG23_ARB_HOLD_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG23_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG23_EFF1_WIN_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG23_ARB_WINNER_q_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG23_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG23_EFF1_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE;
+     } mh_debug_reg23_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg23_t f;
+} mh_debug_reg23_u;
+
+
+/*
+ * MH_DEBUG_REG24 struct
+ */
+
+#define MH_DEBUG_REG24_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG24_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG24_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG24_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG24_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG24_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG24_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG24_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG24_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG24_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG24_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG24_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG24_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG24_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE 10
+
+#define MH_DEBUG_REG24_EFF1_WINNER_SHIFT 0
+#define MH_DEBUG_REG24_ARB_WINNER_SHIFT 3
+#define MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT 6
+#define MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT 7
+#define MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT 8
+#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT 9
+#define MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT 10
+#define MH_DEBUG_REG24_ARB_QUAL_SHIFT  11
+#define MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT 12
+#define MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT 13
+#define MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT 14
+#define MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT 15
+#define MH_DEBUG_REG24_EFF1_WIN_SHIFT  16
+#define MH_DEBUG_REG24_KILL_EFF1_SHIFT 17
+#define MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT 18
+#define MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT 19
+#define MH_DEBUG_REG24_ARB_HOLD_SHIFT  20
+#define MH_DEBUG_REG24_ARB_RTR_q_SHIFT 21
+#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22
+
+#define MH_DEBUG_REG24_EFF1_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG24_ARB_WINNER_MASK 0x00000038
+#define MH_DEBUG_REG24_CP_SEND_QUAL_MASK 0x00000040
+#define MH_DEBUG_REG24_VGT_SEND_QUAL_MASK 0x00000080
+#define MH_DEBUG_REG24_TC_SEND_QUAL_MASK 0x00000100
+#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK 0x00000200
+#define MH_DEBUG_REG24_RB_SEND_QUAL_MASK 0x00000400
+#define MH_DEBUG_REG24_ARB_QUAL_MASK   0x00000800
+#define MH_DEBUG_REG24_CP_EFF1_REQ_MASK 0x00001000
+#define MH_DEBUG_REG24_VGT_EFF1_REQ_MASK 0x00002000
+#define MH_DEBUG_REG24_TC_EFF1_REQ_MASK 0x00004000
+#define MH_DEBUG_REG24_RB_EFF1_REQ_MASK 0x00008000
+#define MH_DEBUG_REG24_EFF1_WIN_MASK   0x00010000
+#define MH_DEBUG_REG24_KILL_EFF1_MASK  0x00020000
+#define MH_DEBUG_REG24_TCD_NEARFULL_q_MASK 0x00040000
+#define MH_DEBUG_REG24_TC_ARB_HOLD_MASK 0x00080000
+#define MH_DEBUG_REG24_ARB_HOLD_MASK   0x00100000
+#define MH_DEBUG_REG24_ARB_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000
+
+#define MH_DEBUG_REG24_MASK \
+     (MH_DEBUG_REG24_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG24_ARB_WINNER_MASK | \
+      MH_DEBUG_REG24_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG24_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG24_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG24_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG24_ARB_QUAL_MASK | \
+      MH_DEBUG_REG24_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG24_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG24_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG24_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG24_EFF1_WIN_MASK | \
+      MH_DEBUG_REG24_KILL_EFF1_MASK | \
+      MH_DEBUG_REG24_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG24_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG24_ARB_HOLD_MASK | \
+      MH_DEBUG_REG24_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK)
+
+#define MH_DEBUG_REG24(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \
+     ((eff1_winner << MH_DEBUG_REG24_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG24_ARB_WINNER_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG24_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG24_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG24_KILL_EFF1_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT) | \
+      (tc_arb_hold << MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG24_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG24_ARB_RTR_q_SHIFT) | \
+      (same_page_limit_count_q << MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT))
+
+#define MH_DEBUG_REG24_GET_EFF1_WINNER(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_EFF1_WINNER_MASK) >> MH_DEBUG_REG24_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG24_GET_ARB_WINNER(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_WINNER_MASK) >> MH_DEBUG_REG24_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG24_GET_CP_SEND_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_VGT_SEND_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_TC_SEND_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_TC_SEND_EFF1_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_RB_SEND_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_ARB_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_QUAL_MASK) >> MH_DEBUG_REG24_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_CP_EFF1_REQ(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_GET_VGT_EFF1_REQ(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_GET_TC_EFF1_REQ(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_GET_RB_EFF1_REQ(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_GET_EFF1_WIN(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_EFF1_WIN_MASK) >> MH_DEBUG_REG24_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG24_GET_KILL_EFF1(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_KILL_EFF1_MASK) >> MH_DEBUG_REG24_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG24_GET_TCD_NEARFULL_q(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG24_GET_TC_ARB_HOLD(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG24_GET_ARB_HOLD(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_HOLD_MASK) >> MH_DEBUG_REG24_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG24_GET_ARB_RTR_q(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_RTR_q_MASK) >> MH_DEBUG_REG24_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG24_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#define MH_DEBUG_REG24_SET_EFF1_WINNER(mh_debug_reg24_reg, eff1_winner) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG24_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG24_SET_ARB_WINNER(mh_debug_reg24_reg, arb_winner) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG24_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG24_SET_CP_SEND_QUAL(mh_debug_reg24_reg, cp_send_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_VGT_SEND_QUAL(mh_debug_reg24_reg, vgt_send_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_TC_SEND_QUAL(mh_debug_reg24_reg, tc_send_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_TC_SEND_EFF1_QUAL(mh_debug_reg24_reg, tc_send_eff1_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_RB_SEND_QUAL(mh_debug_reg24_reg, rb_send_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_ARB_QUAL(mh_debug_reg24_reg, arb_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG24_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_CP_EFF1_REQ(mh_debug_reg24_reg, cp_eff1_req) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_SET_VGT_EFF1_REQ(mh_debug_reg24_reg, vgt_eff1_req) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_SET_TC_EFF1_REQ(mh_debug_reg24_reg, tc_eff1_req) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_SET_RB_EFF1_REQ(mh_debug_reg24_reg, rb_eff1_req) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_SET_EFF1_WIN(mh_debug_reg24_reg, eff1_win) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG24_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG24_SET_KILL_EFF1(mh_debug_reg24_reg, kill_eff1) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG24_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG24_SET_TCD_NEARFULL_q(mh_debug_reg24_reg, tcd_nearfull_q) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG24_SET_TC_ARB_HOLD(mh_debug_reg24_reg, tc_arb_hold) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG24_SET_ARB_HOLD(mh_debug_reg24_reg, arb_hold) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG24_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG24_SET_ARB_RTR_q(mh_debug_reg24_reg, arb_rtr_q) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG24_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG24_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg24_reg, same_page_limit_count_q) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int eff1_winner                    : MH_DEBUG_REG24_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG24_ARB_WINNER_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG24_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG24_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG24_RB_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG24_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG24_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG24_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG24_RB_EFF1_REQ_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG24_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG24_KILL_EFF1_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG24_TC_ARB_HOLD_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG24_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG24_ARB_RTR_q_SIZE;
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+     } mh_debug_reg24_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG24_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG24_ARB_HOLD_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG24_TC_ARB_HOLD_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG24_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG24_EFF1_WIN_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG24_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG24_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG24_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG24_ARB_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG24_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG24_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG24_CP_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG24_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG24_EFF1_WINNER_SIZE;
+     } mh_debug_reg24_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg24_t f;
+} mh_debug_reg24_u;
+
+
+/*
+ * MH_DEBUG_REG25 struct
+ */
+
+#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG25_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE 3
+#define MH_DEBUG_REG25_LEAST_RECENT_d_SIZE 3
+#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE 1
+#define MH_DEBUG_REG25_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG25_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG25_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG25_CLNT_REQ_SIZE   4
+#define MH_DEBUG_REG25_RECENT_d_0_SIZE 3
+#define MH_DEBUG_REG25_RECENT_d_1_SIZE 3
+#define MH_DEBUG_REG25_RECENT_d_2_SIZE 3
+#define MH_DEBUG_REG25_RECENT_d_3_SIZE 3
+
+#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT 0
+#define MH_DEBUG_REG25_ARB_WINNER_SHIFT 3
+#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT 6
+#define MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT 9
+#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT 12
+#define MH_DEBUG_REG25_ARB_HOLD_SHIFT  13
+#define MH_DEBUG_REG25_ARB_RTR_q_SHIFT 14
+#define MH_DEBUG_REG25_EFF1_WIN_SHIFT  15
+#define MH_DEBUG_REG25_CLNT_REQ_SHIFT  16
+#define MH_DEBUG_REG25_RECENT_d_0_SHIFT 20
+#define MH_DEBUG_REG25_RECENT_d_1_SHIFT 23
+#define MH_DEBUG_REG25_RECENT_d_2_SHIFT 26
+#define MH_DEBUG_REG25_RECENT_d_3_SHIFT 29
+
+#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK 0x00000007
+#define MH_DEBUG_REG25_ARB_WINNER_MASK 0x00000038
+#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK 0x000001c0
+#define MH_DEBUG_REG25_LEAST_RECENT_d_MASK 0x00000e00
+#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK 0x00001000
+#define MH_DEBUG_REG25_ARB_HOLD_MASK   0x00002000
+#define MH_DEBUG_REG25_ARB_RTR_q_MASK  0x00004000
+#define MH_DEBUG_REG25_EFF1_WIN_MASK   0x00008000
+#define MH_DEBUG_REG25_CLNT_REQ_MASK   0x000f0000
+#define MH_DEBUG_REG25_RECENT_d_0_MASK 0x00700000
+#define MH_DEBUG_REG25_RECENT_d_1_MASK 0x03800000
+#define MH_DEBUG_REG25_RECENT_d_2_MASK 0x1c000000
+#define MH_DEBUG_REG25_RECENT_d_3_MASK 0xe0000000
+
+#define MH_DEBUG_REG25_MASK \
+     (MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG25_ARB_WINNER_MASK | \
+      MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK | \
+      MH_DEBUG_REG25_LEAST_RECENT_d_MASK | \
+      MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK | \
+      MH_DEBUG_REG25_ARB_HOLD_MASK | \
+      MH_DEBUG_REG25_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG25_EFF1_WIN_MASK | \
+      MH_DEBUG_REG25_CLNT_REQ_MASK | \
+      MH_DEBUG_REG25_RECENT_d_0_MASK | \
+      MH_DEBUG_REG25_RECENT_d_1_MASK | \
+      MH_DEBUG_REG25_RECENT_d_2_MASK | \
+      MH_DEBUG_REG25_RECENT_d_3_MASK)
+
+#define MH_DEBUG_REG25(eff2_lru_winner_out, arb_winner, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, eff1_win, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3) \
+     ((eff2_lru_winner_out << MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG25_ARB_WINNER_SHIFT) | \
+      (least_recent_index_d << MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT) | \
+      (least_recent_d << MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT) | \
+      (update_recent_stack_d << MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG25_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG25_ARB_RTR_q_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG25_EFF1_WIN_SHIFT) | \
+      (clnt_req << MH_DEBUG_REG25_CLNT_REQ_SHIFT) | \
+      (recent_d_0 << MH_DEBUG_REG25_RECENT_d_0_SHIFT) | \
+      (recent_d_1 << MH_DEBUG_REG25_RECENT_d_1_SHIFT) | \
+      (recent_d_2 << MH_DEBUG_REG25_RECENT_d_2_SHIFT) | \
+      (recent_d_3 << MH_DEBUG_REG25_RECENT_d_3_SHIFT))
+
+#define MH_DEBUG_REG25_GET_EFF2_LRU_WINNER_out(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG25_GET_ARB_WINNER(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_WINNER_MASK) >> MH_DEBUG_REG25_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG25_GET_LEAST_RECENT_INDEX_d(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG25_GET_LEAST_RECENT_d(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG25_GET_UPDATE_RECENT_STACK_d(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG25_GET_ARB_HOLD(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_HOLD_MASK) >> MH_DEBUG_REG25_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG25_GET_ARB_RTR_q(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_RTR_q_MASK) >> MH_DEBUG_REG25_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG25_GET_EFF1_WIN(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_EFF1_WIN_MASK) >> MH_DEBUG_REG25_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG25_GET_CLNT_REQ(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_CLNT_REQ_MASK) >> MH_DEBUG_REG25_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG25_GET_RECENT_d_0(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_0_MASK) >> MH_DEBUG_REG25_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG25_GET_RECENT_d_1(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_1_MASK) >> MH_DEBUG_REG25_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG25_GET_RECENT_d_2(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_2_MASK) >> MH_DEBUG_REG25_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG25_GET_RECENT_d_3(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_3_MASK) >> MH_DEBUG_REG25_RECENT_d_3_SHIFT)
+
+#define MH_DEBUG_REG25_SET_EFF2_LRU_WINNER_out(mh_debug_reg25_reg, eff2_lru_winner_out) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG25_SET_ARB_WINNER(mh_debug_reg25_reg, arb_winner) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG25_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG25_SET_LEAST_RECENT_INDEX_d(mh_debug_reg25_reg, least_recent_index_d) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG25_SET_LEAST_RECENT_d(mh_debug_reg25_reg, least_recent_d) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG25_SET_UPDATE_RECENT_STACK_d(mh_debug_reg25_reg, update_recent_stack_d) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG25_SET_ARB_HOLD(mh_debug_reg25_reg, arb_hold) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG25_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG25_SET_ARB_RTR_q(mh_debug_reg25_reg, arb_rtr_q) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG25_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG25_SET_EFF1_WIN(mh_debug_reg25_reg, eff1_win) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG25_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG25_SET_CLNT_REQ(mh_debug_reg25_reg, clnt_req) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG25_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG25_SET_RECENT_d_0(mh_debug_reg25_reg, recent_d_0) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG25_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG25_SET_RECENT_d_1(mh_debug_reg25_reg, recent_d_1) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG25_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG25_SET_RECENT_d_2(mh_debug_reg25_reg, recent_d_2) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG25_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG25_SET_RECENT_d_3(mh_debug_reg25_reg, recent_d_3) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG25_RECENT_d_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG25_ARB_WINNER_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG25_LEAST_RECENT_d_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG25_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG25_ARB_RTR_q_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG25_EFF1_WIN_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG25_CLNT_REQ_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG25_RECENT_d_0_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG25_RECENT_d_1_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG25_RECENT_d_2_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG25_RECENT_d_3_SIZE;
+     } mh_debug_reg25_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int recent_d_3                     : MH_DEBUG_REG25_RECENT_d_3_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG25_RECENT_d_2_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG25_RECENT_d_1_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG25_RECENT_d_0_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG25_CLNT_REQ_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG25_EFF1_WIN_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG25_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG25_ARB_HOLD_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG25_LEAST_RECENT_d_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG25_ARB_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE;
+     } mh_debug_reg25_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg25_t f;
+} mh_debug_reg25_u;
+
+
+/*
+ * MH_DEBUG_REG26 struct
+ */
+
+#define MH_DEBUG_REG26_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG26_TCHOLD_IP_q_SIZE 1
+#define MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE 3
+#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE 7
+#define MH_DEBUG_REG26_WBURST_ACTIVE_SIZE 1
+#define MH_DEBUG_REG26_WLAST_q_SIZE    1
+#define MH_DEBUG_REG26_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG26_WBURST_CNT_q_SIZE 3
+#define MH_DEBUG_REG26_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG26_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG26_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG26_ARB_WINNER_SIZE 3
+
+#define MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT 0
+#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT 1
+#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT 2
+#define MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT 3
+#define MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT 4
+#define MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT 5
+#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 9
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 10
+#define MH_DEBUG_REG26_TC_MH_written_SHIFT 11
+#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT 12
+#define MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT 19
+#define MH_DEBUG_REG26_WLAST_q_SHIFT   20
+#define MH_DEBUG_REG26_WBURST_IP_q_SHIFT 21
+#define MH_DEBUG_REG26_WBURST_CNT_q_SHIFT 22
+#define MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT 25
+#define MH_DEBUG_REG26_CP_MH_write_SHIFT 26
+#define MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT 27
+#define MH_DEBUG_REG26_ARB_WINNER_SHIFT 28
+
+#define MH_DEBUG_REG26_TC_ARB_HOLD_MASK 0x00000001
+#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002
+#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004
+#define MH_DEBUG_REG26_TCD_NEARFULL_q_MASK 0x00000008
+#define MH_DEBUG_REG26_TCHOLD_IP_q_MASK 0x00000010
+#define MH_DEBUG_REG26_TCHOLD_CNT_q_MASK 0x000000e0
+#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00000200
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00000400
+#define MH_DEBUG_REG26_TC_MH_written_MASK 0x00000800
+#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK 0x0007f000
+#define MH_DEBUG_REG26_WBURST_ACTIVE_MASK 0x00080000
+#define MH_DEBUG_REG26_WLAST_q_MASK    0x00100000
+#define MH_DEBUG_REG26_WBURST_IP_q_MASK 0x00200000
+#define MH_DEBUG_REG26_WBURST_CNT_q_MASK 0x01c00000
+#define MH_DEBUG_REG26_CP_SEND_QUAL_MASK 0x02000000
+#define MH_DEBUG_REG26_CP_MH_write_MASK 0x04000000
+#define MH_DEBUG_REG26_RB_SEND_QUAL_MASK 0x08000000
+#define MH_DEBUG_REG26_ARB_WINNER_MASK 0x70000000
+
+#define MH_DEBUG_REG26_MASK \
+     (MH_DEBUG_REG26_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG26_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG26_TCHOLD_IP_q_MASK | \
+      MH_DEBUG_REG26_TCHOLD_CNT_q_MASK | \
+      MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG26_TC_MH_written_MASK | \
+      MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK | \
+      MH_DEBUG_REG26_WBURST_ACTIVE_MASK | \
+      MH_DEBUG_REG26_WLAST_q_MASK | \
+      MH_DEBUG_REG26_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG26_WBURST_CNT_q_MASK | \
+      MH_DEBUG_REG26_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG26_CP_MH_write_MASK | \
+      MH_DEBUG_REG26_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG26_ARB_WINNER_MASK)
+
+#define MH_DEBUG_REG26(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, arb_winner) \
+     ((tc_arb_hold << MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT) | \
+      (tc_noroq_same_row_bank << MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \
+      (tc_roq_same_row_bank << MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT) | \
+      (tchold_cnt_q << MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT) | \
+      (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG26_TC_MH_written_SHIFT) | \
+      (tcd_fullness_cnt_q << MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT) | \
+      (wburst_active << MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG26_WLAST_q_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG26_WBURST_IP_q_SHIFT) | \
+      (wburst_cnt_q << MH_DEBUG_REG26_WBURST_CNT_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG26_CP_MH_write_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG26_ARB_WINNER_SHIFT))
+
+#define MH_DEBUG_REG26_GET_TC_ARB_HOLD(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG26_GET_TCD_NEARFULL_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TCHOLD_IP_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TCHOLD_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_MH_written(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_MH_written_MASK) >> MH_DEBUG_REG26_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG26_GET_TCD_FULLNESS_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_WBURST_ACTIVE(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG26_GET_WLAST_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_WLAST_q_MASK) >> MH_DEBUG_REG26_WLAST_q_SHIFT)
+#define MH_DEBUG_REG26_GET_WBURST_IP_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_IP_q_MASK) >> MH_DEBUG_REG26_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG26_GET_WBURST_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_CNT_q_MASK) >> MH_DEBUG_REG26_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_SEND_QUAL(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_MH_write(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_MH_write_MASK) >> MH_DEBUG_REG26_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_SEND_QUAL(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG26_GET_ARB_WINNER(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_ARB_WINNER_MASK) >> MH_DEBUG_REG26_ARB_WINNER_SHIFT)
+
+#define MH_DEBUG_REG26_SET_TC_ARB_HOLD(mh_debug_reg26_reg, tc_arb_hold) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg26_reg, tc_noroq_same_row_bank) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg26_reg, tc_roq_same_row_bank) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG26_SET_TCD_NEARFULL_q(mh_debug_reg26_reg, tcd_nearfull_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TCHOLD_IP_q(mh_debug_reg26_reg, tchold_ip_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TCHOLD_CNT_q(mh_debug_reg26_reg, tchold_cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg26_reg, mh_arbiter_config_tc_reorder_enable) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_MH_written(mh_debug_reg26_reg, tc_mh_written) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG26_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG26_SET_TCD_FULLNESS_CNT_q(mh_debug_reg26_reg, tcd_fullness_cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_WBURST_ACTIVE(mh_debug_reg26_reg, wburst_active) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG26_SET_WLAST_q(mh_debug_reg26_reg, wlast_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG26_WLAST_q_SHIFT)
+#define MH_DEBUG_REG26_SET_WBURST_IP_q(mh_debug_reg26_reg, wburst_ip_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG26_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG26_SET_WBURST_CNT_q(mh_debug_reg26_reg, wburst_cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG26_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_SEND_QUAL(mh_debug_reg26_reg, cp_send_qual) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_MH_write(mh_debug_reg26_reg, cp_mh_write) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG26_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_SEND_QUAL(mh_debug_reg26_reg, rb_send_qual) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG26_SET_ARB_WINNER(mh_debug_reg26_reg, arb_winner) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG26_ARB_WINNER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG26_TC_ARB_HOLD_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG26_TCHOLD_IP_q_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG26_TC_MH_written_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG26_WBURST_ACTIVE_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG26_WLAST_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG26_WBURST_IP_q_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG26_WBURST_CNT_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG26_CP_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG26_CP_MH_write_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG26_RB_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG26_ARB_WINNER_SIZE;
+          unsigned int                                : 1;
+     } mh_debug_reg26_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int                                : 1;
+          unsigned int arb_winner                     : MH_DEBUG_REG26_ARB_WINNER_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG26_RB_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG26_CP_MH_write_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG26_CP_SEND_QUAL_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG26_WBURST_CNT_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG26_WBURST_IP_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG26_WLAST_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG26_WBURST_ACTIVE_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG26_TC_MH_written_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG26_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG26_TC_ARB_HOLD_SIZE;
+     } mh_debug_reg26_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg26_t f;
+} mh_debug_reg26_u;
+
+
+/*
+ * MH_DEBUG_REG27 struct
+ */
+
+#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE 26
+#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT 0
+#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26
+
+#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK 0x03ffffff
+#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000
+
+#define MH_DEBUG_REG27_MASK \
+     (MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK | \
+      MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG27(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \
+     ((rf_arbiter_config_q << MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG27_GET_RF_ARBITER_CONFIG_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG27_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG27_SET_RF_ARBITER_CONFIG_q(mh_debug_reg27_reg, rf_arbiter_config_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG27_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg27_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg27_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int                                : 3;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE;
+     } mh_debug_reg27_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg27_t f;
+} mh_debug_reg27_u;
+
+
+/*
+ * MH_DEBUG_REG28 struct
+ */
+
+#define MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG28_ROQ_MARK_q_SIZE 8
+#define MH_DEBUG_REG28_ROQ_VALID_q_SIZE 8
+#define MH_DEBUG_REG28_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG28_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG28_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG28_ROQ_MARK_q_SHIFT 8
+#define MH_DEBUG_REG28_ROQ_VALID_q_SHIFT 16
+#define MH_DEBUG_REG28_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG28_ROQ_MARK_q_MASK 0x0000ff00
+#define MH_DEBUG_REG28_ROQ_VALID_q_MASK 0x00ff0000
+#define MH_DEBUG_REG28_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG28_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG28_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG28_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG28_MASK \
+     (MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG28_ROQ_MARK_q_MASK | \
+      MH_DEBUG_REG28_ROQ_VALID_q_MASK | \
+      MH_DEBUG_REG28_TC_MH_send_MASK | \
+      MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG28_KILL_EFF1_MASK | \
+      MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG28_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG28_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG28(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_q << MH_DEBUG_REG28_ROQ_MARK_q_SHIFT) | \
+      (roq_valid_q << MH_DEBUG_REG28_ROQ_VALID_q_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG28_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG28_GET_SAME_ROW_BANK_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG28_GET_ROQ_MARK_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ROQ_MARK_q_MASK) >> MH_DEBUG_REG28_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG28_GET_ROQ_VALID_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ROQ_VALID_q_MASK) >> MH_DEBUG_REG28_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_MH_send(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_MH_send_MASK) >> MH_DEBUG_REG28_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ROQ_RTR_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG28_GET_ANY_SAME_ROW_BANK(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_EFF1_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ROQ_EMPTY(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ROQ_FULL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG28_SET_SAME_ROW_BANK_q(mh_debug_reg28_reg, same_row_bank_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG28_SET_ROQ_MARK_q(mh_debug_reg28_reg, roq_mark_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG28_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG28_SET_ROQ_VALID_q(mh_debug_reg28_reg, roq_valid_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG28_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_MH_send(mh_debug_reg28_reg, tc_mh_send) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG28_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ROQ_RTR_q(mh_debug_reg28_reg, tc_roq_rtr_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg28_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG28_SET_ANY_SAME_ROW_BANK(mh_debug_reg28_reg, any_same_row_bank) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_EFF1_QUAL(mh_debug_reg28_reg, tc_eff1_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ROQ_EMPTY(mh_debug_reg28_reg, tc_roq_empty) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ROQ_FULL(mh_debug_reg28_reg, tc_roq_full) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG28_ROQ_MARK_q_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG28_ROQ_VALID_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG28_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG28_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg28_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG28_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG28_TC_MH_send_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG28_ROQ_VALID_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG28_ROQ_MARK_q_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg28_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg28_t f;
+} mh_debug_reg28_u;
+
+
+/*
+ * MH_DEBUG_REG29 struct
+ */
+
+#define MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG29_ROQ_MARK_d_SIZE 8
+#define MH_DEBUG_REG29_ROQ_VALID_d_SIZE 8
+#define MH_DEBUG_REG29_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG29_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG29_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG29_ROQ_MARK_d_SHIFT 8
+#define MH_DEBUG_REG29_ROQ_VALID_d_SHIFT 16
+#define MH_DEBUG_REG29_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG29_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG29_ROQ_MARK_d_MASK 0x0000ff00
+#define MH_DEBUG_REG29_ROQ_VALID_d_MASK 0x00ff0000
+#define MH_DEBUG_REG29_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG29_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG29_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG29_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG29_MASK \
+     (MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG29_ROQ_MARK_d_MASK | \
+      MH_DEBUG_REG29_ROQ_VALID_d_MASK | \
+      MH_DEBUG_REG29_TC_MH_send_MASK | \
+      MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG29_KILL_EFF1_MASK | \
+      MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG29_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG29_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG29(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_d << MH_DEBUG_REG29_ROQ_MARK_d_SHIFT) | \
+      (roq_valid_d << MH_DEBUG_REG29_ROQ_VALID_d_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG29_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG29_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG29_GET_SAME_ROW_BANK_q(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG29_GET_ROQ_MARK_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ROQ_MARK_d_MASK) >> MH_DEBUG_REG29_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG29_GET_ROQ_VALID_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ROQ_VALID_d_MASK) >> MH_DEBUG_REG29_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_MH_send(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_MH_send_MASK) >> MH_DEBUG_REG29_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_ROQ_RTR_q(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_GET_KILL_EFF1(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_KILL_EFF1_MASK) >> MH_DEBUG_REG29_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG29_GET_ANY_SAME_ROW_BANK(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_EFF1_QUAL(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_ROQ_EMPTY(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_ROQ_FULL(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG29_SET_SAME_ROW_BANK_q(mh_debug_reg29_reg, same_row_bank_q) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG29_SET_ROQ_MARK_d(mh_debug_reg29_reg, roq_mark_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG29_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG29_SET_ROQ_VALID_d(mh_debug_reg29_reg, roq_valid_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG29_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_MH_send(mh_debug_reg29_reg, tc_mh_send) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG29_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_ROQ_RTR_q(mh_debug_reg29_reg, tc_roq_rtr_q) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_SET_KILL_EFF1(mh_debug_reg29_reg, kill_eff1) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG29_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg29_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG29_SET_ANY_SAME_ROW_BANK(mh_debug_reg29_reg, any_same_row_bank) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_EFF1_QUAL(mh_debug_reg29_reg, tc_eff1_qual) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_ROQ_EMPTY(mh_debug_reg29_reg, tc_roq_empty) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_ROQ_FULL(mh_debug_reg29_reg, tc_roq_full) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG29_ROQ_MARK_d_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG29_ROQ_VALID_d_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG29_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG29_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG29_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg29_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG29_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG29_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG29_TC_MH_send_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG29_ROQ_VALID_d_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG29_ROQ_MARK_d_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg29_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg29_t f;
+} mh_debug_reg29_u;
+
+
+/*
+ * MH_DEBUG_REG30 struct
+ */
+
+#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE 8
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE 8
+
+#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT 0
+#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT 8
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT 16
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT 24
+
+#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK 0x000000ff
+#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK 0x0000ff00
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK 0xff000000
+
+#define MH_DEBUG_REG30_MASK \
+     (MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK | \
+      MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK)
+
+#define MH_DEBUG_REG30(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \
+     ((same_row_bank_win << MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT) | \
+      (same_row_bank_req << MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT) | \
+      (non_same_row_bank_win << MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT) | \
+      (non_same_row_bank_req << MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT))
+
+#define MH_DEBUG_REG30_GET_SAME_ROW_BANK_WIN(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG30_GET_SAME_ROW_BANK_REQ(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG30_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG30_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#define MH_DEBUG_REG30_SET_SAME_ROW_BANK_WIN(mh_debug_reg30_reg, same_row_bank_win) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG30_SET_SAME_ROW_BANK_REQ(mh_debug_reg30_reg, same_row_bank_req) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG30_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg30_reg, non_same_row_bank_win) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG30_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg30_reg, non_same_row_bank_req) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int same_row_bank_win              : MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE;
+     } mh_debug_reg30_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int same_row_bank_win              : MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE;
+     } mh_debug_reg30_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg30_t f;
+} mh_debug_reg30_u;
+
+
+/*
+ * MH_DEBUG_REG31 struct
+ */
+
+#define MH_DEBUG_REG31_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE 1
+#define MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE 1
+#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE 1
+#define MH_DEBUG_REG31_ROQ_ADDR_0_SIZE 27
+
+#define MH_DEBUG_REG31_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT 2
+#define MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT 3
+#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT 4
+#define MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT 5
+
+#define MH_DEBUG_REG31_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG31_ROQ_MARK_q_0_MASK 0x00000004
+#define MH_DEBUG_REG31_ROQ_VALID_q_0_MASK 0x00000008
+#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK 0x00000010
+#define MH_DEBUG_REG31_ROQ_ADDR_0_MASK 0xffffffe0
+
+#define MH_DEBUG_REG31_MASK \
+     (MH_DEBUG_REG31_TC_MH_send_MASK | \
+      MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG31_ROQ_MARK_q_0_MASK | \
+      MH_DEBUG_REG31_ROQ_VALID_q_0_MASK | \
+      MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK | \
+      MH_DEBUG_REG31_ROQ_ADDR_0_MASK)
+
+#define MH_DEBUG_REG31(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \
+     ((tc_mh_send << MH_DEBUG_REG31_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_0 << MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT) | \
+      (roq_valid_q_0 << MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT) | \
+      (same_row_bank_q_0 << MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT) | \
+      (roq_addr_0 << MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT))
+
+#define MH_DEBUG_REG31_GET_TC_MH_send(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_TC_MH_send_MASK) >> MH_DEBUG_REG31_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG31_GET_TC_ROQ_RTR_q(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG31_GET_ROQ_MARK_q_0(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG31_GET_ROQ_VALID_q_0(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG31_GET_SAME_ROW_BANK_q_0(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG31_GET_ROQ_ADDR_0(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT)
+
+#define MH_DEBUG_REG31_SET_TC_MH_send(mh_debug_reg31_reg, tc_mh_send) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG31_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG31_SET_TC_ROQ_RTR_q(mh_debug_reg31_reg, tc_roq_rtr_q) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG31_SET_ROQ_MARK_q_0(mh_debug_reg31_reg, roq_mark_q_0) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG31_SET_ROQ_VALID_q_0(mh_debug_reg31_reg, roq_valid_q_0) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG31_SET_SAME_ROW_BANK_q_0(mh_debug_reg31_reg, same_row_bank_q_0) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG31_SET_ROQ_ADDR_0(mh_debug_reg31_reg, roq_addr_0) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG31_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_addr_0                     : MH_DEBUG_REG31_ROQ_ADDR_0_SIZE;
+     } mh_debug_reg31_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int roq_addr_0                     : MH_DEBUG_REG31_ROQ_ADDR_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG31_TC_MH_send_SIZE;
+     } mh_debug_reg31_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg31_t f;
+} mh_debug_reg31_u;
+
+
+/*
+ * MH_DEBUG_REG32 struct
+ */
+
+#define MH_DEBUG_REG32_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE 1
+#define MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE 1
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE 1
+#define MH_DEBUG_REG32_ROQ_ADDR_1_SIZE 27
+
+#define MH_DEBUG_REG32_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT 2
+#define MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT 3
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT 4
+#define MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT 5
+
+#define MH_DEBUG_REG32_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG32_ROQ_MARK_q_1_MASK 0x00000004
+#define MH_DEBUG_REG32_ROQ_VALID_q_1_MASK 0x00000008
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK 0x00000010
+#define MH_DEBUG_REG32_ROQ_ADDR_1_MASK 0xffffffe0
+
+#define MH_DEBUG_REG32_MASK \
+     (MH_DEBUG_REG32_TC_MH_send_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG32_ROQ_MARK_q_1_MASK | \
+      MH_DEBUG_REG32_ROQ_VALID_q_1_MASK | \
+      MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK | \
+      MH_DEBUG_REG32_ROQ_ADDR_1_MASK)
+
+#define MH_DEBUG_REG32(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \
+     ((tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_1 << MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT) | \
+      (roq_valid_q_1 << MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT) | \
+      (same_row_bank_q_1 << MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT) | \
+      (roq_addr_1 << MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT))
+
+#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_MARK_q_1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_VALID_q_1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q_1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_ADDR_1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT)
+
+#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_MARK_q_1(mh_debug_reg32_reg, roq_mark_q_1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_VALID_q_1(mh_debug_reg32_reg, roq_valid_q_1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q_1(mh_debug_reg32_reg, same_row_bank_q_1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_ADDR_1(mh_debug_reg32_reg, roq_addr_1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_addr_1                     : MH_DEBUG_REG32_ROQ_ADDR_1_SIZE;
+     } mh_debug_reg32_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int roq_addr_1                     : MH_DEBUG_REG32_ROQ_ADDR_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+     } mh_debug_reg32_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg32_t f;
+} mh_debug_reg32_u;
+
+
+/*
+ * MH_DEBUG_REG33 struct
+ */
+
+#define MH_DEBUG_REG33_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE 1
+#define MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE 1
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE 1
+#define MH_DEBUG_REG33_ROQ_ADDR_2_SIZE 27
+
+#define MH_DEBUG_REG33_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT 2
+#define MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT 3
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT 4
+#define MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT 5
+
+#define MH_DEBUG_REG33_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG33_ROQ_MARK_q_2_MASK 0x00000004
+#define MH_DEBUG_REG33_ROQ_VALID_q_2_MASK 0x00000008
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK 0x00000010
+#define MH_DEBUG_REG33_ROQ_ADDR_2_MASK 0xffffffe0
+
+#define MH_DEBUG_REG33_MASK \
+     (MH_DEBUG_REG33_TC_MH_send_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG33_ROQ_MARK_q_2_MASK | \
+      MH_DEBUG_REG33_ROQ_VALID_q_2_MASK | \
+      MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK | \
+      MH_DEBUG_REG33_ROQ_ADDR_2_MASK)
+
+#define MH_DEBUG_REG33(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \
+     ((tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_2 << MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT) | \
+      (roq_valid_q_2 << MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT) | \
+      (same_row_bank_q_2 << MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT) | \
+      (roq_addr_2 << MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT))
+
+#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_MARK_q_2(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_VALID_q_2(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q_2(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_ADDR_2(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT)
+
+#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_MARK_q_2(mh_debug_reg33_reg, roq_mark_q_2) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_VALID_q_2(mh_debug_reg33_reg, roq_valid_q_2) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q_2(mh_debug_reg33_reg, same_row_bank_q_2) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_ADDR_2(mh_debug_reg33_reg, roq_addr_2) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_addr_2                     : MH_DEBUG_REG33_ROQ_ADDR_2_SIZE;
+     } mh_debug_reg33_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int roq_addr_2                     : MH_DEBUG_REG33_ROQ_ADDR_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+     } mh_debug_reg33_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg33_t f;
+} mh_debug_reg33_u;
+
+
+/*
+ * MH_DEBUG_REG34 struct
+ */
+
+#define MH_DEBUG_REG34_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE 1
+#define MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE 1
+#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE 1
+#define MH_DEBUG_REG34_ROQ_ADDR_3_SIZE 27
+
+#define MH_DEBUG_REG34_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT 2
+#define MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT 3
+#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT 4
+#define MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT 5
+
+#define MH_DEBUG_REG34_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG34_ROQ_MARK_q_3_MASK 0x00000004
+#define MH_DEBUG_REG34_ROQ_VALID_q_3_MASK 0x00000008
+#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK 0x00000010
+#define MH_DEBUG_REG34_ROQ_ADDR_3_MASK 0xffffffe0
+
+#define MH_DEBUG_REG34_MASK \
+     (MH_DEBUG_REG34_TC_MH_send_MASK | \
+      MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG34_ROQ_MARK_q_3_MASK | \
+      MH_DEBUG_REG34_ROQ_VALID_q_3_MASK | \
+      MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK | \
+      MH_DEBUG_REG34_ROQ_ADDR_3_MASK)
+
+#define MH_DEBUG_REG34(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \
+     ((tc_mh_send << MH_DEBUG_REG34_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_3 << MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT) | \
+      (roq_valid_q_3 << MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT) | \
+      (same_row_bank_q_3 << MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT) | \
+      (roq_addr_3 << MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT))
+
+#define MH_DEBUG_REG34_GET_TC_MH_send(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_TC_MH_send_MASK) >> MH_DEBUG_REG34_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG34_GET_TC_ROQ_RTR_q(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG34_GET_ROQ_MARK_q_3(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG34_GET_ROQ_VALID_q_3(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_q_3(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG34_GET_ROQ_ADDR_3(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT)
+
+#define MH_DEBUG_REG34_SET_TC_MH_send(mh_debug_reg34_reg, tc_mh_send) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG34_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG34_SET_TC_ROQ_RTR_q(mh_debug_reg34_reg, tc_roq_rtr_q) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG34_SET_ROQ_MARK_q_3(mh_debug_reg34_reg, roq_mark_q_3) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG34_SET_ROQ_VALID_q_3(mh_debug_reg34_reg, roq_valid_q_3) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_q_3(mh_debug_reg34_reg, same_row_bank_q_3) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG34_SET_ROQ_ADDR_3(mh_debug_reg34_reg, roq_addr_3) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG34_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_addr_3                     : MH_DEBUG_REG34_ROQ_ADDR_3_SIZE;
+     } mh_debug_reg34_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int roq_addr_3                     : MH_DEBUG_REG34_ROQ_ADDR_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG34_TC_MH_send_SIZE;
+     } mh_debug_reg34_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg34_t f;
+} mh_debug_reg34_u;
+
+
+/*
+ * MH_DEBUG_REG35 struct
+ */
+
+#define MH_DEBUG_REG35_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE 1
+#define MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE 1
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE 1
+#define MH_DEBUG_REG35_ROQ_ADDR_4_SIZE 27
+
+#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT 2
+#define MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT 3
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT 4
+#define MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT 5
+
+#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG35_ROQ_MARK_q_4_MASK 0x00000004
+#define MH_DEBUG_REG35_ROQ_VALID_q_4_MASK 0x00000008
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK 0x00000010
+#define MH_DEBUG_REG35_ROQ_ADDR_4_MASK 0xffffffe0
+
+#define MH_DEBUG_REG35_MASK \
+     (MH_DEBUG_REG35_TC_MH_send_MASK | \
+      MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG35_ROQ_MARK_q_4_MASK | \
+      MH_DEBUG_REG35_ROQ_VALID_q_4_MASK | \
+      MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK | \
+      MH_DEBUG_REG35_ROQ_ADDR_4_MASK)
+
+#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \
+     ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_4 << MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT) | \
+      (roq_valid_q_4 << MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT) | \
+      (same_row_bank_q_4 << MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT) | \
+      (roq_addr_4 << MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT))
+
+#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_MARK_q_4(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_VALID_q_4(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_4(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_ADDR_4(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT)
+
+#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_MARK_q_4(mh_debug_reg35_reg, roq_mark_q_4) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_VALID_q_4(mh_debug_reg35_reg, roq_valid_q_4) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_4(mh_debug_reg35_reg, same_row_bank_q_4) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_ADDR_4(mh_debug_reg35_reg, roq_addr_4) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_addr_4                     : MH_DEBUG_REG35_ROQ_ADDR_4_SIZE;
+     } mh_debug_reg35_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int roq_addr_4                     : MH_DEBUG_REG35_ROQ_ADDR_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+     } mh_debug_reg35_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg35_t f;
+} mh_debug_reg35_u;
+
+
+/*
+ * MH_DEBUG_REG36 struct
+ */
+
+#define MH_DEBUG_REG36_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE 1
+#define MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE 1
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE 1
+#define MH_DEBUG_REG36_ROQ_ADDR_5_SIZE 27
+
+#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT 2
+#define MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT 3
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT 4
+#define MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT 5
+
+#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG36_ROQ_MARK_q_5_MASK 0x00000004
+#define MH_DEBUG_REG36_ROQ_VALID_q_5_MASK 0x00000008
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK 0x00000010
+#define MH_DEBUG_REG36_ROQ_ADDR_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG36_MASK \
+     (MH_DEBUG_REG36_TC_MH_send_MASK | \
+      MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG36_ROQ_MARK_q_5_MASK | \
+      MH_DEBUG_REG36_ROQ_VALID_q_5_MASK | \
+      MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK | \
+      MH_DEBUG_REG36_ROQ_ADDR_5_MASK)
+
+#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \
+     ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_5 << MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT) | \
+      (roq_valid_q_5 << MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT) | \
+      (same_row_bank_q_5 << MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT) | \
+      (roq_addr_5 << MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT))
+
+#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_MARK_q_5(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_VALID_q_5(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_5(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_ADDR_5(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT)
+
+#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_MARK_q_5(mh_debug_reg36_reg, roq_mark_q_5) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_VALID_q_5(mh_debug_reg36_reg, roq_valid_q_5) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_5(mh_debug_reg36_reg, same_row_bank_q_5) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_ADDR_5(mh_debug_reg36_reg, roq_addr_5) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_addr_5                     : MH_DEBUG_REG36_ROQ_ADDR_5_SIZE;
+     } mh_debug_reg36_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int roq_addr_5                     : MH_DEBUG_REG36_ROQ_ADDR_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+     } mh_debug_reg36_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg36_t f;
+} mh_debug_reg36_u;
+
+
+/*
+ * MH_DEBUG_REG37 struct
+ */
+
+#define MH_DEBUG_REG37_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE 1
+#define MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE 1
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE 1
+#define MH_DEBUG_REG37_ROQ_ADDR_6_SIZE 27
+
+#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT 2
+#define MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT 3
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT 4
+#define MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT 5
+
+#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG37_ROQ_MARK_q_6_MASK 0x00000004
+#define MH_DEBUG_REG37_ROQ_VALID_q_6_MASK 0x00000008
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK 0x00000010
+#define MH_DEBUG_REG37_ROQ_ADDR_6_MASK 0xffffffe0
+
+#define MH_DEBUG_REG37_MASK \
+     (MH_DEBUG_REG37_TC_MH_send_MASK | \
+      MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG37_ROQ_MARK_q_6_MASK | \
+      MH_DEBUG_REG37_ROQ_VALID_q_6_MASK | \
+      MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK | \
+      MH_DEBUG_REG37_ROQ_ADDR_6_MASK)
+
+#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \
+     ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_6 << MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT) | \
+      (roq_valid_q_6 << MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT) | \
+      (same_row_bank_q_6 << MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT) | \
+      (roq_addr_6 << MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT))
+
+#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_MARK_q_6(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_VALID_q_6(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_6(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_ADDR_6(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT)
+
+#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_MARK_q_6(mh_debug_reg37_reg, roq_mark_q_6) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_VALID_q_6(mh_debug_reg37_reg, roq_valid_q_6) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_6(mh_debug_reg37_reg, same_row_bank_q_6) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_ADDR_6(mh_debug_reg37_reg, roq_addr_6) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_addr_6                     : MH_DEBUG_REG37_ROQ_ADDR_6_SIZE;
+     } mh_debug_reg37_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int roq_addr_6                     : MH_DEBUG_REG37_ROQ_ADDR_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+     } mh_debug_reg37_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg37_t f;
+} mh_debug_reg37_u;
+
+
+/*
+ * MH_DEBUG_REG38 struct
+ */
+
+#define MH_DEBUG_REG38_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE 1
+#define MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE 1
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE 1
+#define MH_DEBUG_REG38_ROQ_ADDR_7_SIZE 27
+
+#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT 2
+#define MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT 3
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT 4
+#define MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT 5
+
+#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG38_ROQ_MARK_q_7_MASK 0x00000004
+#define MH_DEBUG_REG38_ROQ_VALID_q_7_MASK 0x00000008
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK 0x00000010
+#define MH_DEBUG_REG38_ROQ_ADDR_7_MASK 0xffffffe0
+
+#define MH_DEBUG_REG38_MASK \
+     (MH_DEBUG_REG38_TC_MH_send_MASK | \
+      MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG38_ROQ_MARK_q_7_MASK | \
+      MH_DEBUG_REG38_ROQ_VALID_q_7_MASK | \
+      MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK | \
+      MH_DEBUG_REG38_ROQ_ADDR_7_MASK)
+
+#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \
+     ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_7 << MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT) | \
+      (roq_valid_q_7 << MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT) | \
+      (same_row_bank_q_7 << MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT) | \
+      (roq_addr_7 << MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT))
+
+#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_MARK_q_7(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_VALID_q_7(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_7(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_ADDR_7(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT)
+
+#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_MARK_q_7(mh_debug_reg38_reg, roq_mark_q_7) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_VALID_q_7(mh_debug_reg38_reg, roq_valid_q_7) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_7(mh_debug_reg38_reg, same_row_bank_q_7) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_ADDR_7(mh_debug_reg38_reg, roq_addr_7) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_addr_7                     : MH_DEBUG_REG38_ROQ_ADDR_7_SIZE;
+     } mh_debug_reg38_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int roq_addr_7                     : MH_DEBUG_REG38_ROQ_ADDR_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+     } mh_debug_reg38_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg38_t f;
+} mh_debug_reg38_u;
+
+
+/*
+ * MH_DEBUG_REG39 struct
+ */
+
+#define MH_DEBUG_REG39_ARB_WE_SIZE     1
+#define MH_DEBUG_REG39_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG39_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG39_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG39_ARB_BLEN_q_SIZE 1
+#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE 3
+#define MH_DEBUG_REG39_MMU_WE_SIZE     1
+#define MH_DEBUG_REG39_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG39_MMU_ID_SIZE     3
+#define MH_DEBUG_REG39_MMU_WRITE_SIZE  1
+#define MH_DEBUG_REG39_MMU_BLEN_SIZE   1
+
+#define MH_DEBUG_REG39_ARB_WE_SHIFT    0
+#define MH_DEBUG_REG39_MMU_RTR_SHIFT   1
+#define MH_DEBUG_REG39_ARB_ID_q_SHIFT  2
+#define MH_DEBUG_REG39_ARB_WRITE_q_SHIFT 5
+#define MH_DEBUG_REG39_ARB_BLEN_q_SHIFT 6
+#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT 7
+#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT 8
+#define MH_DEBUG_REG39_MMU_WE_SHIFT    11
+#define MH_DEBUG_REG39_ARQ_RTR_SHIFT   12
+#define MH_DEBUG_REG39_MMU_ID_SHIFT    13
+#define MH_DEBUG_REG39_MMU_WRITE_SHIFT 16
+#define MH_DEBUG_REG39_MMU_BLEN_SHIFT  17
+
+#define MH_DEBUG_REG39_ARB_WE_MASK     0x00000001
+#define MH_DEBUG_REG39_MMU_RTR_MASK    0x00000002
+#define MH_DEBUG_REG39_ARB_ID_q_MASK   0x0000001c
+#define MH_DEBUG_REG39_ARB_WRITE_q_MASK 0x00000020
+#define MH_DEBUG_REG39_ARB_BLEN_q_MASK 0x00000040
+#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK 0x00000080
+#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK 0x00000700
+#define MH_DEBUG_REG39_MMU_WE_MASK     0x00000800
+#define MH_DEBUG_REG39_ARQ_RTR_MASK    0x00001000
+#define MH_DEBUG_REG39_MMU_ID_MASK     0x0000e000
+#define MH_DEBUG_REG39_MMU_WRITE_MASK  0x00010000
+#define MH_DEBUG_REG39_MMU_BLEN_MASK   0x00020000
+
+#define MH_DEBUG_REG39_MASK \
+     (MH_DEBUG_REG39_ARB_WE_MASK | \
+      MH_DEBUG_REG39_MMU_RTR_MASK | \
+      MH_DEBUG_REG39_ARB_ID_q_MASK | \
+      MH_DEBUG_REG39_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG39_ARB_BLEN_q_MASK | \
+      MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG39_MMU_WE_MASK | \
+      MH_DEBUG_REG39_ARQ_RTR_MASK | \
+      MH_DEBUG_REG39_MMU_ID_MASK | \
+      MH_DEBUG_REG39_MMU_WRITE_MASK | \
+      MH_DEBUG_REG39_MMU_BLEN_MASK)
+
+#define MH_DEBUG_REG39(arb_we, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen) \
+     ((arb_we << MH_DEBUG_REG39_ARB_WE_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG39_MMU_RTR_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG39_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG39_ARB_WRITE_q_SHIFT) | \
+      (arb_blen_q << MH_DEBUG_REG39_ARB_BLEN_q_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_fifo_cnt_q << MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG39_MMU_WE_SHIFT) | \
+      (arq_rtr << MH_DEBUG_REG39_ARQ_RTR_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG39_MMU_ID_SHIFT) | \
+      (mmu_write << MH_DEBUG_REG39_MMU_WRITE_SHIFT) | \
+      (mmu_blen << MH_DEBUG_REG39_MMU_BLEN_SHIFT))
+
+#define MH_DEBUG_REG39_GET_ARB_WE(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_WE_MASK) >> MH_DEBUG_REG39_ARB_WE_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_RTR(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_RTR_MASK) >> MH_DEBUG_REG39_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG39_GET_ARB_ID_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_ID_q_MASK) >> MH_DEBUG_REG39_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ARB_WRITE_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_WRITE_q_MASK) >> MH_DEBUG_REG39_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ARB_BLEN_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_BLEN_q_MASK) >> MH_DEBUG_REG39_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ARQ_CTRL_EMPTY(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG39_GET_ARQ_FIFO_CNT_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_WE(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_WE_MASK) >> MH_DEBUG_REG39_MMU_WE_SHIFT)
+#define MH_DEBUG_REG39_GET_ARQ_RTR(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_RTR_MASK) >> MH_DEBUG_REG39_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_ID(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_ID_MASK) >> MH_DEBUG_REG39_MMU_ID_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_WRITE(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_WRITE_MASK) >> MH_DEBUG_REG39_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_BLEN(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_BLEN_MASK) >> MH_DEBUG_REG39_MMU_BLEN_SHIFT)
+
+#define MH_DEBUG_REG39_SET_ARB_WE(mh_debug_reg39_reg, arb_we) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG39_ARB_WE_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_RTR(mh_debug_reg39_reg, mmu_rtr) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG39_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG39_SET_ARB_ID_q(mh_debug_reg39_reg, arb_id_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG39_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ARB_WRITE_q(mh_debug_reg39_reg, arb_write_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG39_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ARB_BLEN_q(mh_debug_reg39_reg, arb_blen_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG39_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ARQ_CTRL_EMPTY(mh_debug_reg39_reg, arq_ctrl_empty) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG39_SET_ARQ_FIFO_CNT_q(mh_debug_reg39_reg, arq_fifo_cnt_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_WE(mh_debug_reg39_reg, mmu_we) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG39_MMU_WE_SHIFT)
+#define MH_DEBUG_REG39_SET_ARQ_RTR(mh_debug_reg39_reg, arq_rtr) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG39_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_ID(mh_debug_reg39_reg, mmu_id) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG39_MMU_ID_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_WRITE(mh_debug_reg39_reg, mmu_write) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG39_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_BLEN(mh_debug_reg39_reg, mmu_blen) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG39_MMU_BLEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int arb_we                         : MH_DEBUG_REG39_ARB_WE_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG39_MMU_RTR_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG39_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG39_ARB_WRITE_q_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG39_ARB_BLEN_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG39_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG39_ARQ_RTR_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG39_MMU_ID_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG39_MMU_WRITE_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG39_MMU_BLEN_SIZE;
+          unsigned int                                : 14;
+     } mh_debug_reg39_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int                                : 14;
+          unsigned int mmu_blen                       : MH_DEBUG_REG39_MMU_BLEN_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG39_MMU_WRITE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG39_MMU_ID_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG39_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG39_MMU_WE_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG39_ARB_BLEN_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG39_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG39_ARB_ID_q_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG39_MMU_RTR_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG39_ARB_WE_SIZE;
+     } mh_debug_reg39_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg39_t f;
+} mh_debug_reg39_u;
+
+
+/*
+ * MH_DEBUG_REG40 struct
+ */
+
+#define MH_DEBUG_REG40_ARB_WE_SIZE     1
+#define MH_DEBUG_REG40_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG40_ARB_VAD_q_SIZE  28
+
+#define MH_DEBUG_REG40_ARB_WE_SHIFT    0
+#define MH_DEBUG_REG40_ARB_ID_q_SHIFT  1
+#define MH_DEBUG_REG40_ARB_VAD_q_SHIFT 4
+
+#define MH_DEBUG_REG40_ARB_WE_MASK     0x00000001
+#define MH_DEBUG_REG40_ARB_ID_q_MASK   0x0000000e
+#define MH_DEBUG_REG40_ARB_VAD_q_MASK  0xfffffff0
+
+#define MH_DEBUG_REG40_MASK \
+     (MH_DEBUG_REG40_ARB_WE_MASK | \
+      MH_DEBUG_REG40_ARB_ID_q_MASK | \
+      MH_DEBUG_REG40_ARB_VAD_q_MASK)
+
+#define MH_DEBUG_REG40(arb_we, arb_id_q, arb_vad_q) \
+     ((arb_we << MH_DEBUG_REG40_ARB_WE_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG40_ARB_ID_q_SHIFT) | \
+      (arb_vad_q << MH_DEBUG_REG40_ARB_VAD_q_SHIFT))
+
+#define MH_DEBUG_REG40_GET_ARB_WE(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_WE_MASK) >> MH_DEBUG_REG40_ARB_WE_SHIFT)
+#define MH_DEBUG_REG40_GET_ARB_ID_q(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_ID_q_MASK) >> MH_DEBUG_REG40_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG40_GET_ARB_VAD_q(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_VAD_q_MASK) >> MH_DEBUG_REG40_ARB_VAD_q_SHIFT)
+
+#define MH_DEBUG_REG40_SET_ARB_WE(mh_debug_reg40_reg, arb_we) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG40_ARB_WE_SHIFT)
+#define MH_DEBUG_REG40_SET_ARB_ID_q(mh_debug_reg40_reg, arb_id_q) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG40_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG40_SET_ARB_VAD_q(mh_debug_reg40_reg, arb_vad_q) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG40_ARB_VAD_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int arb_we                         : MH_DEBUG_REG40_ARB_WE_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG40_ARB_ID_q_SIZE;
+          unsigned int arb_vad_q                      : MH_DEBUG_REG40_ARB_VAD_q_SIZE;
+     } mh_debug_reg40_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int arb_vad_q                      : MH_DEBUG_REG40_ARB_VAD_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG40_ARB_ID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG40_ARB_WE_SIZE;
+     } mh_debug_reg40_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg40_t f;
+} mh_debug_reg40_u;
+
+
+/*
+ * MH_DEBUG_REG41 struct
+ */
+
+#define MH_DEBUG_REG41_MMU_WE_SIZE     1
+#define MH_DEBUG_REG41_MMU_ID_SIZE     3
+#define MH_DEBUG_REG41_MMU_PAD_SIZE    28
+
+#define MH_DEBUG_REG41_MMU_WE_SHIFT    0
+#define MH_DEBUG_REG41_MMU_ID_SHIFT    1
+#define MH_DEBUG_REG41_MMU_PAD_SHIFT   4
+
+#define MH_DEBUG_REG41_MMU_WE_MASK     0x00000001
+#define MH_DEBUG_REG41_MMU_ID_MASK     0x0000000e
+#define MH_DEBUG_REG41_MMU_PAD_MASK    0xfffffff0
+
+#define MH_DEBUG_REG41_MASK \
+     (MH_DEBUG_REG41_MMU_WE_MASK | \
+      MH_DEBUG_REG41_MMU_ID_MASK | \
+      MH_DEBUG_REG41_MMU_PAD_MASK)
+
+#define MH_DEBUG_REG41(mmu_we, mmu_id, mmu_pad) \
+     ((mmu_we << MH_DEBUG_REG41_MMU_WE_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG41_MMU_ID_SHIFT) | \
+      (mmu_pad << MH_DEBUG_REG41_MMU_PAD_SHIFT))
+
+#define MH_DEBUG_REG41_GET_MMU_WE(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_WE_MASK) >> MH_DEBUG_REG41_MMU_WE_SHIFT)
+#define MH_DEBUG_REG41_GET_MMU_ID(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_ID_MASK) >> MH_DEBUG_REG41_MMU_ID_SHIFT)
+#define MH_DEBUG_REG41_GET_MMU_PAD(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_PAD_MASK) >> MH_DEBUG_REG41_MMU_PAD_SHIFT)
+
+#define MH_DEBUG_REG41_SET_MMU_WE(mh_debug_reg41_reg, mmu_we) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG41_MMU_WE_SHIFT)
+#define MH_DEBUG_REG41_SET_MMU_ID(mh_debug_reg41_reg, mmu_id) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG41_MMU_ID_SHIFT)
+#define MH_DEBUG_REG41_SET_MMU_PAD(mh_debug_reg41_reg, mmu_pad) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG41_MMU_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int mmu_we                         : MH_DEBUG_REG41_MMU_WE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG41_MMU_ID_SIZE;
+          unsigned int mmu_pad                        : MH_DEBUG_REG41_MMU_PAD_SIZE;
+     } mh_debug_reg41_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int mmu_pad                        : MH_DEBUG_REG41_MMU_PAD_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG41_MMU_ID_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG41_MMU_WE_SIZE;
+     } mh_debug_reg41_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg41_t f;
+} mh_debug_reg41_u;
+
+
+/*
+ * MH_DEBUG_REG42 struct
+ */
+
+#define MH_DEBUG_REG42_WDB_WE_SIZE     1
+#define MH_DEBUG_REG42_WDB_RTR_SKID_SIZE 1
+#define MH_DEBUG_REG42_ARB_WSTRB_q_SIZE 8
+#define MH_DEBUG_REG42_ARB_WLAST_SIZE  1
+#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE 5
+#define MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE 1
+#define MH_DEBUG_REG42_WDB_WDC_WID_SIZE 3
+#define MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE 1
+#define MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE 8
+
+#define MH_DEBUG_REG42_WDB_WE_SHIFT    0
+#define MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT 1
+#define MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT 2
+#define MH_DEBUG_REG42_ARB_WLAST_SHIFT 10
+#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT 11
+#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT 12
+#define MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT 17
+#define MH_DEBUG_REG42_WDB_WDC_WID_SHIFT 18
+#define MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT 21
+#define MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT 22
+
+#define MH_DEBUG_REG42_WDB_WE_MASK     0x00000001
+#define MH_DEBUG_REG42_WDB_RTR_SKID_MASK 0x00000002
+#define MH_DEBUG_REG42_ARB_WSTRB_q_MASK 0x000003fc
+#define MH_DEBUG_REG42_ARB_WLAST_MASK  0x00000400
+#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK 0x00000800
+#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK 0x0001f000
+#define MH_DEBUG_REG42_WDC_WDB_RE_q_MASK 0x00020000
+#define MH_DEBUG_REG42_WDB_WDC_WID_MASK 0x001c0000
+#define MH_DEBUG_REG42_WDB_WDC_WLAST_MASK 0x00200000
+#define MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK 0x3fc00000
+
+#define MH_DEBUG_REG42_MASK \
+     (MH_DEBUG_REG42_WDB_WE_MASK | \
+      MH_DEBUG_REG42_WDB_RTR_SKID_MASK | \
+      MH_DEBUG_REG42_ARB_WSTRB_q_MASK | \
+      MH_DEBUG_REG42_ARB_WLAST_MASK | \
+      MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG42_WDC_WDB_RE_q_MASK | \
+      MH_DEBUG_REG42_WDB_WDC_WID_MASK | \
+      MH_DEBUG_REG42_WDB_WDC_WLAST_MASK | \
+      MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK)
+
+#define MH_DEBUG_REG42(wdb_we, wdb_rtr_skid, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \
+     ((wdb_we << MH_DEBUG_REG42_WDB_WE_SHIFT) | \
+      (wdb_rtr_skid << MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT) | \
+      (arb_wstrb_q << MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT) | \
+      (arb_wlast << MH_DEBUG_REG42_ARB_WLAST_SHIFT) | \
+      (wdb_ctrl_empty << MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT) | \
+      (wdb_fifo_cnt_q << MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT) | \
+      (wdc_wdb_re_q << MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT) | \
+      (wdb_wdc_wid << MH_DEBUG_REG42_WDB_WDC_WID_SHIFT) | \
+      (wdb_wdc_wlast << MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT) | \
+      (wdb_wdc_wstrb << MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT))
+
+#define MH_DEBUG_REG42_GET_WDB_WE(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WE_MASK) >> MH_DEBUG_REG42_WDB_WE_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_RTR_SKID(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_RTR_SKID_MASK) >> MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT)
+#define MH_DEBUG_REG42_GET_ARB_WSTRB_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG42_GET_ARB_WLAST(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ARB_WLAST_MASK) >> MH_DEBUG_REG42_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_CTRL_EMPTY(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_FIFO_CNT_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG42_GET_WDC_WDB_RE_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_WDC_WID(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WID_MASK) >> MH_DEBUG_REG42_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_WDC_WLAST(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_WDC_WSTRB(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT)
+
+#define MH_DEBUG_REG42_SET_WDB_WE(mh_debug_reg42_reg, wdb_we) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG42_WDB_WE_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_RTR_SKID(mh_debug_reg42_reg, wdb_rtr_skid) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_RTR_SKID_MASK) | (wdb_rtr_skid << MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT)
+#define MH_DEBUG_REG42_SET_ARB_WSTRB_q(mh_debug_reg42_reg, arb_wstrb_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG42_SET_ARB_WLAST(mh_debug_reg42_reg, arb_wlast) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG42_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_CTRL_EMPTY(mh_debug_reg42_reg, wdb_ctrl_empty) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_FIFO_CNT_q(mh_debug_reg42_reg, wdb_fifo_cnt_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG42_SET_WDC_WDB_RE_q(mh_debug_reg42_reg, wdc_wdb_re_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_WDC_WID(mh_debug_reg42_reg, wdb_wdc_wid) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG42_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_WDC_WLAST(mh_debug_reg42_reg, wdb_wdc_wlast) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_WDC_WSTRB(mh_debug_reg42_reg, wdb_wdc_wstrb) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int wdb_we                         : MH_DEBUG_REG42_WDB_WE_SIZE;
+          unsigned int wdb_rtr_skid                   : MH_DEBUG_REG42_WDB_RTR_SKID_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG42_ARB_WSTRB_q_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG42_ARB_WLAST_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG42_WDB_WDC_WID_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg42_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int                                : 2;
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG42_WDB_WDC_WID_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG42_ARB_WLAST_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG42_ARB_WSTRB_q_SIZE;
+          unsigned int wdb_rtr_skid                   : MH_DEBUG_REG42_WDB_RTR_SKID_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG42_WDB_WE_SIZE;
+     } mh_debug_reg42_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg42_t f;
+} mh_debug_reg42_u;
+
+
+/*
+ * MH_DEBUG_REG43 struct
+ */
+
+#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE 32
+
+#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT 0
+
+#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG43_MASK \
+     (MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK)
+
+#define MH_DEBUG_REG43(arb_wdata_q_31_0) \
+     ((arb_wdata_q_31_0 << MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT))
+
+#define MH_DEBUG_REG43_GET_ARB_WDATA_q_31_0(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) >> MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT)
+
+#define MH_DEBUG_REG43_SET_ARB_WDATA_q_31_0(mh_debug_reg43_reg, arb_wdata_q_31_0) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) | (arb_wdata_q_31_0 << MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int arb_wdata_q_31_0               : MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE;
+     } mh_debug_reg43_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int arb_wdata_q_31_0               : MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE;
+     } mh_debug_reg43_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg43_t f;
+} mh_debug_reg43_u;
+
+
+/*
+ * MH_DEBUG_REG44 struct
+ */
+
+#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE 32
+
+#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT 0
+
+#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG44_MASK \
+     (MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK)
+
+#define MH_DEBUG_REG44(arb_wdata_q_63_32) \
+     ((arb_wdata_q_63_32 << MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT))
+
+#define MH_DEBUG_REG44_GET_ARB_WDATA_q_63_32(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) >> MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT)
+
+#define MH_DEBUG_REG44_SET_ARB_WDATA_q_63_32(mh_debug_reg44_reg, arb_wdata_q_63_32) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) | (arb_wdata_q_63_32 << MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_wdata_q_63_32              : MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE;
+     } mh_debug_reg44_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_wdata_q_63_32              : MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE;
+     } mh_debug_reg44_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg44_t f;
+} mh_debug_reg44_u;
+
+
+/*
+ * MH_DEBUG_REG45 struct
+ */
+
+#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE 32
+
+#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT 0
+
+#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG45_MASK \
+     (MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK)
+
+#define MH_DEBUG_REG45(wdb_wdc_wdata_31_0) \
+     ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT))
+
+#define MH_DEBUG_REG45_GET_WDB_WDC_WDATA_31_0(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT)
+
+#define MH_DEBUG_REG45_SET_WDB_WDC_WDATA_31_0(mh_debug_reg45_reg, wdb_wdc_wdata_31_0) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg45_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg45_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg45_t f;
+} mh_debug_reg45_u;
+
+
+/*
+ * MH_DEBUG_REG46 struct
+ */
+
+#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE 32
+
+#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT 0
+
+#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG46_MASK \
+     (MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK)
+
+#define MH_DEBUG_REG46(wdb_wdc_wdata_63_32) \
+     ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT))
+
+#define MH_DEBUG_REG46_GET_WDB_WDC_WDATA_63_32(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT)
+
+#define MH_DEBUG_REG46_SET_WDB_WDC_WDATA_63_32(mh_debug_reg46_reg, wdb_wdc_wdata_63_32) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg46_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg46_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg46_t f;
+} mh_debug_reg46_u;
+
+
+/*
+ * MH_DEBUG_REG47 struct
+ */
+
+#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE 1
+#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE 1
+#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE 6
+#define MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG47_RVALID_q_SIZE   1
+#define MH_DEBUG_REG47_RREADY_q_SIZE   1
+#define MH_DEBUG_REG47_RLAST_q_SIZE    1
+#define MH_DEBUG_REG47_BVALID_q_SIZE   1
+#define MH_DEBUG_REG47_BREADY_q_SIZE   1
+
+#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT 0
+#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT 1
+#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT 2
+#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT 3
+#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT 4
+#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT 5
+#define MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT 6
+#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT 7
+#define MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT 13
+#define MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT 14
+#define MH_DEBUG_REG47_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG47_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG47_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG47_BVALID_q_SHIFT  18
+#define MH_DEBUG_REG47_BREADY_q_SHIFT  19
+
+#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK 0x00000001
+#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK 0x00000002
+#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK 0x00000004
+#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK 0x00000008
+#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK 0x00000010
+#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK 0x00000020
+#define MH_DEBUG_REG47_INFLT_LIMIT_q_MASK 0x00000040
+#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK 0x00001f80
+#define MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK 0x00004000
+#define MH_DEBUG_REG47_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG47_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG47_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG47_BVALID_q_MASK   0x00040000
+#define MH_DEBUG_REG47_BREADY_q_MASK   0x00080000
+
+#define MH_DEBUG_REG47_MASK \
+     (MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK | \
+      MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK | \
+      MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK | \
+      MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG47_INFLT_LIMIT_q_MASK | \
+      MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK | \
+      MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG47_RVALID_q_MASK | \
+      MH_DEBUG_REG47_RREADY_q_MASK | \
+      MH_DEBUG_REG47_RLAST_q_MASK | \
+      MH_DEBUG_REG47_BVALID_q_MASK | \
+      MH_DEBUG_REG47_BREADY_q_MASK)
+
+#define MH_DEBUG_REG47(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \
+     ((ctrl_arc_empty << MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT) | \
+      (ctrl_rarc_empty << MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_ctrl_write << MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (inflt_limit_q << MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT) | \
+      (inflt_limit_cnt_q << MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT) | \
+      (arc_ctrl_re_q << MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT) | \
+      (rarc_ctrl_re_q << MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG47_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG47_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG47_RLAST_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG47_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG47_BREADY_q_SHIFT))
+
+#define MH_DEBUG_REG47_GET_CTRL_ARC_EMPTY(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_GET_CTRL_RARC_EMPTY(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_GET_ARQ_CTRL_EMPTY(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_GET_ARQ_CTRL_WRITE(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG47_GET_TLBMISS_CTRL_RTS(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG47_GET_CTRL_TLBMISS_RE_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG47_GET_INFLT_LIMIT_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG47_GET_INFLT_LIMIT_CNT_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG47_GET_ARC_CTRL_RE_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG47_GET_RARC_CTRL_RE_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG47_GET_RVALID_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_RVALID_q_MASK) >> MH_DEBUG_REG47_RVALID_q_SHIFT)
+#define MH_DEBUG_REG47_GET_RREADY_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_RREADY_q_MASK) >> MH_DEBUG_REG47_RREADY_q_SHIFT)
+#define MH_DEBUG_REG47_GET_RLAST_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_RLAST_q_MASK) >> MH_DEBUG_REG47_RLAST_q_SHIFT)
+#define MH_DEBUG_REG47_GET_BVALID_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_BVALID_q_MASK) >> MH_DEBUG_REG47_BVALID_q_SHIFT)
+#define MH_DEBUG_REG47_GET_BREADY_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_BREADY_q_MASK) >> MH_DEBUG_REG47_BREADY_q_SHIFT)
+
+#define MH_DEBUG_REG47_SET_CTRL_ARC_EMPTY(mh_debug_reg47_reg, ctrl_arc_empty) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_SET_CTRL_RARC_EMPTY(mh_debug_reg47_reg, ctrl_rarc_empty) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_SET_ARQ_CTRL_EMPTY(mh_debug_reg47_reg, arq_ctrl_empty) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_SET_ARQ_CTRL_WRITE(mh_debug_reg47_reg, arq_ctrl_write) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG47_SET_TLBMISS_CTRL_RTS(mh_debug_reg47_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG47_SET_CTRL_TLBMISS_RE_q(mh_debug_reg47_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG47_SET_INFLT_LIMIT_q(mh_debug_reg47_reg, inflt_limit_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG47_SET_INFLT_LIMIT_CNT_q(mh_debug_reg47_reg, inflt_limit_cnt_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG47_SET_ARC_CTRL_RE_q(mh_debug_reg47_reg, arc_ctrl_re_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG47_SET_RARC_CTRL_RE_q(mh_debug_reg47_reg, rarc_ctrl_re_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG47_SET_RVALID_q(mh_debug_reg47_reg, rvalid_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG47_RVALID_q_SHIFT)
+#define MH_DEBUG_REG47_SET_RREADY_q(mh_debug_reg47_reg, rready_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG47_RREADY_q_SHIFT)
+#define MH_DEBUG_REG47_SET_RLAST_q(mh_debug_reg47_reg, rlast_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG47_RLAST_q_SHIFT)
+#define MH_DEBUG_REG47_SET_BVALID_q(mh_debug_reg47_reg, bvalid_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG47_BVALID_q_SHIFT)
+#define MH_DEBUG_REG47_SET_BREADY_q(mh_debug_reg47_reg, bready_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG47_BREADY_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG47_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG47_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG47_RLAST_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG47_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG47_BREADY_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg47_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int                                : 12;
+          unsigned int bready_q                       : MH_DEBUG_REG47_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG47_BVALID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG47_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG47_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG47_RVALID_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE;
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE;
+     } mh_debug_reg47_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg47_t f;
+} mh_debug_reg47_u;
+
+
+/*
+ * MH_DEBUG_REG48 struct
+ */
+
+#define MH_DEBUG_REG48_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG48_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG48_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG48_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG48_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG48_RDC_RID_SIZE    3
+#define MH_DEBUG_REG48_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG48_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE 1
+#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE 6
+#define MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE 1
+#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE 6
+#define MH_DEBUG_REG48_CNT_HOLD_q1_SIZE 1
+#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG48_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG48_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT 3
+#define MH_DEBUG_REG48_TLBMISS_VALID_SHIFT 4
+#define MH_DEBUG_REG48_RDC_VALID_SHIFT 5
+#define MH_DEBUG_REG48_RDC_RID_SHIFT   6
+#define MH_DEBUG_REG48_RDC_RLAST_SHIFT 9
+#define MH_DEBUG_REG48_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT 12
+#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT 13
+#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT 14
+#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT 15
+#define MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT 21
+#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT 22
+#define MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT 28
+#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29
+
+#define MH_DEBUG_REG48_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG48_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG48_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK 0x00000008
+#define MH_DEBUG_REG48_TLBMISS_VALID_MASK 0x00000010
+#define MH_DEBUG_REG48_RDC_VALID_MASK  0x00000020
+#define MH_DEBUG_REG48_RDC_RID_MASK    0x000001c0
+#define MH_DEBUG_REG48_RDC_RLAST_MASK  0x00000200
+#define MH_DEBUG_REG48_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK 0x00001000
+#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK 0x00004000
+#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000
+#define MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK 0x00200000
+#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000
+#define MH_DEBUG_REG48_CNT_HOLD_q1_MASK 0x10000000
+#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000
+
+#define MH_DEBUG_REG48_MASK \
+     (MH_DEBUG_REG48_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG48_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG48_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG48_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG48_RDC_VALID_MASK | \
+      MH_DEBUG_REG48_RDC_RID_MASK | \
+      MH_DEBUG_REG48_RDC_RLAST_MASK | \
+      MH_DEBUG_REG48_RDC_RRESP_MASK | \
+      MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK | \
+      MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK | \
+      MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK | \
+      MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK | \
+      MH_DEBUG_REG48_CNT_HOLD_q1_MASK | \
+      MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG48(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \
+     ((mh_cp_grb_send << MH_DEBUG_REG48_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG48_MH_TC_mcsend_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG48_TLBMISS_VALID_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG48_RDC_VALID_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG48_RDC_RID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG48_RDC_RLAST_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG48_RDC_RRESP_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (mmu_id_request_q << MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT) | \
+      (outstanding_mmuid_cnt_q << MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT) | \
+      (mmu_id_response << MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT) | \
+      (tlbmiss_return_cnt_q << MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT) | \
+      (cnt_hold_q1 << MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG48_GET_MH_CP_grb_send(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_CP_grb_send_MASK) >> MH_DEBUG_REG48_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG48_GET_MH_VGT_grb_send(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG48_GET_MH_TC_mcsend(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_TC_mcsend_MASK) >> MH_DEBUG_REG48_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG48_GET_MH_TLBMISS_SEND(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG48_GET_TLBMISS_VALID(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_VALID_MASK) >> MH_DEBUG_REG48_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG48_GET_RDC_VALID(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_VALID_MASK) >> MH_DEBUG_REG48_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG48_GET_RDC_RID(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RID_MASK) >> MH_DEBUG_REG48_RDC_RID_SHIFT)
+#define MH_DEBUG_REG48_GET_RDC_RLAST(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RLAST_MASK) >> MH_DEBUG_REG48_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG48_GET_RDC_RRESP(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RRESP_MASK) >> MH_DEBUG_REG48_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG48_GET_TLBMISS_CTRL_RTS(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG48_GET_CTRL_TLBMISS_RE_q(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG48_GET_MMU_ID_REQUEST_q(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG48_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG48_GET_MMU_ID_RESPONSE(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG48_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG48_GET_CNT_HOLD_q1(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG48_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG48_SET_MH_CP_grb_send(mh_debug_reg48_reg, mh_cp_grb_send) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG48_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG48_SET_MH_VGT_grb_send(mh_debug_reg48_reg, mh_vgt_grb_send) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG48_SET_MH_TC_mcsend(mh_debug_reg48_reg, mh_tc_mcsend) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG48_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG48_SET_MH_TLBMISS_SEND(mh_debug_reg48_reg, mh_tlbmiss_send) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG48_SET_TLBMISS_VALID(mh_debug_reg48_reg, tlbmiss_valid) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG48_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG48_SET_RDC_VALID(mh_debug_reg48_reg, rdc_valid) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG48_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG48_SET_RDC_RID(mh_debug_reg48_reg, rdc_rid) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG48_RDC_RID_SHIFT)
+#define MH_DEBUG_REG48_SET_RDC_RLAST(mh_debug_reg48_reg, rdc_rlast) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG48_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG48_SET_RDC_RRESP(mh_debug_reg48_reg, rdc_rresp) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG48_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG48_SET_TLBMISS_CTRL_RTS(mh_debug_reg48_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG48_SET_CTRL_TLBMISS_RE_q(mh_debug_reg48_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG48_SET_MMU_ID_REQUEST_q(mh_debug_reg48_reg, mmu_id_request_q) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG48_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg48_reg, outstanding_mmuid_cnt_q) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG48_SET_MMU_ID_RESPONSE(mh_debug_reg48_reg, mmu_id_response) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG48_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg48_reg, tlbmiss_return_cnt_q) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG48_SET_CNT_HOLD_q1(mh_debug_reg48_reg, cnt_hold_q1) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG48_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg48_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG48_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG48_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG48_MH_TC_mcsend_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG48_TLBMISS_VALID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG48_RDC_VALID_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG48_RDC_RID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG48_RDC_RLAST_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG48_RDC_RRESP_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG48_CNT_HOLD_q1_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+     } mh_debug_reg48_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG48_CNT_HOLD_q1_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG48_RDC_RRESP_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG48_RDC_RLAST_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG48_RDC_RID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG48_RDC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG48_TLBMISS_VALID_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG48_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG48_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG48_MH_CP_grb_send_SIZE;
+     } mh_debug_reg48_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg48_t f;
+} mh_debug_reg48_u;
+
+
+/*
+ * MH_DEBUG_REG49 struct
+ */
+
+#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE 32
+
+#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT 0
+
+#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG49_MASK \
+     (MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK)
+
+#define MH_DEBUG_REG49(rf_mmu_page_fault) \
+     ((rf_mmu_page_fault << MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_DEBUG_REG49_GET_RF_MMU_PAGE_FAULT(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_DEBUG_REG49_SET_RF_MMU_PAGE_FAULT(mh_debug_reg49_reg, rf_mmu_page_fault) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg49_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg49_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg49_t f;
+} mh_debug_reg49_u;
+
+
+/*
+ * MH_DEBUG_REG50 struct
+ */
+
+#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE 24
+#define MH_DEBUG_REG50_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG50_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG50_client_behavior_q_SIZE 2
+#define MH_DEBUG_REG50_ARB_WE_SIZE     1
+#define MH_DEBUG_REG50_MMU_RTR_SIZE    1
+
+#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT 0
+#define MH_DEBUG_REG50_ARB_ID_q_SHIFT  24
+#define MH_DEBUG_REG50_ARB_WRITE_q_SHIFT 27
+#define MH_DEBUG_REG50_client_behavior_q_SHIFT 28
+#define MH_DEBUG_REG50_ARB_WE_SHIFT    30
+#define MH_DEBUG_REG50_MMU_RTR_SHIFT   31
+
+#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK 0x00ffffff
+#define MH_DEBUG_REG50_ARB_ID_q_MASK   0x07000000
+#define MH_DEBUG_REG50_ARB_WRITE_q_MASK 0x08000000
+#define MH_DEBUG_REG50_client_behavior_q_MASK 0x30000000
+#define MH_DEBUG_REG50_ARB_WE_MASK     0x40000000
+#define MH_DEBUG_REG50_MMU_RTR_MASK    0x80000000
+
+#define MH_DEBUG_REG50_MASK \
+     (MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK | \
+      MH_DEBUG_REG50_ARB_ID_q_MASK | \
+      MH_DEBUG_REG50_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG50_client_behavior_q_MASK | \
+      MH_DEBUG_REG50_ARB_WE_MASK | \
+      MH_DEBUG_REG50_MMU_RTR_MASK)
+
+#define MH_DEBUG_REG50(rf_mmu_config_q, arb_id_q, arb_write_q, client_behavior_q, arb_we, mmu_rtr) \
+     ((rf_mmu_config_q << MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG50_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG50_ARB_WRITE_q_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG50_client_behavior_q_SHIFT) | \
+      (arb_we << MH_DEBUG_REG50_ARB_WE_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG50_MMU_RTR_SHIFT))
+
+#define MH_DEBUG_REG50_GET_RF_MMU_CONFIG_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK) >> MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG50_GET_ARB_ID_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_ID_q_MASK) >> MH_DEBUG_REG50_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG50_GET_ARB_WRITE_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_WRITE_q_MASK) >> MH_DEBUG_REG50_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG50_GET_client_behavior_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_client_behavior_q_MASK) >> MH_DEBUG_REG50_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG50_GET_ARB_WE(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_WE_MASK) >> MH_DEBUG_REG50_ARB_WE_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_RTR(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_RTR_MASK) >> MH_DEBUG_REG50_MMU_RTR_SHIFT)
+
+#define MH_DEBUG_REG50_SET_RF_MMU_CONFIG_q(mh_debug_reg50_reg, rf_mmu_config_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK) | (rf_mmu_config_q << MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG50_SET_ARB_ID_q(mh_debug_reg50_reg, arb_id_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG50_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG50_SET_ARB_WRITE_q(mh_debug_reg50_reg, arb_write_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG50_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG50_SET_client_behavior_q(mh_debug_reg50_reg, client_behavior_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG50_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG50_SET_ARB_WE(mh_debug_reg50_reg, arb_we) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG50_ARB_WE_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_RTR(mh_debug_reg50_reg, mmu_rtr) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG50_MMU_RTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int rf_mmu_config_q                : MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG50_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG50_ARB_WRITE_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG50_client_behavior_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG50_ARB_WE_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG50_MMU_RTR_SIZE;
+     } mh_debug_reg50_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mmu_rtr                        : MH_DEBUG_REG50_MMU_RTR_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG50_ARB_WE_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG50_client_behavior_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG50_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG50_ARB_ID_q_SIZE;
+          unsigned int rf_mmu_config_q                : MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE;
+     } mh_debug_reg50_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg50_t f;
+} mh_debug_reg50_u;
+
+
+/*
+ * MH_DEBUG_REG51 struct
+ */
+
+#define MH_DEBUG_REG51_stage1_valid_SIZE 1
+#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG51_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG51_tag_match_q_SIZE 1
+#define MH_DEBUG_REG51_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG51_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG51_MMU_MISS_SIZE   1
+#define MH_DEBUG_REG51_MMU_READ_MISS_SIZE 1
+#define MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE 1
+#define MH_DEBUG_REG51_MMU_HIT_SIZE    1
+#define MH_DEBUG_REG51_MMU_READ_HIT_SIZE 1
+#define MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE 1
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE 1
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE 1
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1
+#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE 16
+
+#define MH_DEBUG_REG51_stage1_valid_SHIFT 0
+#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT 1
+#define MH_DEBUG_REG51_pa_in_mpu_range_SHIFT 2
+#define MH_DEBUG_REG51_tag_match_q_SHIFT 3
+#define MH_DEBUG_REG51_tag_miss_q_SHIFT 4
+#define MH_DEBUG_REG51_va_in_range_q_SHIFT 5
+#define MH_DEBUG_REG51_MMU_MISS_SHIFT  6
+#define MH_DEBUG_REG51_MMU_READ_MISS_SHIFT 7
+#define MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT 8
+#define MH_DEBUG_REG51_MMU_HIT_SHIFT   9
+#define MH_DEBUG_REG51_MMU_READ_HIT_SHIFT 10
+#define MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT 11
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT 12
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT 13
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15
+#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT 16
+
+#define MH_DEBUG_REG51_stage1_valid_MASK 0x00000001
+#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK 0x00000002
+#define MH_DEBUG_REG51_pa_in_mpu_range_MASK 0x00000004
+#define MH_DEBUG_REG51_tag_match_q_MASK 0x00000008
+#define MH_DEBUG_REG51_tag_miss_q_MASK 0x00000010
+#define MH_DEBUG_REG51_va_in_range_q_MASK 0x00000020
+#define MH_DEBUG_REG51_MMU_MISS_MASK   0x00000040
+#define MH_DEBUG_REG51_MMU_READ_MISS_MASK 0x00000080
+#define MH_DEBUG_REG51_MMU_WRITE_MISS_MASK 0x00000100
+#define MH_DEBUG_REG51_MMU_HIT_MASK    0x00000200
+#define MH_DEBUG_REG51_MMU_READ_HIT_MASK 0x00000400
+#define MH_DEBUG_REG51_MMU_WRITE_HIT_MASK 0x00000800
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000
+#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG51_MASK \
+     (MH_DEBUG_REG51_stage1_valid_MASK | \
+      MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG51_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG51_tag_match_q_MASK | \
+      MH_DEBUG_REG51_tag_miss_q_MASK | \
+      MH_DEBUG_REG51_va_in_range_q_MASK | \
+      MH_DEBUG_REG51_MMU_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_READ_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_WRITE_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_HIT_MASK | \
+      MH_DEBUG_REG51_MMU_READ_HIT_MASK | \
+      MH_DEBUG_REG51_MMU_WRITE_HIT_MASK | \
+      MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK | \
+      MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK | \
+      MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK)
+
+#define MH_DEBUG_REG51(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \
+     ((stage1_valid << MH_DEBUG_REG51_stage1_valid_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG51_pa_in_mpu_range_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG51_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG51_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG51_va_in_range_q_SHIFT) | \
+      (mmu_miss << MH_DEBUG_REG51_MMU_MISS_SHIFT) | \
+      (mmu_read_miss << MH_DEBUG_REG51_MMU_READ_MISS_SHIFT) | \
+      (mmu_write_miss << MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT) | \
+      (mmu_hit << MH_DEBUG_REG51_MMU_HIT_SHIFT) | \
+      (mmu_read_hit << MH_DEBUG_REG51_MMU_READ_HIT_SHIFT) | \
+      (mmu_write_hit << MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT) | \
+      (mmu_split_mode_tc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \
+      (mmu_split_mode_tc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \
+      (mmu_split_mode_nontc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \
+      (mmu_split_mode_nontc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \
+      (req_va_offset_q << MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT))
+
+#define MH_DEBUG_REG51_GET_stage1_valid(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_stage1_valid_MASK) >> MH_DEBUG_REG51_stage1_valid_SHIFT)
+#define MH_DEBUG_REG51_GET_IGNORE_TAG_MISS_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG51_GET_pa_in_mpu_range(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_pa_in_mpu_range_MASK) >> MH_DEBUG_REG51_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG51_GET_tag_match_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_tag_match_q_MASK) >> MH_DEBUG_REG51_tag_match_q_SHIFT)
+#define MH_DEBUG_REG51_GET_tag_miss_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_tag_miss_q_MASK) >> MH_DEBUG_REG51_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG51_GET_va_in_range_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_va_in_range_q_MASK) >> MH_DEBUG_REG51_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_MISS_MASK) >> MH_DEBUG_REG51_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_READ_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_READ_MISS_MASK) >> MH_DEBUG_REG51_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_WRITE_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_HIT_MASK) >> MH_DEBUG_REG51_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_READ_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_READ_HIT_MASK) >> MH_DEBUG_REG51_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_WRITE_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_REQ_VA_OFFSET_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT)
+
+#define MH_DEBUG_REG51_SET_stage1_valid(mh_debug_reg51_reg, stage1_valid) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG51_stage1_valid_SHIFT)
+#define MH_DEBUG_REG51_SET_IGNORE_TAG_MISS_q(mh_debug_reg51_reg, ignore_tag_miss_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG51_SET_pa_in_mpu_range(mh_debug_reg51_reg, pa_in_mpu_range) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG51_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG51_SET_tag_match_q(mh_debug_reg51_reg, tag_match_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG51_tag_match_q_SHIFT)
+#define MH_DEBUG_REG51_SET_tag_miss_q(mh_debug_reg51_reg, tag_miss_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG51_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG51_SET_va_in_range_q(mh_debug_reg51_reg, va_in_range_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG51_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_MISS(mh_debug_reg51_reg, mmu_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG51_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_READ_MISS(mh_debug_reg51_reg, mmu_read_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG51_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_WRITE_MISS(mh_debug_reg51_reg, mmu_write_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_HIT(mh_debug_reg51_reg, mmu_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG51_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_READ_HIT(mh_debug_reg51_reg, mmu_read_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG51_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_WRITE_HIT(mh_debug_reg51_reg, mmu_write_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg51_reg, mmu_split_mode_tc_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg51_reg, mmu_split_mode_tc_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg51_reg, mmu_split_mode_nontc_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg51_reg, mmu_split_mode_nontc_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_REQ_VA_OFFSET_q(mh_debug_reg51_reg, req_va_offset_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int stage1_valid                   : MH_DEBUG_REG51_stage1_valid_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG51_pa_in_mpu_range_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG51_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG51_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG51_va_in_range_q_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG51_MMU_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG51_MMU_READ_MISS_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG51_MMU_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG51_MMU_READ_HIT_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int req_va_offset_q                : MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE;
+     } mh_debug_reg51_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int req_va_offset_q                : MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG51_MMU_READ_HIT_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG51_MMU_HIT_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG51_MMU_READ_MISS_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG51_MMU_MISS_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG51_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG51_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG51_tag_match_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG51_pa_in_mpu_range_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG51_stage1_valid_SIZE;
+     } mh_debug_reg51_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg51_t f;
+} mh_debug_reg51_u;
+
+
+/*
+ * MH_DEBUG_REG52 struct
+ */
+
+#define MH_DEBUG_REG52_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG52_MMU_WE_SIZE     1
+#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1
+#define MH_DEBUG_REG52_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG52_stage1_valid_SIZE 1
+#define MH_DEBUG_REG52_stage2_valid_SIZE 1
+#define MH_DEBUG_REG52_client_behavior_q_SIZE 2
+#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG52_tag_match_q_SIZE 1
+#define MH_DEBUG_REG52_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG52_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE 1
+#define MH_DEBUG_REG52_TAG_valid_q_SIZE 16
+
+#define MH_DEBUG_REG52_ARQ_RTR_SHIFT   0
+#define MH_DEBUG_REG52_MMU_WE_SHIFT    1
+#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT 2
+#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT 3
+#define MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT 4
+#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5
+#define MH_DEBUG_REG52_pa_in_mpu_range_SHIFT 6
+#define MH_DEBUG_REG52_stage1_valid_SHIFT 7
+#define MH_DEBUG_REG52_stage2_valid_SHIFT 8
+#define MH_DEBUG_REG52_client_behavior_q_SHIFT 9
+#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT 11
+#define MH_DEBUG_REG52_tag_match_q_SHIFT 12
+#define MH_DEBUG_REG52_tag_miss_q_SHIFT 13
+#define MH_DEBUG_REG52_va_in_range_q_SHIFT 14
+#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT 15
+#define MH_DEBUG_REG52_TAG_valid_q_SHIFT 16
+
+#define MH_DEBUG_REG52_ARQ_RTR_MASK    0x00000001
+#define MH_DEBUG_REG52_MMU_WE_MASK     0x00000002
+#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK 0x00000004
+#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK 0x00000008
+#define MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK 0x00000010
+#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020
+#define MH_DEBUG_REG52_pa_in_mpu_range_MASK 0x00000040
+#define MH_DEBUG_REG52_stage1_valid_MASK 0x00000080
+#define MH_DEBUG_REG52_stage2_valid_MASK 0x00000100
+#define MH_DEBUG_REG52_client_behavior_q_MASK 0x00000600
+#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK 0x00000800
+#define MH_DEBUG_REG52_tag_match_q_MASK 0x00001000
+#define MH_DEBUG_REG52_tag_miss_q_MASK 0x00002000
+#define MH_DEBUG_REG52_va_in_range_q_MASK 0x00004000
+#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK 0x00008000
+#define MH_DEBUG_REG52_TAG_valid_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG52_MASK \
+     (MH_DEBUG_REG52_ARQ_RTR_MASK | \
+      MH_DEBUG_REG52_MMU_WE_MASK | \
+      MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \
+      MH_DEBUG_REG52_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG52_stage1_valid_MASK | \
+      MH_DEBUG_REG52_stage2_valid_MASK | \
+      MH_DEBUG_REG52_client_behavior_q_MASK | \
+      MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG52_tag_match_q_MASK | \
+      MH_DEBUG_REG52_tag_miss_q_MASK | \
+      MH_DEBUG_REG52_va_in_range_q_MASK | \
+      MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK | \
+      MH_DEBUG_REG52_TAG_valid_q_MASK)
+
+#define MH_DEBUG_REG52(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \
+     ((arq_rtr << MH_DEBUG_REG52_ARQ_RTR_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG52_MMU_WE_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT) | \
+      (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG52_pa_in_mpu_range_SHIFT) | \
+      (stage1_valid << MH_DEBUG_REG52_stage1_valid_SHIFT) | \
+      (stage2_valid << MH_DEBUG_REG52_stage2_valid_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG52_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG52_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG52_va_in_range_q_SHIFT) | \
+      (pte_fetch_complete_q << MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT) | \
+      (tag_valid_q << MH_DEBUG_REG52_TAG_valid_q_SHIFT))
+
+#define MH_DEBUG_REG52_GET_ARQ_RTR(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARQ_RTR_MASK) >> MH_DEBUG_REG52_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG52_GET_MMU_WE(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_WE_MASK) >> MH_DEBUG_REG52_MMU_WE_SHIFT)
+#define MH_DEBUG_REG52_GET_CTRL_TLBMISS_RE_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG52_GET_TLBMISS_CTRL_RTS(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG52_GET_MH_TLBMISS_SEND(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG52_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG52_GET_pa_in_mpu_range(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_pa_in_mpu_range_MASK) >> MH_DEBUG_REG52_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG52_GET_stage1_valid(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_stage1_valid_MASK) >> MH_DEBUG_REG52_stage1_valid_SHIFT)
+#define MH_DEBUG_REG52_GET_stage2_valid(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_stage2_valid_MASK) >> MH_DEBUG_REG52_stage2_valid_SHIFT)
+#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG52_GET_IGNORE_TAG_MISS_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG52_GET_tag_match_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_tag_match_q_MASK) >> MH_DEBUG_REG52_tag_match_q_SHIFT)
+#define MH_DEBUG_REG52_GET_tag_miss_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_tag_miss_q_MASK) >> MH_DEBUG_REG52_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG52_GET_va_in_range_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_va_in_range_q_MASK) >> MH_DEBUG_REG52_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG52_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG52_GET_TAG_valid_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_TAG_valid_q_MASK) >> MH_DEBUG_REG52_TAG_valid_q_SHIFT)
+
+#define MH_DEBUG_REG52_SET_ARQ_RTR(mh_debug_reg52_reg, arq_rtr) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG52_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG52_SET_MMU_WE(mh_debug_reg52_reg, mmu_we) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG52_MMU_WE_SHIFT)
+#define MH_DEBUG_REG52_SET_CTRL_TLBMISS_RE_q(mh_debug_reg52_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG52_SET_TLBMISS_CTRL_RTS(mh_debug_reg52_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG52_SET_MH_TLBMISS_SEND(mh_debug_reg52_reg, mh_tlbmiss_send) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG52_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg52_reg, mmu_stall_awaiting_tlb_miss_fetch) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG52_SET_pa_in_mpu_range(mh_debug_reg52_reg, pa_in_mpu_range) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG52_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG52_SET_stage1_valid(mh_debug_reg52_reg, stage1_valid) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG52_stage1_valid_SHIFT)
+#define MH_DEBUG_REG52_SET_stage2_valid(mh_debug_reg52_reg, stage2_valid) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG52_stage2_valid_SHIFT)
+#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG52_SET_IGNORE_TAG_MISS_q(mh_debug_reg52_reg, ignore_tag_miss_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG52_SET_tag_match_q(mh_debug_reg52_reg, tag_match_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG52_tag_match_q_SHIFT)
+#define MH_DEBUG_REG52_SET_tag_miss_q(mh_debug_reg52_reg, tag_miss_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG52_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG52_SET_va_in_range_q(mh_debug_reg52_reg, va_in_range_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG52_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG52_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg52_reg, pte_fetch_complete_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG52_SET_TAG_valid_q(mh_debug_reg52_reg, tag_valid_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG52_TAG_valid_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int arq_rtr                        : MH_DEBUG_REG52_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG52_MMU_WE_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG52_pa_in_mpu_range_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG52_stage1_valid_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG52_stage2_valid_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG52_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG52_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG52_va_in_range_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int tag_valid_q                    : MH_DEBUG_REG52_TAG_valid_q_SIZE;
+     } mh_debug_reg52_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int tag_valid_q                    : MH_DEBUG_REG52_TAG_valid_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG52_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG52_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG52_tag_match_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG52_stage2_valid_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG52_stage1_valid_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG52_pa_in_mpu_range_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG52_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG52_ARQ_RTR_SIZE;
+     } mh_debug_reg52_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg52_t f;
+} mh_debug_reg52_u;
+
+
+/*
+ * MH_DEBUG_REG53 struct
+ */
+
+#define MH_DEBUG_REG53_TAG0_VA_SIZE    13
+#define MH_DEBUG_REG53_TAG_valid_q_0_SIZE 1
+#define MH_DEBUG_REG53_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG53_TAG1_VA_SIZE    13
+#define MH_DEBUG_REG53_TAG_valid_q_1_SIZE 1
+
+#define MH_DEBUG_REG53_TAG0_VA_SHIFT   0
+#define MH_DEBUG_REG53_TAG_valid_q_0_SHIFT 13
+#define MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG53_TAG1_VA_SHIFT   16
+#define MH_DEBUG_REG53_TAG_valid_q_1_SHIFT 29
+
+#define MH_DEBUG_REG53_TAG0_VA_MASK    0x00001fff
+#define MH_DEBUG_REG53_TAG_valid_q_0_MASK 0x00002000
+#define MH_DEBUG_REG53_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG53_TAG1_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG53_TAG_valid_q_1_MASK 0x20000000
+
+#define MH_DEBUG_REG53_MASK \
+     (MH_DEBUG_REG53_TAG0_VA_MASK | \
+      MH_DEBUG_REG53_TAG_valid_q_0_MASK | \
+      MH_DEBUG_REG53_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG53_TAG1_VA_MASK | \
+      MH_DEBUG_REG53_TAG_valid_q_1_MASK)
+
+#define MH_DEBUG_REG53(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \
+     ((tag0_va << MH_DEBUG_REG53_TAG0_VA_SHIFT) | \
+      (tag_valid_q_0 << MH_DEBUG_REG53_TAG_valid_q_0_SHIFT) | \
+      (always_zero << MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT) | \
+      (tag1_va << MH_DEBUG_REG53_TAG1_VA_SHIFT) | \
+      (tag_valid_q_1 << MH_DEBUG_REG53_TAG_valid_q_1_SHIFT))
+
+#define MH_DEBUG_REG53_GET_TAG0_VA(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_TAG0_VA_MASK) >> MH_DEBUG_REG53_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG53_GET_TAG_valid_q_0(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_TAG_valid_q_0_MASK) >> MH_DEBUG_REG53_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG53_GET_ALWAYS_ZERO(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG53_GET_TAG1_VA(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_TAG1_VA_MASK) >> MH_DEBUG_REG53_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG53_GET_TAG_valid_q_1(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_TAG_valid_q_1_MASK) >> MH_DEBUG_REG53_TAG_valid_q_1_SHIFT)
+
+#define MH_DEBUG_REG53_SET_TAG0_VA(mh_debug_reg53_reg, tag0_va) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG53_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG53_SET_TAG_valid_q_0(mh_debug_reg53_reg, tag_valid_q_0) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG53_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG53_SET_ALWAYS_ZERO(mh_debug_reg53_reg, always_zero) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG53_SET_TAG1_VA(mh_debug_reg53_reg, tag1_va) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG53_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG53_SET_TAG_valid_q_1(mh_debug_reg53_reg, tag_valid_q_1) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG53_TAG_valid_q_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int tag0_va                        : MH_DEBUG_REG53_TAG0_VA_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG53_TAG_valid_q_0_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG53_ALWAYS_ZERO_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG53_TAG1_VA_SIZE;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG53_TAG_valid_q_1_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg53_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG53_TAG_valid_q_1_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG53_TAG1_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG53_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG53_TAG_valid_q_0_SIZE;
+          unsigned int tag0_va                        : MH_DEBUG_REG53_TAG0_VA_SIZE;
+     } mh_debug_reg53_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg53_t f;
+} mh_debug_reg53_u;
+
+
+/*
+ * MH_DEBUG_REG54 struct
+ */
+
+#define MH_DEBUG_REG54_TAG2_VA_SIZE    13
+#define MH_DEBUG_REG54_TAG_valid_q_2_SIZE 1
+#define MH_DEBUG_REG54_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG54_TAG3_VA_SIZE    13
+#define MH_DEBUG_REG54_TAG_valid_q_3_SIZE 1
+
+#define MH_DEBUG_REG54_TAG2_VA_SHIFT   0
+#define MH_DEBUG_REG54_TAG_valid_q_2_SHIFT 13
+#define MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG54_TAG3_VA_SHIFT   16
+#define MH_DEBUG_REG54_TAG_valid_q_3_SHIFT 29
+
+#define MH_DEBUG_REG54_TAG2_VA_MASK    0x00001fff
+#define MH_DEBUG_REG54_TAG_valid_q_2_MASK 0x00002000
+#define MH_DEBUG_REG54_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG54_TAG3_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG54_TAG_valid_q_3_MASK 0x20000000
+
+#define MH_DEBUG_REG54_MASK \
+     (MH_DEBUG_REG54_TAG2_VA_MASK | \
+      MH_DEBUG_REG54_TAG_valid_q_2_MASK | \
+      MH_DEBUG_REG54_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG54_TAG3_VA_MASK | \
+      MH_DEBUG_REG54_TAG_valid_q_3_MASK)
+
+#define MH_DEBUG_REG54(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \
+     ((tag2_va << MH_DEBUG_REG54_TAG2_VA_SHIFT) | \
+      (tag_valid_q_2 << MH_DEBUG_REG54_TAG_valid_q_2_SHIFT) | \
+      (always_zero << MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT) | \
+      (tag3_va << MH_DEBUG_REG54_TAG3_VA_SHIFT) | \
+      (tag_valid_q_3 << MH_DEBUG_REG54_TAG_valid_q_3_SHIFT))
+
+#define MH_DEBUG_REG54_GET_TAG2_VA(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG2_VA_MASK) >> MH_DEBUG_REG54_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG_valid_q_2(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_2_MASK) >> MH_DEBUG_REG54_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG54_GET_ALWAYS_ZERO(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG3_VA(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG3_VA_MASK) >> MH_DEBUG_REG54_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG_valid_q_3(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_3_MASK) >> MH_DEBUG_REG54_TAG_valid_q_3_SHIFT)
+
+#define MH_DEBUG_REG54_SET_TAG2_VA(mh_debug_reg54_reg, tag2_va) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG54_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG_valid_q_2(mh_debug_reg54_reg, tag_valid_q_2) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG54_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG54_SET_ALWAYS_ZERO(mh_debug_reg54_reg, always_zero) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG3_VA(mh_debug_reg54_reg, tag3_va) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG54_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG_valid_q_3(mh_debug_reg54_reg, tag_valid_q_3) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG54_TAG_valid_q_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int tag2_va                        : MH_DEBUG_REG54_TAG2_VA_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG54_TAG_valid_q_2_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG54_ALWAYS_ZERO_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG54_TAG3_VA_SIZE;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG54_TAG_valid_q_3_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg54_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG54_TAG_valid_q_3_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG54_TAG3_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG54_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG54_TAG_valid_q_2_SIZE;
+          unsigned int tag2_va                        : MH_DEBUG_REG54_TAG2_VA_SIZE;
+     } mh_debug_reg54_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg54_t f;
+} mh_debug_reg54_u;
+
+
+/*
+ * MH_DEBUG_REG55 struct
+ */
+
+#define MH_DEBUG_REG55_TAG4_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_4_SIZE 1
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG55_TAG5_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_5_SIZE 1
+
+#define MH_DEBUG_REG55_TAG4_VA_SHIFT   0
+#define MH_DEBUG_REG55_TAG_valid_q_4_SHIFT 13
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG55_TAG5_VA_SHIFT   16
+#define MH_DEBUG_REG55_TAG_valid_q_5_SHIFT 29
+
+#define MH_DEBUG_REG55_TAG4_VA_MASK    0x00001fff
+#define MH_DEBUG_REG55_TAG_valid_q_4_MASK 0x00002000
+#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG55_TAG5_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG55_TAG_valid_q_5_MASK 0x20000000
+
+#define MH_DEBUG_REG55_MASK \
+     (MH_DEBUG_REG55_TAG4_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_4_MASK | \
+      MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG55_TAG5_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_5_MASK)
+
+#define MH_DEBUG_REG55(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \
+     ((tag4_va << MH_DEBUG_REG55_TAG4_VA_SHIFT) | \
+      (tag_valid_q_4 << MH_DEBUG_REG55_TAG_valid_q_4_SHIFT) | \
+      (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \
+      (tag5_va << MH_DEBUG_REG55_TAG5_VA_SHIFT) | \
+      (tag_valid_q_5 << MH_DEBUG_REG55_TAG_valid_q_5_SHIFT))
+
+#define MH_DEBUG_REG55_GET_TAG4_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG4_VA_MASK) >> MH_DEBUG_REG55_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_4(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_4_MASK) >> MH_DEBUG_REG55_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG5_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG5_VA_MASK) >> MH_DEBUG_REG55_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_5(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_5_MASK) >> MH_DEBUG_REG55_TAG_valid_q_5_SHIFT)
+
+#define MH_DEBUG_REG55_SET_TAG4_VA(mh_debug_reg55_reg, tag4_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG55_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_4(mh_debug_reg55_reg, tag_valid_q_4) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG55_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG5_VA(mh_debug_reg55_reg, tag5_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG55_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_5(mh_debug_reg55_reg, tag_valid_q_5) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG55_TAG_valid_q_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int tag4_va                        : MH_DEBUG_REG55_TAG4_VA_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG55_TAG_valid_q_4_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG55_TAG5_VA_SIZE;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG55_TAG_valid_q_5_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg55_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG55_TAG_valid_q_5_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG55_TAG5_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG55_TAG_valid_q_4_SIZE;
+          unsigned int tag4_va                        : MH_DEBUG_REG55_TAG4_VA_SIZE;
+     } mh_debug_reg55_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg55_t f;
+} mh_debug_reg55_u;
+
+
+/*
+ * MH_DEBUG_REG56 struct
+ */
+
+#define MH_DEBUG_REG56_TAG6_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_6_SIZE 1
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG56_TAG7_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_7_SIZE 1
+
+#define MH_DEBUG_REG56_TAG6_VA_SHIFT   0
+#define MH_DEBUG_REG56_TAG_valid_q_6_SHIFT 13
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG56_TAG7_VA_SHIFT   16
+#define MH_DEBUG_REG56_TAG_valid_q_7_SHIFT 29
+
+#define MH_DEBUG_REG56_TAG6_VA_MASK    0x00001fff
+#define MH_DEBUG_REG56_TAG_valid_q_6_MASK 0x00002000
+#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG56_TAG7_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG56_TAG_valid_q_7_MASK 0x20000000
+
+#define MH_DEBUG_REG56_MASK \
+     (MH_DEBUG_REG56_TAG6_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_6_MASK | \
+      MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG56_TAG7_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_7_MASK)
+
+#define MH_DEBUG_REG56(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \
+     ((tag6_va << MH_DEBUG_REG56_TAG6_VA_SHIFT) | \
+      (tag_valid_q_6 << MH_DEBUG_REG56_TAG_valid_q_6_SHIFT) | \
+      (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \
+      (tag7_va << MH_DEBUG_REG56_TAG7_VA_SHIFT) | \
+      (tag_valid_q_7 << MH_DEBUG_REG56_TAG_valid_q_7_SHIFT))
+
+#define MH_DEBUG_REG56_GET_TAG6_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG6_VA_MASK) >> MH_DEBUG_REG56_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_6(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_6_MASK) >> MH_DEBUG_REG56_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG7_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG7_VA_MASK) >> MH_DEBUG_REG56_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_7(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_7_MASK) >> MH_DEBUG_REG56_TAG_valid_q_7_SHIFT)
+
+#define MH_DEBUG_REG56_SET_TAG6_VA(mh_debug_reg56_reg, tag6_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG56_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_6(mh_debug_reg56_reg, tag_valid_q_6) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG56_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG7_VA(mh_debug_reg56_reg, tag7_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG56_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_7(mh_debug_reg56_reg, tag_valid_q_7) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG56_TAG_valid_q_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int tag6_va                        : MH_DEBUG_REG56_TAG6_VA_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG56_TAG_valid_q_6_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG56_TAG7_VA_SIZE;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG56_TAG_valid_q_7_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg56_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG56_TAG_valid_q_7_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG56_TAG7_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG56_TAG_valid_q_6_SIZE;
+          unsigned int tag6_va                        : MH_DEBUG_REG56_TAG6_VA_SIZE;
+     } mh_debug_reg56_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg56_t f;
+} mh_debug_reg56_u;
+
+
+/*
+ * MH_DEBUG_REG57 struct
+ */
+
+#define MH_DEBUG_REG57_TAG8_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_8_SIZE 1
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG57_TAG9_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_9_SIZE 1
+
+#define MH_DEBUG_REG57_TAG8_VA_SHIFT   0
+#define MH_DEBUG_REG57_TAG_valid_q_8_SHIFT 13
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG57_TAG9_VA_SHIFT   16
+#define MH_DEBUG_REG57_TAG_valid_q_9_SHIFT 29
+
+#define MH_DEBUG_REG57_TAG8_VA_MASK    0x00001fff
+#define MH_DEBUG_REG57_TAG_valid_q_8_MASK 0x00002000
+#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG57_TAG9_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG57_TAG_valid_q_9_MASK 0x20000000
+
+#define MH_DEBUG_REG57_MASK \
+     (MH_DEBUG_REG57_TAG8_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_8_MASK | \
+      MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG57_TAG9_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_9_MASK)
+
+#define MH_DEBUG_REG57(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \
+     ((tag8_va << MH_DEBUG_REG57_TAG8_VA_SHIFT) | \
+      (tag_valid_q_8 << MH_DEBUG_REG57_TAG_valid_q_8_SHIFT) | \
+      (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \
+      (tag9_va << MH_DEBUG_REG57_TAG9_VA_SHIFT) | \
+      (tag_valid_q_9 << MH_DEBUG_REG57_TAG_valid_q_9_SHIFT))
+
+#define MH_DEBUG_REG57_GET_TAG8_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG8_VA_MASK) >> MH_DEBUG_REG57_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_8(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_8_MASK) >> MH_DEBUG_REG57_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG9_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG9_VA_MASK) >> MH_DEBUG_REG57_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_9(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_9_MASK) >> MH_DEBUG_REG57_TAG_valid_q_9_SHIFT)
+
+#define MH_DEBUG_REG57_SET_TAG8_VA(mh_debug_reg57_reg, tag8_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG57_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_8(mh_debug_reg57_reg, tag_valid_q_8) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG57_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG9_VA(mh_debug_reg57_reg, tag9_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG57_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_9(mh_debug_reg57_reg, tag_valid_q_9) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG57_TAG_valid_q_9_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int tag8_va                        : MH_DEBUG_REG57_TAG8_VA_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG57_TAG_valid_q_8_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG57_TAG9_VA_SIZE;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG57_TAG_valid_q_9_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg57_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG57_TAG_valid_q_9_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG57_TAG9_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG57_TAG_valid_q_8_SIZE;
+          unsigned int tag8_va                        : MH_DEBUG_REG57_TAG8_VA_SIZE;
+     } mh_debug_reg57_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg57_t f;
+} mh_debug_reg57_u;
+
+
+/*
+ * MH_DEBUG_REG58 struct
+ */
+
+#define MH_DEBUG_REG58_TAG10_VA_SIZE   13
+#define MH_DEBUG_REG58_TAG_valid_q_10_SIZE 1
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG58_TAG11_VA_SIZE   13
+#define MH_DEBUG_REG58_TAG_valid_q_11_SIZE 1
+
+#define MH_DEBUG_REG58_TAG10_VA_SHIFT  0
+#define MH_DEBUG_REG58_TAG_valid_q_10_SHIFT 13
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG58_TAG11_VA_SHIFT  16
+#define MH_DEBUG_REG58_TAG_valid_q_11_SHIFT 29
+
+#define MH_DEBUG_REG58_TAG10_VA_MASK   0x00001fff
+#define MH_DEBUG_REG58_TAG_valid_q_10_MASK 0x00002000
+#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG58_TAG11_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG58_TAG_valid_q_11_MASK 0x20000000
+
+#define MH_DEBUG_REG58_MASK \
+     (MH_DEBUG_REG58_TAG10_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_10_MASK | \
+      MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG58_TAG11_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_11_MASK)
+
+#define MH_DEBUG_REG58(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \
+     ((tag10_va << MH_DEBUG_REG58_TAG10_VA_SHIFT) | \
+      (tag_valid_q_10 << MH_DEBUG_REG58_TAG_valid_q_10_SHIFT) | \
+      (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \
+      (tag11_va << MH_DEBUG_REG58_TAG11_VA_SHIFT) | \
+      (tag_valid_q_11 << MH_DEBUG_REG58_TAG_valid_q_11_SHIFT))
+
+#define MH_DEBUG_REG58_GET_TAG10_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG10_VA_MASK) >> MH_DEBUG_REG58_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_10(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_10_MASK) >> MH_DEBUG_REG58_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG11_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG11_VA_MASK) >> MH_DEBUG_REG58_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_11(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_11_MASK) >> MH_DEBUG_REG58_TAG_valid_q_11_SHIFT)
+
+#define MH_DEBUG_REG58_SET_TAG10_VA(mh_debug_reg58_reg, tag10_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG58_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_10(mh_debug_reg58_reg, tag_valid_q_10) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG58_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG11_VA(mh_debug_reg58_reg, tag11_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG58_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_11(mh_debug_reg58_reg, tag_valid_q_11) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG58_TAG_valid_q_11_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int tag10_va                       : MH_DEBUG_REG58_TAG10_VA_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG58_TAG_valid_q_10_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG58_TAG11_VA_SIZE;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG58_TAG_valid_q_11_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg58_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG58_TAG_valid_q_11_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG58_TAG11_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG58_TAG_valid_q_10_SIZE;
+          unsigned int tag10_va                       : MH_DEBUG_REG58_TAG10_VA_SIZE;
+     } mh_debug_reg58_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg58_t f;
+} mh_debug_reg58_u;
+
+
+/*
+ * MH_DEBUG_REG59 struct
+ */
+
+#define MH_DEBUG_REG59_TAG12_VA_SIZE   13
+#define MH_DEBUG_REG59_TAG_valid_q_12_SIZE 1
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG59_TAG13_VA_SIZE   13
+#define MH_DEBUG_REG59_TAG_valid_q_13_SIZE 1
+
+#define MH_DEBUG_REG59_TAG12_VA_SHIFT  0
+#define MH_DEBUG_REG59_TAG_valid_q_12_SHIFT 13
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG59_TAG13_VA_SHIFT  16
+#define MH_DEBUG_REG59_TAG_valid_q_13_SHIFT 29
+
+#define MH_DEBUG_REG59_TAG12_VA_MASK   0x00001fff
+#define MH_DEBUG_REG59_TAG_valid_q_12_MASK 0x00002000
+#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG59_TAG13_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG59_TAG_valid_q_13_MASK 0x20000000
+
+#define MH_DEBUG_REG59_MASK \
+     (MH_DEBUG_REG59_TAG12_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_12_MASK | \
+      MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG59_TAG13_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_13_MASK)
+
+#define MH_DEBUG_REG59(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \
+     ((tag12_va << MH_DEBUG_REG59_TAG12_VA_SHIFT) | \
+      (tag_valid_q_12 << MH_DEBUG_REG59_TAG_valid_q_12_SHIFT) | \
+      (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \
+      (tag13_va << MH_DEBUG_REG59_TAG13_VA_SHIFT) | \
+      (tag_valid_q_13 << MH_DEBUG_REG59_TAG_valid_q_13_SHIFT))
+
+#define MH_DEBUG_REG59_GET_TAG12_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG12_VA_MASK) >> MH_DEBUG_REG59_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_12(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_12_MASK) >> MH_DEBUG_REG59_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG13_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG13_VA_MASK) >> MH_DEBUG_REG59_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_13(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_13_MASK) >> MH_DEBUG_REG59_TAG_valid_q_13_SHIFT)
+
+#define MH_DEBUG_REG59_SET_TAG12_VA(mh_debug_reg59_reg, tag12_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG59_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_12(mh_debug_reg59_reg, tag_valid_q_12) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG59_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG13_VA(mh_debug_reg59_reg, tag13_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG59_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_13(mh_debug_reg59_reg, tag_valid_q_13) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG59_TAG_valid_q_13_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int tag12_va                       : MH_DEBUG_REG59_TAG12_VA_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG59_TAG_valid_q_12_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG59_TAG13_VA_SIZE;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG59_TAG_valid_q_13_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg59_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG59_TAG_valid_q_13_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG59_TAG13_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG59_TAG_valid_q_12_SIZE;
+          unsigned int tag12_va                       : MH_DEBUG_REG59_TAG12_VA_SIZE;
+     } mh_debug_reg59_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg59_t f;
+} mh_debug_reg59_u;
+
+
+/*
+ * MH_DEBUG_REG60 struct
+ */
+
+#define MH_DEBUG_REG60_TAG14_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_14_SIZE 1
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG60_TAG15_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_15_SIZE 1
+
+#define MH_DEBUG_REG60_TAG14_VA_SHIFT  0
+#define MH_DEBUG_REG60_TAG_valid_q_14_SHIFT 13
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG60_TAG15_VA_SHIFT  16
+#define MH_DEBUG_REG60_TAG_valid_q_15_SHIFT 29
+
+#define MH_DEBUG_REG60_TAG14_VA_MASK   0x00001fff
+#define MH_DEBUG_REG60_TAG_valid_q_14_MASK 0x00002000
+#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG60_TAG15_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG60_TAG_valid_q_15_MASK 0x20000000
+
+#define MH_DEBUG_REG60_MASK \
+     (MH_DEBUG_REG60_TAG14_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_14_MASK | \
+      MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG60_TAG15_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_15_MASK)
+
+#define MH_DEBUG_REG60(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \
+     ((tag14_va << MH_DEBUG_REG60_TAG14_VA_SHIFT) | \
+      (tag_valid_q_14 << MH_DEBUG_REG60_TAG_valid_q_14_SHIFT) | \
+      (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \
+      (tag15_va << MH_DEBUG_REG60_TAG15_VA_SHIFT) | \
+      (tag_valid_q_15 << MH_DEBUG_REG60_TAG_valid_q_15_SHIFT))
+
+#define MH_DEBUG_REG60_GET_TAG14_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG14_VA_MASK) >> MH_DEBUG_REG60_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_14(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_14_MASK) >> MH_DEBUG_REG60_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG15_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG15_VA_MASK) >> MH_DEBUG_REG60_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_15(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_15_MASK) >> MH_DEBUG_REG60_TAG_valid_q_15_SHIFT)
+
+#define MH_DEBUG_REG60_SET_TAG14_VA(mh_debug_reg60_reg, tag14_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG60_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_14(mh_debug_reg60_reg, tag_valid_q_14) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG60_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG15_VA(mh_debug_reg60_reg, tag15_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG60_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_15(mh_debug_reg60_reg, tag_valid_q_15) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG60_TAG_valid_q_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int tag14_va                       : MH_DEBUG_REG60_TAG14_VA_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG60_TAG_valid_q_14_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG60_TAG15_VA_SIZE;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG60_TAG_valid_q_15_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg60_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG60_TAG_valid_q_15_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG60_TAG15_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG60_TAG_valid_q_14_SIZE;
+          unsigned int tag14_va                       : MH_DEBUG_REG60_TAG14_VA_SIZE;
+     } mh_debug_reg60_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg60_t f;
+} mh_debug_reg60_u;
+
+
+/*
+ * MH_DEBUG_REG61 struct
+ */
+
+#define MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG61_MASK \
+     (MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG61(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG61_GET_MH_DBG_DEFAULT(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG61_SET_MH_DBG_DEFAULT(mh_debug_reg61_reg, mh_dbg_default) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg61_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg61_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg61_t f;
+} mh_debug_reg61_u;
+
+
+/*
+ * MH_DEBUG_REG62 struct
+ */
+
+#define MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG62_MASK \
+     (MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG62(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG62_GET_MH_DBG_DEFAULT(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG62_SET_MH_DBG_DEFAULT(mh_debug_reg62_reg, mh_dbg_default) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg62_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg62_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg62_t f;
+} mh_debug_reg62_u;
+
+
+/*
+ * MH_DEBUG_REG63 struct
+ */
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG63_MASK \
+     (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG63(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \
+     ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \
+     mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg63_t f;
+} mh_debug_reg63_u;
+
+
+/*
+ * MH_MMU_CONFIG struct
+ */
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SIZE  1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1
+#define MH_MMU_CONFIG_RESERVED1_SIZE   2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1
+#define MH_MMU_CONFIG_RESERVED1_SHIFT  2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22
+
+#define MH_MMU_CONFIG_MMU_ENABLE_MASK  0x00000001
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002
+#define MH_MMU_CONFIG_RESERVED1_MASK   0x0000000c
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000
+
+#define MH_MMU_CONFIG_MASK \
+     (MH_MMU_CONFIG_MMU_ENABLE_MASK | \
+      MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \
+      MH_MMU_CONFIG_RESERVED1_MASK | \
+      MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK)
+
+#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior) \
+     ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \
+      (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \
+      (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \
+      (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT))
+
+#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+
+#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int                                : 8;
+     } mh_mmu_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int                                : 8;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+     } mh_mmu_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_config_t f;
+} mh_mmu_config_u;
+
+
+/*
+ * MH_MMU_VA_RANGE struct
+ */
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12
+#define MH_MMU_VA_RANGE_VA_BASE_SIZE   20
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0
+#define MH_MMU_VA_RANGE_VA_BASE_SHIFT  12
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff
+#define MH_MMU_VA_RANGE_VA_BASE_MASK   0xfffff000
+
+#define MH_MMU_VA_RANGE_MASK \
+     (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \
+      MH_MMU_VA_RANGE_VA_BASE_MASK)
+
+#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \
+     ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \
+      (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT))
+
+#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+     } mh_mmu_va_range_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+     } mh_mmu_va_range_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_va_range_t f;
+} mh_mmu_va_range_u;
+
+
+/*
+ * MH_MMU_PT_BASE struct
+ */
+
+#define MH_MMU_PT_BASE_PT_BASE_SIZE    20
+
+#define MH_MMU_PT_BASE_PT_BASE_SHIFT   12
+
+#define MH_MMU_PT_BASE_PT_BASE_MASK    0xfffff000
+
+#define MH_MMU_PT_BASE_MASK \
+     (MH_MMU_PT_BASE_PT_BASE_MASK)
+
+#define MH_MMU_PT_BASE(pt_base) \
+     ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT))
+
+#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \
+     ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \
+     mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int                                : 12;
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+     } mh_mmu_pt_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_pt_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_pt_base_t f;
+} mh_mmu_pt_base_u;
+
+
+/*
+ * MH_MMU_PAGE_FAULT struct
+ */
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE  3
+#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE  20
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4
+#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11
+#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001
+#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c
+#define MH_MMU_PAGE_FAULT_AXI_ID_MASK  0x00000070
+#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800
+#define MH_MMU_PAGE_FAULT_REQ_VA_MASK  0xfffff000
+
+#define MH_MMU_PAGE_FAULT_MASK \
+     (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \
+      MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \
+      MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_PAGE_FAULT_AXI_ID_MASK | \
+      MH_MMU_PAGE_FAULT_RESERVED1_MASK | \
+      MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_REQ_VA_MASK)
+
+#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \
+     ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \
+      (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \
+      (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \
+      (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \
+      (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \
+      (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \
+      (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \
+      (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT))
+
+#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+     } mh_mmu_page_fault_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+     } mh_mmu_page_fault_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_page_fault_t f;
+} mh_mmu_page_fault_u;
+
+
+/*
+ * MH_MMU_TRAN_ERROR struct
+ */
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0
+
+#define MH_MMU_TRAN_ERROR_MASK \
+     (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK)
+
+#define MH_MMU_TRAN_ERROR(tran_error) \
+     ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT))
+
+#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \
+     ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \
+     mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int                                : 5;
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+     } mh_mmu_tran_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+          unsigned int                                : 5;
+     } mh_mmu_tran_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_tran_error_t f;
+} mh_mmu_tran_error_u;
+
+
+/*
+ * MH_MMU_INVALIDATE struct
+ */
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002
+
+#define MH_MMU_INVALIDATE_MASK \
+     (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_MMU_INVALIDATE_INVALIDATE_TC_MASK)
+
+#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \
+     ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT))
+
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int                                : 30;
+     } mh_mmu_invalidate_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int                                : 30;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+     } mh_mmu_invalidate_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_invalidate_t f;
+} mh_mmu_invalidate_u;
+
+
+/*
+ * MH_MMU_MPU_BASE struct
+ */
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SIZE  20
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12
+
+#define MH_MMU_MPU_BASE_MPU_BASE_MASK  0xfffff000
+
+#define MH_MMU_MPU_BASE_MASK \
+     (MH_MMU_MPU_BASE_MPU_BASE_MASK)
+
+#define MH_MMU_MPU_BASE(mpu_base) \
+     ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT))
+
+#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \
+     ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \
+     mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int                                : 12;
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+     } mh_mmu_mpu_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_base_t f;
+} mh_mmu_mpu_base_u;
+
+
+/*
+ * MH_MMU_MPU_END struct
+ */
+
+#define MH_MMU_MPU_END_MPU_END_SIZE    20
+
+#define MH_MMU_MPU_END_MPU_END_SHIFT   12
+
+#define MH_MMU_MPU_END_MPU_END_MASK    0xfffff000
+
+#define MH_MMU_MPU_END_MASK \
+     (MH_MMU_MPU_END_MPU_END_MASK)
+
+#define MH_MMU_MPU_END(mpu_end) \
+     ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT))
+
+#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \
+     ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \
+     mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int                                : 12;
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+     } mh_mmu_mpu_end_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_end_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_end_t f;
+} mh_mmu_mpu_end_u;
+
+
+#endif
+
+
+#if !defined (_PA_FIDDLE_H)
+#define _PA_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  pa_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * PA_CL_VPORT_XSCALE struct
+ */
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_XSCALE_MASK \
+     (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK)
+
+#define PA_CL_VPORT_XSCALE(vport_xscale) \
+     ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT))
+
+#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \
+     ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \
+     pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xscale_t f;
+} pa_cl_vport_xscale_u;
+
+
+/*
+ * PA_CL_VPORT_XOFFSET struct
+ */
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_XOFFSET_MASK \
+     (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK)
+
+#define PA_CL_VPORT_XOFFSET(vport_xoffset) \
+     ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT))
+
+#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \
+     ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \
+     pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xoffset_t f;
+} pa_cl_vport_xoffset_u;
+
+
+/*
+ * PA_CL_VPORT_YSCALE struct
+ */
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_YSCALE_MASK \
+     (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK)
+
+#define PA_CL_VPORT_YSCALE(vport_yscale) \
+     ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT))
+
+#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \
+     ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \
+     pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yscale_t f;
+} pa_cl_vport_yscale_u;
+
+
+/*
+ * PA_CL_VPORT_YOFFSET struct
+ */
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_YOFFSET_MASK \
+     (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK)
+
+#define PA_CL_VPORT_YOFFSET(vport_yoffset) \
+     ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT))
+
+#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \
+     ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \
+     pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yoffset_t f;
+} pa_cl_vport_yoffset_u;
+
+
+/*
+ * PA_CL_VPORT_ZSCALE struct
+ */
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZSCALE_MASK \
+     (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK)
+
+#define PA_CL_VPORT_ZSCALE(vport_zscale) \
+     ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT))
+
+#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \
+     ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \
+     pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zscale_t f;
+} pa_cl_vport_zscale_u;
+
+
+/*
+ * PA_CL_VPORT_ZOFFSET struct
+ */
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZOFFSET_MASK \
+     (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK)
+
+#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \
+     ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT))
+
+#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \
+     ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \
+     pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zoffset_t f;
+} pa_cl_vport_zoffset_u;
+
+
+/*
+ * PA_CL_VTE_CNTL struct
+ */
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE  1
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK  0x00000200
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800
+
+#define PA_CL_VTE_CNTL_MASK \
+     (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \
+      PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK)
+
+#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \
+     ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \
+      (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \
+      (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \
+      (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \
+      (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \
+      (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \
+      (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \
+      (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \
+      (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \
+      (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT))
+
+#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int                                : 2;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int                                : 20;
+     } pa_cl_vte_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int                                : 20;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int                                : 2;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+     } pa_cl_vte_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vte_cntl_t f;
+} pa_cl_vte_cntl_u;
+
+
+/*
+ * PA_CL_CLIP_CNTL struct
+ */
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000
+
+#define PA_CL_CLIP_CNTL_MASK \
+     (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \
+      PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \
+      PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \
+      PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \
+      PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \
+      PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK)
+
+#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \
+     ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \
+      (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \
+      (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \
+      (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \
+      (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \
+      (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \
+      (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \
+      (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT))
+
+#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 16;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int                                : 7;
+     } pa_cl_clip_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 7;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 16;
+     } pa_cl_clip_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_clip_cntl_t f;
+} pa_cl_clip_cntl_u;
+
+
+/*
+ * PA_CL_GB_VERT_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_CLIP_ADJ_MASK \
+     (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \
+     ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \
+     pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_clip_adj_t f;
+} pa_cl_gb_vert_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_VERT_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_DISC_ADJ_MASK \
+     (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \
+     ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \
+     pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_disc_adj_t f;
+} pa_cl_gb_vert_disc_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \
+     (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \
+     ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \
+     pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_clip_adj_t f;
+} pa_cl_gb_horz_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_DISC_ADJ_MASK \
+     (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \
+     ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \
+     pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_disc_adj_t f;
+} pa_cl_gb_horz_disc_adj_u;
+
+
+/*
+ * PA_CL_ENHANCE struct
+ */
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1
+#define PA_CL_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0
+#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001
+#define PA_CL_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_CL_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_CL_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_CL_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_CL_ENHANCE_MASK \
+     (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE3_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE2_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE1_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \
+      (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+          unsigned int                                : 27;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_cl_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 27;
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+     } pa_cl_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_enhance_t f;
+} pa_cl_enhance_u;
+
+
+/*
+ * PA_SC_ENHANCE struct
+ */
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_SC_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_SC_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_SC_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_SC_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_SC_ENHANCE_MASK \
+     (PA_SC_ENHANCE_ECO_SPARE3_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE2_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE1_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int                                : 28;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_sc_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 28;
+     } pa_sc_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_enhance_t f;
+} pa_sc_enhance_u;
+
+
+/*
+ * PA_SU_VTX_CNTL struct
+ */
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1
+#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2
+#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0
+#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1
+#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001
+#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006
+#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038
+
+#define PA_SU_VTX_CNTL_MASK \
+     (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \
+      PA_SU_VTX_CNTL_ROUND_MODE_MASK | \
+      PA_SU_VTX_CNTL_QUANT_MODE_MASK)
+
+#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \
+     ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \
+      (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \
+      (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT))
+
+#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int                                : 26;
+     } pa_su_vtx_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int                                : 26;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+     } pa_su_vtx_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_vtx_cntl_t f;
+} pa_su_vtx_cntl_u;
+
+
+/*
+ * PA_SU_POINT_SIZE struct
+ */
+
+#define PA_SU_POINT_SIZE_HEIGHT_SIZE   16
+#define PA_SU_POINT_SIZE_WIDTH_SIZE    16
+
+#define PA_SU_POINT_SIZE_HEIGHT_SHIFT  0
+#define PA_SU_POINT_SIZE_WIDTH_SHIFT   16
+
+#define PA_SU_POINT_SIZE_HEIGHT_MASK   0x0000ffff
+#define PA_SU_POINT_SIZE_WIDTH_MASK    0xffff0000
+
+#define PA_SU_POINT_SIZE_MASK \
+     (PA_SU_POINT_SIZE_HEIGHT_MASK | \
+      PA_SU_POINT_SIZE_WIDTH_MASK)
+
+#define PA_SU_POINT_SIZE(height, width) \
+     ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \
+      (width << PA_SU_POINT_SIZE_WIDTH_SHIFT))
+
+#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+     } pa_su_point_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+     } pa_su_point_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_size_t f;
+} pa_su_point_size_u;
+
+
+/*
+ * PA_SU_POINT_MINMAX struct
+ */
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff
+#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000
+
+#define PA_SU_POINT_MINMAX_MASK \
+     (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \
+      PA_SU_POINT_MINMAX_MAX_SIZE_MASK)
+
+#define PA_SU_POINT_MINMAX(min_size, max_size) \
+     ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \
+      (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT))
+
+#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_minmax_t f;
+} pa_su_point_minmax_u;
+
+
+/*
+ * PA_SU_LINE_CNTL struct
+ */
+
+#define PA_SU_LINE_CNTL_WIDTH_SIZE     16
+
+#define PA_SU_LINE_CNTL_WIDTH_SHIFT    0
+
+#define PA_SU_LINE_CNTL_WIDTH_MASK     0x0000ffff
+
+#define PA_SU_LINE_CNTL_MASK \
+     (PA_SU_LINE_CNTL_WIDTH_MASK)
+
+#define PA_SU_LINE_CNTL(width) \
+     ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT))
+
+#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \
+     ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \
+     pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+          unsigned int                                : 16;
+     } pa_su_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int                                : 16;
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+     } pa_su_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_line_cntl_t f;
+} pa_su_line_cntl_u;
+
+
+/*
+ * PA_SU_SC_MODE_CNTL struct
+ */
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_SIZE   1
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1
+#define PA_SU_SC_MODE_CNTL_FACE_SHIFT  2
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002
+#define PA_SU_SC_MODE_CNTL_FACE_MASK   0x00000004
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000
+
+#define PA_SU_SC_MODE_CNTL_MASK \
+     (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \
+      PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \
+      PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \
+      PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \
+      PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK)
+
+#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state) \
+     ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \
+      (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \
+      (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \
+      (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \
+      (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \
+      (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \
+      (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \
+      (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \
+      (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \
+      (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \
+      (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \
+      (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \
+      (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \
+      (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \
+      (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \
+      (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \
+      (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \
+      (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT))
+
+#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+
+#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int                                : 5;
+     } pa_su_sc_mode_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int                                : 5;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_sc_mode_cntl_t f;
+} pa_su_sc_mode_cntl_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \
+     ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \
+     pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_scale_t f;
+} pa_su_poly_offset_front_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \
+     ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \
+     pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_offset_t f;
+} pa_su_poly_offset_front_offset_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \
+     ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \
+     pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_scale_t f;
+} pa_su_poly_offset_back_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \
+     ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \
+     pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_offset_t f;
+} pa_su_poly_offset_back_offset_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER0_SELECT_MASK \
+     (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \
+     ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \
+     pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_select_t f;
+} pa_su_perfcounter0_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER1_SELECT_MASK \
+     (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \
+     ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \
+     pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_select_t f;
+} pa_su_perfcounter1_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER2_SELECT_MASK \
+     (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \
+     ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \
+     pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_select_t f;
+} pa_su_perfcounter2_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER3_SELECT_MASK \
+     (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \
+     ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \
+     pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_select_t f;
+} pa_su_perfcounter3_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER0_LOW_MASK \
+     (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \
+     ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \
+     pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_low_t f;
+} pa_su_perfcounter0_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER0_HI_MASK \
+     (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \
+     ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \
+     pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_hi_t f;
+} pa_su_perfcounter0_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER1_LOW_MASK \
+     (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \
+     ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \
+     pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_low_t f;
+} pa_su_perfcounter1_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER1_HI_MASK \
+     (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \
+     ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \
+     pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_hi_t f;
+} pa_su_perfcounter1_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER2_LOW_MASK \
+     (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \
+     ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \
+     pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_low_t f;
+} pa_su_perfcounter2_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER2_HI_MASK \
+     (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \
+     ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \
+     pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_hi_t f;
+} pa_su_perfcounter2_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER3_LOW_MASK \
+     (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \
+     ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \
+     pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_low_t f;
+} pa_su_perfcounter3_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER3_HI_MASK \
+     (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \
+     ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \
+     pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_hi_t f;
+} pa_su_perfcounter3_hi_u;
+
+
+/*
+ * PA_SC_WINDOW_OFFSET struct
+ */
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000
+
+#define PA_SC_WINDOW_OFFSET_MASK \
+     (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \
+      PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK)
+
+#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \
+     ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \
+      (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT))
+
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_window_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+     } pa_sc_window_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_offset_t f;
+} pa_sc_window_offset_u;
+
+
+/*
+ * PA_SC_AA_CONFIG struct
+ */
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000
+
+#define PA_SC_AA_CONFIG_MASK \
+     (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \
+      PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK)
+
+#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \
+     ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \
+      (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT))
+
+#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+          unsigned int                                : 10;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 15;
+     } pa_sc_aa_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int                                : 15;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 10;
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+     } pa_sc_aa_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_config_t f;
+} pa_sc_aa_config_u;
+
+
+/*
+ * PA_SC_AA_MASK struct
+ */
+
+#define PA_SC_AA_MASK_AA_MASK_SIZE     16
+
+#define PA_SC_AA_MASK_AA_MASK_SHIFT    0
+
+#define PA_SC_AA_MASK_AA_MASK_MASK     0x0000ffff
+
+#define PA_SC_AA_MASK_MASK \
+     (PA_SC_AA_MASK_AA_MASK_MASK)
+
+#define PA_SC_AA_MASK(aa_mask) \
+     ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT))
+
+#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \
+     ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \
+     pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_aa_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int                                : 16;
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+     } pa_sc_aa_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_mask_t f;
+} pa_sc_aa_mask_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000
+
+#define PA_SC_LINE_STIPPLE_MASK \
+     (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \
+      PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \
+      PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \
+      PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK)
+
+#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \
+     ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \
+      (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \
+      (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \
+      (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_line_stipple_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int                                : 1;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int                                : 4;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+     } pa_sc_line_stipple_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_t f;
+} pa_sc_line_stipple_u;
+
+
+/*
+ * PA_SC_LINE_CNTL struct
+ */
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200
+#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400
+
+#define PA_SC_LINE_CNTL_MASK \
+     (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \
+      PA_SC_LINE_CNTL_LAST_PIXEL_MASK)
+
+#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \
+     ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \
+      (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \
+      (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \
+      (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT))
+
+#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int                                : 21;
+     } pa_sc_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int                                : 21;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+     } pa_sc_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_cntl_t f;
+} pa_sc_line_cntl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_TL struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000
+
+#define PA_SC_WINDOW_SCISSOR_TL_MASK \
+     (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \
+     ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \
+      (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_tl_t f;
+} pa_sc_window_scissor_tl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_BR struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000
+
+#define PA_SC_WINDOW_SCISSOR_BR_MASK \
+     (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+     } pa_sc_window_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_window_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_br_t f;
+} pa_sc_window_scissor_br_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_TL struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_TL_MASK \
+     (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \
+     ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_screen_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_tl_t f;
+} pa_sc_screen_scissor_tl_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_BR struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_BR_MASK \
+     (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_screen_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_br_t f;
+} pa_sc_screen_scissor_br_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY struct
+ */
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080
+
+#define PA_SC_VIZ_QUERY_MASK \
+     (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \
+      PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \
+      PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK)
+
+#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \
+     ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \
+      (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \
+      (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT))
+
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int                                : 1;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_viz_query_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int                                : 24;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 1;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+     } pa_sc_viz_query_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_t f;
+} pa_sc_viz_query_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY_STATUS struct
+ */
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff
+
+#define PA_SC_VIZ_QUERY_STATUS_MASK \
+     (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK)
+
+#define PA_SC_VIZ_QUERY_STATUS(status_bits) \
+     ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT))
+
+#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \
+     ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \
+     pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_status_t f;
+} pa_sc_viz_query_status_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE_STATE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00
+
+#define PA_SC_LINE_STIPPLE_STATE_MASK \
+     (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \
+      PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK)
+
+#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \
+     ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \
+      (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_line_stipple_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int                                : 16;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+     } pa_sc_line_stipple_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_state_t f;
+} pa_sc_line_stipple_state_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SC_PERFCOUNTER0_SELECT_MASK \
+     (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \
+     ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \
+     pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_sc_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_select_t f;
+} pa_sc_perfcounter0_select_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SC_PERFCOUNTER0_LOW_MASK \
+     (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \
+     ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \
+     pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_low_t f;
+} pa_sc_perfcounter0_low_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SC_PERFCOUNTER0_HI_MASK \
+     (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \
+     ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \
+     pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_hi_t f;
+} pa_sc_perfcounter0_hi_u;
+
+
+/*
+ * PA_CL_CNTL_STATUS struct
+ */
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000
+
+#define PA_CL_CNTL_STATUS_MASK \
+     (PA_CL_CNTL_STATUS_CL_BUSY_MASK)
+
+#define PA_CL_CNTL_STATUS(cl_busy) \
+     ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT))
+
+#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \
+     ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \
+     pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+     } pa_cl_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_cl_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_cntl_status_t f;
+} pa_cl_cntl_status_u;
+
+
+/*
+ * PA_SU_CNTL_STATUS struct
+ */
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000
+
+#define PA_SU_CNTL_STATUS_MASK \
+     (PA_SU_CNTL_STATUS_SU_BUSY_MASK)
+
+#define PA_SU_CNTL_STATUS(su_busy) \
+     ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT))
+
+#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \
+     ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \
+     pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+     } pa_su_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_su_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_cntl_status_t f;
+} pa_su_cntl_status_u;
+
+
+/*
+ * PA_SC_CNTL_STATUS struct
+ */
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000
+
+#define PA_SC_CNTL_STATUS_MASK \
+     (PA_SC_CNTL_STATUS_SC_BUSY_MASK)
+
+#define PA_SC_CNTL_STATUS(sc_busy) \
+     ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT))
+
+#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \
+     ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \
+     pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+     } pa_sc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_sc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_cntl_status_t f;
+} pa_sc_cntl_status_u;
+
+
+/*
+ * PA_SU_DEBUG_CNTL struct
+ */
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SU_DEBUG_CNTL_MASK \
+     (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK)
+
+#define PA_SU_DEBUG_CNTL(su_debug_indx) \
+     ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT))
+
+#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \
+     ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \
+     pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_su_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+     } pa_su_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_cntl_t f;
+} pa_su_debug_cntl_u;
+
+
+/*
+ * PA_SU_DEBUG_DATA struct
+ */
+
+#define PA_SU_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SU_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SU_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SU_DEBUG_DATA_MASK \
+     (PA_SU_DEBUG_DATA_DATA_MASK)
+
+#define PA_SU_DEBUG_DATA(data) \
+     ((data << PA_SU_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \
+     ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \
+     pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_data_t f;
+} pa_su_debug_data_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG00 struct
+ */
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000
+
+#define CLIPPER_DEBUG_REG00_MASK \
+     (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \
+     ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \
+      (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \
+      (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \
+      (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \
+      (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \
+      (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \
+      (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \
+      (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \
+      (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \
+      (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \
+      (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \
+      (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \
+      (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \
+      (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \
+      (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \
+      (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \
+      (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \
+      (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \
+      (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \
+      (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+     } clipper_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg00_t f;
+} clipper_debug_reg00_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG01 struct
+ */
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000
+
+#define CLIPPER_DEBUG_REG01_MASK \
+     (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \
+      CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \
+     ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \
+      (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \
+      (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \
+      (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \
+      (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \
+      (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \
+      (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+     } clipper_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg01_t f;
+} clipper_debug_reg01_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG02 struct
+ */
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+
+#define CLIPPER_DEBUG_REG02_MASK \
+     (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \
+      CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK)
+
+#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \
+     ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \
+      (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT))
+
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+     } clipper_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+     } clipper_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg02_t f;
+} clipper_debug_reg02_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG03 struct
+ */
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG03_MASK \
+     (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \
+     ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+     } clipper_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg03_t f;
+} clipper_debug_reg03_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG04 struct
+ */
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00
+
+#define CLIPPER_DEBUG_REG04_MASK \
+     (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \
+     ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+     } clipper_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg04_t f;
+} clipper_debug_reg04_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG05 struct
+ */
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000
+
+#define CLIPPER_DEBUG_REG05_MASK \
+     (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \
+     ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \
+      (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+     } clipper_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg05_t f;
+} clipper_debug_reg05_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG09 struct
+ */
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000
+#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000
+
+#define CLIPPER_DEBUG_REG09_MASK \
+     (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \
+      CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK)
+
+#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \
+     ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \
+      (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \
+      (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \
+      (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \
+      (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \
+      (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \
+      (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \
+      (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \
+      (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT))
+
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+     } clipper_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+     } clipper_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg09_t f;
+} clipper_debug_reg09_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG10 struct
+ */
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG10_MASK \
+     (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK)
+
+#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \
+     ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \
+      (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \
+      (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \
+      (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \
+      (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT))
+
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+     } clipper_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+     } clipper_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg10_t f;
+} clipper_debug_reg10_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG11 struct
+ */
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0
+
+#define CLIPPER_DEBUG_REG11_MASK \
+     (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \
+      CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \
+     ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+     } clipper_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg11_t f;
+} clipper_debug_reg11_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG12 struct
+ */
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define CLIPPER_DEBUG_REG12_MASK \
+     (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \
+      CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \
+     ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \
+      (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \
+      (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \
+      (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \
+      (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \
+      (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+     } clipper_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg12_t f;
+} clipper_debug_reg12_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG13 struct
+ */
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000
+#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000
+
+#define CLIPPER_DEBUG_REG13_MASK \
+     (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \
+     ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \
+      (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \
+      (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \
+      (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+     } clipper_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg13_t f;
+} clipper_debug_reg13_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG0 struct
+ */
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4
+#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3
+#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0
+#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380
+#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000
+
+#define SXIFCCG_DEBUG_REG0_MASK \
+     (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \
+      SXIFCCG_DEBUG_REG0_position_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG0_point_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK)
+
+#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \
+     ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \
+      (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \
+      (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \
+      (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \
+      (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \
+      (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \
+      (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \
+      (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT))
+
+#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg0_t f;
+} sxifccg_debug_reg0_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG1 struct
+ */
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4
+#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c
+#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000
+#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000
+#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000
+
+#define SXIFCCG_DEBUG_REG1_MASK \
+     (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \
+      SXIFCCG_DEBUG_REG1_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \
+      SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG1_aux_sel_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \
+      SXIFCCG_DEBUG_REG1_param_cache_base_MASK)
+
+#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \
+     ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \
+      (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \
+      (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \
+      (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \
+      (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \
+      (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \
+      (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \
+      (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT))
+
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg1_t f;
+} sxifccg_debug_reg1_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG2 struct
+ */
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002
+#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8
+#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000
+
+#define SXIFCCG_DEBUG_REG2_MASK \
+     (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_aux_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK)
+
+#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \
+     ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \
+      (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \
+      (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \
+      (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \
+      (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \
+      (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \
+      (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \
+      (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \
+      (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \
+      (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT))
+
+#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg2_t f;
+} sxifccg_debug_reg2_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG3 struct
+ */
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4
+#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8
+#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010
+#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00
+#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define SXIFCCG_DEBUG_REG3_MASK \
+     (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG3_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG3_current_state_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK)
+
+#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \
+     ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \
+      (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \
+      (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \
+      (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \
+      (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \
+      (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \
+      (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \
+      (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT))
+
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg3_t f;
+} sxifccg_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG0 struct
+ */
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5
+#define SETUP_DEBUG_REG0_pmode_state_SIZE 6
+#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1
+#define SETUP_DEBUG_REG0_geom_enable_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1
+#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1
+#define SETUP_DEBUG_REG0_geom_busy_SIZE 1
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0
+#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5
+#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11
+#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13
+#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14
+#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15
+#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16
+#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17
+
+#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f
+#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0
+#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800
+#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000
+#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000
+#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000
+#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000
+#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000
+
+#define SETUP_DEBUG_REG0_MASK \
+     (SETUP_DEBUG_REG0_su_cntl_state_MASK | \
+      SETUP_DEBUG_REG0_pmode_state_MASK | \
+      SETUP_DEBUG_REG0_ge_stallb_MASK | \
+      SETUP_DEBUG_REG0_geom_enable_MASK | \
+      SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \
+      SETUP_DEBUG_REG0_su_clip_rtr_MASK | \
+      SETUP_DEBUG_REG0_pfifo_busy_MASK | \
+      SETUP_DEBUG_REG0_su_cntl_busy_MASK | \
+      SETUP_DEBUG_REG0_geom_busy_MASK)
+
+#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \
+     ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \
+      (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \
+      (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \
+      (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \
+      (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \
+      (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \
+      (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \
+      (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \
+      (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT))
+
+#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int                                : 14;
+     } setup_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int                                : 14;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+     } setup_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg0_t f;
+} setup_debug_reg0_u;
+
+
+/*
+ * SETUP_DEBUG_REG1 struct
+ */
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG1_MASK \
+     (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \
+      SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \
+     ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \
+      (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int                                : 4;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+     } setup_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg1_t f;
+} setup_debug_reg1_u;
+
+
+/*
+ * SETUP_DEBUG_REG2 struct
+ */
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG2_MASK \
+     (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \
+      SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \
+     ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \
+      (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int                                : 4;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+     } setup_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg2_t f;
+} setup_debug_reg2_u;
+
+
+/*
+ * SETUP_DEBUG_REG3 struct
+ */
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG3_MASK \
+     (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \
+      SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \
+     ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \
+      (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int                                : 4;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+     } setup_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg3_t f;
+} setup_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG4 struct
+ */
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11
+#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1
+#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3
+#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3
+#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2
+#define SETUP_DEBUG_REG4_type_gated_SIZE 3
+#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_event_gated_SIZE 1
+#define SETUP_DEBUG_REG4_eop_gated_SIZE 1
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0
+#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11
+#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12
+#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13
+#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17
+#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21
+#define SETUP_DEBUG_REG4_type_gated_SHIFT 23
+#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27
+#define SETUP_DEBUG_REG4_event_gated_SHIFT 28
+#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800
+#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000
+#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000
+#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000
+#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000
+#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000
+#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000
+#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000
+#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000
+#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000
+#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000
+
+#define SETUP_DEBUG_REG4_MASK \
+     (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \
+      SETUP_DEBUG_REG4_null_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_backfacing_gated_MASK | \
+      SETUP_DEBUG_REG4_st_indx_gated_MASK | \
+      SETUP_DEBUG_REG4_clipped_gated_MASK | \
+      SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \
+      SETUP_DEBUG_REG4_xmajor_gated_MASK | \
+      SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \
+      SETUP_DEBUG_REG4_type_gated_MASK | \
+      SETUP_DEBUG_REG4_fpov_gated_MASK | \
+      SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_event_gated_MASK | \
+      SETUP_DEBUG_REG4_eop_gated_MASK)
+
+#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \
+     ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \
+      (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \
+      (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \
+      (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \
+      (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \
+      (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \
+      (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \
+      (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \
+      (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \
+      (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \
+      (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \
+      (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \
+      (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT))
+
+#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int                                : 2;
+     } setup_debug_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int                                : 2;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+     } setup_debug_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg4_t f;
+} setup_debug_reg4_u;
+
+
+/*
+ * SETUP_DEBUG_REG5 struct
+ */
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2
+#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22
+#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000
+#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000
+
+#define SETUP_DEBUG_REG5_MASK \
+     (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \
+      SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \
+      SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \
+      SETUP_DEBUG_REG5_event_id_gated_MASK)
+
+#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \
+     ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \
+      (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \
+      (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \
+      (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT))
+
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int                                : 3;
+     } setup_debug_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int                                : 3;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+     } setup_debug_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg5_t f;
+} setup_debug_reg5_u;
+
+
+/*
+ * PA_SC_DEBUG_CNTL struct
+ */
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SC_DEBUG_CNTL_MASK \
+     (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK)
+
+#define PA_SC_DEBUG_CNTL(sc_debug_indx) \
+     ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT))
+
+#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \
+     ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \
+     pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_sc_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+     } pa_sc_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_cntl_t f;
+} pa_sc_debug_cntl_u;
+
+
+/*
+ * PA_SC_DEBUG_DATA struct
+ */
+
+#define PA_SC_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SC_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SC_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SC_DEBUG_DATA_MASK \
+     (PA_SC_DEBUG_DATA_DATA_MASK)
+
+#define PA_SC_DEBUG_DATA(data) \
+     ((data << PA_SC_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \
+     ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \
+     pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_data_t f;
+} pa_sc_debug_data_u;
+
+
+/*
+ * SC_DEBUG_0 struct
+ */
+
+#define SC_DEBUG_0_pa_freeze_b1_SIZE   1
+#define SC_DEBUG_0_pa_sc_valid_SIZE    1
+#define SC_DEBUG_0_pa_sc_phase_SIZE    3
+#define SC_DEBUG_0_cntx_cnt_SIZE       7
+#define SC_DEBUG_0_decr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_incr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_trigger_SIZE        1
+
+#define SC_DEBUG_0_pa_freeze_b1_SHIFT  0
+#define SC_DEBUG_0_pa_sc_valid_SHIFT   1
+#define SC_DEBUG_0_pa_sc_phase_SHIFT   2
+#define SC_DEBUG_0_cntx_cnt_SHIFT      5
+#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12
+#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13
+#define SC_DEBUG_0_trigger_SHIFT       31
+
+#define SC_DEBUG_0_pa_freeze_b1_MASK   0x00000001
+#define SC_DEBUG_0_pa_sc_valid_MASK    0x00000002
+#define SC_DEBUG_0_pa_sc_phase_MASK    0x0000001c
+#define SC_DEBUG_0_cntx_cnt_MASK       0x00000fe0
+#define SC_DEBUG_0_decr_cntx_cnt_MASK  0x00001000
+#define SC_DEBUG_0_incr_cntx_cnt_MASK  0x00002000
+#define SC_DEBUG_0_trigger_MASK        0x80000000
+
+#define SC_DEBUG_0_MASK \
+     (SC_DEBUG_0_pa_freeze_b1_MASK | \
+      SC_DEBUG_0_pa_sc_valid_MASK | \
+      SC_DEBUG_0_pa_sc_phase_MASK | \
+      SC_DEBUG_0_cntx_cnt_MASK | \
+      SC_DEBUG_0_decr_cntx_cnt_MASK | \
+      SC_DEBUG_0_incr_cntx_cnt_MASK | \
+      SC_DEBUG_0_trigger_MASK)
+
+#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \
+     ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \
+      (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \
+      (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \
+      (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \
+      (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \
+      (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \
+      (trigger << SC_DEBUG_0_trigger_SHIFT))
+
+#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_trigger(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT)
+
+#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int                                : 17;
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+     } sc_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+          unsigned int                                : 17;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+     } sc_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_0_t f;
+} sc_debug_0_u;
+
+
+/*
+ * SC_DEBUG_1 struct
+ */
+
+#define SC_DEBUG_1_em_state_SIZE       3
+#define SC_DEBUG_1_em1_data_ready_SIZE 1
+#define SC_DEBUG_1_em2_data_ready_SIZE 1
+#define SC_DEBUG_1_move_em1_to_em2_SIZE 1
+#define SC_DEBUG_1_ef_data_ready_SIZE  1
+#define SC_DEBUG_1_ef_state_SIZE       2
+#define SC_DEBUG_1_pipe_valid_SIZE     1
+#define SC_DEBUG_1_trigger_SIZE        1
+
+#define SC_DEBUG_1_em_state_SHIFT      0
+#define SC_DEBUG_1_em1_data_ready_SHIFT 3
+#define SC_DEBUG_1_em2_data_ready_SHIFT 4
+#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5
+#define SC_DEBUG_1_ef_data_ready_SHIFT 6
+#define SC_DEBUG_1_ef_state_SHIFT      7
+#define SC_DEBUG_1_pipe_valid_SHIFT    9
+#define SC_DEBUG_1_trigger_SHIFT       31
+
+#define SC_DEBUG_1_em_state_MASK       0x00000007
+#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008
+#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010
+#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020
+#define SC_DEBUG_1_ef_data_ready_MASK  0x00000040
+#define SC_DEBUG_1_ef_state_MASK       0x00000180
+#define SC_DEBUG_1_pipe_valid_MASK     0x00000200
+#define SC_DEBUG_1_trigger_MASK        0x80000000
+
+#define SC_DEBUG_1_MASK \
+     (SC_DEBUG_1_em_state_MASK | \
+      SC_DEBUG_1_em1_data_ready_MASK | \
+      SC_DEBUG_1_em2_data_ready_MASK | \
+      SC_DEBUG_1_move_em1_to_em2_MASK | \
+      SC_DEBUG_1_ef_data_ready_MASK | \
+      SC_DEBUG_1_ef_state_MASK | \
+      SC_DEBUG_1_pipe_valid_MASK | \
+      SC_DEBUG_1_trigger_MASK)
+
+#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \
+     ((em_state << SC_DEBUG_1_em_state_SHIFT) | \
+      (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \
+      (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \
+      (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \
+      (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \
+      (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \
+      (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \
+      (trigger << SC_DEBUG_1_trigger_SHIFT))
+
+#define SC_DEBUG_1_GET_em_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_GET_trigger(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT)
+
+#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int                                : 21;
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+     } sc_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+          unsigned int                                : 21;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+     } sc_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_1_t f;
+} sc_debug_1_u;
+
+
+/*
+ * SC_DEBUG_2 struct
+ */
+
+#define SC_DEBUG_2_rc_rtr_dly_SIZE     1
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1
+#define SC_DEBUG_2_pipe_freeze_b_SIZE  1
+#define SC_DEBUG_2_prim_rts_SIZE       1
+#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1
+#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1
+#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1
+#define SC_DEBUG_2_stage0_rts_SIZE     1
+#define SC_DEBUG_2_phase_rts_dly_SIZE  1
+#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1
+#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1
+#define SC_DEBUG_2_event_id_s1_SIZE    5
+#define SC_DEBUG_2_event_s1_SIZE       1
+#define SC_DEBUG_2_trigger_SIZE        1
+
+#define SC_DEBUG_2_rc_rtr_dly_SHIFT    0
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1
+#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3
+#define SC_DEBUG_2_prim_rts_SHIFT      4
+#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5
+#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6
+#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7
+#define SC_DEBUG_2_stage0_rts_SHIFT    8
+#define SC_DEBUG_2_phase_rts_dly_SHIFT 9
+#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15
+#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16
+#define SC_DEBUG_2_event_id_s1_SHIFT   17
+#define SC_DEBUG_2_event_s1_SHIFT      22
+#define SC_DEBUG_2_trigger_SHIFT       31
+
+#define SC_DEBUG_2_rc_rtr_dly_MASK     0x00000001
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002
+#define SC_DEBUG_2_pipe_freeze_b_MASK  0x00000008
+#define SC_DEBUG_2_prim_rts_MASK       0x00000010
+#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020
+#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040
+#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080
+#define SC_DEBUG_2_stage0_rts_MASK     0x00000100
+#define SC_DEBUG_2_phase_rts_dly_MASK  0x00000200
+#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000
+#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000
+#define SC_DEBUG_2_event_id_s1_MASK    0x003e0000
+#define SC_DEBUG_2_event_s1_MASK       0x00400000
+#define SC_DEBUG_2_trigger_MASK        0x80000000
+
+#define SC_DEBUG_2_MASK \
+     (SC_DEBUG_2_rc_rtr_dly_MASK | \
+      SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \
+      SC_DEBUG_2_pipe_freeze_b_MASK | \
+      SC_DEBUG_2_prim_rts_MASK | \
+      SC_DEBUG_2_next_prim_rts_dly_MASK | \
+      SC_DEBUG_2_next_prim_rtr_dly_MASK | \
+      SC_DEBUG_2_pre_stage1_rts_d1_MASK | \
+      SC_DEBUG_2_stage0_rts_MASK | \
+      SC_DEBUG_2_phase_rts_dly_MASK | \
+      SC_DEBUG_2_end_of_prim_s1_dly_MASK | \
+      SC_DEBUG_2_pass_empty_prim_s1_MASK | \
+      SC_DEBUG_2_event_id_s1_MASK | \
+      SC_DEBUG_2_event_s1_MASK | \
+      SC_DEBUG_2_trigger_MASK)
+
+#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \
+     ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \
+      (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \
+      (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \
+      (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \
+      (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \
+      (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \
+      (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \
+      (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \
+      (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \
+      (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \
+      (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \
+      (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \
+      (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \
+      (trigger << SC_DEBUG_2_trigger_SHIFT))
+
+#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_GET_trigger(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT)
+
+#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int                                : 1;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int                                : 8;
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+     } sc_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+          unsigned int                                : 8;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int                                : 1;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+     } sc_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_2_t f;
+} sc_debug_2_u;
+
+
+/*
+ * SC_DEBUG_3 struct
+ */
+
+#define SC_DEBUG_3_x_curr_s1_SIZE      11
+#define SC_DEBUG_3_y_curr_s1_SIZE      11
+#define SC_DEBUG_3_trigger_SIZE        1
+
+#define SC_DEBUG_3_x_curr_s1_SHIFT     0
+#define SC_DEBUG_3_y_curr_s1_SHIFT     11
+#define SC_DEBUG_3_trigger_SHIFT       31
+
+#define SC_DEBUG_3_x_curr_s1_MASK      0x000007ff
+#define SC_DEBUG_3_y_curr_s1_MASK      0x003ff800
+#define SC_DEBUG_3_trigger_MASK        0x80000000
+
+#define SC_DEBUG_3_MASK \
+     (SC_DEBUG_3_x_curr_s1_MASK | \
+      SC_DEBUG_3_y_curr_s1_MASK | \
+      SC_DEBUG_3_trigger_MASK)
+
+#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \
+     ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \
+      (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \
+      (trigger << SC_DEBUG_3_trigger_SHIFT))
+
+#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_trigger(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT)
+
+#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int                                : 9;
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+     } sc_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+          unsigned int                                : 9;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+     } sc_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_3_t f;
+} sc_debug_3_u;
+
+
+/*
+ * SC_DEBUG_4 struct
+ */
+
+#define SC_DEBUG_4_y_end_s1_SIZE       14
+#define SC_DEBUG_4_y_start_s1_SIZE     14
+#define SC_DEBUG_4_y_dir_s1_SIZE       1
+#define SC_DEBUG_4_trigger_SIZE        1
+
+#define SC_DEBUG_4_y_end_s1_SHIFT      0
+#define SC_DEBUG_4_y_start_s1_SHIFT    14
+#define SC_DEBUG_4_y_dir_s1_SHIFT      28
+#define SC_DEBUG_4_trigger_SHIFT       31
+
+#define SC_DEBUG_4_y_end_s1_MASK       0x00003fff
+#define SC_DEBUG_4_y_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_4_y_dir_s1_MASK       0x10000000
+#define SC_DEBUG_4_trigger_MASK        0x80000000
+
+#define SC_DEBUG_4_MASK \
+     (SC_DEBUG_4_y_end_s1_MASK | \
+      SC_DEBUG_4_y_start_s1_MASK | \
+      SC_DEBUG_4_y_dir_s1_MASK | \
+      SC_DEBUG_4_trigger_MASK)
+
+#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \
+     ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \
+      (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \
+      (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_4_trigger_SHIFT))
+
+#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_GET_trigger(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT)
+
+#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+     } sc_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+     } sc_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_4_t f;
+} sc_debug_4_u;
+
+
+/*
+ * SC_DEBUG_5 struct
+ */
+
+#define SC_DEBUG_5_x_end_s1_SIZE       14
+#define SC_DEBUG_5_x_start_s1_SIZE     14
+#define SC_DEBUG_5_x_dir_s1_SIZE       1
+#define SC_DEBUG_5_trigger_SIZE        1
+
+#define SC_DEBUG_5_x_end_s1_SHIFT      0
+#define SC_DEBUG_5_x_start_s1_SHIFT    14
+#define SC_DEBUG_5_x_dir_s1_SHIFT      28
+#define SC_DEBUG_5_trigger_SHIFT       31
+
+#define SC_DEBUG_5_x_end_s1_MASK       0x00003fff
+#define SC_DEBUG_5_x_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_5_x_dir_s1_MASK       0x10000000
+#define SC_DEBUG_5_trigger_MASK        0x80000000
+
+#define SC_DEBUG_5_MASK \
+     (SC_DEBUG_5_x_end_s1_MASK | \
+      SC_DEBUG_5_x_start_s1_MASK | \
+      SC_DEBUG_5_x_dir_s1_MASK | \
+      SC_DEBUG_5_trigger_MASK)
+
+#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \
+     ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \
+      (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \
+      (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_5_trigger_SHIFT))
+
+#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_GET_trigger(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT)
+
+#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+     } sc_debug_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+     } sc_debug_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_5_t f;
+} sc_debug_5_u;
+
+
+/*
+ * SC_DEBUG_6 struct
+ */
+
+#define SC_DEBUG_6_z_ff_empty_SIZE     1
+#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1
+#define SC_DEBUG_6_xy_ff_empty_SIZE    1
+#define SC_DEBUG_6_event_flag_SIZE     1
+#define SC_DEBUG_6_z_mask_needed_SIZE  1
+#define SC_DEBUG_6_state_SIZE          3
+#define SC_DEBUG_6_state_delayed_SIZE  3
+#define SC_DEBUG_6_data_valid_SIZE     1
+#define SC_DEBUG_6_data_valid_d_SIZE   1
+#define SC_DEBUG_6_tilex_delayed_SIZE  9
+#define SC_DEBUG_6_tiley_delayed_SIZE  9
+#define SC_DEBUG_6_trigger_SIZE        1
+
+#define SC_DEBUG_6_z_ff_empty_SHIFT    0
+#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1
+#define SC_DEBUG_6_xy_ff_empty_SHIFT   2
+#define SC_DEBUG_6_event_flag_SHIFT    3
+#define SC_DEBUG_6_z_mask_needed_SHIFT 4
+#define SC_DEBUG_6_state_SHIFT         5
+#define SC_DEBUG_6_state_delayed_SHIFT 8
+#define SC_DEBUG_6_data_valid_SHIFT    11
+#define SC_DEBUG_6_data_valid_d_SHIFT  12
+#define SC_DEBUG_6_tilex_delayed_SHIFT 13
+#define SC_DEBUG_6_tiley_delayed_SHIFT 22
+#define SC_DEBUG_6_trigger_SHIFT       31
+
+#define SC_DEBUG_6_z_ff_empty_MASK     0x00000001
+#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002
+#define SC_DEBUG_6_xy_ff_empty_MASK    0x00000004
+#define SC_DEBUG_6_event_flag_MASK     0x00000008
+#define SC_DEBUG_6_z_mask_needed_MASK  0x00000010
+#define SC_DEBUG_6_state_MASK          0x000000e0
+#define SC_DEBUG_6_state_delayed_MASK  0x00000700
+#define SC_DEBUG_6_data_valid_MASK     0x00000800
+#define SC_DEBUG_6_data_valid_d_MASK   0x00001000
+#define SC_DEBUG_6_tilex_delayed_MASK  0x003fe000
+#define SC_DEBUG_6_tiley_delayed_MASK  0x7fc00000
+#define SC_DEBUG_6_trigger_MASK        0x80000000
+
+#define SC_DEBUG_6_MASK \
+     (SC_DEBUG_6_z_ff_empty_MASK | \
+      SC_DEBUG_6_qmcntl_ff_empty_MASK | \
+      SC_DEBUG_6_xy_ff_empty_MASK | \
+      SC_DEBUG_6_event_flag_MASK | \
+      SC_DEBUG_6_z_mask_needed_MASK | \
+      SC_DEBUG_6_state_MASK | \
+      SC_DEBUG_6_state_delayed_MASK | \
+      SC_DEBUG_6_data_valid_MASK | \
+      SC_DEBUG_6_data_valid_d_MASK | \
+      SC_DEBUG_6_tilex_delayed_MASK | \
+      SC_DEBUG_6_tiley_delayed_MASK | \
+      SC_DEBUG_6_trigger_MASK)
+
+#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \
+     ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \
+      (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \
+      (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \
+      (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \
+      (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \
+      (state << SC_DEBUG_6_state_SHIFT) | \
+      (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \
+      (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \
+      (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \
+      (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \
+      (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \
+      (trigger << SC_DEBUG_6_trigger_SHIFT))
+
+#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_GET_state(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_GET_trigger(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT)
+
+#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+     } sc_debug_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+     } sc_debug_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_6_t f;
+} sc_debug_6_u;
+
+
+/*
+ * SC_DEBUG_7 struct
+ */
+
+#define SC_DEBUG_7_event_flag_SIZE     1
+#define SC_DEBUG_7_deallocate_SIZE     3
+#define SC_DEBUG_7_fpos_SIZE           1
+#define SC_DEBUG_7_sr_prim_we_SIZE     1
+#define SC_DEBUG_7_last_tile_SIZE      1
+#define SC_DEBUG_7_tile_ff_we_SIZE     1
+#define SC_DEBUG_7_qs_data_valid_SIZE  1
+#define SC_DEBUG_7_qs_q0_y_SIZE        2
+#define SC_DEBUG_7_qs_q0_x_SIZE        2
+#define SC_DEBUG_7_qs_q0_valid_SIZE    1
+#define SC_DEBUG_7_prim_ff_we_SIZE     1
+#define SC_DEBUG_7_tile_ff_re_SIZE     1
+#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_7_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_7_new_prim_SIZE       1
+#define SC_DEBUG_7_load_new_tile_data_SIZE 1
+#define SC_DEBUG_7_state_SIZE          2
+#define SC_DEBUG_7_fifos_ready_SIZE    1
+#define SC_DEBUG_7_trigger_SIZE        1
+
+#define SC_DEBUG_7_event_flag_SHIFT    0
+#define SC_DEBUG_7_deallocate_SHIFT    1
+#define SC_DEBUG_7_fpos_SHIFT          4
+#define SC_DEBUG_7_sr_prim_we_SHIFT    5
+#define SC_DEBUG_7_last_tile_SHIFT     6
+#define SC_DEBUG_7_tile_ff_we_SHIFT    7
+#define SC_DEBUG_7_qs_data_valid_SHIFT 8
+#define SC_DEBUG_7_qs_q0_y_SHIFT       9
+#define SC_DEBUG_7_qs_q0_x_SHIFT       11
+#define SC_DEBUG_7_qs_q0_valid_SHIFT   13
+#define SC_DEBUG_7_prim_ff_we_SHIFT    14
+#define SC_DEBUG_7_tile_ff_re_SHIFT    15
+#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16
+#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17
+#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18
+#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19
+#define SC_DEBUG_7_new_prim_SHIFT      20
+#define SC_DEBUG_7_load_new_tile_data_SHIFT 21
+#define SC_DEBUG_7_state_SHIFT         22
+#define SC_DEBUG_7_fifos_ready_SHIFT   24
+#define SC_DEBUG_7_trigger_SHIFT       31
+
+#define SC_DEBUG_7_event_flag_MASK     0x00000001
+#define SC_DEBUG_7_deallocate_MASK     0x0000000e
+#define SC_DEBUG_7_fpos_MASK           0x00000010
+#define SC_DEBUG_7_sr_prim_we_MASK     0x00000020
+#define SC_DEBUG_7_last_tile_MASK      0x00000040
+#define SC_DEBUG_7_tile_ff_we_MASK     0x00000080
+#define SC_DEBUG_7_qs_data_valid_MASK  0x00000100
+#define SC_DEBUG_7_qs_q0_y_MASK        0x00000600
+#define SC_DEBUG_7_qs_q0_x_MASK        0x00001800
+#define SC_DEBUG_7_qs_q0_valid_MASK    0x00002000
+#define SC_DEBUG_7_prim_ff_we_MASK     0x00004000
+#define SC_DEBUG_7_tile_ff_re_MASK     0x00008000
+#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000
+#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000
+#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000
+#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000
+#define SC_DEBUG_7_new_prim_MASK       0x00100000
+#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000
+#define SC_DEBUG_7_state_MASK          0x00c00000
+#define SC_DEBUG_7_fifos_ready_MASK    0x01000000
+#define SC_DEBUG_7_trigger_MASK        0x80000000
+
+#define SC_DEBUG_7_MASK \
+     (SC_DEBUG_7_event_flag_MASK | \
+      SC_DEBUG_7_deallocate_MASK | \
+      SC_DEBUG_7_fpos_MASK | \
+      SC_DEBUG_7_sr_prim_we_MASK | \
+      SC_DEBUG_7_last_tile_MASK | \
+      SC_DEBUG_7_tile_ff_we_MASK | \
+      SC_DEBUG_7_qs_data_valid_MASK | \
+      SC_DEBUG_7_qs_q0_y_MASK | \
+      SC_DEBUG_7_qs_q0_x_MASK | \
+      SC_DEBUG_7_qs_q0_valid_MASK | \
+      SC_DEBUG_7_prim_ff_we_MASK | \
+      SC_DEBUG_7_tile_ff_re_MASK | \
+      SC_DEBUG_7_fw_prim_data_valid_MASK | \
+      SC_DEBUG_7_last_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_prim_MASK | \
+      SC_DEBUG_7_new_prim_MASK | \
+      SC_DEBUG_7_load_new_tile_data_MASK | \
+      SC_DEBUG_7_state_MASK | \
+      SC_DEBUG_7_fifos_ready_MASK | \
+      SC_DEBUG_7_trigger_MASK)
+
+#define SC_DEBUG_7(event_flag, deallocate, fpos, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \
+     ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \
+      (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \
+      (fpos << SC_DEBUG_7_fpos_SHIFT) | \
+      (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \
+      (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \
+      (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \
+      (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \
+      (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \
+      (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \
+      (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \
+      (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \
+      (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \
+      (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \
+      (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \
+      (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \
+      (state << SC_DEBUG_7_state_SHIFT) | \
+      (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \
+      (trigger << SC_DEBUG_7_trigger_SHIFT))
+
+#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_GET_fpos(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fpos_MASK) >> SC_DEBUG_7_fpos_SHIFT)
+#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_GET_state(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_GET_trigger(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT)
+
+#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_SET_fpos(sc_debug_7_reg, fpos) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fpos_MASK) | (fpos << SC_DEBUG_7_fpos_SHIFT)
+#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int fpos                           : SC_DEBUG_7_fpos_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int                                : 6;
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+     } sc_debug_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+          unsigned int                                : 6;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int fpos                           : SC_DEBUG_7_fpos_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+     } sc_debug_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_7_t f;
+} sc_debug_7_u;
+
+
+/*
+ * SC_DEBUG_8 struct
+ */
+
+#define SC_DEBUG_8_sample_last_SIZE    1
+#define SC_DEBUG_8_sample_mask_SIZE    4
+#define SC_DEBUG_8_sample_y_SIZE       2
+#define SC_DEBUG_8_sample_x_SIZE       2
+#define SC_DEBUG_8_sample_send_SIZE    1
+#define SC_DEBUG_8_next_cycle_SIZE     2
+#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1
+#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1
+#define SC_DEBUG_8_num_samples_SIZE    2
+#define SC_DEBUG_8_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_8_last_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_sample_we_SIZE      1
+#define SC_DEBUG_8_fpos_SIZE           1
+#define SC_DEBUG_8_event_id_SIZE       5
+#define SC_DEBUG_8_event_flag_SIZE     1
+#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_8_trigger_SIZE        1
+
+#define SC_DEBUG_8_sample_last_SHIFT   0
+#define SC_DEBUG_8_sample_mask_SHIFT   1
+#define SC_DEBUG_8_sample_y_SHIFT      5
+#define SC_DEBUG_8_sample_x_SHIFT      7
+#define SC_DEBUG_8_sample_send_SHIFT   9
+#define SC_DEBUG_8_next_cycle_SHIFT    10
+#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12
+#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13
+#define SC_DEBUG_8_num_samples_SHIFT   14
+#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16
+#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17
+#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18
+#define SC_DEBUG_8_sample_we_SHIFT     19
+#define SC_DEBUG_8_fpos_SHIFT          20
+#define SC_DEBUG_8_event_id_SHIFT      21
+#define SC_DEBUG_8_event_flag_SHIFT    26
+#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27
+#define SC_DEBUG_8_trigger_SHIFT       31
+
+#define SC_DEBUG_8_sample_last_MASK    0x00000001
+#define SC_DEBUG_8_sample_mask_MASK    0x0000001e
+#define SC_DEBUG_8_sample_y_MASK       0x00000060
+#define SC_DEBUG_8_sample_x_MASK       0x00000180
+#define SC_DEBUG_8_sample_send_MASK    0x00000200
+#define SC_DEBUG_8_next_cycle_MASK     0x00000c00
+#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000
+#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000
+#define SC_DEBUG_8_num_samples_MASK    0x0000c000
+#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000
+#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000
+#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000
+#define SC_DEBUG_8_sample_we_MASK      0x00080000
+#define SC_DEBUG_8_fpos_MASK           0x00100000
+#define SC_DEBUG_8_event_id_MASK       0x03e00000
+#define SC_DEBUG_8_event_flag_MASK     0x04000000
+#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000
+#define SC_DEBUG_8_trigger_MASK        0x80000000
+
+#define SC_DEBUG_8_MASK \
+     (SC_DEBUG_8_sample_last_MASK | \
+      SC_DEBUG_8_sample_mask_MASK | \
+      SC_DEBUG_8_sample_y_MASK | \
+      SC_DEBUG_8_sample_x_MASK | \
+      SC_DEBUG_8_sample_send_MASK | \
+      SC_DEBUG_8_next_cycle_MASK | \
+      SC_DEBUG_8_ez_sample_ff_full_MASK | \
+      SC_DEBUG_8_rb_sc_samp_rtr_MASK | \
+      SC_DEBUG_8_num_samples_MASK | \
+      SC_DEBUG_8_last_quad_of_tile_MASK | \
+      SC_DEBUG_8_last_quad_of_prim_MASK | \
+      SC_DEBUG_8_first_quad_of_prim_MASK | \
+      SC_DEBUG_8_sample_we_MASK | \
+      SC_DEBUG_8_fpos_MASK | \
+      SC_DEBUG_8_event_id_MASK | \
+      SC_DEBUG_8_event_flag_MASK | \
+      SC_DEBUG_8_fw_prim_data_valid_MASK | \
+      SC_DEBUG_8_trigger_MASK)
+
+#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fpos, event_id, event_flag, fw_prim_data_valid, trigger) \
+     ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \
+      (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \
+      (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \
+      (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \
+      (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \
+      (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \
+      (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \
+      (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \
+      (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \
+      (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \
+      (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \
+      (fpos << SC_DEBUG_8_fpos_SHIFT) | \
+      (event_id << SC_DEBUG_8_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \
+      (trigger << SC_DEBUG_8_trigger_SHIFT))
+
+#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_GET_fpos(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fpos_MASK) >> SC_DEBUG_8_fpos_SHIFT)
+#define SC_DEBUG_8_GET_event_id(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_GET_trigger(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT)
+
+#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_SET_fpos(sc_debug_8_reg, fpos) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fpos_MASK) | (fpos << SC_DEBUG_8_fpos_SHIFT)
+#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int fpos                           : SC_DEBUG_8_fpos_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int                                : 3;
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+     } sc_debug_8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int fpos                           : SC_DEBUG_8_fpos_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+     } sc_debug_8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_8_t f;
+} sc_debug_8_u;
+
+
+/*
+ * SC_DEBUG_9 struct
+ */
+
+#define SC_DEBUG_9_rb_sc_send_SIZE     1
+#define SC_DEBUG_9_rb_sc_ez_mask_SIZE  4
+#define SC_DEBUG_9_fifo_data_ready_SIZE 1
+#define SC_DEBUG_9_early_z_enable_SIZE 1
+#define SC_DEBUG_9_mask_state_SIZE     2
+#define SC_DEBUG_9_next_ez_mask_SIZE   16
+#define SC_DEBUG_9_mask_ready_SIZE     1
+#define SC_DEBUG_9_drop_sample_SIZE    1
+#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_9_trigger_SIZE        1
+
+#define SC_DEBUG_9_rb_sc_send_SHIFT    0
+#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1
+#define SC_DEBUG_9_fifo_data_ready_SHIFT 5
+#define SC_DEBUG_9_early_z_enable_SHIFT 6
+#define SC_DEBUG_9_mask_state_SHIFT    7
+#define SC_DEBUG_9_next_ez_mask_SHIFT  9
+#define SC_DEBUG_9_mask_ready_SHIFT    25
+#define SC_DEBUG_9_drop_sample_SHIFT   26
+#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30
+#define SC_DEBUG_9_trigger_SHIFT       31
+
+#define SC_DEBUG_9_rb_sc_send_MASK     0x00000001
+#define SC_DEBUG_9_rb_sc_ez_mask_MASK  0x0000001e
+#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020
+#define SC_DEBUG_9_early_z_enable_MASK 0x00000040
+#define SC_DEBUG_9_mask_state_MASK     0x00000180
+#define SC_DEBUG_9_next_ez_mask_MASK   0x01fffe00
+#define SC_DEBUG_9_mask_ready_MASK     0x02000000
+#define SC_DEBUG_9_drop_sample_MASK    0x04000000
+#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000
+#define SC_DEBUG_9_trigger_MASK        0x80000000
+
+#define SC_DEBUG_9_MASK \
+     (SC_DEBUG_9_rb_sc_send_MASK | \
+      SC_DEBUG_9_rb_sc_ez_mask_MASK | \
+      SC_DEBUG_9_fifo_data_ready_MASK | \
+      SC_DEBUG_9_early_z_enable_MASK | \
+      SC_DEBUG_9_mask_state_MASK | \
+      SC_DEBUG_9_next_ez_mask_MASK | \
+      SC_DEBUG_9_mask_ready_MASK | \
+      SC_DEBUG_9_drop_sample_MASK | \
+      SC_DEBUG_9_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_9_trigger_MASK)
+
+#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \
+     ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \
+      (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \
+      (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \
+      (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \
+      (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \
+      (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \
+      (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \
+      (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \
+      (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \
+      (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \
+      (trigger << SC_DEBUG_9_trigger_SHIFT))
+
+#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_GET_trigger(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT)
+
+#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+     } sc_debug_9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+     } sc_debug_9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_9_t f;
+} sc_debug_9_u;
+
+
+/*
+ * SC_DEBUG_10 struct
+ */
+
+#define SC_DEBUG_10_combined_sample_mask_SIZE 16
+#define SC_DEBUG_10_trigger_SIZE       1
+
+#define SC_DEBUG_10_combined_sample_mask_SHIFT 0
+#define SC_DEBUG_10_trigger_SHIFT      31
+
+#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff
+#define SC_DEBUG_10_trigger_MASK       0x80000000
+
+#define SC_DEBUG_10_MASK \
+     (SC_DEBUG_10_combined_sample_mask_MASK | \
+      SC_DEBUG_10_trigger_MASK)
+
+#define SC_DEBUG_10(combined_sample_mask, trigger) \
+     ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \
+      (trigger << SC_DEBUG_10_trigger_SHIFT))
+
+#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_GET_trigger(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT)
+
+#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+          unsigned int                                : 15;
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+     } sc_debug_10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+          unsigned int                                : 15;
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+     } sc_debug_10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_10_t f;
+} sc_debug_10_u;
+
+
+/*
+ * SC_DEBUG_11 struct
+ */
+
+#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_11_iterator_input_fz_SIZE 1
+#define SC_DEBUG_11_packer_send_quads_SIZE 1
+#define SC_DEBUG_11_packer_send_cmd_SIZE 1
+#define SC_DEBUG_11_packer_send_event_SIZE 1
+#define SC_DEBUG_11_next_state_SIZE    3
+#define SC_DEBUG_11_state_SIZE         3
+#define SC_DEBUG_11_stall_SIZE         1
+#define SC_DEBUG_11_trigger_SIZE       1
+
+#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1
+#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3
+#define SC_DEBUG_11_iterator_input_fz_SHIFT 4
+#define SC_DEBUG_11_packer_send_quads_SHIFT 5
+#define SC_DEBUG_11_packer_send_cmd_SHIFT 6
+#define SC_DEBUG_11_packer_send_event_SHIFT 7
+#define SC_DEBUG_11_next_state_SHIFT   8
+#define SC_DEBUG_11_state_SHIFT        11
+#define SC_DEBUG_11_stall_SHIFT        14
+#define SC_DEBUG_11_trigger_SHIFT      31
+
+#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002
+#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008
+#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010
+#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020
+#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040
+#define SC_DEBUG_11_packer_send_event_MASK 0x00000080
+#define SC_DEBUG_11_next_state_MASK    0x00000700
+#define SC_DEBUG_11_state_MASK         0x00003800
+#define SC_DEBUG_11_stall_MASK         0x00004000
+#define SC_DEBUG_11_trigger_MASK       0x80000000
+
+#define SC_DEBUG_11_MASK \
+     (SC_DEBUG_11_ez_sample_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_11_ez_prim_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_11_iterator_input_fz_MASK | \
+      SC_DEBUG_11_packer_send_quads_MASK | \
+      SC_DEBUG_11_packer_send_cmd_MASK | \
+      SC_DEBUG_11_packer_send_event_MASK | \
+      SC_DEBUG_11_next_state_MASK | \
+      SC_DEBUG_11_state_MASK | \
+      SC_DEBUG_11_stall_MASK | \
+      SC_DEBUG_11_trigger_MASK)
+
+#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \
+     ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \
+      (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \
+      (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \
+      (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \
+      (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \
+      (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \
+      (next_state << SC_DEBUG_11_next_state_SHIFT) | \
+      (state << SC_DEBUG_11_state_SHIFT) | \
+      (stall << SC_DEBUG_11_stall_SHIFT) | \
+      (trigger << SC_DEBUG_11_trigger_SHIFT))
+
+#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_GET_next_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_GET_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_GET_stall(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_GET_trigger(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT)
+
+#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int                                : 16;
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+     } sc_debug_11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+          unsigned int                                : 16;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+     } sc_debug_11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_11_t f;
+} sc_debug_11_u;
+
+
+/*
+ * SC_DEBUG_12 struct
+ */
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1
+#define SC_DEBUG_12_event_id_SIZE      5
+#define SC_DEBUG_12_event_flag_SIZE    1
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_full_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1
+#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1
+#define SC_DEBUG_12_iter_qdhit0_SIZE   1
+#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1
+#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1
+#define SC_DEBUG_12_iter_phase_out_SIZE 2
+#define SC_DEBUG_12_iter_phase_reg_SIZE 2
+#define SC_DEBUG_12_iterator_SP_valid_SIZE 1
+#define SC_DEBUG_12_eopv_reg_SIZE      1
+#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1
+#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1
+#define SC_DEBUG_12_trigger_SIZE       1
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0
+#define SC_DEBUG_12_event_id_SHIFT     1
+#define SC_DEBUG_12_event_flag_SHIFT   6
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7
+#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8
+#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9
+#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11
+#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12
+#define SC_DEBUG_12_iter_qdhit0_SHIFT  13
+#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14
+#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15
+#define SC_DEBUG_12_iter_phase_out_SHIFT 16
+#define SC_DEBUG_12_iter_phase_reg_SHIFT 18
+#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20
+#define SC_DEBUG_12_eopv_reg_SHIFT     21
+#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22
+#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23
+#define SC_DEBUG_12_trigger_SHIFT      31
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001
+#define SC_DEBUG_12_event_id_MASK      0x0000003e
+#define SC_DEBUG_12_event_flag_MASK    0x00000040
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080
+#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100
+#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200
+#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400
+#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800
+#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000
+#define SC_DEBUG_12_iter_qdhit0_MASK   0x00002000
+#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000
+#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000
+#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000
+#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000
+#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000
+#define SC_DEBUG_12_eopv_reg_MASK      0x00200000
+#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000
+#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000
+#define SC_DEBUG_12_trigger_MASK       0x80000000
+
+#define SC_DEBUG_12_MASK \
+     (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \
+      SC_DEBUG_12_event_id_MASK | \
+      SC_DEBUG_12_event_flag_MASK | \
+      SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \
+      SC_DEBUG_12_itercmdfifo_full_MASK | \
+      SC_DEBUG_12_itercmdfifo_empty_MASK | \
+      SC_DEBUG_12_iter_ds_one_clk_command_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_vector_MASK | \
+      SC_DEBUG_12_iter_qdhit0_MASK | \
+      SC_DEBUG_12_bc_use_centers_reg_MASK | \
+      SC_DEBUG_12_bc_output_xy_reg_MASK | \
+      SC_DEBUG_12_iter_phase_out_MASK | \
+      SC_DEBUG_12_iter_phase_reg_MASK | \
+      SC_DEBUG_12_iterator_SP_valid_MASK | \
+      SC_DEBUG_12_eopv_reg_MASK | \
+      SC_DEBUG_12_one_clk_cmd_reg_MASK | \
+      SC_DEBUG_12_iter_dx_end_of_prim_MASK | \
+      SC_DEBUG_12_trigger_MASK)
+
+#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \
+     ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \
+      (event_id << SC_DEBUG_12_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \
+      (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \
+      (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \
+      (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \
+      (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \
+      (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \
+      (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \
+      (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \
+      (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \
+      (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \
+      (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \
+      (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \
+      (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \
+      (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \
+      (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \
+      (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \
+      (trigger << SC_DEBUG_12_trigger_SHIFT))
+
+#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_GET_event_id(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_GET_trigger(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT)
+
+#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int                                : 7;
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+     } sc_debug_12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+          unsigned int                                : 7;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+     } sc_debug_12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_12_t f;
+} sc_debug_12_u;
+
+
+#endif
+
+
+#if !defined (_VGT_FIDDLE_H)
+#define _VGT_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  vgt_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+/*
+ * VGT_OUT_PRIM_TYPE enum
+ */
+
+#define VGT_OUT_POINT                  0x00000000
+#define VGT_OUT_LINE                   0x00000001
+#define VGT_OUT_TRI                    0x00000002
+#define VGT_OUT_RECT_V0                0x00000003
+#define VGT_OUT_RECT_V1                0x00000004
+#define VGT_OUT_RECT_V2                0x00000005
+#define VGT_OUT_RECT_V3                0x00000006
+#define VGT_OUT_RESERVED               0x00000007
+#define VGT_TE_QUAD                    0x00000008
+#define VGT_TE_PRIM_INDEX_LINE         0x00000009
+#define VGT_TE_PRIM_INDEX_TRI          0x0000000a
+#define VGT_TE_PRIM_INDEX_QUAD         0x0000000b
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * GFX_COPY_STATE struct
+ */
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0
+
+#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+
+#define GFX_COPY_STATE_MASK \
+     (GFX_COPY_STATE_SRC_STATE_ID_MASK)
+
+#define GFX_COPY_STATE(src_state_id) \
+     ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT))
+
+#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \
+     ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \
+     gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 31;
+     } gfx_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int                                : 31;
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+     } gfx_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gfx_copy_state_t f;
+} gfx_copy_state_u;
+
+
+/*
+ * VGT_DRAW_INITIATOR struct
+ */
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1
+#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11
+#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800
+#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000
+#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000
+
+#define VGT_DRAW_INITIATOR_MASK \
+     (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \
+      VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \
+      VGT_DRAW_INITIATOR_NOT_EOP_MASK | \
+      VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \
+      VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_NUM_INDICES_MASK)
+
+#define VGT_DRAW_INITIATOR(prim_type, source_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \
+     ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \
+      (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \
+      (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \
+      (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \
+      (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \
+      (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \
+      (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \
+      (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT))
+
+#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int                                : 3;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+     } vgt_draw_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+     } vgt_draw_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_draw_initiator_t f;
+} vgt_draw_initiator_u;
+
+
+/*
+ * VGT_EVENT_INITIATOR struct
+ */
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f
+
+#define VGT_EVENT_INITIATOR_MASK \
+     (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK)
+
+#define VGT_EVENT_INITIATOR(event_type) \
+     ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT))
+
+#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \
+     ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \
+     vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+          unsigned int                                : 26;
+     } vgt_event_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int                                : 26;
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+     } vgt_event_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_event_initiator_t f;
+} vgt_event_initiator_u;
+
+
+/*
+ * VGT_DMA_BASE struct
+ */
+
+#define VGT_DMA_BASE_BASE_ADDR_SIZE    32
+
+#define VGT_DMA_BASE_BASE_ADDR_SHIFT   0
+
+#define VGT_DMA_BASE_BASE_ADDR_MASK    0xffffffff
+
+#define VGT_DMA_BASE_MASK \
+     (VGT_DMA_BASE_BASE_ADDR_MASK)
+
+#define VGT_DMA_BASE(base_addr) \
+     ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT))
+
+#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \
+     ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \
+     vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_base_t f;
+} vgt_dma_base_u;
+
+
+/*
+ * VGT_DMA_SIZE struct
+ */
+
+#define VGT_DMA_SIZE_NUM_WORDS_SIZE    24
+#define VGT_DMA_SIZE_SWAP_MODE_SIZE    2
+
+#define VGT_DMA_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_DMA_SIZE_SWAP_MODE_SHIFT   30
+
+#define VGT_DMA_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_DMA_SIZE_SWAP_MODE_MASK    0xc0000000
+
+#define VGT_DMA_SIZE_MASK \
+     (VGT_DMA_SIZE_NUM_WORDS_MASK | \
+      VGT_DMA_SIZE_SWAP_MODE_MASK)
+
+#define VGT_DMA_SIZE(num_words, swap_mode) \
+     ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \
+      (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT))
+
+#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+     } vgt_dma_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+     } vgt_dma_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_size_t f;
+} vgt_dma_size_u;
+
+
+/*
+ * VGT_BIN_BASE struct
+ */
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff
+
+#define VGT_BIN_BASE_MASK \
+     (VGT_BIN_BASE_BIN_BASE_ADDR_MASK)
+
+#define VGT_BIN_BASE(bin_base_addr) \
+     ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT))
+
+#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \
+     ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \
+     vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_base_t f;
+} vgt_bin_base_u;
+
+
+/*
+ * VGT_BIN_SIZE struct
+ */
+
+#define VGT_BIN_SIZE_NUM_WORDS_SIZE    24
+
+#define VGT_BIN_SIZE_NUM_WORDS_SHIFT   0
+
+#define VGT_BIN_SIZE_NUM_WORDS_MASK    0x00ffffff
+
+#define VGT_BIN_SIZE_MASK \
+     (VGT_BIN_SIZE_NUM_WORDS_MASK)
+
+#define VGT_BIN_SIZE(num_words) \
+     ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT))
+
+#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+
+#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 8;
+     } vgt_bin_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int                                : 8;
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+     } vgt_bin_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_size_t f;
+} vgt_bin_size_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MIN struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MIN_MASK \
+     (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_min_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+     } vgt_current_bin_id_min_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_min_t f;
+} vgt_current_bin_id_min_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MAX struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MAX_MASK \
+     (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_max_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+     } vgt_current_bin_id_max_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_max_t f;
+} vgt_current_bin_id_max_u;
+
+
+/*
+ * VGT_IMMED_DATA struct
+ */
+
+#define VGT_IMMED_DATA_DATA_SIZE       32
+
+#define VGT_IMMED_DATA_DATA_SHIFT      0
+
+#define VGT_IMMED_DATA_DATA_MASK       0xffffffff
+
+#define VGT_IMMED_DATA_MASK \
+     (VGT_IMMED_DATA_DATA_MASK)
+
+#define VGT_IMMED_DATA(data) \
+     ((data << VGT_IMMED_DATA_DATA_SHIFT))
+
+#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \
+     ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT)
+
+#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \
+     vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_immed_data_t f;
+} vgt_immed_data_u;
+
+
+/*
+ * VGT_MAX_VTX_INDX struct
+ */
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff
+
+#define VGT_MAX_VTX_INDX_MASK \
+     (VGT_MAX_VTX_INDX_MAX_INDX_MASK)
+
+#define VGT_MAX_VTX_INDX(max_indx) \
+     ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT))
+
+#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \
+     ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \
+     vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_max_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+     } vgt_max_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_max_vtx_indx_t f;
+} vgt_max_vtx_indx_u;
+
+
+/*
+ * VGT_MIN_VTX_INDX struct
+ */
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff
+
+#define VGT_MIN_VTX_INDX_MASK \
+     (VGT_MIN_VTX_INDX_MIN_INDX_MASK)
+
+#define VGT_MIN_VTX_INDX(min_indx) \
+     ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT))
+
+#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \
+     ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \
+     vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_min_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+     } vgt_min_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_min_vtx_indx_t f;
+} vgt_min_vtx_indx_u;
+
+
+/*
+ * VGT_INDX_OFFSET struct
+ */
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff
+
+#define VGT_INDX_OFFSET_MASK \
+     (VGT_INDX_OFFSET_INDX_OFFSET_MASK)
+
+#define VGT_INDX_OFFSET(indx_offset) \
+     ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT))
+
+#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \
+     ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \
+     vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+          unsigned int                                : 8;
+     } vgt_indx_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int                                : 8;
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+     } vgt_indx_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_indx_offset_t f;
+} vgt_indx_offset_u;
+
+
+/*
+ * VGT_VERTEX_REUSE_BLOCK_CNTL struct
+ */
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \
+     (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \
+     ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT))
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \
+     ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \
+     vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+          unsigned int                                : 29;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int                                : 29;
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vertex_reuse_block_cntl_t f;
+} vgt_vertex_reuse_block_cntl_u;
+
+
+/*
+ * VGT_OUT_DEALLOC_CNTL struct
+ */
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003
+
+#define VGT_OUT_DEALLOC_CNTL_MASK \
+     (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK)
+
+#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \
+     ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT))
+
+#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \
+     ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \
+     vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+          unsigned int                                : 30;
+     } vgt_out_dealloc_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int                                : 30;
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+     } vgt_out_dealloc_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_out_dealloc_cntl_t f;
+} vgt_out_dealloc_cntl_u;
+
+
+/*
+ * VGT_MULTI_PRIM_IB_RESET_INDX struct
+ */
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \
+     (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \
+     ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT))
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \
+     ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \
+     vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int                                : 8;
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_multi_prim_ib_reset_indx_t f;
+} vgt_multi_prim_ib_reset_indx_u;
+
+
+/*
+ * VGT_ENHANCE struct
+ */
+
+#define VGT_ENHANCE_MISC_SIZE          16
+
+#define VGT_ENHANCE_MISC_SHIFT         0
+
+#define VGT_ENHANCE_MISC_MASK          0x0000ffff
+
+#define VGT_ENHANCE_MASK \
+     (VGT_ENHANCE_MISC_MASK)
+
+#define VGT_ENHANCE(misc) \
+     ((misc << VGT_ENHANCE_MISC_SHIFT))
+
+#define VGT_ENHANCE_GET_MISC(vgt_enhance) \
+     ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT)
+
+#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \
+     vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+          unsigned int                                : 16;
+     } vgt_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int                                : 16;
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+     } vgt_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_enhance_t f;
+} vgt_enhance_u;
+
+
+/*
+ * VGT_VTX_VECT_EJECT_REG struct
+ */
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f
+
+#define VGT_VTX_VECT_EJECT_REG_MASK \
+     (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK)
+
+#define VGT_VTX_VECT_EJECT_REG(prim_count) \
+     ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT))
+
+#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \
+     ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \
+     vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+          unsigned int                                : 27;
+     } vgt_vtx_vect_eject_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int                                : 27;
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+     } vgt_vtx_vect_eject_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vtx_vect_eject_reg_t f;
+} vgt_vtx_vect_eject_reg_u;
+
+
+/*
+ * VGT_LAST_COPY_STATE struct
+ */
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000
+
+#define VGT_LAST_COPY_STATE_MASK \
+     (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \
+      VGT_LAST_COPY_STATE_DST_STATE_ID_MASK)
+
+#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \
+     ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \
+      (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT))
+
+#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+     } vgt_last_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+     } vgt_last_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_last_copy_state_t f;
+} vgt_last_copy_state_u;
+
+
+/*
+ * VGT_DEBUG_CNTL struct
+ */
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f
+
+#define VGT_DEBUG_CNTL_MASK \
+     (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK)
+
+#define VGT_DEBUG_CNTL(vgt_debug_indx) \
+     ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT))
+
+#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \
+     ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \
+     vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } vgt_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+     } vgt_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_cntl_t f;
+} vgt_debug_cntl_u;
+
+
+/*
+ * VGT_DEBUG_DATA struct
+ */
+
+#define VGT_DEBUG_DATA_DATA_SIZE       32
+
+#define VGT_DEBUG_DATA_DATA_SHIFT      0
+
+#define VGT_DEBUG_DATA_DATA_MASK       0xffffffff
+
+#define VGT_DEBUG_DATA_MASK \
+     (VGT_DEBUG_DATA_DATA_MASK)
+
+#define VGT_DEBUG_DATA(data) \
+     ((data << VGT_DEBUG_DATA_DATA_SHIFT))
+
+#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \
+     ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT)
+
+#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \
+     vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_data_t f;
+} vgt_debug_data_u;
+
+
+/*
+ * VGT_CNTL_STATUS struct
+ */
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SIZE  1
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8
+
+#define VGT_CNTL_STATUS_VGT_BUSY_MASK  0x00000001
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100
+
+#define VGT_CNTL_STATUS_MASK \
+     (VGT_CNTL_STATUS_VGT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK)
+
+#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \
+     ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \
+      (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \
+      (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \
+      (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \
+      (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \
+      (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \
+      (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \
+      (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \
+      (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT))
+
+#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int                                : 23;
+     } vgt_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int                                : 23;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+     } vgt_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_cntl_status_t f;
+} vgt_cntl_status_u;
+
+
+/*
+ * VGT_DEBUG_REG0 struct
+ */
+
+#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_out_busy_SIZE   1
+#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1
+#define VGT_DEBUG_REG0_grp_busy_SIZE   1
+#define VGT_DEBUG_REG0_dma_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_rbiu_busy_SIZE  1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1
+
+#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0
+#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2
+#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3
+#define VGT_DEBUG_REG0_out_busy_SHIFT  4
+#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5
+#define VGT_DEBUG_REG0_grp_busy_SHIFT  6
+#define VGT_DEBUG_REG0_dma_busy_SHIFT  7
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8
+#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11
+#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12
+#define VGT_DEBUG_REG0_vgt_busy_SHIFT  13
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16
+
+#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001
+#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002
+#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004
+#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008
+#define VGT_DEBUG_REG0_out_busy_MASK   0x00000010
+#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020
+#define VGT_DEBUG_REG0_grp_busy_MASK   0x00000040
+#define VGT_DEBUG_REG0_dma_busy_MASK   0x00000080
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100
+#define VGT_DEBUG_REG0_rbiu_busy_MASK  0x00000200
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800
+#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000
+#define VGT_DEBUG_REG0_vgt_busy_MASK   0x00002000
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000
+
+#define VGT_DEBUG_REG0_MASK \
+     (VGT_DEBUG_REG0_te_grp_busy_MASK | \
+      VGT_DEBUG_REG0_pt_grp_busy_MASK | \
+      VGT_DEBUG_REG0_vr_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_out_busy_MASK | \
+      VGT_DEBUG_REG0_grp_backend_busy_MASK | \
+      VGT_DEBUG_REG0_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_MASK | \
+      VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_busy_MASK)
+
+#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \
+     ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \
+      (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \
+      (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \
+      (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \
+      (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \
+      (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \
+      (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \
+      (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \
+      (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \
+      (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \
+      (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \
+      (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \
+      (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \
+      (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \
+      (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \
+      (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \
+      (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT))
+
+#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int                                : 15;
+     } vgt_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int                                : 15;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+     } vgt_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg0_t f;
+} vgt_debug_reg0_u;
+
+
+/*
+ * VGT_DEBUG_REG1 struct
+ */
+
+#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1
+#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_te_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1
+#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1
+#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1
+#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1
+
+#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0
+#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3
+#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5
+#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7
+#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9
+#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10
+#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11
+#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12
+#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13
+#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14
+#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15
+#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16
+#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20
+#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28
+#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30
+
+#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001
+#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002
+#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004
+#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008
+#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010
+#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020
+#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040
+#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080
+#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100
+#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200
+#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400
+#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800
+#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000
+#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000
+#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000
+#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000
+#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000
+#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000
+#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000
+#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000
+
+#define VGT_DEBUG_REG1_MASK \
+     (VGT_DEBUG_REG1_out_te_data_read_MASK | \
+      VGT_DEBUG_REG1_te_out_data_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_prim_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_data_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_prim_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_indx_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_te_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_te_valid_MASK | \
+      VGT_DEBUG_REG1_pt_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_pt_valid_MASK | \
+      VGT_DEBUG_REG1_vr_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_vr_valid_MASK | \
+      VGT_DEBUG_REG1_grp_dma_read_MASK | \
+      VGT_DEBUG_REG1_dma_grp_valid_MASK | \
+      VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \
+      VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \
+      VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_MH_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \
+      VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_SQ_send_MASK | \
+      VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK)
+
+#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \
+     ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \
+      (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \
+      (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \
+      (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \
+      (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \
+      (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \
+      (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \
+      (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \
+      (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \
+      (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \
+      (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \
+      (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \
+      (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \
+      (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \
+      (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \
+      (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \
+      (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \
+      (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \
+      (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \
+      (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \
+      (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \
+      (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \
+      (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \
+      (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \
+      (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \
+      (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \
+      (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \
+      (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \
+      (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \
+      (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \
+      (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT))
+
+#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int                                : 1;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+     } vgt_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg1_t f;
+} vgt_debug_reg1_u;
+
+
+/*
+ * VGT_DEBUG_REG3 struct
+ */
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002
+
+#define VGT_DEBUG_REG3_MASK \
+     (VGT_DEBUG_REG3_vgt_clk_en_MASK | \
+      VGT_DEBUG_REG3_reg_fifos_clk_en_MASK)
+
+#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \
+     ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \
+      (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT))
+
+#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int                                : 30;
+     } vgt_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int                                : 30;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+     } vgt_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg3_t f;
+} vgt_debug_reg3_u;
+
+
+/*
+ * VGT_DEBUG_REG6 struct
+ */
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG6_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_extract_vector_SIZE 1
+#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG6_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG6_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG6_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG6_MASK \
+     (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG6_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG6_input_data_valid_MASK | \
+      VGT_DEBUG_REG6_input_data_xfer_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG6_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG6_shifter_first_load_MASK | \
+      VGT_DEBUG_REG6_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG6_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG6_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG6_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG6_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG6_extract_vector_MASK | \
+      VGT_DEBUG_REG6_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG6_destination_rtr_MASK | \
+      VGT_DEBUG_REG6_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int                                : 3;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg6_t f;
+} vgt_debug_reg6_u;
+
+
+/*
+ * VGT_DEBUG_REG7 struct
+ */
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG7_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG7_MASK \
+     (VGT_DEBUG_REG7_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG7_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG7_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG7_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+     } vgt_debug_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+     } vgt_debug_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg7_t f;
+} vgt_debug_reg7_u;
+
+
+/*
+ * VGT_DEBUG_REG8 struct
+ */
+
+#define VGT_DEBUG_REG8_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG8_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG8_MASK \
+     (VGT_DEBUG_REG8_current_source_sel_MASK | \
+      VGT_DEBUG_REG8_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG8_input_data_cnt_MASK | \
+      VGT_DEBUG_REG8_input_data_lsw_MASK | \
+      VGT_DEBUG_REG8_input_data_msw_MASK | \
+      VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+     } vgt_debug_reg8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg8_t f;
+} vgt_debug_reg8_u;
+
+
+/*
+ * VGT_DEBUG_REG9 struct
+ */
+
+#define VGT_DEBUG_REG9_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG9_MASK \
+     (VGT_DEBUG_REG9_next_stride_q_MASK | \
+      VGT_DEBUG_REG9_next_stride_d_MASK | \
+      VGT_DEBUG_REG9_current_shift_q_MASK | \
+      VGT_DEBUG_REG9_current_shift_d_MASK | \
+      VGT_DEBUG_REG9_current_stride_q_MASK | \
+      VGT_DEBUG_REG9_current_stride_d_MASK | \
+      VGT_DEBUG_REG9_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int                                : 1;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+     } vgt_debug_reg9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg9_t f;
+} vgt_debug_reg9_u;
+
+
+/*
+ * VGT_DEBUG_REG10 struct
+ */
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG10_bin_valid_SIZE 1
+#define VGT_DEBUG_REG10_read_block_SIZE 1
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1
+#define VGT_DEBUG_REG10_selected_data_SIZE 8
+#define VGT_DEBUG_REG10_mask_input_data_SIZE 8
+#define VGT_DEBUG_REG10_gap_q_SIZE     1
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1
+#define VGT_DEBUG_REG10_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3
+#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4
+#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5
+#define VGT_DEBUG_REG10_bin_valid_SHIFT 6
+#define VGT_DEBUG_REG10_read_block_SHIFT 7
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8
+#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10
+#define VGT_DEBUG_REG10_selected_data_SHIFT 11
+#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19
+#define VGT_DEBUG_REG10_gap_q_SHIFT    27
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30
+#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008
+#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010
+#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020
+#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040
+#define VGT_DEBUG_REG10_read_block_MASK 0x00000080
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100
+#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200
+#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400
+#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800
+#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000
+#define VGT_DEBUG_REG10_gap_q_MASK     0x08000000
+#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000
+#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000
+#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000
+#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG10_MASK \
+     (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG10_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG10_bin_valid_MASK | \
+      VGT_DEBUG_REG10_read_block_MASK | \
+      VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \
+      VGT_DEBUG_REG10_last_bit_enable_q_MASK | \
+      VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \
+      VGT_DEBUG_REG10_selected_data_MASK | \
+      VGT_DEBUG_REG10_mask_input_data_MASK | \
+      VGT_DEBUG_REG10_gap_q_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \
+      VGT_DEBUG_REG10_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \
+     ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \
+      (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \
+      (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \
+      (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \
+      (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \
+      (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \
+      (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \
+      (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \
+      (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \
+      (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \
+      (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \
+      (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \
+      (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \
+      (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \
+      (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+     } vgt_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+     } vgt_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg10_t f;
+} vgt_debug_reg10_u;
+
+
+/*
+ * VGT_DEBUG_REG12 struct
+ */
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG12_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_extract_vector_SIZE 1
+#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG12_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG12_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG12_MASK \
+     (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG12_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG12_input_data_valid_MASK | \
+      VGT_DEBUG_REG12_input_data_xfer_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG12_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG12_shifter_first_load_MASK | \
+      VGT_DEBUG_REG12_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG12_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG12_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG12_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG12_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG12_extract_vector_MASK | \
+      VGT_DEBUG_REG12_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG12_destination_rtr_MASK | \
+      VGT_DEBUG_REG12_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int                                : 3;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg12_t f;
+} vgt_debug_reg12_u;
+
+
+/*
+ * VGT_DEBUG_REG13 struct
+ */
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG13_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG13_MASK \
+     (VGT_DEBUG_REG13_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG13_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG13_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG13_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+     } vgt_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+     } vgt_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg13_t f;
+} vgt_debug_reg13_u;
+
+
+/*
+ * VGT_DEBUG_REG14 struct
+ */
+
+#define VGT_DEBUG_REG14_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG14_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG14_MASK \
+     (VGT_DEBUG_REG14_current_source_sel_MASK | \
+      VGT_DEBUG_REG14_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG14_input_data_cnt_MASK | \
+      VGT_DEBUG_REG14_input_data_lsw_MASK | \
+      VGT_DEBUG_REG14_input_data_msw_MASK | \
+      VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+     } vgt_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg14_t f;
+} vgt_debug_reg14_u;
+
+
+/*
+ * VGT_DEBUG_REG15 struct
+ */
+
+#define VGT_DEBUG_REG15_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG15_MASK \
+     (VGT_DEBUG_REG15_next_stride_q_MASK | \
+      VGT_DEBUG_REG15_next_stride_d_MASK | \
+      VGT_DEBUG_REG15_current_shift_q_MASK | \
+      VGT_DEBUG_REG15_current_shift_d_MASK | \
+      VGT_DEBUG_REG15_current_stride_q_MASK | \
+      VGT_DEBUG_REG15_current_stride_d_MASK | \
+      VGT_DEBUG_REG15_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int                                : 1;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+     } vgt_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg15_t f;
+} vgt_debug_reg15_u;
+
+
+/*
+ * VGT_DEBUG_REG16 struct
+ */
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1
+#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1
+#define VGT_DEBUG_REG16_current_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_en_SIZE 1
+#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1
+#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9
+#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10
+#define VGT_DEBUG_REG16_current_state_q_SHIFT 11
+#define VGT_DEBUG_REG16_old_state_q_SHIFT 12
+#define VGT_DEBUG_REG16_old_state_en_SHIFT 13
+#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15
+#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17
+#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30
+#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200
+#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400
+#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800
+#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000
+#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000
+#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000
+#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000
+#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000
+#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000
+#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000
+#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG16_MASK \
+     (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \
+      VGT_DEBUG_REG16_rst_last_bit_MASK | \
+      VGT_DEBUG_REG16_current_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_en_MASK | \
+      VGT_DEBUG_REG16_prev_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_last_bit_block_q_MASK | \
+      VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \
+      VGT_DEBUG_REG16_load_empty_reg_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \
+      VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \
+     ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \
+      (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \
+      (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \
+      (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \
+      (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \
+      (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \
+      (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \
+      (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \
+      (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \
+      (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \
+      (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \
+      (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \
+      (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \
+      (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \
+      (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \
+      (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \
+      (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \
+      (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \
+      (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \
+      (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \
+      (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+     } vgt_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+     } vgt_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg16_t f;
+} vgt_debug_reg16_u;
+
+
+/*
+ * VGT_DEBUG_REG17 struct
+ */
+
+#define VGT_DEBUG_REG17_save_read_q_SIZE 1
+#define VGT_DEBUG_REG17_extend_read_q_SIZE 1
+#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2
+#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1
+#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1
+#define VGT_DEBUG_REG17_check_second_reg_SIZE 1
+#define VGT_DEBUG_REG17_check_first_reg_SIZE 1
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1
+#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG17_save_read_q_SHIFT 0
+#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1
+#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2
+#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4
+#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5
+#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6
+#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7
+#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8
+#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14
+#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15
+#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24
+#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001
+#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002
+#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c
+#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010
+#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020
+#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040
+#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080
+#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100
+#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000
+#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000
+#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000
+#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000
+#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000
+#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG17_MASK \
+     (VGT_DEBUG_REG17_save_read_q_MASK | \
+      VGT_DEBUG_REG17_extend_read_q_MASK | \
+      VGT_DEBUG_REG17_grp_indx_size_MASK | \
+      VGT_DEBUG_REG17_cull_prim_true_MASK | \
+      VGT_DEBUG_REG17_reset_bit2_q_MASK | \
+      VGT_DEBUG_REG17_reset_bit1_q_MASK | \
+      VGT_DEBUG_REG17_first_reg_first_q_MASK | \
+      VGT_DEBUG_REG17_check_second_reg_MASK | \
+      VGT_DEBUG_REG17_check_first_reg_MASK | \
+      VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \
+      VGT_DEBUG_REG17_to_second_reg_q_MASK | \
+      VGT_DEBUG_REG17_roll_over_msk_q_MASK | \
+      VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \
+     ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \
+      (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \
+      (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \
+      (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \
+      (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \
+      (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \
+      (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \
+      (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \
+      (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \
+      (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \
+      (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \
+      (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \
+      (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \
+      (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \
+      (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \
+      (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \
+      (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \
+      (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+     } vgt_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+     } vgt_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg17_t f;
+} vgt_debug_reg17_u;
+
+
+/*
+ * VGT_DEBUG_REG18 struct
+ */
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_start_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1
+#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13
+#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15
+#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16
+#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17
+#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20
+#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21
+#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22
+#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23
+#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24
+#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26
+#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27
+#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28
+#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000
+#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000
+#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000
+#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000
+#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000
+#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000
+#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000
+#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000
+#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000
+#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000
+#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000
+#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000
+#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000
+#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000
+
+#define VGT_DEBUG_REG18_MASK \
+     (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG18_dma_mem_full_MASK | \
+      VGT_DEBUG_REG18_dma_ram_re_MASK | \
+      VGT_DEBUG_REG18_dma_ram_we_MASK | \
+      VGT_DEBUG_REG18_dma_mem_empty_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \
+      VGT_DEBUG_REG18_bin_mem_full_MASK | \
+      VGT_DEBUG_REG18_bin_ram_we_MASK | \
+      VGT_DEBUG_REG18_bin_ram_re_MASK | \
+      VGT_DEBUG_REG18_bin_mem_empty_MASK | \
+      VGT_DEBUG_REG18_start_bin_req_MASK | \
+      VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \
+      VGT_DEBUG_REG18_dma_req_xfer_MASK | \
+      VGT_DEBUG_REG18_have_valid_bin_req_MASK | \
+      VGT_DEBUG_REG18_have_valid_dma_req_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK)
+
+#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \
+     ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \
+      (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \
+      (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \
+      (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \
+      (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \
+      (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \
+      (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \
+      (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \
+      (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \
+      (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \
+      (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \
+      (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \
+      (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \
+      (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \
+      (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \
+      (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \
+      (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \
+      (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \
+      (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT))
+
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+     } vgt_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+     } vgt_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg18_t f;
+} vgt_debug_reg18_u;
+
+
+/*
+ * VGT_DEBUG_REG20 struct
+ */
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_sent_cnt_SIZE  4
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5
+#define VGT_DEBUG_REG20_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5
+#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6
+#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7
+#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8
+#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9
+#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10
+#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11
+#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12
+#define VGT_DEBUG_REG20_hold_prim_SHIFT 13
+#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21
+#define VGT_DEBUG_REG20_out_trigger_SHIFT 26
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004
+#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020
+#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040
+#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080
+#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100
+#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200
+#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400
+#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800
+#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000
+#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000
+#define VGT_DEBUG_REG20_sent_cnt_MASK  0x0003c000
+#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000
+#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000
+#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000
+
+#define VGT_DEBUG_REG20_MASK \
+     (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_re_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_we_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_full_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_re_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_we_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_full_MASK | \
+      VGT_DEBUG_REG20_hold_prim_MASK | \
+      VGT_DEBUG_REG20_sent_cnt_MASK | \
+      VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \
+      VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \
+      VGT_DEBUG_REG20_out_trigger_MASK)
+
+#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \
+     ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \
+      (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \
+      (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \
+      (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \
+      (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \
+      (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \
+      (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \
+      (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \
+      (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \
+      (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \
+      (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \
+      (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \
+      (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \
+      (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \
+      (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \
+      (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \
+      (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \
+      (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \
+      (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int                                : 5;
+     } vgt_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int                                : 5;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+     } vgt_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg20_t f;
+} vgt_debug_reg20_u;
+
+
+/*
+ * VGT_DEBUG_REG21 struct
+ */
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3
+#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4
+#define VGT_DEBUG_REG21_new_packet_q_SIZE 1
+#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1
+#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1
+#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1
+#define VGT_DEBUG_REG21_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1
+#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14
+#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18
+#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22
+#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25
+#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26
+#define VGT_DEBUG_REG21_out_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e
+#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380
+#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000
+#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000
+#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000
+#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000
+#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000
+#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000
+#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG21_MASK \
+     (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \
+      VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \
+      VGT_DEBUG_REG21_alloc_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \
+      VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \
+      VGT_DEBUG_REG21_new_packet_q_MASK | \
+      VGT_DEBUG_REG21_new_allocate_q_MASK | \
+      VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \
+      VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \
+      VGT_DEBUG_REG21_insert_null_prim_MASK | \
+      VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \
+      VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \
+      VGT_DEBUG_REG21_buffered_thread_size_MASK | \
+      VGT_DEBUG_REG21_out_trigger_MASK)
+
+#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \
+     ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \
+      (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \
+      (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \
+      (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \
+      (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \
+      (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \
+      (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \
+      (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \
+      (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \
+      (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \
+      (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \
+      (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \
+      (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \
+      (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int                                : 4;
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+     } vgt_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+          unsigned int                                : 4;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+     } vgt_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg21_t f;
+} vgt_debug_reg21_u;
+
+
+/*
+ * VGT_CRC_SQ_DATA struct
+ */
+
+#define VGT_CRC_SQ_DATA_CRC_SIZE       32
+
+#define VGT_CRC_SQ_DATA_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_DATA_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_DATA_MASK \
+     (VGT_CRC_SQ_DATA_CRC_MASK)
+
+#define VGT_CRC_SQ_DATA(crc) \
+     ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT))
+
+#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \
+     ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \
+     vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_data_t f;
+} vgt_crc_sq_data_u;
+
+
+/*
+ * VGT_CRC_SQ_CTRL struct
+ */
+
+#define VGT_CRC_SQ_CTRL_CRC_SIZE       32
+
+#define VGT_CRC_SQ_CTRL_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_CTRL_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_CTRL_MASK \
+     (VGT_CRC_SQ_CTRL_CRC_MASK)
+
+#define VGT_CRC_SQ_CTRL(crc) \
+     ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT))
+
+#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \
+     ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \
+     vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_ctrl_t f;
+} vgt_crc_sq_ctrl_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER0_SELECT_MASK \
+     (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \
+     ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \
+     vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_select_t f;
+} vgt_perfcounter0_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER1_SELECT_MASK \
+     (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \
+     ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \
+     vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_select_t f;
+} vgt_perfcounter1_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER2_SELECT_MASK \
+     (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \
+     ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \
+     vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_select_t f;
+} vgt_perfcounter2_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER3_SELECT_MASK \
+     (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \
+     ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \
+     vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_select_t f;
+} vgt_perfcounter3_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_LOW struct
+ */
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER0_LOW_MASK \
+     (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \
+     ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \
+     vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_low_t f;
+} vgt_perfcounter0_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_LOW struct
+ */
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER1_LOW_MASK \
+     (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \
+     ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \
+     vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_low_t f;
+} vgt_perfcounter1_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_LOW struct
+ */
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER2_LOW_MASK \
+     (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \
+     ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \
+     vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_low_t f;
+} vgt_perfcounter2_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_LOW struct
+ */
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER3_LOW_MASK \
+     (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \
+     ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \
+     vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_low_t f;
+} vgt_perfcounter3_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_HI struct
+ */
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER0_HI_MASK \
+     (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \
+     ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \
+     vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_hi_t f;
+} vgt_perfcounter0_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_HI struct
+ */
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER1_HI_MASK \
+     (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \
+     ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \
+     vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_hi_t f;
+} vgt_perfcounter1_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_HI struct
+ */
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER2_HI_MASK \
+     (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \
+     ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \
+     vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_hi_t f;
+} vgt_perfcounter2_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_HI struct
+ */
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER3_HI_MASK \
+     (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \
+     ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \
+     vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_hi_t f;
+} vgt_perfcounter3_hi_u;
+
+
+#endif
+
+
+#if !defined (_SQ_FIDDLE_H)
+#define _SQ_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sq_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * SQ_GPR_MANAGEMENT struct
+ */
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000
+
+#define SQ_GPR_MANAGEMENT_MASK \
+     (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK)
+
+#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \
+     ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \
+      (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \
+      (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT))
+
+#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 13;
+     } sq_gpr_management_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int                                : 13;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+     } sq_gpr_management_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_gpr_management_t f;
+} sq_gpr_management_u;
+
+
+/*
+ * SQ_FLOW_CONTROL struct
+ */
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1
+#define SQ_FLOW_CONTROL_ONE_ALU_SIZE   1
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4
+#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE  1
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0
+#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4
+#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT  8
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12
+#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003
+#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010
+#define SQ_FLOW_CONTROL_ONE_ALU_MASK   0x00000100
+#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000
+#define SQ_FLOW_CONTROL_NO_PV_PS_MASK  0x00010000
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000
+
+#define SQ_FLOW_CONTROL_MASK \
+     (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ONE_THREAD_MASK | \
+      SQ_FLOW_CONTROL_ONE_ALU_MASK | \
+      SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \
+      SQ_FLOW_CONTROL_NO_PV_PS_MASK | \
+      SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \
+      SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \
+      SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \
+      SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \
+      SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \
+      SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \
+      SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK)
+
+#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \
+     ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \
+      (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \
+      (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \
+      (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \
+      (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \
+      (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \
+      (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \
+      (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \
+      (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \
+      (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \
+      (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \
+      (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \
+      (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \
+      (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \
+      (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT))
+
+#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+          unsigned int                                : 2;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int                                : 4;
+     } sq_flow_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int                                : 4;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 2;
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+     } sq_flow_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_flow_control_t f;
+} sq_flow_control_u;
+
+
+/*
+ * SQ_INST_STORE_MANAGMENT struct
+ */
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000
+
+#define SQ_INST_STORE_MANAGMENT_MASK \
+     (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \
+      SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK)
+
+#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \
+     ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \
+      (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT))
+
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+     } sq_inst_store_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+     } sq_inst_store_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_inst_store_managment_t f;
+} sq_inst_store_managment_u;
+
+
+/*
+ * SQ_RESOURCE_MANAGMENT struct
+ */
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000
+
+#define SQ_RESOURCE_MANAGMENT_MASK \
+     (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK)
+
+#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \
+     ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT))
+
+#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int                                : 7;
+     } sq_resource_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int                                : 7;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+     } sq_resource_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_resource_managment_t f;
+} sq_resource_managment_u;
+
+
+/*
+ * SQ_EO_RT struct
+ */
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE  8
+#define SQ_EO_RT_EO_TSTATE_RT_SIZE     8
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0
+#define SQ_EO_RT_EO_TSTATE_RT_SHIFT    16
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_MASK  0x000000ff
+#define SQ_EO_RT_EO_TSTATE_RT_MASK     0x00ff0000
+
+#define SQ_EO_RT_MASK \
+     (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \
+      SQ_EO_RT_EO_TSTATE_RT_MASK)
+
+#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \
+     ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \
+      (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT))
+
+#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+     } sq_eo_rt_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+     } sq_eo_rt_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_eo_rt_t f;
+} sq_eo_rt_u;
+
+
+/*
+ * SQ_DEBUG_MISC struct
+ */
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8
+#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1
+#define SQ_DEBUG_MISC_RESERVED_SIZE    2
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12
+#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20
+#define SQ_DEBUG_MISC_RESERVED_SHIFT   21
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000
+#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000
+#define SQ_DEBUG_MISC_RESERVED_MASK    0x00600000
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000
+
+#define SQ_DEBUG_MISC_MASK \
+     (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_READ_CTX_MASK | \
+      SQ_DEBUG_MISC_RESERVED_MASK | \
+      SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK)
+
+#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \
+     ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \
+      (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \
+      (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \
+      (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \
+      (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \
+      (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \
+      (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \
+      (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \
+      (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT))
+
+#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int                                : 3;
+     } sq_debug_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int                                : 3;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+     } sq_debug_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_t f;
+} sq_debug_misc_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_CNTL struct
+ */
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000
+#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000
+
+#define SQ_ACTIVITY_METER_CNTL_MASK \
+     (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \
+      SQ_ACTIVITY_METER_CNTL_SPARE_MASK)
+
+#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \
+     ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \
+      (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \
+      (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \
+      (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT))
+
+#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_cntl_t f;
+} sq_activity_meter_cntl_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_STATUS struct
+ */
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff
+
+#define SQ_ACTIVITY_METER_STATUS_MASK \
+     (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK)
+
+#define SQ_ACTIVITY_METER_STATUS(percent_busy) \
+     ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT))
+
+#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \
+     ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \
+     sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+          unsigned int                                : 24;
+     } sq_activity_meter_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int                                : 24;
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+     } sq_activity_meter_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_status_t f;
+} sq_activity_meter_status_u;
+
+
+/*
+ * SQ_INPUT_ARB_PRIORITY struct
+ */
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+
+#define SQ_INPUT_ARB_PRIORITY_MASK \
+     (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK)
+
+#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \
+     ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT))
+
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int                                : 14;
+     } sq_input_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int                                : 14;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_input_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_input_arb_priority_t f;
+} sq_input_arb_priority_u;
+
+
+/*
+ * SQ_THREAD_ARB_PRIORITY struct
+ */
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000
+
+#define SQ_THREAD_ARB_PRIORITY_MASK \
+     (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \
+      SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \
+      SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK)
+
+#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \
+     ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \
+      (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \
+      (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \
+      (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \
+      (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT))
+
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int                                : 9;
+     } sq_thread_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int                                : 9;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_thread_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_thread_arb_priority_t f;
+} sq_thread_arb_priority_u;
+
+
+/*
+ * SQ_DEBUG_INPUT_FSM struct
+ */
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE  3
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007
+#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK  0x00007000
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000
+
+#define SQ_DEBUG_INPUT_FSM_MASK \
+     (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \
+      SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK)
+
+#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \
+     ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \
+      (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \
+      (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \
+      (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \
+      (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \
+      (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \
+      (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \
+      (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT))
+
+#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_input_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int                                : 4;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+     } sq_debug_input_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_input_fsm_t f;
+} sq_debug_input_fsm_u;
+
+
+/*
+ * SQ_DEBUG_CONST_MGR_FSM struct
+ */
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000
+
+#define SQ_DEBUG_CONST_MGR_FSM_MASK \
+     (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK)
+
+#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \
+     ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \
+      (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \
+      (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \
+      (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \
+      (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \
+      (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \
+      (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \
+      (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \
+      (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \
+      (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT))
+
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int                                : 8;
+     } sq_debug_const_mgr_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int                                : 8;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+     } sq_debug_const_mgr_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_const_mgr_fsm_t f;
+} sq_debug_const_mgr_fsm_u;
+
+
+/*
+ * SQ_DEBUG_TP_FSM struct
+ */
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1
+#define SQ_DEBUG_TP_FSM_CF_TP_SIZE     4
+#define SQ_DEBUG_TP_FSM_IF_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2
+#define SQ_DEBUG_TP_FSM_GS_TP_SIZE     2
+#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT    0
+#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3
+#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT    4
+#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT    8
+#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT   12
+#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14
+#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT    16
+#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18
+#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT   20
+#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22
+#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT   24
+#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28
+
+#define SQ_DEBUG_TP_FSM_EX_TP_MASK     0x00000007
+#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_TP_FSM_CF_TP_MASK     0x000000f0
+#define SQ_DEBUG_TP_FSM_IF_TP_MASK     0x00000700
+#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_TP_FSM_TIS_TP_MASK    0x00003000
+#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000
+#define SQ_DEBUG_TP_FSM_GS_TP_MASK     0x00030000
+#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000
+#define SQ_DEBUG_TP_FSM_FCR_TP_MASK    0x00300000
+#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000
+#define SQ_DEBUG_TP_FSM_FCS_TP_MASK    0x03000000
+#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000
+
+#define SQ_DEBUG_TP_FSM_MASK \
+     (SQ_DEBUG_TP_FSM_EX_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED0_MASK | \
+      SQ_DEBUG_TP_FSM_CF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_IF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_TP_FSM_TIS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_TP_FSM_GS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED3_MASK | \
+      SQ_DEBUG_TP_FSM_FCR_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED4_MASK | \
+      SQ_DEBUG_TP_FSM_FCS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED5_MASK | \
+      SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK)
+
+#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \
+     ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \
+      (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \
+      (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \
+      (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \
+      (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \
+      (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \
+      (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \
+      (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \
+      (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \
+      (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \
+      (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \
+      (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \
+      (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \
+      (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT))
+
+#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_tp_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+     } sq_debug_tp_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tp_fsm_t f;
+} sq_debug_tp_fsm_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_0 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_0_MASK \
+     (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_0_t f;
+} sq_debug_fsm_alu_0_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_1 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_1_MASK \
+     (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_1_t f;
+} sq_debug_fsm_alu_1_u;
+
+
+/*
+ * SQ_DEBUG_EXP_ALLOC struct
+ */
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000
+
+#define SQ_DEBUG_EXP_ALLOC_MASK \
+     (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \
+      SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK)
+
+#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \
+     ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \
+      (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \
+      (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \
+      (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \
+      (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT))
+
+#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_exp_alloc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int                                : 10;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+     } sq_debug_exp_alloc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_exp_alloc_t f;
+} sq_debug_exp_alloc_u;
+
+
+/*
+ * SQ_DEBUG_PTR_BUFF struct
+ */
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000
+
+#define SQ_DEBUG_PTR_BUFF_MASK \
+     (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \
+      SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \
+      SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \
+      SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \
+      SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \
+      SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK)
+
+#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \
+     ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \
+      (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \
+      (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \
+      (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \
+      (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \
+      (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \
+      (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \
+      (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \
+      (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT))
+
+#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_ptr_buff_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int                                : 4;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+     } sq_debug_ptr_buff_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_ptr_buff_t f;
+} sq_debug_ptr_buff_u;
+
+
+/*
+ * SQ_DEBUG_GPR_VTX struct
+ */
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_VTX_MASK \
+     (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \
+     ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \
+      (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \
+      (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \
+      (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_vtx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int                                : 1;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_vtx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_vtx_t f;
+} sq_debug_gpr_vtx_u;
+
+
+/*
+ * SQ_DEBUG_GPR_PIX struct
+ */
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_PIX_MASK \
+     (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \
+     ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \
+      (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \
+      (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \
+      (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_pix_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int                                : 1;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_pix_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_pix_t f;
+} sq_debug_gpr_pix_u;
+
+
+/*
+ * SQ_DEBUG_TB_STATUS_SEL struct
+ */
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000
+
+#define SQ_DEBUG_TB_STATUS_SEL_MASK \
+     (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK)
+
+#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \
+     ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \
+      (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \
+      (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \
+      (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \
+      (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT))
+
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tb_status_sel_t f;
+} sq_debug_tb_status_sel_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_0 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE  1
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK  0x00200000
+
+#define SQ_DEBUG_VTX_TB_0_MASK \
+     (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \
+      SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK)
+
+#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \
+     ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \
+      (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \
+      (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \
+      (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \
+      (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \
+      (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \
+      (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_vtx_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int                                : 10;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+     } sq_debug_vtx_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_0_t f;
+} sq_debug_vtx_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_1 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff
+
+#define SQ_DEBUG_VTX_TB_1_MASK \
+     (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK)
+
+#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \
+     ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \
+     ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \
+     sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+          unsigned int                                : 16;
+     } sq_debug_vtx_tb_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int                                : 16;
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+     } sq_debug_vtx_tb_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_1_t f;
+} sq_debug_vtx_tb_1_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATUS_REG struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \
+     (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \
+     ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \
+     ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \
+     sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_status_reg_t f;
+} sq_debug_vtx_tb_status_reg_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \
+     ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \
+     ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \
+     sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_state_mem_t f;
+} sq_debug_vtx_tb_state_mem_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE    1
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25
+#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT   31
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000
+#define SQ_DEBUG_PIX_TB_0_BUSY_MASK    0x80000000
+
+#define SQ_DEBUG_PIX_TB_0_MASK \
+     (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_BUSY_MASK)
+
+#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \
+     ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \
+      (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \
+      (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \
+      (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \
+      (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \
+      (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_0_t f;
+} sq_debug_pix_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \
+     ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \
+     ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \
+     sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_0_t f;
+} sq_debug_pix_tb_status_reg_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \
+     ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \
+     ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \
+     sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_1_t f;
+} sq_debug_pix_tb_status_reg_1_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \
+     ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \
+     ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \
+     sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_2_t f;
+} sq_debug_pix_tb_status_reg_2_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \
+     ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \
+     ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \
+     sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_3_t f;
+} sq_debug_pix_tb_status_reg_3_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \
+     ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \
+     ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \
+     sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_state_mem_t f;
+} sq_debug_pix_tb_state_mem_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER0_SELECT_MASK \
+     (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \
+     ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \
+     sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_select_t f;
+} sq_perfcounter0_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER1_SELECT_MASK \
+     (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \
+     ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \
+     sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_select_t f;
+} sq_perfcounter1_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER2_SELECT_MASK \
+     (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \
+     ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \
+     sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_select_t f;
+} sq_perfcounter2_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER3_SELECT_MASK \
+     (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \
+     ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \
+     sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_select_t f;
+} sq_perfcounter3_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_LOW struct
+ */
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER0_LOW_MASK \
+     (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \
+     ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \
+     sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_low_t f;
+} sq_perfcounter0_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_HI struct
+ */
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER0_HI_MASK \
+     (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \
+     ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \
+     sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_hi_t f;
+} sq_perfcounter0_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_LOW struct
+ */
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER1_LOW_MASK \
+     (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \
+     ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \
+     sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_low_t f;
+} sq_perfcounter1_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_HI struct
+ */
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER1_HI_MASK \
+     (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \
+     ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \
+     sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_hi_t f;
+} sq_perfcounter1_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_LOW struct
+ */
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER2_LOW_MASK \
+     (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \
+     ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \
+     sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_low_t f;
+} sq_perfcounter2_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_HI struct
+ */
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER2_HI_MASK \
+     (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \
+     ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \
+     sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_hi_t f;
+} sq_perfcounter2_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_LOW struct
+ */
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER3_LOW_MASK \
+     (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \
+     ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \
+     sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_low_t f;
+} sq_perfcounter3_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_HI struct
+ */
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER3_HI_MASK \
+     (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \
+     ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \
+     sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_hi_t f;
+} sq_perfcounter3_hi_u;
+
+
+/*
+ * SX_PERFCOUNTER0_SELECT struct
+ */
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SX_PERFCOUNTER0_SELECT_MASK \
+     (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SX_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \
+     ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \
+     sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sx_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sx_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_select_t f;
+} sx_perfcounter0_select_u;
+
+
+/*
+ * SX_PERFCOUNTER0_LOW struct
+ */
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SX_PERFCOUNTER0_LOW_MASK \
+     (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \
+     ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \
+     sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_low_t f;
+} sx_perfcounter0_low_u;
+
+
+/*
+ * SX_PERFCOUNTER0_HI struct
+ */
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SX_PERFCOUNTER0_HI_MASK \
+     (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \
+     ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \
+     sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sx_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sx_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_hi_t f;
+} sx_perfcounter0_hi_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_0 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0
+#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT 6
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8
+#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT 14
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_ALU_0_MASK \
+     (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_ALU_0(vector_result, cst_0_abs_mod, low_precision_16b_fp, scalar_result, sst_0_abs_mod, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \
+     ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \
+      (cst_0_abs_mod << SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT) | \
+      (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \
+      (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \
+      (sst_0_abs_mod << SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT) | \
+      (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \
+      (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \
+      (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \
+      (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \
+      (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \
+      (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_CST_0_ABS_MOD(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK) >> SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SST_0_ABS_MOD(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK) >> SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_CST_0_ABS_MOD(sq_instruction_alu_0_reg, cst_0_abs_mod) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK) | (cst_0_abs_mod << SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SST_0_ABS_MOD(sq_instruction_alu_0_reg, sst_0_abs_mod) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK) | (sst_0_abs_mod << SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+          unsigned int cst_0_abs_mod                  : SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int sst_0_abs_mod                  : SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+     } sq_instruction_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int sst_0_abs_mod                  : SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int cst_0_abs_mod                  : SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE;
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+     } sq_instruction_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_0_t f;
+} sq_instruction_alu_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_1 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_1_MASK \
+     (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \
+      SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK)
+
+#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \
+     ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \
+      (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \
+      (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \
+      (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \
+      (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \
+      (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \
+      (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \
+      (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \
+      (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \
+      (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \
+      (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \
+      (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \
+      (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \
+      (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \
+      (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \
+      (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \
+      (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \
+      (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+     } sq_instruction_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+     } sq_instruction_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_1_t f;
+} sq_instruction_alu_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_2 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_2_MASK \
+     (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK)
+
+#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \
+     ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \
+      (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \
+      (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \
+      (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \
+      (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \
+      (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \
+      (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \
+      (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \
+      (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \
+      (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \
+      (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \
+      (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \
+      (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+     } sq_instruction_alu_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+     } sq_instruction_alu_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_2_t f;
+} sq_instruction_alu_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_0_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \
+     ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \
+      (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_0_t f;
+} sq_instruction_cf_exec_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_1_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \
+     ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_1_t f;
+} sq_instruction_cf_exec_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_EXEC_2_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \
+     ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \
+      (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_2_t f;
+} sq_instruction_cf_exec_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000
+
+#define SQ_INSTRUCTION_CF_LOOP_0_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \
+      (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_0_t f;
+} sq_instruction_cf_loop_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_CF_LOOP_1_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_1_t f;
+} sq_instruction_cf_loop_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_LOOP_2_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \
+     ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_2_t f;
+} sq_instruction_cf_loop_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \
+      (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_0_t f;
+} sq_instruction_cf_jmp_call_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \
+      (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_1_t f;
+} sq_instruction_cf_jmp_call_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_2_t f;
+} sq_instruction_cf_jmp_call_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \
+     ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_0_t f;
+} sq_instruction_cf_alloc_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \
+      (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_1_t f;
+} sq_instruction_cf_alloc_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_2_t f;
+} sq_instruction_cf_alloc_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_TFETCH_0_MASK \
+     (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \
+     ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \
+      (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \
+      (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \
+      (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \
+      (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \
+      (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_0_t f;
+} sq_instruction_tfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_1_MASK \
+     (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \
+      (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \
+      (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \
+      (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \
+      (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \
+      (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \
+      (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \
+      (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \
+      (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \
+      (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_1_t f;
+} sq_instruction_tfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_2_MASK \
+     (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \
+     ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \
+      (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \
+      (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \
+      (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \
+      (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \
+      (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \
+      (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_2_t f;
+} sq_instruction_tfetch_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_VFETCH_0_MASK \
+     (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \
+     ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \
+      (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \
+      (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \
+      (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_0_t f;
+} sq_instruction_vfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_1_MASK \
+     (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \
+      (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \
+      (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \
+      (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \
+      (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \
+      (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_1_t f;
+} sq_instruction_vfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_2_MASK \
+     (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \
+     ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \
+      (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+          unsigned int                                : 8;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 7;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int                                : 7;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 8;
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_2_t f;
+} sq_instruction_vfetch_2_u;
+
+
+/*
+ * SQ_CONSTANT_0 struct
+ */
+
+#define SQ_CONSTANT_0_RED_SIZE         32
+
+#define SQ_CONSTANT_0_RED_SHIFT        0
+
+#define SQ_CONSTANT_0_RED_MASK         0xffffffff
+
+#define SQ_CONSTANT_0_MASK \
+     (SQ_CONSTANT_0_RED_MASK)
+
+#define SQ_CONSTANT_0(red) \
+     ((red << SQ_CONSTANT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \
+     ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \
+     sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_0_t f;
+} sq_constant_0_u;
+
+
+/*
+ * SQ_CONSTANT_1 struct
+ */
+
+#define SQ_CONSTANT_1_GREEN_SIZE       32
+
+#define SQ_CONSTANT_1_GREEN_SHIFT      0
+
+#define SQ_CONSTANT_1_GREEN_MASK       0xffffffff
+
+#define SQ_CONSTANT_1_MASK \
+     (SQ_CONSTANT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_1(green) \
+     ((green << SQ_CONSTANT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \
+     ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \
+     sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_1_t f;
+} sq_constant_1_u;
+
+
+/*
+ * SQ_CONSTANT_2 struct
+ */
+
+#define SQ_CONSTANT_2_BLUE_SIZE        32
+
+#define SQ_CONSTANT_2_BLUE_SHIFT       0
+
+#define SQ_CONSTANT_2_BLUE_MASK        0xffffffff
+
+#define SQ_CONSTANT_2_MASK \
+     (SQ_CONSTANT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_2(blue) \
+     ((blue << SQ_CONSTANT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \
+     ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \
+     sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_2_t f;
+} sq_constant_2_u;
+
+
+/*
+ * SQ_CONSTANT_3 struct
+ */
+
+#define SQ_CONSTANT_3_ALPHA_SIZE       32
+
+#define SQ_CONSTANT_3_ALPHA_SHIFT      0
+
+#define SQ_CONSTANT_3_ALPHA_MASK       0xffffffff
+
+#define SQ_CONSTANT_3_MASK \
+     (SQ_CONSTANT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_3(alpha) \
+     ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \
+     ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \
+     sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_3_t f;
+} sq_constant_3_u;
+
+
+/*
+ * SQ_FETCH_0 struct
+ */
+
+#define SQ_FETCH_0_VALUE_SIZE          32
+
+#define SQ_FETCH_0_VALUE_SHIFT         0
+
+#define SQ_FETCH_0_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_0_MASK \
+     (SQ_FETCH_0_VALUE_MASK)
+
+#define SQ_FETCH_0(value) \
+     ((value << SQ_FETCH_0_VALUE_SHIFT))
+
+#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \
+     ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT)
+
+#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \
+     sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_0_t f;
+} sq_fetch_0_u;
+
+
+/*
+ * SQ_FETCH_1 struct
+ */
+
+#define SQ_FETCH_1_VALUE_SIZE          32
+
+#define SQ_FETCH_1_VALUE_SHIFT         0
+
+#define SQ_FETCH_1_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_1_MASK \
+     (SQ_FETCH_1_VALUE_MASK)
+
+#define SQ_FETCH_1(value) \
+     ((value << SQ_FETCH_1_VALUE_SHIFT))
+
+#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \
+     ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT)
+
+#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \
+     sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_1_t f;
+} sq_fetch_1_u;
+
+
+/*
+ * SQ_FETCH_2 struct
+ */
+
+#define SQ_FETCH_2_VALUE_SIZE          32
+
+#define SQ_FETCH_2_VALUE_SHIFT         0
+
+#define SQ_FETCH_2_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_2_MASK \
+     (SQ_FETCH_2_VALUE_MASK)
+
+#define SQ_FETCH_2(value) \
+     ((value << SQ_FETCH_2_VALUE_SHIFT))
+
+#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \
+     ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT)
+
+#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \
+     sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_2_t f;
+} sq_fetch_2_u;
+
+
+/*
+ * SQ_FETCH_3 struct
+ */
+
+#define SQ_FETCH_3_VALUE_SIZE          32
+
+#define SQ_FETCH_3_VALUE_SHIFT         0
+
+#define SQ_FETCH_3_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_3_MASK \
+     (SQ_FETCH_3_VALUE_MASK)
+
+#define SQ_FETCH_3(value) \
+     ((value << SQ_FETCH_3_VALUE_SHIFT))
+
+#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \
+     ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT)
+
+#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \
+     sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_3_t f;
+} sq_fetch_3_u;
+
+
+/*
+ * SQ_FETCH_4 struct
+ */
+
+#define SQ_FETCH_4_VALUE_SIZE          32
+
+#define SQ_FETCH_4_VALUE_SHIFT         0
+
+#define SQ_FETCH_4_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_4_MASK \
+     (SQ_FETCH_4_VALUE_MASK)
+
+#define SQ_FETCH_4(value) \
+     ((value << SQ_FETCH_4_VALUE_SHIFT))
+
+#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \
+     ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT)
+
+#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \
+     sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_4_t f;
+} sq_fetch_4_u;
+
+
+/*
+ * SQ_FETCH_5 struct
+ */
+
+#define SQ_FETCH_5_VALUE_SIZE          32
+
+#define SQ_FETCH_5_VALUE_SHIFT         0
+
+#define SQ_FETCH_5_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_5_MASK \
+     (SQ_FETCH_5_VALUE_MASK)
+
+#define SQ_FETCH_5(value) \
+     ((value << SQ_FETCH_5_VALUE_SHIFT))
+
+#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \
+     ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT)
+
+#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \
+     sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_5_t f;
+} sq_fetch_5_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_0 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0
+#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001
+#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_0_MASK \
+     (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \
+      SQ_CONSTANT_VFETCH_0_STATE_MASK | \
+      SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \
+     ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \
+      (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \
+      (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_0_t f;
+} sq_constant_vfetch_0_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_1 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_1_MASK \
+     (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \
+      SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \
+     ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \
+      (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_1_t f;
+} sq_constant_vfetch_1_u;
+
+
+/*
+ * SQ_CONSTANT_T2 struct
+ */
+
+#define SQ_CONSTANT_T2_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T2_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T2_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T2_MASK \
+     (SQ_CONSTANT_T2_VALUE_MASK)
+
+#define SQ_CONSTANT_T2(value) \
+     ((value << SQ_CONSTANT_T2_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \
+     ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \
+     sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t2_t f;
+} sq_constant_t2_u;
+
+
+/*
+ * SQ_CONSTANT_T3 struct
+ */
+
+#define SQ_CONSTANT_T3_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T3_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T3_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T3_MASK \
+     (SQ_CONSTANT_T3_VALUE_MASK)
+
+#define SQ_CONSTANT_T3(value) \
+     ((value << SQ_CONSTANT_T3_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \
+     ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \
+     sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t3_t f;
+} sq_constant_t3_u;
+
+
+/*
+ * SQ_CF_BOOLEANS struct
+ */
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_BOOLEANS_MASK \
+     (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_booleans_t f;
+} sq_cf_booleans_u;
+
+
+/*
+ * SQ_CF_LOOP struct
+ */
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_START_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE   8
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT  16
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK  0x000000ff
+#define SQ_CF_LOOP_CF_LOOP_START_MASK  0x0000ff00
+#define SQ_CF_LOOP_CF_LOOP_STEP_MASK   0x00ff0000
+
+#define SQ_CF_LOOP_MASK \
+     (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_loop_t f;
+} sq_cf_loop_u;
+
+
+/*
+ * SQ_CONSTANT_RT_0 struct
+ */
+
+#define SQ_CONSTANT_RT_0_RED_SIZE      32
+
+#define SQ_CONSTANT_RT_0_RED_SHIFT     0
+
+#define SQ_CONSTANT_RT_0_RED_MASK      0xffffffff
+
+#define SQ_CONSTANT_RT_0_MASK \
+     (SQ_CONSTANT_RT_0_RED_MASK)
+
+#define SQ_CONSTANT_RT_0(red) \
+     ((red << SQ_CONSTANT_RT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \
+     ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \
+     sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_0_t f;
+} sq_constant_rt_0_u;
+
+
+/*
+ * SQ_CONSTANT_RT_1 struct
+ */
+
+#define SQ_CONSTANT_RT_1_GREEN_SIZE    32
+
+#define SQ_CONSTANT_RT_1_GREEN_SHIFT   0
+
+#define SQ_CONSTANT_RT_1_GREEN_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_1_MASK \
+     (SQ_CONSTANT_RT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_RT_1(green) \
+     ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \
+     ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \
+     sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_1_t f;
+} sq_constant_rt_1_u;
+
+
+/*
+ * SQ_CONSTANT_RT_2 struct
+ */
+
+#define SQ_CONSTANT_RT_2_BLUE_SIZE     32
+
+#define SQ_CONSTANT_RT_2_BLUE_SHIFT    0
+
+#define SQ_CONSTANT_RT_2_BLUE_MASK     0xffffffff
+
+#define SQ_CONSTANT_RT_2_MASK \
+     (SQ_CONSTANT_RT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_RT_2(blue) \
+     ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \
+     ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \
+     sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_2_t f;
+} sq_constant_rt_2_u;
+
+
+/*
+ * SQ_CONSTANT_RT_3 struct
+ */
+
+#define SQ_CONSTANT_RT_3_ALPHA_SIZE    32
+
+#define SQ_CONSTANT_RT_3_ALPHA_SHIFT   0
+
+#define SQ_CONSTANT_RT_3_ALPHA_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_3_MASK \
+     (SQ_CONSTANT_RT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_RT_3(alpha) \
+     ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \
+     ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \
+     sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_3_t f;
+} sq_constant_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_0 struct
+ */
+
+#define SQ_FETCH_RT_0_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_0_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_0_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_0_MASK \
+     (SQ_FETCH_RT_0_VALUE_MASK)
+
+#define SQ_FETCH_RT_0(value) \
+     ((value << SQ_FETCH_RT_0_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \
+     ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \
+     sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_0_t f;
+} sq_fetch_rt_0_u;
+
+
+/*
+ * SQ_FETCH_RT_1 struct
+ */
+
+#define SQ_FETCH_RT_1_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_1_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_1_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_1_MASK \
+     (SQ_FETCH_RT_1_VALUE_MASK)
+
+#define SQ_FETCH_RT_1(value) \
+     ((value << SQ_FETCH_RT_1_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \
+     ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \
+     sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_1_t f;
+} sq_fetch_rt_1_u;
+
+
+/*
+ * SQ_FETCH_RT_2 struct
+ */
+
+#define SQ_FETCH_RT_2_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_2_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_2_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_2_MASK \
+     (SQ_FETCH_RT_2_VALUE_MASK)
+
+#define SQ_FETCH_RT_2(value) \
+     ((value << SQ_FETCH_RT_2_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \
+     ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \
+     sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_2_t f;
+} sq_fetch_rt_2_u;
+
+
+/*
+ * SQ_FETCH_RT_3 struct
+ */
+
+#define SQ_FETCH_RT_3_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_3_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_3_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_3_MASK \
+     (SQ_FETCH_RT_3_VALUE_MASK)
+
+#define SQ_FETCH_RT_3(value) \
+     ((value << SQ_FETCH_RT_3_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \
+     ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \
+     sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_3_t f;
+} sq_fetch_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_4 struct
+ */
+
+#define SQ_FETCH_RT_4_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_4_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_4_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_4_MASK \
+     (SQ_FETCH_RT_4_VALUE_MASK)
+
+#define SQ_FETCH_RT_4(value) \
+     ((value << SQ_FETCH_RT_4_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \
+     ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \
+     sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_4_t f;
+} sq_fetch_rt_4_u;
+
+
+/*
+ * SQ_FETCH_RT_5 struct
+ */
+
+#define SQ_FETCH_RT_5_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_5_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_5_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_5_MASK \
+     (SQ_FETCH_RT_5_VALUE_MASK)
+
+#define SQ_FETCH_RT_5(value) \
+     ((value << SQ_FETCH_RT_5_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \
+     ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \
+     sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_5_t f;
+} sq_fetch_rt_5_u;
+
+
+/*
+ * SQ_CF_RT_BOOLEANS struct
+ */
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_RT_BOOLEANS_MASK \
+     (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_booleans_t f;
+} sq_cf_rt_booleans_u;
+
+
+/*
+ * SQ_CF_RT_LOOP struct
+ */
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff
+#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000
+
+#define SQ_CF_RT_LOOP_MASK \
+     (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_rt_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_rt_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_loop_t f;
+} sq_cf_rt_loop_u;
+
+
+/*
+ * SQ_VS_PROGRAM struct
+ */
+
+#define SQ_VS_PROGRAM_BASE_SIZE        12
+#define SQ_VS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_VS_PROGRAM_BASE_SHIFT       0
+#define SQ_VS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_VS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_VS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_VS_PROGRAM_MASK \
+     (SQ_VS_PROGRAM_BASE_MASK | \
+      SQ_VS_PROGRAM_SIZE_MASK)
+
+#define SQ_VS_PROGRAM(base, size) \
+     ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_VS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_vs_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+     } sq_vs_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_program_t f;
+} sq_vs_program_u;
+
+
+/*
+ * SQ_PS_PROGRAM struct
+ */
+
+#define SQ_PS_PROGRAM_BASE_SIZE        12
+#define SQ_PS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_PS_PROGRAM_BASE_SHIFT       0
+#define SQ_PS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_PS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_PS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_PS_PROGRAM_MASK \
+     (SQ_PS_PROGRAM_BASE_MASK | \
+      SQ_PS_PROGRAM_SIZE_MASK)
+
+#define SQ_PS_PROGRAM(base, size) \
+     ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_PS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_ps_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+     } sq_ps_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_program_t f;
+} sq_ps_program_u;
+
+
+/*
+ * SQ_CF_PROGRAM_SIZE struct
+ */
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000
+
+#define SQ_CF_PROGRAM_SIZE_MASK \
+     (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \
+      SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK)
+
+#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \
+     ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \
+      (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT))
+
+#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 9;
+     } sq_cf_program_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int                                : 9;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+     } sq_cf_program_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_program_size_t f;
+} sq_cf_program_size_u;
+
+
+/*
+ * SQ_INTERPOLATOR_CNTL struct
+ */
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000
+
+#define SQ_INTERPOLATOR_CNTL_MASK \
+     (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \
+      SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK)
+
+#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \
+     ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \
+      (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT))
+
+#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+     } sq_interpolator_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+     } sq_interpolator_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_interpolator_cntl_t f;
+} sq_interpolator_cntl_u;
+
+
+/*
+ * SQ_PROGRAM_CNTL struct
+ */
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000
+#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000
+
+#define SQ_PROGRAM_CNTL_MASK \
+     (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK)
+
+#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \
+     ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \
+      (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \
+      (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \
+      (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \
+      (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \
+      (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \
+      (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \
+      (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \
+      (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \
+      (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT))
+
+#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+     } sq_program_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+     } sq_program_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_program_cntl_t f;
+} sq_program_cntl_u;
+
+
+/*
+ * SQ_WRAPPING_0 struct
+ */
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f
+#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0
+#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00
+#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000
+#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000
+#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000
+#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000
+#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000
+
+#define SQ_WRAPPING_0_MASK \
+     (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_7_MASK)
+
+#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \
+     ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \
+      (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \
+      (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \
+      (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \
+      (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \
+      (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \
+      (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \
+      (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT))
+
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+     } sq_wrapping_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+     } sq_wrapping_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_0_t f;
+} sq_wrapping_0_u;
+
+
+/*
+ * SQ_WRAPPING_1 struct
+ */
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f
+#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0
+#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00
+#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000
+#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000
+#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000
+#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000
+#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000
+
+#define SQ_WRAPPING_1_MASK \
+     (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_15_MASK)
+
+#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \
+     ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \
+      (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \
+      (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \
+      (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \
+      (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \
+      (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \
+      (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \
+      (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT))
+
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+     } sq_wrapping_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+     } sq_wrapping_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_1_t f;
+} sq_wrapping_1_u;
+
+
+/*
+ * SQ_VS_CONST struct
+ */
+
+#define SQ_VS_CONST_BASE_SIZE          9
+#define SQ_VS_CONST_SIZE_SIZE          9
+
+#define SQ_VS_CONST_BASE_SHIFT         0
+#define SQ_VS_CONST_SIZE_SHIFT         12
+
+#define SQ_VS_CONST_BASE_MASK          0x000001ff
+#define SQ_VS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_VS_CONST_MASK \
+     (SQ_VS_CONST_BASE_MASK | \
+      SQ_VS_CONST_SIZE_MASK)
+
+#define SQ_VS_CONST(base, size) \
+     ((base << SQ_VS_CONST_BASE_SHIFT) | \
+      (size << SQ_VS_CONST_SIZE_SHIFT))
+
+#define SQ_VS_CONST_GET_BASE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT)
+
+#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_vs_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+     } sq_vs_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_const_t f;
+} sq_vs_const_u;
+
+
+/*
+ * SQ_PS_CONST struct
+ */
+
+#define SQ_PS_CONST_BASE_SIZE          9
+#define SQ_PS_CONST_SIZE_SIZE          9
+
+#define SQ_PS_CONST_BASE_SHIFT         0
+#define SQ_PS_CONST_SIZE_SHIFT         12
+
+#define SQ_PS_CONST_BASE_MASK          0x000001ff
+#define SQ_PS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_PS_CONST_MASK \
+     (SQ_PS_CONST_BASE_MASK | \
+      SQ_PS_CONST_SIZE_MASK)
+
+#define SQ_PS_CONST(base, size) \
+     ((base << SQ_PS_CONST_BASE_SHIFT) | \
+      (size << SQ_PS_CONST_SIZE_SHIFT))
+
+#define SQ_PS_CONST_GET_BASE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT)
+
+#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_ps_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+     } sq_ps_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_const_t f;
+} sq_ps_const_u;
+
+
+/*
+ * SQ_CONTEXT_MISC struct
+ */
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000
+
+#define SQ_CONTEXT_MISC_MASK \
+     (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \
+      SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \
+      SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \
+      SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \
+      SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK)
+
+#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \
+     ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \
+      (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \
+      (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \
+      (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \
+      (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \
+      (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \
+      (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT))
+
+#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int                                : 4;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int                                : 13;
+     } sq_context_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int                                : 13;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int                                : 4;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+     } sq_context_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_context_misc_t f;
+} sq_context_misc_u;
+
+
+/*
+ * SQ_CF_RD_BASE struct
+ */
+
+#define SQ_CF_RD_BASE_RD_BASE_SIZE     3
+
+#define SQ_CF_RD_BASE_RD_BASE_SHIFT    0
+
+#define SQ_CF_RD_BASE_RD_BASE_MASK     0x00000007
+
+#define SQ_CF_RD_BASE_MASK \
+     (SQ_CF_RD_BASE_RD_BASE_MASK)
+
+#define SQ_CF_RD_BASE(rd_base) \
+     ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT))
+
+#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \
+     ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \
+     sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+          unsigned int                                : 29;
+     } sq_cf_rd_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int                                : 29;
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+     } sq_cf_rd_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rd_base_t f;
+} sq_cf_rd_base_u;
+
+
+/*
+ * SQ_DEBUG_MISC_0 struct
+ */
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000
+
+#define SQ_DEBUG_MISC_0_MASK \
+     (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK)
+
+#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \
+     ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \
+      (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \
+      (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \
+      (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT))
+
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+     } sq_debug_misc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+     } sq_debug_misc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_0_t f;
+} sq_debug_misc_0_u;
+
+
+/*
+ * SQ_DEBUG_MISC_1 struct
+ */
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000
+
+#define SQ_DEBUG_MISC_1_MASK \
+     (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \
+      SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \
+      SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \
+      SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK)
+
+#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \
+     ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \
+      (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \
+      (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \
+      (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT))
+
+#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int                                : 5;
+     } sq_debug_misc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int                                : 5;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+     } sq_debug_misc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_1_t f;
+} sq_debug_misc_1_u;
+
+
+#endif
+
+
+#if !defined (_SX_FIDDLE_H)
+#define _SX_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sx_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_TP_FIDDLE_H)
+#define _TP_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  tp_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * TC_CNTL_STATUS struct
+ */
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2
+#define TC_CNTL_STATUS_TC_BUSY_SIZE    1
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18
+#define TC_CNTL_STATUS_TC_BUSY_SHIFT   31
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000
+#define TC_CNTL_STATUS_TC_BUSY_MASK    0x80000000
+
+#define TC_CNTL_STATUS_MASK \
+     (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \
+      TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \
+      TC_CNTL_STATUS_TC_BUSY_MASK)
+
+#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \
+     ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \
+      (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \
+      (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT))
+
+#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+          unsigned int                                : 17;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+     } tc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 17;
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+     } tc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tc_cntl_status_t f;
+} tc_cntl_status_u;
+
+
+/*
+ * TCR_CHICKEN struct
+ */
+
+#define TCR_CHICKEN_SPARE_SIZE         32
+
+#define TCR_CHICKEN_SPARE_SHIFT        0
+
+#define TCR_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCR_CHICKEN_MASK \
+     (TCR_CHICKEN_SPARE_MASK)
+
+#define TCR_CHICKEN(spare) \
+     ((spare << TCR_CHICKEN_SPARE_SHIFT))
+
+#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \
+     ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT)
+
+#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \
+     tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_chicken_t f;
+} tcr_chicken_u;
+
+
+/*
+ * TCF_CHICKEN struct
+ */
+
+#define TCF_CHICKEN_SPARE_SIZE         32
+
+#define TCF_CHICKEN_SPARE_SHIFT        0
+
+#define TCF_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCF_CHICKEN_MASK \
+     (TCF_CHICKEN_SPARE_MASK)
+
+#define TCF_CHICKEN(spare) \
+     ((spare << TCF_CHICKEN_SPARE_SHIFT))
+
+#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \
+     ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT)
+
+#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \
+     tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_chicken_t f;
+} tcf_chicken_u;
+
+
+/*
+ * TCM_CHICKEN struct
+ */
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1
+#define TCM_CHICKEN_SPARE_SIZE         23
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8
+#define TCM_CHICKEN_SPARE_SHIFT        9
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100
+#define TCM_CHICKEN_SPARE_MASK         0xfffffe00
+
+#define TCM_CHICKEN_MASK \
+     (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \
+      TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \
+      TCM_CHICKEN_SPARE_MASK)
+
+#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \
+     ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \
+      (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \
+      (spare << TCM_CHICKEN_SPARE_SHIFT))
+
+#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT)
+
+#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+     } tcm_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+     } tcm_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_chicken_t f;
+} tcm_chicken_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER0_SELECT_MASK \
+     (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \
+     ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \
+     tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_select_t f;
+} tcr_perfcounter0_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER1_SELECT_MASK \
+     (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \
+     ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \
+     tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_select_t f;
+} tcr_perfcounter1_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_HI struct
+ */
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER0_HI_MASK \
+     (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \
+     ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \
+     tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_hi_t f;
+} tcr_perfcounter0_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_HI struct
+ */
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER1_HI_MASK \
+     (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \
+     ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \
+     tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_hi_t f;
+} tcr_perfcounter1_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_LOW struct
+ */
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER0_LOW_MASK \
+     (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \
+     ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \
+     tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_low_t f;
+} tcr_perfcounter0_low_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_LOW struct
+ */
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER1_LOW_MASK \
+     (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \
+     ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \
+     tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_low_t f;
+} tcr_perfcounter1_low_u;
+
+
+/*
+ * TP_TC_CLKGATE_CNTL struct
+ */
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038
+
+#define TP_TC_CLKGATE_CNTL_MASK \
+     (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \
+      TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK)
+
+#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \
+     ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \
+      (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT))
+
+#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int                                : 26;
+     } tp_tc_clkgate_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int                                : 26;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+     } tp_tc_clkgate_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp_tc_clkgate_cntl_t f;
+} tp_tc_clkgate_cntl_u;
+
+
+/*
+ * TPC_CNTL_STATUS struct
+ */
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BUSY_SIZE  1
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15
+#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17
+#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19
+#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22
+#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23
+#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25
+#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27
+#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30
+#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000
+#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000
+#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000
+#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000
+#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000
+#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000
+#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000
+#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000
+#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000
+#define TPC_CNTL_STATUS_TPC_BUSY_MASK  0x80000000
+
+#define TPC_CNTL_STATUS_MASK \
+     (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTR_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TF_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \
+      TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \
+      TPC_CNTL_STATUS_TPC_BUSY_MASK)
+
+#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \
+     ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \
+      (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \
+      (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \
+      (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \
+      (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \
+      (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \
+      (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \
+      (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \
+      (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \
+      (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \
+      (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \
+      (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \
+      (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \
+      (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \
+      (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \
+      (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \
+      (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \
+      (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \
+      (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \
+      (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \
+      (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \
+      (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \
+      (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT))
+
+#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_cntl_status_t f;
+} tpc_cntl_status_u;
+
+
+/*
+ * TPC_DEBUG0 struct
+ */
+
+#define TPC_DEBUG0_LOD_CNTL_SIZE       2
+#define TPC_DEBUG0_IC_CTR_SIZE         2
+#define TPC_DEBUG0_WALKER_CNTL_SIZE    4
+#define TPC_DEBUG0_ALIGNER_CNTL_SIZE   3
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1
+#define TPC_DEBUG0_WALKER_STATE_SIZE   10
+#define TPC_DEBUG0_ALIGNER_STATE_SIZE  2
+#define TPC_DEBUG0_REG_CLK_EN_SIZE     1
+#define TPC_DEBUG0_TPC_CLK_EN_SIZE     1
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE   1
+
+#define TPC_DEBUG0_LOD_CNTL_SHIFT      0
+#define TPC_DEBUG0_IC_CTR_SHIFT        2
+#define TPC_DEBUG0_WALKER_CNTL_SHIFT   4
+#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT  8
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12
+#define TPC_DEBUG0_WALKER_STATE_SHIFT  16
+#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26
+#define TPC_DEBUG0_REG_CLK_EN_SHIFT    29
+#define TPC_DEBUG0_TPC_CLK_EN_SHIFT    30
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT  31
+
+#define TPC_DEBUG0_LOD_CNTL_MASK       0x00000003
+#define TPC_DEBUG0_IC_CTR_MASK         0x0000000c
+#define TPC_DEBUG0_WALKER_CNTL_MASK    0x000000f0
+#define TPC_DEBUG0_ALIGNER_CNTL_MASK   0x00000700
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000
+#define TPC_DEBUG0_WALKER_STATE_MASK   0x03ff0000
+#define TPC_DEBUG0_ALIGNER_STATE_MASK  0x0c000000
+#define TPC_DEBUG0_REG_CLK_EN_MASK     0x20000000
+#define TPC_DEBUG0_TPC_CLK_EN_MASK     0x40000000
+#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK   0x80000000
+
+#define TPC_DEBUG0_MASK \
+     (TPC_DEBUG0_LOD_CNTL_MASK | \
+      TPC_DEBUG0_IC_CTR_MASK | \
+      TPC_DEBUG0_WALKER_CNTL_MASK | \
+      TPC_DEBUG0_ALIGNER_CNTL_MASK | \
+      TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \
+      TPC_DEBUG0_WALKER_STATE_MASK | \
+      TPC_DEBUG0_ALIGNER_STATE_MASK | \
+      TPC_DEBUG0_REG_CLK_EN_MASK | \
+      TPC_DEBUG0_TPC_CLK_EN_MASK | \
+      TPC_DEBUG0_SQ_TP_WAKEUP_MASK)
+
+#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \
+     ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \
+      (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \
+      (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \
+      (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \
+      (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \
+      (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \
+      (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \
+      (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \
+      (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \
+      (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT))
+
+#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 3;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+     } tpc_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+     } tpc_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug0_t f;
+} tpc_debug0_u;
+
+
+/*
+ * TPC_DEBUG1 struct
+ */
+
+#define TPC_DEBUG1_UNUSED_SIZE         1
+
+#define TPC_DEBUG1_UNUSED_SHIFT        0
+
+#define TPC_DEBUG1_UNUSED_MASK         0x00000001
+
+#define TPC_DEBUG1_MASK \
+     (TPC_DEBUG1_UNUSED_MASK)
+
+#define TPC_DEBUG1(unused) \
+     ((unused << TPC_DEBUG1_UNUSED_SHIFT))
+
+#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \
+     ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT)
+
+#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \
+     tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+          unsigned int                                : 31;
+     } tpc_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int                                : 31;
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+     } tpc_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug1_t f;
+} tpc_debug1_u;
+
+
+/*
+ * TPC_CHICKEN struct
+ */
+
+#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1
+#define TPC_CHICKEN_SPARE_SIZE         31
+
+#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0
+#define TPC_CHICKEN_SPARE_SHIFT        1
+
+#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001
+#define TPC_CHICKEN_SPARE_MASK         0xfffffffe
+
+#define TPC_CHICKEN_MASK \
+     (TPC_CHICKEN_BLEND_PRECISION_MASK | \
+      TPC_CHICKEN_SPARE_MASK)
+
+#define TPC_CHICKEN(blend_precision, spare) \
+     ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \
+      (spare << TPC_CHICKEN_SPARE_SHIFT))
+
+#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT)
+
+#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+     } tpc_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+     } tpc_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_chicken_t f;
+} tpc_chicken_u;
+
+
+/*
+ * TP0_CNTL_STATUS struct
+ */
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1
+#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TP_BUSY_SIZE   1
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14
+#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16
+#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17
+#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18
+#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19
+#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21
+#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23
+#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25
+#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27
+#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29
+#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30
+#define TP0_CNTL_STATUS_TP_BUSY_SHIFT  31
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200
+#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000
+#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000
+#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000
+#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000
+#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000
+#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000
+#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000
+#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000
+#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000
+#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000
+#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000
+#define TP0_CNTL_STATUS_TP_BUSY_MASK   0x80000000
+
+#define TP0_CNTL_STATUS_MASK \
+     (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_IN_LC_RTS_MASK | \
+      TP0_CNTL_STATUS_LC_LA_RTS_MASK | \
+      TP0_CNTL_STATUS_LA_FL_RTS_MASK | \
+      TP0_CNTL_STATUS_FL_TA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \
+      TP0_CNTL_STATUS_TB_TO_RTS_MASK | \
+      TP0_CNTL_STATUS_TP_BUSY_MASK)
+
+#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \
+     ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \
+      (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \
+      (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \
+      (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \
+      (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \
+      (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \
+      (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \
+      (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \
+      (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \
+      (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \
+      (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \
+      (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \
+      (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \
+      (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \
+      (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \
+      (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \
+      (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \
+      (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \
+      (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \
+      (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \
+      (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \
+      (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \
+      (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \
+      (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \
+      (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \
+      (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \
+      (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \
+      (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \
+      (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \
+      (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT))
+
+#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_cntl_status_t f;
+} tp0_cntl_status_u;
+
+
+/*
+ * TP0_DEBUG struct
+ */
+
+#define TP0_DEBUG_Q_LOD_CNTL_SIZE      2
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE  1
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17
+#define TP0_DEBUG_REG_CLK_EN_SIZE      1
+#define TP0_DEBUG_PERF_CLK_EN_SIZE     1
+#define TP0_DEBUG_TP_CLK_EN_SIZE       1
+#define TP0_DEBUG_Q_WALKER_CNTL_SIZE   4
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE  3
+
+#define TP0_DEBUG_Q_LOD_CNTL_SHIFT     0
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4
+#define TP0_DEBUG_REG_CLK_EN_SHIFT     21
+#define TP0_DEBUG_PERF_CLK_EN_SHIFT    22
+#define TP0_DEBUG_TP_CLK_EN_SHIFT      23
+#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT  24
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28
+
+#define TP0_DEBUG_Q_LOD_CNTL_MASK      0x00000003
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK  0x00000008
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0
+#define TP0_DEBUG_REG_CLK_EN_MASK      0x00200000
+#define TP0_DEBUG_PERF_CLK_EN_MASK     0x00400000
+#define TP0_DEBUG_TP_CLK_EN_MASK       0x00800000
+#define TP0_DEBUG_Q_WALKER_CNTL_MASK   0x0f000000
+#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK  0x70000000
+
+#define TP0_DEBUG_MASK \
+     (TP0_DEBUG_Q_LOD_CNTL_MASK | \
+      TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \
+      TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \
+      TP0_DEBUG_REG_CLK_EN_MASK | \
+      TP0_DEBUG_PERF_CLK_EN_MASK | \
+      TP0_DEBUG_TP_CLK_EN_MASK | \
+      TP0_DEBUG_Q_WALKER_CNTL_MASK | \
+      TP0_DEBUG_Q_ALIGNER_CNTL_MASK)
+
+#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \
+     ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \
+      (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \
+      (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \
+      (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \
+      (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \
+      (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \
+      (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \
+      (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT))
+
+#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+     } tp0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int                                : 1;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+     } tp0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_debug_t f;
+} tp0_debug_u;
+
+
+/*
+ * TP0_CHICKEN struct
+ */
+
+#define TP0_CHICKEN_TT_MODE_SIZE       1
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1
+#define TP0_CHICKEN_SPARE_SIZE         30
+
+#define TP0_CHICKEN_TT_MODE_SHIFT      0
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1
+#define TP0_CHICKEN_SPARE_SHIFT        2
+
+#define TP0_CHICKEN_TT_MODE_MASK       0x00000001
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002
+#define TP0_CHICKEN_SPARE_MASK         0xfffffffc
+
+#define TP0_CHICKEN_MASK \
+     (TP0_CHICKEN_TT_MODE_MASK | \
+      TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \
+      TP0_CHICKEN_SPARE_MASK)
+
+#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \
+     ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \
+      (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \
+      (spare << TP0_CHICKEN_SPARE_SHIFT))
+
+#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT)
+
+#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+     } tp0_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+     } tp0_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_chicken_t f;
+} tp0_chicken_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER0_SELECT_MASK \
+     (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \
+     ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \
+     tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_select_t f;
+} tp0_perfcounter0_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_HI struct
+ */
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER0_HI_MASK \
+     (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \
+     ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \
+     tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_hi_t f;
+} tp0_perfcounter0_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_LOW struct
+ */
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER0_LOW_MASK \
+     (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \
+     ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \
+     tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_low_t f;
+} tp0_perfcounter0_low_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER1_SELECT_MASK \
+     (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \
+     ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \
+     tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_select_t f;
+} tp0_perfcounter1_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_HI struct
+ */
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER1_HI_MASK \
+     (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \
+     ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \
+     tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_hi_t f;
+} tp0_perfcounter1_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_LOW struct
+ */
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER1_LOW_MASK \
+     (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \
+     ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \
+     tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_low_t f;
+} tp0_perfcounter1_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER0_SELECT_MASK \
+     (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \
+     ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \
+     tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_select_t f;
+} tcm_perfcounter0_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER1_SELECT_MASK \
+     (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \
+     ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \
+     tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_select_t f;
+} tcm_perfcounter1_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_HI struct
+ */
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER0_HI_MASK \
+     (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \
+     ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \
+     tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_hi_t f;
+} tcm_perfcounter0_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_HI struct
+ */
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER1_HI_MASK \
+     (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \
+     ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \
+     tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_hi_t f;
+} tcm_perfcounter1_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_LOW struct
+ */
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER0_LOW_MASK \
+     (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \
+     ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \
+     tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_low_t f;
+} tcm_perfcounter0_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_LOW struct
+ */
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER1_LOW_MASK \
+     (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \
+     ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \
+     tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_low_t f;
+} tcm_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER0_SELECT_MASK \
+     (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \
+     ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \
+     tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_select_t f;
+} tcf_perfcounter0_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER1_SELECT_MASK \
+     (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \
+     ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \
+     tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_select_t f;
+} tcf_perfcounter1_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER2_SELECT_MASK \
+     (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \
+     ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \
+     tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_select_t f;
+} tcf_perfcounter2_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER3_SELECT_MASK \
+     (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \
+     ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \
+     tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_select_t f;
+} tcf_perfcounter3_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER4_SELECT_MASK \
+     (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \
+     ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \
+     tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter4_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter4_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_select_t f;
+} tcf_perfcounter4_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER5_SELECT_MASK \
+     (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \
+     ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \
+     tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter5_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter5_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_select_t f;
+} tcf_perfcounter5_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER6_SELECT_MASK \
+     (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \
+     ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \
+     tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter6_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter6_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_select_t f;
+} tcf_perfcounter6_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER7_SELECT_MASK \
+     (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \
+     ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \
+     tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter7_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter7_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_select_t f;
+} tcf_perfcounter7_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER8_SELECT_MASK \
+     (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \
+     ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \
+     tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter8_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter8_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_select_t f;
+} tcf_perfcounter8_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER9_SELECT_MASK \
+     (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \
+     ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \
+     tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter9_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter9_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_select_t f;
+} tcf_perfcounter9_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER10_SELECT_MASK \
+     (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \
+     ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \
+     tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter10_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter10_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_select_t f;
+} tcf_perfcounter10_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER11_SELECT_MASK \
+     (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \
+     ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \
+     tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter11_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter11_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_select_t f;
+} tcf_perfcounter11_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_HI struct
+ */
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER0_HI_MASK \
+     (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \
+     ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \
+     tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_hi_t f;
+} tcf_perfcounter0_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_HI struct
+ */
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER1_HI_MASK \
+     (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \
+     ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \
+     tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_hi_t f;
+} tcf_perfcounter1_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_HI struct
+ */
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER2_HI_MASK \
+     (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \
+     ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \
+     tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_hi_t f;
+} tcf_perfcounter2_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_HI struct
+ */
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER3_HI_MASK \
+     (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \
+     ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \
+     tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_hi_t f;
+} tcf_perfcounter3_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_HI struct
+ */
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER4_HI_MASK \
+     (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \
+     ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \
+     tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter4_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter4_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_hi_t f;
+} tcf_perfcounter4_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_HI struct
+ */
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER5_HI_MASK \
+     (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \
+     ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \
+     tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter5_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter5_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_hi_t f;
+} tcf_perfcounter5_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_HI struct
+ */
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER6_HI_MASK \
+     (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \
+     ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \
+     tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter6_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter6_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_hi_t f;
+} tcf_perfcounter6_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_HI struct
+ */
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER7_HI_MASK \
+     (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \
+     ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \
+     tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter7_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter7_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_hi_t f;
+} tcf_perfcounter7_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_HI struct
+ */
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER8_HI_MASK \
+     (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \
+     ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \
+     tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter8_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter8_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_hi_t f;
+} tcf_perfcounter8_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_HI struct
+ */
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER9_HI_MASK \
+     (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \
+     ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \
+     tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter9_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter9_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_hi_t f;
+} tcf_perfcounter9_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_HI struct
+ */
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER10_HI_MASK \
+     (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \
+     ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \
+     tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter10_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter10_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_hi_t f;
+} tcf_perfcounter10_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_HI struct
+ */
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER11_HI_MASK \
+     (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \
+     ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \
+     tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter11_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter11_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_hi_t f;
+} tcf_perfcounter11_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_LOW struct
+ */
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER0_LOW_MASK \
+     (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \
+     ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \
+     tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_low_t f;
+} tcf_perfcounter0_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_LOW struct
+ */
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER1_LOW_MASK \
+     (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \
+     ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \
+     tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_low_t f;
+} tcf_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_LOW struct
+ */
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER2_LOW_MASK \
+     (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \
+     ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \
+     tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_low_t f;
+} tcf_perfcounter2_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_LOW struct
+ */
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER3_LOW_MASK \
+     (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \
+     ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \
+     tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_low_t f;
+} tcf_perfcounter3_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_LOW struct
+ */
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER4_LOW_MASK \
+     (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \
+     ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \
+     tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_low_t f;
+} tcf_perfcounter4_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_LOW struct
+ */
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER5_LOW_MASK \
+     (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \
+     ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \
+     tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_low_t f;
+} tcf_perfcounter5_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_LOW struct
+ */
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER6_LOW_MASK \
+     (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \
+     ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \
+     tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_low_t f;
+} tcf_perfcounter6_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_LOW struct
+ */
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER7_LOW_MASK \
+     (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \
+     ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \
+     tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_low_t f;
+} tcf_perfcounter7_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_LOW struct
+ */
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER8_LOW_MASK \
+     (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \
+     ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \
+     tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_low_t f;
+} tcf_perfcounter8_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_LOW struct
+ */
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER9_LOW_MASK \
+     (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \
+     ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \
+     tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_low_t f;
+} tcf_perfcounter9_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_LOW struct
+ */
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER10_LOW_MASK \
+     (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \
+     ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \
+     tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_low_t f;
+} tcf_perfcounter10_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_LOW struct
+ */
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER11_LOW_MASK \
+     (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \
+     ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \
+     tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_low_t f;
+} tcf_perfcounter11_low_u;
+
+
+/*
+ * TCF_DEBUG struct
+ */
+
+#define TCF_DEBUG_not_MH_TC_rtr_SIZE   1
+#define TCF_DEBUG_TC_MH_send_SIZE      1
+#define TCF_DEBUG_not_FG0_rtr_SIZE     1
+#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1
+#define TCF_DEBUG_TCB_ff_stall_SIZE    1
+#define TCF_DEBUG_TCB_miss_stall_SIZE  1
+#define TCF_DEBUG_TCA_TCB_stall_SIZE   1
+#define TCF_DEBUG_PF0_stall_SIZE       1
+#define TCF_DEBUG_TP0_full_SIZE        1
+#define TCF_DEBUG_TPC_full_SIZE        1
+#define TCF_DEBUG_not_TPC_rtr_SIZE     1
+#define TCF_DEBUG_tca_state_rts_SIZE   1
+#define TCF_DEBUG_tca_rts_SIZE         1
+
+#define TCF_DEBUG_not_MH_TC_rtr_SHIFT  6
+#define TCF_DEBUG_TC_MH_send_SHIFT     7
+#define TCF_DEBUG_not_FG0_rtr_SHIFT    8
+#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12
+#define TCF_DEBUG_TCB_ff_stall_SHIFT   13
+#define TCF_DEBUG_TCB_miss_stall_SHIFT 14
+#define TCF_DEBUG_TCA_TCB_stall_SHIFT  15
+#define TCF_DEBUG_PF0_stall_SHIFT      16
+#define TCF_DEBUG_TP0_full_SHIFT       20
+#define TCF_DEBUG_TPC_full_SHIFT       24
+#define TCF_DEBUG_not_TPC_rtr_SHIFT    25
+#define TCF_DEBUG_tca_state_rts_SHIFT  26
+#define TCF_DEBUG_tca_rts_SHIFT        27
+
+#define TCF_DEBUG_not_MH_TC_rtr_MASK   0x00000040
+#define TCF_DEBUG_TC_MH_send_MASK      0x00000080
+#define TCF_DEBUG_not_FG0_rtr_MASK     0x00000100
+#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000
+#define TCF_DEBUG_TCB_ff_stall_MASK    0x00002000
+#define TCF_DEBUG_TCB_miss_stall_MASK  0x00004000
+#define TCF_DEBUG_TCA_TCB_stall_MASK   0x00008000
+#define TCF_DEBUG_PF0_stall_MASK       0x00010000
+#define TCF_DEBUG_TP0_full_MASK        0x00100000
+#define TCF_DEBUG_TPC_full_MASK        0x01000000
+#define TCF_DEBUG_not_TPC_rtr_MASK     0x02000000
+#define TCF_DEBUG_tca_state_rts_MASK   0x04000000
+#define TCF_DEBUG_tca_rts_MASK         0x08000000
+
+#define TCF_DEBUG_MASK \
+     (TCF_DEBUG_not_MH_TC_rtr_MASK | \
+      TCF_DEBUG_TC_MH_send_MASK | \
+      TCF_DEBUG_not_FG0_rtr_MASK | \
+      TCF_DEBUG_not_TCB_TCO_rtr_MASK | \
+      TCF_DEBUG_TCB_ff_stall_MASK | \
+      TCF_DEBUG_TCB_miss_stall_MASK | \
+      TCF_DEBUG_TCA_TCB_stall_MASK | \
+      TCF_DEBUG_PF0_stall_MASK | \
+      TCF_DEBUG_TP0_full_MASK | \
+      TCF_DEBUG_TPC_full_MASK | \
+      TCF_DEBUG_not_TPC_rtr_MASK | \
+      TCF_DEBUG_tca_state_rts_MASK | \
+      TCF_DEBUG_tca_rts_MASK)
+
+#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \
+     ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \
+      (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \
+      (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \
+      (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \
+      (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \
+      (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \
+      (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \
+      (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \
+      (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \
+      (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \
+      (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \
+      (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \
+      (tca_rts << TCF_DEBUG_tca_rts_SHIFT))
+
+#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_GET_TP0_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_GET_TPC_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_GET_tca_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT)
+
+#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 6;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int                                : 4;
+     } tcf_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 4;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int                                : 6;
+     } tcf_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_debug_t f;
+} tcf_debug_u;
+
+
+/*
+ * TCA_FIFO_DEBUG struct
+ */
+
+#define TCA_FIFO_DEBUG_tp0_full_SIZE   1
+#define TCA_FIFO_DEBUG_tpc_full_SIZE   1
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1
+#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1
+#define TCA_FIFO_DEBUG_FW_full_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1
+#define TCA_FIFO_DEBUG_FW_rts0_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1
+
+#define TCA_FIFO_DEBUG_tp0_full_SHIFT  0
+#define TCA_FIFO_DEBUG_tpc_full_SHIFT  4
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5
+#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6
+#define TCA_FIFO_DEBUG_FW_full_SHIFT   7
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8
+#define TCA_FIFO_DEBUG_FW_rts0_SHIFT   12
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17
+
+#define TCA_FIFO_DEBUG_tp0_full_MASK   0x00000001
+#define TCA_FIFO_DEBUG_tpc_full_MASK   0x00000010
+#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020
+#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040
+#define TCA_FIFO_DEBUG_FW_full_MASK    0x00000080
+#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100
+#define TCA_FIFO_DEBUG_FW_rts0_MASK    0x00001000
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000
+#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000
+
+#define TCA_FIFO_DEBUG_MASK \
+     (TCA_FIFO_DEBUG_tp0_full_MASK | \
+      TCA_FIFO_DEBUG_tpc_full_MASK | \
+      TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \
+      TCA_FIFO_DEBUG_load_tp_fifos_MASK | \
+      TCA_FIFO_DEBUG_FW_full_MASK | \
+      TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \
+      TCA_FIFO_DEBUG_FW_rts0_MASK | \
+      TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \
+      TCA_FIFO_DEBUG_FW_tpc_rts_MASK)
+
+#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \
+     ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \
+      (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \
+      (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \
+      (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \
+      (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \
+      (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \
+      (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \
+      (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \
+      (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT))
+
+#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int                                : 14;
+     } tca_fifo_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int                                : 14;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+     } tca_fifo_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_fifo_debug_t f;
+} tca_fifo_debug_u;
+
+
+/*
+ * TCA_PROBE_DEBUG struct
+ */
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001
+
+#define TCA_PROBE_DEBUG_MASK \
+     (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK)
+
+#define TCA_PROBE_DEBUG(probefilter_stall) \
+     ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT))
+
+#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \
+     ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \
+     tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+          unsigned int                                : 31;
+     } tca_probe_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int                                : 31;
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+     } tca_probe_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_probe_debug_t f;
+} tca_probe_debug_u;
+
+
+/*
+ * TCA_TPC_DEBUG struct
+ */
+
+#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1
+#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1
+
+#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12
+#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13
+
+#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000
+#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000
+
+#define TCA_TPC_DEBUG_MASK \
+     (TCA_TPC_DEBUG_captue_state_rts_MASK | \
+      TCA_TPC_DEBUG_capture_tca_rts_MASK)
+
+#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \
+     ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \
+      (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT))
+
+#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 12;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int                                : 18;
+     } tca_tpc_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 18;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int                                : 12;
+     } tca_tpc_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_tpc_debug_t f;
+} tca_tpc_debug_u;
+
+
+/*
+ * TCB_CORE_DEBUG struct
+ */
+
+#define TCB_CORE_DEBUG_access512_SIZE  1
+#define TCB_CORE_DEBUG_tiled_SIZE      1
+#define TCB_CORE_DEBUG_opcode_SIZE     3
+#define TCB_CORE_DEBUG_format_SIZE     6
+#define TCB_CORE_DEBUG_sector_format_SIZE 5
+#define TCB_CORE_DEBUG_sector_format512_SIZE 3
+
+#define TCB_CORE_DEBUG_access512_SHIFT 0
+#define TCB_CORE_DEBUG_tiled_SHIFT     1
+#define TCB_CORE_DEBUG_opcode_SHIFT    4
+#define TCB_CORE_DEBUG_format_SHIFT    8
+#define TCB_CORE_DEBUG_sector_format_SHIFT 16
+#define TCB_CORE_DEBUG_sector_format512_SHIFT 24
+
+#define TCB_CORE_DEBUG_access512_MASK  0x00000001
+#define TCB_CORE_DEBUG_tiled_MASK      0x00000002
+#define TCB_CORE_DEBUG_opcode_MASK     0x00000070
+#define TCB_CORE_DEBUG_format_MASK     0x00003f00
+#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000
+#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000
+
+#define TCB_CORE_DEBUG_MASK \
+     (TCB_CORE_DEBUG_access512_MASK | \
+      TCB_CORE_DEBUG_tiled_MASK | \
+      TCB_CORE_DEBUG_opcode_MASK | \
+      TCB_CORE_DEBUG_format_MASK | \
+      TCB_CORE_DEBUG_sector_format_MASK | \
+      TCB_CORE_DEBUG_sector_format512_MASK)
+
+#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \
+     ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \
+      (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \
+      (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \
+      (format << TCB_CORE_DEBUG_format_SHIFT) | \
+      (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \
+      (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT))
+
+#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int                                : 2;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 1;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 5;
+     } tcb_core_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int                                : 5;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 2;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+     } tcb_core_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_core_debug_t f;
+} tcb_core_debug_u;
+
+
+/*
+ * TCB_TAG0_DEBUG struct
+ */
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG0_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG0_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG0_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG0_DEBUG_MASK \
+     (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG0_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG0_DEBUG_miss_stall_MASK | \
+      TCB_TAG0_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG0_DEBUG_max_misses_MASK)
+
+#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+     } tcb_tag0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag0_debug_t f;
+} tcb_tag0_debug_u;
+
+
+/*
+ * TCB_TAG1_DEBUG struct
+ */
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG1_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG1_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG1_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG1_DEBUG_MASK \
+     (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG1_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG1_DEBUG_miss_stall_MASK | \
+      TCB_TAG1_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG1_DEBUG_max_misses_MASK)
+
+#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+     } tcb_tag1_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag1_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag1_debug_t f;
+} tcb_tag1_debug_u;
+
+
+/*
+ * TCB_TAG2_DEBUG struct
+ */
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG2_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG2_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG2_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG2_DEBUG_MASK \
+     (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG2_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG2_DEBUG_miss_stall_MASK | \
+      TCB_TAG2_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG2_DEBUG_max_misses_MASK)
+
+#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+     } tcb_tag2_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag2_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag2_debug_t f;
+} tcb_tag2_debug_u;
+
+
+/*
+ * TCB_TAG3_DEBUG struct
+ */
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG3_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG3_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG3_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG3_DEBUG_MASK \
+     (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG3_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG3_DEBUG_miss_stall_MASK | \
+      TCB_TAG3_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG3_DEBUG_max_misses_MASK)
+
+#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+     } tcb_tag3_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag3_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag3_debug_t f;
+} tcb_tag3_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \
+     (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \
+     ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \
+      (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \
+      (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \
+      (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \
+      (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \
+      (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \
+      (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \
+      (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT))
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int                                : 3;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int                                : 3;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_sector_walker0_debug_t f;
+} tcb_fetch_gen_sector_walker0_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_WALKER_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \
+     (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \
+     ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \
+      (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \
+      (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \
+      (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \
+      (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \
+      (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT))
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 4;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int                                : 12;
+     } tcb_fetch_gen_walker_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 12;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int                                : 4;
+     } tcb_fetch_gen_walker_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_walker_debug_t f;
+} tcb_fetch_gen_walker_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_PIPE0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \
+     (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \
+     ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \
+      (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \
+      (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \
+      (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \
+      (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \
+      (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \
+      (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \
+      (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \
+      (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \
+      (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \
+      (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT))
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_pipe0_debug_t f;
+} tcb_fetch_gen_pipe0_debug_u;
+
+
+/*
+ * TCD_INPUT0_DEBUG struct
+ */
+
+#define TCD_INPUT0_DEBUG_empty_SIZE    1
+#define TCD_INPUT0_DEBUG_full_SIZE     1
+#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_cnt_q1_SIZE   2
+#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_ip_send_SIZE  1
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1
+
+#define TCD_INPUT0_DEBUG_empty_SHIFT   16
+#define TCD_INPUT0_DEBUG_full_SHIFT    17
+#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20
+#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT  21
+#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23
+#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26
+
+#define TCD_INPUT0_DEBUG_empty_MASK    0x00010000
+#define TCD_INPUT0_DEBUG_full_MASK     0x00020000
+#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000
+#define TCD_INPUT0_DEBUG_cnt_q1_MASK   0x00600000
+#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000
+#define TCD_INPUT0_DEBUG_ip_send_MASK  0x01000000
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000
+#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000
+
+#define TCD_INPUT0_DEBUG_MASK \
+     (TCD_INPUT0_DEBUG_empty_MASK | \
+      TCD_INPUT0_DEBUG_full_MASK | \
+      TCD_INPUT0_DEBUG_valid_q1_MASK | \
+      TCD_INPUT0_DEBUG_cnt_q1_MASK | \
+      TCD_INPUT0_DEBUG_last_send_q1_MASK | \
+      TCD_INPUT0_DEBUG_ip_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_busy_MASK)
+
+#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \
+     ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \
+      (full << TCD_INPUT0_DEBUG_full_SHIFT) | \
+      (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \
+      (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \
+      (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \
+      (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \
+      (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \
+      (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT))
+
+#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 16;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int                                : 2;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int                                : 5;
+     } tcd_input0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 5;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int                                : 2;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int                                : 16;
+     } tcd_input0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_input0_debug_t f;
+} tcd_input0_debug_u;
+
+
+/*
+ * TCD_DEGAMMA_DEBUG struct
+ */
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040
+
+#define TCD_DEGAMMA_DEBUG_MASK \
+     (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK)
+
+#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \
+     ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \
+      (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \
+      (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \
+      (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \
+      (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \
+      (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT))
+
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int                                : 25;
+     } tcd_degamma_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int                                : 25;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+     } tcd_degamma_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_degamma_debug_t f;
+} tcd_degamma_debug_u;
+
+
+/*
+ * TCD_DXTMUX_SCTARB_DEBUG struct
+ */
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000
+
+#define TCD_DXTMUX_SCTARB_DEBUG_MASK \
+     (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK)
+
+#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \
+     ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \
+      (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \
+      (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \
+      (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \
+      (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \
+      (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \
+      (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \
+      (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \
+      (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT))
+
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 9;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int                                : 2;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 2;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int                                : 9;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtmux_sctarb_debug_t f;
+} tcd_dxtmux_sctarb_debug_u;
+
+
+/*
+ * TCD_DXTC_ARB_DEBUG struct
+ */
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4
+#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010
+#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000
+
+#define TCD_DXTC_ARB_DEBUG_MASK \
+     (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \
+      TCD_DXTC_ARB_DEBUG_pstate_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK)
+
+#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \
+     ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \
+      (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \
+      (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \
+      (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \
+      (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \
+      (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \
+      (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \
+      (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \
+      (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT))
+
+#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int                                : 4;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+     } tcd_dxtc_arb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int                                : 4;
+     } tcd_dxtc_arb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtc_arb_debug_t f;
+} tcd_dxtc_arb_debug_u;
+
+
+/*
+ * TCD_STALLS_DEBUG struct
+ */
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000
+#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000
+
+#define TCD_STALLS_DEBUG_MASK \
+     (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_incoming_rtr_MASK)
+
+#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \
+     ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \
+      (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \
+      (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \
+      (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \
+      (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \
+      (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT))
+
+#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int                                : 10;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+     } tcd_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int                                : 10;
+     } tcd_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_stalls_debug_t f;
+} tcd_stalls_debug_u;
+
+
+/*
+ * TCO_STALLS_DEBUG struct
+ */
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080
+
+#define TCO_STALLS_DEBUG_MASK \
+     (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK)
+
+#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \
+     ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \
+      (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \
+      (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT))
+
+#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 5;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int                                : 24;
+     } tco_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 24;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int                                : 5;
+     } tco_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_stalls_debug_t f;
+} tco_stalls_debug_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG0 struct
+ */
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1
+#define TCO_QUAD0_DEBUG0_busy_SIZE     1
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16
+#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29
+#define TCO_QUAD0_DEBUG0_busy_SHIFT    30
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000
+#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000
+#define TCO_QUAD0_DEBUG0_busy_MASK     0x40000000
+
+#define TCO_QUAD0_DEBUG0_MASK \
+     (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \
+      TCO_QUAD0_DEBUG0_read_cache_q_MASK | \
+      TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \
+      TCO_QUAD0_DEBUG0_busy_MASK)
+
+#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \
+     ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \
+      (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \
+      (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \
+      (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \
+      (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \
+      (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \
+      (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \
+      (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \
+      (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \
+      (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \
+      (busy << TCO_QUAD0_DEBUG0_busy_SHIFT))
+
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int                                : 2;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int                                : 1;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 2;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+     } tco_quad0_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug0_t f;
+} tco_quad0_debug0_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG1 struct
+ */
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_empty_SIZE    1
+#define TCO_QUAD0_DEBUG1_full_SIZE     1
+#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0
+#define TCO_QUAD0_DEBUG1_empty_SHIFT   1
+#define TCO_QUAD0_DEBUG1_full_SHIFT    2
+#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001
+#define TCO_QUAD0_DEBUG1_empty_MASK    0x00000002
+#define TCO_QUAD0_DEBUG1_full_MASK     0x00000004
+#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800
+#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000
+#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000
+
+#define TCO_QUAD0_DEBUG1_MASK \
+     (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_empty_MASK | \
+      TCO_QUAD0_DEBUG1_full_MASK | \
+      TCO_QUAD0_DEBUG1_write_enable_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \
+      TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \
+      TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK)
+
+#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \
+     ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \
+      (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \
+      (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \
+      (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \
+      (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \
+      (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \
+      (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \
+      (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \
+      (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \
+      (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \
+      (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \
+      (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \
+      (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT))
+
+#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int                                : 2;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int                                : 1;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int                                : 2;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+     } tco_quad0_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug1_t f;
+} tco_quad0_debug1_u;
+
+
+#endif
+
+
+#if !defined (_TC_FIDDLE_H)
+#define _TC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  tc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_SC_FIDDLE_H)
+#define _SC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_BC_FIDDLE_H)
+#define _BC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  bc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * RB_SURFACE_INFO struct
+ */
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff
+#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000
+
+#define RB_SURFACE_INFO_MASK \
+     (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \
+      RB_SURFACE_INFO_MSAA_SAMPLES_MASK)
+
+#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \
+     ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \
+      (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT))
+
+#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int                                : 16;
+     } rb_surface_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int                                : 16;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+     } rb_surface_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_surface_info_t f;
+} rb_surface_info_u;
+
+
+/*
+ * RB_COLOR_INFO struct
+ */
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2
+#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1
+#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2
+#define RB_COLOR_INFO_COLOR_SWAP_SIZE  2
+#define RB_COLOR_INFO_COLOR_BASE_SIZE  20
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4
+#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6
+#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7
+#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9
+#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12
+
+#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030
+#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040
+#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180
+#define RB_COLOR_INFO_COLOR_SWAP_MASK  0x00000600
+#define RB_COLOR_INFO_COLOR_BASE_MASK  0xfffff000
+
+#define RB_COLOR_INFO_MASK \
+     (RB_COLOR_INFO_COLOR_FORMAT_MASK | \
+      RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \
+      RB_COLOR_INFO_COLOR_LINEAR_MASK | \
+      RB_COLOR_INFO_COLOR_ENDIAN_MASK | \
+      RB_COLOR_INFO_COLOR_SWAP_MASK | \
+      RB_COLOR_INFO_COLOR_BASE_MASK)
+
+#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \
+     ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \
+      (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \
+      (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \
+      (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \
+      (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \
+      (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT))
+
+#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+     } rb_color_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+     } rb_color_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_info_t f;
+} rb_color_info_u;
+
+
+/*
+ * RB_DEPTH_INFO struct
+ */
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1
+#define RB_DEPTH_INFO_DEPTH_BASE_SIZE  20
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0
+#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001
+#define RB_DEPTH_INFO_DEPTH_BASE_MASK  0xfffff000
+
+#define RB_DEPTH_INFO_MASK \
+     (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \
+      RB_DEPTH_INFO_DEPTH_BASE_MASK)
+
+#define RB_DEPTH_INFO(depth_format, depth_base) \
+     ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \
+      (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT))
+
+#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+     } rb_depth_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+     } rb_depth_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_info_t f;
+} rb_depth_info_u;
+
+
+/*
+ * RB_STENCILREFMASK struct
+ */
+
+#define RB_STENCILREFMASK_STENCILREF_SIZE 8
+#define RB_STENCILREFMASK_STENCILMASK_SIZE 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8
+
+#define RB_STENCILREFMASK_STENCILREF_SHIFT 0
+#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16
+
+#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff
+#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00
+#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000
+
+#define RB_STENCILREFMASK_MASK \
+     (RB_STENCILREFMASK_STENCILREF_MASK | \
+      RB_STENCILREFMASK_STENCILMASK_MASK | \
+      RB_STENCILREFMASK_STENCILWRITEMASK_MASK)
+
+#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask) \
+     ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \
+      (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \
+      (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT))
+
+#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+
+#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int                                : 8;
+     } rb_stencilrefmask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int                                : 8;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+     } rb_stencilrefmask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_t f;
+} rb_stencilrefmask_u;
+
+
+/*
+ * RB_ALPHA_REF struct
+ */
+
+#define RB_ALPHA_REF_ALPHA_REF_SIZE    32
+
+#define RB_ALPHA_REF_ALPHA_REF_SHIFT   0
+
+#define RB_ALPHA_REF_ALPHA_REF_MASK    0xffffffff
+
+#define RB_ALPHA_REF_MASK \
+     (RB_ALPHA_REF_ALPHA_REF_MASK)
+
+#define RB_ALPHA_REF(alpha_ref) \
+     ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT))
+
+#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \
+     ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \
+     rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_alpha_ref_t f;
+} rb_alpha_ref_u;
+
+
+/*
+ * RB_COLOR_MASK struct
+ */
+
+#define RB_COLOR_MASK_WRITE_RED_SIZE   1
+#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1
+#define RB_COLOR_MASK_WRITE_BLUE_SIZE  1
+#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1
+
+#define RB_COLOR_MASK_WRITE_RED_SHIFT  0
+#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1
+#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2
+#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3
+
+#define RB_COLOR_MASK_WRITE_RED_MASK   0x00000001
+#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002
+#define RB_COLOR_MASK_WRITE_BLUE_MASK  0x00000004
+#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008
+
+#define RB_COLOR_MASK_MASK \
+     (RB_COLOR_MASK_WRITE_RED_MASK | \
+      RB_COLOR_MASK_WRITE_GREEN_MASK | \
+      RB_COLOR_MASK_WRITE_BLUE_MASK | \
+      RB_COLOR_MASK_WRITE_ALPHA_MASK)
+
+#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha) \
+     ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \
+      (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \
+      (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \
+      (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT))
+
+#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+
+#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int                                : 28;
+     } rb_color_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int                                : 28;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+     } rb_color_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_mask_t f;
+} rb_color_mask_u;
+
+
+/*
+ * RB_BLEND_RED struct
+ */
+
+#define RB_BLEND_RED_BLEND_RED_SIZE    8
+
+#define RB_BLEND_RED_BLEND_RED_SHIFT   0
+
+#define RB_BLEND_RED_BLEND_RED_MASK    0x000000ff
+
+#define RB_BLEND_RED_MASK \
+     (RB_BLEND_RED_BLEND_RED_MASK)
+
+#define RB_BLEND_RED(blend_red) \
+     ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT))
+
+#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \
+     ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \
+     rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_red_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int                                : 24;
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+     } rb_blend_red_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_red_t f;
+} rb_blend_red_u;
+
+
+/*
+ * RB_BLEND_GREEN struct
+ */
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0
+
+#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff
+
+#define RB_BLEND_GREEN_MASK \
+     (RB_BLEND_GREEN_BLEND_GREEN_MASK)
+
+#define RB_BLEND_GREEN(blend_green) \
+     ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT))
+
+#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \
+     ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \
+     rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_green_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int                                : 24;
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+     } rb_blend_green_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_green_t f;
+} rb_blend_green_u;
+
+
+/*
+ * RB_BLEND_BLUE struct
+ */
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SIZE  8
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0
+
+#define RB_BLEND_BLUE_BLEND_BLUE_MASK  0x000000ff
+
+#define RB_BLEND_BLUE_MASK \
+     (RB_BLEND_BLUE_BLEND_BLUE_MASK)
+
+#define RB_BLEND_BLUE(blend_blue) \
+     ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT))
+
+#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \
+     ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \
+     rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_blue_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int                                : 24;
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+     } rb_blend_blue_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_blue_t f;
+} rb_blend_blue_u;
+
+
+/*
+ * RB_BLEND_ALPHA struct
+ */
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff
+
+#define RB_BLEND_ALPHA_MASK \
+     (RB_BLEND_ALPHA_BLEND_ALPHA_MASK)
+
+#define RB_BLEND_ALPHA(blend_alpha) \
+     ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT))
+
+#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \
+     ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \
+     rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_alpha_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int                                : 24;
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+     } rb_blend_alpha_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_alpha_t f;
+} rb_blend_alpha_u;
+
+
+/*
+ * RB_FOG_COLOR struct
+ */
+
+#define RB_FOG_COLOR_FOG_RED_SIZE      8
+#define RB_FOG_COLOR_FOG_GREEN_SIZE    8
+#define RB_FOG_COLOR_FOG_BLUE_SIZE     8
+
+#define RB_FOG_COLOR_FOG_RED_SHIFT     0
+#define RB_FOG_COLOR_FOG_GREEN_SHIFT   8
+#define RB_FOG_COLOR_FOG_BLUE_SHIFT    16
+
+#define RB_FOG_COLOR_FOG_RED_MASK      0x000000ff
+#define RB_FOG_COLOR_FOG_GREEN_MASK    0x0000ff00
+#define RB_FOG_COLOR_FOG_BLUE_MASK     0x00ff0000
+
+#define RB_FOG_COLOR_MASK \
+     (RB_FOG_COLOR_FOG_RED_MASK | \
+      RB_FOG_COLOR_FOG_GREEN_MASK | \
+      RB_FOG_COLOR_FOG_BLUE_MASK)
+
+#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \
+     ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \
+      (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \
+      (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT))
+
+#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int                                : 8;
+     } rb_fog_color_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int                                : 8;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+     } rb_fog_color_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_fog_color_t f;
+} rb_fog_color_u;
+
+
+/*
+ * RB_STENCILREFMASK_BF struct
+ */
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000
+
+#define RB_STENCILREFMASK_BF_MASK \
+     (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK)
+
+#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf) \
+     ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \
+      (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \
+      (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT))
+
+#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+
+#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int                                : 8;
+     } rb_stencilrefmask_bf_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int                                : 8;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+     } rb_stencilrefmask_bf_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_bf_t f;
+} rb_stencilrefmask_bf_u;
+
+
+/*
+ * RB_DEPTHCONTROL struct
+ */
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_Z_ENABLE_SIZE  1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_ZFUNC_SIZE     3
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0
+#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3
+#define RB_DEPTHCONTROL_ZFUNC_SHIFT    4
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7
+#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8
+#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11
+#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14
+#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001
+#define RB_DEPTHCONTROL_Z_ENABLE_MASK  0x00000002
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008
+#define RB_DEPTHCONTROL_ZFUNC_MASK     0x00000070
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080
+#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700
+#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800
+#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000
+#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000
+
+#define RB_DEPTHCONTROL_MASK \
+     (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_ZFUNC_MASK | \
+      RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK)
+
+#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \
+     ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \
+      (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \
+      (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \
+      (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \
+      (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \
+      (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \
+      (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \
+      (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \
+      (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \
+      (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \
+      (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \
+      (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \
+      (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \
+      (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT))
+
+#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+     } rb_depthcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+     } rb_depthcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depthcontrol_t f;
+} rb_depthcontrol_u;
+
+
+/*
+ * RB_BLENDCONTROL struct
+ */
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1
+#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29
+#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000
+#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000
+
+#define RB_BLENDCONTROL_MASK \
+     (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_MASK)
+
+#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \
+     ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \
+      (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \
+      (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \
+      (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \
+      (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \
+      (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \
+      (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \
+      (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT))
+
+#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int                                : 1;
+     } rb_blendcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int                                : 1;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+     } rb_blendcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blendcontrol_t f;
+} rb_blendcontrol_u;
+
+
+/*
+ * RB_COLORCONTROL struct
+ */
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1
+#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1
+#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1
+#define RB_COLORCONTROL_ROP_CODE_SIZE  4
+#define RB_COLORCONTROL_DITHER_MODE_SIZE 2
+#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2
+#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4
+#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5
+#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7
+#define RB_COLORCONTROL_ROP_CODE_SHIFT 8
+#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12
+#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14
+#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30
+
+#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010
+#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020
+#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080
+#define RB_COLORCONTROL_ROP_CODE_MASK  0x00000f00
+#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000
+#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000
+#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000
+
+#define RB_COLORCONTROL_MASK \
+     (RB_COLORCONTROL_ALPHA_FUNC_MASK | \
+      RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \
+      RB_COLORCONTROL_BLEND_DISABLE_MASK | \
+      RB_COLORCONTROL_FOG_ENABLE_MASK | \
+      RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \
+      RB_COLORCONTROL_ROP_CODE_MASK | \
+      RB_COLORCONTROL_DITHER_MODE_MASK | \
+      RB_COLORCONTROL_DITHER_TYPE_MASK | \
+      RB_COLORCONTROL_PIXEL_FOG_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK)
+
+#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \
+     ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \
+      (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \
+      (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \
+      (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \
+      (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \
+      (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \
+      (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \
+      (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \
+      (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \
+      (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \
+      (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \
+      (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \
+      (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \
+      (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT))
+
+#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int                                : 7;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+     } rb_colorcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int                                : 7;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+     } rb_colorcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_colorcontrol_t f;
+} rb_colorcontrol_u;
+
+
+/*
+ * RB_MODECONTROL struct
+ */
+
+#define RB_MODECONTROL_EDRAM_MODE_SIZE 3
+
+#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0
+
+#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007
+
+#define RB_MODECONTROL_MASK \
+     (RB_MODECONTROL_EDRAM_MODE_MASK)
+
+#define RB_MODECONTROL(edram_mode) \
+     ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT))
+
+#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \
+     ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \
+     rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+          unsigned int                                : 29;
+     } rb_modecontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int                                : 29;
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+     } rb_modecontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_modecontrol_t f;
+} rb_modecontrol_u;
+
+
+/*
+ * RB_COLOR_DEST_MASK struct
+ */
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff
+
+#define RB_COLOR_DEST_MASK_MASK \
+     (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK)
+
+#define RB_COLOR_DEST_MASK(color_dest_mask) \
+     ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT))
+
+#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \
+     ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \
+     rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_dest_mask_t f;
+} rb_color_dest_mask_u;
+
+
+/*
+ * RB_COPY_CONTROL struct
+ */
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1
+#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3
+#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008
+#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0
+
+#define RB_COPY_CONTROL_MASK \
+     (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \
+      RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \
+      RB_COPY_CONTROL_CLEAR_MASK_MASK)
+
+#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \
+     ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \
+      (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \
+      (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT))
+
+#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int                                : 24;
+     } rb_copy_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int                                : 24;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+     } rb_copy_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_control_t f;
+} rb_copy_control_u;
+
+
+/*
+ * RB_COPY_DEST_BASE struct
+ */
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000
+
+#define RB_COPY_DEST_BASE_MASK \
+     (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK)
+
+#define RB_COPY_DEST_BASE(copy_dest_base) \
+     ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT))
+
+#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \
+     ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \
+     rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int                                : 12;
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+     } rb_copy_dest_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+          unsigned int                                : 12;
+     } rb_copy_dest_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_base_t f;
+} rb_copy_dest_base_u;
+
+
+/*
+ * RB_COPY_DEST_PITCH struct
+ */
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff
+
+#define RB_COPY_DEST_PITCH_MASK \
+     (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK)
+
+#define RB_COPY_DEST_PITCH(copy_dest_pitch) \
+     ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT))
+
+#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \
+     ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \
+     rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+          unsigned int                                : 23;
+     } rb_copy_dest_pitch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int                                : 23;
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+     } rb_copy_dest_pitch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pitch_t f;
+} rb_copy_dest_pitch_u;
+
+
+/*
+ * RB_COPY_DEST_INFO struct
+ */
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000
+
+#define RB_COPY_DEST_INFO_MASK \
+     (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK)
+
+#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \
+     ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \
+      (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \
+      (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \
+      (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \
+      (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \
+      (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \
+      (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \
+      (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \
+      (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \
+      (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT))
+
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int                                : 14;
+     } rb_copy_dest_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int                                : 14;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+     } rb_copy_dest_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_info_t f;
+} rb_copy_dest_info_u;
+
+
+/*
+ * RB_COPY_DEST_PIXEL_OFFSET struct
+ */
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000
+
+#define RB_COPY_DEST_PIXEL_OFFSET_MASK \
+     (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \
+      RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK)
+
+#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \
+     ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \
+      (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT))
+
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int                                : 6;
+     } rb_copy_dest_pixel_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int                                : 6;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+     } rb_copy_dest_pixel_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pixel_offset_t f;
+} rb_copy_dest_pixel_offset_u;
+
+
+/*
+ * RB_DEPTH_CLEAR struct
+ */
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff
+
+#define RB_DEPTH_CLEAR_MASK \
+     (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK)
+
+#define RB_DEPTH_CLEAR(depth_clear) \
+     ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT))
+
+#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \
+     ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \
+     rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_clear_t f;
+} rb_depth_clear_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_CTL struct
+ */
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002
+
+#define RB_SAMPLE_COUNT_CTL_MASK \
+     (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \
+      RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK)
+
+#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \
+     ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \
+      (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT))
+
+#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int                                : 30;
+     } rb_sample_count_ctl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int                                : 30;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+     } rb_sample_count_ctl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_ctl_t f;
+} rb_sample_count_ctl_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_ADDR struct
+ */
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff
+
+#define RB_SAMPLE_COUNT_ADDR_MASK \
+     (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK)
+
+#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \
+     ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT))
+
+#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \
+     ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \
+     rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_addr_t f;
+} rb_sample_count_addr_u;
+
+
+/*
+ * RB_BC_CONTROL struct
+ */
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1
+#define RB_BC_CONTROL_CRC_MODE_SIZE    1
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1
+#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_RESERVED9_SIZE   1
+#define RB_BC_CONTROL_RESERVED10_SIZE  1
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14
+#define RB_BC_CONTROL_CRC_MODE_SHIFT   15
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16
+#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29
+#define RB_BC_CONTROL_RESERVED9_SHIFT  30
+#define RB_BC_CONTROL_RESERVED10_SHIFT 31
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000
+#define RB_BC_CONTROL_CRC_MODE_MASK    0x00008000
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000
+#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000
+#define RB_BC_CONTROL_RESERVED9_MASK   0x40000000
+#define RB_BC_CONTROL_RESERVED10_MASK  0x80000000
+
+#define RB_BC_CONTROL_MASK \
+     (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \
+      RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \
+      RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \
+      RB_BC_CONTROL_CRC_MODE_MASK | \
+      RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \
+      RB_BC_CONTROL_DISABLE_ACCUM_MASK | \
+      RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \
+      RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_RESERVED9_MASK | \
+      RB_BC_CONTROL_RESERVED10_MASK)
+
+#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, reserved9, reserved10) \
+     ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \
+      (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \
+      (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \
+      (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \
+      (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \
+      (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \
+      (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \
+      (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \
+      (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \
+      (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \
+      (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \
+      (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \
+      (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \
+      (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \
+      (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \
+      (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \
+      (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \
+      (reserved9 << RB_BC_CONTROL_RESERVED9_SHIFT) | \
+      (reserved10 << RB_BC_CONTROL_RESERVED10_SHIFT))
+
+#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_RESERVED9(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_RESERVED9_MASK) >> RB_BC_CONTROL_RESERVED9_SHIFT)
+#define RB_BC_CONTROL_GET_RESERVED10(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_RESERVED10_MASK) >> RB_BC_CONTROL_RESERVED10_SHIFT)
+
+#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_RESERVED9(rb_bc_control_reg, reserved9) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED9_MASK) | (reserved9 << RB_BC_CONTROL_RESERVED9_SHIFT)
+#define RB_BC_CONTROL_SET_RESERVED10(rb_bc_control_reg, reserved10) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED10_MASK) | (reserved10 << RB_BC_CONTROL_RESERVED10_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int                                : 1;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int reserved9                      : RB_BC_CONTROL_RESERVED9_SIZE;
+          unsigned int reserved10                     : RB_BC_CONTROL_RESERVED10_SIZE;
+     } rb_bc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int reserved10                     : RB_BC_CONTROL_RESERVED10_SIZE;
+          unsigned int reserved9                      : RB_BC_CONTROL_RESERVED9_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+     } rb_bc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_control_t f;
+} rb_bc_control_u;
+
+
+/*
+ * RB_EDRAM_INFO struct
+ */
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE  4
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2
+#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4
+#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_MASK  0x0000000f
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030
+#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000
+
+#define RB_EDRAM_INFO_MASK \
+     (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \
+      RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \
+      RB_EDRAM_INFO_EDRAM_RANGE_MASK)
+
+#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \
+     ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \
+      (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \
+      (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT))
+
+#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+     } rb_edram_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+     } rb_edram_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_edram_info_t f;
+} rb_edram_info_u;
+
+
+/*
+ * RB_CRC_RD_PORT struct
+ */
+
+#define RB_CRC_RD_PORT_CRC_DATA_SIZE   32
+
+#define RB_CRC_RD_PORT_CRC_DATA_SHIFT  0
+
+#define RB_CRC_RD_PORT_CRC_DATA_MASK   0xffffffff
+
+#define RB_CRC_RD_PORT_MASK \
+     (RB_CRC_RD_PORT_CRC_DATA_MASK)
+
+#define RB_CRC_RD_PORT(crc_data) \
+     ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT))
+
+#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \
+     ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \
+     rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_rd_port_t f;
+} rb_crc_rd_port_u;
+
+
+/*
+ * RB_CRC_CONTROL struct
+ */
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001
+
+#define RB_CRC_CONTROL_MASK \
+     (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK)
+
+#define RB_CRC_CONTROL(crc_rd_advance) \
+     ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT))
+
+#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \
+     ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \
+     rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+          unsigned int                                : 31;
+     } rb_crc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int                                : 31;
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+     } rb_crc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_control_t f;
+} rb_crc_control_u;
+
+
+/*
+ * RB_CRC_MASK struct
+ */
+
+#define RB_CRC_MASK_CRC_MASK_SIZE      32
+
+#define RB_CRC_MASK_CRC_MASK_SHIFT     0
+
+#define RB_CRC_MASK_CRC_MASK_MASK      0xffffffff
+
+#define RB_CRC_MASK_MASK \
+     (RB_CRC_MASK_CRC_MASK_MASK)
+
+#define RB_CRC_MASK(crc_mask) \
+     ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT))
+
+#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \
+     ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \
+     rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_mask_t f;
+} rb_crc_mask_u;
+
+
+/*
+ * RB_PERFCOUNTER0_SELECT struct
+ */
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define RB_PERFCOUNTER0_SELECT_MASK \
+     (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define RB_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \
+     ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \
+     rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } rb_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } rb_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_select_t f;
+} rb_perfcounter0_select_u;
+
+
+/*
+ * RB_PERFCOUNTER0_LOW struct
+ */
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define RB_PERFCOUNTER0_LOW_MASK \
+     (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \
+     ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \
+     rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_low_t f;
+} rb_perfcounter0_low_u;
+
+
+/*
+ * RB_PERFCOUNTER0_HI struct
+ */
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define RB_PERFCOUNTER0_HI_MASK \
+     (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \
+     ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \
+     rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } rb_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } rb_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_hi_t f;
+} rb_perfcounter0_hi_u;
+
+
+/*
+ * RB_TOTAL_SAMPLES struct
+ */
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff
+
+#define RB_TOTAL_SAMPLES_MASK \
+     (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK)
+
+#define RB_TOTAL_SAMPLES(total_samples) \
+     ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT))
+
+#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \
+     ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \
+     rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_total_samples_t f;
+} rb_total_samples_u;
+
+
+/*
+ * RB_ZPASS_SAMPLES struct
+ */
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff
+
+#define RB_ZPASS_SAMPLES_MASK \
+     (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK)
+
+#define RB_ZPASS_SAMPLES(zpass_samples) \
+     ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT))
+
+#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \
+     ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \
+     rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zpass_samples_t f;
+} rb_zpass_samples_u;
+
+
+/*
+ * RB_ZFAIL_SAMPLES struct
+ */
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_ZFAIL_SAMPLES_MASK \
+     (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK)
+
+#define RB_ZFAIL_SAMPLES(zfail_samples) \
+     ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT))
+
+#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \
+     ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \
+     rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zfail_samples_t f;
+} rb_zfail_samples_u;
+
+
+/*
+ * RB_SFAIL_SAMPLES struct
+ */
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_SFAIL_SAMPLES_MASK \
+     (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK)
+
+#define RB_SFAIL_SAMPLES(sfail_samples) \
+     ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT))
+
+#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \
+     ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \
+     rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sfail_samples_t f;
+} rb_sfail_samples_u;
+
+
+/*
+ * RB_DEBUG_0 struct
+ */
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE  1
+#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE  1
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1
+#define RB_DEBUG_0_C_REQ_FULL_SIZE     1
+#define RB_DEBUG_0_C_MASK_FULL_SIZE    1
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7
+#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8
+#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17
+#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18
+#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25
+#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26
+#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28
+#define RB_DEBUG_0_C_REQ_FULL_SHIFT    29
+#define RB_DEBUG_0_C_MASK_FULL_SHIFT   30
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020
+#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK  0x00000040
+#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK  0x00000080
+#define RB_DEBUG_0_RDREQ_C1_FULL_MASK  0x00000100
+#define RB_DEBUG_0_RDREQ_C0_FULL_MASK  0x00000200
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000
+#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK  0x00010000
+#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK  0x00020000
+#define RB_DEBUG_0_WRREQ_C1_FULL_MASK  0x00040000
+#define RB_DEBUG_0_WRREQ_C0_FULL_MASK  0x00080000
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000
+#define RB_DEBUG_0_C_SX_LAT_FULL_MASK  0x04000000
+#define RB_DEBUG_0_C_SX_CMD_FULL_MASK  0x08000000
+#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000
+#define RB_DEBUG_0_C_REQ_FULL_MASK     0x20000000
+#define RB_DEBUG_0_C_MASK_FULL_MASK    0x40000000
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000
+
+#define RB_DEBUG_0_MASK \
+     (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_C_SX_LAT_FULL_MASK | \
+      RB_DEBUG_0_C_SX_CMD_FULL_MASK | \
+      RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \
+      RB_DEBUG_0_C_REQ_FULL_MASK | \
+      RB_DEBUG_0_C_MASK_FULL_MASK | \
+      RB_DEBUG_0_EZ_INFSAMP_FULL_MASK)
+
+#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \
+     ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \
+      (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \
+      (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \
+      (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \
+      (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \
+      (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \
+      (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \
+      (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \
+      (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \
+      (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \
+      (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \
+      (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \
+      (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \
+      (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \
+      (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \
+      (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \
+      (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \
+      (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \
+      (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \
+      (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \
+      (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT))
+
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+     } rb_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+     } rb_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_0_t f;
+} rb_debug_0_u;
+
+
+/*
+ * RB_DEBUG_1 struct
+ */
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_REQ_EMPTY_SIZE    1
+#define RB_DEBUG_1_C_MASK_EMPTY_SIZE   1
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28
+#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT   29
+#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT  30
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000
+#define RB_DEBUG_1_C_REQ_EMPTY_MASK    0x20000000
+#define RB_DEBUG_1_C_MASK_EMPTY_MASK   0x40000000
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000
+
+#define RB_DEBUG_1_MASK \
+     (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \
+      RB_DEBUG_1_C_REQ_EMPTY_MASK | \
+      RB_DEBUG_1_C_MASK_EMPTY_MASK | \
+      RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK)
+
+#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \
+     ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \
+      (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \
+      (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \
+      (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \
+      (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \
+      (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \
+      (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \
+      (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \
+      (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \
+      (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \
+      (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \
+      (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \
+      (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \
+      (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \
+      (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \
+      (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \
+      (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \
+      (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \
+      (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \
+      (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \
+      (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT))
+
+#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_1_t f;
+} rb_debug_1_u;
+
+
+/*
+ * RB_DEBUG_2 struct
+ */
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z1_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z0_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z1_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z_SAMP_FULL_SIZE    1
+#define RB_DEBUG_2_Z_TILE_FULL_SIZE    1
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE   1
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16
+#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT  17
+#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT  18
+#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT   19
+#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT   20
+#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT   21
+#define RB_DEBUG_2_Z_TILE_FULL_SHIFT   22
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT  28
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT  29
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT  30
+#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT  31
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000
+#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000
+#define RB_DEBUG_2_Z0_MASK_FULL_MASK   0x00020000
+#define RB_DEBUG_2_Z1_MASK_FULL_MASK   0x00040000
+#define RB_DEBUG_2_Z0_REQ_FULL_MASK    0x00080000
+#define RB_DEBUG_2_Z1_REQ_FULL_MASK    0x00100000
+#define RB_DEBUG_2_Z_SAMP_FULL_MASK    0x00200000
+#define RB_DEBUG_2_Z_TILE_FULL_MASK    0x00400000
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK  0x04000000
+#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK  0x08000000
+#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK   0x10000000
+#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK   0x20000000
+#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK   0x40000000
+#define RB_DEBUG_2_Z_TILE_EMPTY_MASK   0x80000000
+
+#define RB_DEBUG_2_MASK \
+     (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \
+      RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \
+      RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \
+      RB_DEBUG_2_Z0_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z1_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z0_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z1_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z_SAMP_FULL_MASK | \
+      RB_DEBUG_2_Z_TILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \
+      RB_DEBUG_2_Z_TILE_EMPTY_MASK)
+
+#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \
+     ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \
+      (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \
+      (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \
+      (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \
+      (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \
+      (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \
+      (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \
+      (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \
+      (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \
+      (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \
+      (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \
+      (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \
+      (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \
+      (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \
+      (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \
+      (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \
+      (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \
+      (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \
+      (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \
+      (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \
+      (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \
+      (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \
+      (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT))
+
+#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+     } rb_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+     } rb_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_2_t f;
+} rb_debug_2_u;
+
+
+/*
+ * RB_DEBUG_3 struct
+ */
+
+#define RB_DEBUG_3_ACCUM_VALID_SIZE    4
+#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4
+#define RB_DEBUG_3_SHD_FULL_SIZE       1
+#define RB_DEBUG_3_SHD_EMPTY_SIZE      1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1
+
+#define RB_DEBUG_3_ACCUM_VALID_SHIFT   0
+#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15
+#define RB_DEBUG_3_SHD_FULL_SHIFT      19
+#define RB_DEBUG_3_SHD_EMPTY_SHIFT     20
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28
+
+#define RB_DEBUG_3_ACCUM_VALID_MASK    0x0000000f
+#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000
+#define RB_DEBUG_3_SHD_FULL_MASK       0x00080000
+#define RB_DEBUG_3_SHD_EMPTY_MASK      0x00100000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000
+
+#define RB_DEBUG_3_MASK \
+     (RB_DEBUG_3_ACCUM_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_FLUSHING_MASK | \
+      RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \
+      RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \
+      RB_DEBUG_3_SHD_FULL_MASK | \
+      RB_DEBUG_3_SHD_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_FULL_MASK)
+
+#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \
+     ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \
+      (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \
+      (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \
+      (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \
+      (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \
+      (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \
+      (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \
+      (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \
+      (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \
+      (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \
+      (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \
+      (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \
+      (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \
+      (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \
+      (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT))
+
+#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int                                : 3;
+     } rb_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int                                : 3;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+     } rb_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_3_t f;
+} rb_debug_3_u;
+
+
+/*
+ * RB_DEBUG_4 struct
+ */
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00
+
+#define RB_DEBUG_4_MASK \
+     (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \
+      RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \
+      RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK)
+
+#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \
+     ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \
+      (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \
+      (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \
+      (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \
+      (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \
+      (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT))
+
+#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int                                : 19;
+     } rb_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int                                : 19;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+     } rb_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_4_t f;
+} rb_debug_4_u;
+
+
+/*
+ * RB_FLAG_CONTROL struct
+ */
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001
+
+#define RB_FLAG_CONTROL_MASK \
+     (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK)
+
+#define RB_FLAG_CONTROL(debug_flag_clear) \
+     ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT))
+
+#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \
+     ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \
+     rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+          unsigned int                                : 31;
+     } rb_flag_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int                                : 31;
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+     } rb_flag_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_flag_control_t f;
+} rb_flag_control_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_ENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000
+
+#define BC_DUMMY_CRAYRB_ENUMS_MASK \
+     (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK)
+
+#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \
+     ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \
+      (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \
+      (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \
+      (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \
+      (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \
+      (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \
+      (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT))
+
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_enums_t f;
+} bc_dummy_crayrb_enums_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_MOREENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \
+     (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \
+     ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT))
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \
+     ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \
+     bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+          unsigned int                                : 30;
+     } bc_dummy_crayrb_moreenums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int                                : 30;
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+     } bc_dummy_crayrb_moreenums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_moreenums_t f;
+} bc_dummy_crayrb_moreenums_u;
+
+
+#endif
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h
new file mode 100644
index 000000000000..1feebebda054
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h
@@ -0,0 +1,540 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_TYPEDEF_HEADER)
+#define _yamato_TYPEDEF_HEADER
+
+#include "yamato_registers.h"
+
+typedef union PA_CL_VPORT_XSCALE                regPA_CL_VPORT_XSCALE;
+typedef union PA_CL_VPORT_XOFFSET               regPA_CL_VPORT_XOFFSET;
+typedef union PA_CL_VPORT_YSCALE                regPA_CL_VPORT_YSCALE;
+typedef union PA_CL_VPORT_YOFFSET               regPA_CL_VPORT_YOFFSET;
+typedef union PA_CL_VPORT_ZSCALE                regPA_CL_VPORT_ZSCALE;
+typedef union PA_CL_VPORT_ZOFFSET               regPA_CL_VPORT_ZOFFSET;
+typedef union PA_CL_VTE_CNTL                    regPA_CL_VTE_CNTL;
+typedef union PA_CL_CLIP_CNTL                   regPA_CL_CLIP_CNTL;
+typedef union PA_CL_GB_VERT_CLIP_ADJ            regPA_CL_GB_VERT_CLIP_ADJ;
+typedef union PA_CL_GB_VERT_DISC_ADJ            regPA_CL_GB_VERT_DISC_ADJ;
+typedef union PA_CL_GB_HORZ_CLIP_ADJ            regPA_CL_GB_HORZ_CLIP_ADJ;
+typedef union PA_CL_GB_HORZ_DISC_ADJ            regPA_CL_GB_HORZ_DISC_ADJ;
+typedef union PA_CL_ENHANCE                     regPA_CL_ENHANCE;
+typedef union PA_SC_ENHANCE                     regPA_SC_ENHANCE;
+typedef union PA_SU_VTX_CNTL                    regPA_SU_VTX_CNTL;
+typedef union PA_SU_POINT_SIZE                  regPA_SU_POINT_SIZE;
+typedef union PA_SU_POINT_MINMAX                regPA_SU_POINT_MINMAX;
+typedef union PA_SU_LINE_CNTL                   regPA_SU_LINE_CNTL;
+typedef union PA_SU_SC_MODE_CNTL                regPA_SU_SC_MODE_CNTL;
+typedef union PA_SU_POLY_OFFSET_FRONT_SCALE     regPA_SU_POLY_OFFSET_FRONT_SCALE;
+typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET    regPA_SU_POLY_OFFSET_FRONT_OFFSET;
+typedef union PA_SU_POLY_OFFSET_BACK_SCALE      regPA_SU_POLY_OFFSET_BACK_SCALE;
+typedef union PA_SU_POLY_OFFSET_BACK_OFFSET     regPA_SU_POLY_OFFSET_BACK_OFFSET;
+typedef union PA_SU_PERFCOUNTER0_SELECT         regPA_SU_PERFCOUNTER0_SELECT;
+typedef union PA_SU_PERFCOUNTER1_SELECT         regPA_SU_PERFCOUNTER1_SELECT;
+typedef union PA_SU_PERFCOUNTER2_SELECT         regPA_SU_PERFCOUNTER2_SELECT;
+typedef union PA_SU_PERFCOUNTER3_SELECT         regPA_SU_PERFCOUNTER3_SELECT;
+typedef union PA_SU_PERFCOUNTER0_LOW            regPA_SU_PERFCOUNTER0_LOW;
+typedef union PA_SU_PERFCOUNTER0_HI             regPA_SU_PERFCOUNTER0_HI;
+typedef union PA_SU_PERFCOUNTER1_LOW            regPA_SU_PERFCOUNTER1_LOW;
+typedef union PA_SU_PERFCOUNTER1_HI             regPA_SU_PERFCOUNTER1_HI;
+typedef union PA_SU_PERFCOUNTER2_LOW            regPA_SU_PERFCOUNTER2_LOW;
+typedef union PA_SU_PERFCOUNTER2_HI             regPA_SU_PERFCOUNTER2_HI;
+typedef union PA_SU_PERFCOUNTER3_LOW            regPA_SU_PERFCOUNTER3_LOW;
+typedef union PA_SU_PERFCOUNTER3_HI             regPA_SU_PERFCOUNTER3_HI;
+typedef union PA_SC_WINDOW_OFFSET               regPA_SC_WINDOW_OFFSET;
+typedef union PA_SC_AA_CONFIG                   regPA_SC_AA_CONFIG;
+typedef union PA_SC_AA_MASK                     regPA_SC_AA_MASK;
+typedef union PA_SC_LINE_STIPPLE                regPA_SC_LINE_STIPPLE;
+typedef union PA_SC_LINE_CNTL                   regPA_SC_LINE_CNTL;
+typedef union PA_SC_WINDOW_SCISSOR_TL           regPA_SC_WINDOW_SCISSOR_TL;
+typedef union PA_SC_WINDOW_SCISSOR_BR           regPA_SC_WINDOW_SCISSOR_BR;
+typedef union PA_SC_SCREEN_SCISSOR_TL           regPA_SC_SCREEN_SCISSOR_TL;
+typedef union PA_SC_SCREEN_SCISSOR_BR           regPA_SC_SCREEN_SCISSOR_BR;
+typedef union PA_SC_VIZ_QUERY                   regPA_SC_VIZ_QUERY;
+typedef union PA_SC_VIZ_QUERY_STATUS            regPA_SC_VIZ_QUERY_STATUS;
+typedef union PA_SC_LINE_STIPPLE_STATE          regPA_SC_LINE_STIPPLE_STATE;
+typedef union PA_SC_PERFCOUNTER0_SELECT         regPA_SC_PERFCOUNTER0_SELECT;
+typedef union PA_SC_PERFCOUNTER0_LOW            regPA_SC_PERFCOUNTER0_LOW;
+typedef union PA_SC_PERFCOUNTER0_HI             regPA_SC_PERFCOUNTER0_HI;
+typedef union PA_CL_CNTL_STATUS                 regPA_CL_CNTL_STATUS;
+typedef union PA_SU_CNTL_STATUS                 regPA_SU_CNTL_STATUS;
+typedef union PA_SC_CNTL_STATUS                 regPA_SC_CNTL_STATUS;
+typedef union PA_SU_DEBUG_CNTL                  regPA_SU_DEBUG_CNTL;
+typedef union PA_SU_DEBUG_DATA                  regPA_SU_DEBUG_DATA;
+typedef union PA_SC_DEBUG_CNTL                  regPA_SC_DEBUG_CNTL;
+typedef union PA_SC_DEBUG_DATA                  regPA_SC_DEBUG_DATA;
+typedef union GFX_COPY_STATE                    regGFX_COPY_STATE;
+typedef union VGT_DRAW_INITIATOR                regVGT_DRAW_INITIATOR;
+typedef union VGT_EVENT_INITIATOR               regVGT_EVENT_INITIATOR;
+typedef union VGT_DMA_BASE                      regVGT_DMA_BASE;
+typedef union VGT_DMA_SIZE                      regVGT_DMA_SIZE;
+typedef union VGT_BIN_BASE                      regVGT_BIN_BASE;
+typedef union VGT_BIN_SIZE                      regVGT_BIN_SIZE;
+typedef union VGT_CURRENT_BIN_ID_MIN            regVGT_CURRENT_BIN_ID_MIN;
+typedef union VGT_CURRENT_BIN_ID_MAX            regVGT_CURRENT_BIN_ID_MAX;
+typedef union VGT_IMMED_DATA                    regVGT_IMMED_DATA;
+typedef union VGT_MAX_VTX_INDX                  regVGT_MAX_VTX_INDX;
+typedef union VGT_MIN_VTX_INDX                  regVGT_MIN_VTX_INDX;
+typedef union VGT_INDX_OFFSET                   regVGT_INDX_OFFSET;
+typedef union VGT_VERTEX_REUSE_BLOCK_CNTL       regVGT_VERTEX_REUSE_BLOCK_CNTL;
+typedef union VGT_OUT_DEALLOC_CNTL              regVGT_OUT_DEALLOC_CNTL;
+typedef union VGT_MULTI_PRIM_IB_RESET_INDX      regVGT_MULTI_PRIM_IB_RESET_INDX;
+typedef union VGT_ENHANCE                       regVGT_ENHANCE;
+typedef union VGT_VTX_VECT_EJECT_REG            regVGT_VTX_VECT_EJECT_REG;
+typedef union VGT_LAST_COPY_STATE               regVGT_LAST_COPY_STATE;
+typedef union VGT_DEBUG_CNTL                    regVGT_DEBUG_CNTL;
+typedef union VGT_DEBUG_DATA                    regVGT_DEBUG_DATA;
+typedef union VGT_CNTL_STATUS                   regVGT_CNTL_STATUS;
+typedef union VGT_CRC_SQ_DATA                   regVGT_CRC_SQ_DATA;
+typedef union VGT_CRC_SQ_CTRL                   regVGT_CRC_SQ_CTRL;
+typedef union VGT_PERFCOUNTER0_SELECT           regVGT_PERFCOUNTER0_SELECT;
+typedef union VGT_PERFCOUNTER1_SELECT           regVGT_PERFCOUNTER1_SELECT;
+typedef union VGT_PERFCOUNTER2_SELECT           regVGT_PERFCOUNTER2_SELECT;
+typedef union VGT_PERFCOUNTER3_SELECT           regVGT_PERFCOUNTER3_SELECT;
+typedef union VGT_PERFCOUNTER0_LOW              regVGT_PERFCOUNTER0_LOW;
+typedef union VGT_PERFCOUNTER1_LOW              regVGT_PERFCOUNTER1_LOW;
+typedef union VGT_PERFCOUNTER2_LOW              regVGT_PERFCOUNTER2_LOW;
+typedef union VGT_PERFCOUNTER3_LOW              regVGT_PERFCOUNTER3_LOW;
+typedef union VGT_PERFCOUNTER0_HI               regVGT_PERFCOUNTER0_HI;
+typedef union VGT_PERFCOUNTER1_HI               regVGT_PERFCOUNTER1_HI;
+typedef union VGT_PERFCOUNTER2_HI               regVGT_PERFCOUNTER2_HI;
+typedef union VGT_PERFCOUNTER3_HI               regVGT_PERFCOUNTER3_HI;
+typedef union TC_CNTL_STATUS                    regTC_CNTL_STATUS;
+typedef union TCR_CHICKEN                       regTCR_CHICKEN;
+typedef union TCF_CHICKEN                       regTCF_CHICKEN;
+typedef union TCM_CHICKEN                       regTCM_CHICKEN;
+typedef union TCR_PERFCOUNTER0_SELECT           regTCR_PERFCOUNTER0_SELECT;
+typedef union TCR_PERFCOUNTER1_SELECT           regTCR_PERFCOUNTER1_SELECT;
+typedef union TCR_PERFCOUNTER0_HI               regTCR_PERFCOUNTER0_HI;
+typedef union TCR_PERFCOUNTER1_HI               regTCR_PERFCOUNTER1_HI;
+typedef union TCR_PERFCOUNTER0_LOW              regTCR_PERFCOUNTER0_LOW;
+typedef union TCR_PERFCOUNTER1_LOW              regTCR_PERFCOUNTER1_LOW;
+typedef union TP_TC_CLKGATE_CNTL                regTP_TC_CLKGATE_CNTL;
+typedef union TPC_CNTL_STATUS                   regTPC_CNTL_STATUS;
+typedef union TPC_DEBUG0                        regTPC_DEBUG0;
+typedef union TPC_DEBUG1                        regTPC_DEBUG1;
+typedef union TPC_CHICKEN                       regTPC_CHICKEN;
+typedef union TP0_CNTL_STATUS                   regTP0_CNTL_STATUS;
+typedef union TP0_DEBUG                         regTP0_DEBUG;
+typedef union TP0_CHICKEN                       regTP0_CHICKEN;
+typedef union TP0_PERFCOUNTER0_SELECT           regTP0_PERFCOUNTER0_SELECT;
+typedef union TP0_PERFCOUNTER0_HI               regTP0_PERFCOUNTER0_HI;
+typedef union TP0_PERFCOUNTER0_LOW              regTP0_PERFCOUNTER0_LOW;
+typedef union TP0_PERFCOUNTER1_SELECT           regTP0_PERFCOUNTER1_SELECT;
+typedef union TP0_PERFCOUNTER1_HI               regTP0_PERFCOUNTER1_HI;
+typedef union TP0_PERFCOUNTER1_LOW              regTP0_PERFCOUNTER1_LOW;
+typedef union TCM_PERFCOUNTER0_SELECT           regTCM_PERFCOUNTER0_SELECT;
+typedef union TCM_PERFCOUNTER1_SELECT           regTCM_PERFCOUNTER1_SELECT;
+typedef union TCM_PERFCOUNTER0_HI               regTCM_PERFCOUNTER0_HI;
+typedef union TCM_PERFCOUNTER1_HI               regTCM_PERFCOUNTER1_HI;
+typedef union TCM_PERFCOUNTER0_LOW              regTCM_PERFCOUNTER0_LOW;
+typedef union TCM_PERFCOUNTER1_LOW              regTCM_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER0_SELECT           regTCF_PERFCOUNTER0_SELECT;
+typedef union TCF_PERFCOUNTER1_SELECT           regTCF_PERFCOUNTER1_SELECT;
+typedef union TCF_PERFCOUNTER2_SELECT           regTCF_PERFCOUNTER2_SELECT;
+typedef union TCF_PERFCOUNTER3_SELECT           regTCF_PERFCOUNTER3_SELECT;
+typedef union TCF_PERFCOUNTER4_SELECT           regTCF_PERFCOUNTER4_SELECT;
+typedef union TCF_PERFCOUNTER5_SELECT           regTCF_PERFCOUNTER5_SELECT;
+typedef union TCF_PERFCOUNTER6_SELECT           regTCF_PERFCOUNTER6_SELECT;
+typedef union TCF_PERFCOUNTER7_SELECT           regTCF_PERFCOUNTER7_SELECT;
+typedef union TCF_PERFCOUNTER8_SELECT           regTCF_PERFCOUNTER8_SELECT;
+typedef union TCF_PERFCOUNTER9_SELECT           regTCF_PERFCOUNTER9_SELECT;
+typedef union TCF_PERFCOUNTER10_SELECT          regTCF_PERFCOUNTER10_SELECT;
+typedef union TCF_PERFCOUNTER11_SELECT          regTCF_PERFCOUNTER11_SELECT;
+typedef union TCF_PERFCOUNTER0_HI               regTCF_PERFCOUNTER0_HI;
+typedef union TCF_PERFCOUNTER1_HI               regTCF_PERFCOUNTER1_HI;
+typedef union TCF_PERFCOUNTER2_HI               regTCF_PERFCOUNTER2_HI;
+typedef union TCF_PERFCOUNTER3_HI               regTCF_PERFCOUNTER3_HI;
+typedef union TCF_PERFCOUNTER4_HI               regTCF_PERFCOUNTER4_HI;
+typedef union TCF_PERFCOUNTER5_HI               regTCF_PERFCOUNTER5_HI;
+typedef union TCF_PERFCOUNTER6_HI               regTCF_PERFCOUNTER6_HI;
+typedef union TCF_PERFCOUNTER7_HI               regTCF_PERFCOUNTER7_HI;
+typedef union TCF_PERFCOUNTER8_HI               regTCF_PERFCOUNTER8_HI;
+typedef union TCF_PERFCOUNTER9_HI               regTCF_PERFCOUNTER9_HI;
+typedef union TCF_PERFCOUNTER10_HI              regTCF_PERFCOUNTER10_HI;
+typedef union TCF_PERFCOUNTER11_HI              regTCF_PERFCOUNTER11_HI;
+typedef union TCF_PERFCOUNTER0_LOW              regTCF_PERFCOUNTER0_LOW;
+typedef union TCF_PERFCOUNTER1_LOW              regTCF_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER2_LOW              regTCF_PERFCOUNTER2_LOW;
+typedef union TCF_PERFCOUNTER3_LOW              regTCF_PERFCOUNTER3_LOW;
+typedef union TCF_PERFCOUNTER4_LOW              regTCF_PERFCOUNTER4_LOW;
+typedef union TCF_PERFCOUNTER5_LOW              regTCF_PERFCOUNTER5_LOW;
+typedef union TCF_PERFCOUNTER6_LOW              regTCF_PERFCOUNTER6_LOW;
+typedef union TCF_PERFCOUNTER7_LOW              regTCF_PERFCOUNTER7_LOW;
+typedef union TCF_PERFCOUNTER8_LOW              regTCF_PERFCOUNTER8_LOW;
+typedef union TCF_PERFCOUNTER9_LOW              regTCF_PERFCOUNTER9_LOW;
+typedef union TCF_PERFCOUNTER10_LOW             regTCF_PERFCOUNTER10_LOW;
+typedef union TCF_PERFCOUNTER11_LOW             regTCF_PERFCOUNTER11_LOW;
+typedef union TCF_DEBUG                         regTCF_DEBUG;
+typedef union TCA_FIFO_DEBUG                    regTCA_FIFO_DEBUG;
+typedef union TCA_PROBE_DEBUG                   regTCA_PROBE_DEBUG;
+typedef union TCA_TPC_DEBUG                     regTCA_TPC_DEBUG;
+typedef union TCB_CORE_DEBUG                    regTCB_CORE_DEBUG;
+typedef union TCB_TAG0_DEBUG                    regTCB_TAG0_DEBUG;
+typedef union TCB_TAG1_DEBUG                    regTCB_TAG1_DEBUG;
+typedef union TCB_TAG2_DEBUG                    regTCB_TAG2_DEBUG;
+typedef union TCB_TAG3_DEBUG                    regTCB_TAG3_DEBUG;
+typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG;
+typedef union TCB_FETCH_GEN_WALKER_DEBUG        regTCB_FETCH_GEN_WALKER_DEBUG;
+typedef union TCB_FETCH_GEN_PIPE0_DEBUG         regTCB_FETCH_GEN_PIPE0_DEBUG;
+typedef union TCD_INPUT0_DEBUG                  regTCD_INPUT0_DEBUG;
+typedef union TCD_DEGAMMA_DEBUG                 regTCD_DEGAMMA_DEBUG;
+typedef union TCD_DXTMUX_SCTARB_DEBUG           regTCD_DXTMUX_SCTARB_DEBUG;
+typedef union TCD_DXTC_ARB_DEBUG                regTCD_DXTC_ARB_DEBUG;
+typedef union TCD_STALLS_DEBUG                  regTCD_STALLS_DEBUG;
+typedef union TCO_STALLS_DEBUG                  regTCO_STALLS_DEBUG;
+typedef union TCO_QUAD0_DEBUG0                  regTCO_QUAD0_DEBUG0;
+typedef union TCO_QUAD0_DEBUG1                  regTCO_QUAD0_DEBUG1;
+typedef union SQ_GPR_MANAGEMENT                 regSQ_GPR_MANAGEMENT;
+typedef union SQ_FLOW_CONTROL                   regSQ_FLOW_CONTROL;
+typedef union SQ_INST_STORE_MANAGMENT           regSQ_INST_STORE_MANAGMENT;
+typedef union SQ_RESOURCE_MANAGMENT             regSQ_RESOURCE_MANAGMENT;
+typedef union SQ_EO_RT                          regSQ_EO_RT;
+typedef union SQ_DEBUG_MISC                     regSQ_DEBUG_MISC;
+typedef union SQ_ACTIVITY_METER_CNTL            regSQ_ACTIVITY_METER_CNTL;
+typedef union SQ_ACTIVITY_METER_STATUS          regSQ_ACTIVITY_METER_STATUS;
+typedef union SQ_INPUT_ARB_PRIORITY             regSQ_INPUT_ARB_PRIORITY;
+typedef union SQ_THREAD_ARB_PRIORITY            regSQ_THREAD_ARB_PRIORITY;
+typedef union SQ_DEBUG_INPUT_FSM                regSQ_DEBUG_INPUT_FSM;
+typedef union SQ_DEBUG_CONST_MGR_FSM            regSQ_DEBUG_CONST_MGR_FSM;
+typedef union SQ_DEBUG_TP_FSM                   regSQ_DEBUG_TP_FSM;
+typedef union SQ_DEBUG_FSM_ALU_0                regSQ_DEBUG_FSM_ALU_0;
+typedef union SQ_DEBUG_FSM_ALU_1                regSQ_DEBUG_FSM_ALU_1;
+typedef union SQ_DEBUG_EXP_ALLOC                regSQ_DEBUG_EXP_ALLOC;
+typedef union SQ_DEBUG_PTR_BUFF                 regSQ_DEBUG_PTR_BUFF;
+typedef union SQ_DEBUG_GPR_VTX                  regSQ_DEBUG_GPR_VTX;
+typedef union SQ_DEBUG_GPR_PIX                  regSQ_DEBUG_GPR_PIX;
+typedef union SQ_DEBUG_TB_STATUS_SEL            regSQ_DEBUG_TB_STATUS_SEL;
+typedef union SQ_DEBUG_VTX_TB_0                 regSQ_DEBUG_VTX_TB_0;
+typedef union SQ_DEBUG_VTX_TB_1                 regSQ_DEBUG_VTX_TB_1;
+typedef union SQ_DEBUG_VTX_TB_STATUS_REG        regSQ_DEBUG_VTX_TB_STATUS_REG;
+typedef union SQ_DEBUG_VTX_TB_STATE_MEM         regSQ_DEBUG_VTX_TB_STATE_MEM;
+typedef union SQ_DEBUG_PIX_TB_0                 regSQ_DEBUG_PIX_TB_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0      regSQ_DEBUG_PIX_TB_STATUS_REG_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1      regSQ_DEBUG_PIX_TB_STATUS_REG_1;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2      regSQ_DEBUG_PIX_TB_STATUS_REG_2;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3      regSQ_DEBUG_PIX_TB_STATUS_REG_3;
+typedef union SQ_DEBUG_PIX_TB_STATE_MEM         regSQ_DEBUG_PIX_TB_STATE_MEM;
+typedef union SQ_PERFCOUNTER0_SELECT            regSQ_PERFCOUNTER0_SELECT;
+typedef union SQ_PERFCOUNTER1_SELECT            regSQ_PERFCOUNTER1_SELECT;
+typedef union SQ_PERFCOUNTER2_SELECT            regSQ_PERFCOUNTER2_SELECT;
+typedef union SQ_PERFCOUNTER3_SELECT            regSQ_PERFCOUNTER3_SELECT;
+typedef union SQ_PERFCOUNTER0_LOW               regSQ_PERFCOUNTER0_LOW;
+typedef union SQ_PERFCOUNTER0_HI                regSQ_PERFCOUNTER0_HI;
+typedef union SQ_PERFCOUNTER1_LOW               regSQ_PERFCOUNTER1_LOW;
+typedef union SQ_PERFCOUNTER1_HI                regSQ_PERFCOUNTER1_HI;
+typedef union SQ_PERFCOUNTER2_LOW               regSQ_PERFCOUNTER2_LOW;
+typedef union SQ_PERFCOUNTER2_HI                regSQ_PERFCOUNTER2_HI;
+typedef union SQ_PERFCOUNTER3_LOW               regSQ_PERFCOUNTER3_LOW;
+typedef union SQ_PERFCOUNTER3_HI                regSQ_PERFCOUNTER3_HI;
+typedef union SX_PERFCOUNTER0_SELECT            regSX_PERFCOUNTER0_SELECT;
+typedef union SX_PERFCOUNTER0_LOW               regSX_PERFCOUNTER0_LOW;
+typedef union SX_PERFCOUNTER0_HI                regSX_PERFCOUNTER0_HI;
+typedef union SQ_INSTRUCTION_ALU_0              regSQ_INSTRUCTION_ALU_0;
+typedef union SQ_INSTRUCTION_ALU_1              regSQ_INSTRUCTION_ALU_1;
+typedef union SQ_INSTRUCTION_ALU_2              regSQ_INSTRUCTION_ALU_2;
+typedef union SQ_INSTRUCTION_CF_EXEC_0          regSQ_INSTRUCTION_CF_EXEC_0;
+typedef union SQ_INSTRUCTION_CF_EXEC_1          regSQ_INSTRUCTION_CF_EXEC_1;
+typedef union SQ_INSTRUCTION_CF_EXEC_2          regSQ_INSTRUCTION_CF_EXEC_2;
+typedef union SQ_INSTRUCTION_CF_LOOP_0          regSQ_INSTRUCTION_CF_LOOP_0;
+typedef union SQ_INSTRUCTION_CF_LOOP_1          regSQ_INSTRUCTION_CF_LOOP_1;
+typedef union SQ_INSTRUCTION_CF_LOOP_2          regSQ_INSTRUCTION_CF_LOOP_2;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_0      regSQ_INSTRUCTION_CF_JMP_CALL_0;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_1      regSQ_INSTRUCTION_CF_JMP_CALL_1;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_2      regSQ_INSTRUCTION_CF_JMP_CALL_2;
+typedef union SQ_INSTRUCTION_CF_ALLOC_0         regSQ_INSTRUCTION_CF_ALLOC_0;
+typedef union SQ_INSTRUCTION_CF_ALLOC_1         regSQ_INSTRUCTION_CF_ALLOC_1;
+typedef union SQ_INSTRUCTION_CF_ALLOC_2         regSQ_INSTRUCTION_CF_ALLOC_2;
+typedef union SQ_INSTRUCTION_TFETCH_0           regSQ_INSTRUCTION_TFETCH_0;
+typedef union SQ_INSTRUCTION_TFETCH_1           regSQ_INSTRUCTION_TFETCH_1;
+typedef union SQ_INSTRUCTION_TFETCH_2           regSQ_INSTRUCTION_TFETCH_2;
+typedef union SQ_INSTRUCTION_VFETCH_0           regSQ_INSTRUCTION_VFETCH_0;
+typedef union SQ_INSTRUCTION_VFETCH_1           regSQ_INSTRUCTION_VFETCH_1;
+typedef union SQ_INSTRUCTION_VFETCH_2           regSQ_INSTRUCTION_VFETCH_2;
+typedef union SQ_CONSTANT_0                     regSQ_CONSTANT_0;
+typedef union SQ_CONSTANT_1                     regSQ_CONSTANT_1;
+typedef union SQ_CONSTANT_2                     regSQ_CONSTANT_2;
+typedef union SQ_CONSTANT_3                     regSQ_CONSTANT_3;
+typedef union SQ_FETCH_0                        regSQ_FETCH_0;
+typedef union SQ_FETCH_1                        regSQ_FETCH_1;
+typedef union SQ_FETCH_2                        regSQ_FETCH_2;
+typedef union SQ_FETCH_3                        regSQ_FETCH_3;
+typedef union SQ_FETCH_4                        regSQ_FETCH_4;
+typedef union SQ_FETCH_5                        regSQ_FETCH_5;
+typedef union SQ_CONSTANT_VFETCH_0              regSQ_CONSTANT_VFETCH_0;
+typedef union SQ_CONSTANT_VFETCH_1              regSQ_CONSTANT_VFETCH_1;
+typedef union SQ_CONSTANT_T2                    regSQ_CONSTANT_T2;
+typedef union SQ_CONSTANT_T3                    regSQ_CONSTANT_T3;
+typedef union SQ_CF_BOOLEANS                    regSQ_CF_BOOLEANS;
+typedef union SQ_CF_LOOP                        regSQ_CF_LOOP;
+typedef union SQ_CONSTANT_RT_0                  regSQ_CONSTANT_RT_0;
+typedef union SQ_CONSTANT_RT_1                  regSQ_CONSTANT_RT_1;
+typedef union SQ_CONSTANT_RT_2                  regSQ_CONSTANT_RT_2;
+typedef union SQ_CONSTANT_RT_3                  regSQ_CONSTANT_RT_3;
+typedef union SQ_FETCH_RT_0                     regSQ_FETCH_RT_0;
+typedef union SQ_FETCH_RT_1                     regSQ_FETCH_RT_1;
+typedef union SQ_FETCH_RT_2                     regSQ_FETCH_RT_2;
+typedef union SQ_FETCH_RT_3                     regSQ_FETCH_RT_3;
+typedef union SQ_FETCH_RT_4                     regSQ_FETCH_RT_4;
+typedef union SQ_FETCH_RT_5                     regSQ_FETCH_RT_5;
+typedef union SQ_CF_RT_BOOLEANS                 regSQ_CF_RT_BOOLEANS;
+typedef union SQ_CF_RT_LOOP                     regSQ_CF_RT_LOOP;
+typedef union SQ_VS_PROGRAM                     regSQ_VS_PROGRAM;
+typedef union SQ_PS_PROGRAM                     regSQ_PS_PROGRAM;
+typedef union SQ_CF_PROGRAM_SIZE                regSQ_CF_PROGRAM_SIZE;
+typedef union SQ_INTERPOLATOR_CNTL              regSQ_INTERPOLATOR_CNTL;
+typedef union SQ_PROGRAM_CNTL                   regSQ_PROGRAM_CNTL;
+typedef union SQ_WRAPPING_0                     regSQ_WRAPPING_0;
+typedef union SQ_WRAPPING_1                     regSQ_WRAPPING_1;
+typedef union SQ_VS_CONST                       regSQ_VS_CONST;
+typedef union SQ_PS_CONST                       regSQ_PS_CONST;
+typedef union SQ_CONTEXT_MISC                   regSQ_CONTEXT_MISC;
+typedef union SQ_CF_RD_BASE                     regSQ_CF_RD_BASE;
+typedef union SQ_DEBUG_MISC_0                   regSQ_DEBUG_MISC_0;
+typedef union SQ_DEBUG_MISC_1                   regSQ_DEBUG_MISC_1;
+typedef union MH_ARBITER_CONFIG                 regMH_ARBITER_CONFIG;
+typedef union MH_CLNT_AXI_ID_REUSE              regMH_CLNT_AXI_ID_REUSE;
+typedef union MH_INTERRUPT_MASK                 regMH_INTERRUPT_MASK;
+typedef union MH_INTERRUPT_STATUS               regMH_INTERRUPT_STATUS;
+typedef union MH_INTERRUPT_CLEAR                regMH_INTERRUPT_CLEAR;
+typedef union MH_AXI_ERROR                      regMH_AXI_ERROR;
+typedef union MH_PERFCOUNTER0_SELECT            regMH_PERFCOUNTER0_SELECT;
+typedef union MH_PERFCOUNTER1_SELECT            regMH_PERFCOUNTER1_SELECT;
+typedef union MH_PERFCOUNTER0_CONFIG            regMH_PERFCOUNTER0_CONFIG;
+typedef union MH_PERFCOUNTER1_CONFIG            regMH_PERFCOUNTER1_CONFIG;
+typedef union MH_PERFCOUNTER0_LOW               regMH_PERFCOUNTER0_LOW;
+typedef union MH_PERFCOUNTER1_LOW               regMH_PERFCOUNTER1_LOW;
+typedef union MH_PERFCOUNTER0_HI                regMH_PERFCOUNTER0_HI;
+typedef union MH_PERFCOUNTER1_HI                regMH_PERFCOUNTER1_HI;
+typedef union MH_DEBUG_CTRL                     regMH_DEBUG_CTRL;
+typedef union MH_DEBUG_DATA                     regMH_DEBUG_DATA;
+typedef union MH_MMU_CONFIG                     regMH_MMU_CONFIG;
+typedef union MH_MMU_VA_RANGE                   regMH_MMU_VA_RANGE;
+typedef union MH_MMU_PT_BASE                    regMH_MMU_PT_BASE;
+typedef union MH_MMU_PAGE_FAULT                 regMH_MMU_PAGE_FAULT;
+typedef union MH_MMU_TRAN_ERROR                 regMH_MMU_TRAN_ERROR;
+typedef union MH_MMU_INVALIDATE                 regMH_MMU_INVALIDATE;
+typedef union MH_MMU_MPU_BASE                   regMH_MMU_MPU_BASE;
+typedef union MH_MMU_MPU_END                    regMH_MMU_MPU_END;
+typedef union WAIT_UNTIL                        regWAIT_UNTIL;
+typedef union RBBM_ISYNC_CNTL                   regRBBM_ISYNC_CNTL;
+typedef union RBBM_STATUS                       regRBBM_STATUS;
+typedef union RBBM_DSPLY                        regRBBM_DSPLY;
+typedef union RBBM_RENDER_LATEST                regRBBM_RENDER_LATEST;
+typedef union RBBM_RTL_RELEASE                  regRBBM_RTL_RELEASE;
+typedef union RBBM_PATCH_RELEASE                regRBBM_PATCH_RELEASE;
+typedef union RBBM_AUXILIARY_CONFIG             regRBBM_AUXILIARY_CONFIG;
+typedef union RBBM_PERIPHID0                    regRBBM_PERIPHID0;
+typedef union RBBM_PERIPHID1                    regRBBM_PERIPHID1;
+typedef union RBBM_PERIPHID2                    regRBBM_PERIPHID2;
+typedef union RBBM_PERIPHID3                    regRBBM_PERIPHID3;
+typedef union RBBM_CNTL                         regRBBM_CNTL;
+typedef union RBBM_SKEW_CNTL                    regRBBM_SKEW_CNTL;
+typedef union RBBM_SOFT_RESET                   regRBBM_SOFT_RESET;
+typedef union RBBM_PM_OVERRIDE1                 regRBBM_PM_OVERRIDE1;
+typedef union RBBM_PM_OVERRIDE2                 regRBBM_PM_OVERRIDE2;
+typedef union GC_SYS_IDLE                       regGC_SYS_IDLE;
+typedef union NQWAIT_UNTIL                      regNQWAIT_UNTIL;
+typedef union RBBM_DEBUG                        regRBBM_DEBUG;
+typedef union RBBM_READ_ERROR                   regRBBM_READ_ERROR;
+typedef union RBBM_WAIT_IDLE_CLOCKS             regRBBM_WAIT_IDLE_CLOCKS;
+typedef union RBBM_INT_CNTL                     regRBBM_INT_CNTL;
+typedef union RBBM_INT_STATUS                   regRBBM_INT_STATUS;
+typedef union RBBM_INT_ACK                      regRBBM_INT_ACK;
+typedef union MASTER_INT_SIGNAL                 regMASTER_INT_SIGNAL;
+typedef union RBBM_PERFCOUNTER1_SELECT          regRBBM_PERFCOUNTER1_SELECT;
+typedef union RBBM_PERFCOUNTER1_LO              regRBBM_PERFCOUNTER1_LO;
+typedef union RBBM_PERFCOUNTER1_HI              regRBBM_PERFCOUNTER1_HI;
+typedef union CP_RB_BASE                        regCP_RB_BASE;
+typedef union CP_RB_CNTL                        regCP_RB_CNTL;
+typedef union CP_RB_RPTR_ADDR                   regCP_RB_RPTR_ADDR;
+typedef union CP_RB_RPTR                        regCP_RB_RPTR;
+typedef union CP_RB_RPTR_WR                     regCP_RB_RPTR_WR;
+typedef union CP_RB_WPTR                        regCP_RB_WPTR;
+typedef union CP_RB_WPTR_DELAY                  regCP_RB_WPTR_DELAY;
+typedef union CP_RB_WPTR_BASE                   regCP_RB_WPTR_BASE;
+typedef union CP_IB1_BASE                       regCP_IB1_BASE;
+typedef union CP_IB1_BUFSZ                      regCP_IB1_BUFSZ;
+typedef union CP_IB2_BASE                       regCP_IB2_BASE;
+typedef union CP_IB2_BUFSZ                      regCP_IB2_BUFSZ;
+typedef union CP_ST_BASE                        regCP_ST_BASE;
+typedef union CP_ST_BUFSZ                       regCP_ST_BUFSZ;
+typedef union CP_QUEUE_THRESHOLDS               regCP_QUEUE_THRESHOLDS;
+typedef union CP_MEQ_THRESHOLDS                 regCP_MEQ_THRESHOLDS;
+typedef union CP_CSQ_AVAIL                      regCP_CSQ_AVAIL;
+typedef union CP_STQ_AVAIL                      regCP_STQ_AVAIL;
+typedef union CP_MEQ_AVAIL                      regCP_MEQ_AVAIL;
+typedef union CP_CSQ_RB_STAT                    regCP_CSQ_RB_STAT;
+typedef union CP_CSQ_IB1_STAT                   regCP_CSQ_IB1_STAT;
+typedef union CP_CSQ_IB2_STAT                   regCP_CSQ_IB2_STAT;
+typedef union CP_NON_PREFETCH_CNTRS             regCP_NON_PREFETCH_CNTRS;
+typedef union CP_STQ_ST_STAT                    regCP_STQ_ST_STAT;
+typedef union CP_MEQ_STAT                       regCP_MEQ_STAT;
+typedef union CP_MIU_TAG_STAT                   regCP_MIU_TAG_STAT;
+typedef union CP_CMD_INDEX                      regCP_CMD_INDEX;
+typedef union CP_CMD_DATA                       regCP_CMD_DATA;
+typedef union CP_ME_CNTL                        regCP_ME_CNTL;
+typedef union CP_ME_STATUS                      regCP_ME_STATUS;
+typedef union CP_ME_RAM_WADDR                   regCP_ME_RAM_WADDR;
+typedef union CP_ME_RAM_RADDR                   regCP_ME_RAM_RADDR;
+typedef union CP_ME_RAM_DATA                    regCP_ME_RAM_DATA;
+typedef union CP_ME_RDADDR                      regCP_ME_RDADDR;
+typedef union CP_DEBUG                          regCP_DEBUG;
+typedef union SCRATCH_REG0                      regSCRATCH_REG0;
+typedef union GUI_SCRATCH_REG0                  regGUI_SCRATCH_REG0;
+typedef union SCRATCH_REG1                      regSCRATCH_REG1;
+typedef union GUI_SCRATCH_REG1                  regGUI_SCRATCH_REG1;
+typedef union SCRATCH_REG2                      regSCRATCH_REG2;
+typedef union GUI_SCRATCH_REG2                  regGUI_SCRATCH_REG2;
+typedef union SCRATCH_REG3                      regSCRATCH_REG3;
+typedef union GUI_SCRATCH_REG3                  regGUI_SCRATCH_REG3;
+typedef union SCRATCH_REG4                      regSCRATCH_REG4;
+typedef union GUI_SCRATCH_REG4                  regGUI_SCRATCH_REG4;
+typedef union SCRATCH_REG5                      regSCRATCH_REG5;
+typedef union GUI_SCRATCH_REG5                  regGUI_SCRATCH_REG5;
+typedef union SCRATCH_REG6                      regSCRATCH_REG6;
+typedef union GUI_SCRATCH_REG6                  regGUI_SCRATCH_REG6;
+typedef union SCRATCH_REG7                      regSCRATCH_REG7;
+typedef union GUI_SCRATCH_REG7                  regGUI_SCRATCH_REG7;
+typedef union SCRATCH_UMSK                      regSCRATCH_UMSK;
+typedef union SCRATCH_ADDR                      regSCRATCH_ADDR;
+typedef union CP_ME_VS_EVENT_SRC                regCP_ME_VS_EVENT_SRC;
+typedef union CP_ME_VS_EVENT_ADDR               regCP_ME_VS_EVENT_ADDR;
+typedef union CP_ME_VS_EVENT_DATA               regCP_ME_VS_EVENT_DATA;
+typedef union CP_ME_VS_EVENT_ADDR_SWM           regCP_ME_VS_EVENT_ADDR_SWM;
+typedef union CP_ME_VS_EVENT_DATA_SWM           regCP_ME_VS_EVENT_DATA_SWM;
+typedef union CP_ME_PS_EVENT_SRC                regCP_ME_PS_EVENT_SRC;
+typedef union CP_ME_PS_EVENT_ADDR               regCP_ME_PS_EVENT_ADDR;
+typedef union CP_ME_PS_EVENT_DATA               regCP_ME_PS_EVENT_DATA;
+typedef union CP_ME_PS_EVENT_ADDR_SWM           regCP_ME_PS_EVENT_ADDR_SWM;
+typedef union CP_ME_PS_EVENT_DATA_SWM           regCP_ME_PS_EVENT_DATA_SWM;
+typedef union CP_ME_CF_EVENT_SRC                regCP_ME_CF_EVENT_SRC;
+typedef union CP_ME_CF_EVENT_ADDR               regCP_ME_CF_EVENT_ADDR;
+typedef union CP_ME_CF_EVENT_DATA               regCP_ME_CF_EVENT_DATA;
+typedef union CP_ME_NRT_ADDR                    regCP_ME_NRT_ADDR;
+typedef union CP_ME_NRT_DATA                    regCP_ME_NRT_DATA;
+typedef union CP_ME_VS_FETCH_DONE_SRC           regCP_ME_VS_FETCH_DONE_SRC;
+typedef union CP_ME_VS_FETCH_DONE_ADDR          regCP_ME_VS_FETCH_DONE_ADDR;
+typedef union CP_ME_VS_FETCH_DONE_DATA          regCP_ME_VS_FETCH_DONE_DATA;
+typedef union CP_INT_CNTL                       regCP_INT_CNTL;
+typedef union CP_INT_STATUS                     regCP_INT_STATUS;
+typedef union CP_INT_ACK                        regCP_INT_ACK;
+typedef union CP_PFP_UCODE_ADDR                 regCP_PFP_UCODE_ADDR;
+typedef union CP_PFP_UCODE_DATA                 regCP_PFP_UCODE_DATA;
+typedef union CP_PERFMON_CNTL                   regCP_PERFMON_CNTL;
+typedef union CP_PERFCOUNTER_SELECT             regCP_PERFCOUNTER_SELECT;
+typedef union CP_PERFCOUNTER_LO                 regCP_PERFCOUNTER_LO;
+typedef union CP_PERFCOUNTER_HI                 regCP_PERFCOUNTER_HI;
+typedef union CP_BIN_MASK_LO                    regCP_BIN_MASK_LO;
+typedef union CP_BIN_MASK_HI                    regCP_BIN_MASK_HI;
+typedef union CP_BIN_SELECT_LO                  regCP_BIN_SELECT_LO;
+typedef union CP_BIN_SELECT_HI                  regCP_BIN_SELECT_HI;
+typedef union CP_NV_FLAGS_0                     regCP_NV_FLAGS_0;
+typedef union CP_NV_FLAGS_1                     regCP_NV_FLAGS_1;
+typedef union CP_NV_FLAGS_2                     regCP_NV_FLAGS_2;
+typedef union CP_NV_FLAGS_3                     regCP_NV_FLAGS_3;
+typedef union CP_STATE_DEBUG_INDEX              regCP_STATE_DEBUG_INDEX;
+typedef union CP_STATE_DEBUG_DATA               regCP_STATE_DEBUG_DATA;
+typedef union CP_PROG_COUNTER                   regCP_PROG_COUNTER;
+typedef union CP_STAT                           regCP_STAT;
+typedef union BIOS_0_SCRATCH                    regBIOS_0_SCRATCH;
+typedef union BIOS_1_SCRATCH                    regBIOS_1_SCRATCH;
+typedef union BIOS_2_SCRATCH                    regBIOS_2_SCRATCH;
+typedef union BIOS_3_SCRATCH                    regBIOS_3_SCRATCH;
+typedef union BIOS_4_SCRATCH                    regBIOS_4_SCRATCH;
+typedef union BIOS_5_SCRATCH                    regBIOS_5_SCRATCH;
+typedef union BIOS_6_SCRATCH                    regBIOS_6_SCRATCH;
+typedef union BIOS_7_SCRATCH                    regBIOS_7_SCRATCH;
+typedef union BIOS_8_SCRATCH                    regBIOS_8_SCRATCH;
+typedef union BIOS_9_SCRATCH                    regBIOS_9_SCRATCH;
+typedef union BIOS_10_SCRATCH                   regBIOS_10_SCRATCH;
+typedef union BIOS_11_SCRATCH                   regBIOS_11_SCRATCH;
+typedef union BIOS_12_SCRATCH                   regBIOS_12_SCRATCH;
+typedef union BIOS_13_SCRATCH                   regBIOS_13_SCRATCH;
+typedef union BIOS_14_SCRATCH                   regBIOS_14_SCRATCH;
+typedef union BIOS_15_SCRATCH                   regBIOS_15_SCRATCH;
+typedef union COHER_SIZE_PM4                    regCOHER_SIZE_PM4;
+typedef union COHER_BASE_PM4                    regCOHER_BASE_PM4;
+typedef union COHER_STATUS_PM4                  regCOHER_STATUS_PM4;
+typedef union COHER_SIZE_HOST                   regCOHER_SIZE_HOST;
+typedef union COHER_BASE_HOST                   regCOHER_BASE_HOST;
+typedef union COHER_STATUS_HOST                 regCOHER_STATUS_HOST;
+typedef union COHER_DEST_BASE_0                 regCOHER_DEST_BASE_0;
+typedef union COHER_DEST_BASE_1                 regCOHER_DEST_BASE_1;
+typedef union COHER_DEST_BASE_2                 regCOHER_DEST_BASE_2;
+typedef union COHER_DEST_BASE_3                 regCOHER_DEST_BASE_3;
+typedef union COHER_DEST_BASE_4                 regCOHER_DEST_BASE_4;
+typedef union COHER_DEST_BASE_5                 regCOHER_DEST_BASE_5;
+typedef union COHER_DEST_BASE_6                 regCOHER_DEST_BASE_6;
+typedef union COHER_DEST_BASE_7                 regCOHER_DEST_BASE_7;
+typedef union RB_SURFACE_INFO                   regRB_SURFACE_INFO;
+typedef union RB_COLOR_INFO                     regRB_COLOR_INFO;
+typedef union RB_DEPTH_INFO                     regRB_DEPTH_INFO;
+typedef union RB_STENCILREFMASK                 regRB_STENCILREFMASK;
+typedef union RB_ALPHA_REF                      regRB_ALPHA_REF;
+typedef union RB_COLOR_MASK                     regRB_COLOR_MASK;
+typedef union RB_BLEND_RED                      regRB_BLEND_RED;
+typedef union RB_BLEND_GREEN                    regRB_BLEND_GREEN;
+typedef union RB_BLEND_BLUE                     regRB_BLEND_BLUE;
+typedef union RB_BLEND_ALPHA                    regRB_BLEND_ALPHA;
+typedef union RB_FOG_COLOR                      regRB_FOG_COLOR;
+typedef union RB_STENCILREFMASK_BF              regRB_STENCILREFMASK_BF;
+typedef union RB_DEPTHCONTROL                   regRB_DEPTHCONTROL;
+typedef union RB_BLENDCONTROL                   regRB_BLENDCONTROL;
+typedef union RB_COLORCONTROL                   regRB_COLORCONTROL;
+typedef union RB_MODECONTROL                    regRB_MODECONTROL;
+typedef union RB_COLOR_DEST_MASK                regRB_COLOR_DEST_MASK;
+typedef union RB_COPY_CONTROL                   regRB_COPY_CONTROL;
+typedef union RB_COPY_DEST_BASE                 regRB_COPY_DEST_BASE;
+typedef union RB_COPY_DEST_PITCH                regRB_COPY_DEST_PITCH;
+typedef union RB_COPY_DEST_INFO                 regRB_COPY_DEST_INFO;
+typedef union RB_COPY_DEST_PIXEL_OFFSET         regRB_COPY_DEST_PIXEL_OFFSET;
+typedef union RB_DEPTH_CLEAR                    regRB_DEPTH_CLEAR;
+typedef union RB_SAMPLE_COUNT_CTL               regRB_SAMPLE_COUNT_CTL;
+typedef union RB_SAMPLE_COUNT_ADDR              regRB_SAMPLE_COUNT_ADDR;
+typedef union RB_BC_CONTROL                     regRB_BC_CONTROL;
+typedef union RB_EDRAM_INFO                     regRB_EDRAM_INFO;
+typedef union RB_CRC_RD_PORT                    regRB_CRC_RD_PORT;
+typedef union RB_CRC_CONTROL                    regRB_CRC_CONTROL;
+typedef union RB_CRC_MASK                       regRB_CRC_MASK;
+typedef union RB_PERFCOUNTER0_SELECT            regRB_PERFCOUNTER0_SELECT;
+typedef union RB_PERFCOUNTER0_LOW               regRB_PERFCOUNTER0_LOW;
+typedef union RB_PERFCOUNTER0_HI                regRB_PERFCOUNTER0_HI;
+typedef union RB_TOTAL_SAMPLES                  regRB_TOTAL_SAMPLES;
+typedef union RB_ZPASS_SAMPLES                  regRB_ZPASS_SAMPLES;
+typedef union RB_ZFAIL_SAMPLES                  regRB_ZFAIL_SAMPLES;
+typedef union RB_SFAIL_SAMPLES                  regRB_SFAIL_SAMPLES;
+typedef union RB_DEBUG_0                        regRB_DEBUG_0;
+typedef union RB_DEBUG_1                        regRB_DEBUG_1;
+typedef union RB_DEBUG_2                        regRB_DEBUG_2;
+typedef union RB_DEBUG_3                        regRB_DEBUG_3;
+typedef union RB_DEBUG_4                        regRB_DEBUG_4;
+typedef union RB_FLAG_CONTROL                   regRB_FLAG_CONTROL;
+typedef union BC_DUMMY_CRAYRB_ENUMS             regBC_DUMMY_CRAYRB_ENUMS;
+typedef union BC_DUMMY_CRAYRB_MOREENUMS         regBC_DUMMY_CRAYRB_MOREENUMS;
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h
new file mode 100644
index 000000000000..15cfbebf2907
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h
@@ -0,0 +1,1897 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_ENUM_HEADER)
+#define _yamato_ENUM_HEADER
+
+
+
+#ifndef _DRIVER_BUILD
+#ifndef GL_ZERO
+#define GL__ZERO                      BLEND_ZERO
+#define GL__ONE                       BLEND_ONE
+#define GL__SRC_COLOR                 BLEND_SRC_COLOR
+#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
+#define GL__DST_COLOR                 BLEND_DST_COLOR
+#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
+#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
+#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
+#define GL__DST_ALPHA                 BLEND_DST_ALPHA
+#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
+#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
+#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
+#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
+#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
+#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
+#endif
+#endif
+
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+#ifndef ENUMS_SU_PERFCNT_SELECT_H
+#define ENUMS_SU_PERFCNT_SELECT_H
+typedef enum SU_PERFCNT_SELECT {
+ PERF_PAPC_PASX_REQ = 0,
+ UNUSED1 = 1,
+ PERF_PAPC_PASX_FIRST_VECTOR = 2,
+ PERF_PAPC_PASX_SECOND_VECTOR = 3,
+ PERF_PAPC_PASX_FIRST_DEAD = 4,
+ PERF_PAPC_PASX_SECOND_DEAD = 5,
+ PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
+ PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
+ PERF_PAPC_PA_INPUT_PRIM = 8,
+ PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
+ PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
+ PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
+ PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
+ PERF_PAPC_CLPR_CULL_PRIM = 13,
+ UNUSED2 = 14,
+ PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
+ UNUSED3 = 16,
+ PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
+ PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
+ PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
+ UNUSED4 = 20,
+ PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
+ UNUSED5 = 22,
+ PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
+ PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
+ PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
+ PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
+ PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
+ PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
+ PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
+ PERF_PAPC_CLSM_NULL_PRIM = 36,
+ PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
+ PERF_PAPC_CLSM_CLIP_PRIM = 38,
+ PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
+ PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
+ PERF_PAPC_SU_INPUT_PRIM = 47,
+ PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
+ PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
+ PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
+ PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
+ PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
+ PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
+ PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
+ PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
+ PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
+ PERF_PAPC_SU_OUTPUT_PRIM = 57,
+ PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
+ PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
+ PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
+ PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
+ PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
+ PERF_PAPC_PASX_REQ_IDLE = 69,
+ PERF_PAPC_PASX_REQ_BUSY = 70,
+ PERF_PAPC_PASX_REQ_STALLED = 71,
+ PERF_PAPC_PASX_REC_IDLE = 72,
+ PERF_PAPC_PASX_REC_BUSY = 73,
+ PERF_PAPC_PASX_REC_STARVED_SX = 74,
+ PERF_PAPC_PASX_REC_STALLED = 75,
+ PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
+ PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
+ PERF_PAPC_CCGSM_IDLE = 78,
+ PERF_PAPC_CCGSM_BUSY = 79,
+ PERF_PAPC_CCGSM_STALLED = 80,
+ PERF_PAPC_CLPRIM_IDLE = 81,
+ PERF_PAPC_CLPRIM_BUSY = 82,
+ PERF_PAPC_CLPRIM_STALLED = 83,
+ PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
+ PERF_PAPC_CLIPSM_IDLE = 85,
+ PERF_PAPC_CLIPSM_BUSY = 86,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
+ PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
+ PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
+ PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
+ PERF_PAPC_CLIPGA_IDLE = 92,
+ PERF_PAPC_CLIPGA_BUSY = 93,
+ PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
+ PERF_PAPC_CLIPGA_STALLED = 95,
+ PERF_PAPC_CLIP_IDLE = 96,
+ PERF_PAPC_CLIP_BUSY = 97,
+ PERF_PAPC_SU_IDLE = 98,
+ PERF_PAPC_SU_BUSY = 99,
+ PERF_PAPC_SU_STARVED_CLIP = 100,
+ PERF_PAPC_SU_STALLED_SC = 101,
+ PERF_PAPC_SU_FACENESS_CULL = 102,
+} SU_PERFCNT_SELECT;
+#endif /*ENUMS_SU_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SC_PERFCNT_SELECT_H
+#define ENUMS_SC_PERFCNT_SELECT_H
+typedef enum SC_PERFCNT_SELECT {
+ SC_SR_WINDOW_VALID = 0,
+ SC_CW_WINDOW_VALID = 1,
+ SC_QM_WINDOW_VALID = 2,
+ SC_FW_WINDOW_VALID = 3,
+ SC_EZ_WINDOW_VALID = 4,
+ SC_IT_WINDOW_VALID = 5,
+ SC_STARVED_BY_PA = 6,
+ SC_STALLED_BY_RB_TILE = 7,
+ SC_STALLED_BY_RB_SAMP = 8,
+ SC_STARVED_BY_RB_EZ = 9,
+ SC_STALLED_BY_SAMPLE_FF = 10,
+ SC_STALLED_BY_SQ = 11,
+ SC_STALLED_BY_SP = 12,
+ SC_TOTAL_NO_PRIMS = 13,
+ SC_NON_EMPTY_PRIMS = 14,
+ SC_NO_TILES_PASSING_QM = 15,
+ SC_NO_PIXELS_PRE_EZ = 16,
+ SC_NO_PIXELS_POST_EZ = 17,
+} SC_PERFCNT_SELECT;
+#endif /*ENUMS_SC_PERFCNT_SELECT_H*/
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+#ifndef ENUMS_VGT_DI_PRIM_TYPE_H
+#define ENUMS_VGT_DI_PRIM_TYPE_H
+typedef enum VGT_DI_PRIM_TYPE {
+ DI_PT_NONE = 0,
+ DI_PT_POINTLIST = 1,
+ DI_PT_LINELIST = 2,
+ DI_PT_LINESTRIP = 3,
+ DI_PT_TRILIST = 4,
+ DI_PT_TRIFAN = 5,
+ DI_PT_TRISTRIP = 6,
+ DI_PT_UNUSED_1 = 7,
+ DI_PT_RECTLIST = 8,
+ DI_PT_UNUSED_2 = 9,
+ DI_PT_UNUSED_3 = 10,
+ DI_PT_UNUSED_4 = 11,
+ DI_PT_UNUSED_5 = 12,
+ DI_PT_QUADLIST = 13,
+ DI_PT_QUADSTRIP = 14,
+ DI_PT_POLYGON = 15,
+ DI_PT_2D_COPY_RECT_LIST_V0 = 16,
+ DI_PT_2D_COPY_RECT_LIST_V1 = 17,
+ DI_PT_2D_COPY_RECT_LIST_V2 = 18,
+ DI_PT_2D_COPY_RECT_LIST_V3 = 19,
+ DI_PT_2D_FILL_RECT_LIST = 20,
+ DI_PT_2D_LINE_STRIP = 21,
+ DI_PT_2D_TRI_STRIP = 22,
+} VGT_DI_PRIM_TYPE;
+#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/
+
+#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H
+#define ENUMS_VGT_DI_SOURCE_SELECT_H
+typedef enum VGT_DI_SOURCE_SELECT {
+ DI_SRC_SEL_DMA = 0,
+ DI_SRC_SEL_IMMEDIATE = 1,
+ DI_SRC_SEL_AUTO_INDEX = 2,
+ DI_SRC_SEL_RESERVED = 3
+} VGT_DI_SOURCE_SELECT;
+#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_FACENESS_CULL_SELECT_H
+#define ENUMS_VGT_DI_FACENESS_CULL_SELECT_H
+typedef enum VGT_DI_FACENESS_CULL_SELECT {
+ DI_FACE_CULL_NONE = 0,
+ DI_FACE_CULL_FETCH = 1,
+ DI_FACE_BACKFACE_CULL = 2,
+ DI_FACE_FRONTFACE_CULL = 3
+} VGT_DI_FACENESS_CULL_SELECT;
+#endif /*ENUMS_VGT_DI_FACENESS_CULL_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_INDEX_SIZE_H
+#define ENUMS_VGT_DI_INDEX_SIZE_H
+typedef enum VGT_DI_INDEX_SIZE {
+ DI_INDEX_SIZE_16_BIT = 0,
+ DI_INDEX_SIZE_32_BIT = 1
+} VGT_DI_INDEX_SIZE;
+#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/
+
+#ifndef ENUMS_VGT_DI_SMALL_INDEX_H
+#define ENUMS_VGT_DI_SMALL_INDEX_H
+typedef enum VGT_DI_SMALL_INDEX {
+ DI_USE_INDEX_SIZE = 0,
+ DI_INDEX_SIZE_8_BIT = 1
+} VGT_DI_SMALL_INDEX;
+#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/
+
+#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE {
+ DISABLE_PRE_FETCH_CULL_ENABLE = 0,
+ PRE_FETCH_CULL_ENABLE = 1
+} VGT_DI_PRE_FETCH_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+typedef enum VGT_DI_GRP_CULL_ENABLE {
+ DISABLE_GRP_CULL_ENABLE = 0,
+ GRP_CULL_ENABLE = 1
+} VGT_DI_GRP_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_EVENT_TYPE_H
+#define ENUMS_VGT_EVENT_TYPE_H
+typedef enum VGT_EVENT_TYPE {
+ VS_DEALLOC = 0,
+ PS_DEALLOC = 1,
+ VS_DONE_TS = 2,
+ PS_DONE_TS = 3,
+ CACHE_FLUSH_TS = 4,
+ CONTEXT_DONE = 5,
+ CACHE_FLUSH = 6,
+ VIZQUERY_START = 7,
+ VIZQUERY_END = 8,
+ SC_WAIT_WC = 9,
+ RST_PIX_CNT = 13,
+ RST_VTX_CNT = 14,
+ TILE_FLUSH = 15,
+ CACHE_FLUSH_AND_INV_TS_EVENT = 20,
+ ZPASS_DONE = 21,
+ CACHE_FLUSH_AND_INV_EVENT = 22,
+ PERFCOUNTER_START = 23,
+ PERFCOUNTER_STOP = 24,
+ VS_FETCH_DONE = 27,
+ FACENESS_FLUSH = 28,
+} VGT_EVENT_TYPE;
+#endif /*ENUMS_VGT_EVENT_TYPE_H*/
+
+#ifndef ENUMS_VGT_DMA_SWAP_MODE_H
+#define ENUMS_VGT_DMA_SWAP_MODE_H
+typedef enum VGT_DMA_SWAP_MODE {
+ VGT_DMA_SWAP_NONE = 0,
+ VGT_DMA_SWAP_16_BIT = 1,
+ VGT_DMA_SWAP_32_BIT = 2,
+ VGT_DMA_SWAP_WORD = 3
+} VGT_DMA_SWAP_MODE;
+#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/
+
+#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H
+#define ENUMS_VGT_PERFCOUNT_SELECT_H
+typedef enum VGT_PERFCOUNT_SELECT {
+ VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
+ VGT_SQ_SEND = 1,
+ VGT_SQ_STALLED = 2,
+ VGT_SQ_STARVED_BUSY = 3,
+ VGT_SQ_STARVED_IDLE = 4,
+ VGT_SQ_STATIC = 5,
+ VGT_PA_EVENT_WINDOW_ACTIVE = 6,
+ VGT_PA_CLIP_V_SEND = 7,
+ VGT_PA_CLIP_V_STALLED = 8,
+ VGT_PA_CLIP_V_STARVED_BUSY = 9,
+ VGT_PA_CLIP_V_STARVED_IDLE = 10,
+ VGT_PA_CLIP_V_STATIC = 11,
+ VGT_PA_CLIP_P_SEND = 12,
+ VGT_PA_CLIP_P_STALLED = 13,
+ VGT_PA_CLIP_P_STARVED_BUSY = 14,
+ VGT_PA_CLIP_P_STARVED_IDLE = 15,
+ VGT_PA_CLIP_P_STATIC = 16,
+ VGT_PA_CLIP_S_SEND = 17,
+ VGT_PA_CLIP_S_STALLED = 18,
+ VGT_PA_CLIP_S_STARVED_BUSY = 19,
+ VGT_PA_CLIP_S_STARVED_IDLE = 20,
+ VGT_PA_CLIP_S_STATIC = 21,
+ RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
+ RBIU_IMMED_DATA_FIFO_STARVED = 23,
+ RBIU_IMMED_DATA_FIFO_STALLED = 24,
+ RBIU_DMA_REQUEST_FIFO_STARVED = 25,
+ RBIU_DMA_REQUEST_FIFO_STALLED = 26,
+ RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
+ RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
+ BIN_PRIM_NEAR_CULL = 29,
+ BIN_PRIM_ZERO_CULL = 30,
+ BIN_PRIM_FAR_CULL = 31,
+ BIN_PRIM_BIN_CULL = 32,
+ BIN_PRIM_FACE_CULL = 33,
+ SPARE34 = 34,
+ SPARE35 = 35,
+ SPARE36 = 36,
+ SPARE37 = 37,
+ SPARE38 = 38,
+ SPARE39 = 39,
+ TE_SU_IN_VALID = 40,
+ TE_SU_IN_READ = 41,
+ TE_SU_IN_PRIM = 42,
+ TE_SU_IN_EOP = 43,
+ TE_SU_IN_NULL_PRIM = 44,
+ TE_WK_IN_VALID = 45,
+ TE_WK_IN_READ = 46,
+ TE_OUT_PRIM_VALID = 47,
+ TE_OUT_PRIM_READ = 48,
+} VGT_PERFCOUNT_SELECT;
+#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H
+#define ENUMS_TCR_PERFCOUNT_SELECT_H
+typedef enum TCR_PERFCOUNT_SELECT {
+ DGMMPD_IPMUX0_STALL = 0,
+ reserved_46 = 1,
+ reserved_47 = 2,
+ reserved_48 = 3,
+ DGMMPD_IPMUX_ALL_STALL = 4,
+ OPMUX0_L2_WRITES = 5,
+ reserved_49 = 6,
+ reserved_50 = 7,
+ reserved_51 = 8,
+} TCR_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TP_PERFCOUNT_SELECT_H
+#define ENUMS_TP_PERFCOUNT_SELECT_H
+typedef enum TP_PERFCOUNT_SELECT {
+ POINT_QUADS = 0,
+ BILIN_QUADS = 1,
+ ANISO_QUADS = 2,
+ MIP_QUADS = 3,
+ VOL_QUADS = 4,
+ MIP_VOL_QUADS = 5,
+ MIP_ANISO_QUADS = 6,
+ VOL_ANISO_QUADS = 7,
+ ANISO_2_1_QUADS = 8,
+ ANISO_4_1_QUADS = 9,
+ ANISO_6_1_QUADS = 10,
+ ANISO_8_1_QUADS = 11,
+ ANISO_10_1_QUADS = 12,
+ ANISO_12_1_QUADS = 13,
+ ANISO_14_1_QUADS = 14,
+ ANISO_16_1_QUADS = 15,
+ MIP_VOL_ANISO_QUADS = 16,
+ ALIGN_2_QUADS = 17,
+ ALIGN_4_QUADS = 18,
+ PIX_0_QUAD = 19,
+ PIX_1_QUAD = 20,
+ PIX_2_QUAD = 21,
+ PIX_3_QUAD = 22,
+ PIX_4_QUAD = 23,
+ TP_MIPMAP_LOD0 = 24,
+ TP_MIPMAP_LOD1 = 25,
+ TP_MIPMAP_LOD2 = 26,
+ TP_MIPMAP_LOD3 = 27,
+ TP_MIPMAP_LOD4 = 28,
+ TP_MIPMAP_LOD5 = 29,
+ TP_MIPMAP_LOD6 = 30,
+ TP_MIPMAP_LOD7 = 31,
+ TP_MIPMAP_LOD8 = 32,
+ TP_MIPMAP_LOD9 = 33,
+ TP_MIPMAP_LOD10 = 34,
+ TP_MIPMAP_LOD11 = 35,
+ TP_MIPMAP_LOD12 = 36,
+ TP_MIPMAP_LOD13 = 37,
+ TP_MIPMAP_LOD14 = 38,
+} TP_PERFCOUNT_SELECT;
+#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H
+#define ENUMS_TCM_PERFCOUNT_SELECT_H
+typedef enum TCM_PERFCOUNT_SELECT {
+ QUAD0_RD_LAT_FIFO_EMPTY = 0,
+ reserved_01 = 1,
+ reserved_02 = 2,
+ QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
+ QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
+ QUAD0_RD_LAT_FIFO_FULL = 5,
+ QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
+ reserved_07 = 7,
+ reserved_08 = 8,
+ reserved_09 = 9,
+ reserved_10 = 10,
+ reserved_11 = 11,
+ reserved_12 = 12,
+ reserved_13 = 13,
+ reserved_14 = 14,
+ reserved_15 = 15,
+ reserved_16 = 16,
+ reserved_17 = 17,
+ reserved_18 = 18,
+ reserved_19 = 19,
+ reserved_20 = 20,
+ reserved_21 = 21,
+ reserved_22 = 22,
+ reserved_23 = 23,
+ reserved_24 = 24,
+ reserved_25 = 25,
+ reserved_26 = 26,
+ reserved_27 = 27,
+ READ_STARVED_QUAD0 = 28,
+ reserved_29 = 29,
+ reserved_30 = 30,
+ reserved_31 = 31,
+ READ_STARVED = 32,
+ READ_STALLED_QUAD0 = 33,
+ reserved_34 = 34,
+ reserved_35 = 35,
+ reserved_36 = 36,
+ READ_STALLED = 37,
+ VALID_READ_QUAD0 = 38,
+ reserved_39 = 39,
+ reserved_40 = 40,
+ reserved_41 = 41,
+ TC_TP_STARVED_QUAD0 = 42,
+ reserved_43 = 43,
+ reserved_44 = 44,
+ reserved_45 = 45,
+ TC_TP_STARVED = 46,
+} TCM_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H
+#define ENUMS_TCF_PERFCOUNT_SELECT_H
+typedef enum TCF_PERFCOUNT_SELECT {
+ VALID_CYCLES = 0,
+ SINGLE_PHASES = 1,
+ ANISO_PHASES = 2,
+ MIP_PHASES = 3,
+ VOL_PHASES = 4,
+ MIP_VOL_PHASES = 5,
+ MIP_ANISO_PHASES = 6,
+ VOL_ANISO_PHASES = 7,
+ ANISO_2_1_PHASES = 8,
+ ANISO_4_1_PHASES = 9,
+ ANISO_6_1_PHASES = 10,
+ ANISO_8_1_PHASES = 11,
+ ANISO_10_1_PHASES = 12,
+ ANISO_12_1_PHASES = 13,
+ ANISO_14_1_PHASES = 14,
+ ANISO_16_1_PHASES = 15,
+ MIP_VOL_ANISO_PHASES = 16,
+ ALIGN_2_PHASES = 17,
+ ALIGN_4_PHASES = 18,
+ TPC_BUSY = 19,
+ TPC_STALLED = 20,
+ TPC_STARVED = 21,
+ TPC_WORKING = 22,
+ TPC_WALKER_BUSY = 23,
+ TPC_WALKER_STALLED = 24,
+ TPC_WALKER_WORKING = 25,
+ TPC_ALIGNER_BUSY = 26,
+ TPC_ALIGNER_STALLED = 27,
+ TPC_ALIGNER_STALLED_BY_BLEND = 28,
+ TPC_ALIGNER_STALLED_BY_CACHE = 29,
+ TPC_ALIGNER_WORKING = 30,
+ TPC_BLEND_BUSY = 31,
+ TPC_BLEND_SYNC = 32,
+ TPC_BLEND_STARVED = 33,
+ TPC_BLEND_WORKING = 34,
+ OPCODE_0x00 = 35,
+ OPCODE_0x01 = 36,
+ OPCODE_0x04 = 37,
+ OPCODE_0x10 = 38,
+ OPCODE_0x11 = 39,
+ OPCODE_0x12 = 40,
+ OPCODE_0x13 = 41,
+ OPCODE_0x18 = 42,
+ OPCODE_0x19 = 43,
+ OPCODE_0x1A = 44,
+ OPCODE_OTHER = 45,
+ IN_FIFO_0_EMPTY = 56,
+ IN_FIFO_0_LT_HALF_FULL = 57,
+ IN_FIFO_0_HALF_FULL = 58,
+ IN_FIFO_0_FULL = 59,
+ IN_FIFO_TPC_EMPTY = 72,
+ IN_FIFO_TPC_LT_HALF_FULL = 73,
+ IN_FIFO_TPC_HALF_FULL = 74,
+ IN_FIFO_TPC_FULL = 75,
+ TPC_TC_XFC = 76,
+ TPC_TC_STATE = 77,
+ TC_STALL = 78,
+ QUAD0_TAPS = 79,
+ QUADS = 83,
+ TCA_SYNC_STALL = 84,
+ TAG_STALL = 85,
+ TCB_SYNC_STALL = 88,
+ TCA_VALID = 89,
+ PROBES_VALID = 90,
+ MISS_STALL = 91,
+ FETCH_FIFO_STALL = 92,
+ TCO_STALL = 93,
+ ANY_STALL = 94,
+ TAG_MISSES = 95,
+ TAG_HITS = 96,
+ SUB_TAG_MISSES = 97,
+ SET0_INVALIDATES = 98,
+ SET1_INVALIDATES = 99,
+ SET2_INVALIDATES = 100,
+ SET3_INVALIDATES = 101,
+ SET0_TAG_MISSES = 102,
+ SET1_TAG_MISSES = 103,
+ SET2_TAG_MISSES = 104,
+ SET3_TAG_MISSES = 105,
+ SET0_TAG_HITS = 106,
+ SET1_TAG_HITS = 107,
+ SET2_TAG_HITS = 108,
+ SET3_TAG_HITS = 109,
+ SET0_SUB_TAG_MISSES = 110,
+ SET1_SUB_TAG_MISSES = 111,
+ SET2_SUB_TAG_MISSES = 112,
+ SET3_SUB_TAG_MISSES = 113,
+ SET0_EVICT1 = 114,
+ SET0_EVICT2 = 115,
+ SET0_EVICT3 = 116,
+ SET0_EVICT4 = 117,
+ SET0_EVICT5 = 118,
+ SET0_EVICT6 = 119,
+ SET0_EVICT7 = 120,
+ SET0_EVICT8 = 121,
+ SET1_EVICT1 = 130,
+ SET1_EVICT2 = 131,
+ SET1_EVICT3 = 132,
+ SET1_EVICT4 = 133,
+ SET1_EVICT5 = 134,
+ SET1_EVICT6 = 135,
+ SET1_EVICT7 = 136,
+ SET1_EVICT8 = 137,
+ SET2_EVICT1 = 146,
+ SET2_EVICT2 = 147,
+ SET2_EVICT3 = 148,
+ SET2_EVICT4 = 149,
+ SET2_EVICT5 = 150,
+ SET2_EVICT6 = 151,
+ SET2_EVICT7 = 152,
+ SET2_EVICT8 = 153,
+ SET3_EVICT1 = 162,
+ SET3_EVICT2 = 163,
+ SET3_EVICT3 = 164,
+ SET3_EVICT4 = 165,
+ SET3_EVICT5 = 166,
+ SET3_EVICT6 = 167,
+ SET3_EVICT7 = 168,
+ SET3_EVICT8 = 169,
+ FF_EMPTY = 178,
+ FF_LT_HALF_FULL = 179,
+ FF_HALF_FULL = 180,
+ FF_FULL = 181,
+ FF_XFC = 182,
+ FF_STALLED = 183,
+ FG_MASKS = 184,
+ FG_LEFT_MASKS = 185,
+ FG_LEFT_MASK_STALLED = 186,
+ FG_LEFT_NOT_DONE_STALL = 187,
+ FG_LEFT_FG_STALL = 188,
+ FG_LEFT_SECTORS = 189,
+ FG0_REQUESTS = 195,
+ FG0_STALLED = 196,
+ MEM_REQ512 = 199,
+ MEM_REQ_SENT = 200,
+ MEM_LOCAL_READ_REQ = 202,
+ TC0_MH_STALLED = 203,
+} TCF_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+#ifndef ENUMS_SQ_PERFCNT_SELECT_H
+#define ENUMS_SQ_PERFCNT_SELECT_H
+typedef enum SQ_PERFCNT_SELECT {
+ SQ_PIXEL_VECTORS_SUB = 0,
+ SQ_VERTEX_VECTORS_SUB = 1,
+ SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
+ SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
+ SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
+ SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
+ SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
+ SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
+ SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
+ SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
+ SQ_EXPORT_CYCLES = 10,
+ SQ_ALU_CST_WRITTEN = 11,
+ SQ_TEX_CST_WRITTEN = 12,
+ SQ_ALU_CST_STALL = 13,
+ SQ_ALU_TEX_STALL = 14,
+ SQ_INST_WRITTEN = 15,
+ SQ_BOOLEAN_WRITTEN = 16,
+ SQ_LOOPS_WRITTEN = 17,
+ SQ_PIXEL_SWAP_IN = 18,
+ SQ_PIXEL_SWAP_OUT = 19,
+ SQ_VERTEX_SWAP_IN = 20,
+ SQ_VERTEX_SWAP_OUT = 21,
+ SQ_ALU_VTX_INST_ISSUED = 22,
+ SQ_TEX_VTX_INST_ISSUED = 23,
+ SQ_VC_VTX_INST_ISSUED = 24,
+ SQ_CF_VTX_INST_ISSUED = 25,
+ SQ_ALU_PIX_INST_ISSUED = 26,
+ SQ_TEX_PIX_INST_ISSUED = 27,
+ SQ_VC_PIX_INST_ISSUED = 28,
+ SQ_CF_PIX_INST_ISSUED = 29,
+ SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
+ SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
+ SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
+ SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
+ SQ_ALU_NOPS = 34,
+ SQ_PRED_SKIP = 35,
+ SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
+ SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
+ SQ_SYNC_TEX_STALL_VTX = 38,
+ SQ_SYNC_VC_STALL_VTX = 39,
+ SQ_CONSTANTS_USED_SIMD0 = 40,
+ SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
+ SQ_GPR_STALL_VTX = 42,
+ SQ_GPR_STALL_PIX = 43,
+ SQ_VTX_RS_STALL = 44,
+ SQ_PIX_RS_STALL = 45,
+ SQ_SX_PC_FULL   = 46,
+ SQ_SX_EXP_BUFF_FULL = 47,
+ SQ_SX_POS_BUFF_FULL = 48,
+ SQ_INTERP_QUADS = 49,
+ SQ_INTERP_ACTIVE = 50,
+ SQ_IN_PIXEL_STALL = 51,
+ SQ_IN_VTX_STALL = 52,
+ SQ_VTX_CNT = 53,
+ SQ_VTX_VECTOR2 = 54,
+ SQ_VTX_VECTOR3 = 55,
+ SQ_VTX_VECTOR4 = 56,
+ SQ_PIXEL_VECTOR1 = 57,
+ SQ_PIXEL_VECTOR23 = 58,
+ SQ_PIXEL_VECTOR4 = 59,
+ SQ_CONSTANTS_USED_SIMD1 = 60,
+ SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
+ SQ_SX_MEM_EXP_FULL = 62,
+ SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
+ SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
+ SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
+ SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
+ SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
+ SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68,
+ SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
+ SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70,
+ SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
+ SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
+ SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
+ SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
+ SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
+ SQ_PERFCOUNT_VTX_POP_THREAD = 76,
+ SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
+ SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
+ SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
+ SQ_PERFCOUNT_PIX_POP_THREAD = 80,
+ SQ_SYNC_TEX_STALL_PIX = 81,
+ SQ_SYNC_VC_STALL_PIX = 82,
+ SQ_CONSTANTS_USED_SIMD2 = 83,
+ SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
+ SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85,
+ SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86,
+ SQ_ALU0_FIFO_FULL_SIMD0 = 87,
+ SQ_ALU1_FIFO_FULL_SIMD0 = 88,
+ SQ_ALU0_FIFO_FULL_SIMD1 = 89,
+ SQ_ALU1_FIFO_FULL_SIMD1 = 90,
+ SQ_ALU0_FIFO_FULL_SIMD2 = 91,
+ SQ_ALU1_FIFO_FULL_SIMD2 = 92,
+ SQ_ALU0_FIFO_FULL_SIMD3 = 93,
+ SQ_ALU1_FIFO_FULL_SIMD3 = 94,
+ VC_PERF_STATIC = 95,
+ VC_PERF_STALLED = 96,
+ VC_PERF_STARVED = 97,
+ VC_PERF_SEND = 98,
+ VC_PERF_ACTUAL_STARVED = 99,
+ PIXEL_THREAD_0_ACTIVE   = 100,
+ VERTEX_THREAD_0_ACTIVE  = 101,
+ PIXEL_THREAD_0_NUMBER   = 102,
+ VERTEX_THREAD_0_NUMBER  = 103,
+ VERTEX_EVENT_NUMBER     = 104,
+ PIXEL_EVENT_NUMBER  = 105,
+ PTRBUFF_EF_PUSH = 106,
+ PTRBUFF_EF_POP_EVENT = 107,
+ PTRBUFF_EF_POP_NEW_VTX = 108,
+ PTRBUFF_EF_POP_DEALLOC = 109,
+ PTRBUFF_EF_POP_PVECTOR = 110,
+ PTRBUFF_EF_POP_PVECTOR_X = 111,
+ PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
+ PTRBUFF_PB_DEALLOC = 113,
+ PTRBUFF_PI_STATE_PPB_POP = 114,
+ PTRBUFF_PI_RTR = 115,
+ PTRBUFF_PI_READ_EN = 116,
+ PTRBUFF_PI_BUFF_SWAP = 117,
+ PTRBUFF_SQ_FREE_BUFF = 118,
+ PTRBUFF_SQ_DEC = 119,
+ PTRBUFF_SC_VALID_CNTL_EVENT = 120,
+ PTRBUFF_SC_VALID_IJ_XFER = 121,
+ PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
+ PTRBUFF_QUAL_NEW_VECTOR = 123,
+ PTRBUFF_QUAL_EVENT = 124,
+ PTRBUFF_END_BUFFER = 125,
+ PTRBUFF_FILL_QUAD = 126,
+ VERTS_WRITTEN_SPI = 127,
+ TP_FETCH_INSTR_EXEC = 128,
+ TP_FETCH_INSTR_REQ = 129,
+ TP_DATA_RETURN = 130,
+ SPI_WRITE_CYCLES_SP = 131,
+ SPI_WRITES_SP = 132,
+ SP_ALU_INSTR_EXEC = 133,
+ SP_CONST_ADDR_TO_SQ = 134,
+ SP_PRED_KILLS_TO_SQ = 135,
+ SP_EXPORT_CYCLES_TO_SX = 136,
+ SP_EXPORTS_TO_SX = 137,
+ SQ_CYCLES_ELAPSED = 138,
+ SQ_TCFS_OPT_ALLOC_EXEC = 139,
+ SQ_TCFS_NO_OPT_ALLOC = 140,
+ SQ_ALU0_NO_OPT_ALLOC = 141,
+ SQ_ALU1_NO_OPT_ALLOC = 142,
+ SQ_TCFS_ARB_XFC_CNT = 143,
+ SQ_ALU0_ARB_XFC_CNT = 144,
+ SQ_ALU1_ARB_XFC_CNT = 145,
+ SQ_TCFS_CFS_UPDATE_CNT = 146,
+ SQ_ALU0_CFS_UPDATE_CNT = 147,
+ SQ_ALU1_CFS_UPDATE_CNT = 148,
+ SQ_VTX_PUSH_THREAD_CNT = 149,
+ SQ_VTX_POP_THREAD_CNT = 150,
+ SQ_PIX_PUSH_THREAD_CNT = 151,
+ SQ_PIX_POP_THREAD_CNT = 152,
+ SQ_PIX_TOTAL = 153,
+ SQ_PIX_KILLED = 154,
+} SQ_PERFCNT_SELECT;
+#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SX_PERFCNT_SELECT_H
+#define ENUMS_SX_PERFCNT_SELECT_H
+typedef enum SX_PERFCNT_SELECT {
+ SX_EXPORT_VECTORS = 0,
+ SX_DUMMY_QUADS  = 1,
+ SX_ALPHA_FAIL = 2,
+ SX_RB_QUAD_BUSY = 3,
+ SX_RB_COLOR_BUSY = 4,
+ SX_RB_QUAD_STALL = 5,
+ SX_RB_COLOR_STALL = 6,
+} SX_PERFCNT_SELECT;
+#endif /*ENUMS_SX_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_Abs_modifier_H
+#define ENUMS_Abs_modifier_H
+typedef enum Abs_modifier {
+ NO_ABS_MOD = 0,
+ ABS_MOD = 1
+} Abs_modifier;
+#endif /*ENUMS_Abs_modifier_H*/
+
+#ifndef ENUMS_Exporting_H
+#define ENUMS_Exporting_H
+typedef enum Exporting {
+ NOT_EXPORTING = 0,
+ EXPORTING = 1
+} Exporting;
+#endif /*ENUMS_Exporting_H*/
+
+#ifndef ENUMS_ScalarOpcode_H
+#define ENUMS_ScalarOpcode_H
+typedef enum ScalarOpcode {
+ ADDs = 0,
+ ADD_PREVs = 1,
+ MULs = 2,
+ MUL_PREVs = 3,
+ MUL_PREV2s = 4,
+ MAXs = 5,
+ MINs = 6,
+ SETEs = 7,
+ SETGTs = 8,
+ SETGTEs = 9,
+ SETNEs = 10,
+ FRACs = 11,
+ TRUNCs = 12,
+ FLOORs = 13,
+ EXP_IEEE = 14,
+ LOG_CLAMP = 15,
+ LOG_IEEE = 16,
+ RECIP_CLAMP = 17,
+ RECIP_FF = 18,
+ RECIP_IEEE = 19,
+ RECIPSQ_CLAMP = 20,
+ RECIPSQ_FF = 21,
+ RECIPSQ_IEEE = 22,
+ MOVAs = 23,
+ MOVA_FLOORs = 24,
+ SUBs = 25,
+ SUB_PREVs = 26,
+ PRED_SETEs = 27,
+ PRED_SETNEs = 28,
+ PRED_SETGTs = 29,
+ PRED_SETGTEs = 30,
+ PRED_SET_INVs = 31,
+ PRED_SET_POPs = 32,
+ PRED_SET_CLRs = 33,
+ PRED_SET_RESTOREs = 34,
+ KILLEs = 35,
+ KILLGTs = 36,
+ KILLGTEs = 37,
+ KILLNEs = 38,
+ KILLONEs = 39,
+ SQRT_IEEE = 40,
+ MUL_CONST_0 = 42,
+ MUL_CONST_1 = 43,
+ ADD_CONST_0 = 44,
+ ADD_CONST_1 = 45,
+ SUB_CONST_0 = 46,
+ SUB_CONST_1 = 47,
+ SIN = 48,
+ COS = 49,
+ RETAIN_PREV = 50,
+} ScalarOpcode;
+#endif /*ENUMS_ScalarOpcode_H*/
+
+#ifndef ENUMS_SwizzleType_H
+#define ENUMS_SwizzleType_H
+typedef enum SwizzleType {
+ NO_SWIZZLE = 0,
+ SHIFT_RIGHT_1 = 1,
+ SHIFT_RIGHT_2 = 2,
+ SHIFT_RIGHT_3 = 3
+} SwizzleType;
+#endif /*ENUMS_SwizzleType_H*/
+
+#ifndef ENUMS_InputModifier_H
+#define ENUMS_InputModifier_H
+typedef enum InputModifier {
+ NIL = 0,
+ NEGATE = 1
+} InputModifier;
+#endif /*ENUMS_InputModifier_H*/
+
+#ifndef ENUMS_PredicateSelect_H
+#define ENUMS_PredicateSelect_H
+typedef enum PredicateSelect {
+ NO_PREDICATION = 0,
+ PREDICATE_QUAD = 1,
+ PREDICATED_2 = 2,
+ PREDICATED_3 = 3
+} PredicateSelect;
+#endif /*ENUMS_PredicateSelect_H*/
+
+#ifndef ENUMS_OperandSelect1_H
+#define ENUMS_OperandSelect1_H
+typedef enum OperandSelect1 {
+ ABSOLUTE_REG = 0,
+ RELATIVE_REG = 1
+} OperandSelect1;
+#endif /*ENUMS_OperandSelect1_H*/
+
+#ifndef ENUMS_VectorOpcode_H
+#define ENUMS_VectorOpcode_H
+typedef enum VectorOpcode {
+ ADDv = 0,
+ MULv = 1,
+ MAXv = 2,
+ MINv = 3,
+ SETEv = 4,
+ SETGTv = 5,
+ SETGTEv = 6,
+ SETNEv = 7,
+ FRACv = 8,
+ TRUNCv = 9,
+ FLOORv = 10,
+ MULADDv = 11,
+ CNDEv = 12,
+ CNDGTEv = 13,
+ CNDGTv = 14,
+ DOT4v = 15,
+ DOT3v = 16,
+ DOT2ADDv = 17,
+ CUBEv = 18,
+ MAX4v = 19,
+ PRED_SETE_PUSHv = 20,
+ PRED_SETNE_PUSHv = 21,
+ PRED_SETGT_PUSHv = 22,
+ PRED_SETGTE_PUSHv = 23,
+ KILLEv = 24,
+ KILLGTv = 25,
+ KILLGTEv = 26,
+ KILLNEv = 27,
+ DSTv = 28,
+ MOVAv = 29,
+} VectorOpcode;
+#endif /*ENUMS_VectorOpcode_H*/
+
+#ifndef ENUMS_OperandSelect0_H
+#define ENUMS_OperandSelect0_H
+typedef enum OperandSelect0 {
+ CONSTANT = 0,
+ NON_CONSTANT = 1
+} OperandSelect0;
+#endif /*ENUMS_OperandSelect0_H*/
+
+#ifndef ENUMS_Ressource_type_H
+#define ENUMS_Ressource_type_H
+typedef enum Ressource_type {
+ ALU = 0,
+ TEXTURE = 1
+} Ressource_type;
+#endif /*ENUMS_Ressource_type_H*/
+
+#ifndef ENUMS_Instruction_serial_H
+#define ENUMS_Instruction_serial_H
+typedef enum Instruction_serial {
+ NOT_SERIAL = 0,
+ SERIAL = 1
+} Instruction_serial;
+#endif /*ENUMS_Instruction_serial_H*/
+
+#ifndef ENUMS_VC_type_H
+#define ENUMS_VC_type_H
+typedef enum VC_type {
+ ALU_TP_REQUEST = 0,
+ VC_REQUEST = 1
+} VC_type;
+#endif /*ENUMS_VC_type_H*/
+
+#ifndef ENUMS_Addressing_H
+#define ENUMS_Addressing_H
+typedef enum Addressing {
+ RELATIVE_ADDR = 0,
+ ABSOLUTE_ADDR = 1
+} Addressing;
+#endif /*ENUMS_Addressing_H*/
+
+#ifndef ENUMS_CFOpcode_H
+#define ENUMS_CFOpcode_H
+typedef enum CFOpcode {
+ NOP = 0,
+ EXECUTE = 1,
+ EXECUTE_END = 2,
+ COND_EXECUTE = 3,
+ COND_EXECUTE_END = 4,
+ COND_PRED_EXECUTE = 5,
+ COND_PRED_EXECUTE_END = 6,
+ LOOP_START = 7,
+ LOOP_END = 8,
+ COND_CALL = 9,
+ RETURN = 10,
+ COND_JMP = 11,
+ ALLOCATE = 12,
+ COND_EXECUTE_PRED_CLEAN = 13,
+ COND_EXECUTE_PRED_CLEAN_END = 14,
+ MARK_VS_FETCH_DONE = 15
+} CFOpcode;
+#endif /*ENUMS_CFOpcode_H*/
+
+#ifndef ENUMS_Allocation_type_H
+#define ENUMS_Allocation_type_H
+typedef enum Allocation_type {
+ SQ_NO_ALLOC = 0,
+ SQ_POSITION = 1,
+ SQ_PARAMETER_PIXEL = 2,
+ SQ_MEMORY = 3
+} Allocation_type;
+#endif /*ENUMS_Allocation_type_H*/
+
+#ifndef ENUMS_TexInstOpcode_H
+#define ENUMS_TexInstOpcode_H
+typedef enum TexInstOpcode {
+ TEX_INST_FETCH = 1,
+ TEX_INST_RESERVED_1 = 2,
+ TEX_INST_RESERVED_2 = 3,
+ TEX_INST_RESERVED_3 = 4,
+ TEX_INST_GET_BORDER_COLOR_FRAC = 16,
+ TEX_INST_GET_COMP_TEX_LOD = 17,
+ TEX_INST_GET_GRADIENTS = 18,
+ TEX_INST_GET_WEIGHTS = 19,
+ TEX_INST_SET_TEX_LOD = 24,
+ TEX_INST_SET_GRADIENTS_H = 25,
+ TEX_INST_SET_GRADIENTS_V = 26,
+ TEX_INST_RESERVED_4 = 27,
+} TexInstOpcode;
+#endif /*ENUMS_TexInstOpcode_H*/
+
+#ifndef ENUMS_Addressmode_H
+#define ENUMS_Addressmode_H
+typedef enum Addressmode {
+ LOGICAL = 0,
+ LOOP_RELATIVE = 1
+} Addressmode;
+#endif /*ENUMS_Addressmode_H*/
+
+#ifndef ENUMS_TexCoordDenorm_H
+#define ENUMS_TexCoordDenorm_H
+typedef enum TexCoordDenorm {
+ TEX_COORD_NORMALIZED = 0,
+ TEX_COORD_UNNORMALIZED = 1
+} TexCoordDenorm;
+#endif /*ENUMS_TexCoordDenorm_H*/
+
+#ifndef ENUMS_SrcSel_H
+#define ENUMS_SrcSel_H
+typedef enum SrcSel {
+ SRC_SEL_X = 0,
+ SRC_SEL_Y = 1,
+ SRC_SEL_Z = 2,
+ SRC_SEL_W = 3
+} SrcSel;
+#endif /*ENUMS_SrcSel_H*/
+
+#ifndef ENUMS_DstSel_H
+#define ENUMS_DstSel_H
+typedef enum DstSel {
+ DST_SEL_X = 0,
+ DST_SEL_Y = 1,
+ DST_SEL_Z = 2,
+ DST_SEL_W = 3,
+ DST_SEL_0 = 4,
+ DST_SEL_1 = 5,
+ DST_SEL_RSVD = 6,
+ DST_SEL_MASK = 7
+} DstSel;
+#endif /*ENUMS_DstSel_H*/
+
+#ifndef ENUMS_MagFilter_H
+#define ENUMS_MagFilter_H
+typedef enum MagFilter {
+ MAG_FILTER_POINT = 0,
+ MAG_FILTER_LINEAR = 1,
+ MAG_FILTER_RESERVED_0 = 2,
+ MAG_FILTER_USE_FETCH_CONST = 3
+} MagFilter;
+#endif /*ENUMS_MagFilter_H*/
+
+#ifndef ENUMS_MinFilter_H
+#define ENUMS_MinFilter_H
+typedef enum MinFilter {
+ MIN_FILTER_POINT = 0,
+ MIN_FILTER_LINEAR = 1,
+ MIN_FILTER_RESERVED_0 = 2,
+ MIN_FILTER_USE_FETCH_CONST = 3
+} MinFilter;
+#endif /*ENUMS_MinFilter_H*/
+
+#ifndef ENUMS_MipFilter_H
+#define ENUMS_MipFilter_H
+typedef enum MipFilter {
+ MIP_FILTER_POINT = 0,
+ MIP_FILTER_LINEAR = 1,
+ MIP_FILTER_BASEMAP = 2,
+ MIP_FILTER_USE_FETCH_CONST = 3
+} MipFilter;
+#endif /*ENUMS_MipFilter_H*/
+
+#ifndef ENUMS_AnisoFilter_H
+#define ENUMS_AnisoFilter_H
+typedef enum AnisoFilter {
+ ANISO_FILTER_DISABLED = 0,
+ ANISO_FILTER_MAX_1_1 = 1,
+ ANISO_FILTER_MAX_2_1 = 2,
+ ANISO_FILTER_MAX_4_1 = 3,
+ ANISO_FILTER_MAX_8_1 = 4,
+ ANISO_FILTER_MAX_16_1 = 5,
+ ANISO_FILTER_USE_FETCH_CONST = 7
+} AnisoFilter;
+#endif /*ENUMS_AnisoFilter_H*/
+
+#ifndef ENUMS_ArbitraryFilter_H
+#define ENUMS_ArbitraryFilter_H
+typedef enum ArbitraryFilter {
+ ARBITRARY_FILTER_2X4_SYM = 0,
+ ARBITRARY_FILTER_2X4_ASYM = 1,
+ ARBITRARY_FILTER_4X2_SYM = 2,
+ ARBITRARY_FILTER_4X2_ASYM = 3,
+ ARBITRARY_FILTER_4X4_SYM = 4,
+ ARBITRARY_FILTER_4X4_ASYM = 5,
+ ARBITRARY_FILTER_USE_FETCH_CONST = 7
+} ArbitraryFilter;
+#endif /*ENUMS_ArbitraryFilter_H*/
+
+#ifndef ENUMS_VolMagFilter_H
+#define ENUMS_VolMagFilter_H
+typedef enum VolMagFilter {
+ VOL_MAG_FILTER_POINT = 0,
+ VOL_MAG_FILTER_LINEAR = 1,
+ VOL_MAG_FILTER_USE_FETCH_CONST = 3
+} VolMagFilter;
+#endif /*ENUMS_VolMagFilter_H*/
+
+#ifndef ENUMS_VolMinFilter_H
+#define ENUMS_VolMinFilter_H
+typedef enum VolMinFilter {
+ VOL_MIN_FILTER_POINT = 0,
+ VOL_MIN_FILTER_LINEAR = 1,
+ VOL_MIN_FILTER_USE_FETCH_CONST = 3
+} VolMinFilter;
+#endif /*ENUMS_VolMinFilter_H*/
+
+#ifndef ENUMS_PredSelect_H
+#define ENUMS_PredSelect_H
+typedef enum PredSelect {
+ NOT_PREDICATED = 0,
+ PREDICATED = 1
+} PredSelect;
+#endif /*ENUMS_PredSelect_H*/
+
+#ifndef ENUMS_SampleLocation_H
+#define ENUMS_SampleLocation_H
+typedef enum SampleLocation {
+ SAMPLE_CENTROID = 0,
+ SAMPLE_CENTER = 1
+} SampleLocation;
+#endif /*ENUMS_SampleLocation_H*/
+
+#ifndef ENUMS_VertexMode_H
+#define ENUMS_VertexMode_H
+typedef enum VertexMode {
+ POSITION_1_VECTOR = 0,
+ POSITION_2_VECTORS_UNUSED = 1,
+ POSITION_2_VECTORS_SPRITE = 2,
+ POSITION_2_VECTORS_EDGE = 3,
+ POSITION_2_VECTORS_KILL = 4,
+ POSITION_2_VECTORS_SPRITE_KILL = 5,
+ POSITION_2_VECTORS_EDGE_KILL = 6,
+ MULTIPASS = 7
+} VertexMode;
+#endif /*ENUMS_VertexMode_H*/
+
+#ifndef ENUMS_Sample_Cntl_H
+#define ENUMS_Sample_Cntl_H
+typedef enum Sample_Cntl {
+ CENTROIDS_ONLY = 0,
+ CENTERS_ONLY = 1,
+ CENTROIDS_AND_CENTERS = 2,
+ UNDEF = 3
+} Sample_Cntl;
+#endif /*ENUMS_Sample_Cntl_H*/
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+#ifndef ENUMS_MhPerfEncode_H
+#define ENUMS_MhPerfEncode_H
+typedef enum MhPerfEncode {
+ CP_R0_REQUESTS = 0,
+ CP_R1_REQUESTS = 1,
+ CP_R2_REQUESTS = 2,
+ CP_R3_REQUESTS = 3,
+ CP_R4_REQUESTS = 4,
+ CP_TOTAL_READ_REQUESTS = 5,
+ CP_TOTAL_WRITE_REQUESTS = 6,
+ CP_TOTAL_REQUESTS = 7,
+ CP_DATA_BYTES_WRITTEN = 8,
+ CP_WRITE_CLEAN_RESPONSES = 9,
+ CP_R0_READ_BURSTS_RECEIVED = 10,
+ CP_R1_READ_BURSTS_RECEIVED = 11,
+ CP_R2_READ_BURSTS_RECEIVED = 12,
+ CP_R3_READ_BURSTS_RECEIVED = 13,
+ CP_R4_READ_BURSTS_RECEIVED = 14,
+ CP_TOTAL_READ_BURSTS_RECEIVED = 15,
+ CP_R0_DATA_BEATS_READ = 16,
+ CP_R1_DATA_BEATS_READ = 17,
+ CP_R2_DATA_BEATS_READ = 18,
+ CP_R3_DATA_BEATS_READ = 19,
+ CP_R4_DATA_BEATS_READ = 20,
+ CP_TOTAL_DATA_BEATS_READ = 21,
+ VGT_R0_REQUESTS = 22,
+ VGT_R1_REQUESTS = 23,
+ VGT_TOTAL_REQUESTS = 24,
+ VGT_R0_READ_BURSTS_RECEIVED = 25,
+ VGT_R1_READ_BURSTS_RECEIVED = 26,
+ VGT_TOTAL_READ_BURSTS_RECEIVED = 27,
+ VGT_R0_DATA_BEATS_READ = 28,
+ VGT_R1_DATA_BEATS_READ = 29,
+ VGT_TOTAL_DATA_BEATS_READ = 30,
+ TC_TOTAL_REQUESTS = 31,
+ TC_ROQ_REQUESTS = 32,
+ TC_INFO_SENT = 33,
+ TC_READ_BURSTS_RECEIVED = 34,
+ TC_DATA_BEATS_READ = 35,
+ TCD_BURSTS_READ = 36,
+ RB_REQUESTS = 37,
+ RB_DATA_BYTES_WRITTEN = 38,
+ RB_WRITE_CLEAN_RESPONSES = 39,
+ AXI_READ_REQUESTS_ID_0 = 40,
+ AXI_READ_REQUESTS_ID_1 = 41,
+ AXI_READ_REQUESTS_ID_2 = 42,
+ AXI_READ_REQUESTS_ID_3 = 43,
+ AXI_READ_REQUESTS_ID_4 = 44,
+ AXI_READ_REQUESTS_ID_5 = 45,
+ AXI_READ_REQUESTS_ID_6 = 46,
+ AXI_READ_REQUESTS_ID_7 = 47,
+ AXI_TOTAL_READ_REQUESTS = 48,
+ AXI_WRITE_REQUESTS_ID_0 = 49,
+ AXI_WRITE_REQUESTS_ID_1 = 50,
+ AXI_WRITE_REQUESTS_ID_2 = 51,
+ AXI_WRITE_REQUESTS_ID_3 = 52,
+ AXI_WRITE_REQUESTS_ID_4 = 53,
+ AXI_WRITE_REQUESTS_ID_5 = 54,
+ AXI_WRITE_REQUESTS_ID_6 = 55,
+ AXI_WRITE_REQUESTS_ID_7 = 56,
+ AXI_TOTAL_WRITE_REQUESTS = 57,
+ AXI_TOTAL_REQUESTS_ID_0 = 58,
+ AXI_TOTAL_REQUESTS_ID_1 = 59,
+ AXI_TOTAL_REQUESTS_ID_2 = 60,
+ AXI_TOTAL_REQUESTS_ID_3 = 61,
+ AXI_TOTAL_REQUESTS_ID_4 = 62,
+ AXI_TOTAL_REQUESTS_ID_5 = 63,
+ AXI_TOTAL_REQUESTS_ID_6 = 64,
+ AXI_TOTAL_REQUESTS_ID_7 = 65,
+ AXI_TOTAL_REQUESTS = 66,
+ AXI_READ_CHANNEL_BURSTS_ID_0 = 67,
+ AXI_READ_CHANNEL_BURSTS_ID_1 = 68,
+ AXI_READ_CHANNEL_BURSTS_ID_2 = 69,
+ AXI_READ_CHANNEL_BURSTS_ID_3 = 70,
+ AXI_READ_CHANNEL_BURSTS_ID_4 = 71,
+ AXI_READ_CHANNEL_BURSTS_ID_5 = 72,
+ AXI_READ_CHANNEL_BURSTS_ID_6 = 73,
+ AXI_READ_CHANNEL_BURSTS_ID_7 = 74,
+ AXI_READ_CHANNEL_TOTAL_BURSTS = 75,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83,
+ AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84,
+ AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85,
+ AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86,
+ AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87,
+ AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88,
+ AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89,
+ AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90,
+ AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91,
+ AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92,
+ AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101,
+ AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110,
+ AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111,
+ TOTAL_MMU_MISSES = 112,
+ MMU_READ_MISSES = 113,
+ MMU_WRITE_MISSES = 114,
+ TOTAL_MMU_HITS = 115,
+ MMU_READ_HITS = 116,
+ MMU_WRITE_HITS = 117,
+ SPLIT_MODE_TC_HITS = 118,
+ SPLIT_MODE_TC_MISSES = 119,
+ SPLIT_MODE_NON_TC_HITS = 120,
+ SPLIT_MODE_NON_TC_MISSES = 121,
+ STALL_AWAITING_TLB_MISS_FETCH = 122,
+ MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123,
+ MMU_TLB_MISS_DATA_BEATS_READ = 124,
+ CP_CYCLES_HELD_OFF = 125,
+ VGT_CYCLES_HELD_OFF = 126,
+ TC_CYCLES_HELD_OFF = 127,
+ TC_ROQ_CYCLES_HELD_OFF = 128,
+ TC_CYCLES_HELD_OFF_TCD_FULL = 129,
+ RB_CYCLES_HELD_OFF = 130,
+ TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131,
+ TLB_MISS_CYCLES_HELD_OFF = 132,
+ AXI_READ_REQUEST_HELD_OFF = 133,
+ AXI_WRITE_REQUEST_HELD_OFF = 134,
+ AXI_REQUEST_HELD_OFF = 135,
+ AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136,
+ AXI_WRITE_DATA_HELD_OFF = 137,
+ CP_SAME_PAGE_BANK_REQUESTS = 138,
+ VGT_SAME_PAGE_BANK_REQUESTS = 139,
+ TC_SAME_PAGE_BANK_REQUESTS = 140,
+ TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141,
+ RB_SAME_PAGE_BANK_REQUESTS = 142,
+ TOTAL_SAME_PAGE_BANK_REQUESTS = 143,
+ CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144,
+ VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145,
+ TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146,
+ RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147,
+ TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148,
+ TOTAL_MH_READ_REQUESTS = 149,
+ TOTAL_MH_WRITE_REQUESTS = 150,
+ TOTAL_MH_REQUESTS = 151,
+ MH_BUSY = 152,
+ CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153,
+ VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154,
+ TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155,
+ RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156,
+ TC_ROQ_N_VALID_ENTRIES = 157,
+ ARQ_N_ENTRIES = 158,
+ WDB_N_ENTRIES = 159,
+ MH_READ_LATENCY_OUTST_REQ_SUM = 160,
+ MC_READ_LATENCY_OUTST_REQ_SUM = 161,
+ MC_TOTAL_READ_REQUESTS = 162,
+ ELAPSED_CYCLES_MH_GATED_CLK = 163,
+ ELAPSED_CLK_CYCLES = 164,
+ CP_W_16B_REQUESTS = 165,
+ CP_W_32B_REQUESTS = 166,
+ TC_16B_REQUESTS = 167,
+ TC_32B_REQUESTS = 168,
+ PA_REQUESTS = 169,
+ PA_DATA_BYTES_WRITTEN = 170,
+ PA_WRITE_CLEAN_RESPONSES = 171,
+ PA_CYCLES_HELD_OFF = 172,
+ AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173,
+ AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174,
+ AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175,
+ AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176,
+ AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177,
+ AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178,
+ AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179,
+ AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180,
+ AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181,
+} MhPerfEncode;
+#endif /*ENUMS_MhPerfEncode_H*/
+
+#ifndef ENUMS_MmuClntBeh_H
+#define ENUMS_MmuClntBeh_H
+typedef enum MmuClntBeh {
+ BEH_NEVR = 0,
+ BEH_TRAN_RNG = 1,
+ BEH_TRAN_FLT = 2,
+} MmuClntBeh;
+#endif /*ENUMS_MmuClntBeh_H*/
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H
+#define ENUMS_RBBM_PERFCOUNT1_SEL_H
+typedef enum RBBM_PERFCOUNT1_SEL {
+ RBBM1_COUNT = 0,
+ RBBM1_NRT_BUSY = 1,
+ RBBM1_RB_BUSY = 2,
+ RBBM1_SQ_CNTX0_BUSY = 3,
+ RBBM1_SQ_CNTX17_BUSY = 4,
+ RBBM1_VGT_BUSY = 5,
+ RBBM1_VGT_NODMA_BUSY = 6,
+ RBBM1_PA_BUSY = 7,
+ RBBM1_SC_CNTX_BUSY = 8,
+ RBBM1_TPC_BUSY = 9,
+ RBBM1_TC_BUSY = 10,
+ RBBM1_SX_BUSY = 11,
+ RBBM1_CP_COHER_BUSY = 12,
+ RBBM1_CP_NRT_BUSY = 13,
+ RBBM1_GFX_IDLE_STALL = 14,
+ RBBM1_INTERRUPT = 15,
+} RBBM_PERFCOUNT1_SEL;
+#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+#ifndef ENUMS_CP_PERFCOUNT_SEL_H
+#define ENUMS_CP_PERFCOUNT_SEL_H
+typedef enum CP_PERFCOUNT_SEL {
+ ALWAYS_COUNT = 0,
+ TRANS_FIFO_FULL = 1,
+ TRANS_FIFO_AF = 2,
+ RCIU_PFPTRANS_WAIT = 3,
+ Reserved_04 = 4,
+ Reserved_05 = 5,
+ RCIU_NRTTRANS_WAIT = 6,
+ Reserved_07 = 7,
+ CSF_NRT_READ_WAIT = 8,
+ CSF_I1_FIFO_FULL = 9,
+ CSF_I2_FIFO_FULL = 10,
+ CSF_ST_FIFO_FULL = 11,
+ Reserved_12 = 12,
+ CSF_RING_ROQ_FULL = 13,
+ CSF_I1_ROQ_FULL = 14,
+ CSF_I2_ROQ_FULL = 15,
+ CSF_ST_ROQ_FULL = 16,
+ Reserved_17 = 17,
+ MIU_TAG_MEM_FULL = 18,
+ MIU_WRITECLEAN = 19,
+ Reserved_20 = 20,
+ Reserved_21 = 21,
+ MIU_NRT_WRITE_STALLED = 22,
+ MIU_NRT_READ_STALLED = 23,
+ ME_WRITE_CONFIRM_FIFO_FULL = 24,
+ ME_VS_DEALLOC_FIFO_FULL = 25,
+ ME_PS_DEALLOC_FIFO_FULL = 26,
+ ME_REGS_VS_EVENT_FIFO_FULL = 27,
+ ME_REGS_PS_EVENT_FIFO_FULL = 28,
+ ME_REGS_CF_EVENT_FIFO_FULL = 29,
+ ME_MICRO_RB_STARVED = 30,
+ ME_MICRO_I1_STARVED = 31,
+ ME_MICRO_I2_STARVED = 32,
+ ME_MICRO_ST_STARVED = 33,
+ Reserved_34 = 34,
+ Reserved_35 = 35,
+ Reserved_36 = 36,
+ Reserved_37 = 37,
+ Reserved_38 = 38,
+ Reserved_39 = 39,
+ RCIU_RBBM_DWORD_SENT = 40,
+ ME_BUSY_CLOCKS = 41,
+ ME_WAIT_CONTEXT_AVAIL = 42,
+ PFP_TYPE0_PACKET = 43,
+ PFP_TYPE3_PACKET = 44,
+ CSF_RB_WPTR_NEQ_RPTR = 45,
+ CSF_I1_SIZE_NEQ_ZERO = 46,
+ CSF_I2_SIZE_NEQ_ZERO = 47,
+ CSF_RBI1I2_FETCHING = 48,
+ Reserved_49 = 49,
+ Reserved_50 = 50,
+ Reserved_51 = 51,
+ Reserved_52 = 52,
+ Reserved_53 = 53,
+ Reserved_54 = 54,
+ Reserved_55 = 55,
+ Reserved_56 = 56,
+ Reserved_57 = 57,
+ Reserved_58 = 58,
+ Reserved_59 = 59,
+ Reserved_60 = 60,
+ Reserved_61 = 61,
+ Reserved_62 = 62,
+ Reserved_63 = 63
+} CP_PERFCOUNT_SEL;
+#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+#ifndef ENUMS_ColorformatX_H
+#define ENUMS_ColorformatX_H
+typedef enum ColorformatX {
+ COLORX_4_4_4_4 = 0,
+ COLORX_1_5_5_5 = 1,
+ COLORX_5_6_5 = 2,
+ COLORX_8 = 3,
+ COLORX_8_8 = 4,
+ COLORX_8_8_8_8 = 5,
+ COLORX_S8_8_8_8 = 6,
+ COLORX_16_FLOAT = 7,
+ COLORX_16_16_FLOAT = 8,
+ COLORX_16_16_16_16_FLOAT = 9,
+ COLORX_32_FLOAT = 10,
+ COLORX_32_32_FLOAT = 11,
+ COLORX_32_32_32_32_FLOAT = 12,
+ COLORX_2_3_3 = 13,
+ COLORX_8_8_8 = 14,
+} ColorformatX;
+#endif /*ENUMS_ColorformatX_H*/
+
+#ifndef ENUMS_DepthformatX_H
+#define ENUMS_DepthformatX_H
+typedef enum DepthformatX {
+ DEPTHX_16 = 0,
+ DEPTHX_24_8 = 1
+} DepthformatX;
+#endif /*ENUMS_DepthformatX_H*/
+
+#ifndef ENUMS_CompareFrag_H
+#define ENUMS_CompareFrag_H
+typedef enum CompareFrag {
+ FRAG_NEVER = 0,
+ FRAG_LESS = 1,
+ FRAG_EQUAL = 2,
+ FRAG_LEQUAL = 3,
+ FRAG_GREATER = 4,
+ FRAG_NOTEQUAL = 5,
+ FRAG_GEQUAL = 6,
+ FRAG_ALWAYS = 7
+} CompareFrag;
+#endif /*ENUMS_CompareFrag_H*/
+
+#ifndef ENUMS_CompareRef_H
+#define ENUMS_CompareRef_H
+typedef enum CompareRef {
+ REF_NEVER = 0,
+ REF_LESS = 1,
+ REF_EQUAL = 2,
+ REF_LEQUAL = 3,
+ REF_GREATER = 4,
+ REF_NOTEQUAL = 5,
+ REF_GEQUAL = 6,
+ REF_ALWAYS = 7
+} CompareRef;
+#endif /*ENUMS_CompareRef_H*/
+
+#ifndef ENUMS_StencilOp_H
+#define ENUMS_StencilOp_H
+typedef enum StencilOp {
+ STENCIL_KEEP = 0,
+ STENCIL_ZERO = 1,
+ STENCIL_REPLACE = 2,
+ STENCIL_INCR_CLAMP = 3,
+ STENCIL_DECR_CLAMP = 4,
+ STENCIL_INVERT = 5,
+ STENCIL_INCR_WRAP = 6,
+ STENCIL_DECR_WRAP = 7
+} StencilOp;
+#endif /*ENUMS_StencilOp_H*/
+
+#ifndef ENUMS_BlendOpX_H
+#define ENUMS_BlendOpX_H
+typedef enum BlendOpX {
+ BLENDX_ZERO = 0,
+ BLENDX_ONE = 1,
+ BLENDX_SRC_COLOR = 4,
+ BLENDX_ONE_MINUS_SRC_COLOR = 5,
+ BLENDX_SRC_ALPHA = 6,
+ BLENDX_ONE_MINUS_SRC_ALPHA = 7,
+ BLENDX_DST_COLOR = 8,
+ BLENDX_ONE_MINUS_DST_COLOR = 9,
+ BLENDX_DST_ALPHA = 10,
+ BLENDX_ONE_MINUS_DST_ALPHA = 11,
+ BLENDX_CONSTANT_COLOR = 12,
+ BLENDX_ONE_MINUS_CONSTANT_COLOR = 13,
+ BLENDX_CONSTANT_ALPHA = 14,
+ BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15,
+ BLENDX_SRC_ALPHA_SATURATE = 16,
+} BlendOpX;
+#endif /*ENUMS_BlendOpX_H*/
+
+#ifndef ENUMS_CombFuncX_H
+#define ENUMS_CombFuncX_H
+typedef enum CombFuncX {
+ COMB_DST_PLUS_SRC = 0,
+ COMB_SRC_MINUS_DST = 1,
+ COMB_MIN_DST_SRC = 2,
+ COMB_MAX_DST_SRC = 3,
+ COMB_DST_MINUS_SRC = 4,
+ COMB_DST_PLUS_SRC_BIAS = 5,
+} CombFuncX;
+#endif /*ENUMS_CombFuncX_H*/
+
+#ifndef ENUMS_DitherModeX_H
+#define ENUMS_DitherModeX_H
+typedef enum DitherModeX {
+ DITHER_DISABLE = 0,
+ DITHER_ALWAYS = 1,
+ DITHER_IF_ALPHA_OFF = 2,
+} DitherModeX;
+#endif /*ENUMS_DitherModeX_H*/
+
+#ifndef ENUMS_DitherTypeX_H
+#define ENUMS_DitherTypeX_H
+typedef enum DitherTypeX {
+ DITHER_PIXEL = 0,
+ DITHER_SUBPIXEL = 1,
+} DitherTypeX;
+#endif /*ENUMS_DitherTypeX_H*/
+
+#ifndef ENUMS_EdramMode_H
+#define ENUMS_EdramMode_H
+typedef enum EdramMode {
+ EDRAM_NOP = 0,
+ COLOR_DEPTH = 4,
+ DEPTH_ONLY = 5,
+ EDRAM_COPY = 6,
+} EdramMode;
+#endif /*ENUMS_EdramMode_H*/
+
+#ifndef ENUMS_SurfaceEndian_H
+#define ENUMS_SurfaceEndian_H
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0,
+ ENDIAN_8IN16 = 1,
+ ENDIAN_8IN32 = 2,
+ ENDIAN_16IN32 = 3,
+ ENDIAN_8IN64 = 4,
+ ENDIAN_8IN128 = 5,
+} SurfaceEndian;
+#endif /*ENUMS_SurfaceEndian_H*/
+
+#ifndef ENUMS_EdramSizeX_H
+#define ENUMS_EdramSizeX_H
+typedef enum EdramSizeX {
+ EDRAMSIZE_16KB = 0,
+ EDRAMSIZE_32KB = 1,
+ EDRAMSIZE_64KB = 2,
+ EDRAMSIZE_128KB = 3,
+ EDRAMSIZE_256KB = 4,
+ EDRAMSIZE_512KB = 5,
+ EDRAMSIZE_1MB = 6,
+ EDRAMSIZE_2MB = 7,
+ EDRAMSIZE_4MB = 8,
+ EDRAMSIZE_8MB = 9,
+ EDRAMSIZE_16MB = 10,
+} EdramSizeX;
+#endif /*ENUMS_EdramSizeX_H*/
+
+#ifndef ENUMS_RB_PERFCNT_SELECT_H
+#define ENUMS_RB_PERFCNT_SELECT_H
+typedef enum RB_PERFCNT_SELECT {
+ RBPERF_CNTX_BUSY = 0,
+ RBPERF_CNTX_BUSY_MAX = 1,
+ RBPERF_SX_QUAD_STARVED = 2,
+ RBPERF_SX_QUAD_STARVED_MAX = 3,
+ RBPERF_GA_GC_CH0_SYS_REQ = 4,
+ RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
+ RBPERF_GA_GC_CH1_SYS_REQ = 6,
+ RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
+ RBPERF_MH_STARVED = 8,
+ RBPERF_MH_STARVED_MAX = 9,
+ RBPERF_AZ_BC_COLOR_BUSY = 10,
+ RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
+ RBPERF_AZ_BC_Z_BUSY = 12,
+ RBPERF_AZ_BC_Z_BUSY_MAX = 13,
+ RBPERF_RB_SC_TILE_RTR_N = 14,
+ RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
+ RBPERF_RB_SC_SAMP_RTR_N = 16,
+ RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
+ RBPERF_RB_SX_QUAD_RTR_N = 18,
+ RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
+ RBPERF_RB_SX_COLOR_RTR_N = 20,
+ RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
+ RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
+ RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
+ RBPERF_ZXP_STALL = 24,
+ RBPERF_ZXP_STALL_MAX = 25,
+ RBPERF_EVENT_PENDING = 26,
+ RBPERF_EVENT_PENDING_MAX = 27,
+ RBPERF_RB_MH_VALID = 28,
+ RBPERF_RB_MH_VALID_MAX = 29,
+ RBPERF_SX_RB_QUAD_SEND = 30,
+ RBPERF_SX_RB_COLOR_SEND = 31,
+ RBPERF_SC_RB_TILE_SEND = 32,
+ RBPERF_SC_RB_SAMPLE_SEND = 33,
+ RBPERF_SX_RB_MEM_EXPORT = 34,
+ RBPERF_SX_RB_QUAD_EVENT = 35,
+ RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
+ RBPERF_SC_RB_TILE_EVENT_ALL = 37,
+ RBPERF_RB_SC_EZ_SEND = 38,
+ RBPERF_RB_SX_INDEX_SEND = 39,
+ RBPERF_GMEM_INTFO_RD = 40,
+ RBPERF_GMEM_INTF1_RD = 41,
+ RBPERF_GMEM_INTFO_WR = 42,
+ RBPERF_GMEM_INTF1_WR = 43,
+ RBPERF_RB_CP_CONTEXT_DONE = 44,
+ RBPERF_RB_CP_CACHE_FLUSH = 45,
+ RBPERF_ZPASS_DONE = 46,
+ RBPERF_ZCMD_VALID = 47,
+ RBPERF_CCMD_VALID = 48,
+ RBPERF_ACCUM_GRANT = 49,
+ RBPERF_ACCUM_C0_GRANT = 50,
+ RBPERF_ACCUM_C1_GRANT = 51,
+ RBPERF_ACCUM_FULL_BE_WR = 52,
+ RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
+ RBPERF_ACCUM_TIMEOUT_PULSE = 54,
+ RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
+ RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
+} RB_PERFCNT_SELECT;
+#endif /*ENUMS_RB_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_DepthFormat_H
+#define ENUMS_DepthFormat_H
+typedef enum DepthFormat {
+ DEPTH_24_8 = 22,
+ DEPTH_24_8_FLOAT = 23,
+ DEPTH_16 = 24,
+} DepthFormat;
+#endif /*ENUMS_DepthFormat_H*/
+
+#ifndef ENUMS_SurfaceSwap_H
+#define ENUMS_SurfaceSwap_H
+typedef enum SurfaceSwap {
+ SWAP_LOWRED = 0,
+ SWAP_LOWBLUE = 1
+} SurfaceSwap;
+#endif /*ENUMS_SurfaceSwap_H*/
+
+#ifndef ENUMS_DepthArray_H
+#define ENUMS_DepthArray_H
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0,
+ ARRAY_2D_DEPTH = 1,
+} DepthArray;
+#endif /*ENUMS_DepthArray_H*/
+
+#ifndef ENUMS_ColorArray_H
+#define ENUMS_ColorArray_H
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0,
+ ARRAY_2D_COLOR = 1,
+ ARRAY_3D_SLICE_COLOR = 3
+} ColorArray;
+#endif /*ENUMS_ColorArray_H*/
+
+#ifndef ENUMS_ColorFormat_H
+#define ENUMS_ColorFormat_H
+typedef enum ColorFormat {
+ COLOR_8 = 2,
+ COLOR_1_5_5_5 = 3,
+ COLOR_5_6_5 = 4,
+ COLOR_6_5_5 = 5,
+ COLOR_8_8_8_8 = 6,
+ COLOR_2_10_10_10 = 7,
+ COLOR_8_A = 8,
+ COLOR_8_B = 9,
+ COLOR_8_8 = 10,
+ COLOR_8_8_8 = 11,
+ COLOR_8_8_8_8_A = 14,
+ COLOR_4_4_4_4 = 15,
+ COLOR_10_11_11 = 16,
+ COLOR_11_11_10 = 17,
+ COLOR_16 = 24,
+ COLOR_16_16 = 25,
+ COLOR_16_16_16_16 = 26,
+ COLOR_16_FLOAT = 30,
+ COLOR_16_16_FLOAT = 31,
+ COLOR_16_16_16_16_FLOAT = 32,
+ COLOR_32_FLOAT = 36,
+ COLOR_32_32_FLOAT = 37,
+ COLOR_32_32_32_32_FLOAT = 38,
+ COLOR_2_3_3 = 39,
+} ColorFormat;
+#endif /*ENUMS_ColorFormat_H*/
+
+#ifndef ENUMS_SurfaceNumber_H
+#define ENUMS_SurfaceNumber_H
+typedef enum SurfaceNumber {
+ NUMBER_UREPEAT = 0,
+ NUMBER_SREPEAT = 1,
+ NUMBER_UINTEGER = 2,
+ NUMBER_SINTEGER = 3,
+ NUMBER_GAMMA = 4,
+ NUMBER_FIXED = 5,
+ NUMBER_FLOAT = 7
+} SurfaceNumber;
+#endif /*ENUMS_SurfaceNumber_H*/
+
+#ifndef ENUMS_SurfaceFormat_H
+#define ENUMS_SurfaceFormat_H
+typedef enum SurfaceFormat {
+ FMT_1_REVERSE = 0,
+ FMT_1 = 1,
+ FMT_8 = 2,
+ FMT_1_5_5_5 = 3,
+ FMT_5_6_5 = 4,
+ FMT_6_5_5 = 5,
+ FMT_8_8_8_8 = 6,
+ FMT_2_10_10_10 = 7,
+ FMT_8_A = 8,
+ FMT_8_B = 9,
+ FMT_8_8 = 10,
+ FMT_Cr_Y1_Cb_Y0 = 11,
+ FMT_Y1_Cr_Y0_Cb = 12,
+ FMT_5_5_5_1 = 13,
+ FMT_8_8_8_8_A = 14,
+ FMT_4_4_4_4 = 15,
+ FMT_8_8_8 = 16,
+ FMT_DXT1 = 18,
+ FMT_DXT2_3 = 19,
+ FMT_DXT4_5 = 20,
+ FMT_10_10_10_2 = 21,
+ FMT_24_8 = 22,
+ FMT_16 = 24,
+ FMT_16_16 = 25,
+ FMT_16_16_16_16 = 26,
+ FMT_16_EXPAND = 27,
+ FMT_16_16_EXPAND = 28,
+ FMT_16_16_16_16_EXPAND = 29,
+ FMT_16_FLOAT = 30,
+ FMT_16_16_FLOAT = 31,
+ FMT_16_16_16_16_FLOAT = 32,
+ FMT_32 = 33,
+ FMT_32_32 = 34,
+ FMT_32_32_32_32 = 35,
+ FMT_32_FLOAT = 36,
+ FMT_32_32_FLOAT = 37,
+ FMT_32_32_32_32_FLOAT = 38,
+ FMT_ATI_TC_RGB = 39,
+ FMT_ATI_TC_RGBA = 40,
+ FMT_ATI_TC_555_565_RGB = 41,
+ FMT_ATI_TC_555_565_RGBA = 42,
+ FMT_ATI_TC_RGBA_INTERP = 43,
+ FMT_ATI_TC_555_565_RGBA_INTERP = 44,
+ FMT_ETC1_RGBA_INTERP = 46,
+ FMT_ETC1_RGB = 47,
+ FMT_ETC1_RGBA = 48,
+ FMT_DXN = 49,
+ FMT_2_3_3 = 51,
+ FMT_2_10_10_10_AS_16_16_16_16 = 54,
+ FMT_10_10_10_2_AS_16_16_16_16 = 55,
+ FMT_32_32_32_FLOAT = 57,
+ FMT_DXT3A = 58,
+ FMT_DXT5A = 59,
+ FMT_CTX1 = 60,
+} SurfaceFormat;
+#endif /*ENUMS_SurfaceFormat_H*/
+
+#ifndef ENUMS_SurfaceTiling_H
+#define ENUMS_SurfaceTiling_H
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0,
+ ARRAY_TILED = 1
+} SurfaceTiling;
+#endif /*ENUMS_SurfaceTiling_H*/
+
+#ifndef ENUMS_SurfaceArray_H
+#define ENUMS_SurfaceArray_H
+typedef enum SurfaceArray {
+ ARRAY_1D = 0,
+ ARRAY_2D = 1,
+ ARRAY_3D = 2,
+ ARRAY_3D_SLICE = 3
+} SurfaceArray;
+#endif /*ENUMS_SurfaceArray_H*/
+
+#ifndef ENUMS_SurfaceNumberX_H
+#define ENUMS_SurfaceNumberX_H
+typedef enum SurfaceNumberX {
+ NUMBERX_UREPEAT = 0,
+ NUMBERX_SREPEAT = 1,
+ NUMBERX_UINTEGER = 2,
+ NUMBERX_SINTEGER = 3,
+ NUMBERX_FLOAT = 7
+} SurfaceNumberX;
+#endif /*ENUMS_SurfaceNumberX_H*/
+
+#ifndef ENUMS_ColorArrayX_H
+#define ENUMS_ColorArrayX_H
+typedef enum ColorArrayX {
+ ARRAYX_2D_COLOR = 0,
+ ARRAYX_3D_SLICE_COLOR = 1,
+} ColorArrayX;
+#endif /*ENUMS_ColorArrayX_H*/
+
+#endif /*_yamato_ENUM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h
new file mode 100644
index 000000000000..87a454a1e38a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h
@@ -0,0 +1,1703 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_ENUMTYPE(SU_PERFCNT_SELECT)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0)
+    GENERATE_ENUM(UNUSED1, 1)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13)
+    GENERATE_ENUM(UNUSED2, 14)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15)
+    GENERATE_ENUM(UNUSED3, 16)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19)
+    GENERATE_ENUM(UNUSED4, 20)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21)
+    GENERATE_ENUM(UNUSED5, 22)
+    GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36)
+    GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49)
+    GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50)
+    GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51)
+    GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95)
+    GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96)
+    GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97)
+    GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98)
+    GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99)
+    GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100)
+    GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101)
+    GENERATE_ENUM(PERF_PAPC_SU_FACENESS_CULL, 102)
+END_ENUMTYPE(SU_PERFCNT_SELECT)
+
+START_ENUMTYPE(SC_PERFCNT_SELECT)
+    GENERATE_ENUM(SC_SR_WINDOW_VALID, 0)
+    GENERATE_ENUM(SC_CW_WINDOW_VALID, 1)
+    GENERATE_ENUM(SC_QM_WINDOW_VALID, 2)
+    GENERATE_ENUM(SC_FW_WINDOW_VALID, 3)
+    GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4)
+    GENERATE_ENUM(SC_IT_WINDOW_VALID, 5)
+    GENERATE_ENUM(SC_STARVED_BY_PA, 6)
+    GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7)
+    GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8)
+    GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9)
+    GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10)
+    GENERATE_ENUM(SC_STALLED_BY_SQ, 11)
+    GENERATE_ENUM(SC_STALLED_BY_SP, 12)
+    GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13)
+    GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14)
+    GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15)
+    GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16)
+    GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17)
+END_ENUMTYPE(SC_PERFCNT_SELECT)
+
+START_ENUMTYPE(VGT_DI_PRIM_TYPE)
+    GENERATE_ENUM(DI_PT_NONE, 0)
+    GENERATE_ENUM(DI_PT_POINTLIST, 1)
+    GENERATE_ENUM(DI_PT_LINELIST, 2)
+    GENERATE_ENUM(DI_PT_LINESTRIP, 3)
+    GENERATE_ENUM(DI_PT_TRILIST, 4)
+    GENERATE_ENUM(DI_PT_TRIFAN, 5)
+    GENERATE_ENUM(DI_PT_TRISTRIP, 6)
+    GENERATE_ENUM(DI_PT_UNUSED_1, 7)
+    GENERATE_ENUM(DI_PT_RECTLIST, 8)
+    GENERATE_ENUM(DI_PT_UNUSED_2, 9)
+    GENERATE_ENUM(DI_PT_UNUSED_3, 10)
+    GENERATE_ENUM(DI_PT_UNUSED_4, 11)
+    GENERATE_ENUM(DI_PT_UNUSED_5, 12)
+    GENERATE_ENUM(DI_PT_QUADLIST, 13)
+    GENERATE_ENUM(DI_PT_QUADSTRIP, 14)
+    GENERATE_ENUM(DI_PT_POLYGON, 15)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19)
+    GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20)
+    GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21)
+    GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22)
+END_ENUMTYPE(VGT_DI_PRIM_TYPE)
+
+START_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+    GENERATE_ENUM(DI_SRC_SEL_DMA, 0)
+    GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1)
+    GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2)
+    GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3)
+END_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+
+START_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT)
+    GENERATE_ENUM(DI_FACE_CULL_NONE, 0)
+    GENERATE_ENUM(DI_FACE_CULL_FETCH, 1)
+    GENERATE_ENUM(DI_FACE_BACKFACE_CULL, 2)
+    GENERATE_ENUM(DI_FACE_FRONTFACE_CULL, 3)
+END_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT)
+
+START_ENUMTYPE(VGT_DI_INDEX_SIZE)
+    GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1)
+END_ENUMTYPE(VGT_DI_INDEX_SIZE)
+
+START_ENUMTYPE(VGT_DI_SMALL_INDEX)
+    GENERATE_ENUM(DI_USE_INDEX_SIZE, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1)
+END_ENUMTYPE(VGT_DI_SMALL_INDEX)
+
+START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0)
+    GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0)
+    GENERATE_ENUM(GRP_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_EVENT_TYPE)
+    GENERATE_ENUM(VS_DEALLOC, 0)
+    GENERATE_ENUM(PS_DEALLOC, 1)
+    GENERATE_ENUM(VS_DONE_TS, 2)
+    GENERATE_ENUM(PS_DONE_TS, 3)
+    GENERATE_ENUM(CACHE_FLUSH_TS, 4)
+    GENERATE_ENUM(CONTEXT_DONE, 5)
+    GENERATE_ENUM(CACHE_FLUSH, 6)
+    GENERATE_ENUM(VIZQUERY_START, 7)
+    GENERATE_ENUM(VIZQUERY_END, 8)
+    GENERATE_ENUM(SC_WAIT_WC, 9)
+    GENERATE_ENUM(RST_PIX_CNT, 13)
+    GENERATE_ENUM(RST_VTX_CNT, 14)
+    GENERATE_ENUM(TILE_FLUSH, 15)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20)
+    GENERATE_ENUM(ZPASS_DONE, 21)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22)
+    GENERATE_ENUM(PERFCOUNTER_START, 23)
+    GENERATE_ENUM(PERFCOUNTER_STOP, 24)
+    GENERATE_ENUM(VS_FETCH_DONE, 27)
+    GENERATE_ENUM(FACENESS_FLUSH, 28)
+END_ENUMTYPE(VGT_EVENT_TYPE)
+
+START_ENUMTYPE(VGT_DMA_SWAP_MODE)
+    GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0)
+    GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1)
+    GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2)
+    GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3)
+END_ENUMTYPE(VGT_DMA_SWAP_MODE)
+
+START_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0)
+    GENERATE_ENUM(VGT_SQ_SEND, 1)
+    GENERATE_ENUM(VGT_SQ_STALLED, 2)
+    GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3)
+    GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4)
+    GENERATE_ENUM(VGT_SQ_STATIC, 5)
+    GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6)
+    GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11)
+    GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16)
+    GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21)
+    GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28)
+    GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29)
+    GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30)
+    GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31)
+    GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32)
+    GENERATE_ENUM(BIN_PRIM_FACE_CULL, 33)
+    GENERATE_ENUM(SPARE34, 34)
+    GENERATE_ENUM(SPARE35, 35)
+    GENERATE_ENUM(SPARE36, 36)
+    GENERATE_ENUM(SPARE37, 37)
+    GENERATE_ENUM(SPARE38, 38)
+    GENERATE_ENUM(SPARE39, 39)
+    GENERATE_ENUM(TE_SU_IN_VALID, 40)
+    GENERATE_ENUM(TE_SU_IN_READ, 41)
+    GENERATE_ENUM(TE_SU_IN_PRIM, 42)
+    GENERATE_ENUM(TE_SU_IN_EOP, 43)
+    GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44)
+    GENERATE_ENUM(TE_WK_IN_VALID, 45)
+    GENERATE_ENUM(TE_WK_IN_READ, 46)
+    GENERATE_ENUM(TE_OUT_PRIM_VALID, 47)
+    GENERATE_ENUM(TE_OUT_PRIM_READ, 48)
+END_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+    GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0)
+    GENERATE_ENUM(reserved_46, 1)
+    GENERATE_ENUM(reserved_47, 2)
+    GENERATE_ENUM(reserved_48, 3)
+    GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4)
+    GENERATE_ENUM(OPMUX0_L2_WRITES, 5)
+    GENERATE_ENUM(reserved_49, 6)
+    GENERATE_ENUM(reserved_50, 7)
+    GENERATE_ENUM(reserved_51, 8)
+END_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TP_PERFCOUNT_SELECT)
+    GENERATE_ENUM(POINT_QUADS, 0)
+    GENERATE_ENUM(BILIN_QUADS, 1)
+    GENERATE_ENUM(ANISO_QUADS, 2)
+    GENERATE_ENUM(MIP_QUADS, 3)
+    GENERATE_ENUM(VOL_QUADS, 4)
+    GENERATE_ENUM(MIP_VOL_QUADS, 5)
+    GENERATE_ENUM(MIP_ANISO_QUADS, 6)
+    GENERATE_ENUM(VOL_ANISO_QUADS, 7)
+    GENERATE_ENUM(ANISO_2_1_QUADS, 8)
+    GENERATE_ENUM(ANISO_4_1_QUADS, 9)
+    GENERATE_ENUM(ANISO_6_1_QUADS, 10)
+    GENERATE_ENUM(ANISO_8_1_QUADS, 11)
+    GENERATE_ENUM(ANISO_10_1_QUADS, 12)
+    GENERATE_ENUM(ANISO_12_1_QUADS, 13)
+    GENERATE_ENUM(ANISO_14_1_QUADS, 14)
+    GENERATE_ENUM(ANISO_16_1_QUADS, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16)
+    GENERATE_ENUM(ALIGN_2_QUADS, 17)
+    GENERATE_ENUM(ALIGN_4_QUADS, 18)
+    GENERATE_ENUM(PIX_0_QUAD, 19)
+    GENERATE_ENUM(PIX_1_QUAD, 20)
+    GENERATE_ENUM(PIX_2_QUAD, 21)
+    GENERATE_ENUM(PIX_3_QUAD, 22)
+    GENERATE_ENUM(PIX_4_QUAD, 23)
+    GENERATE_ENUM(TP_MIPMAP_LOD0, 24)
+    GENERATE_ENUM(TP_MIPMAP_LOD1, 25)
+    GENERATE_ENUM(TP_MIPMAP_LOD2, 26)
+    GENERATE_ENUM(TP_MIPMAP_LOD3, 27)
+    GENERATE_ENUM(TP_MIPMAP_LOD4, 28)
+    GENERATE_ENUM(TP_MIPMAP_LOD5, 29)
+    GENERATE_ENUM(TP_MIPMAP_LOD6, 30)
+    GENERATE_ENUM(TP_MIPMAP_LOD7, 31)
+    GENERATE_ENUM(TP_MIPMAP_LOD8, 32)
+    GENERATE_ENUM(TP_MIPMAP_LOD9, 33)
+    GENERATE_ENUM(TP_MIPMAP_LOD10, 34)
+    GENERATE_ENUM(TP_MIPMAP_LOD11, 35)
+    GENERATE_ENUM(TP_MIPMAP_LOD12, 36)
+    GENERATE_ENUM(TP_MIPMAP_LOD13, 37)
+    GENERATE_ENUM(TP_MIPMAP_LOD14, 38)
+END_ENUMTYPE(TP_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0)
+    GENERATE_ENUM(reserved_01, 1)
+    GENERATE_ENUM(reserved_02, 2)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6)
+    GENERATE_ENUM(reserved_07, 7)
+    GENERATE_ENUM(reserved_08, 8)
+    GENERATE_ENUM(reserved_09, 9)
+    GENERATE_ENUM(reserved_10, 10)
+    GENERATE_ENUM(reserved_11, 11)
+    GENERATE_ENUM(reserved_12, 12)
+    GENERATE_ENUM(reserved_13, 13)
+    GENERATE_ENUM(reserved_14, 14)
+    GENERATE_ENUM(reserved_15, 15)
+    GENERATE_ENUM(reserved_16, 16)
+    GENERATE_ENUM(reserved_17, 17)
+    GENERATE_ENUM(reserved_18, 18)
+    GENERATE_ENUM(reserved_19, 19)
+    GENERATE_ENUM(reserved_20, 20)
+    GENERATE_ENUM(reserved_21, 21)
+    GENERATE_ENUM(reserved_22, 22)
+    GENERATE_ENUM(reserved_23, 23)
+    GENERATE_ENUM(reserved_24, 24)
+    GENERATE_ENUM(reserved_25, 25)
+    GENERATE_ENUM(reserved_26, 26)
+    GENERATE_ENUM(reserved_27, 27)
+    GENERATE_ENUM(READ_STARVED_QUAD0, 28)
+    GENERATE_ENUM(reserved_29, 29)
+    GENERATE_ENUM(reserved_30, 30)
+    GENERATE_ENUM(reserved_31, 31)
+    GENERATE_ENUM(READ_STARVED, 32)
+    GENERATE_ENUM(READ_STALLED_QUAD0, 33)
+    GENERATE_ENUM(reserved_34, 34)
+    GENERATE_ENUM(reserved_35, 35)
+    GENERATE_ENUM(reserved_36, 36)
+    GENERATE_ENUM(READ_STALLED, 37)
+    GENERATE_ENUM(VALID_READ_QUAD0, 38)
+    GENERATE_ENUM(reserved_39, 39)
+    GENERATE_ENUM(reserved_40, 40)
+    GENERATE_ENUM(reserved_41, 41)
+    GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42)
+    GENERATE_ENUM(reserved_43, 43)
+    GENERATE_ENUM(reserved_44, 44)
+    GENERATE_ENUM(reserved_45, 45)
+    GENERATE_ENUM(TC_TP_STARVED, 46)
+END_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VALID_CYCLES, 0)
+    GENERATE_ENUM(SINGLE_PHASES, 1)
+    GENERATE_ENUM(ANISO_PHASES, 2)
+    GENERATE_ENUM(MIP_PHASES, 3)
+    GENERATE_ENUM(VOL_PHASES, 4)
+    GENERATE_ENUM(MIP_VOL_PHASES, 5)
+    GENERATE_ENUM(MIP_ANISO_PHASES, 6)
+    GENERATE_ENUM(VOL_ANISO_PHASES, 7)
+    GENERATE_ENUM(ANISO_2_1_PHASES, 8)
+    GENERATE_ENUM(ANISO_4_1_PHASES, 9)
+    GENERATE_ENUM(ANISO_6_1_PHASES, 10)
+    GENERATE_ENUM(ANISO_8_1_PHASES, 11)
+    GENERATE_ENUM(ANISO_10_1_PHASES, 12)
+    GENERATE_ENUM(ANISO_12_1_PHASES, 13)
+    GENERATE_ENUM(ANISO_14_1_PHASES, 14)
+    GENERATE_ENUM(ANISO_16_1_PHASES, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16)
+    GENERATE_ENUM(ALIGN_2_PHASES, 17)
+    GENERATE_ENUM(ALIGN_4_PHASES, 18)
+    GENERATE_ENUM(TPC_BUSY, 19)
+    GENERATE_ENUM(TPC_STALLED, 20)
+    GENERATE_ENUM(TPC_STARVED, 21)
+    GENERATE_ENUM(TPC_WORKING, 22)
+    GENERATE_ENUM(TPC_WALKER_BUSY, 23)
+    GENERATE_ENUM(TPC_WALKER_STALLED, 24)
+    GENERATE_ENUM(TPC_WALKER_WORKING, 25)
+    GENERATE_ENUM(TPC_ALIGNER_BUSY, 26)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED, 27)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29)
+    GENERATE_ENUM(TPC_ALIGNER_WORKING, 30)
+    GENERATE_ENUM(TPC_BLEND_BUSY, 31)
+    GENERATE_ENUM(TPC_BLEND_SYNC, 32)
+    GENERATE_ENUM(TPC_BLEND_STARVED, 33)
+    GENERATE_ENUM(TPC_BLEND_WORKING, 34)
+    GENERATE_ENUM(OPCODE_0x00, 35)
+    GENERATE_ENUM(OPCODE_0x01, 36)
+    GENERATE_ENUM(OPCODE_0x04, 37)
+    GENERATE_ENUM(OPCODE_0x10, 38)
+    GENERATE_ENUM(OPCODE_0x11, 39)
+    GENERATE_ENUM(OPCODE_0x12, 40)
+    GENERATE_ENUM(OPCODE_0x13, 41)
+    GENERATE_ENUM(OPCODE_0x18, 42)
+    GENERATE_ENUM(OPCODE_0x19, 43)
+    GENERATE_ENUM(OPCODE_0x1A, 44)
+    GENERATE_ENUM(OPCODE_OTHER, 45)
+    GENERATE_ENUM(IN_FIFO_0_EMPTY, 56)
+    GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57)
+    GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58)
+    GENERATE_ENUM(IN_FIFO_0_FULL, 59)
+    GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72)
+    GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73)
+    GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74)
+    GENERATE_ENUM(IN_FIFO_TPC_FULL, 75)
+    GENERATE_ENUM(TPC_TC_XFC, 76)
+    GENERATE_ENUM(TPC_TC_STATE, 77)
+    GENERATE_ENUM(TC_STALL, 78)
+    GENERATE_ENUM(QUAD0_TAPS, 79)
+    GENERATE_ENUM(QUADS, 83)
+    GENERATE_ENUM(TCA_SYNC_STALL, 84)
+    GENERATE_ENUM(TAG_STALL, 85)
+    GENERATE_ENUM(TCB_SYNC_STALL, 88)
+    GENERATE_ENUM(TCA_VALID, 89)
+    GENERATE_ENUM(PROBES_VALID, 90)
+    GENERATE_ENUM(MISS_STALL, 91)
+    GENERATE_ENUM(FETCH_FIFO_STALL, 92)
+    GENERATE_ENUM(TCO_STALL, 93)
+    GENERATE_ENUM(ANY_STALL, 94)
+    GENERATE_ENUM(TAG_MISSES, 95)
+    GENERATE_ENUM(TAG_HITS, 96)
+    GENERATE_ENUM(SUB_TAG_MISSES, 97)
+    GENERATE_ENUM(SET0_INVALIDATES, 98)
+    GENERATE_ENUM(SET1_INVALIDATES, 99)
+    GENERATE_ENUM(SET2_INVALIDATES, 100)
+    GENERATE_ENUM(SET3_INVALIDATES, 101)
+    GENERATE_ENUM(SET0_TAG_MISSES, 102)
+    GENERATE_ENUM(SET1_TAG_MISSES, 103)
+    GENERATE_ENUM(SET2_TAG_MISSES, 104)
+    GENERATE_ENUM(SET3_TAG_MISSES, 105)
+    GENERATE_ENUM(SET0_TAG_HITS, 106)
+    GENERATE_ENUM(SET1_TAG_HITS, 107)
+    GENERATE_ENUM(SET2_TAG_HITS, 108)
+    GENERATE_ENUM(SET3_TAG_HITS, 109)
+    GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110)
+    GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111)
+    GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112)
+    GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113)
+    GENERATE_ENUM(SET0_EVICT1, 114)
+    GENERATE_ENUM(SET0_EVICT2, 115)
+    GENERATE_ENUM(SET0_EVICT3, 116)
+    GENERATE_ENUM(SET0_EVICT4, 117)
+    GENERATE_ENUM(SET0_EVICT5, 118)
+    GENERATE_ENUM(SET0_EVICT6, 119)
+    GENERATE_ENUM(SET0_EVICT7, 120)
+    GENERATE_ENUM(SET0_EVICT8, 121)
+    GENERATE_ENUM(SET1_EVICT1, 130)
+    GENERATE_ENUM(SET1_EVICT2, 131)
+    GENERATE_ENUM(SET1_EVICT3, 132)
+    GENERATE_ENUM(SET1_EVICT4, 133)
+    GENERATE_ENUM(SET1_EVICT5, 134)
+    GENERATE_ENUM(SET1_EVICT6, 135)
+    GENERATE_ENUM(SET1_EVICT7, 136)
+    GENERATE_ENUM(SET1_EVICT8, 137)
+    GENERATE_ENUM(SET2_EVICT1, 146)
+    GENERATE_ENUM(SET2_EVICT2, 147)
+    GENERATE_ENUM(SET2_EVICT3, 148)
+    GENERATE_ENUM(SET2_EVICT4, 149)
+    GENERATE_ENUM(SET2_EVICT5, 150)
+    GENERATE_ENUM(SET2_EVICT6, 151)
+    GENERATE_ENUM(SET2_EVICT7, 152)
+    GENERATE_ENUM(SET2_EVICT8, 153)
+    GENERATE_ENUM(SET3_EVICT1, 162)
+    GENERATE_ENUM(SET3_EVICT2, 163)
+    GENERATE_ENUM(SET3_EVICT3, 164)
+    GENERATE_ENUM(SET3_EVICT4, 165)
+    GENERATE_ENUM(SET3_EVICT5, 166)
+    GENERATE_ENUM(SET3_EVICT6, 167)
+    GENERATE_ENUM(SET3_EVICT7, 168)
+    GENERATE_ENUM(SET3_EVICT8, 169)
+    GENERATE_ENUM(FF_EMPTY, 178)
+    GENERATE_ENUM(FF_LT_HALF_FULL, 179)
+    GENERATE_ENUM(FF_HALF_FULL, 180)
+    GENERATE_ENUM(FF_FULL, 181)
+    GENERATE_ENUM(FF_XFC, 182)
+    GENERATE_ENUM(FF_STALLED, 183)
+    GENERATE_ENUM(FG_MASKS, 184)
+    GENERATE_ENUM(FG_LEFT_MASKS, 185)
+    GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186)
+    GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187)
+    GENERATE_ENUM(FG_LEFT_FG_STALL, 188)
+    GENERATE_ENUM(FG_LEFT_SECTORS, 189)
+    GENERATE_ENUM(FG0_REQUESTS, 195)
+    GENERATE_ENUM(FG0_STALLED, 196)
+    GENERATE_ENUM(MEM_REQ512, 199)
+    GENERATE_ENUM(MEM_REQ_SENT, 200)
+    GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202)
+    GENERATE_ENUM(TC0_MH_STALLED, 203)
+END_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(SQ_PERFCNT_SELECT)
+    GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0)
+    GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9)
+    GENERATE_ENUM(SQ_EXPORT_CYCLES, 10)
+    GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11)
+    GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12)
+    GENERATE_ENUM(SQ_ALU_CST_STALL, 13)
+    GENERATE_ENUM(SQ_ALU_TEX_STALL, 14)
+    GENERATE_ENUM(SQ_INST_WRITTEN, 15)
+    GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16)
+    GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21)
+    GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22)
+    GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23)
+    GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24)
+    GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25)
+    GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26)
+    GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27)
+    GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28)
+    GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33)
+    GENERATE_ENUM(SQ_ALU_NOPS, 34)
+    GENERATE_ENUM(SQ_PRED_SKIP, 35)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41)
+    GENERATE_ENUM(SQ_GPR_STALL_VTX, 42)
+    GENERATE_ENUM(SQ_GPR_STALL_PIX, 43)
+    GENERATE_ENUM(SQ_VTX_RS_STALL, 44)
+    GENERATE_ENUM(SQ_PIX_RS_STALL, 45)
+    GENERATE_ENUM(SQ_SX_PC_FULL, 46)
+    GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47)
+    GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48)
+    GENERATE_ENUM(SQ_INTERP_QUADS, 49)
+    GENERATE_ENUM(SQ_INTERP_ACTIVE, 50)
+    GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51)
+    GENERATE_ENUM(SQ_IN_VTX_STALL, 52)
+    GENERATE_ENUM(SQ_VTX_CNT, 53)
+    GENERATE_ENUM(SQ_VTX_VECTOR2, 54)
+    GENERATE_ENUM(SQ_VTX_VECTOR3, 55)
+    GENERATE_ENUM(SQ_VTX_VECTOR4, 56)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61)
+    GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_QUAL_TP_DONE, 68)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_QUAL_TP_DONE, 70)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_POP_THREAD, 76)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_POP_THREAD, 80)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_DEALLOC_ACK, 85)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_DEALLOC_ACK, 86)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94)
+    GENERATE_ENUM(VC_PERF_STATIC, 95)
+    GENERATE_ENUM(VC_PERF_STALLED, 96)
+    GENERATE_ENUM(VC_PERF_STARVED, 97)
+    GENERATE_ENUM(VC_PERF_SEND, 98)
+    GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99)
+    GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100)
+    GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101)
+    GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102)
+    GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103)
+    GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104)
+    GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105)
+    GENERATE_ENUM(PTRBUFF_EF_PUSH, 106)
+    GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107)
+    GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108)
+    GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112)
+    GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113)
+    GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114)
+    GENERATE_ENUM(PTRBUFF_PI_RTR, 115)
+    GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116)
+    GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117)
+    GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118)
+    GENERATE_ENUM(PTRBUFF_SQ_DEC, 119)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121)
+    GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122)
+    GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123)
+    GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124)
+    GENERATE_ENUM(PTRBUFF_END_BUFFER, 125)
+    GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126)
+    GENERATE_ENUM(VERTS_WRITTEN_SPI, 127)
+    GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128)
+    GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129)
+    GENERATE_ENUM(TP_DATA_RETURN, 130)
+    GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131)
+    GENERATE_ENUM(SPI_WRITES_SP, 132)
+    GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133)
+    GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134)
+    GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135)
+    GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136)
+    GENERATE_ENUM(SP_EXPORTS_TO_SX, 137)
+    GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138)
+    GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139)
+    GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140)
+    GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141)
+    GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142)
+    GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143)
+    GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144)
+    GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145)
+    GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146)
+    GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147)
+    GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148)
+    GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149)
+    GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150)
+    GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151)
+    GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152)
+    GENERATE_ENUM(SQ_PIX_TOTAL, 153)
+    GENERATE_ENUM(SQ_PIX_KILLED, 154)
+END_ENUMTYPE(SQ_PERFCNT_SELECT)
+
+START_ENUMTYPE(SX_PERFCNT_SELECT)
+    GENERATE_ENUM(SX_EXPORT_VECTORS, 0)
+    GENERATE_ENUM(SX_DUMMY_QUADS, 1)
+    GENERATE_ENUM(SX_ALPHA_FAIL, 2)
+    GENERATE_ENUM(SX_RB_QUAD_BUSY, 3)
+    GENERATE_ENUM(SX_RB_COLOR_BUSY, 4)
+    GENERATE_ENUM(SX_RB_QUAD_STALL, 5)
+    GENERATE_ENUM(SX_RB_COLOR_STALL, 6)
+END_ENUMTYPE(SX_PERFCNT_SELECT)
+
+START_ENUMTYPE(Abs_modifier)
+    GENERATE_ENUM(NO_ABS_MOD, 0)
+    GENERATE_ENUM(ABS_MOD, 1)
+END_ENUMTYPE(Abs_modifier)
+
+START_ENUMTYPE(Exporting)
+    GENERATE_ENUM(NOT_EXPORTING, 0)
+    GENERATE_ENUM(EXPORTING, 1)
+END_ENUMTYPE(Exporting)
+
+START_ENUMTYPE(ScalarOpcode)
+    GENERATE_ENUM(ADDs, 0)
+    GENERATE_ENUM(ADD_PREVs, 1)
+    GENERATE_ENUM(MULs, 2)
+    GENERATE_ENUM(MUL_PREVs, 3)
+    GENERATE_ENUM(MUL_PREV2s, 4)
+    GENERATE_ENUM(MAXs, 5)
+    GENERATE_ENUM(MINs, 6)
+    GENERATE_ENUM(SETEs, 7)
+    GENERATE_ENUM(SETGTs, 8)
+    GENERATE_ENUM(SETGTEs, 9)
+    GENERATE_ENUM(SETNEs, 10)
+    GENERATE_ENUM(FRACs, 11)
+    GENERATE_ENUM(TRUNCs, 12)
+    GENERATE_ENUM(FLOORs, 13)
+    GENERATE_ENUM(EXP_IEEE, 14)
+    GENERATE_ENUM(LOG_CLAMP, 15)
+    GENERATE_ENUM(LOG_IEEE, 16)
+    GENERATE_ENUM(RECIP_CLAMP, 17)
+    GENERATE_ENUM(RECIP_FF, 18)
+    GENERATE_ENUM(RECIP_IEEE, 19)
+    GENERATE_ENUM(RECIPSQ_CLAMP, 20)
+    GENERATE_ENUM(RECIPSQ_FF, 21)
+    GENERATE_ENUM(RECIPSQ_IEEE, 22)
+    GENERATE_ENUM(MOVAs, 23)
+    GENERATE_ENUM(MOVA_FLOORs, 24)
+    GENERATE_ENUM(SUBs, 25)
+    GENERATE_ENUM(SUB_PREVs, 26)
+    GENERATE_ENUM(PRED_SETEs, 27)
+    GENERATE_ENUM(PRED_SETNEs, 28)
+    GENERATE_ENUM(PRED_SETGTs, 29)
+    GENERATE_ENUM(PRED_SETGTEs, 30)
+    GENERATE_ENUM(PRED_SET_INVs, 31)
+    GENERATE_ENUM(PRED_SET_POPs, 32)
+    GENERATE_ENUM(PRED_SET_CLRs, 33)
+    GENERATE_ENUM(PRED_SET_RESTOREs, 34)
+    GENERATE_ENUM(KILLEs, 35)
+    GENERATE_ENUM(KILLGTs, 36)
+    GENERATE_ENUM(KILLGTEs, 37)
+    GENERATE_ENUM(KILLNEs, 38)
+    GENERATE_ENUM(KILLONEs, 39)
+    GENERATE_ENUM(SQRT_IEEE, 40)
+    GENERATE_ENUM(MUL_CONST_0, 42)
+    GENERATE_ENUM(MUL_CONST_1, 43)
+    GENERATE_ENUM(ADD_CONST_0, 44)
+    GENERATE_ENUM(ADD_CONST_1, 45)
+    GENERATE_ENUM(SUB_CONST_0, 46)
+    GENERATE_ENUM(SUB_CONST_1, 47)
+    GENERATE_ENUM(SIN, 48)
+    GENERATE_ENUM(COS, 49)
+    GENERATE_ENUM(RETAIN_PREV, 50)
+END_ENUMTYPE(ScalarOpcode)
+
+START_ENUMTYPE(SwizzleType)
+    GENERATE_ENUM(NO_SWIZZLE, 0)
+    GENERATE_ENUM(SHIFT_RIGHT_1, 1)
+    GENERATE_ENUM(SHIFT_RIGHT_2, 2)
+    GENERATE_ENUM(SHIFT_RIGHT_3, 3)
+END_ENUMTYPE(SwizzleType)
+
+START_ENUMTYPE(InputModifier)
+    GENERATE_ENUM(NIL, 0)
+    GENERATE_ENUM(NEGATE, 1)
+END_ENUMTYPE(InputModifier)
+
+START_ENUMTYPE(PredicateSelect)
+    GENERATE_ENUM(NO_PREDICATION, 0)
+    GENERATE_ENUM(PREDICATE_QUAD, 1)
+    GENERATE_ENUM(PREDICATED_2, 2)
+    GENERATE_ENUM(PREDICATED_3, 3)
+END_ENUMTYPE(PredicateSelect)
+
+START_ENUMTYPE(OperandSelect1)
+    GENERATE_ENUM(ABSOLUTE_REG, 0)
+    GENERATE_ENUM(RELATIVE_REG, 1)
+END_ENUMTYPE(OperandSelect1)
+
+START_ENUMTYPE(VectorOpcode)
+    GENERATE_ENUM(ADDv, 0)
+    GENERATE_ENUM(MULv, 1)
+    GENERATE_ENUM(MAXv, 2)
+    GENERATE_ENUM(MINv, 3)
+    GENERATE_ENUM(SETEv, 4)
+    GENERATE_ENUM(SETGTv, 5)
+    GENERATE_ENUM(SETGTEv, 6)
+    GENERATE_ENUM(SETNEv, 7)
+    GENERATE_ENUM(FRACv, 8)
+    GENERATE_ENUM(TRUNCv, 9)
+    GENERATE_ENUM(FLOORv, 10)
+    GENERATE_ENUM(MULADDv, 11)
+    GENERATE_ENUM(CNDEv, 12)
+    GENERATE_ENUM(CNDGTEv, 13)
+    GENERATE_ENUM(CNDGTv, 14)
+    GENERATE_ENUM(DOT4v, 15)
+    GENERATE_ENUM(DOT3v, 16)
+    GENERATE_ENUM(DOT2ADDv, 17)
+    GENERATE_ENUM(CUBEv, 18)
+    GENERATE_ENUM(MAX4v, 19)
+    GENERATE_ENUM(PRED_SETE_PUSHv, 20)
+    GENERATE_ENUM(PRED_SETNE_PUSHv, 21)
+    GENERATE_ENUM(PRED_SETGT_PUSHv, 22)
+    GENERATE_ENUM(PRED_SETGTE_PUSHv, 23)
+    GENERATE_ENUM(KILLEv, 24)
+    GENERATE_ENUM(KILLGTv, 25)
+    GENERATE_ENUM(KILLGTEv, 26)
+    GENERATE_ENUM(KILLNEv, 27)
+    GENERATE_ENUM(DSTv, 28)
+    GENERATE_ENUM(MOVAv, 29)
+END_ENUMTYPE(VectorOpcode)
+
+START_ENUMTYPE(OperandSelect0)
+    GENERATE_ENUM(CONSTANT, 0)
+    GENERATE_ENUM(NON_CONSTANT, 1)
+END_ENUMTYPE(OperandSelect0)
+
+START_ENUMTYPE(Ressource_type)
+    GENERATE_ENUM(ALU, 0)
+    GENERATE_ENUM(TEXTURE, 1)
+END_ENUMTYPE(Ressource_type)
+
+START_ENUMTYPE(Instruction_serial)
+    GENERATE_ENUM(NOT_SERIAL, 0)
+    GENERATE_ENUM(SERIAL, 1)
+END_ENUMTYPE(Instruction_serial)
+
+START_ENUMTYPE(VC_type)
+    GENERATE_ENUM(ALU_TP_REQUEST, 0)
+    GENERATE_ENUM(VC_REQUEST, 1)
+END_ENUMTYPE(VC_type)
+
+START_ENUMTYPE(Addressing)
+    GENERATE_ENUM(RELATIVE_ADDR, 0)
+    GENERATE_ENUM(ABSOLUTE_ADDR, 1)
+END_ENUMTYPE(Addressing)
+
+START_ENUMTYPE(CFOpcode)
+    GENERATE_ENUM(NOP, 0)
+    GENERATE_ENUM(EXECUTE, 1)
+    GENERATE_ENUM(EXECUTE_END, 2)
+    GENERATE_ENUM(COND_EXECUTE, 3)
+    GENERATE_ENUM(COND_EXECUTE_END, 4)
+    GENERATE_ENUM(COND_PRED_EXECUTE, 5)
+    GENERATE_ENUM(COND_PRED_EXECUTE_END, 6)
+    GENERATE_ENUM(LOOP_START, 7)
+    GENERATE_ENUM(LOOP_END, 8)
+    GENERATE_ENUM(COND_CALL, 9)
+    GENERATE_ENUM(RETURN, 10)
+    GENERATE_ENUM(COND_JMP, 11)
+    GENERATE_ENUM(ALLOCATE, 12)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14)
+    GENERATE_ENUM(MARK_VS_FETCH_DONE, 15)
+END_ENUMTYPE(CFOpcode)
+
+START_ENUMTYPE(Allocation_type)
+    GENERATE_ENUM(SQ_NO_ALLOC, 0)
+    GENERATE_ENUM(SQ_POSITION, 1)
+    GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2)
+    GENERATE_ENUM(SQ_MEMORY, 3)
+END_ENUMTYPE(Allocation_type)
+
+START_ENUMTYPE(TexInstOpcode)
+    GENERATE_ENUM(TEX_INST_FETCH, 1)
+    GENERATE_ENUM(TEX_INST_RESERVED_1, 2)
+    GENERATE_ENUM(TEX_INST_RESERVED_2, 3)
+    GENERATE_ENUM(TEX_INST_RESERVED_3, 4)
+    GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16)
+    GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17)
+    GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18)
+    GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19)
+    GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26)
+    GENERATE_ENUM(TEX_INST_RESERVED_4, 27)
+END_ENUMTYPE(TexInstOpcode)
+
+START_ENUMTYPE(Addressmode)
+    GENERATE_ENUM(LOGICAL, 0)
+    GENERATE_ENUM(LOOP_RELATIVE, 1)
+END_ENUMTYPE(Addressmode)
+
+START_ENUMTYPE(TexCoordDenorm)
+    GENERATE_ENUM(TEX_COORD_NORMALIZED, 0)
+    GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1)
+END_ENUMTYPE(TexCoordDenorm)
+
+START_ENUMTYPE(SrcSel)
+    GENERATE_ENUM(SRC_SEL_X, 0)
+    GENERATE_ENUM(SRC_SEL_Y, 1)
+    GENERATE_ENUM(SRC_SEL_Z, 2)
+    GENERATE_ENUM(SRC_SEL_W, 3)
+END_ENUMTYPE(SrcSel)
+
+START_ENUMTYPE(DstSel)
+    GENERATE_ENUM(DST_SEL_X, 0)
+    GENERATE_ENUM(DST_SEL_Y, 1)
+    GENERATE_ENUM(DST_SEL_Z, 2)
+    GENERATE_ENUM(DST_SEL_W, 3)
+    GENERATE_ENUM(DST_SEL_0, 4)
+    GENERATE_ENUM(DST_SEL_1, 5)
+    GENERATE_ENUM(DST_SEL_RSVD, 6)
+    GENERATE_ENUM(DST_SEL_MASK, 7)
+END_ENUMTYPE(DstSel)
+
+START_ENUMTYPE(MagFilter)
+    GENERATE_ENUM(MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MagFilter)
+
+START_ENUMTYPE(MinFilter)
+    GENERATE_ENUM(MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MinFilter)
+
+START_ENUMTYPE(MipFilter)
+    GENERATE_ENUM(MIP_FILTER_POINT, 0)
+    GENERATE_ENUM(MIP_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIP_FILTER_BASEMAP, 2)
+    GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MipFilter)
+
+START_ENUMTYPE(AnisoFilter)
+    GENERATE_ENUM(ANISO_FILTER_DISABLED, 0)
+    GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1)
+    GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2)
+    GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3)
+    GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4)
+    GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5)
+    GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(AnisoFilter)
+
+START_ENUMTYPE(ArbitraryFilter)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5)
+    GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(ArbitraryFilter)
+
+START_ENUMTYPE(VolMagFilter)
+    GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMagFilter)
+
+START_ENUMTYPE(VolMinFilter)
+    GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMinFilter)
+
+START_ENUMTYPE(PredSelect)
+    GENERATE_ENUM(NOT_PREDICATED, 0)
+    GENERATE_ENUM(PREDICATED, 1)
+END_ENUMTYPE(PredSelect)
+
+START_ENUMTYPE(SampleLocation)
+    GENERATE_ENUM(SAMPLE_CENTROID, 0)
+    GENERATE_ENUM(SAMPLE_CENTER, 1)
+END_ENUMTYPE(SampleLocation)
+
+START_ENUMTYPE(VertexMode)
+    GENERATE_ENUM(POSITION_1_VECTOR, 0)
+    GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3)
+    GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6)
+    GENERATE_ENUM(MULTIPASS, 7)
+END_ENUMTYPE(VertexMode)
+
+START_ENUMTYPE(Sample_Cntl)
+    GENERATE_ENUM(CENTROIDS_ONLY, 0)
+    GENERATE_ENUM(CENTERS_ONLY, 1)
+    GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2)
+    GENERATE_ENUM(UNDEF, 3)
+END_ENUMTYPE(Sample_Cntl)
+
+START_ENUMTYPE(MhPerfEncode)
+    GENERATE_ENUM(CP_R0_REQUESTS, 0)
+    GENERATE_ENUM(CP_R1_REQUESTS, 1)
+    GENERATE_ENUM(CP_R2_REQUESTS, 2)
+    GENERATE_ENUM(CP_R3_REQUESTS, 3)
+    GENERATE_ENUM(CP_R4_REQUESTS, 4)
+    GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5)
+    GENERATE_ENUM(CP_TOTAL_WRITE_REQUESTS, 6)
+    GENERATE_ENUM(CP_TOTAL_REQUESTS, 7)
+    GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8)
+    GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9)
+    GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10)
+    GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11)
+    GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12)
+    GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13)
+    GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14)
+    GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15)
+    GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16)
+    GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17)
+    GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18)
+    GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19)
+    GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20)
+    GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21)
+    GENERATE_ENUM(VGT_R0_REQUESTS, 22)
+    GENERATE_ENUM(VGT_R1_REQUESTS, 23)
+    GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24)
+    GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25)
+    GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26)
+    GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27)
+    GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28)
+    GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29)
+    GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30)
+    GENERATE_ENUM(TC_TOTAL_REQUESTS, 31)
+    GENERATE_ENUM(TC_ROQ_REQUESTS, 32)
+    GENERATE_ENUM(TC_INFO_SENT, 33)
+    GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34)
+    GENERATE_ENUM(TC_DATA_BEATS_READ, 35)
+    GENERATE_ENUM(TCD_BURSTS_READ, 36)
+    GENERATE_ENUM(RB_REQUESTS, 37)
+    GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38)
+    GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56)
+    GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111)
+    GENERATE_ENUM(TOTAL_MMU_MISSES, 112)
+    GENERATE_ENUM(MMU_READ_MISSES, 113)
+    GENERATE_ENUM(MMU_WRITE_MISSES, 114)
+    GENERATE_ENUM(TOTAL_MMU_HITS, 115)
+    GENERATE_ENUM(MMU_READ_HITS, 116)
+    GENERATE_ENUM(MMU_WRITE_HITS, 117)
+    GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118)
+    GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121)
+    GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122)
+    GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123)
+    GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124)
+    GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125)
+    GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127)
+    GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129)
+    GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130)
+    GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131)
+    GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132)
+    GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133)
+    GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136)
+    GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140)
+    GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148)
+    GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149)
+    GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150)
+    GENERATE_ENUM(TOTAL_MH_REQUESTS, 151)
+    GENERATE_ENUM(MH_BUSY, 152)
+    GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153)
+    GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154)
+    GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155)
+    GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156)
+    GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157)
+    GENERATE_ENUM(ARQ_N_ENTRIES, 158)
+    GENERATE_ENUM(WDB_N_ENTRIES, 159)
+    GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160)
+    GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161)
+    GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162)
+    GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163)
+    GENERATE_ENUM(ELAPSED_CLK_CYCLES, 164)
+    GENERATE_ENUM(CP_W_16B_REQUESTS, 165)
+    GENERATE_ENUM(CP_W_32B_REQUESTS, 166)
+    GENERATE_ENUM(TC_16B_REQUESTS, 167)
+    GENERATE_ENUM(TC_32B_REQUESTS, 168)
+    GENERATE_ENUM(PA_REQUESTS, 169)
+    GENERATE_ENUM(PA_DATA_BYTES_WRITTEN, 170)
+    GENERATE_ENUM(PA_WRITE_CLEAN_RESPONSES, 171)
+    GENERATE_ENUM(PA_CYCLES_HELD_OFF, 172)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_0, 173)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_1, 174)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_2, 175)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_3, 176)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_4, 177)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_5, 178)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_6, 179)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_7, 180)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUEST_DATA_BEATS, 181)
+END_ENUMTYPE(MhPerfEncode)
+
+START_ENUMTYPE(MmuClntBeh)
+    GENERATE_ENUM(BEH_NEVR, 0)
+    GENERATE_ENUM(BEH_TRAN_RNG, 1)
+    GENERATE_ENUM(BEH_TRAN_FLT, 2)
+END_ENUMTYPE(MmuClntBeh)
+
+START_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+    GENERATE_ENUM(RBBM1_COUNT, 0)
+    GENERATE_ENUM(RBBM1_NRT_BUSY, 1)
+    GENERATE_ENUM(RBBM1_RB_BUSY, 2)
+    GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3)
+    GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4)
+    GENERATE_ENUM(RBBM1_VGT_BUSY, 5)
+    GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6)
+    GENERATE_ENUM(RBBM1_PA_BUSY, 7)
+    GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8)
+    GENERATE_ENUM(RBBM1_TPC_BUSY, 9)
+    GENERATE_ENUM(RBBM1_TC_BUSY, 10)
+    GENERATE_ENUM(RBBM1_SX_BUSY, 11)
+    GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12)
+    GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13)
+    GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14)
+    GENERATE_ENUM(RBBM1_INTERRUPT, 15)
+END_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+
+START_ENUMTYPE(CP_PERFCOUNT_SEL)
+    GENERATE_ENUM(ALWAYS_COUNT, 0)
+    GENERATE_ENUM(TRANS_FIFO_FULL, 1)
+    GENERATE_ENUM(TRANS_FIFO_AF, 2)
+    GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3)
+    GENERATE_ENUM(Reserved_04, 4)
+    GENERATE_ENUM(Reserved_05, 5)
+    GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6)
+    GENERATE_ENUM(Reserved_07, 7)
+    GENERATE_ENUM(CSF_NRT_READ_WAIT, 8)
+    GENERATE_ENUM(CSF_I1_FIFO_FULL, 9)
+    GENERATE_ENUM(CSF_I2_FIFO_FULL, 10)
+    GENERATE_ENUM(CSF_ST_FIFO_FULL, 11)
+    GENERATE_ENUM(Reserved_12, 12)
+    GENERATE_ENUM(CSF_RING_ROQ_FULL, 13)
+    GENERATE_ENUM(CSF_I1_ROQ_FULL, 14)
+    GENERATE_ENUM(CSF_I2_ROQ_FULL, 15)
+    GENERATE_ENUM(CSF_ST_ROQ_FULL, 16)
+    GENERATE_ENUM(Reserved_17, 17)
+    GENERATE_ENUM(MIU_TAG_MEM_FULL, 18)
+    GENERATE_ENUM(MIU_WRITECLEAN, 19)
+    GENERATE_ENUM(Reserved_20, 20)
+    GENERATE_ENUM(Reserved_21, 21)
+    GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22)
+    GENERATE_ENUM(MIU_NRT_READ_STALLED, 23)
+    GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24)
+    GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25)
+    GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26)
+    GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27)
+    GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28)
+    GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29)
+    GENERATE_ENUM(ME_MICRO_RB_STARVED, 30)
+    GENERATE_ENUM(ME_MICRO_I1_STARVED, 31)
+    GENERATE_ENUM(ME_MICRO_I2_STARVED, 32)
+    GENERATE_ENUM(ME_MICRO_ST_STARVED, 33)
+    GENERATE_ENUM(Reserved_34, 34)
+    GENERATE_ENUM(Reserved_35, 35)
+    GENERATE_ENUM(Reserved_36, 36)
+    GENERATE_ENUM(Reserved_37, 37)
+    GENERATE_ENUM(Reserved_38, 38)
+    GENERATE_ENUM(Reserved_39, 39)
+    GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40)
+    GENERATE_ENUM(ME_BUSY_CLOCKS, 41)
+    GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42)
+    GENERATE_ENUM(PFP_TYPE0_PACKET, 43)
+    GENERATE_ENUM(PFP_TYPE3_PACKET, 44)
+    GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45)
+    GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46)
+    GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47)
+    GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48)
+    GENERATE_ENUM(Reserved_49, 49)
+    GENERATE_ENUM(Reserved_50, 50)
+    GENERATE_ENUM(Reserved_51, 51)
+    GENERATE_ENUM(Reserved_52, 52)
+    GENERATE_ENUM(Reserved_53, 53)
+    GENERATE_ENUM(Reserved_54, 54)
+    GENERATE_ENUM(Reserved_55, 55)
+    GENERATE_ENUM(Reserved_56, 56)
+    GENERATE_ENUM(Reserved_57, 57)
+    GENERATE_ENUM(Reserved_58, 58)
+    GENERATE_ENUM(Reserved_59, 59)
+    GENERATE_ENUM(Reserved_60, 60)
+    GENERATE_ENUM(Reserved_61, 61)
+    GENERATE_ENUM(Reserved_62, 62)
+    GENERATE_ENUM(Reserved_63, 63)
+END_ENUMTYPE(CP_PERFCOUNT_SEL)
+
+START_ENUMTYPE(ColorformatX)
+    GENERATE_ENUM(COLORX_4_4_4_4, 0)
+    GENERATE_ENUM(COLORX_1_5_5_5, 1)
+    GENERATE_ENUM(COLORX_5_6_5, 2)
+    GENERATE_ENUM(COLORX_8, 3)
+    GENERATE_ENUM(COLORX_8_8, 4)
+    GENERATE_ENUM(COLORX_8_8_8_8, 5)
+    GENERATE_ENUM(COLORX_S8_8_8_8, 6)
+    GENERATE_ENUM(COLORX_16_FLOAT, 7)
+    GENERATE_ENUM(COLORX_16_16_FLOAT, 8)
+    GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9)
+    GENERATE_ENUM(COLORX_32_FLOAT, 10)
+    GENERATE_ENUM(COLORX_32_32_FLOAT, 11)
+    GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12)
+    GENERATE_ENUM(COLORX_2_3_3, 13)
+    GENERATE_ENUM(COLORX_8_8_8, 14)
+END_ENUMTYPE(ColorformatX)
+
+START_ENUMTYPE(DepthformatX)
+    GENERATE_ENUM(DEPTHX_16, 0)
+    GENERATE_ENUM(DEPTHX_24_8, 1)
+END_ENUMTYPE(DepthformatX)
+
+START_ENUMTYPE(CompareFrag)
+    GENERATE_ENUM(FRAG_NEVER, 0)
+    GENERATE_ENUM(FRAG_LESS, 1)
+    GENERATE_ENUM(FRAG_EQUAL, 2)
+    GENERATE_ENUM(FRAG_LEQUAL, 3)
+    GENERATE_ENUM(FRAG_GREATER, 4)
+    GENERATE_ENUM(FRAG_NOTEQUAL, 5)
+    GENERATE_ENUM(FRAG_GEQUAL, 6)
+    GENERATE_ENUM(FRAG_ALWAYS, 7)
+END_ENUMTYPE(CompareFrag)
+
+START_ENUMTYPE(CompareRef)
+    GENERATE_ENUM(REF_NEVER, 0)
+    GENERATE_ENUM(REF_LESS, 1)
+    GENERATE_ENUM(REF_EQUAL, 2)
+    GENERATE_ENUM(REF_LEQUAL, 3)
+    GENERATE_ENUM(REF_GREATER, 4)
+    GENERATE_ENUM(REF_NOTEQUAL, 5)
+    GENERATE_ENUM(REF_GEQUAL, 6)
+    GENERATE_ENUM(REF_ALWAYS, 7)
+END_ENUMTYPE(CompareRef)
+
+START_ENUMTYPE(StencilOp)
+    GENERATE_ENUM(STENCIL_KEEP, 0)
+    GENERATE_ENUM(STENCIL_ZERO, 1)
+    GENERATE_ENUM(STENCIL_REPLACE, 2)
+    GENERATE_ENUM(STENCIL_INCR_CLAMP, 3)
+    GENERATE_ENUM(STENCIL_DECR_CLAMP, 4)
+    GENERATE_ENUM(STENCIL_INVERT, 5)
+    GENERATE_ENUM(STENCIL_INCR_WRAP, 6)
+    GENERATE_ENUM(STENCIL_DECR_WRAP, 7)
+END_ENUMTYPE(StencilOp)
+
+START_ENUMTYPE(BlendOpX)
+    GENERATE_ENUM(BLENDX_ZERO, 0)
+    GENERATE_ENUM(BLENDX_ONE, 1)
+    GENERATE_ENUM(BLENDX_SRC_COLOR, 4)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA, 6)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7)
+    GENERATE_ENUM(BLENDX_DST_COLOR, 8)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9)
+    GENERATE_ENUM(BLENDX_DST_ALPHA, 10)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11)
+    GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13)
+    GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16)
+END_ENUMTYPE(BlendOpX)
+
+START_ENUMTYPE(CombFuncX)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC, 0)
+    GENERATE_ENUM(COMB_SRC_MINUS_DST, 1)
+    GENERATE_ENUM(COMB_MIN_DST_SRC, 2)
+    GENERATE_ENUM(COMB_MAX_DST_SRC, 3)
+    GENERATE_ENUM(COMB_DST_MINUS_SRC, 4)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5)
+END_ENUMTYPE(CombFuncX)
+
+START_ENUMTYPE(DitherModeX)
+    GENERATE_ENUM(DITHER_DISABLE, 0)
+    GENERATE_ENUM(DITHER_ALWAYS, 1)
+    GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2)
+END_ENUMTYPE(DitherModeX)
+
+START_ENUMTYPE(DitherTypeX)
+    GENERATE_ENUM(DITHER_PIXEL, 0)
+    GENERATE_ENUM(DITHER_SUBPIXEL, 1)
+END_ENUMTYPE(DitherTypeX)
+
+START_ENUMTYPE(EdramMode)
+    GENERATE_ENUM(EDRAM_NOP, 0)
+    GENERATE_ENUM(COLOR_DEPTH, 4)
+    GENERATE_ENUM(DEPTH_ONLY, 5)
+    GENERATE_ENUM(EDRAM_COPY, 6)
+END_ENUMTYPE(EdramMode)
+
+START_ENUMTYPE(SurfaceEndian)
+    GENERATE_ENUM(ENDIAN_NONE, 0)
+    GENERATE_ENUM(ENDIAN_8IN16, 1)
+    GENERATE_ENUM(ENDIAN_8IN32, 2)
+    GENERATE_ENUM(ENDIAN_16IN32, 3)
+    GENERATE_ENUM(ENDIAN_8IN64, 4)
+    GENERATE_ENUM(ENDIAN_8IN128, 5)
+END_ENUMTYPE(SurfaceEndian)
+
+START_ENUMTYPE(EdramSizeX)
+    GENERATE_ENUM(EDRAMSIZE_16KB, 0)
+    GENERATE_ENUM(EDRAMSIZE_32KB, 1)
+    GENERATE_ENUM(EDRAMSIZE_64KB, 2)
+    GENERATE_ENUM(EDRAMSIZE_128KB, 3)
+    GENERATE_ENUM(EDRAMSIZE_256KB, 4)
+    GENERATE_ENUM(EDRAMSIZE_512KB, 5)
+    GENERATE_ENUM(EDRAMSIZE_1MB, 6)
+    GENERATE_ENUM(EDRAMSIZE_2MB, 7)
+    GENERATE_ENUM(EDRAMSIZE_4MB, 8)
+    GENERATE_ENUM(EDRAMSIZE_8MB, 9)
+    GENERATE_ENUM(EDRAMSIZE_16MB, 10)
+END_ENUMTYPE(EdramSizeX)
+
+START_ENUMTYPE(RB_PERFCNT_SELECT)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY, 0)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7)
+    GENERATE_ENUM(RBPERF_MH_STARVED, 8)
+    GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23)
+    GENERATE_ENUM(RBPERF_ZXP_STALL, 24)
+    GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING, 26)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID, 28)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30)
+    GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32)
+    GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33)
+    GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37)
+    GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38)
+    GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43)
+    GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44)
+    GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45)
+    GENERATE_ENUM(RBPERF_ZPASS_DONE, 46)
+    GENERATE_ENUM(RBPERF_ZCMD_VALID, 47)
+    GENERATE_ENUM(RBPERF_CCMD_VALID, 48)
+    GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49)
+    GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50)
+    GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51)
+    GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52)
+    GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53)
+    GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54)
+    GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55)
+    GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56)
+END_ENUMTYPE(RB_PERFCNT_SELECT)
+
+START_ENUMTYPE(DepthFormat)
+    GENERATE_ENUM(DEPTH_24_8, 22)
+    GENERATE_ENUM(DEPTH_24_8_FLOAT, 23)
+    GENERATE_ENUM(DEPTH_16, 24)
+END_ENUMTYPE(DepthFormat)
+
+START_ENUMTYPE(SurfaceSwap)
+    GENERATE_ENUM(SWAP_LOWRED, 0)
+    GENERATE_ENUM(SWAP_LOWBLUE, 1)
+END_ENUMTYPE(SurfaceSwap)
+
+START_ENUMTYPE(DepthArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0)
+    GENERATE_ENUM(ARRAY_2D_DEPTH, 1)
+END_ENUMTYPE(DepthArray)
+
+START_ENUMTYPE(ColorArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0)
+    GENERATE_ENUM(ARRAY_2D_COLOR, 1)
+    GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3)
+END_ENUMTYPE(ColorArray)
+
+START_ENUMTYPE(ColorFormat)
+    GENERATE_ENUM(COLOR_8, 2)
+    GENERATE_ENUM(COLOR_1_5_5_5, 3)
+    GENERATE_ENUM(COLOR_5_6_5, 4)
+    GENERATE_ENUM(COLOR_6_5_5, 5)
+    GENERATE_ENUM(COLOR_8_8_8_8, 6)
+    GENERATE_ENUM(COLOR_2_10_10_10, 7)
+    GENERATE_ENUM(COLOR_8_A, 8)
+    GENERATE_ENUM(COLOR_8_B, 9)
+    GENERATE_ENUM(COLOR_8_8, 10)
+    GENERATE_ENUM(COLOR_8_8_8, 11)
+    GENERATE_ENUM(COLOR_8_8_8_8_A, 14)
+    GENERATE_ENUM(COLOR_4_4_4_4, 15)
+    GENERATE_ENUM(COLOR_10_11_11, 16)
+    GENERATE_ENUM(COLOR_11_11_10, 17)
+    GENERATE_ENUM(COLOR_16, 24)
+    GENERATE_ENUM(COLOR_16_16, 25)
+    GENERATE_ENUM(COLOR_16_16_16_16, 26)
+    GENERATE_ENUM(COLOR_16_FLOAT, 30)
+    GENERATE_ENUM(COLOR_16_16_FLOAT, 31)
+    GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(COLOR_32_FLOAT, 36)
+    GENERATE_ENUM(COLOR_32_32_FLOAT, 37)
+    GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(COLOR_2_3_3, 39)
+END_ENUMTYPE(ColorFormat)
+
+START_ENUMTYPE(SurfaceNumber)
+    GENERATE_ENUM(NUMBER_UREPEAT, 0)
+    GENERATE_ENUM(NUMBER_SREPEAT, 1)
+    GENERATE_ENUM(NUMBER_UINTEGER, 2)
+    GENERATE_ENUM(NUMBER_SINTEGER, 3)
+    GENERATE_ENUM(NUMBER_GAMMA, 4)
+    GENERATE_ENUM(NUMBER_FIXED, 5)
+    GENERATE_ENUM(NUMBER_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumber)
+
+START_ENUMTYPE(SurfaceFormat)
+    GENERATE_ENUM(FMT_1_REVERSE, 0)
+    GENERATE_ENUM(FMT_1, 1)
+    GENERATE_ENUM(FMT_8, 2)
+    GENERATE_ENUM(FMT_1_5_5_5, 3)
+    GENERATE_ENUM(FMT_5_6_5, 4)
+    GENERATE_ENUM(FMT_6_5_5, 5)
+    GENERATE_ENUM(FMT_8_8_8_8, 6)
+    GENERATE_ENUM(FMT_2_10_10_10, 7)
+    GENERATE_ENUM(FMT_8_A, 8)
+    GENERATE_ENUM(FMT_8_B, 9)
+    GENERATE_ENUM(FMT_8_8, 10)
+    GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11)
+    GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12)
+    GENERATE_ENUM(FMT_5_5_5_1, 13)
+    GENERATE_ENUM(FMT_8_8_8_8_A, 14)
+    GENERATE_ENUM(FMT_4_4_4_4, 15)
+    GENERATE_ENUM(FMT_8_8_8, 16)
+    GENERATE_ENUM(FMT_DXT1, 18)
+    GENERATE_ENUM(FMT_DXT2_3, 19)
+    GENERATE_ENUM(FMT_DXT4_5, 20)
+    GENERATE_ENUM(FMT_10_10_10_2, 21)
+    GENERATE_ENUM(FMT_24_8, 22)
+    GENERATE_ENUM(FMT_16, 24)
+    GENERATE_ENUM(FMT_16_16, 25)
+    GENERATE_ENUM(FMT_16_16_16_16, 26)
+    GENERATE_ENUM(FMT_16_EXPAND, 27)
+    GENERATE_ENUM(FMT_16_16_EXPAND, 28)
+    GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29)
+    GENERATE_ENUM(FMT_16_FLOAT, 30)
+    GENERATE_ENUM(FMT_16_16_FLOAT, 31)
+    GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(FMT_32, 33)
+    GENERATE_ENUM(FMT_32_32, 34)
+    GENERATE_ENUM(FMT_32_32_32_32, 35)
+    GENERATE_ENUM(FMT_32_FLOAT, 36)
+    GENERATE_ENUM(FMT_32_32_FLOAT, 37)
+    GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(FMT_ATI_TC_RGB, 39)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA, 40)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44)
+    GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46)
+    GENERATE_ENUM(FMT_ETC1_RGB, 47)
+    GENERATE_ENUM(FMT_ETC1_RGBA, 48)
+    GENERATE_ENUM(FMT_DXN, 49)
+    GENERATE_ENUM(FMT_2_3_3, 51)
+    GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54)
+    GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55)
+    GENERATE_ENUM(FMT_32_32_32_FLOAT, 57)
+    GENERATE_ENUM(FMT_DXT3A, 58)
+    GENERATE_ENUM(FMT_DXT5A, 59)
+    GENERATE_ENUM(FMT_CTX1, 60)
+END_ENUMTYPE(SurfaceFormat)
+
+START_ENUMTYPE(SurfaceTiling)
+    GENERATE_ENUM(ARRAY_LINEAR, 0)
+    GENERATE_ENUM(ARRAY_TILED, 1)
+END_ENUMTYPE(SurfaceTiling)
+
+START_ENUMTYPE(SurfaceArray)
+    GENERATE_ENUM(ARRAY_1D, 0)
+    GENERATE_ENUM(ARRAY_2D, 1)
+    GENERATE_ENUM(ARRAY_3D, 2)
+    GENERATE_ENUM(ARRAY_3D_SLICE, 3)
+END_ENUMTYPE(SurfaceArray)
+
+START_ENUMTYPE(SurfaceNumberX)
+    GENERATE_ENUM(NUMBERX_UREPEAT, 0)
+    GENERATE_ENUM(NUMBERX_SREPEAT, 1)
+    GENERATE_ENUM(NUMBERX_UINTEGER, 2)
+    GENERATE_ENUM(NUMBERX_SINTEGER, 3)
+    GENERATE_ENUM(NUMBERX_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumberX)
+
+START_ENUMTYPE(ColorArrayX)
+    GENERATE_ENUM(ARRAYX_2D_COLOR, 0)
+    GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1)
+END_ENUMTYPE(ColorArrayX)
+
+
+
+
+// **************************************************************************
+// These are ones that had to be added in addition to what's generated
+// by the autoreg (in CSIM)
+// **************************************************************************
+START_ENUMTYPE(DXClipSpaceDef)
+    GENERATE_ENUM(DXCLIP_OPENGL, 0)
+    GENERATE_ENUM(DXCLIP_DIRECTX, 1)
+END_ENUMTYPE(DXClipSpaceDef)
+
+START_ENUMTYPE(PixCenter)
+    GENERATE_ENUM(PIXCENTER_D3D, 0)
+    GENERATE_ENUM(PIXCENTER_OGL, 1)
+END_ENUMTYPE(PixCenter)
+
+START_ENUMTYPE(RoundMode)
+    GENERATE_ENUM(TRUNCATE,   0)
+    GENERATE_ENUM(ROUND,      1)
+    GENERATE_ENUM(ROUNDTOEVEN,    2)
+    GENERATE_ENUM(ROUNDTOODD,     3)
+END_ENUMTYPE(RoundMode)
+
+START_ENUMTYPE(QuantMode)
+    GENERATE_ENUM(ONE_SIXTEENTH,   0)
+    GENERATE_ENUM(ONE_EIGHTH,      1)
+    GENERATE_ENUM(ONE_QUARTER,     2)
+    GENERATE_ENUM(ONE_HALF,    3)
+    GENERATE_ENUM(ONE,         4)
+END_ENUMTYPE(QuantMode)
+
+START_ENUMTYPE(FrontFace)
+    GENERATE_ENUM(FRONT_CCW,        0)
+    GENERATE_ENUM(FRONT_CW,     1)
+END_ENUMTYPE(FrontFace)
+
+START_ENUMTYPE(PolyMode)
+    GENERATE_ENUM(DISABLED,    0)
+    GENERATE_ENUM(DUALMODE,    1)
+END_ENUMTYPE(PolyMode)
+
+START_ENUMTYPE(PType)
+    GENERATE_ENUM(DRAW_POINTS,      0)
+    GENERATE_ENUM(DRAW_LINES,       1)
+    GENERATE_ENUM(DRAW_TRIANGLES,   2)
+END_ENUMTYPE(PType)
+
+START_ENUMTYPE(MSAANumSamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     3)
+END_ENUMTYPE(MSAANumSamples)
+
+START_ENUMTYPE(PatternBitOrder)
+    GENERATE_ENUM(LITTLE,   0)
+    GENERATE_ENUM(BIG,      1)
+END_ENUMTYPE(PatternBitOrder)
+
+START_ENUMTYPE(AutoResetCntl)
+    GENERATE_ENUM(NEVER,        0)
+    GENERATE_ENUM(EACHPRIMITIVE,    1)
+    GENERATE_ENUM(EACHPACKET,       2)
+END_ENUMTYPE(AutoResetCntl)
+
+START_ENUMTYPE(ParamShade)
+    GENERATE_ENUM(FLAT,     0)
+    GENERATE_ENUM(GOURAUD,  1)
+END_ENUMTYPE(ParamShade)
+
+START_ENUMTYPE(SamplingPattern)
+    GENERATE_ENUM(CENTROID, 0)
+    GENERATE_ENUM(PIXCENTER, 1)
+END_ENUMTYPE(SamplingPattern)
+
+START_ENUMTYPE(MSAASamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     2)
+END_ENUMTYPE(MSAASamples)
+
+START_ENUMTYPE(CopySampleSelect)
+    GENERATE_ENUM(SAMPLE_0, 0)
+    GENERATE_ENUM(SAMPLE_1, 1)
+    GENERATE_ENUM(SAMPLE_2, 2)
+    GENERATE_ENUM(SAMPLE_3, 3)
+    GENERATE_ENUM(SAMPLE_01,    4)
+    GENERATE_ENUM(SAMPLE_23,    5)
+    GENERATE_ENUM(SAMPLE_0123,  6)
+END_ENUMTYPE(CopySampleSelect)
+
+
+#undef START_ENUMTYPE
+#undef GENERATE_ENUM
+#undef END_ENUMTYPE
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h
new file mode 100644
index 000000000000..d04379887b78
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h
@@ -0,0 +1,3405 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_REGISTER(PA_CL_VPORT_XSCALE)
+    GENERATE_FIELD(VPORT_XSCALE, float)
+END_REGISTER(PA_CL_VPORT_XSCALE)
+
+START_REGISTER(PA_CL_VPORT_XOFFSET)
+    GENERATE_FIELD(VPORT_XOFFSET, float)
+END_REGISTER(PA_CL_VPORT_XOFFSET)
+
+START_REGISTER(PA_CL_VPORT_YSCALE)
+    GENERATE_FIELD(VPORT_YSCALE, float)
+END_REGISTER(PA_CL_VPORT_YSCALE)
+
+START_REGISTER(PA_CL_VPORT_YOFFSET)
+    GENERATE_FIELD(VPORT_YOFFSET, float)
+END_REGISTER(PA_CL_VPORT_YOFFSET)
+
+START_REGISTER(PA_CL_VPORT_ZSCALE)
+    GENERATE_FIELD(VPORT_ZSCALE, float)
+END_REGISTER(PA_CL_VPORT_ZSCALE)
+
+START_REGISTER(PA_CL_VPORT_ZOFFSET)
+    GENERATE_FIELD(VPORT_ZOFFSET, float)
+END_REGISTER(PA_CL_VPORT_ZOFFSET)
+
+START_REGISTER(PA_CL_VTE_CNTL)
+    GENERATE_FIELD(VPORT_X_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool)
+    GENERATE_FIELD(VTX_XY_FMT, bool)
+    GENERATE_FIELD(VTX_Z_FMT, bool)
+    GENERATE_FIELD(VTX_W0_FMT, bool)
+    GENERATE_FIELD(PERFCOUNTER_REF, bool)
+END_REGISTER(PA_CL_VTE_CNTL)
+
+START_REGISTER(PA_CL_CLIP_CNTL)
+    GENERATE_FIELD(CLIP_DISABLE, bool)
+    GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool)
+    GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef)
+    GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool)
+    GENERATE_FIELD(VTX_KILL_OR, bool)
+    GENERATE_FIELD(XY_NAN_RETAIN, bool)
+    GENERATE_FIELD(Z_NAN_RETAIN, bool)
+    GENERATE_FIELD(W_NAN_RETAIN, bool)
+END_REGISTER(PA_CL_CLIP_CNTL)
+
+START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+
+START_REGISTER(PA_CL_ENHANCE)
+    GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE0, int)
+END_REGISTER(PA_CL_ENHANCE)
+
+START_REGISTER(PA_SC_ENHANCE)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE0, int)
+END_REGISTER(PA_SC_ENHANCE)
+
+START_REGISTER(PA_SU_VTX_CNTL)
+    GENERATE_FIELD(PIX_CENTER, PixCenter)
+    GENERATE_FIELD(ROUND_MODE, RoundMode)
+    GENERATE_FIELD(QUANT_MODE, QuantMode)
+END_REGISTER(PA_SU_VTX_CNTL)
+
+START_REGISTER(PA_SU_POINT_SIZE)
+    GENERATE_FIELD(HEIGHT, fixed12_4)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_POINT_SIZE)
+
+START_REGISTER(PA_SU_POINT_MINMAX)
+    GENERATE_FIELD(MIN_SIZE, fixed12_4)
+    GENERATE_FIELD(MAX_SIZE, fixed12_4)
+END_REGISTER(PA_SU_POINT_MINMAX)
+
+START_REGISTER(PA_SU_LINE_CNTL)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_LINE_CNTL)
+
+START_REGISTER(PA_SU_FACE_DATA)
+    GENERATE_FIELD(BASE_ADDR, int)
+END_REGISTER(PA_SU_FACE_DATA)
+
+START_REGISTER(PA_SU_SC_MODE_CNTL)
+    GENERATE_FIELD(CULL_FRONT, bool)
+    GENERATE_FIELD(CULL_BACK, bool)
+    GENERATE_FIELD(FACE, FrontFace)
+    GENERATE_FIELD(POLY_MODE, PolyMode)
+    GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType)
+    GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType)
+    GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool)
+    GENERATE_FIELD(MSAA_ENABLE, bool)
+    GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool)
+    GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool)
+    GENERATE_FIELD(PROVOKING_VTX_LAST, bool)
+    GENERATE_FIELD(PERSP_CORR_DIS, bool)
+    GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool)
+    GENERATE_FIELD(QUAD_ORDER_ENABLE, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool)
+    GENERATE_FIELD(CLAMPED_FACENESS, bool)
+    GENERATE_FIELD(ZERO_AREA_FACENESS, bool)
+    GENERATE_FIELD(FACE_KILL_ENABLE, bool)
+    GENERATE_FIELD(FACE_WRITE_ENABLE, bool)
+END_REGISTER(PA_SU_SC_MODE_CNTL)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT)
+END_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_HI)
+
+START_REGISTER(PA_SC_WINDOW_OFFSET)
+    GENERATE_FIELD(WINDOW_X_OFFSET, signedint15)
+    GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15)
+END_REGISTER(PA_SC_WINDOW_OFFSET)
+
+START_REGISTER(PA_SC_AA_CONFIG)
+    GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples)
+    GENERATE_FIELD(MAX_SAMPLE_DIST, int)
+END_REGISTER(PA_SC_AA_CONFIG)
+
+START_REGISTER(PA_SC_AA_MASK)
+    GENERATE_FIELD(AA_MASK, hex)
+END_REGISTER(PA_SC_AA_MASK)
+
+START_REGISTER(PA_SC_LINE_STIPPLE)
+    GENERATE_FIELD(LINE_PATTERN, hex)
+    GENERATE_FIELD(REPEAT_COUNT, intMinusOne)
+    GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder)
+    GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl)
+END_REGISTER(PA_SC_LINE_STIPPLE)
+
+START_REGISTER(PA_SC_LINE_CNTL)
+    GENERATE_FIELD(BRES_CNTL, int)
+    GENERATE_FIELD(USE_BRES_CNTL, bool)
+    GENERATE_FIELD(EXPAND_LINE_WIDTH, bool)
+    GENERATE_FIELD(LAST_PIXEL, bool)
+END_REGISTER(PA_SC_LINE_CNTL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+    GENERATE_FIELD(TL_X, int)
+    GENERATE_FIELD(TL_Y, int)
+    GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+    GENERATE_FIELD(BR_X, int)
+    GENERATE_FIELD(BR_Y, int)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+    GENERATE_FIELD(TL_X, int)
+    GENERATE_FIELD(TL_Y, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+    GENERATE_FIELD(BR_X, int)
+    GENERATE_FIELD(BR_Y, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+
+START_REGISTER(PA_SC_VIZ_QUERY)
+    GENERATE_FIELD(VIZ_QUERY_ENA, bool)
+    GENERATE_FIELD(VIZ_QUERY_ID, int)
+    GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool)
+END_REGISTER(PA_SC_VIZ_QUERY)
+
+START_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+    GENERATE_FIELD(STATUS_BITS, hex)
+END_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+
+START_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+    GENERATE_FIELD(CURRENT_PTR, int)
+    GENERATE_FIELD(CURRENT_COUNT, int)
+END_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT)
+END_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_CL_CNTL_STATUS)
+    GENERATE_FIELD(CL_BUSY, int)
+END_REGISTER(PA_CL_CNTL_STATUS)
+
+START_REGISTER(PA_SU_CNTL_STATUS)
+    GENERATE_FIELD(SU_BUSY, int)
+END_REGISTER(PA_SU_CNTL_STATUS)
+
+START_REGISTER(PA_SC_CNTL_STATUS)
+    GENERATE_FIELD(SC_BUSY, int)
+END_REGISTER(PA_SC_CNTL_STATUS)
+
+START_REGISTER(PA_SU_DEBUG_CNTL)
+    GENERATE_FIELD(SU_DEBUG_INDX, int)
+END_REGISTER(PA_SU_DEBUG_CNTL)
+
+START_REGISTER(PA_SU_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(PA_SU_DEBUG_DATA)
+
+START_REGISTER(PA_SC_DEBUG_CNTL)
+    GENERATE_FIELD(SC_DEBUG_INDX, int)
+END_REGISTER(PA_SC_DEBUG_CNTL)
+
+START_REGISTER(PA_SC_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(PA_SC_DEBUG_DATA)
+
+START_REGISTER(GFX_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+END_REGISTER(GFX_COPY_STATE)
+
+START_REGISTER(VGT_DRAW_INITIATOR)
+    GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE)
+    GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT)
+    GENERATE_FIELD(FACENESS_CULL_SELECT, VGT_DI_FACENESS_CULL_SELECT)
+    GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE)
+    GENERATE_FIELD(NOT_EOP, bool)
+    GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX)
+    GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_FIELD(NUM_INDICES, uint)
+END_REGISTER(VGT_DRAW_INITIATOR)
+
+START_REGISTER(VGT_EVENT_INITIATOR)
+    GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE)
+END_REGISTER(VGT_EVENT_INITIATOR)
+
+START_REGISTER(VGT_DMA_BASE)
+    GENERATE_FIELD(BASE_ADDR, uint)
+END_REGISTER(VGT_DMA_BASE)
+
+START_REGISTER(VGT_DMA_SIZE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+    GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE)
+END_REGISTER(VGT_DMA_SIZE)
+
+START_REGISTER(VGT_BIN_BASE)
+    GENERATE_FIELD(BIN_BASE_ADDR, uint)
+END_REGISTER(VGT_BIN_BASE)
+
+START_REGISTER(VGT_BIN_SIZE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+    GENERATE_FIELD(FACENESS_FETCH, int)
+    GENERATE_FIELD(FACENESS_RESET, int)
+END_REGISTER(VGT_BIN_SIZE)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+    GENERATE_FIELD(COLUMN, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(GUARD_BAND, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+    GENERATE_FIELD(COLUMN, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(GUARD_BAND, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+
+START_REGISTER(VGT_IMMED_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_IMMED_DATA)
+
+START_REGISTER(VGT_MAX_VTX_INDX)
+    GENERATE_FIELD(MAX_INDX, int)
+END_REGISTER(VGT_MAX_VTX_INDX)
+
+START_REGISTER(VGT_MIN_VTX_INDX)
+    GENERATE_FIELD(MIN_INDX, int)
+END_REGISTER(VGT_MIN_VTX_INDX)
+
+START_REGISTER(VGT_INDX_OFFSET)
+    GENERATE_FIELD(INDX_OFFSET, int)
+END_REGISTER(VGT_INDX_OFFSET)
+
+START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+    GENERATE_FIELD(VTX_REUSE_DEPTH, int)
+END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+
+START_REGISTER(VGT_OUT_DEALLOC_CNTL)
+    GENERATE_FIELD(DEALLOC_DIST, int)
+END_REGISTER(VGT_OUT_DEALLOC_CNTL)
+
+START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+    GENERATE_FIELD(RESET_INDX, int)
+END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+
+START_REGISTER(VGT_ENHANCE)
+    GENERATE_FIELD(MISC, hex)
+END_REGISTER(VGT_ENHANCE)
+
+START_REGISTER(VGT_VTX_VECT_EJECT_REG)
+    GENERATE_FIELD(PRIM_COUNT, int)
+END_REGISTER(VGT_VTX_VECT_EJECT_REG)
+
+START_REGISTER(VGT_LAST_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+    GENERATE_FIELD(DST_STATE_ID, int)
+END_REGISTER(VGT_LAST_COPY_STATE)
+
+START_REGISTER(VGT_DEBUG_CNTL)
+    GENERATE_FIELD(VGT_DEBUG_INDX, int)
+END_REGISTER(VGT_DEBUG_CNTL)
+
+START_REGISTER(VGT_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_DEBUG_DATA)
+
+START_REGISTER(VGT_CNTL_STATUS)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_REQ_BUSY, int)
+    GENERATE_FIELD(VGT_GRP_BUSY, int)
+    GENERATE_FIELD(VGT_VR_BUSY, int)
+    GENERATE_FIELD(VGT_BIN_BUSY, int)
+    GENERATE_FIELD(VGT_PT_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_INDX_BUSY, int)
+END_REGISTER(VGT_CNTL_STATUS)
+
+START_REGISTER(VGT_CRC_SQ_DATA)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_DATA)
+
+START_REGISTER(VGT_CRC_SQ_CTRL)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_CTRL)
+
+START_REGISTER(VGT_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER0_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER1_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER2_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER3_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_HI)
+
+START_REGISTER(VGT_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_HI)
+
+START_REGISTER(VGT_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_HI)
+
+START_REGISTER(VGT_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_HI)
+
+START_REGISTER(TC_CNTL_STATUS)
+    GENERATE_FIELD(L2_INVALIDATE, int)
+    GENERATE_FIELD(TC_L2_HIT_MISS, int)
+    GENERATE_FIELD(TC_BUSY, int)
+END_REGISTER(TC_CNTL_STATUS)
+
+START_REGISTER(TCR_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCR_CHICKEN)
+
+START_REGISTER(TCF_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCF_CHICKEN)
+
+START_REGISTER(TCM_CHICKEN)
+    GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int)
+    GENERATE_FIELD(ETC_COLOR_ENDIAN, int)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCM_CHICKEN)
+
+START_REGISTER(TCR_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER0_HI)
+
+START_REGISTER(TCR_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER1_HI)
+
+START_REGISTER(TCR_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCR_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER1_LOW)
+
+START_REGISTER(TP_TC_CLKGATE_CNTL)
+    GENERATE_FIELD(TP_BUSY_EXTEND, int)
+    GENERATE_FIELD(TC_BUSY_EXTEND, int)
+END_REGISTER(TP_TC_CLKGATE_CNTL)
+
+START_REGISTER(TPC_CNTL_STATUS)
+    GENERATE_FIELD(TPC_INPUT_BUSY, int)
+    GENERATE_FIELD(TPC_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TPC_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_BUSY, int)
+    GENERATE_FIELD(TF_TW_RTS, int)
+    GENERATE_FIELD(TF_TW_STATE_RTS, int)
+    GENERATE_FIELD(TF_TW_RTR, int)
+    GENERATE_FIELD(TW_TA_RTS, int)
+    GENERATE_FIELD(TW_TA_TT_RTS, int)
+    GENERATE_FIELD(TW_TA_LAST_RTS, int)
+    GENERATE_FIELD(TW_TA_RTR, int)
+    GENERATE_FIELD(TA_TB_RTS, int)
+    GENERATE_FIELD(TA_TB_TT_RTS, int)
+    GENERATE_FIELD(TA_TB_RTR, int)
+    GENERATE_FIELD(TA_TF_RTS, int)
+    GENERATE_FIELD(TA_TF_TC_FIFO_REN, int)
+    GENERATE_FIELD(TP_SQ_DEC, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+END_REGISTER(TPC_CNTL_STATUS)
+
+START_REGISTER(TPC_DEBUG0)
+    GENERATE_FIELD(LOD_CNTL, int)
+    GENERATE_FIELD(IC_CTR, int)
+    GENERATE_FIELD(WALKER_CNTL, int)
+    GENERATE_FIELD(ALIGNER_CNTL, int)
+    GENERATE_FIELD(PREV_TC_STATE_VALID, int)
+    GENERATE_FIELD(WALKER_STATE, int)
+    GENERATE_FIELD(ALIGNER_STATE, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(TPC_CLK_EN, int)
+    GENERATE_FIELD(SQ_TP_WAKEUP, int)
+END_REGISTER(TPC_DEBUG0)
+
+START_REGISTER(TPC_DEBUG1)
+    GENERATE_FIELD(UNUSED, int)
+END_REGISTER(TPC_DEBUG1)
+
+START_REGISTER(TPC_CHICKEN)
+    GENERATE_FIELD(BLEND_PRECISION, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(TPC_CHICKEN)
+
+START_REGISTER(TP0_CNTL_STATUS)
+    GENERATE_FIELD(TP_INPUT_BUSY, int)
+    GENERATE_FIELD(TP_LOD_BUSY, int)
+    GENERATE_FIELD(TP_LOD_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ADDR_BUSY, int)
+    GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TP_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_FETCH_BUSY, int)
+    GENERATE_FIELD(TP_CH_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_TT_BUSY, int)
+    GENERATE_FIELD(TP_HICOLOR_BUSY, int)
+    GENERATE_FIELD(TP_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_OUTPUT_BUSY, int)
+    GENERATE_FIELD(IN_LC_RTS, int)
+    GENERATE_FIELD(LC_LA_RTS, int)
+    GENERATE_FIELD(LA_FL_RTS, int)
+    GENERATE_FIELD(FL_TA_RTS, int)
+    GENERATE_FIELD(TA_FA_RTS, int)
+    GENERATE_FIELD(TA_FA_TT_RTS, int)
+    GENERATE_FIELD(FA_AL_RTS, int)
+    GENERATE_FIELD(FA_AL_TT_RTS, int)
+    GENERATE_FIELD(AL_TF_RTS, int)
+    GENERATE_FIELD(AL_TF_TT_RTS, int)
+    GENERATE_FIELD(TF_TB_RTS, int)
+    GENERATE_FIELD(TF_TB_TT_RTS, int)
+    GENERATE_FIELD(TB_TT_RTS, int)
+    GENERATE_FIELD(TB_TT_TT_RESET, int)
+    GENERATE_FIELD(TB_TO_RTS, int)
+    GENERATE_FIELD(TP_BUSY, int)
+END_REGISTER(TP0_CNTL_STATUS)
+
+START_REGISTER(TP0_DEBUG)
+    GENERATE_FIELD(Q_LOD_CNTL, int)
+    GENERATE_FIELD(Q_SQ_TP_WAKEUP, int)
+    GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(PERF_CLK_EN, int)
+    GENERATE_FIELD(TP_CLK_EN, int)
+    GENERATE_FIELD(Q_WALKER_CNTL, int)
+    GENERATE_FIELD(Q_ALIGNER_CNTL, int)
+END_REGISTER(TP0_DEBUG)
+
+START_REGISTER(TP0_CHICKEN)
+    GENERATE_FIELD(TT_MODE, int)
+    GENERATE_FIELD(VFETCH_ADDRESS_MODE, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(TP0_CHICKEN)
+
+START_REGISTER(TP0_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT)
+END_REGISTER(TP0_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER0_HI)
+
+START_REGISTER(TP0_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER0_LOW)
+
+START_REGISTER(TP0_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, int)
+END_REGISTER(TP0_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER1_HI)
+
+START_REGISTER(TP0_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER0_HI)
+
+START_REGISTER(TCM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER1_HI)
+
+START_REGISTER(TCM_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER2_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER3_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER4_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER4_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER5_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER5_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER6_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER6_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER7_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER7_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER8_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER8_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER9_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER9_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER10_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER10_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER11_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER11_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER0_HI)
+
+START_REGISTER(TCF_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER1_HI)
+
+START_REGISTER(TCF_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER2_HI)
+
+START_REGISTER(TCF_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER3_HI)
+
+START_REGISTER(TCF_PERFCOUNTER4_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER4_HI)
+
+START_REGISTER(TCF_PERFCOUNTER5_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER5_HI)
+
+START_REGISTER(TCF_PERFCOUNTER6_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER6_HI)
+
+START_REGISTER(TCF_PERFCOUNTER7_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER7_HI)
+
+START_REGISTER(TCF_PERFCOUNTER8_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER8_HI)
+
+START_REGISTER(TCF_PERFCOUNTER9_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER9_HI)
+
+START_REGISTER(TCF_PERFCOUNTER10_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER10_HI)
+
+START_REGISTER(TCF_PERFCOUNTER11_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER11_HI)
+
+START_REGISTER(TCF_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER2_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER3_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER4_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER4_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER5_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER5_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER6_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER6_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER7_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER7_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER8_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER8_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER9_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER9_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER10_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER10_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER11_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER11_LOW)
+
+START_REGISTER(TCF_DEBUG)
+    GENERATE_FIELD(not_MH_TC_rtr, int)
+    GENERATE_FIELD(TC_MH_send, int)
+    GENERATE_FIELD(not_FG0_rtr, int)
+    GENERATE_FIELD(not_TCB_TCO_rtr, int)
+    GENERATE_FIELD(TCB_ff_stall, int)
+    GENERATE_FIELD(TCB_miss_stall, int)
+    GENERATE_FIELD(TCA_TCB_stall, int)
+    GENERATE_FIELD(PF0_stall, int)
+    GENERATE_FIELD(TP0_full, int)
+    GENERATE_FIELD(TPC_full, int)
+    GENERATE_FIELD(not_TPC_rtr, int)
+    GENERATE_FIELD(tca_state_rts, int)
+    GENERATE_FIELD(tca_rts, int)
+END_REGISTER(TCF_DEBUG)
+
+START_REGISTER(TCA_FIFO_DEBUG)
+    GENERATE_FIELD(tp0_full, int)
+    GENERATE_FIELD(tpc_full, int)
+    GENERATE_FIELD(load_tpc_fifo, int)
+    GENERATE_FIELD(load_tp_fifos, int)
+    GENERATE_FIELD(FW_full, int)
+    GENERATE_FIELD(not_FW_rtr0, int)
+    GENERATE_FIELD(FW_rts0, int)
+    GENERATE_FIELD(not_FW_tpc_rtr, int)
+    GENERATE_FIELD(FW_tpc_rts, int)
+END_REGISTER(TCA_FIFO_DEBUG)
+
+START_REGISTER(TCA_PROBE_DEBUG)
+    GENERATE_FIELD(ProbeFilter_stall, int)
+END_REGISTER(TCA_PROBE_DEBUG)
+
+START_REGISTER(TCA_TPC_DEBUG)
+    GENERATE_FIELD(captue_state_rts, int)
+    GENERATE_FIELD(capture_tca_rts, int)
+END_REGISTER(TCA_TPC_DEBUG)
+
+START_REGISTER(TCB_CORE_DEBUG)
+    GENERATE_FIELD(access512, int)
+    GENERATE_FIELD(tiled, int)
+    GENERATE_FIELD(opcode, int)
+    GENERATE_FIELD(format, int)
+    GENERATE_FIELD(sector_format, int)
+    GENERATE_FIELD(sector_format512, int)
+END_REGISTER(TCB_CORE_DEBUG)
+
+START_REGISTER(TCB_TAG0_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG0_DEBUG)
+
+START_REGISTER(TCB_TAG1_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG1_DEBUG)
+
+START_REGISTER(TCB_TAG2_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG2_DEBUG)
+
+START_REGISTER(TCB_TAG3_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG3_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+    GENERATE_FIELD(left_done, int)
+    GENERATE_FIELD(fg0_sends_left, int)
+    GENERATE_FIELD(one_sector_to_go_left_q, int)
+    GENERATE_FIELD(no_sectors_to_go, int)
+    GENERATE_FIELD(update_left, int)
+    GENERATE_FIELD(sector_mask_left_count_q, int)
+    GENERATE_FIELD(sector_mask_left_q, int)
+    GENERATE_FIELD(valid_left_q, int)
+END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+    GENERATE_FIELD(quad_sel_left, int)
+    GENERATE_FIELD(set_sel_left, int)
+    GENERATE_FIELD(right_eq_left, int)
+    GENERATE_FIELD(ff_fg_type512, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(setquads_to_send, int)
+END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+    GENERATE_FIELD(tc0_arb_rts, int)
+    GENERATE_FIELD(ga_out_rts, int)
+    GENERATE_FIELD(tc_arb_format, int)
+    GENERATE_FIELD(tc_arb_fmsopcode, int)
+    GENERATE_FIELD(tc_arb_request_type, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(fgo_busy, int)
+    GENERATE_FIELD(ga_busy, int)
+    GENERATE_FIELD(mc_sel_q, int)
+    GENERATE_FIELD(valid_q, int)
+    GENERATE_FIELD(arb_RTR, int)
+END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+
+START_REGISTER(TCD_INPUT0_DEBUG)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(valid_q1, int)
+    GENERATE_FIELD(cnt_q1, int)
+    GENERATE_FIELD(last_send_q1, int)
+    GENERATE_FIELD(ip_send, int)
+    GENERATE_FIELD(ipbuf_dxt_send, int)
+    GENERATE_FIELD(ipbuf_busy, int)
+END_REGISTER(TCD_INPUT0_DEBUG)
+
+START_REGISTER(TCD_DEGAMMA_DEBUG)
+    GENERATE_FIELD(dgmm_ftfconv_dgmmen, int)
+    GENERATE_FIELD(dgmm_ctrl_dgmm8, int)
+    GENERATE_FIELD(dgmm_ctrl_last_send, int)
+    GENERATE_FIELD(dgmm_ctrl_send, int)
+    GENERATE_FIELD(dgmm_stall, int)
+    GENERATE_FIELD(dgmm_pstate, int)
+END_REGISTER(TCD_DEGAMMA_DEBUG)
+
+START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(sctrmx_rtr, int)
+    GENERATE_FIELD(dxtc_rtr, int)
+    GENERATE_FIELD(sctrarb_multcyl_send, int)
+    GENERATE_FIELD(sctrmx0_sctrarb_rts, int)
+    GENERATE_FIELD(dxtc_sctrarb_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_last_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_send, int)
+    GENERATE_FIELD(dcmp_mux_send, int)
+END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+
+START_REGISTER(TCD_DXTC_ARB_DEBUG)
+    GENERATE_FIELD(n0_stall, int)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(arb_dcmp01_last_send, int)
+    GENERATE_FIELD(arb_dcmp01_cnt, int)
+    GENERATE_FIELD(arb_dcmp01_sector, int)
+    GENERATE_FIELD(arb_dcmp01_cacheline, int)
+    GENERATE_FIELD(arb_dcmp01_format, int)
+    GENERATE_FIELD(arb_dcmp01_send, int)
+    GENERATE_FIELD(n0_dxt2_4_types, int)
+END_REGISTER(TCD_DXTC_ARB_DEBUG)
+
+START_REGISTER(TCD_STALLS_DEBUG)
+    GENERATE_FIELD(not_multcyl_sctrarb_rtr, int)
+    GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int)
+    GENERATE_FIELD(not_dcmp0_arb_rtr, int)
+    GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int)
+    GENERATE_FIELD(not_mux_dcmp_rtr, int)
+    GENERATE_FIELD(not_incoming_rtr, int)
+END_REGISTER(TCD_STALLS_DEBUG)
+
+START_REGISTER(TCO_STALLS_DEBUG)
+    GENERATE_FIELD(quad0_sg_crd_RTR, int)
+    GENERATE_FIELD(quad0_rl_sg_RTR, int)
+    GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int)
+END_REGISTER(TCO_STALLS_DEBUG)
+
+START_REGISTER(TCO_QUAD0_DEBUG0)
+    GENERATE_FIELD(rl_sg_sector_format, int)
+    GENERATE_FIELD(rl_sg_end_of_sample, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(sg_crd_end_of_sample, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(stageN1_valid_q, int)
+    GENERATE_FIELD(read_cache_q, int)
+    GENERATE_FIELD(cache_read_RTR, int)
+    GENERATE_FIELD(all_sectors_written_set3, int)
+    GENERATE_FIELD(all_sectors_written_set2, int)
+    GENERATE_FIELD(all_sectors_written_set1, int)
+    GENERATE_FIELD(all_sectors_written_set0, int)
+    GENERATE_FIELD(busy, int)
+END_REGISTER(TCO_QUAD0_DEBUG0)
+
+START_REGISTER(TCO_QUAD0_DEBUG1)
+    GENERATE_FIELD(fifo_busy, int)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(write_enable, int)
+    GENERATE_FIELD(fifo_write_ptr, int)
+    GENERATE_FIELD(fifo_read_ptr, int)
+    GENERATE_FIELD(cache_read_busy, int)
+    GENERATE_FIELD(latency_fifo_busy, int)
+    GENERATE_FIELD(input_quad_busy, int)
+    GENERATE_FIELD(tco_quad_pipe_busy, int)
+    GENERATE_FIELD(TCB_TCO_rtr_d, int)
+    GENERATE_FIELD(TCB_TCO_xfc_q, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(TCO_TCB_read_xfc, int)
+END_REGISTER(TCO_QUAD0_DEBUG1)
+
+START_REGISTER(SQ_GPR_MANAGEMENT)
+    GENERATE_FIELD(REG_DYNAMIC, int)
+    GENERATE_FIELD(REG_SIZE_PIX, int)
+    GENERATE_FIELD(REG_SIZE_VTX, int)
+END_REGISTER(SQ_GPR_MANAGEMENT)
+
+START_REGISTER(SQ_FLOW_CONTROL)
+    GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(ONE_THREAD, int)
+    GENERATE_FIELD(ONE_ALU, int)
+    GENERATE_FIELD(CF_WR_BASE, hex)
+    GENERATE_FIELD(NO_PV_PS, int)
+    GENERATE_FIELD(NO_LOOP_EXIT, int)
+    GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int)
+    GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(VC_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(ALU_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(NO_ARB_EJECT, int)
+    GENERATE_FIELD(NO_CFS_EJECT, int)
+    GENERATE_FIELD(POS_EXP_PRIORITY, int)
+    GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int)
+    GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int)
+END_REGISTER(SQ_FLOW_CONTROL)
+
+START_REGISTER(SQ_INST_STORE_MANAGMENT)
+    GENERATE_FIELD(INST_BASE_PIX, int)
+    GENERATE_FIELD(INST_BASE_VTX, int)
+END_REGISTER(SQ_INST_STORE_MANAGMENT)
+
+START_REGISTER(SQ_RESOURCE_MANAGMENT)
+    GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(EXPORT_BUF_ENTRIES, int)
+END_REGISTER(SQ_RESOURCE_MANAGMENT)
+
+START_REGISTER(SQ_EO_RT)
+    GENERATE_FIELD(EO_CONSTANTS_RT, int)
+    GENERATE_FIELD(EO_TSTATE_RT, int)
+END_REGISTER(SQ_EO_RT)
+
+START_REGISTER(SQ_DEBUG_MISC)
+    GENERATE_FIELD(DB_ALUCST_SIZE, int)
+    GENERATE_FIELD(DB_TSTATE_SIZE, int)
+    GENERATE_FIELD(DB_READ_CTX, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DB_READ_MEMORY, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_0, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_1, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_2, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_3, int)
+END_REGISTER(SQ_DEBUG_MISC)
+
+START_REGISTER(SQ_ACTIVITY_METER_CNTL)
+    GENERATE_FIELD(TIMEBASE, int)
+    GENERATE_FIELD(THRESHOLD_LOW, int)
+    GENERATE_FIELD(THRESHOLD_HIGH, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(SQ_ACTIVITY_METER_CNTL)
+
+START_REGISTER(SQ_ACTIVITY_METER_STATUS)
+    GENERATE_FIELD(PERCENT_BUSY, int)
+END_REGISTER(SQ_ACTIVITY_METER_STATUS)
+
+START_REGISTER(SQ_INPUT_ARB_PRIORITY)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(THRESHOLD, int)
+END_REGISTER(SQ_INPUT_ARB_PRIORITY)
+
+START_REGISTER(SQ_THREAD_ARB_PRIORITY)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(THRESHOLD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int)
+END_REGISTER(SQ_THREAD_ARB_PRIORITY)
+
+START_REGISTER(SQ_VS_WATCHDOG_TIMER)
+    GENERATE_FIELD(ENABLE, int)
+    GENERATE_FIELD(TIMEOUT_COUNT, int)
+END_REGISTER(SQ_VS_WATCHDOG_TIMER)
+
+START_REGISTER(SQ_PS_WATCHDOG_TIMER)
+    GENERATE_FIELD(ENABLE, int)
+    GENERATE_FIELD(TIMEOUT_COUNT, int)
+END_REGISTER(SQ_PS_WATCHDOG_TIMER)
+
+START_REGISTER(SQ_INT_CNTL)
+    GENERATE_FIELD(PS_WATCHDOG_MASK, int)
+    GENERATE_FIELD(VS_WATCHDOG_MASK, int)
+END_REGISTER(SQ_INT_CNTL)
+
+START_REGISTER(SQ_INT_STATUS)
+    GENERATE_FIELD(PS_WATCHDOG_TIMEOUT, int)
+    GENERATE_FIELD(VS_WATCHDOG_TIMEOUT, int)
+END_REGISTER(SQ_INT_STATUS)
+
+START_REGISTER(SQ_INT_ACK)
+    GENERATE_FIELD(PS_WATCHDOG_ACK, int)
+    GENERATE_FIELD(VS_WATCHDOG_ACK, int)
+END_REGISTER(SQ_INT_ACK)
+
+START_REGISTER(SQ_DEBUG_INPUT_FSM)
+    GENERATE_FIELD(VC_VSR_LD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VC_GPR_LD, int)
+    GENERATE_FIELD(PC_PISM, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PC_AS, int)
+    GENERATE_FIELD(PC_INTERP_CNT, int)
+    GENERATE_FIELD(PC_GPR_SIZE, int)
+END_REGISTER(SQ_DEBUG_INPUT_FSM)
+
+START_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+    GENERATE_FIELD(TEX_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(ALU_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(ALU_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(TEX_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int)
+END_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+
+START_REGISTER(SQ_DEBUG_TP_FSM)
+    GENERATE_FIELD(EX_TP, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_TP, int)
+    GENERATE_FIELD(IF_TP, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(TIS_TP, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(GS_TP, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(FCR_TP, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(FCS_TP, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_TP, int)
+END_REGISTER(SQ_DEBUG_TP_FSM)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_0)
+    GENERATE_FIELD(EX_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_0)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_1)
+    GENERATE_FIELD(EX_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_1)
+
+START_REGISTER(SQ_DEBUG_EXP_ALLOC)
+    GENERATE_FIELD(POS_BUF_AVAIL, int)
+    GENERATE_FIELD(COLOR_BUF_AVAIL, int)
+    GENERATE_FIELD(EA_BUF_AVAIL, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int)
+END_REGISTER(SQ_DEBUG_EXP_ALLOC)
+
+START_REGISTER(SQ_DEBUG_PTR_BUFF)
+    GENERATE_FIELD(END_OF_BUFFER, int)
+    GENERATE_FIELD(DEALLOC_CNT, int)
+    GENERATE_FIELD(QUAL_NEW_VECTOR, int)
+    GENERATE_FIELD(EVENT_CONTEXT_ID, int)
+    GENERATE_FIELD(SC_EVENT_ID, int)
+    GENERATE_FIELD(QUAL_EVENT, int)
+    GENERATE_FIELD(PRIM_TYPE_POLYGON, int)
+    GENERATE_FIELD(EF_EMPTY, int)
+    GENERATE_FIELD(VTX_SYNC_CNT, int)
+END_REGISTER(SQ_DEBUG_PTR_BUFF)
+
+START_REGISTER(SQ_DEBUG_GPR_VTX)
+    GENERATE_FIELD(VTX_TAIL_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VTX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(VTX_MAX, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(VTX_FREE, int)
+END_REGISTER(SQ_DEBUG_GPR_VTX)
+
+START_REGISTER(SQ_DEBUG_GPR_PIX)
+    GENERATE_FIELD(PIX_TAIL_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PIX_MAX, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(PIX_FREE, int)
+END_REGISTER(SQ_DEBUG_GPR_PIX)
+
+START_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+    GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VC_THREAD_BUF_DLY, int)
+    GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int)
+END_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_0)
+    GENERATE_FIELD(VTX_HEAD_PTR_Q, int)
+    GENERATE_FIELD(TAIL_PTR_Q, int)
+    GENERATE_FIELD(FULL_CNT_Q, int)
+    GENERATE_FIELD(NXT_POS_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_PC_ALLOC_CNT, int)
+    GENERATE_FIELD(SX_EVENT_FULL, int)
+    GENERATE_FIELD(BUSY_Q, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_0)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_1)
+    GENERATE_FIELD(VS_DONE_PTR, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_1)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+    GENERATE_FIELD(VS_STATUS_REG, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+    GENERATE_FIELD(VS_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_0)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(TAIL_PTR, int)
+    GENERATE_FIELD(FULL_CNT, int)
+    GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_PIX_EXP_CNT, int)
+    GENERATE_FIELD(BUSY, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_0, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_1, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_2, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_3, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+    GENERATE_FIELD(PIX_TB_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+
+START_REGISTER(SQ_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT)
+END_REGISTER(SQ_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER1_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER2_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER3_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_HI)
+
+START_REGISTER(SQ_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_HI)
+
+START_REGISTER(SQ_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_HI)
+
+START_REGISTER(SX_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT)
+END_REGISTER(SX_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SX_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_LOW)
+
+START_REGISTER(SX_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_0)
+    GENERATE_FIELD(VECTOR_RESULT, int)
+    GENERATE_FIELD(VECTOR_DST_REL, Abs_modifier)
+    GENERATE_FIELD(LOW_PRECISION_16B_FP, int)
+    GENERATE_FIELD(SCALAR_RESULT, int)
+    GENERATE_FIELD(SCALAR_DST_REL, int)
+    GENERATE_FIELD(EXPORT_DATA, Exporting)
+    GENERATE_FIELD(VECTOR_WRT_MSK, int)
+    GENERATE_FIELD(SCALAR_WRT_MSK, int)
+    GENERATE_FIELD(VECTOR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode)
+END_REGISTER(SQ_INSTRUCTION_ALU_0)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_1)
+    GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier)
+    GENERATE_FIELD(PRED_SELECT, PredicateSelect)
+    GENERATE_FIELD(RELATIVE_ADDR, int)
+    GENERATE_FIELD(CONST_1_REL_ABS, int)
+    GENERATE_FIELD(CONST_0_REL_ABS, int)
+END_REGISTER(SQ_INSTRUCTION_ALU_1)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_2)
+    GENERATE_FIELD(SRC_C_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_C, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier)
+    GENERATE_FIELD(SRC_B_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_B, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier)
+    GENERATE_FIELD(SRC_A_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_A, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier)
+    GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode)
+    GENERATE_FIELD(SRC_C_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_B_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_A_SEL, OperandSelect0)
+END_REGISTER(SQ_INSTRUCTION_ALU_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(YIELD, int)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(YIELD, int)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(PREDICATED_JMP, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(RESERVED_2, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+    GENERATE_FIELD(OPCODE, TexInstOpcode)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, Addressmode)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(DST_GPR_AM, Addressmode)
+    GENERATE_FIELD(FETCH_VALID_ONLY, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm)
+    GENERATE_FIELD(SRC_SEL_X, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Y, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Z, SrcSel)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+    GENERATE_FIELD(DST_SEL_X, DstSel)
+    GENERATE_FIELD(DST_SEL_Y, DstSel)
+    GENERATE_FIELD(DST_SEL_Z, DstSel)
+    GENERATE_FIELD(DST_SEL_W, DstSel)
+    GENERATE_FIELD(MAG_FILTER, MagFilter)
+    GENERATE_FIELD(MIN_FILTER, MinFilter)
+    GENERATE_FIELD(MIP_FILTER, MipFilter)
+    GENERATE_FIELD(ANISO_FILTER, AnisoFilter)
+    GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter)
+    GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter)
+    GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter)
+    GENERATE_FIELD(USE_COMP_LOD, int)
+    GENERATE_FIELD(USE_REG_LOD, int)
+    GENERATE_FIELD(PRED_SELECT, PredSelect)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+    GENERATE_FIELD(USE_REG_GRADIENTS, int)
+    GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation)
+    GENERATE_FIELD(LOD_BIAS, int)
+    GENERATE_FIELD(UNUSED, int)
+    GENERATE_FIELD(OFFSET_X, int)
+    GENERATE_FIELD(OFFSET_Y, int)
+    GENERATE_FIELD(OFFSET_Z, int)
+    GENERATE_FIELD(PRED_CONDITION, int)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+    GENERATE_FIELD(OPCODE, int)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, int)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(DST_GPR_AM, int)
+    GENERATE_FIELD(MUST_BE_ONE, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(CONST_INDEX_SEL, int)
+    GENERATE_FIELD(SRC_SEL, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+    GENERATE_FIELD(DST_SEL_X, int)
+    GENERATE_FIELD(DST_SEL_Y, int)
+    GENERATE_FIELD(DST_SEL_Z, int)
+    GENERATE_FIELD(DST_SEL_W, int)
+    GENERATE_FIELD(FORMAT_COMP_ALL, int)
+    GENERATE_FIELD(NUM_FORMAT_ALL, int)
+    GENERATE_FIELD(SIGNED_RF_MODE_ALL, int)
+    GENERATE_FIELD(DATA_FORMAT, int)
+    GENERATE_FIELD(EXP_ADJUST_ALL, int)
+    GENERATE_FIELD(PRED_SELECT, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+    GENERATE_FIELD(STRIDE, int)
+    GENERATE_FIELD(OFFSET, int)
+    GENERATE_FIELD(PRED_CONDITION, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+
+START_REGISTER(SQ_CONSTANT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_0)
+
+START_REGISTER(SQ_CONSTANT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_1)
+
+START_REGISTER(SQ_CONSTANT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_2)
+
+START_REGISTER(SQ_CONSTANT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_3)
+
+START_REGISTER(SQ_FETCH_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_0)
+
+START_REGISTER(SQ_FETCH_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_1)
+
+START_REGISTER(SQ_FETCH_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_2)
+
+START_REGISTER(SQ_FETCH_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_3)
+
+START_REGISTER(SQ_FETCH_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_4)
+
+START_REGISTER(SQ_FETCH_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_5)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_0)
+    GENERATE_FIELD(TYPE, int)
+    GENERATE_FIELD(STATE, int)
+    GENERATE_FIELD(BASE_ADDRESS, hex)
+END_REGISTER(SQ_CONSTANT_VFETCH_0)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_1)
+    GENERATE_FIELD(ENDIAN_SWAP, int)
+    GENERATE_FIELD(LIMIT_ADDRESS, hex)
+END_REGISTER(SQ_CONSTANT_VFETCH_1)
+
+START_REGISTER(SQ_CONSTANT_T2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T2)
+
+START_REGISTER(SQ_CONSTANT_T3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T3)
+
+START_REGISTER(SQ_CF_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+END_REGISTER(SQ_CF_BOOLEANS)
+
+START_REGISTER(SQ_CF_LOOP)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+END_REGISTER(SQ_CF_LOOP)
+
+START_REGISTER(SQ_CONSTANT_RT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_RT_0)
+
+START_REGISTER(SQ_CONSTANT_RT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_RT_1)
+
+START_REGISTER(SQ_CONSTANT_RT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_RT_2)
+
+START_REGISTER(SQ_CONSTANT_RT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_0)
+
+START_REGISTER(SQ_FETCH_RT_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_1)
+
+START_REGISTER(SQ_FETCH_RT_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_2)
+
+START_REGISTER(SQ_FETCH_RT_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_4)
+
+START_REGISTER(SQ_FETCH_RT_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_5)
+
+START_REGISTER(SQ_CF_RT_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+END_REGISTER(SQ_CF_RT_BOOLEANS)
+
+START_REGISTER(SQ_CF_RT_LOOP)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+END_REGISTER(SQ_CF_RT_LOOP)
+
+START_REGISTER(SQ_VS_PROGRAM)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_VS_PROGRAM)
+
+START_REGISTER(SQ_PS_PROGRAM)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_PS_PROGRAM)
+
+START_REGISTER(SQ_CF_PROGRAM_SIZE)
+    GENERATE_FIELD(VS_CF_SIZE, int)
+    GENERATE_FIELD(PS_CF_SIZE, int)
+END_REGISTER(SQ_CF_PROGRAM_SIZE)
+
+START_REGISTER(SQ_INTERPOLATOR_CNTL)
+    GENERATE_FIELD(PARAM_SHADE, ParamShade)
+    GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern)
+END_REGISTER(SQ_INTERPOLATOR_CNTL)
+
+START_REGISTER(SQ_PROGRAM_CNTL)
+    GENERATE_FIELD(VS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(PS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(VS_RESOURCE, int)
+    GENERATE_FIELD(PS_RESOURCE, int)
+    GENERATE_FIELD(PARAM_GEN, int)
+    GENERATE_FIELD(GEN_INDEX_PIX, int)
+    GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne)
+    GENERATE_FIELD(VS_EXPORT_MODE, VertexMode)
+    GENERATE_FIELD(PS_EXPORT_MODE, int)
+    GENERATE_FIELD(GEN_INDEX_VTX, int)
+END_REGISTER(SQ_PROGRAM_CNTL)
+
+START_REGISTER(SQ_WRAPPING_0)
+    GENERATE_FIELD(PARAM_WRAP_0, hex)
+    GENERATE_FIELD(PARAM_WRAP_1, hex)
+    GENERATE_FIELD(PARAM_WRAP_2, hex)
+    GENERATE_FIELD(PARAM_WRAP_3, hex)
+    GENERATE_FIELD(PARAM_WRAP_4, hex)
+    GENERATE_FIELD(PARAM_WRAP_5, hex)
+    GENERATE_FIELD(PARAM_WRAP_6, hex)
+    GENERATE_FIELD(PARAM_WRAP_7, hex)
+END_REGISTER(SQ_WRAPPING_0)
+
+START_REGISTER(SQ_WRAPPING_1)
+    GENERATE_FIELD(PARAM_WRAP_8, hex)
+    GENERATE_FIELD(PARAM_WRAP_9, hex)
+    GENERATE_FIELD(PARAM_WRAP_10, hex)
+    GENERATE_FIELD(PARAM_WRAP_11, hex)
+    GENERATE_FIELD(PARAM_WRAP_12, hex)
+    GENERATE_FIELD(PARAM_WRAP_13, hex)
+    GENERATE_FIELD(PARAM_WRAP_14, hex)
+    GENERATE_FIELD(PARAM_WRAP_15, hex)
+END_REGISTER(SQ_WRAPPING_1)
+
+START_REGISTER(SQ_VS_CONST)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_VS_CONST)
+
+START_REGISTER(SQ_PS_CONST)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_PS_CONST)
+
+START_REGISTER(SQ_CONTEXT_MISC)
+    GENERATE_FIELD(INST_PRED_OPTIMIZE, int)
+    GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int)
+    GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl)
+    GENERATE_FIELD(PARAM_GEN_POS, int)
+    GENERATE_FIELD(PERFCOUNTER_REF, int)
+    GENERATE_FIELD(YEILD_OPTIMIZE, int)
+    GENERATE_FIELD(TX_CACHE_SEL, int)
+END_REGISTER(SQ_CONTEXT_MISC)
+
+START_REGISTER(SQ_CF_RD_BASE)
+    GENERATE_FIELD(RD_BASE, hex)
+END_REGISTER(SQ_CF_RD_BASE)
+
+START_REGISTER(SQ_DEBUG_MISC_0)
+    GENERATE_FIELD(DB_PROB_ON, int)
+    GENERATE_FIELD(DB_PROB_BREAK, int)
+    GENERATE_FIELD(DB_PROB_ADDR, int)
+    GENERATE_FIELD(DB_PROB_COUNT, int)
+END_REGISTER(SQ_DEBUG_MISC_0)
+
+START_REGISTER(SQ_DEBUG_MISC_1)
+    GENERATE_FIELD(DB_ON_PIX, int)
+    GENERATE_FIELD(DB_ON_VTX, int)
+    GENERATE_FIELD(DB_INST_COUNT, int)
+    GENERATE_FIELD(DB_BREAK_ADDR, int)
+END_REGISTER(SQ_DEBUG_MISC_1)
+
+START_REGISTER(MH_ARBITER_CONFIG)
+    GENERATE_FIELD(SAME_PAGE_LIMIT, int)
+    GENERATE_FIELD(SAME_PAGE_GRANULARITY, int)
+    GENERATE_FIELD(L1_ARB_ENABLE, bool)
+    GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int)
+    GENERATE_FIELD(L2_ARB_CONTROL, int)
+    GENERATE_FIELD(PAGE_SIZE, int)
+    GENERATE_FIELD(TC_REORDER_ENABLE, bool)
+    GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT, int)
+    GENERATE_FIELD(CP_CLNT_ENABLE, bool)
+    GENERATE_FIELD(VGT_CLNT_ENABLE, bool)
+    GENERATE_FIELD(TC_CLNT_ENABLE, bool)
+    GENERATE_FIELD(RB_CLNT_ENABLE, bool)
+    GENERATE_FIELD(PA_CLNT_ENABLE, bool)
+END_REGISTER(MH_ARBITER_CONFIG)
+
+START_REGISTER(MH_CLNT_AXI_ID_REUSE)
+    GENERATE_FIELD(CPw_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(RBw_ID, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(MMUr_ID, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(PAw_ID, int)
+END_REGISTER(MH_CLNT_AXI_ID_REUSE)
+
+START_REGISTER(MH_INTERRUPT_MASK)
+    GENERATE_FIELD(AXI_READ_ERROR, bool)
+    GENERATE_FIELD(AXI_WRITE_ERROR, bool)
+    GENERATE_FIELD(MMU_PAGE_FAULT, bool)
+END_REGISTER(MH_INTERRUPT_MASK)
+
+START_REGISTER(MH_INTERRUPT_STATUS)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+END_REGISTER(MH_INTERRUPT_STATUS)
+
+START_REGISTER(MH_INTERRUPT_CLEAR)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+END_REGISTER(MH_INTERRUPT_CLEAR)
+
+START_REGISTER(MH_AXI_ERROR)
+    GENERATE_FIELD(AXI_READ_ID, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ID, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+END_REGISTER(MH_AXI_ERROR)
+
+START_REGISTER(MH_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER0_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER1_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER0_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER0_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER1_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER1_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER0_LOW)
+
+START_REGISTER(MH_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER1_LOW)
+
+START_REGISTER(MH_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER0_HI)
+
+START_REGISTER(MH_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER1_HI)
+
+START_REGISTER(MH_DEBUG_CTRL)
+    GENERATE_FIELD(INDEX, int)
+END_REGISTER(MH_DEBUG_CTRL)
+
+START_REGISTER(MH_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(MH_DEBUG_DATA)
+
+START_REGISTER(MH_AXI_HALT_CONTROL)
+    GENERATE_FIELD(AXI_HALT, bool)
+END_REGISTER(MH_AXI_HALT_CONTROL)
+
+START_REGISTER(MH_MMU_CONFIG)
+    GENERATE_FIELD(MMU_ENABLE, bool)
+    GENERATE_FIELD(SPLIT_MODE_ENABLE, bool)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(PA_W_CLNT_BEHAVIOR, MmuClntBeh)
+END_REGISTER(MH_MMU_CONFIG)
+
+START_REGISTER(MH_MMU_VA_RANGE)
+    GENERATE_FIELD(NUM_64KB_REGIONS, int)
+    GENERATE_FIELD(VA_BASE, int)
+END_REGISTER(MH_MMU_VA_RANGE)
+
+START_REGISTER(MH_MMU_PT_BASE)
+    GENERATE_FIELD(PT_BASE, int)
+END_REGISTER(MH_MMU_PT_BASE)
+
+START_REGISTER(MH_MMU_PAGE_FAULT)
+    GENERATE_FIELD(PAGE_FAULT, int)
+    GENERATE_FIELD(OP_TYPE, int)
+    GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(AXI_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(READ_PROTECTION_ERROR, int)
+    GENERATE_FIELD(WRITE_PROTECTION_ERROR, int)
+    GENERATE_FIELD(REQ_VA, int)
+END_REGISTER(MH_MMU_PAGE_FAULT)
+
+START_REGISTER(MH_MMU_TRAN_ERROR)
+    GENERATE_FIELD(TRAN_ERROR, int)
+END_REGISTER(MH_MMU_TRAN_ERROR)
+
+START_REGISTER(MH_MMU_INVALIDATE)
+    GENERATE_FIELD(INVALIDATE_ALL, int)
+    GENERATE_FIELD(INVALIDATE_TC, int)
+END_REGISTER(MH_MMU_INVALIDATE)
+
+START_REGISTER(MH_MMU_MPU_BASE)
+    GENERATE_FIELD(MPU_BASE, int)
+END_REGISTER(MH_MMU_MPU_BASE)
+
+START_REGISTER(MH_MMU_MPU_END)
+    GENERATE_FIELD(MPU_END, int)
+END_REGISTER(MH_MMU_MPU_END)
+
+START_REGISTER(WAIT_UNTIL)
+    GENERATE_FIELD(WAIT_RE_VSYNC, int)
+    GENERATE_FIELD(WAIT_FE_VSYNC, int)
+    GENERATE_FIELD(WAIT_VSYNC, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID0, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID1, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID2, int)
+    GENERATE_FIELD(WAIT_CMDFIFO, int)
+    GENERATE_FIELD(WAIT_2D_IDLE, int)
+    GENERATE_FIELD(WAIT_3D_IDLE, int)
+    GENERATE_FIELD(WAIT_2D_IDLECLEAN, int)
+    GENERATE_FIELD(WAIT_3D_IDLECLEAN, int)
+    GENERATE_FIELD(CMDFIFO_ENTRIES, int)
+END_REGISTER(WAIT_UNTIL)
+
+START_REGISTER(RBBM_ISYNC_CNTL)
+    GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int)
+    GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int)
+END_REGISTER(RBBM_ISYNC_CNTL)
+
+START_REGISTER(RBBM_STATUS)
+    GENERATE_FIELD(CMDFIFO_AVAIL, int)
+    GENERATE_FIELD(TC_BUSY, int)
+    GENERATE_FIELD(HIRQ_PENDING, int)
+    GENERATE_FIELD(CPRQ_PENDING, int)
+    GENERATE_FIELD(CFRQ_PENDING, int)
+    GENERATE_FIELD(PFRQ_PENDING, int)
+    GENERATE_FIELD(VGT_BUSY_NO_DMA, int)
+    GENERATE_FIELD(RBBM_WU_BUSY, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(MH_BUSY, int)
+    GENERATE_FIELD(MH_COHERENCY_BUSY, int)
+    GENERATE_FIELD(SX_BUSY, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+    GENERATE_FIELD(SC_CNTX_BUSY, int)
+    GENERATE_FIELD(PA_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX17_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX0_BUSY, int)
+    GENERATE_FIELD(RB_CNTX_BUSY, int)
+    GENERATE_FIELD(GUI_ACTIVE, int)
+END_REGISTER(RBBM_STATUS)
+
+START_REGISTER(RBBM_DSPLY)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID0, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID1, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID2, int)
+    GENERATE_FIELD(SEL_DMI_VSYNC_VALID, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH1_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH1_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH2_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH2_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CHANNEL_SELECT, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH3_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH3_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH4_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH4_NUM_BUFS, int)
+END_REGISTER(RBBM_DSPLY)
+
+START_REGISTER(RBBM_RENDER_LATEST)
+    GENERATE_FIELD(DMI_CH1_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH2_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH3_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH4_BUFFER_ID, int)
+END_REGISTER(RBBM_RENDER_LATEST)
+
+START_REGISTER(RBBM_RTL_RELEASE)
+    GENERATE_FIELD(CHANGELIST, int)
+END_REGISTER(RBBM_RTL_RELEASE)
+
+START_REGISTER(RBBM_PATCH_RELEASE)
+    GENERATE_FIELD(PATCH_REVISION, int)
+    GENERATE_FIELD(PATCH_SELECTION, int)
+    GENERATE_FIELD(CUSTOMER_ID, int)
+END_REGISTER(RBBM_PATCH_RELEASE)
+
+START_REGISTER(RBBM_AUXILIARY_CONFIG)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(RBBM_AUXILIARY_CONFIG)
+
+START_REGISTER(RBBM_PERIPHID0)
+    GENERATE_FIELD(PARTNUMBER0, int)
+END_REGISTER(RBBM_PERIPHID0)
+
+START_REGISTER(RBBM_PERIPHID1)
+    GENERATE_FIELD(PARTNUMBER1, int)
+    GENERATE_FIELD(DESIGNER0, int)
+END_REGISTER(RBBM_PERIPHID1)
+
+START_REGISTER(RBBM_PERIPHID2)
+    GENERATE_FIELD(DESIGNER1, int)
+    GENERATE_FIELD(REVISION, int)
+END_REGISTER(RBBM_PERIPHID2)
+
+START_REGISTER(RBBM_PERIPHID3)
+    GENERATE_FIELD(RBBM_HOST_INTERFACE, int)
+    GENERATE_FIELD(GARB_SLAVE_INTERFACE, int)
+    GENERATE_FIELD(MH_INTERFACE, int)
+    GENERATE_FIELD(CONTINUATION, int)
+END_REGISTER(RBBM_PERIPHID3)
+
+START_REGISTER(RBBM_CNTL)
+    GENERATE_FIELD(READ_TIMEOUT, int)
+    GENERATE_FIELD(REGCLK_DEASSERT_TIME, int)
+END_REGISTER(RBBM_CNTL)
+
+START_REGISTER(RBBM_SKEW_CNTL)
+    GENERATE_FIELD(SKEW_TOP_THRESHOLD, int)
+    GENERATE_FIELD(SKEW_COUNT, int)
+END_REGISTER(RBBM_SKEW_CNTL)
+
+START_REGISTER(RBBM_SOFT_RESET)
+    GENERATE_FIELD(SOFT_RESET_CP, int)
+    GENERATE_FIELD(SOFT_RESET_PA, int)
+    GENERATE_FIELD(SOFT_RESET_MH, int)
+    GENERATE_FIELD(SOFT_RESET_BC, int)
+    GENERATE_FIELD(SOFT_RESET_SQ, int)
+    GENERATE_FIELD(SOFT_RESET_SX, int)
+    GENERATE_FIELD(SOFT_RESET_CIB, int)
+    GENERATE_FIELD(SOFT_RESET_SC, int)
+    GENERATE_FIELD(SOFT_RESET_VGT, int)
+END_REGISTER(RBBM_SOFT_RESET)
+
+START_REGISTER(RBBM_PM_OVERRIDE1)
+    GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE1)
+
+START_REGISTER(RBBM_PM_OVERRIDE2)
+    GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE2)
+
+START_REGISTER(GC_SYS_IDLE)
+    GENERATE_FIELD(GC_SYS_IDLE_DELAY, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI_MASK, int)
+    GENERATE_FIELD(GC_SYS_URGENT_RAMP, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI, int)
+    GENERATE_FIELD(GC_SYS_URGENT_RAMP_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int)
+END_REGISTER(GC_SYS_IDLE)
+
+START_REGISTER(NQWAIT_UNTIL)
+    GENERATE_FIELD(WAIT_GUI_IDLE, int)
+END_REGISTER(NQWAIT_UNTIL)
+
+START_REGISTER(RBBM_DEBUG_OUT)
+    GENERATE_FIELD(DEBUG_BUS_OUT, int)
+END_REGISTER(RBBM_DEBUG_OUT)
+
+START_REGISTER(RBBM_DEBUG_CNTL)
+    GENERATE_FIELD(SUB_BLOCK_ADDR, int)
+    GENERATE_FIELD(SUB_BLOCK_SEL, int)
+    GENERATE_FIELD(SW_ENABLE, int)
+    GENERATE_FIELD(GPIO_SUB_BLOCK_ADDR, int)
+    GENERATE_FIELD(GPIO_SUB_BLOCK_SEL, int)
+    GENERATE_FIELD(GPIO_BYTE_LANE_ENB, int)
+END_REGISTER(RBBM_DEBUG_CNTL)
+
+START_REGISTER(RBBM_DEBUG)
+    GENERATE_FIELD(IGNORE_RTR, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_WU, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int)
+    GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int)
+    GENERATE_FIELD(IGNORE_RTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(CP_RBBM_NRTRTR, int)
+    GENERATE_FIELD(VGT_RBBM_NRTRTR, int)
+    GENERATE_FIELD(SQ_RBBM_NRTRTR, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int)
+    GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int)
+END_REGISTER(RBBM_DEBUG)
+
+START_REGISTER(RBBM_READ_ERROR)
+    GENERATE_FIELD(READ_ADDRESS, int)
+    GENERATE_FIELD(READ_REQUESTER, int)
+    GENERATE_FIELD(READ_ERROR, int)
+END_REGISTER(RBBM_READ_ERROR)
+
+START_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+    GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int)
+END_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+
+START_REGISTER(RBBM_INT_CNTL)
+    GENERATE_FIELD(RDERR_INT_MASK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int)
+    GENERATE_FIELD(GUI_IDLE_INT_MASK, int)
+END_REGISTER(RBBM_INT_CNTL)
+
+START_REGISTER(RBBM_INT_STATUS)
+    GENERATE_FIELD(RDERR_INT_STAT, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int)
+    GENERATE_FIELD(GUI_IDLE_INT_STAT, int)
+END_REGISTER(RBBM_INT_STATUS)
+
+START_REGISTER(RBBM_INT_ACK)
+    GENERATE_FIELD(RDERR_INT_ACK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int)
+    GENERATE_FIELD(GUI_IDLE_INT_ACK, int)
+END_REGISTER(RBBM_INT_ACK)
+
+START_REGISTER(MASTER_INT_SIGNAL)
+    GENERATE_FIELD(MH_INT_STAT, int)
+    GENERATE_FIELD(SQ_INT_STAT, int)
+    GENERATE_FIELD(CP_INT_STAT, int)
+    GENERATE_FIELD(RBBM_INT_STAT, int)
+END_REGISTER(MASTER_INT_SIGNAL)
+
+START_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL)
+END_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(RBBM_PERFCOUNTER1_LO)
+    GENERATE_FIELD(PERF_COUNT1_LO, int)
+END_REGISTER(RBBM_PERFCOUNTER1_LO)
+
+START_REGISTER(RBBM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT1_HI, int)
+END_REGISTER(RBBM_PERFCOUNTER1_HI)
+
+START_REGISTER(CP_RB_BASE)
+    GENERATE_FIELD(RB_BASE, int)
+END_REGISTER(CP_RB_BASE)
+
+START_REGISTER(CP_RB_CNTL)
+    GENERATE_FIELD(RB_BUFSZ, int)
+    GENERATE_FIELD(RB_BLKSZ, int)
+    GENERATE_FIELD(BUF_SWAP, int)
+    GENERATE_FIELD(RB_POLL_EN, int)
+    GENERATE_FIELD(RB_NO_UPDATE, int)
+    GENERATE_FIELD(RB_RPTR_WR_ENA, int)
+END_REGISTER(CP_RB_CNTL)
+
+START_REGISTER(CP_RB_RPTR_ADDR)
+    GENERATE_FIELD(RB_RPTR_SWAP, int)
+    GENERATE_FIELD(RB_RPTR_ADDR, int)
+END_REGISTER(CP_RB_RPTR_ADDR)
+
+START_REGISTER(CP_RB_RPTR)
+    GENERATE_FIELD(RB_RPTR, int)
+END_REGISTER(CP_RB_RPTR)
+
+START_REGISTER(CP_RB_RPTR_WR)
+    GENERATE_FIELD(RB_RPTR_WR, int)
+END_REGISTER(CP_RB_RPTR_WR)
+
+START_REGISTER(CP_RB_WPTR)
+    GENERATE_FIELD(RB_WPTR, int)
+END_REGISTER(CP_RB_WPTR)
+
+START_REGISTER(CP_RB_WPTR_DELAY)
+    GENERATE_FIELD(PRE_WRITE_TIMER, int)
+    GENERATE_FIELD(PRE_WRITE_LIMIT, int)
+END_REGISTER(CP_RB_WPTR_DELAY)
+
+START_REGISTER(CP_RB_WPTR_BASE)
+    GENERATE_FIELD(RB_WPTR_SWAP, int)
+    GENERATE_FIELD(RB_WPTR_BASE, int)
+END_REGISTER(CP_RB_WPTR_BASE)
+
+START_REGISTER(CP_IB1_BASE)
+    GENERATE_FIELD(IB1_BASE, int)
+END_REGISTER(CP_IB1_BASE)
+
+START_REGISTER(CP_IB1_BUFSZ)
+    GENERATE_FIELD(IB1_BUFSZ, int)
+END_REGISTER(CP_IB1_BUFSZ)
+
+START_REGISTER(CP_IB2_BASE)
+    GENERATE_FIELD(IB2_BASE, int)
+END_REGISTER(CP_IB2_BASE)
+
+START_REGISTER(CP_IB2_BUFSZ)
+    GENERATE_FIELD(IB2_BUFSZ, int)
+END_REGISTER(CP_IB2_BUFSZ)
+
+START_REGISTER(CP_ST_BASE)
+    GENERATE_FIELD(ST_BASE, int)
+END_REGISTER(CP_ST_BASE)
+
+START_REGISTER(CP_ST_BUFSZ)
+    GENERATE_FIELD(ST_BUFSZ, int)
+END_REGISTER(CP_ST_BUFSZ)
+
+START_REGISTER(CP_QUEUE_THRESHOLDS)
+    GENERATE_FIELD(CSQ_IB1_START, int)
+    GENERATE_FIELD(CSQ_IB2_START, int)
+    GENERATE_FIELD(CSQ_ST_START, int)
+END_REGISTER(CP_QUEUE_THRESHOLDS)
+
+START_REGISTER(CP_MEQ_THRESHOLDS)
+    GENERATE_FIELD(MEQ_END, int)
+    GENERATE_FIELD(ROQ_END, int)
+END_REGISTER(CP_MEQ_THRESHOLDS)
+
+START_REGISTER(CP_CSQ_AVAIL)
+    GENERATE_FIELD(CSQ_CNT_RING, int)
+    GENERATE_FIELD(CSQ_CNT_IB1, int)
+    GENERATE_FIELD(CSQ_CNT_IB2, int)
+END_REGISTER(CP_CSQ_AVAIL)
+
+START_REGISTER(CP_STQ_AVAIL)
+    GENERATE_FIELD(STQ_CNT_ST, int)
+END_REGISTER(CP_STQ_AVAIL)
+
+START_REGISTER(CP_MEQ_AVAIL)
+    GENERATE_FIELD(MEQ_CNT, int)
+END_REGISTER(CP_MEQ_AVAIL)
+
+START_REGISTER(CP_CSQ_RB_STAT)
+    GENERATE_FIELD(CSQ_RPTR_PRIMARY, int)
+    GENERATE_FIELD(CSQ_WPTR_PRIMARY, int)
+END_REGISTER(CP_CSQ_RB_STAT)
+
+START_REGISTER(CP_CSQ_IB1_STAT)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int)
+END_REGISTER(CP_CSQ_IB1_STAT)
+
+START_REGISTER(CP_CSQ_IB2_STAT)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int)
+END_REGISTER(CP_CSQ_IB2_STAT)
+
+START_REGISTER(CP_NON_PREFETCH_CNTRS)
+    GENERATE_FIELD(IB1_COUNTER, int)
+    GENERATE_FIELD(IB2_COUNTER, int)
+END_REGISTER(CP_NON_PREFETCH_CNTRS)
+
+START_REGISTER(CP_STQ_ST_STAT)
+    GENERATE_FIELD(STQ_RPTR_ST, int)
+    GENERATE_FIELD(STQ_WPTR_ST, int)
+END_REGISTER(CP_STQ_ST_STAT)
+
+START_REGISTER(CP_MEQ_STAT)
+    GENERATE_FIELD(MEQ_RPTR, int)
+    GENERATE_FIELD(MEQ_WPTR, int)
+END_REGISTER(CP_MEQ_STAT)
+
+START_REGISTER(CP_MIU_TAG_STAT)
+    GENERATE_FIELD(TAG_0_STAT, int)
+    GENERATE_FIELD(TAG_1_STAT, int)
+    GENERATE_FIELD(TAG_2_STAT, int)
+    GENERATE_FIELD(TAG_3_STAT, int)
+    GENERATE_FIELD(TAG_4_STAT, int)
+    GENERATE_FIELD(TAG_5_STAT, int)
+    GENERATE_FIELD(TAG_6_STAT, int)
+    GENERATE_FIELD(TAG_7_STAT, int)
+    GENERATE_FIELD(TAG_8_STAT, int)
+    GENERATE_FIELD(TAG_9_STAT, int)
+    GENERATE_FIELD(TAG_10_STAT, int)
+    GENERATE_FIELD(TAG_11_STAT, int)
+    GENERATE_FIELD(TAG_12_STAT, int)
+    GENERATE_FIELD(TAG_13_STAT, int)
+    GENERATE_FIELD(TAG_14_STAT, int)
+    GENERATE_FIELD(TAG_15_STAT, int)
+    GENERATE_FIELD(TAG_16_STAT, int)
+    GENERATE_FIELD(TAG_17_STAT, int)
+    GENERATE_FIELD(INVALID_RETURN_TAG, int)
+END_REGISTER(CP_MIU_TAG_STAT)
+
+START_REGISTER(CP_CMD_INDEX)
+    GENERATE_FIELD(CMD_INDEX, int)
+    GENERATE_FIELD(CMD_QUEUE_SEL, int)
+END_REGISTER(CP_CMD_INDEX)
+
+START_REGISTER(CP_CMD_DATA)
+    GENERATE_FIELD(CMD_DATA, int)
+END_REGISTER(CP_CMD_DATA)
+
+START_REGISTER(CP_ME_CNTL)
+    GENERATE_FIELD(ME_STATMUX, int)
+    GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(ME_HALT, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(PROG_CNT_SIZE, int)
+END_REGISTER(CP_ME_CNTL)
+
+START_REGISTER(CP_ME_STATUS)
+    GENERATE_FIELD(ME_DEBUG_DATA, int)
+END_REGISTER(CP_ME_STATUS)
+
+START_REGISTER(CP_ME_RAM_WADDR)
+    GENERATE_FIELD(ME_RAM_WADDR, int)
+END_REGISTER(CP_ME_RAM_WADDR)
+
+START_REGISTER(CP_ME_RAM_RADDR)
+    GENERATE_FIELD(ME_RAM_RADDR, int)
+END_REGISTER(CP_ME_RAM_RADDR)
+
+START_REGISTER(CP_ME_RAM_DATA)
+    GENERATE_FIELD(ME_RAM_DATA, int)
+END_REGISTER(CP_ME_RAM_DATA)
+
+START_REGISTER(CP_ME_RDADDR)
+    GENERATE_FIELD(ME_RDADDR, int)
+END_REGISTER(CP_ME_RDADDR)
+
+START_REGISTER(CP_DEBUG)
+    GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int)
+    GENERATE_FIELD(PREDICATE_DISABLE, int)
+    GENERATE_FIELD(PROG_END_PTR_ENABLE, int)
+    GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int)
+    GENERATE_FIELD(PREFETCH_PASS_NOPS, int)
+    GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int)
+    GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int)
+    GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int)
+    GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int)
+END_REGISTER(CP_DEBUG)
+
+START_REGISTER(SCRATCH_REG0)
+    GENERATE_FIELD(SCRATCH_REG0, int)
+END_REGISTER(SCRATCH_REG0)
+
+START_REGISTER(SCRATCH_REG1)
+    GENERATE_FIELD(SCRATCH_REG1, int)
+END_REGISTER(SCRATCH_REG1)
+
+START_REGISTER(SCRATCH_REG2)
+    GENERATE_FIELD(SCRATCH_REG2, int)
+END_REGISTER(SCRATCH_REG2)
+
+START_REGISTER(SCRATCH_REG3)
+    GENERATE_FIELD(SCRATCH_REG3, int)
+END_REGISTER(SCRATCH_REG3)
+
+START_REGISTER(SCRATCH_REG4)
+    GENERATE_FIELD(SCRATCH_REG4, int)
+END_REGISTER(SCRATCH_REG4)
+
+START_REGISTER(SCRATCH_REG5)
+    GENERATE_FIELD(SCRATCH_REG5, int)
+END_REGISTER(SCRATCH_REG5)
+
+START_REGISTER(SCRATCH_REG6)
+    GENERATE_FIELD(SCRATCH_REG6, int)
+END_REGISTER(SCRATCH_REG6)
+
+START_REGISTER(SCRATCH_REG7)
+    GENERATE_FIELD(SCRATCH_REG7, int)
+END_REGISTER(SCRATCH_REG7)
+
+START_REGISTER(SCRATCH_UMSK)
+    GENERATE_FIELD(SCRATCH_UMSK, int)
+    GENERATE_FIELD(SCRATCH_SWAP, int)
+END_REGISTER(SCRATCH_UMSK)
+
+START_REGISTER(SCRATCH_ADDR)
+    GENERATE_FIELD(SCRATCH_ADDR, hex)
+END_REGISTER(SCRATCH_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_SRC)
+    GENERATE_FIELD(VS_DONE_SWM, int)
+    GENERATE_FIELD(VS_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_EVENT_SRC)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR)
+    GENERATE_FIELD(VS_DONE_SWAP, int)
+    GENERATE_FIELD(VS_DONE_ADDR, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA)
+    GENERATE_FIELD(VS_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(VS_DONE_SWAP_SWM, int)
+    GENERATE_FIELD(VS_DONE_ADDR_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+    GENERATE_FIELD(VS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_SRC)
+    GENERATE_FIELD(PS_DONE_SWM, int)
+    GENERATE_FIELD(PS_DONE_CNTR, int)
+END_REGISTER(CP_ME_PS_EVENT_SRC)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR)
+    GENERATE_FIELD(PS_DONE_SWAP, int)
+    GENERATE_FIELD(PS_DONE_ADDR, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA)
+    GENERATE_FIELD(PS_DONE_DATA, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(PS_DONE_SWAP_SWM, int)
+    GENERATE_FIELD(PS_DONE_ADDR_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+    GENERATE_FIELD(PS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_CF_EVENT_SRC)
+    GENERATE_FIELD(CF_DONE_SRC, int)
+END_REGISTER(CP_ME_CF_EVENT_SRC)
+
+START_REGISTER(CP_ME_CF_EVENT_ADDR)
+    GENERATE_FIELD(CF_DONE_SWAP, int)
+    GENERATE_FIELD(CF_DONE_ADDR, int)
+END_REGISTER(CP_ME_CF_EVENT_ADDR)
+
+START_REGISTER(CP_ME_CF_EVENT_DATA)
+    GENERATE_FIELD(CF_DONE_DATA, int)
+END_REGISTER(CP_ME_CF_EVENT_DATA)
+
+START_REGISTER(CP_ME_NRT_ADDR)
+    GENERATE_FIELD(NRT_WRITE_SWAP, int)
+    GENERATE_FIELD(NRT_WRITE_ADDR, int)
+END_REGISTER(CP_ME_NRT_ADDR)
+
+START_REGISTER(CP_ME_NRT_DATA)
+    GENERATE_FIELD(NRT_WRITE_DATA, int)
+END_REGISTER(CP_ME_NRT_DATA)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+    GENERATE_FIELD(VS_FETCH_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+    GENERATE_FIELD(VS_FETCH_DONE_SWAP, int)
+    GENERATE_FIELD(VS_FETCH_DONE_ADDR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+    GENERATE_FIELD(VS_FETCH_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+
+START_REGISTER(CP_INT_CNTL)
+    GENERATE_FIELD(SW_INT_MASK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int)
+    GENERATE_FIELD(OPCODE_ERROR_MASK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int)
+    GENERATE_FIELD(IB_ERROR_MASK, int)
+    GENERATE_FIELD(IB2_INT_MASK, int)
+    GENERATE_FIELD(IB1_INT_MASK, int)
+    GENERATE_FIELD(RB_INT_MASK, int)
+END_REGISTER(CP_INT_CNTL)
+
+START_REGISTER(CP_INT_STATUS)
+    GENERATE_FIELD(SW_INT_STAT, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int)
+    GENERATE_FIELD(OPCODE_ERROR_STAT, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int)
+    GENERATE_FIELD(IB_ERROR_STAT, int)
+    GENERATE_FIELD(IB2_INT_STAT, int)
+    GENERATE_FIELD(IB1_INT_STAT, int)
+    GENERATE_FIELD(RB_INT_STAT, int)
+END_REGISTER(CP_INT_STATUS)
+
+START_REGISTER(CP_INT_ACK)
+    GENERATE_FIELD(SW_INT_ACK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int)
+    GENERATE_FIELD(OPCODE_ERROR_ACK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int)
+    GENERATE_FIELD(IB_ERROR_ACK, int)
+    GENERATE_FIELD(IB2_INT_ACK, int)
+    GENERATE_FIELD(IB1_INT_ACK, int)
+    GENERATE_FIELD(RB_INT_ACK, int)
+END_REGISTER(CP_INT_ACK)
+
+START_REGISTER(CP_PFP_UCODE_ADDR)
+    GENERATE_FIELD(UCODE_ADDR, hex)
+END_REGISTER(CP_PFP_UCODE_ADDR)
+
+START_REGISTER(CP_PFP_UCODE_DATA)
+    GENERATE_FIELD(UCODE_DATA, hex)
+END_REGISTER(CP_PFP_UCODE_DATA)
+
+START_REGISTER(CP_PERFMON_CNTL)
+    GENERATE_FIELD(PERFMON_STATE, int)
+    GENERATE_FIELD(PERFMON_ENABLE_MODE, int)
+END_REGISTER(CP_PERFMON_CNTL)
+
+START_REGISTER(CP_PERFCOUNTER_SELECT)
+    GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL)
+END_REGISTER(CP_PERFCOUNTER_SELECT)
+
+START_REGISTER(CP_PERFCOUNTER_LO)
+    GENERATE_FIELD(PERFCOUNT_LO, int)
+END_REGISTER(CP_PERFCOUNTER_LO)
+
+START_REGISTER(CP_PERFCOUNTER_HI)
+    GENERATE_FIELD(PERFCOUNT_HI, int)
+END_REGISTER(CP_PERFCOUNTER_HI)
+
+START_REGISTER(CP_BIN_MASK_LO)
+    GENERATE_FIELD(BIN_MASK_LO, int)
+END_REGISTER(CP_BIN_MASK_LO)
+
+START_REGISTER(CP_BIN_MASK_HI)
+    GENERATE_FIELD(BIN_MASK_HI, int)
+END_REGISTER(CP_BIN_MASK_HI)
+
+START_REGISTER(CP_BIN_SELECT_LO)
+    GENERATE_FIELD(BIN_SELECT_LO, int)
+END_REGISTER(CP_BIN_SELECT_LO)
+
+START_REGISTER(CP_BIN_SELECT_HI)
+    GENERATE_FIELD(BIN_SELECT_HI, int)
+END_REGISTER(CP_BIN_SELECT_HI)
+
+START_REGISTER(CP_NV_FLAGS_0)
+    GENERATE_FIELD(DISCARD_0, int)
+    GENERATE_FIELD(END_RCVD_0, int)
+    GENERATE_FIELD(DISCARD_1, int)
+    GENERATE_FIELD(END_RCVD_1, int)
+    GENERATE_FIELD(DISCARD_2, int)
+    GENERATE_FIELD(END_RCVD_2, int)
+    GENERATE_FIELD(DISCARD_3, int)
+    GENERATE_FIELD(END_RCVD_3, int)
+    GENERATE_FIELD(DISCARD_4, int)
+    GENERATE_FIELD(END_RCVD_4, int)
+    GENERATE_FIELD(DISCARD_5, int)
+    GENERATE_FIELD(END_RCVD_5, int)
+    GENERATE_FIELD(DISCARD_6, int)
+    GENERATE_FIELD(END_RCVD_6, int)
+    GENERATE_FIELD(DISCARD_7, int)
+    GENERATE_FIELD(END_RCVD_7, int)
+    GENERATE_FIELD(DISCARD_8, int)
+    GENERATE_FIELD(END_RCVD_8, int)
+    GENERATE_FIELD(DISCARD_9, int)
+    GENERATE_FIELD(END_RCVD_9, int)
+    GENERATE_FIELD(DISCARD_10, int)
+    GENERATE_FIELD(END_RCVD_10, int)
+    GENERATE_FIELD(DISCARD_11, int)
+    GENERATE_FIELD(END_RCVD_11, int)
+    GENERATE_FIELD(DISCARD_12, int)
+    GENERATE_FIELD(END_RCVD_12, int)
+    GENERATE_FIELD(DISCARD_13, int)
+    GENERATE_FIELD(END_RCVD_13, int)
+    GENERATE_FIELD(DISCARD_14, int)
+    GENERATE_FIELD(END_RCVD_14, int)
+    GENERATE_FIELD(DISCARD_15, int)
+    GENERATE_FIELD(END_RCVD_15, int)
+END_REGISTER(CP_NV_FLAGS_0)
+
+START_REGISTER(CP_NV_FLAGS_1)
+    GENERATE_FIELD(DISCARD_16, int)
+    GENERATE_FIELD(END_RCVD_16, int)
+    GENERATE_FIELD(DISCARD_17, int)
+    GENERATE_FIELD(END_RCVD_17, int)
+    GENERATE_FIELD(DISCARD_18, int)
+    GENERATE_FIELD(END_RCVD_18, int)
+    GENERATE_FIELD(DISCARD_19, int)
+    GENERATE_FIELD(END_RCVD_19, int)
+    GENERATE_FIELD(DISCARD_20, int)
+    GENERATE_FIELD(END_RCVD_20, int)
+    GENERATE_FIELD(DISCARD_21, int)
+    GENERATE_FIELD(END_RCVD_21, int)
+    GENERATE_FIELD(DISCARD_22, int)
+    GENERATE_FIELD(END_RCVD_22, int)
+    GENERATE_FIELD(DISCARD_23, int)
+    GENERATE_FIELD(END_RCVD_23, int)
+    GENERATE_FIELD(DISCARD_24, int)
+    GENERATE_FIELD(END_RCVD_24, int)
+    GENERATE_FIELD(DISCARD_25, int)
+    GENERATE_FIELD(END_RCVD_25, int)
+    GENERATE_FIELD(DISCARD_26, int)
+    GENERATE_FIELD(END_RCVD_26, int)
+    GENERATE_FIELD(DISCARD_27, int)
+    GENERATE_FIELD(END_RCVD_27, int)
+    GENERATE_FIELD(DISCARD_28, int)
+    GENERATE_FIELD(END_RCVD_28, int)
+    GENERATE_FIELD(DISCARD_29, int)
+    GENERATE_FIELD(END_RCVD_29, int)
+    GENERATE_FIELD(DISCARD_30, int)
+    GENERATE_FIELD(END_RCVD_30, int)
+    GENERATE_FIELD(DISCARD_31, int)
+    GENERATE_FIELD(END_RCVD_31, int)
+END_REGISTER(CP_NV_FLAGS_1)
+
+START_REGISTER(CP_NV_FLAGS_2)
+    GENERATE_FIELD(DISCARD_32, int)
+    GENERATE_FIELD(END_RCVD_32, int)
+    GENERATE_FIELD(DISCARD_33, int)
+    GENERATE_FIELD(END_RCVD_33, int)
+    GENERATE_FIELD(DISCARD_34, int)
+    GENERATE_FIELD(END_RCVD_34, int)
+    GENERATE_FIELD(DISCARD_35, int)
+    GENERATE_FIELD(END_RCVD_35, int)
+    GENERATE_FIELD(DISCARD_36, int)
+    GENERATE_FIELD(END_RCVD_36, int)
+    GENERATE_FIELD(DISCARD_37, int)
+    GENERATE_FIELD(END_RCVD_37, int)
+    GENERATE_FIELD(DISCARD_38, int)
+    GENERATE_FIELD(END_RCVD_38, int)
+    GENERATE_FIELD(DISCARD_39, int)
+    GENERATE_FIELD(END_RCVD_39, int)
+    GENERATE_FIELD(DISCARD_40, int)
+    GENERATE_FIELD(END_RCVD_40, int)
+    GENERATE_FIELD(DISCARD_41, int)
+    GENERATE_FIELD(END_RCVD_41, int)
+    GENERATE_FIELD(DISCARD_42, int)
+    GENERATE_FIELD(END_RCVD_42, int)
+    GENERATE_FIELD(DISCARD_43, int)
+    GENERATE_FIELD(END_RCVD_43, int)
+    GENERATE_FIELD(DISCARD_44, int)
+    GENERATE_FIELD(END_RCVD_44, int)
+    GENERATE_FIELD(DISCARD_45, int)
+    GENERATE_FIELD(END_RCVD_45, int)
+    GENERATE_FIELD(DISCARD_46, int)
+    GENERATE_FIELD(END_RCVD_46, int)
+    GENERATE_FIELD(DISCARD_47, int)
+    GENERATE_FIELD(END_RCVD_47, int)
+END_REGISTER(CP_NV_FLAGS_2)
+
+START_REGISTER(CP_NV_FLAGS_3)
+    GENERATE_FIELD(DISCARD_48, int)
+    GENERATE_FIELD(END_RCVD_48, int)
+    GENERATE_FIELD(DISCARD_49, int)
+    GENERATE_FIELD(END_RCVD_49, int)
+    GENERATE_FIELD(DISCARD_50, int)
+    GENERATE_FIELD(END_RCVD_50, int)
+    GENERATE_FIELD(DISCARD_51, int)
+    GENERATE_FIELD(END_RCVD_51, int)
+    GENERATE_FIELD(DISCARD_52, int)
+    GENERATE_FIELD(END_RCVD_52, int)
+    GENERATE_FIELD(DISCARD_53, int)
+    GENERATE_FIELD(END_RCVD_53, int)
+    GENERATE_FIELD(DISCARD_54, int)
+    GENERATE_FIELD(END_RCVD_54, int)
+    GENERATE_FIELD(DISCARD_55, int)
+    GENERATE_FIELD(END_RCVD_55, int)
+    GENERATE_FIELD(DISCARD_56, int)
+    GENERATE_FIELD(END_RCVD_56, int)
+    GENERATE_FIELD(DISCARD_57, int)
+    GENERATE_FIELD(END_RCVD_57, int)
+    GENERATE_FIELD(DISCARD_58, int)
+    GENERATE_FIELD(END_RCVD_58, int)
+    GENERATE_FIELD(DISCARD_59, int)
+    GENERATE_FIELD(END_RCVD_59, int)
+    GENERATE_FIELD(DISCARD_60, int)
+    GENERATE_FIELD(END_RCVD_60, int)
+    GENERATE_FIELD(DISCARD_61, int)
+    GENERATE_FIELD(END_RCVD_61, int)
+    GENERATE_FIELD(DISCARD_62, int)
+    GENERATE_FIELD(END_RCVD_62, int)
+    GENERATE_FIELD(DISCARD_63, int)
+    GENERATE_FIELD(END_RCVD_63, int)
+END_REGISTER(CP_NV_FLAGS_3)
+
+START_REGISTER(CP_STATE_DEBUG_INDEX)
+    GENERATE_FIELD(STATE_DEBUG_INDEX, int)
+END_REGISTER(CP_STATE_DEBUG_INDEX)
+
+START_REGISTER(CP_STATE_DEBUG_DATA)
+    GENERATE_FIELD(STATE_DEBUG_DATA, int)
+END_REGISTER(CP_STATE_DEBUG_DATA)
+
+START_REGISTER(CP_PROG_COUNTER)
+    GENERATE_FIELD(COUNTER, int)
+END_REGISTER(CP_PROG_COUNTER)
+
+START_REGISTER(CP_STAT)
+    GENERATE_FIELD(MIU_WR_BUSY, int)
+    GENERATE_FIELD(MIU_RD_REQ_BUSY, int)
+    GENERATE_FIELD(MIU_RD_RETURN_BUSY, int)
+    GENERATE_FIELD(RBIU_BUSY, int)
+    GENERATE_FIELD(RCIU_BUSY, int)
+    GENERATE_FIELD(CSF_RING_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(CSF_ST_BUSY, int)
+    GENERATE_FIELD(CSF_BUSY, int)
+    GENERATE_FIELD(RING_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int)
+    GENERATE_FIELD(ST_QUEUE_BUSY, int)
+    GENERATE_FIELD(PFP_BUSY, int)
+    GENERATE_FIELD(MEQ_RING_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(MIU_WC_STALL, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(_3D_BUSY, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(ME_WC_BUSY, int)
+    GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int)
+    GENERATE_FIELD(CP_BUSY, int)
+END_REGISTER(CP_STAT)
+
+START_REGISTER(BIOS_0_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_0_SCRATCH)
+
+START_REGISTER(BIOS_1_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_1_SCRATCH)
+
+START_REGISTER(BIOS_2_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_2_SCRATCH)
+
+START_REGISTER(BIOS_3_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_3_SCRATCH)
+
+START_REGISTER(BIOS_4_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_4_SCRATCH)
+
+START_REGISTER(BIOS_5_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_5_SCRATCH)
+
+START_REGISTER(BIOS_6_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_6_SCRATCH)
+
+START_REGISTER(BIOS_7_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_7_SCRATCH)
+
+START_REGISTER(BIOS_8_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_8_SCRATCH)
+
+START_REGISTER(BIOS_9_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_9_SCRATCH)
+
+START_REGISTER(BIOS_10_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_10_SCRATCH)
+
+START_REGISTER(BIOS_11_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_11_SCRATCH)
+
+START_REGISTER(BIOS_12_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_12_SCRATCH)
+
+START_REGISTER(BIOS_13_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_13_SCRATCH)
+
+START_REGISTER(BIOS_14_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_14_SCRATCH)
+
+START_REGISTER(BIOS_15_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_15_SCRATCH)
+
+START_REGISTER(COHER_SIZE_PM4)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_PM4)
+
+START_REGISTER(COHER_BASE_PM4)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(COHER_BASE_PM4)
+
+START_REGISTER(COHER_STATUS_PM4)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(RB_COLOR_INFO_ENA, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(STATUS, int)
+END_REGISTER(COHER_STATUS_PM4)
+
+START_REGISTER(COHER_SIZE_HOST)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_HOST)
+
+START_REGISTER(COHER_BASE_HOST)
+    GENERATE_FIELD(BASE, hex)
+END_REGISTER(COHER_BASE_HOST)
+
+START_REGISTER(COHER_STATUS_HOST)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(RB_COLOR_INFO_ENA, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(STATUS, int)
+END_REGISTER(COHER_STATUS_HOST)
+
+START_REGISTER(COHER_DEST_BASE_0)
+    GENERATE_FIELD(DEST_BASE_0, hex)
+END_REGISTER(COHER_DEST_BASE_0)
+
+START_REGISTER(COHER_DEST_BASE_1)
+    GENERATE_FIELD(DEST_BASE_1, hex)
+END_REGISTER(COHER_DEST_BASE_1)
+
+START_REGISTER(COHER_DEST_BASE_2)
+    GENERATE_FIELD(DEST_BASE_2, hex)
+END_REGISTER(COHER_DEST_BASE_2)
+
+START_REGISTER(COHER_DEST_BASE_3)
+    GENERATE_FIELD(DEST_BASE_3, hex)
+END_REGISTER(COHER_DEST_BASE_3)
+
+START_REGISTER(COHER_DEST_BASE_4)
+    GENERATE_FIELD(DEST_BASE_4, hex)
+END_REGISTER(COHER_DEST_BASE_4)
+
+START_REGISTER(COHER_DEST_BASE_5)
+    GENERATE_FIELD(DEST_BASE_5, hex)
+END_REGISTER(COHER_DEST_BASE_5)
+
+START_REGISTER(COHER_DEST_BASE_6)
+    GENERATE_FIELD(DEST_BASE_6, hex)
+END_REGISTER(COHER_DEST_BASE_6)
+
+START_REGISTER(COHER_DEST_BASE_7)
+    GENERATE_FIELD(DEST_BASE_7, hex)
+END_REGISTER(COHER_DEST_BASE_7)
+
+START_REGISTER(RB_SURFACE_INFO)
+    GENERATE_FIELD(SURFACE_PITCH, uint)
+    GENERATE_FIELD(MSAA_SAMPLES, MSAASamples)
+END_REGISTER(RB_SURFACE_INFO)
+
+START_REGISTER(RB_COLOR_INFO)
+    GENERATE_FIELD(COLOR_FORMAT, ColorformatX)
+    GENERATE_FIELD(COLOR_ROUND_MODE, uint)
+    GENERATE_FIELD(COLOR_LINEAR, bool)
+    GENERATE_FIELD(COLOR_ENDIAN, uint)
+    GENERATE_FIELD(COLOR_SWAP, uint)
+    GENERATE_FIELD(COLOR_BASE, uint)
+END_REGISTER(RB_COLOR_INFO)
+
+START_REGISTER(RB_DEPTH_INFO)
+    GENERATE_FIELD(DEPTH_FORMAT, DepthformatX)
+    GENERATE_FIELD(DEPTH_BASE, uint)
+END_REGISTER(RB_DEPTH_INFO)
+
+START_REGISTER(RB_STENCILREFMASK)
+    GENERATE_FIELD(STENCILREF, hex)
+    GENERATE_FIELD(STENCILMASK, hex)
+    GENERATE_FIELD(STENCILWRITEMASK, hex)
+    GENERATE_FIELD(RESERVED0, bool)
+    GENERATE_FIELD(RESERVED1, bool)
+END_REGISTER(RB_STENCILREFMASK)
+
+START_REGISTER(RB_ALPHA_REF)
+    GENERATE_FIELD(ALPHA_REF, float)
+END_REGISTER(RB_ALPHA_REF)
+
+START_REGISTER(RB_COLOR_MASK)
+    GENERATE_FIELD(WRITE_RED, bool)
+    GENERATE_FIELD(WRITE_GREEN, bool)
+    GENERATE_FIELD(WRITE_BLUE, bool)
+    GENERATE_FIELD(WRITE_ALPHA, bool)
+    GENERATE_FIELD(RESERVED2, bool)
+    GENERATE_FIELD(RESERVED3, bool)
+END_REGISTER(RB_COLOR_MASK)
+
+START_REGISTER(RB_BLEND_RED)
+    GENERATE_FIELD(BLEND_RED, uint)
+END_REGISTER(RB_BLEND_RED)
+
+START_REGISTER(RB_BLEND_GREEN)
+    GENERATE_FIELD(BLEND_GREEN, uint)
+END_REGISTER(RB_BLEND_GREEN)
+
+START_REGISTER(RB_BLEND_BLUE)
+    GENERATE_FIELD(BLEND_BLUE, uint)
+END_REGISTER(RB_BLEND_BLUE)
+
+START_REGISTER(RB_BLEND_ALPHA)
+    GENERATE_FIELD(BLEND_ALPHA, uint)
+END_REGISTER(RB_BLEND_ALPHA)
+
+START_REGISTER(RB_FOG_COLOR)
+    GENERATE_FIELD(FOG_RED, uint)
+    GENERATE_FIELD(FOG_GREEN, uint)
+    GENERATE_FIELD(FOG_BLUE, uint)
+END_REGISTER(RB_FOG_COLOR)
+
+START_REGISTER(RB_STENCILREFMASK_BF)
+    GENERATE_FIELD(STENCILREF_BF, hex)
+    GENERATE_FIELD(STENCILMASK_BF, hex)
+    GENERATE_FIELD(STENCILWRITEMASK_BF, hex)
+    GENERATE_FIELD(RESERVED4, bool)
+    GENERATE_FIELD(RESERVED5, bool)
+END_REGISTER(RB_STENCILREFMASK_BF)
+
+START_REGISTER(RB_DEPTHCONTROL)
+    GENERATE_FIELD(STENCIL_ENABLE, bool)
+    GENERATE_FIELD(Z_ENABLE, bool)
+    GENERATE_FIELD(Z_WRITE_ENABLE, bool)
+    GENERATE_FIELD(EARLY_Z_ENABLE, bool)
+    GENERATE_FIELD(ZFUNC, CompareFrag)
+    GENERATE_FIELD(BACKFACE_ENABLE, bool)
+    GENERATE_FIELD(STENCILFUNC, CompareRef)
+    GENERATE_FIELD(STENCILFAIL, StencilOp)
+    GENERATE_FIELD(STENCILZPASS, StencilOp)
+    GENERATE_FIELD(STENCILZFAIL, StencilOp)
+    GENERATE_FIELD(STENCILFUNC_BF, CompareRef)
+    GENERATE_FIELD(STENCILFAIL_BF, StencilOp)
+    GENERATE_FIELD(STENCILZPASS_BF, StencilOp)
+    GENERATE_FIELD(STENCILZFAIL_BF, StencilOp)
+END_REGISTER(RB_DEPTHCONTROL)
+
+START_REGISTER(RB_BLENDCONTROL)
+    GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(BLEND_FORCE_ENABLE, bool)
+    GENERATE_FIELD(BLEND_FORCE, bool)
+END_REGISTER(RB_BLENDCONTROL)
+
+START_REGISTER(RB_COLORCONTROL)
+    GENERATE_FIELD(ALPHA_FUNC, CompareRef)
+    GENERATE_FIELD(ALPHA_TEST_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool)
+    GENERATE_FIELD(BLEND_DISABLE, bool)
+    GENERATE_FIELD(FOG_ENABLE, bool)
+    GENERATE_FIELD(VS_EXPORTS_FOG, bool)
+    GENERATE_FIELD(ROP_CODE, uint)
+    GENERATE_FIELD(DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(PIXEL_FOG, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex)
+END_REGISTER(RB_COLORCONTROL)
+
+START_REGISTER(RB_MODECONTROL)
+    GENERATE_FIELD(EDRAM_MODE, EdramMode)
+END_REGISTER(RB_MODECONTROL)
+
+START_REGISTER(RB_COLOR_DEST_MASK)
+    GENERATE_FIELD(COLOR_DEST_MASK, uint)
+END_REGISTER(RB_COLOR_DEST_MASK)
+
+START_REGISTER(RB_COPY_CONTROL)
+    GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect)
+    GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool)
+    GENERATE_FIELD(CLEAR_MASK, uint)
+END_REGISTER(RB_COPY_CONTROL)
+
+START_REGISTER(RB_COPY_DEST_BASE)
+    GENERATE_FIELD(COPY_DEST_BASE, uint)
+END_REGISTER(RB_COPY_DEST_BASE)
+
+START_REGISTER(RB_COPY_DEST_PITCH)
+    GENERATE_FIELD(COPY_DEST_PITCH, uint)
+END_REGISTER(RB_COPY_DEST_PITCH)
+
+START_REGISTER(RB_COPY_DEST_INFO)
+    GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian)
+    GENERATE_FIELD(COPY_DEST_LINEAR, uint)
+    GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX)
+    GENERATE_FIELD(COPY_DEST_SWAP, uint)
+    GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(COPY_MASK_WRITE_RED, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex)
+END_REGISTER(RB_COPY_DEST_INFO)
+
+START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+    GENERATE_FIELD(OFFSET_X, uint)
+    GENERATE_FIELD(OFFSET_Y, uint)
+END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+
+START_REGISTER(RB_DEPTH_CLEAR)
+    GENERATE_FIELD(DEPTH_CLEAR, uint)
+END_REGISTER(RB_DEPTH_CLEAR)
+
+START_REGISTER(RB_SAMPLE_COUNT_CTL)
+    GENERATE_FIELD(RESET_SAMPLE_COUNT, bool)
+    GENERATE_FIELD(COPY_SAMPLE_COUNT, bool)
+END_REGISTER(RB_SAMPLE_COUNT_CTL)
+
+START_REGISTER(RB_SAMPLE_COUNT_ADDR)
+    GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint)
+END_REGISTER(RB_SAMPLE_COUNT_ADDR)
+
+START_REGISTER(RB_BC_CONTROL)
+    GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint)
+    GENERATE_FIELD(DISABLE_EDRAM_CAM, bool)
+    GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool)
+    GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool)
+    GENERATE_FIELD(AZ_THROTTLE_COUNT, uint)
+    GENERATE_FIELD(ENABLE_CRC_UPDATE, bool)
+    GENERATE_FIELD(CRC_MODE, bool)
+    GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool)
+    GENERATE_FIELD(DISABLE_ACCUM, bool)
+    GENERATE_FIELD(ACCUM_ALLOC_MASK, uint)
+    GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool)
+    GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int)
+    GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(CRC_SYSTEM, bool)
+    GENERATE_FIELD(RESERVED6, bool)
+END_REGISTER(RB_BC_CONTROL)
+
+START_REGISTER(RB_EDRAM_INFO)
+    GENERATE_FIELD(EDRAM_SIZE, EdramSizeX)
+    GENERATE_FIELD(EDRAM_MAPPING_MODE, uint)
+    GENERATE_FIELD(EDRAM_RANGE, hex)
+END_REGISTER(RB_EDRAM_INFO)
+
+START_REGISTER(RB_CRC_RD_PORT)
+    GENERATE_FIELD(CRC_DATA, hex)
+END_REGISTER(RB_CRC_RD_PORT)
+
+START_REGISTER(RB_CRC_CONTROL)
+    GENERATE_FIELD(CRC_RD_ADVANCE, bool)
+END_REGISTER(RB_CRC_CONTROL)
+
+START_REGISTER(RB_CRC_MASK)
+    GENERATE_FIELD(CRC_MASK, hex)
+END_REGISTER(RB_CRC_MASK)
+
+START_REGISTER(RB_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT)
+END_REGISTER(RB_PERFCOUNTER0_SELECT)
+
+START_REGISTER(RB_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_LOW)
+
+START_REGISTER(RB_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_HI)
+
+START_REGISTER(RB_TOTAL_SAMPLES)
+    GENERATE_FIELD(TOTAL_SAMPLES, int)
+END_REGISTER(RB_TOTAL_SAMPLES)
+
+START_REGISTER(RB_ZPASS_SAMPLES)
+    GENERATE_FIELD(ZPASS_SAMPLES, int)
+END_REGISTER(RB_ZPASS_SAMPLES)
+
+START_REGISTER(RB_ZFAIL_SAMPLES)
+    GENERATE_FIELD(ZFAIL_SAMPLES, int)
+END_REGISTER(RB_ZFAIL_SAMPLES)
+
+START_REGISTER(RB_SFAIL_SAMPLES)
+    GENERATE_FIELD(SFAIL_SAMPLES, int)
+END_REGISTER(RB_SFAIL_SAMPLES)
+
+START_REGISTER(RB_DEBUG_0)
+    GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z1_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z0_FULL, bool)
+    GENERATE_FIELD(RDREQ_C1_FULL, bool)
+    GENERATE_FIELD(RDREQ_C0_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z1_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z0_FULL, bool)
+    GENERATE_FIELD(WRREQ_C1_FULL, bool)
+    GENERATE_FIELD(WRREQ_C0_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool)
+    GENERATE_FIELD(C_SX_LAT_FULL, bool)
+    GENERATE_FIELD(C_SX_CMD_FULL, bool)
+    GENERATE_FIELD(C_EZ_TILE_FULL, bool)
+    GENERATE_FIELD(C_REQ_FULL, bool)
+    GENERATE_FIELD(C_MASK_FULL, bool)
+    GENERATE_FIELD(EZ_INFSAMP_FULL, bool)
+END_REGISTER(RB_DEBUG_0)
+
+START_REGISTER(RB_DEBUG_1)
+    GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(C_SX_LAT_EMPTY, bool)
+    GENERATE_FIELD(C_SX_CMD_EMPTY, bool)
+    GENERATE_FIELD(C_EZ_TILE_EMPTY, bool)
+    GENERATE_FIELD(C_REQ_EMPTY, bool)
+    GENERATE_FIELD(C_MASK_EMPTY, bool)
+    GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool)
+END_REGISTER(RB_DEBUG_1)
+
+START_REGISTER(RB_DEBUG_2)
+    GENERATE_FIELD(TILE_FIFO_COUNT, bool)
+    GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool)
+    GENERATE_FIELD(MEM_EXPORT_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool)
+    GENERATE_FIELD(CURRENT_TILE_EVENT, bool)
+    GENERATE_FIELD(EZ_INFTILE_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool)
+    GENERATE_FIELD(Z0_MASK_FULL, bool)
+    GENERATE_FIELD(Z1_MASK_FULL, bool)
+    GENERATE_FIELD(Z0_REQ_FULL, bool)
+    GENERATE_FIELD(Z1_REQ_FULL, bool)
+    GENERATE_FIELD(Z_SAMP_FULL, bool)
+    GENERATE_FIELD(Z_TILE_FULL, bool)
+    GENERATE_FIELD(EZ_INFTILE_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool)
+    GENERATE_FIELD(Z0_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z1_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z0_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z1_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z_SAMP_EMPTY, bool)
+    GENERATE_FIELD(Z_TILE_EMPTY, bool)
+END_REGISTER(RB_DEBUG_2)
+
+START_REGISTER(RB_DEBUG_3)
+    GENERATE_FIELD(ACCUM_VALID, bool)
+    GENERATE_FIELD(ACCUM_FLUSHING, bool)
+    GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool)
+    GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool)
+    GENERATE_FIELD(SHD_FULL, bool)
+    GENERATE_FIELD(SHD_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool)
+    GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_LOWER_FULL, bool)
+    GENERATE_FIELD(ZEXP_UPPER_FULL, bool)
+END_REGISTER(RB_DEBUG_3)
+
+START_REGISTER(RB_DEBUG_4)
+    GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool)
+    GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool)
+    GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool)
+END_REGISTER(RB_DEBUG_4)
+
+START_REGISTER(RB_FLAG_CONTROL)
+    GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool)
+END_REGISTER(RB_FLAG_CONTROL)
+
+START_REGISTER(RB_BC_SPARES)
+    GENERATE_FIELD(RESERVED, bool)
+END_REGISTER(RB_BC_SPARES)
+
+START_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray)
+    GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX)
+END_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+
+START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX)
+END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h
new file mode 100644
index 000000000000..0e32e421d0a3
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h
@@ -0,0 +1,95 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _R400IPT_H_
+#define _R400IPT_H_
+
+// Hand-generated list from Yamato_PM4_Spec.doc
+
+#define PM4_PACKET0_NOP     0x00000000          // Empty type-0 packet header
+#define PM4_PACKET1_NOP     0x40000000          // Empty type-1 packet header
+#define PM4_PACKET2_NOP     0x80000000          // Empty type-2 packet header (reserved)
+
+#define PM4_COUNT_SHIFT     16  
+#define PM4_COUNT_MASK      
+#define PM4_PACKET_COUNT(__x)   ((((__x)-1) << PM4_COUNT_SHIFT) & 0x3fff0000)
+// Type 3 packet headers
+
+#define PM4_PACKET3_NOP                         0xC0001000  // Do nothing.
+#define PM4_PACKET3_IB_PREFETCH_END             0xC0001700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_SUBBLK_PREFETCH             0xC0001F00  // Internal Packet Used Only by CP
+
+#define PM4_PACKET3_INSTR_PREFETCH              0xC0002000  // Internal Packet Used Only by CP
+#define PM4_PACKET3_REG_RMW                     0xC0002100  // Register Read-Modify-Write                               New for R400
+#define PM4_PACKET3_DRAW_INDX                   0xC0002200  // Initiate fetch of index buffer                           New for R400
+#define PM4_PACKET3_VIZ_QUERY                   0xC0002300  // Begin/End initiator for Viz Query extent processing      New for R400
+#define PM4_PACKET3_SET_STATE                   0xC0002500  // Fetch State Sub-Blocks and Initiate Shader Code DMAs     New for R400
+#define PM4_PACKET3_WAIT_FOR_IDLE               0xC0002600  // Wait for the engine to be idle. 
+#define PM4_PACKET3_IM_LOAD                     0xC0002700  // Load Sequencer Instruction Memory for a Specific Shader  New for R400
+#define PM4_PACKET3_IM_LOAD_IMMEDIATE           0xC0002B00  // Load Sequencer Instruction Memory for a Specific Shader  New for R400
+#define PM4_PACKET3_SET_CONSTANT                0xC0002D00  // Load Constant Into Chip & Shadow to Memory               New for R400
+#define PM4_PACKET3_LOAD_CONSTANT_CONTEXT       0xC0002E00  // Load All Constants from a Location in Memory             New for R400
+#define PM4_PACKET3_LOAD_ALU_CONSTANT           0xC0002F00  // Load ALu constants from a location in memory - similar to SET_CONSTANT but tuned for performance when loading only ALU constants
+
+#define PM4_PACKET3_DRAW_INDX_BIN               0xC0003400  // Initiate fetch of index buffer and BIN info used for visibility test
+#define PM4_PACKET3_3D_DRAW_INDX_2_BIN          0xC0003500  // Draw using supplied indices and initiate fetch of BIN info for visibility test
+#define PM4_PACKET3_3D_DRAW_INDX_2              0xC0003600  // Draw primitives using vertex buf and Indices in this packet. Pkt does NOT contain vtx fmt
+#define PM4_PACKET3_INDIRECT_BUFFER_PFD         0xC0003700
+#define PM4_PACKET3_INVALIDATE_STATE            0xC0003B00  // Selective Invalidation of State Pointers                 New for R400
+#define PM4_PACKET3_WAIT_REG_MEM                0xC0003C00  // Wait Until a Register or Memory Location is a Specific Value.   New for R400
+#define PM4_PACKET3_MEM_WRITE                   0xC0003D00  // Write DWORD to Memory For Synchronization                New for R400
+#define PM4_PACKET3_REG_TO_MEM                  0xC0003E00  // Reads Register in Chip and Writes to Memory              New for R400
+#define PM4_PACKET3_INDIRECT_BUFFER             0xC0003F00  // Indirect Buffer Dispatch - Pre-fetch parser uses this packet type in determining to pre-fetch the indirect buffer.  Supported
+
+#define PM4_PACKET3_CP_INTERRUPT                0xC0004000  // Generate Interrupt from the Command Stream               New for R400
+#define PM4_PACKET3_COND_EXEC                   0xC0004400  // Conditional execution of a sequence of packets
+#define PM4_PACKET3_COND_WRITE                  0xC0004500  // Conditional Write to Memory                              New for R400
+#define PM4_PACKET3_EVENT_WRITE                 0xC0004600  // Generate An Event that Creates a Write to Memory when Completed  New for R400
+#define PM4_PACKET3_INSTR_MATCH                 0xC0004700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_ME_INIT                     0xC0004800  // Initialize CP's Micro Engine                             New for R400
+#define PM4_PACKET3_CONST_PREFETCH              0xC0004900  // Internal packet used only by CP
+#define PM4_PACKET3_MEM_WRITE_CNTR              0xC0004F00
+
+#define PM4_PACKET3_SET_BIN_MASK                0xC0005000  // Sets the 64-bit BIN_MASK register in the PFP
+#define PM4_PACKET3_SET_BIN_SELECT              0xC0005100  // Sets the 64-bit BIN_SELECT register in the PFP
+#define PM4_PACKET3_WAIT_REG_EQ                 0xC0005200  // Wait until a register location is equal to a specific value
+#define PM4_PACKET3_WAIT_REG_GTE                0xC0005300  // Wait until a register location is greater than or equal to a specific value
+#define PM4_PACKET3_INCR_UPDT_STATE             0xC0005500  // Internal Packet Used Only by CP  
+#define PM4_PACKET3_INCR_UPDT_CONST             0xC0005600  // Internal Packet Used Only by CP
+#define PM4_PACKET3_INCR_UPDT_INSTR             0xC0005700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_EVENT_WRITE_SHD             0xC0005800  // Generate a VS|PS_Done Event.
+#define PM4_PACKET3_EVENT_WRITE_CFL             0xC0005900  // Generate a Cach Flush Done Event
+#define PM4_PACKET3_EVENT_WRITE_ZPD             0xC0005B00  // Generate a Cach Flush Done Event
+#define PM4_PACKET3_WAIT_UNTIL_READ             0xC0005C00  // Wait Until a Read completes.
+#define PM4_PACKET3_WAIT_IB_PFD_COMPLETE        0xC0005D00  // Wait Until all Base/Size writes from an IB_PFD packet have completed.
+#define PM4_PACKET3_CONTEXT_UPDATE              0xC0005E00  // Updates the current context if needed.
+
+    /****** New Opcodes For R400 (all decode values are TBD) ******/
+
+
+#endif //  _R400IPT_H_
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h
new file mode 100644
index 000000000000..52ced9af774c
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h
@@ -0,0 +1,5908 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_MASK_HEADER)
+#define _yamato_MASK_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK            0xffffffffL
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK             0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA                  0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK            0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA                 0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK             0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA                  0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK            0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA                 0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK             0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA                  0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK            0x00000020L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA                 0x00000020L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK                    0x00000100L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT                         0x00000100L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK                     0x00000200L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT                          0x00000200L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK                    0x00000400L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT                         0x00000400L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK               0x00000800L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF                    0x00000800L
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK                 0x00010000L
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE                      0x00010000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK       0x00040000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA            0x00040000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK            0x00080000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF                 0x00080000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK          0x00100000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT               0x00100000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK                  0x00200000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR                       0x00200000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK                0x00400000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN                     0x00400000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK                 0x00800000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN                      0x00800000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK                 0x01000000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN                      0x01000000L
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK           0x00000001L
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA                0x00000001L
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_CL_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_SC_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK                    0x00000001L
+#define PA_SU_VTX_CNTL__PIX_CENTER                         0x00000001L
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK                    0x00000006L
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK                    0x00000038L
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT_MASK                      0x0000ffffL
+#define PA_SU_POINT_SIZE__WIDTH_MASK                       0xffff0000L
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK                  0x0000ffffL
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK                  0xffff0000L
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH_MASK                        0x0000ffffL
+
+// PA_SU_FACE_DATA
+#define PA_SU_FACE_DATA__BASE_ADDR_MASK                    0xffffffe0L
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK                0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT                     0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK                 0x00000002L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK                      0x00000002L
+#define PA_SU_SC_MODE_CNTL__FACE_MASK                      0x00000004L
+#define PA_SU_SC_MODE_CNTL__FACE                           0x00000004L
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK                 0x00000018L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK      0x000000e0L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK       0x00000700L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK  0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE       0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK   0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE        0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK   0x00002000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE        0x00002000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK               0x00008000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE                    0x00008000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK  0x00010000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE       0x00010000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK       0x00040000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE            0x00040000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK        0x00080000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST             0x00080000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK            0x00100000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS                 0x00100000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK         0x00200000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA              0x00200000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK         0x00800000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE              0x00800000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK      0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI           0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L
+#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS_MASK          0x10000000L
+#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS               0x10000000L
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS_MASK        0x20000000L
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS             0x20000000L
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE_MASK          0x40000000L
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE               0x40000000L
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE_MASK         0x80000000L
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE              0x80000000L
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK          0xffffffffL
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK        0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK           0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK         0xffffffffL
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK          0x00007fffL
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK          0x7fff0000L
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK             0x00000007L
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK              0x0001e000L
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK_MASK                        0x0000ffffL
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK              0x0000ffffL
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK              0x00ff0000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK         0x10000000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER              0x10000000L
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK           0x60000000L
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL_MASK                    0x000000ffL
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK                0x00000100L
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL                     0x00000100L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK            0x00000200L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH                 0x00000200L
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK                   0x00000400L
+#define PA_SC_LINE_CNTL__LAST_PIXEL                        0x00000400L
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK                 0x3fff0000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE     0x80000000L
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK                 0x3fff0000L
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK                 0x7fff0000L
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK                 0x7fff0000L
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK                0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA                     0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK                 0x0000003eL
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK        0x00000080L
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z             0x00000080L
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK           0xffffffffL
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK         0x0000000fL
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK       0x0000ff00L
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY_MASK                    0x80000000L
+#define PA_CL_CNTL_STATUS__CL_BUSY                         0x80000000L
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK                    0x80000000L
+#define PA_SU_CNTL_STATUS__SU_BUSY                         0x80000000L
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY_MASK                    0x80000000L
+#define PA_SC_CNTL_STATUS__SC_BUSY                         0x80000000L
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK    0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write         0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK     0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full          0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK    0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write         0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK     0x00000008L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full          0x00000008L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty   0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full    0x00000020L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty      0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK  0x00000080L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full       0x00000080L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK  0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty       0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK   0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full        0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK  0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty       0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK   0x00000800L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full        0x00000800L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty      0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK       0x00002000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full            0x00002000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty  0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full   0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty  0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full   0x00020000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty    0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full     0x00080000L
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK              0xfff00000L
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet   0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim    0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive  0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK      0x00380000L
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK              0xff000000L
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK             0x001fffffL
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK             0x7f000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK             0x000fff00L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK             0xfc000000L
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event  0x00000080L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK             0xffffff00L
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK             0x00000006L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK             0x00c00000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK             0xf0000000L
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK     0x00000001L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event          0x00000001L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK             0x000000c0L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK             0x00003000L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK             0x000c0000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK          0x00100000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid               0x00100000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait      0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK     0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty          0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK      0x20000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full           0x20000000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK             0x00000030L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK             0x00000c00L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK             0x00180000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet  0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK  0xfc000000L
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK              0xfffffff0L
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK             0x0000001cL
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK   0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty        0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK             0x00007800L
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK   0x00200000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid        0x00200000L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK             0xffc00000L
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK        0x0000000fL
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK       0x000007f0L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK             0x00003800L
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK      0x0003c000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1  0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0  0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK        0x07f00000L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK             0xf8000000L
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK             0x0000000fL
+#define SXIFCCG_DEBUG_REG0__position_address_MASK          0x00000070L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK              0x00000380L
+#define SXIFCCG_DEBUG_REG0__point_address_MASK             0x00001c00L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK              0x0000e000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx   0x00010000L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK              0x00060000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK    0x00780000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK         0x3f800000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK     0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc          0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK     0x80000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel          0x80000000L
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK              0x00000003L
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK            0x0000000cL
+#define SXIFCCG_DEBUG_REG1__available_positions_MASK       0x00000070L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK              0x00000780L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK        0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance             0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK           0x00007000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector  0x00008000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK              0x000f0000L
+#define SXIFCCG_DEBUG_REG1__aux_sel_MASK                   0x00100000L
+#define SXIFCCG_DEBUG_REG1__aux_sel                        0x00100000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK              0x00600000L
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK              0x01800000L
+#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK          0xfe000000L
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent_MASK                   0x00000001L
+#define SXIFCCG_DEBUG_REG2__sx_sent                        0x00000001L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK              0x00000002L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3                   0x00000002L
+#define SXIFCCG_DEBUG_REG2__sx_aux_MASK                    0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_aux                         0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK           0x000001f8L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK          0x0000fe00L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK              0x00010000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2                   0x00010000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx    0x00020000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK              0x000c0000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK              0x03c00000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK   0x04000000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded        0x04000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK     0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty          0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK      0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full           0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK  0xe0000000L
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK              0x00000010L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3                   0x00000010L
+#define SXIFCCG_DEBUG_REG3__available_positions_MASK       0x000000e0L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK              0x00000f00L
+#define SXIFCCG_DEBUG_REG3__current_state_MASK             0x00003000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK         0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty              0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK          0x00008000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full               0x00008000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK              0x00030000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK    0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty         0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK     0x00080000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full          0x00080000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK   0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty        0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK    0x00200000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full         0x00200000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK              0xffc00000L
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state_MASK               0x0000001fL
+#define SETUP_DEBUG_REG0__pmode_state_MASK                 0x000007e0L
+#define SETUP_DEBUG_REG0__ge_stallb_MASK                   0x00000800L
+#define SETUP_DEBUG_REG0__ge_stallb                        0x00000800L
+#define SETUP_DEBUG_REG0__geom_enable_MASK                 0x00001000L
+#define SETUP_DEBUG_REG0__geom_enable                      0x00001000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK           0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr                0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_rtr_MASK                 0x00004000L
+#define SETUP_DEBUG_REG0__su_clip_rtr                      0x00004000L
+#define SETUP_DEBUG_REG0__pfifo_busy_MASK                  0x00008000L
+#define SETUP_DEBUG_REG0__pfifo_busy                       0x00008000L
+#define SETUP_DEBUG_REG0__su_cntl_busy_MASK                0x00010000L
+#define SETUP_DEBUG_REG0__su_cntl_busy                     0x00010000L
+#define SETUP_DEBUG_REG0__geom_busy_MASK                   0x00020000L
+#define SETUP_DEBUG_REG0__geom_busy                        0x00020000L
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG4__null_prim_gated_MASK             0x00000800L
+#define SETUP_DEBUG_REG4__null_prim_gated                  0x00000800L
+#define SETUP_DEBUG_REG4__backfacing_gated_MASK            0x00001000L
+#define SETUP_DEBUG_REG4__backfacing_gated                 0x00001000L
+#define SETUP_DEBUG_REG4__st_indx_gated_MASK               0x0000e000L
+#define SETUP_DEBUG_REG4__clipped_gated_MASK               0x00010000L
+#define SETUP_DEBUG_REG4__clipped_gated                    0x00010000L
+#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK          0x000e0000L
+#define SETUP_DEBUG_REG4__xmajor_gated_MASK                0x00100000L
+#define SETUP_DEBUG_REG4__xmajor_gated                     0x00100000L
+#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK          0x00600000L
+#define SETUP_DEBUG_REG4__type_gated_MASK                  0x03800000L
+#define SETUP_DEBUG_REG4__fpov_gated_MASK                  0x04000000L
+#define SETUP_DEBUG_REG4__fpov_gated                       0x04000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK            0x08000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated                 0x08000000L
+#define SETUP_DEBUG_REG4__event_gated_MASK                 0x10000000L
+#define SETUP_DEBUG_REG4__event_gated                      0x10000000L
+#define SETUP_DEBUG_REG4__eop_gated_MASK                   0x20000000L
+#define SETUP_DEBUG_REG4__eop_gated                        0x20000000L
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK       0x003ff800L
+#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK         0x00c00000L
+#define SETUP_DEBUG_REG5__event_id_gated_MASK              0x1f000000L
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1_MASK                      0x00000001L
+#define SC_DEBUG_0__pa_freeze_b1                           0x00000001L
+#define SC_DEBUG_0__pa_sc_valid_MASK                       0x00000002L
+#define SC_DEBUG_0__pa_sc_valid                            0x00000002L
+#define SC_DEBUG_0__pa_sc_phase_MASK                       0x0000001cL
+#define SC_DEBUG_0__cntx_cnt_MASK                          0x00000fe0L
+#define SC_DEBUG_0__decr_cntx_cnt_MASK                     0x00001000L
+#define SC_DEBUG_0__decr_cntx_cnt                          0x00001000L
+#define SC_DEBUG_0__incr_cntx_cnt_MASK                     0x00002000L
+#define SC_DEBUG_0__incr_cntx_cnt                          0x00002000L
+#define SC_DEBUG_0__trigger_MASK                           0x80000000L
+#define SC_DEBUG_0__trigger                                0x80000000L
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state_MASK                          0x00000007L
+#define SC_DEBUG_1__em1_data_ready_MASK                    0x00000008L
+#define SC_DEBUG_1__em1_data_ready                         0x00000008L
+#define SC_DEBUG_1__em2_data_ready_MASK                    0x00000010L
+#define SC_DEBUG_1__em2_data_ready                         0x00000010L
+#define SC_DEBUG_1__move_em1_to_em2_MASK                   0x00000020L
+#define SC_DEBUG_1__move_em1_to_em2                        0x00000020L
+#define SC_DEBUG_1__ef_data_ready_MASK                     0x00000040L
+#define SC_DEBUG_1__ef_data_ready                          0x00000040L
+#define SC_DEBUG_1__ef_state_MASK                          0x00000180L
+#define SC_DEBUG_1__pipe_valid_MASK                        0x00000200L
+#define SC_DEBUG_1__pipe_valid                             0x00000200L
+#define SC_DEBUG_1__trigger_MASK                           0x80000000L
+#define SC_DEBUG_1__trigger                                0x80000000L
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly_MASK                        0x00000001L
+#define SC_DEBUG_2__rc_rtr_dly                             0x00000001L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK              0x00000002L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1                   0x00000002L
+#define SC_DEBUG_2__pipe_freeze_b_MASK                     0x00000008L
+#define SC_DEBUG_2__pipe_freeze_b                          0x00000008L
+#define SC_DEBUG_2__prim_rts_MASK                          0x00000010L
+#define SC_DEBUG_2__prim_rts                               0x00000010L
+#define SC_DEBUG_2__next_prim_rts_dly_MASK                 0x00000020L
+#define SC_DEBUG_2__next_prim_rts_dly                      0x00000020L
+#define SC_DEBUG_2__next_prim_rtr_dly_MASK                 0x00000040L
+#define SC_DEBUG_2__next_prim_rtr_dly                      0x00000040L
+#define SC_DEBUG_2__pre_stage1_rts_d1_MASK                 0x00000080L
+#define SC_DEBUG_2__pre_stage1_rts_d1                      0x00000080L
+#define SC_DEBUG_2__stage0_rts_MASK                        0x00000100L
+#define SC_DEBUG_2__stage0_rts                             0x00000100L
+#define SC_DEBUG_2__phase_rts_dly_MASK                     0x00000200L
+#define SC_DEBUG_2__phase_rts_dly                          0x00000200L
+#define SC_DEBUG_2__end_of_prim_s1_dly_MASK                0x00008000L
+#define SC_DEBUG_2__end_of_prim_s1_dly                     0x00008000L
+#define SC_DEBUG_2__pass_empty_prim_s1_MASK                0x00010000L
+#define SC_DEBUG_2__pass_empty_prim_s1                     0x00010000L
+#define SC_DEBUG_2__event_id_s1_MASK                       0x003e0000L
+#define SC_DEBUG_2__event_s1_MASK                          0x00400000L
+#define SC_DEBUG_2__event_s1                               0x00400000L
+#define SC_DEBUG_2__trigger_MASK                           0x80000000L
+#define SC_DEBUG_2__trigger                                0x80000000L
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1_MASK                         0x000007ffL
+#define SC_DEBUG_3__y_curr_s1_MASK                         0x003ff800L
+#define SC_DEBUG_3__trigger_MASK                           0x80000000L
+#define SC_DEBUG_3__trigger                                0x80000000L
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_4__y_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_4__y_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_4__y_dir_s1                               0x10000000L
+#define SC_DEBUG_4__trigger_MASK                           0x80000000L
+#define SC_DEBUG_4__trigger                                0x80000000L
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_5__x_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_5__x_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_5__x_dir_s1                               0x10000000L
+#define SC_DEBUG_5__trigger_MASK                           0x80000000L
+#define SC_DEBUG_5__trigger                                0x80000000L
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty_MASK                        0x00000001L
+#define SC_DEBUG_6__z_ff_empty                             0x00000001L
+#define SC_DEBUG_6__qmcntl_ff_empty_MASK                   0x00000002L
+#define SC_DEBUG_6__qmcntl_ff_empty                        0x00000002L
+#define SC_DEBUG_6__xy_ff_empty_MASK                       0x00000004L
+#define SC_DEBUG_6__xy_ff_empty                            0x00000004L
+#define SC_DEBUG_6__event_flag_MASK                        0x00000008L
+#define SC_DEBUG_6__event_flag                             0x00000008L
+#define SC_DEBUG_6__z_mask_needed_MASK                     0x00000010L
+#define SC_DEBUG_6__z_mask_needed                          0x00000010L
+#define SC_DEBUG_6__state_MASK                             0x000000e0L
+#define SC_DEBUG_6__state_delayed_MASK                     0x00000700L
+#define SC_DEBUG_6__data_valid_MASK                        0x00000800L
+#define SC_DEBUG_6__data_valid                             0x00000800L
+#define SC_DEBUG_6__data_valid_d_MASK                      0x00001000L
+#define SC_DEBUG_6__data_valid_d                           0x00001000L
+#define SC_DEBUG_6__tilex_delayed_MASK                     0x003fe000L
+#define SC_DEBUG_6__tiley_delayed_MASK                     0x7fc00000L
+#define SC_DEBUG_6__trigger_MASK                           0x80000000L
+#define SC_DEBUG_6__trigger                                0x80000000L
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag_MASK                        0x00000001L
+#define SC_DEBUG_7__event_flag                             0x00000001L
+#define SC_DEBUG_7__deallocate_MASK                        0x0000000eL
+#define SC_DEBUG_7__fposition_MASK                         0x00000010L
+#define SC_DEBUG_7__fposition                              0x00000010L
+#define SC_DEBUG_7__sr_prim_we_MASK                        0x00000020L
+#define SC_DEBUG_7__sr_prim_we                             0x00000020L
+#define SC_DEBUG_7__last_tile_MASK                         0x00000040L
+#define SC_DEBUG_7__last_tile                              0x00000040L
+#define SC_DEBUG_7__tile_ff_we_MASK                        0x00000080L
+#define SC_DEBUG_7__tile_ff_we                             0x00000080L
+#define SC_DEBUG_7__qs_data_valid_MASK                     0x00000100L
+#define SC_DEBUG_7__qs_data_valid                          0x00000100L
+#define SC_DEBUG_7__qs_q0_y_MASK                           0x00000600L
+#define SC_DEBUG_7__qs_q0_x_MASK                           0x00001800L
+#define SC_DEBUG_7__qs_q0_valid_MASK                       0x00002000L
+#define SC_DEBUG_7__qs_q0_valid                            0x00002000L
+#define SC_DEBUG_7__prim_ff_we_MASK                        0x00004000L
+#define SC_DEBUG_7__prim_ff_we                             0x00004000L
+#define SC_DEBUG_7__tile_ff_re_MASK                        0x00008000L
+#define SC_DEBUG_7__tile_ff_re                             0x00008000L
+#define SC_DEBUG_7__fw_prim_data_valid_MASK                0x00010000L
+#define SC_DEBUG_7__fw_prim_data_valid                     0x00010000L
+#define SC_DEBUG_7__last_quad_of_tile_MASK                 0x00020000L
+#define SC_DEBUG_7__last_quad_of_tile                      0x00020000L
+#define SC_DEBUG_7__first_quad_of_tile_MASK                0x00040000L
+#define SC_DEBUG_7__first_quad_of_tile                     0x00040000L
+#define SC_DEBUG_7__first_quad_of_prim_MASK                0x00080000L
+#define SC_DEBUG_7__first_quad_of_prim                     0x00080000L
+#define SC_DEBUG_7__new_prim_MASK                          0x00100000L
+#define SC_DEBUG_7__new_prim                               0x00100000L
+#define SC_DEBUG_7__load_new_tile_data_MASK                0x00200000L
+#define SC_DEBUG_7__load_new_tile_data                     0x00200000L
+#define SC_DEBUG_7__state_MASK                             0x00c00000L
+#define SC_DEBUG_7__fifos_ready_MASK                       0x01000000L
+#define SC_DEBUG_7__fifos_ready                            0x01000000L
+#define SC_DEBUG_7__trigger_MASK                           0x80000000L
+#define SC_DEBUG_7__trigger                                0x80000000L
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last_MASK                       0x00000001L
+#define SC_DEBUG_8__sample_last                            0x00000001L
+#define SC_DEBUG_8__sample_mask_MASK                       0x0000001eL
+#define SC_DEBUG_8__sample_y_MASK                          0x00000060L
+#define SC_DEBUG_8__sample_x_MASK                          0x00000180L
+#define SC_DEBUG_8__sample_send_MASK                       0x00000200L
+#define SC_DEBUG_8__sample_send                            0x00000200L
+#define SC_DEBUG_8__next_cycle_MASK                        0x00000c00L
+#define SC_DEBUG_8__ez_sample_ff_full_MASK                 0x00001000L
+#define SC_DEBUG_8__ez_sample_ff_full                      0x00001000L
+#define SC_DEBUG_8__rb_sc_samp_rtr_MASK                    0x00002000L
+#define SC_DEBUG_8__rb_sc_samp_rtr                         0x00002000L
+#define SC_DEBUG_8__num_samples_MASK                       0x0000c000L
+#define SC_DEBUG_8__last_quad_of_tile_MASK                 0x00010000L
+#define SC_DEBUG_8__last_quad_of_tile                      0x00010000L
+#define SC_DEBUG_8__last_quad_of_prim_MASK                 0x00020000L
+#define SC_DEBUG_8__last_quad_of_prim                      0x00020000L
+#define SC_DEBUG_8__first_quad_of_prim_MASK                0x00040000L
+#define SC_DEBUG_8__first_quad_of_prim                     0x00040000L
+#define SC_DEBUG_8__sample_we_MASK                         0x00080000L
+#define SC_DEBUG_8__sample_we                              0x00080000L
+#define SC_DEBUG_8__fposition_MASK                         0x00100000L
+#define SC_DEBUG_8__fposition                              0x00100000L
+#define SC_DEBUG_8__event_id_MASK                          0x03e00000L
+#define SC_DEBUG_8__event_flag_MASK                        0x04000000L
+#define SC_DEBUG_8__event_flag                             0x04000000L
+#define SC_DEBUG_8__fw_prim_data_valid_MASK                0x08000000L
+#define SC_DEBUG_8__fw_prim_data_valid                     0x08000000L
+#define SC_DEBUG_8__trigger_MASK                           0x80000000L
+#define SC_DEBUG_8__trigger                                0x80000000L
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send_MASK                        0x00000001L
+#define SC_DEBUG_9__rb_sc_send                             0x00000001L
+#define SC_DEBUG_9__rb_sc_ez_mask_MASK                     0x0000001eL
+#define SC_DEBUG_9__fifo_data_ready_MASK                   0x00000020L
+#define SC_DEBUG_9__fifo_data_ready                        0x00000020L
+#define SC_DEBUG_9__early_z_enable_MASK                    0x00000040L
+#define SC_DEBUG_9__early_z_enable                         0x00000040L
+#define SC_DEBUG_9__mask_state_MASK                        0x00000180L
+#define SC_DEBUG_9__next_ez_mask_MASK                      0x01fffe00L
+#define SC_DEBUG_9__mask_ready_MASK                        0x02000000L
+#define SC_DEBUG_9__mask_ready                             0x02000000L
+#define SC_DEBUG_9__drop_sample_MASK                       0x04000000L
+#define SC_DEBUG_9__drop_sample                            0x04000000L
+#define SC_DEBUG_9__fetch_new_sample_data_MASK             0x08000000L
+#define SC_DEBUG_9__fetch_new_sample_data                  0x08000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK          0x10000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask               0x10000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK         0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data              0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK           0x40000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data                0x40000000L
+#define SC_DEBUG_9__trigger_MASK                           0x80000000L
+#define SC_DEBUG_9__trigger                                0x80000000L
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask_MASK             0x0000ffffL
+#define SC_DEBUG_10__trigger_MASK                          0x80000000L
+#define SC_DEBUG_10__trigger                               0x80000000L
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready_MASK             0x00000001L
+#define SC_DEBUG_11__ez_sample_data_ready                  0x00000001L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK        0x00000002L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data             0x00000002L
+#define SC_DEBUG_11__ez_prim_data_ready_MASK               0x00000004L
+#define SC_DEBUG_11__ez_prim_data_ready                    0x00000004L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK          0x00000008L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data               0x00000008L
+#define SC_DEBUG_11__iterator_input_fz_MASK                0x00000010L
+#define SC_DEBUG_11__iterator_input_fz                     0x00000010L
+#define SC_DEBUG_11__packer_send_quads_MASK                0x00000020L
+#define SC_DEBUG_11__packer_send_quads                     0x00000020L
+#define SC_DEBUG_11__packer_send_cmd_MASK                  0x00000040L
+#define SC_DEBUG_11__packer_send_cmd                       0x00000040L
+#define SC_DEBUG_11__packer_send_event_MASK                0x00000080L
+#define SC_DEBUG_11__packer_send_event                     0x00000080L
+#define SC_DEBUG_11__next_state_MASK                       0x00000700L
+#define SC_DEBUG_11__state_MASK                            0x00003800L
+#define SC_DEBUG_11__stall_MASK                            0x00004000L
+#define SC_DEBUG_11__stall                                 0x00004000L
+#define SC_DEBUG_11__trigger_MASK                          0x80000000L
+#define SC_DEBUG_11__trigger                               0x80000000L
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff_MASK            0x00000001L
+#define SC_DEBUG_12__SQ_iterator_free_buff                 0x00000001L
+#define SC_DEBUG_12__event_id_MASK                         0x0000003eL
+#define SC_DEBUG_12__event_flag_MASK                       0x00000040L
+#define SC_DEBUG_12__event_flag                            0x00000040L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK          0x00000080L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly               0x00000080L
+#define SC_DEBUG_12__itercmdfifo_full_MASK                 0x00000100L
+#define SC_DEBUG_12__itercmdfifo_full                      0x00000100L
+#define SC_DEBUG_12__itercmdfifo_empty_MASK                0x00000200L
+#define SC_DEBUG_12__itercmdfifo_empty                     0x00000200L
+#define SC_DEBUG_12__iter_ds_one_clk_command_MASK          0x00000400L
+#define SC_DEBUG_12__iter_ds_one_clk_command               0x00000400L
+#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK             0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_prim0                  0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_vector_MASK            0x00001000L
+#define SC_DEBUG_12__iter_ds_end_of_vector                 0x00001000L
+#define SC_DEBUG_12__iter_qdhit0_MASK                      0x00002000L
+#define SC_DEBUG_12__iter_qdhit0                           0x00002000L
+#define SC_DEBUG_12__bc_use_centers_reg_MASK               0x00004000L
+#define SC_DEBUG_12__bc_use_centers_reg                    0x00004000L
+#define SC_DEBUG_12__bc_output_xy_reg_MASK                 0x00008000L
+#define SC_DEBUG_12__bc_output_xy_reg                      0x00008000L
+#define SC_DEBUG_12__iter_phase_out_MASK                   0x00030000L
+#define SC_DEBUG_12__iter_phase_reg_MASK                   0x000c0000L
+#define SC_DEBUG_12__iterator_SP_valid_MASK                0x00100000L
+#define SC_DEBUG_12__iterator_SP_valid                     0x00100000L
+#define SC_DEBUG_12__eopv_reg_MASK                         0x00200000L
+#define SC_DEBUG_12__eopv_reg                              0x00200000L
+#define SC_DEBUG_12__one_clk_cmd_reg_MASK                  0x00400000L
+#define SC_DEBUG_12__one_clk_cmd_reg                       0x00400000L
+#define SC_DEBUG_12__iter_dx_end_of_prim_MASK              0x00800000L
+#define SC_DEBUG_12__iter_dx_end_of_prim                   0x00800000L
+#define SC_DEBUG_12__trigger_MASK                          0x80000000L
+#define SC_DEBUG_12__trigger                               0x80000000L
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK                  0x00000001L
+#define GFX_COPY_STATE__SRC_STATE_ID                       0x00000001L
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK                 0x0000003fL
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK             0x000000c0L
+#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT_MASK      0x00000300L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK                0x00000800L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE                     0x00000800L
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK                   0x00001000L
+#define VGT_DRAW_INITIATOR__NOT_EOP                        0x00001000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK               0x00002000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX                    0x00002000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK     0x00004000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE          0x00004000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK           0x00008000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE                0x00008000L
+#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK               0xffff0000L
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK               0x0000003fL
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR_MASK                       0xffffffffL
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_DMA_SIZE__SWAP_MODE_MASK                       0xc0000000L
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK                   0xffffffffL
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_BIN_SIZE__FACENESS_FETCH_MASK                  0x40000000L
+#define VGT_BIN_SIZE__FACENESS_FETCH                       0x40000000L
+#define VGT_BIN_SIZE__FACENESS_RESET_MASK                  0x80000000L
+#define VGT_BIN_SIZE__FACENESS_RESET                       0x80000000L
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK                    0x00ffffffL
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK                    0x00ffffffL
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK                  0x00ffffffL
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK  0x00000007L
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK            0x00000003L
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK      0x00ffffffL
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC_MASK                             0x0000ffffL
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK            0x0000001fL
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK             0x00000001L
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID                  0x00000001L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK             0x00010000L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID                  0x00010000L
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK                0x0000001fL
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK                     0x00000001L
+#define VGT_CNTL_STATUS__VGT_BUSY                          0x00000001L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK                 0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY                      0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK             0x00000004L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY                  0x00000004L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK                 0x00000008L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY                      0x00000008L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK                  0x00000010L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY                       0x00000010L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK                 0x00000020L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY                      0x00000020L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK                  0x00000040L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY                       0x00000040L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK                 0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY                      0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK            0x00000100L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY                 0x00000100L
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy_MASK                   0x00000001L
+#define VGT_DEBUG_REG0__te_grp_busy                        0x00000001L
+#define VGT_DEBUG_REG0__pt_grp_busy_MASK                   0x00000002L
+#define VGT_DEBUG_REG0__pt_grp_busy                        0x00000002L
+#define VGT_DEBUG_REG0__vr_grp_busy_MASK                   0x00000004L
+#define VGT_DEBUG_REG0__vr_grp_busy                        0x00000004L
+#define VGT_DEBUG_REG0__dma_request_busy_MASK              0x00000008L
+#define VGT_DEBUG_REG0__dma_request_busy                   0x00000008L
+#define VGT_DEBUG_REG0__out_busy_MASK                      0x00000010L
+#define VGT_DEBUG_REG0__out_busy                           0x00000010L
+#define VGT_DEBUG_REG0__grp_backend_busy_MASK              0x00000020L
+#define VGT_DEBUG_REG0__grp_backend_busy                   0x00000020L
+#define VGT_DEBUG_REG0__grp_busy_MASK                      0x00000040L
+#define VGT_DEBUG_REG0__grp_busy                           0x00000040L
+#define VGT_DEBUG_REG0__dma_busy_MASK                      0x00000080L
+#define VGT_DEBUG_REG0__dma_busy                           0x00000080L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK         0x00000100L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy              0x00000100L
+#define VGT_DEBUG_REG0__rbiu_busy_MASK                     0x00000200L
+#define VGT_DEBUG_REG0__rbiu_busy                          0x00000200L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK      0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended           0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK               0x00000800L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy                    0x00000800L
+#define VGT_DEBUG_REG0__vgt_busy_extended_MASK             0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_extended                  0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_MASK                      0x00002000L
+#define VGT_DEBUG_REG0__vgt_busy                           0x00002000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK       0x00004000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out            0x00004000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK          0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy               0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK                 0x00010000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy                      0x00010000L
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read_MASK              0x00000001L
+#define VGT_DEBUG_REG1__out_te_data_read                   0x00000001L
+#define VGT_DEBUG_REG1__te_out_data_valid_MASK             0x00000002L
+#define VGT_DEBUG_REG1__te_out_data_valid                  0x00000002L
+#define VGT_DEBUG_REG1__out_pt_prim_read_MASK              0x00000004L
+#define VGT_DEBUG_REG1__out_pt_prim_read                   0x00000004L
+#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK             0x00000008L
+#define VGT_DEBUG_REG1__pt_out_prim_valid                  0x00000008L
+#define VGT_DEBUG_REG1__out_pt_data_read_MASK              0x00000010L
+#define VGT_DEBUG_REG1__out_pt_data_read                   0x00000010L
+#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK             0x00000020L
+#define VGT_DEBUG_REG1__pt_out_indx_valid                  0x00000020L
+#define VGT_DEBUG_REG1__out_vr_prim_read_MASK              0x00000040L
+#define VGT_DEBUG_REG1__out_vr_prim_read                   0x00000040L
+#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK             0x00000080L
+#define VGT_DEBUG_REG1__vr_out_prim_valid                  0x00000080L
+#define VGT_DEBUG_REG1__out_vr_indx_read_MASK              0x00000100L
+#define VGT_DEBUG_REG1__out_vr_indx_read                   0x00000100L
+#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK             0x00000200L
+#define VGT_DEBUG_REG1__vr_out_indx_valid                  0x00000200L
+#define VGT_DEBUG_REG1__te_grp_read_MASK                   0x00000400L
+#define VGT_DEBUG_REG1__te_grp_read                        0x00000400L
+#define VGT_DEBUG_REG1__grp_te_valid_MASK                  0x00000800L
+#define VGT_DEBUG_REG1__grp_te_valid                       0x00000800L
+#define VGT_DEBUG_REG1__pt_grp_read_MASK                   0x00001000L
+#define VGT_DEBUG_REG1__pt_grp_read                        0x00001000L
+#define VGT_DEBUG_REG1__grp_pt_valid_MASK                  0x00002000L
+#define VGT_DEBUG_REG1__grp_pt_valid                       0x00002000L
+#define VGT_DEBUG_REG1__vr_grp_read_MASK                   0x00004000L
+#define VGT_DEBUG_REG1__vr_grp_read                        0x00004000L
+#define VGT_DEBUG_REG1__grp_vr_valid_MASK                  0x00008000L
+#define VGT_DEBUG_REG1__grp_vr_valid                       0x00008000L
+#define VGT_DEBUG_REG1__grp_dma_read_MASK                  0x00010000L
+#define VGT_DEBUG_REG1__grp_dma_read                       0x00010000L
+#define VGT_DEBUG_REG1__dma_grp_valid_MASK                 0x00020000L
+#define VGT_DEBUG_REG1__dma_grp_valid                      0x00020000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK              0x00040000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read                   0x00040000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK             0x00080000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid                  0x00080000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK                    0x00100000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr                         0x00100000L
+#define VGT_DEBUG_REG1__VGT_MH_send_MASK                   0x00200000L
+#define VGT_DEBUG_REG1__VGT_MH_send                        0x00200000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK             0x00400000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr                  0x00400000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK            0x00800000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send                 0x00800000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK             0x01000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr                  0x01000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK            0x02000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send                 0x02000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK             0x04000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr                  0x04000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK            0x08000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send                 0x08000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK                    0x10000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr                         0x10000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send_MASK                   0x20000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send                        0x20000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK                0x40000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q                     0x40000000L
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en_MASK                    0x00000001L
+#define VGT_DEBUG_REG3__vgt_clk_en                         0x00000001L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK              0x00000002L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en                   0x00000002L
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK          0x0000001fL
+#define VGT_DEBUG_REG6__right_word_indx_q_MASK             0x000003e0L
+#define VGT_DEBUG_REG6__input_data_valid_MASK              0x00000400L
+#define VGT_DEBUG_REG6__input_data_valid                   0x00000400L
+#define VGT_DEBUG_REG6__input_data_xfer_MASK               0x00000800L
+#define VGT_DEBUG_REG6__input_data_xfer                    0x00000800L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK        0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q             0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK        0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d             0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK    0x00004000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d         0x00004000L
+#define VGT_DEBUG_REG6__space_avail_from_shift_MASK        0x00008000L
+#define VGT_DEBUG_REG6__space_avail_from_shift             0x00008000L
+#define VGT_DEBUG_REG6__shifter_first_load_MASK            0x00010000L
+#define VGT_DEBUG_REG6__shifter_first_load                 0x00010000L
+#define VGT_DEBUG_REG6__di_state_sel_q_MASK                0x00020000L
+#define VGT_DEBUG_REG6__di_state_sel_q                     0x00020000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q   0x00040000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK         0x00080000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q              0x00080000L
+#define VGT_DEBUG_REG6__di_event_flag_q_MASK               0x00100000L
+#define VGT_DEBUG_REG6__di_event_flag_q                    0x00100000L
+#define VGT_DEBUG_REG6__read_draw_initiator_MASK           0x00200000L
+#define VGT_DEBUG_REG6__read_draw_initiator                0x00200000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK   0x00400000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter        0x00400000L
+#define VGT_DEBUG_REG6__last_shift_of_packet_MASK          0x00800000L
+#define VGT_DEBUG_REG6__last_shift_of_packet               0x00800000L
+#define VGT_DEBUG_REG6__last_decr_of_packet_MASK           0x01000000L
+#define VGT_DEBUG_REG6__last_decr_of_packet                0x01000000L
+#define VGT_DEBUG_REG6__extract_vector_MASK                0x02000000L
+#define VGT_DEBUG_REG6__extract_vector                     0x02000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr_MASK                0x04000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr                     0x04000000L
+#define VGT_DEBUG_REG6__destination_rtr_MASK               0x08000000L
+#define VGT_DEBUG_REG6__destination_rtr                    0x08000000L
+#define VGT_DEBUG_REG6__grp_trigger_MASK                   0x10000000L
+#define VGT_DEBUG_REG6__grp_trigger                        0x10000000L
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q_MASK            0x0000ffffL
+#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK       0x000f0000L
+#define VGT_DEBUG_REG7__shift_amount_extract_MASK          0x00f00000L
+#define VGT_DEBUG_REG7__di_prim_type_q_MASK                0x3f000000L
+#define VGT_DEBUG_REG7__current_source_sel_MASK            0xc0000000L
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel_MASK            0x00000003L
+#define VGT_DEBUG_REG8__left_word_indx_q_MASK              0x0000007cL
+#define VGT_DEBUG_REG8__input_data_cnt_MASK                0x00000f80L
+#define VGT_DEBUG_REG8__input_data_lsw_MASK                0x0001f000L
+#define VGT_DEBUG_REG8__input_data_msw_MASK                0x003e0000L
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q_MASK                 0x0000001fL
+#define VGT_DEBUG_REG9__next_stride_d_MASK                 0x000003e0L
+#define VGT_DEBUG_REG9__current_shift_q_MASK               0x00007c00L
+#define VGT_DEBUG_REG9__current_shift_d_MASK               0x000f8000L
+#define VGT_DEBUG_REG9__current_stride_q_MASK              0x01f00000L
+#define VGT_DEBUG_REG9__current_stride_d_MASK              0x3e000000L
+#define VGT_DEBUG_REG9__grp_trigger_MASK                   0x40000000L
+#define VGT_DEBUG_REG9__grp_trigger                        0x40000000L
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0      0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0    0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0    0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L
+#define VGT_DEBUG_REG10__di_state_sel_q_MASK               0x00000010L
+#define VGT_DEBUG_REG10__di_state_sel_q                    0x00000010L
+#define VGT_DEBUG_REG10__last_decr_of_packet_MASK          0x00000020L
+#define VGT_DEBUG_REG10__last_decr_of_packet               0x00000020L
+#define VGT_DEBUG_REG10__bin_valid_MASK                    0x00000040L
+#define VGT_DEBUG_REG10__bin_valid                         0x00000040L
+#define VGT_DEBUG_REG10__read_block_MASK                   0x00000080L
+#define VGT_DEBUG_REG10__read_block                        0x00000080L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK       0x00000100L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read            0x00000100L
+#define VGT_DEBUG_REG10__last_bit_enable_q_MASK            0x00000200L
+#define VGT_DEBUG_REG10__last_bit_enable_q                 0x00000200L
+#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK            0x00000400L
+#define VGT_DEBUG_REG10__last_bit_end_di_q                 0x00000400L
+#define VGT_DEBUG_REG10__selected_data_MASK                0x0007f800L
+#define VGT_DEBUG_REG10__mask_input_data_MASK              0x07f80000L
+#define VGT_DEBUG_REG10__gap_q_MASK                        0x08000000L
+#define VGT_DEBUG_REG10__gap_q                             0x08000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK            0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z                 0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK            0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y                 0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK            0x40000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x                 0x40000000L
+#define VGT_DEBUG_REG10__grp_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG10__grp_trigger                       0x80000000L
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK         0x0000001fL
+#define VGT_DEBUG_REG12__right_word_indx_q_MASK            0x000003e0L
+#define VGT_DEBUG_REG12__input_data_valid_MASK             0x00000400L
+#define VGT_DEBUG_REG12__input_data_valid                  0x00000400L
+#define VGT_DEBUG_REG12__input_data_xfer_MASK              0x00000800L
+#define VGT_DEBUG_REG12__input_data_xfer                   0x00000800L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK       0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q            0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK       0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d            0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK   0x00004000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d        0x00004000L
+#define VGT_DEBUG_REG12__space_avail_from_shift_MASK       0x00008000L
+#define VGT_DEBUG_REG12__space_avail_from_shift            0x00008000L
+#define VGT_DEBUG_REG12__shifter_first_load_MASK           0x00010000L
+#define VGT_DEBUG_REG12__shifter_first_load                0x00010000L
+#define VGT_DEBUG_REG12__di_state_sel_q_MASK               0x00020000L
+#define VGT_DEBUG_REG12__di_state_sel_q                    0x00020000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q  0x00040000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK        0x00080000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q             0x00080000L
+#define VGT_DEBUG_REG12__di_event_flag_q_MASK              0x00100000L
+#define VGT_DEBUG_REG12__di_event_flag_q                   0x00100000L
+#define VGT_DEBUG_REG12__read_draw_initiator_MASK          0x00200000L
+#define VGT_DEBUG_REG12__read_draw_initiator               0x00200000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK  0x00400000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter       0x00400000L
+#define VGT_DEBUG_REG12__last_shift_of_packet_MASK         0x00800000L
+#define VGT_DEBUG_REG12__last_shift_of_packet              0x00800000L
+#define VGT_DEBUG_REG12__last_decr_of_packet_MASK          0x01000000L
+#define VGT_DEBUG_REG12__last_decr_of_packet               0x01000000L
+#define VGT_DEBUG_REG12__extract_vector_MASK               0x02000000L
+#define VGT_DEBUG_REG12__extract_vector                    0x02000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr_MASK               0x04000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr                    0x04000000L
+#define VGT_DEBUG_REG12__destination_rtr_MASK              0x08000000L
+#define VGT_DEBUG_REG12__destination_rtr                   0x08000000L
+#define VGT_DEBUG_REG12__bgrp_trigger_MASK                 0x10000000L
+#define VGT_DEBUG_REG12__bgrp_trigger                      0x10000000L
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q_MASK           0x0000ffffL
+#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK      0x000f0000L
+#define VGT_DEBUG_REG13__shift_amount_extract_MASK         0x00f00000L
+#define VGT_DEBUG_REG13__di_prim_type_q_MASK               0x3f000000L
+#define VGT_DEBUG_REG13__current_source_sel_MASK           0xc0000000L
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel_MASK           0x00000003L
+#define VGT_DEBUG_REG14__left_word_indx_q_MASK             0x0000007cL
+#define VGT_DEBUG_REG14__input_data_cnt_MASK               0x00000f80L
+#define VGT_DEBUG_REG14__input_data_lsw_MASK               0x0001f000L
+#define VGT_DEBUG_REG14__input_data_msw_MASK               0x003e0000L
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q_MASK                0x0000001fL
+#define VGT_DEBUG_REG15__next_stride_d_MASK                0x000003e0L
+#define VGT_DEBUG_REG15__current_shift_q_MASK              0x00007c00L
+#define VGT_DEBUG_REG15__current_shift_d_MASK              0x000f8000L
+#define VGT_DEBUG_REG15__current_stride_q_MASK             0x01f00000L
+#define VGT_DEBUG_REG15__current_stride_d_MASK             0x3e000000L
+#define VGT_DEBUG_REG15__bgrp_trigger_MASK                 0x40000000L
+#define VGT_DEBUG_REG15__bgrp_trigger                      0x40000000L
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK    0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full         0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK   0x00000002L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty        0x00000002L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK     0x00000004L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read          0x00000004L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK      0x00000008L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we           0x00000008L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK     0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full          0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK    0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty         0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK     0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q          0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK       0x00000080L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we            0x00000080L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK           0x00000100L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill                0x00000100L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK           0x00000200L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid                0x00000200L
+#define VGT_DEBUG_REG16__rst_last_bit_MASK                 0x00000400L
+#define VGT_DEBUG_REG16__rst_last_bit                      0x00000400L
+#define VGT_DEBUG_REG16__current_state_q_MASK              0x00000800L
+#define VGT_DEBUG_REG16__current_state_q                   0x00000800L
+#define VGT_DEBUG_REG16__old_state_q_MASK                  0x00001000L
+#define VGT_DEBUG_REG16__old_state_q                       0x00001000L
+#define VGT_DEBUG_REG16__old_state_en_MASK                 0x00002000L
+#define VGT_DEBUG_REG16__old_state_en                      0x00002000L
+#define VGT_DEBUG_REG16__prev_last_bit_q_MASK              0x00004000L
+#define VGT_DEBUG_REG16__prev_last_bit_q                   0x00004000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK               0x00008000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q                    0x00008000L
+#define VGT_DEBUG_REG16__last_bit_block_q_MASK             0x00010000L
+#define VGT_DEBUG_REG16__last_bit_block_q                  0x00010000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK             0x00020000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q                  0x00020000L
+#define VGT_DEBUG_REG16__load_empty_reg_MASK               0x00040000L
+#define VGT_DEBUG_REG16__load_empty_reg                    0x00040000L
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK     0x07f80000L
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK  0x18000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable      0x20000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK     0x40000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q          0x40000000L
+#define VGT_DEBUG_REG16__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG16__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q_MASK                  0x00000001L
+#define VGT_DEBUG_REG17__save_read_q                       0x00000001L
+#define VGT_DEBUG_REG17__extend_read_q_MASK                0x00000002L
+#define VGT_DEBUG_REG17__extend_read_q                     0x00000002L
+#define VGT_DEBUG_REG17__grp_indx_size_MASK                0x0000000cL
+#define VGT_DEBUG_REG17__cull_prim_true_MASK               0x00000010L
+#define VGT_DEBUG_REG17__cull_prim_true                    0x00000010L
+#define VGT_DEBUG_REG17__reset_bit2_q_MASK                 0x00000020L
+#define VGT_DEBUG_REG17__reset_bit2_q                      0x00000020L
+#define VGT_DEBUG_REG17__reset_bit1_q_MASK                 0x00000040L
+#define VGT_DEBUG_REG17__reset_bit1_q                      0x00000040L
+#define VGT_DEBUG_REG17__first_reg_first_q_MASK            0x00000080L
+#define VGT_DEBUG_REG17__first_reg_first_q                 0x00000080L
+#define VGT_DEBUG_REG17__check_second_reg_MASK             0x00000100L
+#define VGT_DEBUG_REG17__check_second_reg                  0x00000100L
+#define VGT_DEBUG_REG17__check_first_reg_MASK              0x00000200L
+#define VGT_DEBUG_REG17__check_first_reg                   0x00000200L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK   0x00000400L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata        0x00000400L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK      0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q           0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK      0x00001000L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q           0x00001000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK       0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q            0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK       0x00004000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q            0x00004000L
+#define VGT_DEBUG_REG17__to_second_reg_q_MASK              0x00008000L
+#define VGT_DEBUG_REG17__to_second_reg_q                   0x00008000L
+#define VGT_DEBUG_REG17__roll_over_msk_q_MASK              0x00010000L
+#define VGT_DEBUG_REG17__roll_over_msk_q                   0x00010000L
+#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK                0x00fe0000L
+#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK                0x7f000000L
+#define VGT_DEBUG_REG17__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG17__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK      0x0000003fL
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK      0x00000fc0L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK   0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re        0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK  0x00006000L
+#define VGT_DEBUG_REG18__dma_mem_full_MASK                 0x00008000L
+#define VGT_DEBUG_REG18__dma_mem_full                      0x00008000L
+#define VGT_DEBUG_REG18__dma_ram_re_MASK                   0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_re                        0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_we_MASK                   0x00020000L
+#define VGT_DEBUG_REG18__dma_ram_we                        0x00020000L
+#define VGT_DEBUG_REG18__dma_mem_empty_MASK                0x00040000L
+#define VGT_DEBUG_REG18__dma_mem_empty                     0x00040000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK         0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re              0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK         0x00100000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we              0x00100000L
+#define VGT_DEBUG_REG18__bin_mem_full_MASK                 0x00200000L
+#define VGT_DEBUG_REG18__bin_mem_full                      0x00200000L
+#define VGT_DEBUG_REG18__bin_ram_we_MASK                   0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_we                        0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_re_MASK                   0x00800000L
+#define VGT_DEBUG_REG18__bin_ram_re                        0x00800000L
+#define VGT_DEBUG_REG18__bin_mem_empty_MASK                0x01000000L
+#define VGT_DEBUG_REG18__bin_mem_empty                     0x01000000L
+#define VGT_DEBUG_REG18__start_bin_req_MASK                0x02000000L
+#define VGT_DEBUG_REG18__start_bin_req                     0x02000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK          0x04000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used               0x04000000L
+#define VGT_DEBUG_REG18__dma_req_xfer_MASK                 0x08000000L
+#define VGT_DEBUG_REG18__dma_req_xfer                      0x08000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req_MASK           0x10000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req                0x10000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req_MASK           0x20000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req                0x20000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK  0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable       0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK         0x00000001L
+#define VGT_DEBUG_REG20__prim_side_indx_valid              0x00000001L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK         0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty              0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK            0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_re                 0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK            0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_we                 0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK          0x00000010L
+#define VGT_DEBUG_REG20__indx_side_fifo_full               0x00000010L
+#define VGT_DEBUG_REG20__prim_buffer_empty_MASK            0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_empty                 0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_re_MASK               0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_re                    0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_we_MASK               0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_we                    0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_full_MASK             0x00000100L
+#define VGT_DEBUG_REG20__prim_buffer_full                  0x00000100L
+#define VGT_DEBUG_REG20__indx_buffer_empty_MASK            0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_empty                 0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_re_MASK               0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_re                    0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_we_MASK               0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_we                    0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_full_MASK             0x00001000L
+#define VGT_DEBUG_REG20__indx_buffer_full                  0x00001000L
+#define VGT_DEBUG_REG20__hold_prim_MASK                    0x00002000L
+#define VGT_DEBUG_REG20__hold_prim                         0x00002000L
+#define VGT_DEBUG_REG20__sent_cnt_MASK                     0x0003c000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK          0x00040000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector               0x00040000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK         0x00080000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim              0x00080000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK         0x00100000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim              0x00100000L
+#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK     0x03e00000L
+#define VGT_DEBUG_REG20__out_trigger_MASK                  0x04000000L
+#define VGT_DEBUG_REG20__out_trigger                       0x04000000L
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK    0x00000001L
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector         0x00000001L
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK   0x0000000eL
+#define VGT_DEBUG_REG21__alloc_counter_q_MASK              0x00000070L
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK      0x00000380L
+#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK            0x00003c00L
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK      0x0003c000L
+#define VGT_DEBUG_REG21__new_packet_q_MASK                 0x00040000L
+#define VGT_DEBUG_REG21__new_packet_q                      0x00040000L
+#define VGT_DEBUG_REG21__new_allocate_q_MASK               0x00080000L
+#define VGT_DEBUG_REG21__new_allocate_q                    0x00080000L
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK      0x00300000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK         0x00400000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q              0x00400000L
+#define VGT_DEBUG_REG21__insert_null_prim_MASK             0x00800000L
+#define VGT_DEBUG_REG21__insert_null_prim                  0x00800000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK        0x01000000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux             0x01000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK        0x02000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux             0x02000000L
+#define VGT_DEBUG_REG21__buffered_thread_size_MASK         0x04000000L
+#define VGT_DEBUG_REG21__buffered_thread_size              0x04000000L
+#define VGT_DEBUG_REG21__out_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG21__out_trigger                       0x80000000L
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC_MASK                          0xffffffffL
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC_MASK                          0xffffffffL
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE_MASK                 0x00000001L
+#define TC_CNTL_STATUS__L2_INVALIDATE                      0x00000001L
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK                0x000c0000L
+#define TC_CNTL_STATUS__TC_BUSY_MASK                       0x80000000L
+#define TC_CNTL_STATUS__TC_BUSY                            0x80000000L
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK                 0x00000100L
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN                      0x00000100L
+#define TCM_CHICKEN__SPARE_MASK                            0xfffffe00L
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK            0x00000007L
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK            0x00000038L
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK               0x00000001L
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY                    0x00000001L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK             0x00000002L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY                  0x00000002L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK          0x00000004L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY               0x00000004L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK          0x00000008L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY               0x00000008L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK         0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY              0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK           0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY                0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK              0x00000040L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY                   0x00000040L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK        0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY             0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK          0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY               0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK             0x00000400L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY                  0x00000400L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK             0x00001000L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY                  0x00001000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK          0x00002000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY               0x00002000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK            0x00004000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY                 0x00004000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK               0x00008000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY                    0x00008000L
+#define TPC_CNTL_STATUS__TF_TW_RTS_MASK                    0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_RTS                         0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK              0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS                   0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_RTR_MASK                    0x00080000L
+#define TPC_CNTL_STATUS__TF_TW_RTR                         0x00080000L
+#define TPC_CNTL_STATUS__TW_TA_RTS_MASK                    0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_RTS                         0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK                 0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS                      0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK               0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS                    0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_RTR_MASK                    0x00800000L
+#define TPC_CNTL_STATUS__TW_TA_RTR                         0x00800000L
+#define TPC_CNTL_STATUS__TA_TB_RTS_MASK                    0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_RTS                         0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK                 0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS                      0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR_MASK                    0x08000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR                         0x08000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS_MASK                    0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS                         0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK            0x20000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN                 0x20000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK                    0x40000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC                         0x40000000L
+#define TPC_CNTL_STATUS__TPC_BUSY_MASK                     0x80000000L
+#define TPC_CNTL_STATUS__TPC_BUSY                          0x80000000L
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL_MASK                          0x00000003L
+#define TPC_DEBUG0__IC_CTR_MASK                            0x0000000cL
+#define TPC_DEBUG0__WALKER_CNTL_MASK                       0x000000f0L
+#define TPC_DEBUG0__ALIGNER_CNTL_MASK                      0x00000700L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK               0x00001000L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID                    0x00001000L
+#define TPC_DEBUG0__WALKER_STATE_MASK                      0x03ff0000L
+#define TPC_DEBUG0__ALIGNER_STATE_MASK                     0x0c000000L
+#define TPC_DEBUG0__REG_CLK_EN_MASK                        0x20000000L
+#define TPC_DEBUG0__REG_CLK_EN                             0x20000000L
+#define TPC_DEBUG0__TPC_CLK_EN_MASK                        0x40000000L
+#define TPC_DEBUG0__TPC_CLK_EN                             0x40000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK                      0x80000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP                           0x80000000L
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED_MASK                            0x00000001L
+#define TPC_DEBUG1__UNUSED                                 0x00000001L
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION_MASK                  0x00000001L
+#define TPC_CHICKEN__BLEND_PRECISION                       0x00000001L
+#define TPC_CHICKEN__SPARE_MASK                            0xfffffffeL
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK                0x00000001L
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY                     0x00000001L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK                  0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY                       0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK             0x00000004L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY                  0x00000004L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK                 0x00000008L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY                      0x00000008L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK           0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY                0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK              0x00000020L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY                   0x00000020L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK              0x00000040L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY                   0x00000040L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK              0x00000080L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY                   0x00000080L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK                0x00000100L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY                     0x00000100L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK             0x00000200L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY                  0x00000200L
+#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK                   0x00000400L
+#define TP0_CNTL_STATUS__TP_TT_BUSY                        0x00000400L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK              0x00000800L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY                   0x00000800L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK                0x00001000L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY                     0x00001000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK             0x00002000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY                  0x00002000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK               0x00004000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY                    0x00004000L
+#define TP0_CNTL_STATUS__IN_LC_RTS_MASK                    0x00010000L
+#define TP0_CNTL_STATUS__IN_LC_RTS                         0x00010000L
+#define TP0_CNTL_STATUS__LC_LA_RTS_MASK                    0x00020000L
+#define TP0_CNTL_STATUS__LC_LA_RTS                         0x00020000L
+#define TP0_CNTL_STATUS__LA_FL_RTS_MASK                    0x00040000L
+#define TP0_CNTL_STATUS__LA_FL_RTS                         0x00040000L
+#define TP0_CNTL_STATUS__FL_TA_RTS_MASK                    0x00080000L
+#define TP0_CNTL_STATUS__FL_TA_RTS                         0x00080000L
+#define TP0_CNTL_STATUS__TA_FA_RTS_MASK                    0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_RTS                         0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK                 0x00200000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS                      0x00200000L
+#define TP0_CNTL_STATUS__FA_AL_RTS_MASK                    0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_RTS                         0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK                 0x00800000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS                      0x00800000L
+#define TP0_CNTL_STATUS__AL_TF_RTS_MASK                    0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_RTS                         0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK                 0x02000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS                      0x02000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS_MASK                    0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS                         0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK                 0x08000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS                      0x08000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS_MASK                    0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS                         0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK               0x20000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET                    0x20000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS_MASK                    0x40000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS                         0x40000000L
+#define TP0_CNTL_STATUS__TP_BUSY_MASK                      0x80000000L
+#define TP0_CNTL_STATUS__TP_BUSY                           0x80000000L
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL_MASK                         0x00000003L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK                     0x00000008L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP                          0x00000008L
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK               0x001ffff0L
+#define TP0_DEBUG__REG_CLK_EN_MASK                         0x00200000L
+#define TP0_DEBUG__REG_CLK_EN                              0x00200000L
+#define TP0_DEBUG__PERF_CLK_EN_MASK                        0x00400000L
+#define TP0_DEBUG__PERF_CLK_EN                             0x00400000L
+#define TP0_DEBUG__TP_CLK_EN_MASK                          0x00800000L
+#define TP0_DEBUG__TP_CLK_EN                               0x00800000L
+#define TP0_DEBUG__Q_WALKER_CNTL_MASK                      0x0f000000L
+#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK                     0x70000000L
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE_MASK                          0x00000001L
+#define TP0_CHICKEN__TT_MODE                               0x00000001L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK              0x00000002L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE                   0x00000002L
+#define TP0_CHICKEN__SPARE_MASK                            0xfffffffcL
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr_MASK                      0x00000040L
+#define TCF_DEBUG__not_MH_TC_rtr                           0x00000040L
+#define TCF_DEBUG__TC_MH_send_MASK                         0x00000080L
+#define TCF_DEBUG__TC_MH_send                              0x00000080L
+#define TCF_DEBUG__not_FG0_rtr_MASK                        0x00000100L
+#define TCF_DEBUG__not_FG0_rtr                             0x00000100L
+#define TCF_DEBUG__not_TCB_TCO_rtr_MASK                    0x00001000L
+#define TCF_DEBUG__not_TCB_TCO_rtr                         0x00001000L
+#define TCF_DEBUG__TCB_ff_stall_MASK                       0x00002000L
+#define TCF_DEBUG__TCB_ff_stall                            0x00002000L
+#define TCF_DEBUG__TCB_miss_stall_MASK                     0x00004000L
+#define TCF_DEBUG__TCB_miss_stall                          0x00004000L
+#define TCF_DEBUG__TCA_TCB_stall_MASK                      0x00008000L
+#define TCF_DEBUG__TCA_TCB_stall                           0x00008000L
+#define TCF_DEBUG__PF0_stall_MASK                          0x00010000L
+#define TCF_DEBUG__PF0_stall                               0x00010000L
+#define TCF_DEBUG__TP0_full_MASK                           0x00100000L
+#define TCF_DEBUG__TP0_full                                0x00100000L
+#define TCF_DEBUG__TPC_full_MASK                           0x01000000L
+#define TCF_DEBUG__TPC_full                                0x01000000L
+#define TCF_DEBUG__not_TPC_rtr_MASK                        0x02000000L
+#define TCF_DEBUG__not_TPC_rtr                             0x02000000L
+#define TCF_DEBUG__tca_state_rts_MASK                      0x04000000L
+#define TCF_DEBUG__tca_state_rts                           0x04000000L
+#define TCF_DEBUG__tca_rts_MASK                            0x08000000L
+#define TCF_DEBUG__tca_rts                                 0x08000000L
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full_MASK                      0x00000001L
+#define TCA_FIFO_DEBUG__tp0_full                           0x00000001L
+#define TCA_FIFO_DEBUG__tpc_full_MASK                      0x00000010L
+#define TCA_FIFO_DEBUG__tpc_full                           0x00000010L
+#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK                 0x00000020L
+#define TCA_FIFO_DEBUG__load_tpc_fifo                      0x00000020L
+#define TCA_FIFO_DEBUG__load_tp_fifos_MASK                 0x00000040L
+#define TCA_FIFO_DEBUG__load_tp_fifos                      0x00000040L
+#define TCA_FIFO_DEBUG__FW_full_MASK                       0x00000080L
+#define TCA_FIFO_DEBUG__FW_full                            0x00000080L
+#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK                   0x00000100L
+#define TCA_FIFO_DEBUG__not_FW_rtr0                        0x00000100L
+#define TCA_FIFO_DEBUG__FW_rts0_MASK                       0x00001000L
+#define TCA_FIFO_DEBUG__FW_rts0                            0x00001000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK                0x00010000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr                     0x00010000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK                    0x00020000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts                         0x00020000L
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK            0x00000001L
+#define TCA_PROBE_DEBUG__ProbeFilter_stall                 0x00000001L
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts_MASK               0x00001000L
+#define TCA_TPC_DEBUG__captue_state_rts                    0x00001000L
+#define TCA_TPC_DEBUG__capture_tca_rts_MASK                0x00002000L
+#define TCA_TPC_DEBUG__capture_tca_rts                     0x00002000L
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512_MASK                     0x00000001L
+#define TCB_CORE_DEBUG__access512                          0x00000001L
+#define TCB_CORE_DEBUG__tiled_MASK                         0x00000002L
+#define TCB_CORE_DEBUG__tiled                              0x00000002L
+#define TCB_CORE_DEBUG__opcode_MASK                        0x00000070L
+#define TCB_CORE_DEBUG__format_MASK                        0x00003f00L
+#define TCB_CORE_DEBUG__sector_format_MASK                 0x001f0000L
+#define TCB_CORE_DEBUG__sector_format512_MASK              0x07000000L
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG0_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG0_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG0_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG0_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG0_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG1_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG1_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG1_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG1_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG1_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG2_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG2_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG2_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG2_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG2_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG3_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG3_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG3_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG3_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG3_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done      0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left    0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q   0x10000000L
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK     0x00000030L
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK      0x000000c0L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK     0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left          0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK     0x00007000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK              0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy                   0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK  0x000f0000L
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK        0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts             0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK         0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts              0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK      0x0000fff0L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK   0x001f0000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK               0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy                    0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK           0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy                0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK            0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy                 0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK           0x0c000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK            0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q                 0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK            0x40000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR                 0x40000000L
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty_MASK                       0x00010000L
+#define TCD_INPUT0_DEBUG__empty                            0x00010000L
+#define TCD_INPUT0_DEBUG__full_MASK                        0x00020000L
+#define TCD_INPUT0_DEBUG__full                             0x00020000L
+#define TCD_INPUT0_DEBUG__valid_q1_MASK                    0x00100000L
+#define TCD_INPUT0_DEBUG__valid_q1                         0x00100000L
+#define TCD_INPUT0_DEBUG__cnt_q1_MASK                      0x00600000L
+#define TCD_INPUT0_DEBUG__last_send_q1_MASK                0x00800000L
+#define TCD_INPUT0_DEBUG__last_send_q1                     0x00800000L
+#define TCD_INPUT0_DEBUG__ip_send_MASK                     0x01000000L
+#define TCD_INPUT0_DEBUG__ip_send                          0x01000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK              0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send                   0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK                  0x04000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy                       0x04000000L
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK        0x00000003L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK            0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8                 0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK        0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send             0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK             0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send                  0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK                 0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall                      0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK                0x00000040L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate                     0x00000040L
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK               0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate                    0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK           0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr                0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK             0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr                  0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send      0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK  0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts       0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK    0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send         0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send     0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK     0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send          0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK        0x20000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send             0x20000000L
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK                  0x00000010L
+#define TCD_DXTC_ARB_DEBUG__n0_stall                       0x00000010L
+#define TCD_DXTC_ARB_DEBUG__pstate_MASK                    0x00000020L
+#define TCD_DXTC_ARB_DEBUG__pstate                         0x00000020L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK      0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send           0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK            0x00000180L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK         0x00000e00L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK      0x0003f000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK         0x3ffc0000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK           0x40000000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send                0x40000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK           0x80000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types                0x80000000L
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK     0x00000400L
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr          0x00000400L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK     0x00000800L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr          0x00000800L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK           0x00020000L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr                0x00020000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK         0x00040000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr              0x00040000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK            0x00080000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr                 0x00080000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK            0x80000000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr                 0x80000000L
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK            0x00000020L
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR                 0x00000020L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK             0x00000040L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR                  0x00000040L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK         0x00000080L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d              0x00000080L
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK         0x000000ffL
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK         0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample              0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK                   0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr                        0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK                   0x00000400L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts                        0x00000400L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK        0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample             0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK                  0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr                       0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK                  0x00002000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts                       0x00002000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK             0x00010000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q                  0x00010000L
+#define TCO_QUAD0_DEBUG0__read_cache_q_MASK                0x01000000L
+#define TCO_QUAD0_DEBUG0__read_cache_q                     0x01000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK              0x02000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR                   0x02000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK    0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3         0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK    0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2         0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK    0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1         0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK    0x20000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0         0x20000000L
+#define TCO_QUAD0_DEBUG0__busy_MASK                        0x40000000L
+#define TCO_QUAD0_DEBUG0__busy                             0x40000000L
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy_MASK                   0x00000001L
+#define TCO_QUAD0_DEBUG1__fifo_busy                        0x00000001L
+#define TCO_QUAD0_DEBUG1__empty_MASK                       0x00000002L
+#define TCO_QUAD0_DEBUG1__empty                            0x00000002L
+#define TCO_QUAD0_DEBUG1__full_MASK                        0x00000004L
+#define TCO_QUAD0_DEBUG1__full                             0x00000004L
+#define TCO_QUAD0_DEBUG1__write_enable_MASK                0x00000008L
+#define TCO_QUAD0_DEBUG1__write_enable                     0x00000008L
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK              0x000007f0L
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK               0x0003f800L
+#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK             0x00100000L
+#define TCO_QUAD0_DEBUG1__cache_read_busy                  0x00100000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK           0x00200000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy                0x00200000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK             0x00400000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy                  0x00400000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK          0x00800000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy               0x00800000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK               0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d                    0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK               0x02000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q                    0x02000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK                   0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr                        0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK                   0x08000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts                        0x08000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK                  0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr                       0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK                  0x20000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts                       0x20000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK            0x40000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc                 0x40000000L
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK                0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC                     0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK               0x000007f0L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK               0x0007f000L
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK     0x00000003L
+#define SQ_FLOW_CONTROL__ONE_THREAD_MASK                   0x00000010L
+#define SQ_FLOW_CONTROL__ONE_THREAD                        0x00000010L
+#define SQ_FLOW_CONTROL__ONE_ALU_MASK                      0x00000100L
+#define SQ_FLOW_CONTROL__ONE_ALU                           0x00000100L
+#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK                   0x0000f000L
+#define SQ_FLOW_CONTROL__NO_PV_PS_MASK                     0x00010000L
+#define SQ_FLOW_CONTROL__NO_PV_PS                          0x00010000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK                 0x00020000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT                      0x00020000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK            0x00040000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE                 0x00040000L
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK   0x00180000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK        0x00200000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY             0x00200000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK       0x00400000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY            0x00400000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK                 0x00800000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT                      0x00800000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK                 0x01000000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT                      0x01000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK             0x02000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY                  0x02000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK  0x04000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION       0x04000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK      0x08000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC           0x08000000L
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK        0x00000fffL
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK        0x0fff0000L
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK     0x01ff0000L
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT_MASK                     0x000000ffL
+#define SQ_EO_RT__EO_TSTATE_RT_MASK                        0x00ff0000L
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK                 0x000007ffL
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK                 0x000ff000L
+#define SQ_DEBUG_MISC__DB_READ_CTX_MASK                    0x00100000L
+#define SQ_DEBUG_MISC__DB_READ_CTX                         0x00100000L
+#define SQ_DEBUG_MISC__RESERVED_MASK                       0x00600000L
+#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK                 0x01800000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK                0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0                     0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK                0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1                     0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK                0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2                     0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK                0x10000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3                     0x10000000L
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK              0x000000ffL
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK         0x0000ff00L
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK        0x00ff0000L
+#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK                 0xff000000L
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK        0x000000ffL
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK        0x00000007L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK          0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN               0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK        0x00000070L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK          0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN               0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK              0x0003ff00L
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK       0x00000007L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK         0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN              0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK       0x00000070L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK         0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN              0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK             0x0003ff00L
+#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK              0x000c0000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK  0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL       0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK  0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL       0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L
+
+// SQ_VS_WATCHDOG_TIMER
+#define SQ_VS_WATCHDOG_TIMER__ENABLE_MASK                  0x00000001L
+#define SQ_VS_WATCHDOG_TIMER__ENABLE                       0x00000001L
+#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK           0xfffffffeL
+
+// SQ_PS_WATCHDOG_TIMER
+#define SQ_PS_WATCHDOG_TIMER__ENABLE_MASK                  0x00000001L
+#define SQ_PS_WATCHDOG_TIMER__ENABLE                       0x00000001L
+#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK           0xfffffffeL
+
+// SQ_INT_CNTL
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK_MASK                 0x00000001L
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK                      0x00000001L
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK_MASK                 0x00000002L
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK                      0x00000002L
+
+// SQ_INT_STATUS
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT_MASK            0x00000001L
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT                 0x00000001L
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT_MASK            0x00000002L
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT                 0x00000002L
+
+// SQ_INT_ACK
+#define SQ_INT_ACK__PS_WATCHDOG_ACK_MASK                   0x00000001L
+#define SQ_INT_ACK__PS_WATCHDOG_ACK                        0x00000001L
+#define SQ_INT_ACK__VS_WATCHDOG_ACK_MASK                   0x00000002L
+#define SQ_INT_ACK__VS_WATCHDOG_ACK                        0x00000002L
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK                 0x00000007L
+#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK                  0x00000008L
+#define SQ_DEBUG_INPUT_FSM__RESERVED                       0x00000008L
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK                 0x000000f0L
+#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK                   0x00000700L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1                      0x00000800L
+#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK                     0x00007000L
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK             0x000f8000L
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK               0x0ff00000L
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK             0x000000e0L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK             0x0000e000L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK  0x00030000L
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK  0x000c0000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK  0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE       0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK  0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE       0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK  0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE       0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK  0x00800000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE       0x00800000L
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP_MASK                        0x00000007L
+#define SQ_DEBUG_TP_FSM__RESERVED0_MASK                    0x00000008L
+#define SQ_DEBUG_TP_FSM__RESERVED0                         0x00000008L
+#define SQ_DEBUG_TP_FSM__CF_TP_MASK                        0x000000f0L
+#define SQ_DEBUG_TP_FSM__IF_TP_MASK                        0x00000700L
+#define SQ_DEBUG_TP_FSM__RESERVED1_MASK                    0x00000800L
+#define SQ_DEBUG_TP_FSM__RESERVED1                         0x00000800L
+#define SQ_DEBUG_TP_FSM__TIS_TP_MASK                       0x00003000L
+#define SQ_DEBUG_TP_FSM__RESERVED2_MASK                    0x0000c000L
+#define SQ_DEBUG_TP_FSM__GS_TP_MASK                        0x00030000L
+#define SQ_DEBUG_TP_FSM__RESERVED3_MASK                    0x000c0000L
+#define SQ_DEBUG_TP_FSM__FCR_TP_MASK                       0x00300000L
+#define SQ_DEBUG_TP_FSM__RESERVED4_MASK                    0x00c00000L
+#define SQ_DEBUG_TP_FSM__FCS_TP_MASK                       0x03000000L
+#define SQ_DEBUG_TP_FSM__RESERVED5_MASK                    0x0c000000L
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK                    0x70000000L
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK             0x0000000fL
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK           0x00000ff0L
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK              0x00007000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK                  0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED                       0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK       0x003f0000L
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK              0x00000001L
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER                   0x00000001L
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK                0x0000001eL
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK            0x00000020L
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR                 0x00000020L
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK           0x000001c0L
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK                0x00003e00L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK                 0x00004000L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT                      0x00004000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK          0x00008000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON               0x00008000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK                   0x00010000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY                        0x00010000L
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK               0x0ffe0000L
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_VTX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_VTX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_VTX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_PIX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_PIX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_PIX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN     0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN     0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK     0x60000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC    0x80000000L
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK             0x0000000fL
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK                 0x000000f0L
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK                 0x00000f00L
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK          0x0000f000L
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK           0x000f0000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK              0x00100000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL                   0x00100000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK                     0x00200000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q                          0x00200000L
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK                0x0000ffffL
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK     0xffffffffL
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK       0xffffffffL
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK               0x0000003fL
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK                   0x00000fc0L
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK                   0x0007f000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK          0x01f80000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK            0x7e000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY_MASK                       0x80000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY                            0x80000000L
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK   0xffffffffL
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL_MASK          0x00000040L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL               0x00000040L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK    0x00000080L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP         0x00000080L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL_MASK          0x00004000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL               0x00004000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK             0x00008000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA                  0x00008000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK          0x000f0000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK          0x00f00000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK            0x01000000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP                 0x01000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK            0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP                 0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK           0xfc000000L
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK         0x00000003L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK         0x0000000cL
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK         0x00000030L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK         0x000000c0L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK         0x00000300L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK         0x00000c00L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK         0x00003000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK         0x0000c000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK         0x00030000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK         0x000c0000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK         0x00300000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK         0x00c00000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK           0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD                0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK           0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD                0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK           0x04000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD                0x04000000L
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK             0x18000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK           0x20000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR                0x20000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK         0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS              0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK         0x80000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS              0x80000000L
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK            0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C                 0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK           0x00000080L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C                0x00000080L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK            0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B                 0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK           0x00008000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B                0x00008000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK           0x003f0000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK            0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A                 0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK           0x00800000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A                0x00800000L
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK           0x1f000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK               0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL                    0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK               0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL                    0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK               0x80000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK             0x000001ffL
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK            0x00000e00L
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK               0x00007000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK               0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD                    0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK         0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0              0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0            0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK         0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1              0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK       0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1            0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK         0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2              0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK       0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2            0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK         0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3              0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK       0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3            0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK         0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4              0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK       0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4            0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK         0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5              0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK       0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5            0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK           0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0                0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK           0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1                0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK           0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2                0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK           0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3                0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK           0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4                0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK           0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5                0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK           0x000003fcL
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK           0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION                0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK             0x01ff0000L
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK            0x0e000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK               0x70000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK               0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK         0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0              0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0            0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK         0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1              0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK       0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1            0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK         0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2              0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK       0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2            0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK         0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3              0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK       0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3            0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK         0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4              0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK       0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4            0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK         0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5              0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK       0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5            0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK           0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0                0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK           0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1                0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK           0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2                0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK           0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3                0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK           0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4                0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK           0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5                0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK           0x03fc0000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK           0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION                0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK             0x000003ffL
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK          0x0000fc00L
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK             0x001f0000L
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK          0xffe00000L
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK          0x000007ffL
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK             0x03ff0000L
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK          0xfc000000L
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK             0x0000001fL
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK            0x07ffffe0L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK         0x000003ffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK      0x00001c00L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK      0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL           0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK  0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP       0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK      0xffff8000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK      0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0           0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION            0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK       0x000003fcL
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK       0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION            0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK    0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE         0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK          0x0000f000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK         0x03ff0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK      0x1c000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK      0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL           0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK      0xc0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK        0x0001ffffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION            0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK       0x03fc0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK       0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION            0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK    0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE         0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK          0xf0000000L
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK               0x0000000fL
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK           0xfffffff0L
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK         0x000000ffL
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK          0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL               0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK      0x00000600L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK         0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE              0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK             0x0000f000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK               0x000f0000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK         0xfff00000L
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK           0x00ffffffL
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK          0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL               0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK      0x06000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK         0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE              0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK             0xf0000000L
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK     0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY          0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK      0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM           0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK            0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK            0x30000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK            0xc0000000L
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK           0x00003000L
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK           0x0000c000L
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK           0x00030000L
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK         0x001c0000L
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK     0x00e00000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK       0x03000000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK       0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK         0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD              0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK          0x60000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK    0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS         0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK      0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION           0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK             0x000001fcL
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK               0x0000fe00L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK             0x001f0000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK             0x03e00000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK             0x7c000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK          0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE               0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK      0x06000000L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK              0xc0000000L
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK      0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL           0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK       0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL            0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK   0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL        0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK          0x003f0000L
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK       0x3f800000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK               0x000000ffL
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK               0x00ff0000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED_MASK                            0xffffffffL
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN_MASK                          0xffffffffL
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE_MASK                           0xffffffffL
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA_MASK                          0xffffffffL
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE_MASK                             0xffffffffL
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE_MASK                    0x00000001L
+#define SQ_CONSTANT_VFETCH_0__TYPE                         0x00000001L
+#define SQ_CONSTANT_VFETCH_0__STATE_MASK                   0x00000002L
+#define SQ_CONSTANT_VFETCH_0__STATE                        0x00000002L
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK            0xfffffffcL
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK             0x00000003L
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK           0xfffffffcL
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE_MASK                         0xffffffffL
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE_MASK                         0xffffffffL
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK                 0x000000ffL
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK                 0x0000ff00L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK                 0x00ff0000L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK                 0xff000000L
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK                     0x000000ffL
+#define SQ_CF_LOOP__CF_LOOP_START_MASK                     0x0000ff00L
+#define SQ_CF_LOOP__CF_LOOP_STEP_MASK                      0x00ff0000L
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED_MASK                         0xffffffffL
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN_MASK                       0xffffffffL
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE_MASK                        0xffffffffL
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA_MASK                       0xffffffffL
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE_MASK                          0xffffffffL
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK              0x000000ffL
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK              0x0000ff00L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK              0x00ff0000L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK              0xff000000L
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK                  0x000000ffL
+#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK                  0x0000ff00L
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK                   0x00ff0000L
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_VS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_PS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK                0x000007ffL
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK                0x007ff000L
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK             0x0000ffffL
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK        0xffff0000L
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK                   0x0000003fL
+#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK                   0x00003f00L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK                  0x00010000L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE                       0x00010000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK                  0x00020000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE                       0x00020000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK                    0x00040000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN                         0x00040000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK                0x00080000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX                     0x00080000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK              0x00f00000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK               0x07000000L
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK               0x78000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK                0x80000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX                     0x80000000L
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK                   0x0000000fL
+#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK                   0x000000f0L
+#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK                   0x00000f00L
+#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK                   0x0000f000L
+#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK                   0x000f0000L
+#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK                   0x00f00000L
+#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK                   0x0f000000L
+#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK                   0xf0000000L
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK                   0x0000000fL
+#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK                   0x000000f0L
+#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK                  0x00000f00L
+#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK                  0x0000f000L
+#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK                  0x000f0000L
+#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK                  0x00f00000L
+#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK                  0x0f000000L
+#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK                  0xf0000000L
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_VS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_PS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK           0x00000001L
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE                0x00000001L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK          0x00000002L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY               0x00000002L
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK               0x0000000cL
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK                0x0000ff00L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK              0x00010000L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF                   0x00010000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK               0x00020000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE                    0x00020000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK                 0x00040000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL                      0x00040000L
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE_MASK                        0x00000007L
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK                   0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_ON                        0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK                0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK                     0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK                 0x0007ff00L
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK                0xff000000L
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK                    0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_PIX                         0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK                    0x00000002L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX                         0x00000002L
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK                0x0000ff00L
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK                0x07ff0000L
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK            0x0000003fL
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK      0x00000040L
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY           0x00000040L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK              0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE                   0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK         0x00000100L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE              0x00000100L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK             0x00000200L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL                  0x00000200L
+#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK                  0x00001c00L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK          0x00002000L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE               0x00002000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK         0x00004000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE              0x00004000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK     0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE          0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK            0x003f0000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK             0x00400000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE                  0x00400000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK            0x00800000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE                 0x00800000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK             0x01000000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE                  0x01000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK             0x02000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE                  0x02000000L
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE_MASK             0x04000000L
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE                  0x04000000L
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK                  0x00000007L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK               0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1                    0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK                  0x00000070L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK               0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2                    0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK                 0x00000700L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3_MASK               0x00000800L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3                    0x00000800L
+#define MH_CLNT_AXI_ID_REUSE__PAw_ID_MASK                  0x00007000L
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK             0x00000001L
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR                  0x00000001L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK            0x00000002L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR                 0x00000002L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK             0x00000004L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT                  0x00000004L
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK           0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR                0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK          0x00000002L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR               0x00000002L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK           0x00000004L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT                0x00000004L
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK            0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR                 0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK           0x00000002L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR                0x00000002L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK            0x00000004L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT                 0x00000004L
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID_MASK                     0x00000007L
+#define MH_AXI_ERROR__AXI_READ_ERROR_MASK                  0x00000008L
+#define MH_AXI_ERROR__AXI_READ_ERROR                       0x00000008L
+#define MH_AXI_ERROR__AXI_WRITE_ID_MASK                    0x00000070L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK                 0x00000080L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR                      0x00000080L
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX_MASK                          0x0000003fL
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA_MASK                           0xffffffffL
+
+// MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL__AXI_HALT_MASK                 0x00000001L
+#define MH_AXI_HALT_CONTROL__AXI_HALT                      0x00000001L
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY_MASK                       0x00000001L
+#define MH_DEBUG_REG00__MH_BUSY                            0x00000001L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK             0x00000002L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING                  0x00000002L
+#define MH_DEBUG_REG00__CP_REQUEST_MASK                    0x00000004L
+#define MH_DEBUG_REG00__CP_REQUEST                         0x00000004L
+#define MH_DEBUG_REG00__VGT_REQUEST_MASK                   0x00000008L
+#define MH_DEBUG_REG00__VGT_REQUEST                        0x00000008L
+#define MH_DEBUG_REG00__TC_REQUEST_MASK                    0x00000010L
+#define MH_DEBUG_REG00__TC_REQUEST                         0x00000010L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK                  0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY                       0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_FULL_MASK                   0x00000040L
+#define MH_DEBUG_REG00__TC_CAM_FULL                        0x00000040L
+#define MH_DEBUG_REG00__TCD_EMPTY_MASK                     0x00000080L
+#define MH_DEBUG_REG00__TCD_EMPTY                          0x00000080L
+#define MH_DEBUG_REG00__TCD_FULL_MASK                      0x00000100L
+#define MH_DEBUG_REG00__TCD_FULL                           0x00000100L
+#define MH_DEBUG_REG00__RB_REQUEST_MASK                    0x00000200L
+#define MH_DEBUG_REG00__RB_REQUEST                         0x00000200L
+#define MH_DEBUG_REG00__PA_REQUEST_MASK                    0x00000400L
+#define MH_DEBUG_REG00__PA_REQUEST                         0x00000400L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK               0x00000800L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE                    0x00000800L
+#define MH_DEBUG_REG00__ARQ_EMPTY_MASK                     0x00001000L
+#define MH_DEBUG_REG00__ARQ_EMPTY                          0x00001000L
+#define MH_DEBUG_REG00__ARQ_FULL_MASK                      0x00002000L
+#define MH_DEBUG_REG00__ARQ_FULL                           0x00002000L
+#define MH_DEBUG_REG00__WDB_EMPTY_MASK                     0x00004000L
+#define MH_DEBUG_REG00__WDB_EMPTY                          0x00004000L
+#define MH_DEBUG_REG00__WDB_FULL_MASK                      0x00008000L
+#define MH_DEBUG_REG00__WDB_FULL                           0x00008000L
+#define MH_DEBUG_REG00__AXI_AVALID_MASK                    0x00010000L
+#define MH_DEBUG_REG00__AXI_AVALID                         0x00010000L
+#define MH_DEBUG_REG00__AXI_AREADY_MASK                    0x00020000L
+#define MH_DEBUG_REG00__AXI_AREADY                         0x00020000L
+#define MH_DEBUG_REG00__AXI_ARVALID_MASK                   0x00040000L
+#define MH_DEBUG_REG00__AXI_ARVALID                        0x00040000L
+#define MH_DEBUG_REG00__AXI_ARREADY_MASK                   0x00080000L
+#define MH_DEBUG_REG00__AXI_ARREADY                        0x00080000L
+#define MH_DEBUG_REG00__AXI_WVALID_MASK                    0x00100000L
+#define MH_DEBUG_REG00__AXI_WVALID                         0x00100000L
+#define MH_DEBUG_REG00__AXI_WREADY_MASK                    0x00200000L
+#define MH_DEBUG_REG00__AXI_WREADY                         0x00200000L
+#define MH_DEBUG_REG00__AXI_RVALID_MASK                    0x00400000L
+#define MH_DEBUG_REG00__AXI_RVALID                         0x00400000L
+#define MH_DEBUG_REG00__AXI_RREADY_MASK                    0x00800000L
+#define MH_DEBUG_REG00__AXI_RREADY                         0x00800000L
+#define MH_DEBUG_REG00__AXI_BVALID_MASK                    0x01000000L
+#define MH_DEBUG_REG00__AXI_BVALID                         0x01000000L
+#define MH_DEBUG_REG00__AXI_BREADY_MASK                    0x02000000L
+#define MH_DEBUG_REG00__AXI_BREADY                         0x02000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK                  0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ                       0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK                  0x08000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK                       0x08000000L
+#define MH_DEBUG_REG00__AXI_RDY_ENA_MASK                   0x10000000L
+#define MH_DEBUG_REG00__AXI_RDY_ENA                        0x10000000L
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q_MASK                     0x00000001L
+#define MH_DEBUG_REG01__CP_SEND_q                          0x00000001L
+#define MH_DEBUG_REG01__CP_RTR_q_MASK                      0x00000002L
+#define MH_DEBUG_REG01__CP_RTR_q                           0x00000002L
+#define MH_DEBUG_REG01__CP_WRITE_q_MASK                    0x00000004L
+#define MH_DEBUG_REG01__CP_WRITE_q                         0x00000004L
+#define MH_DEBUG_REG01__CP_TAG_q_MASK                      0x00000038L
+#define MH_DEBUG_REG01__CP_BLEN_q_MASK                     0x00000040L
+#define MH_DEBUG_REG01__CP_BLEN_q                          0x00000040L
+#define MH_DEBUG_REG01__VGT_SEND_q_MASK                    0x00000080L
+#define MH_DEBUG_REG01__VGT_SEND_q                         0x00000080L
+#define MH_DEBUG_REG01__VGT_RTR_q_MASK                     0x00000100L
+#define MH_DEBUG_REG01__VGT_RTR_q                          0x00000100L
+#define MH_DEBUG_REG01__VGT_TAG_q_MASK                     0x00000200L
+#define MH_DEBUG_REG01__VGT_TAG_q                          0x00000200L
+#define MH_DEBUG_REG01__TC_SEND_q_MASK                     0x00000400L
+#define MH_DEBUG_REG01__TC_SEND_q                          0x00000400L
+#define MH_DEBUG_REG01__TC_RTR_q_MASK                      0x00000800L
+#define MH_DEBUG_REG01__TC_RTR_q                           0x00000800L
+#define MH_DEBUG_REG01__TC_BLEN_q_MASK                     0x00001000L
+#define MH_DEBUG_REG01__TC_BLEN_q                          0x00001000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK                 0x00002000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q                      0x00002000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK                  0x00004000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q                       0x00004000L
+#define MH_DEBUG_REG01__TC_MH_written_MASK                 0x00008000L
+#define MH_DEBUG_REG01__TC_MH_written                      0x00008000L
+#define MH_DEBUG_REG01__RB_SEND_q_MASK                     0x00010000L
+#define MH_DEBUG_REG01__RB_SEND_q                          0x00010000L
+#define MH_DEBUG_REG01__RB_RTR_q_MASK                      0x00020000L
+#define MH_DEBUG_REG01__RB_RTR_q                           0x00020000L
+#define MH_DEBUG_REG01__PA_SEND_q_MASK                     0x00040000L
+#define MH_DEBUG_REG01__PA_SEND_q                          0x00040000L
+#define MH_DEBUG_REG01__PA_RTR_q_MASK                      0x00080000L
+#define MH_DEBUG_REG01__PA_RTR_q                           0x00080000L
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG02__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG02__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG02__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG02__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK                 0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_rlast                      0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_tag_MASK                   0x00000070L
+#define MH_DEBUG_REG02__RDC_RID_MASK                       0x00000380L
+#define MH_DEBUG_REG02__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG02__MH_CP_writeclean_MASK              0x00001000L
+#define MH_DEBUG_REG02__MH_CP_writeclean                   0x00001000L
+#define MH_DEBUG_REG02__MH_RB_writeclean_MASK              0x00002000L
+#define MH_DEBUG_REG02__MH_RB_writeclean                   0x00002000L
+#define MH_DEBUG_REG02__MH_PA_writeclean_MASK              0x00004000L
+#define MH_DEBUG_REG02__MH_PA_writeclean                   0x00004000L
+#define MH_DEBUG_REG02__BRC_BID_MASK                       0x00038000L
+#define MH_DEBUG_REG02__BRC_BRESP_MASK                     0x000c0000L
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK             0xffffffffL
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK            0xffffffffL
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG05__CP_MH_send                         0x00000001L
+#define MH_DEBUG_REG05__CP_MH_write_MASK                   0x00000002L
+#define MH_DEBUG_REG05__CP_MH_write                        0x00000002L
+#define MH_DEBUG_REG05__CP_MH_tag_MASK                     0x0000001cL
+#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK                 0xffffffe0L
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__CP_MH_be_MASK                      0x000000ffL
+#define MH_DEBUG_REG08__RB_MH_be_MASK                      0x0000ff00L
+#define MH_DEBUG_REG08__PA_MH_be_MASK                      0x00ff0000L
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK                   0x00000007L
+#define MH_DEBUG_REG09__VGT_MH_send_MASK                   0x00000008L
+#define MH_DEBUG_REG09__VGT_MH_send                        0x00000008L
+#define MH_DEBUG_REG09__VGT_MH_tagbe_MASK                  0x00000010L
+#define MH_DEBUG_REG09__VGT_MH_tagbe                       0x00000010L
+#define MH_DEBUG_REG09__VGT_MH_ad_31_5_MASK                0xffffffe0L
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG10__TC_MH_send_MASK                    0x00000004L
+#define MH_DEBUG_REG10__TC_MH_send                         0x00000004L
+#define MH_DEBUG_REG10__TC_MH_mask_MASK                    0x00000018L
+#define MH_DEBUG_REG10__TC_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__TC_MH_info_MASK                    0x01ffffffL
+#define MH_DEBUG_REG11__TC_MH_send_MASK                    0x02000000L
+#define MH_DEBUG_REG11__TC_MH_send                         0x02000000L
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__MH_TC_mcinfo_MASK                  0x01ffffffL
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send_MASK             0x02000000L
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send                  0x02000000L
+#define MH_DEBUG_REG12__TC_MH_written_MASK                 0x04000000L
+#define MH_DEBUG_REG12__TC_MH_written                      0x04000000L
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK                   0x00000004L
+#define MH_DEBUG_REG13__TC_ROQ_SEND                        0x00000004L
+#define MH_DEBUG_REG13__TC_ROQ_MASK_MASK                   0x00000018L
+#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5_MASK              0xffffffe0L
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__TC_ROQ_INFO_MASK                   0x01ffffffL
+#define MH_DEBUG_REG14__TC_ROQ_SEND_MASK                   0x02000000L
+#define MH_DEBUG_REG14__TC_ROQ_SEND                        0x02000000L
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG15__RB_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG15__RB_MH_send                         0x00000010L
+#define MH_DEBUG_REG15__RB_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__RB_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG18__PA_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG18__PA_MH_send                         0x00000010L
+#define MH_DEBUG_REG18__PA_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__PA_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__PA_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG21__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG21__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG21__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG21__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG21__ALEN_q_2_0_MASK                    0x000000e0L
+#define MH_DEBUG_REG21__ARVALID_q_MASK                     0x00000100L
+#define MH_DEBUG_REG21__ARVALID_q                          0x00000100L
+#define MH_DEBUG_REG21__ARREADY_q_MASK                     0x00000200L
+#define MH_DEBUG_REG21__ARREADY_q                          0x00000200L
+#define MH_DEBUG_REG21__ARID_q_MASK                        0x00001c00L
+#define MH_DEBUG_REG21__ARLEN_q_1_0_MASK                   0x00006000L
+#define MH_DEBUG_REG21__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG21__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG21__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG21__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG21__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG21__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG21__RID_q_MASK                         0x001c0000L
+#define MH_DEBUG_REG21__WVALID_q_MASK                      0x00200000L
+#define MH_DEBUG_REG21__WVALID_q                           0x00200000L
+#define MH_DEBUG_REG21__WREADY_q_MASK                      0x00400000L
+#define MH_DEBUG_REG21__WREADY_q                           0x00400000L
+#define MH_DEBUG_REG21__WLAST_q_MASK                       0x00800000L
+#define MH_DEBUG_REG21__WLAST_q                            0x00800000L
+#define MH_DEBUG_REG21__WID_q_MASK                         0x07000000L
+#define MH_DEBUG_REG21__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG21__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG21__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG21__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG21__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG22__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG22__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG22__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG22__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG22__ALEN_q_1_0_MASK                    0x00000060L
+#define MH_DEBUG_REG22__ARVALID_q_MASK                     0x00000080L
+#define MH_DEBUG_REG22__ARVALID_q                          0x00000080L
+#define MH_DEBUG_REG22__ARREADY_q_MASK                     0x00000100L
+#define MH_DEBUG_REG22__ARREADY_q                          0x00000100L
+#define MH_DEBUG_REG22__ARID_q_MASK                        0x00000e00L
+#define MH_DEBUG_REG22__ARLEN_q_1_1_MASK                   0x00001000L
+#define MH_DEBUG_REG22__ARLEN_q_1_1                        0x00001000L
+#define MH_DEBUG_REG22__WVALID_q_MASK                      0x00002000L
+#define MH_DEBUG_REG22__WVALID_q                           0x00002000L
+#define MH_DEBUG_REG22__WREADY_q_MASK                      0x00004000L
+#define MH_DEBUG_REG22__WREADY_q                           0x00004000L
+#define MH_DEBUG_REG22__WLAST_q_MASK                       0x00008000L
+#define MH_DEBUG_REG22__WLAST_q                            0x00008000L
+#define MH_DEBUG_REG22__WID_q_MASK                         0x00070000L
+#define MH_DEBUG_REG22__WSTRB_q_MASK                       0x07f80000L
+#define MH_DEBUG_REG22__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG22__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG22__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG22__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG22__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q                      0x00000001L
+#define MH_DEBUG_REG23__CTRL_ARC_ID_MASK                   0x0000000eL
+#define MH_DEBUG_REG23__CTRL_ARC_PAD_MASK                  0xfffffff0L
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG24__REG_A_MASK                         0x0000fffcL
+#define MH_DEBUG_REG24__REG_RE_MASK                        0x00010000L
+#define MH_DEBUG_REG24__REG_RE                             0x00010000L
+#define MH_DEBUG_REG24__REG_WE_MASK                        0x00020000L
+#define MH_DEBUG_REG24__REG_WE                             0x00020000L
+#define MH_DEBUG_REG24__BLOCK_RS_MASK                      0x00040000L
+#define MH_DEBUG_REG24__BLOCK_RS                           0x00040000L
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__REG_WD_MASK                        0xffffffffL
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__MH_RBBM_busy_MASK                  0x00000001L
+#define MH_DEBUG_REG26__MH_RBBM_busy                       0x00000001L
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int_MASK          0x00000002L
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int               0x00000002L
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int_MASK         0x00000004L
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int              0x00000004L
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int_MASK       0x00000008L
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int            0x00000008L
+#define MH_DEBUG_REG26__GAT_CLK_ENA_MASK                   0x00000010L
+#define MH_DEBUG_REG26__GAT_CLK_ENA                        0x00000010L
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override_MASK       0x00000020L
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override            0x00000020L
+#define MH_DEBUG_REG26__CNT_q_MASK                         0x00000fc0L
+#define MH_DEBUG_REG26__TCD_EMPTY_q_MASK                   0x00001000L
+#define MH_DEBUG_REG26__TCD_EMPTY_q                        0x00001000L
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY_MASK                  0x00002000L
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY                       0x00002000L
+#define MH_DEBUG_REG26__MH_BUSY_d_MASK                     0x00004000L
+#define MH_DEBUG_REG26__MH_BUSY_d                          0x00004000L
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY_MASK                 0x00008000L
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY                      0x00008000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL   0x00010000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC    0x00020000L
+#define MH_DEBUG_REG26__CP_SEND_q_MASK                     0x00040000L
+#define MH_DEBUG_REG26__CP_SEND_q                          0x00040000L
+#define MH_DEBUG_REG26__CP_RTR_q_MASK                      0x00080000L
+#define MH_DEBUG_REG26__CP_RTR_q                           0x00080000L
+#define MH_DEBUG_REG26__VGT_SEND_q_MASK                    0x00100000L
+#define MH_DEBUG_REG26__VGT_SEND_q                         0x00100000L
+#define MH_DEBUG_REG26__VGT_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG26__VGT_RTR_q                          0x00200000L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK                 0x00400000L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q                      0x00400000L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK              0x00800000L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q                   0x00800000L
+#define MH_DEBUG_REG26__RB_SEND_q_MASK                     0x01000000L
+#define MH_DEBUG_REG26__RB_SEND_q                          0x01000000L
+#define MH_DEBUG_REG26__RB_RTR_q_MASK                      0x02000000L
+#define MH_DEBUG_REG26__RB_RTR_q                           0x02000000L
+#define MH_DEBUG_REG26__PA_SEND_q_MASK                     0x04000000L
+#define MH_DEBUG_REG26__PA_SEND_q                          0x04000000L
+#define MH_DEBUG_REG26__PA_RTR_q_MASK                      0x08000000L
+#define MH_DEBUG_REG26__PA_RTR_q                           0x08000000L
+#define MH_DEBUG_REG26__RDC_VALID_MASK                     0x10000000L
+#define MH_DEBUG_REG26__RDC_VALID                          0x10000000L
+#define MH_DEBUG_REG26__RDC_RLAST_MASK                     0x20000000L
+#define MH_DEBUG_REG26__RDC_RLAST                          0x20000000L
+#define MH_DEBUG_REG26__TLBMISS_VALID_MASK                 0x40000000L
+#define MH_DEBUG_REG26__TLBMISS_VALID                      0x40000000L
+#define MH_DEBUG_REG26__BRC_VALID_MASK                     0x80000000L
+#define MH_DEBUG_REG26__BRC_VALID                          0x80000000L
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__EFF2_FP_WINNER_MASK                0x00000007L
+#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out_MASK           0x00000038L
+#define MH_DEBUG_REG27__EFF1_WINNER_MASK                   0x000001c0L
+#define MH_DEBUG_REG27__ARB_WINNER_MASK                    0x00000e00L
+#define MH_DEBUG_REG27__ARB_WINNER_q_MASK                  0x00007000L
+#define MH_DEBUG_REG27__EFF1_WIN_MASK                      0x00008000L
+#define MH_DEBUG_REG27__EFF1_WIN                           0x00008000L
+#define MH_DEBUG_REG27__KILL_EFF1_MASK                     0x00010000L
+#define MH_DEBUG_REG27__KILL_EFF1                          0x00010000L
+#define MH_DEBUG_REG27__ARB_HOLD_MASK                      0x00020000L
+#define MH_DEBUG_REG27__ARB_HOLD                           0x00020000L
+#define MH_DEBUG_REG27__ARB_RTR_q_MASK                     0x00040000L
+#define MH_DEBUG_REG27__ARB_RTR_q                          0x00040000L
+#define MH_DEBUG_REG27__CP_SEND_QUAL_MASK                  0x00080000L
+#define MH_DEBUG_REG27__CP_SEND_QUAL                       0x00080000L
+#define MH_DEBUG_REG27__VGT_SEND_QUAL_MASK                 0x00100000L
+#define MH_DEBUG_REG27__VGT_SEND_QUAL                      0x00100000L
+#define MH_DEBUG_REG27__TC_SEND_QUAL_MASK                  0x00200000L
+#define MH_DEBUG_REG27__TC_SEND_QUAL                       0x00200000L
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL_MASK             0x00400000L
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL                  0x00400000L
+#define MH_DEBUG_REG27__RB_SEND_QUAL_MASK                  0x00800000L
+#define MH_DEBUG_REG27__RB_SEND_QUAL                       0x00800000L
+#define MH_DEBUG_REG27__PA_SEND_QUAL_MASK                  0x01000000L
+#define MH_DEBUG_REG27__PA_SEND_QUAL                       0x01000000L
+#define MH_DEBUG_REG27__ARB_QUAL_MASK                      0x02000000L
+#define MH_DEBUG_REG27__ARB_QUAL                           0x02000000L
+#define MH_DEBUG_REG27__CP_EFF1_REQ_MASK                   0x04000000L
+#define MH_DEBUG_REG27__CP_EFF1_REQ                        0x04000000L
+#define MH_DEBUG_REG27__VGT_EFF1_REQ_MASK                  0x08000000L
+#define MH_DEBUG_REG27__VGT_EFF1_REQ                       0x08000000L
+#define MH_DEBUG_REG27__TC_EFF1_REQ_MASK                   0x10000000L
+#define MH_DEBUG_REG27__TC_EFF1_REQ                        0x10000000L
+#define MH_DEBUG_REG27__RB_EFF1_REQ_MASK                   0x20000000L
+#define MH_DEBUG_REG27__RB_EFF1_REQ                        0x20000000L
+#define MH_DEBUG_REG27__TCD_NEARFULL_q_MASK                0x40000000L
+#define MH_DEBUG_REG27__TCD_NEARFULL_q                     0x40000000L
+#define MH_DEBUG_REG27__TCHOLD_IP_q_MASK                   0x80000000L
+#define MH_DEBUG_REG27__TCHOLD_IP_q                        0x80000000L
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__EFF1_WINNER_MASK                   0x00000007L
+#define MH_DEBUG_REG28__ARB_WINNER_MASK                    0x00000038L
+#define MH_DEBUG_REG28__CP_SEND_QUAL_MASK                  0x00000040L
+#define MH_DEBUG_REG28__CP_SEND_QUAL                       0x00000040L
+#define MH_DEBUG_REG28__VGT_SEND_QUAL_MASK                 0x00000080L
+#define MH_DEBUG_REG28__VGT_SEND_QUAL                      0x00000080L
+#define MH_DEBUG_REG28__TC_SEND_QUAL_MASK                  0x00000100L
+#define MH_DEBUG_REG28__TC_SEND_QUAL                       0x00000100L
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL_MASK             0x00000200L
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL                  0x00000200L
+#define MH_DEBUG_REG28__RB_SEND_QUAL_MASK                  0x00000400L
+#define MH_DEBUG_REG28__RB_SEND_QUAL                       0x00000400L
+#define MH_DEBUG_REG28__ARB_QUAL_MASK                      0x00000800L
+#define MH_DEBUG_REG28__ARB_QUAL                           0x00000800L
+#define MH_DEBUG_REG28__CP_EFF1_REQ_MASK                   0x00001000L
+#define MH_DEBUG_REG28__CP_EFF1_REQ                        0x00001000L
+#define MH_DEBUG_REG28__VGT_EFF1_REQ_MASK                  0x00002000L
+#define MH_DEBUG_REG28__VGT_EFF1_REQ                       0x00002000L
+#define MH_DEBUG_REG28__TC_EFF1_REQ_MASK                   0x00004000L
+#define MH_DEBUG_REG28__TC_EFF1_REQ                        0x00004000L
+#define MH_DEBUG_REG28__RB_EFF1_REQ_MASK                   0x00008000L
+#define MH_DEBUG_REG28__RB_EFF1_REQ                        0x00008000L
+#define MH_DEBUG_REG28__EFF1_WIN_MASK                      0x00010000L
+#define MH_DEBUG_REG28__EFF1_WIN                           0x00010000L
+#define MH_DEBUG_REG28__KILL_EFF1_MASK                     0x00020000L
+#define MH_DEBUG_REG28__KILL_EFF1                          0x00020000L
+#define MH_DEBUG_REG28__TCD_NEARFULL_q_MASK                0x00040000L
+#define MH_DEBUG_REG28__TCD_NEARFULL_q                     0x00040000L
+#define MH_DEBUG_REG28__TC_ARB_HOLD_MASK                   0x00080000L
+#define MH_DEBUG_REG28__TC_ARB_HOLD                        0x00080000L
+#define MH_DEBUG_REG28__ARB_HOLD_MASK                      0x00100000L
+#define MH_DEBUG_REG28__ARB_HOLD                           0x00100000L
+#define MH_DEBUG_REG28__ARB_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG28__ARB_RTR_q                          0x00200000L
+#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q_MASK       0xffc00000L
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out_MASK           0x00000007L
+#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d_MASK          0x00000038L
+#define MH_DEBUG_REG29__LEAST_RECENT_d_MASK                0x000001c0L
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d_MASK         0x00000200L
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d              0x00000200L
+#define MH_DEBUG_REG29__ARB_HOLD_MASK                      0x00000400L
+#define MH_DEBUG_REG29__ARB_HOLD                           0x00000400L
+#define MH_DEBUG_REG29__ARB_RTR_q_MASK                     0x00000800L
+#define MH_DEBUG_REG29__ARB_RTR_q                          0x00000800L
+#define MH_DEBUG_REG29__CLNT_REQ_MASK                      0x0001f000L
+#define MH_DEBUG_REG29__RECENT_d_0_MASK                    0x000e0000L
+#define MH_DEBUG_REG29__RECENT_d_1_MASK                    0x00700000L
+#define MH_DEBUG_REG29__RECENT_d_2_MASK                    0x03800000L
+#define MH_DEBUG_REG29__RECENT_d_3_MASK                    0x1c000000L
+#define MH_DEBUG_REG29__RECENT_d_4_MASK                    0xe0000000L
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__TC_ARB_HOLD_MASK                   0x00000001L
+#define MH_DEBUG_REG30__TC_ARB_HOLD                        0x00000001L
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK_MASK        0x00000002L
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK             0x00000002L
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK_MASK          0x00000004L
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK               0x00000004L
+#define MH_DEBUG_REG30__TCD_NEARFULL_q_MASK                0x00000008L
+#define MH_DEBUG_REG30__TCD_NEARFULL_q                     0x00000008L
+#define MH_DEBUG_REG30__TCHOLD_IP_q_MASK                   0x00000010L
+#define MH_DEBUG_REG30__TCHOLD_IP_q                        0x00000010L
+#define MH_DEBUG_REG30__TCHOLD_CNT_q_MASK                  0x000000e0L
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q_MASK              0x00000200L
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q                   0x00000200L
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q_MASK                 0x00000400L
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q                      0x00000400L
+#define MH_DEBUG_REG30__TC_MH_written_MASK                 0x00000800L
+#define MH_DEBUG_REG30__TC_MH_written                      0x00000800L
+#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q_MASK            0x0007f000L
+#define MH_DEBUG_REG30__WBURST_ACTIVE_MASK                 0x00080000L
+#define MH_DEBUG_REG30__WBURST_ACTIVE                      0x00080000L
+#define MH_DEBUG_REG30__WLAST_q_MASK                       0x00100000L
+#define MH_DEBUG_REG30__WLAST_q                            0x00100000L
+#define MH_DEBUG_REG30__WBURST_IP_q_MASK                   0x00200000L
+#define MH_DEBUG_REG30__WBURST_IP_q                        0x00200000L
+#define MH_DEBUG_REG30__WBURST_CNT_q_MASK                  0x01c00000L
+#define MH_DEBUG_REG30__CP_SEND_QUAL_MASK                  0x02000000L
+#define MH_DEBUG_REG30__CP_SEND_QUAL                       0x02000000L
+#define MH_DEBUG_REG30__CP_MH_write_MASK                   0x04000000L
+#define MH_DEBUG_REG30__CP_MH_write                        0x04000000L
+#define MH_DEBUG_REG30__RB_SEND_QUAL_MASK                  0x08000000L
+#define MH_DEBUG_REG30__RB_SEND_QUAL                       0x08000000L
+#define MH_DEBUG_REG30__PA_SEND_QUAL_MASK                  0x10000000L
+#define MH_DEBUG_REG30__PA_SEND_QUAL                       0x10000000L
+#define MH_DEBUG_REG30__ARB_WINNER_MASK                    0xe0000000L
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q_MASK           0x03ffffffL
+#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0x1c000000L
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG32__ROQ_MARK_q_MASK                    0x0000ff00L
+#define MH_DEBUG_REG32__ROQ_VALID_q_MASK                   0x00ff0000L
+#define MH_DEBUG_REG32__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG32__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG32__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG32__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG32__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG32__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG32__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG32__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG33__ROQ_MARK_d_MASK                    0x0000ff00L
+#define MH_DEBUG_REG33__ROQ_VALID_d_MASK                   0x00ff0000L
+#define MH_DEBUG_REG33__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG33__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG33__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG33__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG33__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG33__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG33__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG33__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN_MASK             0x000000ffL
+#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ_MASK             0x0000ff00L
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN_MASK         0x00ff0000L
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ_MASK         0xff000000L
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG35__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG35__ROQ_MARK_q_0_MASK                  0x00000004L
+#define MH_DEBUG_REG35__ROQ_MARK_q_0                       0x00000004L
+#define MH_DEBUG_REG35__ROQ_VALID_q_0_MASK                 0x00000008L
+#define MH_DEBUG_REG35__ROQ_VALID_q_0                      0x00000008L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0_MASK             0x00000010L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0                  0x00000010L
+#define MH_DEBUG_REG35__ROQ_ADDR_0_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG36__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG36__ROQ_MARK_q_1_MASK                  0x00000004L
+#define MH_DEBUG_REG36__ROQ_MARK_q_1                       0x00000004L
+#define MH_DEBUG_REG36__ROQ_VALID_q_1_MASK                 0x00000008L
+#define MH_DEBUG_REG36__ROQ_VALID_q_1                      0x00000008L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1_MASK             0x00000010L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1                  0x00000010L
+#define MH_DEBUG_REG36__ROQ_ADDR_1_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG37__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG37__ROQ_MARK_q_2_MASK                  0x00000004L
+#define MH_DEBUG_REG37__ROQ_MARK_q_2                       0x00000004L
+#define MH_DEBUG_REG37__ROQ_VALID_q_2_MASK                 0x00000008L
+#define MH_DEBUG_REG37__ROQ_VALID_q_2                      0x00000008L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2_MASK             0x00000010L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2                  0x00000010L
+#define MH_DEBUG_REG37__ROQ_ADDR_2_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG38__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG38__ROQ_MARK_q_3_MASK                  0x00000004L
+#define MH_DEBUG_REG38__ROQ_MARK_q_3                       0x00000004L
+#define MH_DEBUG_REG38__ROQ_VALID_q_3_MASK                 0x00000008L
+#define MH_DEBUG_REG38__ROQ_VALID_q_3                      0x00000008L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3_MASK             0x00000010L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3                  0x00000010L
+#define MH_DEBUG_REG38__ROQ_ADDR_3_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG39__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG39__ROQ_MARK_q_4_MASK                  0x00000004L
+#define MH_DEBUG_REG39__ROQ_MARK_q_4                       0x00000004L
+#define MH_DEBUG_REG39__ROQ_VALID_q_4_MASK                 0x00000008L
+#define MH_DEBUG_REG39__ROQ_VALID_q_4                      0x00000008L
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4_MASK             0x00000010L
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4                  0x00000010L
+#define MH_DEBUG_REG39__ROQ_ADDR_4_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG40__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG40__ROQ_MARK_q_5_MASK                  0x00000004L
+#define MH_DEBUG_REG40__ROQ_MARK_q_5                       0x00000004L
+#define MH_DEBUG_REG40__ROQ_VALID_q_5_MASK                 0x00000008L
+#define MH_DEBUG_REG40__ROQ_VALID_q_5                      0x00000008L
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5_MASK             0x00000010L
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5                  0x00000010L
+#define MH_DEBUG_REG40__ROQ_ADDR_5_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG41__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG41__ROQ_MARK_q_6_MASK                  0x00000004L
+#define MH_DEBUG_REG41__ROQ_MARK_q_6                       0x00000004L
+#define MH_DEBUG_REG41__ROQ_VALID_q_6_MASK                 0x00000008L
+#define MH_DEBUG_REG41__ROQ_VALID_q_6                      0x00000008L
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6_MASK             0x00000010L
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6                  0x00000010L
+#define MH_DEBUG_REG41__ROQ_ADDR_6_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG42__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG42__ROQ_MARK_q_7_MASK                  0x00000004L
+#define MH_DEBUG_REG42__ROQ_MARK_q_7                       0x00000004L
+#define MH_DEBUG_REG42__ROQ_VALID_q_7_MASK                 0x00000008L
+#define MH_DEBUG_REG42__ROQ_VALID_q_7                      0x00000008L
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7_MASK             0x00000010L
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7                  0x00000010L
+#define MH_DEBUG_REG42__ROQ_ADDR_7_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_REG_WE_q_MASK                  0x00000001L
+#define MH_DEBUG_REG43__ARB_REG_WE_q                       0x00000001L
+#define MH_DEBUG_REG43__ARB_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG43__ARB_WE                             0x00000002L
+#define MH_DEBUG_REG43__ARB_REG_VALID_q_MASK               0x00000004L
+#define MH_DEBUG_REG43__ARB_REG_VALID_q                    0x00000004L
+#define MH_DEBUG_REG43__ARB_RTR_q_MASK                     0x00000008L
+#define MH_DEBUG_REG43__ARB_RTR_q                          0x00000008L
+#define MH_DEBUG_REG43__ARB_REG_RTR_MASK                   0x00000010L
+#define MH_DEBUG_REG43__ARB_REG_RTR                        0x00000010L
+#define MH_DEBUG_REG43__WDAT_BURST_RTR_MASK                0x00000020L
+#define MH_DEBUG_REG43__WDAT_BURST_RTR                     0x00000020L
+#define MH_DEBUG_REG43__MMU_RTR_MASK                       0x00000040L
+#define MH_DEBUG_REG43__MMU_RTR                            0x00000040L
+#define MH_DEBUG_REG43__ARB_ID_q_MASK                      0x00000380L
+#define MH_DEBUG_REG43__ARB_WRITE_q_MASK                   0x00000400L
+#define MH_DEBUG_REG43__ARB_WRITE_q                        0x00000400L
+#define MH_DEBUG_REG43__ARB_BLEN_q_MASK                    0x00000800L
+#define MH_DEBUG_REG43__ARB_BLEN_q                         0x00000800L
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY_MASK                0x00001000L
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY                     0x00001000L
+#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q_MASK                0x0000e000L
+#define MH_DEBUG_REG43__MMU_WE_MASK                        0x00010000L
+#define MH_DEBUG_REG43__MMU_WE                             0x00010000L
+#define MH_DEBUG_REG43__ARQ_RTR_MASK                       0x00020000L
+#define MH_DEBUG_REG43__ARQ_RTR                            0x00020000L
+#define MH_DEBUG_REG43__MMU_ID_MASK                        0x001c0000L
+#define MH_DEBUG_REG43__MMU_WRITE_MASK                     0x00200000L
+#define MH_DEBUG_REG43__MMU_WRITE                          0x00200000L
+#define MH_DEBUG_REG43__MMU_BLEN_MASK                      0x00400000L
+#define MH_DEBUG_REG43__MMU_BLEN                           0x00400000L
+#define MH_DEBUG_REG43__WBURST_IP_q_MASK                   0x00800000L
+#define MH_DEBUG_REG43__WBURST_IP_q                        0x00800000L
+#define MH_DEBUG_REG43__WDAT_REG_WE_q_MASK                 0x01000000L
+#define MH_DEBUG_REG43__WDAT_REG_WE_q                      0x01000000L
+#define MH_DEBUG_REG43__WDB_WE_MASK                        0x02000000L
+#define MH_DEBUG_REG43__WDB_WE                             0x02000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4_MASK                0x04000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4                     0x04000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3_MASK                0x08000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3                     0x08000000L
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG44__ARB_WE                             0x00000001L
+#define MH_DEBUG_REG44__ARB_ID_q_MASK                      0x0000000eL
+#define MH_DEBUG_REG44__ARB_VAD_q_MASK                     0xfffffff0L
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__MMU_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG45__MMU_WE                             0x00000001L
+#define MH_DEBUG_REG45__MMU_ID_MASK                        0x0000000eL
+#define MH_DEBUG_REG45__MMU_PAD_MASK                       0xfffffff0L
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDAT_REG_WE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG46__WDAT_REG_WE_q                      0x00000001L
+#define MH_DEBUG_REG46__WDB_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG46__WDB_WE                             0x00000002L
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q_MASK              0x00000004L
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q                   0x00000004L
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4_MASK                0x00000008L
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4                     0x00000008L
+#define MH_DEBUG_REG46__ARB_WSTRB_q_MASK                   0x00000ff0L
+#define MH_DEBUG_REG46__ARB_WLAST_MASK                     0x00001000L
+#define MH_DEBUG_REG46__ARB_WLAST                          0x00001000L
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY_MASK                0x00002000L
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY                     0x00002000L
+#define MH_DEBUG_REG46__WDB_FIFO_CNT_q_MASK                0x0007c000L
+#define MH_DEBUG_REG46__WDC_WDB_RE_q_MASK                  0x00080000L
+#define MH_DEBUG_REG46__WDC_WDB_RE_q                       0x00080000L
+#define MH_DEBUG_REG46__WDB_WDC_WID_MASK                   0x00700000L
+#define MH_DEBUG_REG46__WDB_WDC_WLAST_MASK                 0x00800000L
+#define MH_DEBUG_REG46__WDB_WDC_WLAST                      0x00800000L
+#define MH_DEBUG_REG46__WDB_WDC_WSTRB_MASK                 0xff000000L
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0_MASK            0xffffffffL
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32_MASK           0xffffffffL
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY_MASK                0x00000001L
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY                     0x00000001L
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY_MASK               0x00000002L
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY                    0x00000002L
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY_MASK                0x00000004L
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY                     0x00000004L
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE_MASK                0x00000008L
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE                     0x00000008L
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS_MASK              0x00000010L
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS                   0x00000010L
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q_MASK             0x00000020L
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q                  0x00000020L
+#define MH_DEBUG_REG49__INFLT_LIMIT_q_MASK                 0x00000040L
+#define MH_DEBUG_REG49__INFLT_LIMIT_q                      0x00000040L
+#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q_MASK             0x00001f80L
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q_MASK                 0x00002000L
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q                      0x00002000L
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q_MASK                0x00004000L
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q                     0x00004000L
+#define MH_DEBUG_REG49__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG49__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG49__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG49__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG49__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG49__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG49__BVALID_q_MASK                      0x00040000L
+#define MH_DEBUG_REG49__BVALID_q                           0x00040000L
+#define MH_DEBUG_REG49__BREADY_q_MASK                      0x00080000L
+#define MH_DEBUG_REG49__BREADY_q                           0x00080000L
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG50__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG50__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG50__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG50__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG50__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND_MASK               0x00000008L
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND                    0x00000008L
+#define MH_DEBUG_REG50__TLBMISS_VALID_MASK                 0x00000010L
+#define MH_DEBUG_REG50__TLBMISS_VALID                      0x00000010L
+#define MH_DEBUG_REG50__RDC_VALID_MASK                     0x00000020L
+#define MH_DEBUG_REG50__RDC_VALID                          0x00000020L
+#define MH_DEBUG_REG50__RDC_RID_MASK                       0x000001c0L
+#define MH_DEBUG_REG50__RDC_RLAST_MASK                     0x00000200L
+#define MH_DEBUG_REG50__RDC_RLAST                          0x00000200L
+#define MH_DEBUG_REG50__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS_MASK              0x00001000L
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS                   0x00001000L
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q_MASK             0x00002000L
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q                  0x00002000L
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q_MASK              0x00004000L
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q                   0x00004000L
+#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q_MASK       0x001f8000L
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE_MASK               0x00200000L
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE                    0x00200000L
+#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q_MASK          0x0fc00000L
+#define MH_DEBUG_REG50__CNT_HOLD_q1_MASK                   0x10000000L
+#define MH_DEBUG_REG50__CNT_HOLD_q1                        0x10000000L
+#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0xe0000000L
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT_MASK             0xffffffffL
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0_MASK        0x00000003L
+#define MH_DEBUG_REG52__ARB_WE_MASK                        0x00000004L
+#define MH_DEBUG_REG52__ARB_WE                             0x00000004L
+#define MH_DEBUG_REG52__MMU_RTR_MASK                       0x00000008L
+#define MH_DEBUG_REG52__MMU_RTR                            0x00000008L
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4_MASK       0x03fffff0L
+#define MH_DEBUG_REG52__ARB_ID_q_MASK                      0x1c000000L
+#define MH_DEBUG_REG52__ARB_WRITE_q_MASK                   0x20000000L
+#define MH_DEBUG_REG52__ARB_WRITE_q                        0x20000000L
+#define MH_DEBUG_REG52__client_behavior_q_MASK             0xc0000000L
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__stage1_valid_MASK                  0x00000001L
+#define MH_DEBUG_REG53__stage1_valid                       0x00000001L
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q_MASK             0x00000002L
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q                  0x00000002L
+#define MH_DEBUG_REG53__pa_in_mpu_range_MASK               0x00000004L
+#define MH_DEBUG_REG53__pa_in_mpu_range                    0x00000004L
+#define MH_DEBUG_REG53__tag_match_q_MASK                   0x00000008L
+#define MH_DEBUG_REG53__tag_match_q                        0x00000008L
+#define MH_DEBUG_REG53__tag_miss_q_MASK                    0x00000010L
+#define MH_DEBUG_REG53__tag_miss_q                         0x00000010L
+#define MH_DEBUG_REG53__va_in_range_q_MASK                 0x00000020L
+#define MH_DEBUG_REG53__va_in_range_q                      0x00000020L
+#define MH_DEBUG_REG53__MMU_MISS_MASK                      0x00000040L
+#define MH_DEBUG_REG53__MMU_MISS                           0x00000040L
+#define MH_DEBUG_REG53__MMU_READ_MISS_MASK                 0x00000080L
+#define MH_DEBUG_REG53__MMU_READ_MISS                      0x00000080L
+#define MH_DEBUG_REG53__MMU_WRITE_MISS_MASK                0x00000100L
+#define MH_DEBUG_REG53__MMU_WRITE_MISS                     0x00000100L
+#define MH_DEBUG_REG53__MMU_HIT_MASK                       0x00000200L
+#define MH_DEBUG_REG53__MMU_HIT                            0x00000200L
+#define MH_DEBUG_REG53__MMU_READ_HIT_MASK                  0x00000400L
+#define MH_DEBUG_REG53__MMU_READ_HIT                       0x00000400L
+#define MH_DEBUG_REG53__MMU_WRITE_HIT_MASK                 0x00000800L
+#define MH_DEBUG_REG53__MMU_WRITE_HIT                      0x00000800L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS_MASK        0x00001000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS             0x00001000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT_MASK         0x00002000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT              0x00002000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS_MASK     0x00004000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS          0x00004000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT_MASK      0x00008000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT           0x00008000L
+#define MH_DEBUG_REG53__REQ_VA_OFFSET_q_MASK               0xffff0000L
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__ARQ_RTR_MASK                       0x00000001L
+#define MH_DEBUG_REG54__ARQ_RTR                            0x00000001L
+#define MH_DEBUG_REG54__MMU_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG54__MMU_WE                             0x00000002L
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q_MASK             0x00000004L
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q                  0x00000004L
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS_MASK              0x00000008L
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS                   0x00000008L
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND_MASK               0x00000010L
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND                    0x00000010L
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH  0x00000020L
+#define MH_DEBUG_REG54__pa_in_mpu_range_MASK               0x00000040L
+#define MH_DEBUG_REG54__pa_in_mpu_range                    0x00000040L
+#define MH_DEBUG_REG54__stage1_valid_MASK                  0x00000080L
+#define MH_DEBUG_REG54__stage1_valid                       0x00000080L
+#define MH_DEBUG_REG54__stage2_valid_MASK                  0x00000100L
+#define MH_DEBUG_REG54__stage2_valid                       0x00000100L
+#define MH_DEBUG_REG54__client_behavior_q_MASK             0x00000600L
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q_MASK             0x00000800L
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q                  0x00000800L
+#define MH_DEBUG_REG54__tag_match_q_MASK                   0x00001000L
+#define MH_DEBUG_REG54__tag_match_q                        0x00001000L
+#define MH_DEBUG_REG54__tag_miss_q_MASK                    0x00002000L
+#define MH_DEBUG_REG54__tag_miss_q                         0x00002000L
+#define MH_DEBUG_REG54__va_in_range_q_MASK                 0x00004000L
+#define MH_DEBUG_REG54__va_in_range_q                      0x00004000L
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q_MASK          0x00008000L
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q               0x00008000L
+#define MH_DEBUG_REG54__TAG_valid_q_MASK                   0xffff0000L
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG0_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG55__TAG_valid_q_0_MASK                 0x00002000L
+#define MH_DEBUG_REG55__TAG_valid_q_0                      0x00002000L
+#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG55__TAG1_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG55__TAG_valid_q_1_MASK                 0x20000000L
+#define MH_DEBUG_REG55__TAG_valid_q_1                      0x20000000L
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG2_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG56__TAG_valid_q_2_MASK                 0x00002000L
+#define MH_DEBUG_REG56__TAG_valid_q_2                      0x00002000L
+#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG56__TAG3_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG56__TAG_valid_q_3_MASK                 0x20000000L
+#define MH_DEBUG_REG56__TAG_valid_q_3                      0x20000000L
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG4_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG57__TAG_valid_q_4_MASK                 0x00002000L
+#define MH_DEBUG_REG57__TAG_valid_q_4                      0x00002000L
+#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG57__TAG5_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG57__TAG_valid_q_5_MASK                 0x20000000L
+#define MH_DEBUG_REG57__TAG_valid_q_5                      0x20000000L
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG6_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG58__TAG_valid_q_6_MASK                 0x00002000L
+#define MH_DEBUG_REG58__TAG_valid_q_6                      0x00002000L
+#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG58__TAG7_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG58__TAG_valid_q_7_MASK                 0x20000000L
+#define MH_DEBUG_REG58__TAG_valid_q_7                      0x20000000L
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG8_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG59__TAG_valid_q_8_MASK                 0x00002000L
+#define MH_DEBUG_REG59__TAG_valid_q_8                      0x00002000L
+#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG59__TAG9_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG59__TAG_valid_q_9_MASK                 0x20000000L
+#define MH_DEBUG_REG59__TAG_valid_q_9                      0x20000000L
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG10_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG60__TAG_valid_q_10_MASK                0x00002000L
+#define MH_DEBUG_REG60__TAG_valid_q_10                     0x00002000L
+#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG60__TAG11_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG60__TAG_valid_q_11_MASK                0x20000000L
+#define MH_DEBUG_REG60__TAG_valid_q_11                     0x20000000L
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__TAG12_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG61__TAG_valid_q_12_MASK                0x00002000L
+#define MH_DEBUG_REG61__TAG_valid_q_12                     0x00002000L
+#define MH_DEBUG_REG61__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG61__TAG13_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG61__TAG_valid_q_13_MASK                0x20000000L
+#define MH_DEBUG_REG61__TAG_valid_q_13                     0x20000000L
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__TAG14_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG62__TAG_valid_q_14_MASK                0x00002000L
+#define MH_DEBUG_REG62__TAG_valid_q_14                     0x00002000L
+#define MH_DEBUG_REG62__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG62__TAG15_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG62__TAG_valid_q_15_MASK                0x20000000L
+#define MH_DEBUG_REG62__TAG_valid_q_15                     0x20000000L
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE_MASK                     0x00000001L
+#define MH_MMU_CONFIG__MMU_ENABLE                          0x00000001L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK              0x00000002L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE                   0x00000002L
+#define MH_MMU_CONFIG__RESERVED1_MASK                      0x0000000cL
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK             0x00000030L
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK             0x000000c0L
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK            0x00000300L
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK            0x00000c00L
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK            0x00003000L
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK            0x0000c000L
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK            0x00030000L
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK           0x000c0000L
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK           0x00300000L
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK             0x00c00000L
+#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR_MASK             0x03000000L
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK             0x00000fffL
+#define MH_MMU_VA_RANGE__VA_BASE_MASK                      0xfffff000L
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE_MASK                       0xfffff000L
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK                 0x00000001L
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT                      0x00000001L
+#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK                    0x00000002L
+#define MH_MMU_PAGE_FAULT__OP_TYPE                         0x00000002L
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK              0x0000000cL
+#define MH_MMU_PAGE_FAULT__AXI_ID_MASK                     0x00000070L
+#define MH_MMU_PAGE_FAULT__RESERVED1_MASK                  0x00000080L
+#define MH_MMU_PAGE_FAULT__RESERVED1                       0x00000080L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK   0x00000100L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE        0x00000100L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK       0x00000200L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE            0x00000200L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK      0x00000400L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR           0x00000400L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK     0x00000800L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR          0x00000800L
+#define MH_MMU_PAGE_FAULT__REQ_VA_MASK                     0xfffff000L
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK                 0xffffffe0L
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK             0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL                  0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK              0x00000002L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC                   0x00000002L
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE_MASK                     0xfffff000L
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END_MASK                       0xfffff000L
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK                     0x00000002L
+#define WAIT_UNTIL__WAIT_RE_VSYNC                          0x00000002L
+#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK                     0x00000004L
+#define WAIT_UNTIL__WAIT_FE_VSYNC                          0x00000004L
+#define WAIT_UNTIL__WAIT_VSYNC_MASK                        0x00000008L
+#define WAIT_UNTIL__WAIT_VSYNC                             0x00000008L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK                    0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0                         0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK                    0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1                         0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK                    0x00000040L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2                         0x00000040L
+#define WAIT_UNTIL__WAIT_CMDFIFO_MASK                      0x00000400L
+#define WAIT_UNTIL__WAIT_CMDFIFO                           0x00000400L
+#define WAIT_UNTIL__WAIT_2D_IDLE_MASK                      0x00004000L
+#define WAIT_UNTIL__WAIT_2D_IDLE                           0x00004000L
+#define WAIT_UNTIL__WAIT_3D_IDLE_MASK                      0x00008000L
+#define WAIT_UNTIL__WAIT_3D_IDLE                           0x00008000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK                 0x00010000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN                      0x00010000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK                 0x00020000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN                      0x00020000L
+#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK                   0x00f00000L
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK           0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI                0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK      0x00000020L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI           0x00000020L
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL_MASK                    0x0000001fL
+#define RBBM_STATUS__TC_BUSY_MASK                          0x00000020L
+#define RBBM_STATUS__TC_BUSY                               0x00000020L
+#define RBBM_STATUS__HIRQ_PENDING_MASK                     0x00000100L
+#define RBBM_STATUS__HIRQ_PENDING                          0x00000100L
+#define RBBM_STATUS__CPRQ_PENDING_MASK                     0x00000200L
+#define RBBM_STATUS__CPRQ_PENDING                          0x00000200L
+#define RBBM_STATUS__CFRQ_PENDING_MASK                     0x00000400L
+#define RBBM_STATUS__CFRQ_PENDING                          0x00000400L
+#define RBBM_STATUS__PFRQ_PENDING_MASK                     0x00000800L
+#define RBBM_STATUS__PFRQ_PENDING                          0x00000800L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK                  0x00001000L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA                       0x00001000L
+#define RBBM_STATUS__RBBM_WU_BUSY_MASK                     0x00004000L
+#define RBBM_STATUS__RBBM_WU_BUSY                          0x00004000L
+#define RBBM_STATUS__CP_NRT_BUSY_MASK                      0x00010000L
+#define RBBM_STATUS__CP_NRT_BUSY                           0x00010000L
+#define RBBM_STATUS__MH_BUSY_MASK                          0x00040000L
+#define RBBM_STATUS__MH_BUSY                               0x00040000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK                0x00080000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY                     0x00080000L
+#define RBBM_STATUS__SX_BUSY_MASK                          0x00200000L
+#define RBBM_STATUS__SX_BUSY                               0x00200000L
+#define RBBM_STATUS__TPC_BUSY_MASK                         0x00400000L
+#define RBBM_STATUS__TPC_BUSY                              0x00400000L
+#define RBBM_STATUS__SC_CNTX_BUSY_MASK                     0x01000000L
+#define RBBM_STATUS__SC_CNTX_BUSY                          0x01000000L
+#define RBBM_STATUS__PA_BUSY_MASK                          0x02000000L
+#define RBBM_STATUS__PA_BUSY                               0x02000000L
+#define RBBM_STATUS__VGT_BUSY_MASK                         0x04000000L
+#define RBBM_STATUS__VGT_BUSY                              0x04000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK                   0x08000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY                        0x08000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK                    0x10000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY                         0x10000000L
+#define RBBM_STATUS__RB_CNTX_BUSY_MASK                     0x40000000L
+#define RBBM_STATUS__RB_CNTX_BUSY                          0x40000000L
+#define RBBM_STATUS__GUI_ACTIVE_MASK                       0x80000000L
+#define RBBM_STATUS__GUI_ACTIVE                            0x80000000L
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0_MASK             0x00000001L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0                  0x00000001L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1_MASK             0x00000002L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1                  0x00000002L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2_MASK             0x00000004L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2                  0x00000004L
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID_MASK               0x00000008L
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID                    0x00000008L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0_MASK                0x00000010L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0                     0x00000010L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1_MASK                0x00000020L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1                     0x00000020L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2_MASK                0x00000040L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2                     0x00000040L
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL_MASK                   0x00000080L
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL                        0x00000080L
+#define RBBM_DSPLY__DMI_CH1_NUM_BUFS_MASK                  0x00000300L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0_MASK                0x00000400L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0                     0x00000400L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1_MASK                0x00000800L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1                     0x00000800L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2_MASK                0x00001000L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2                     0x00001000L
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL_MASK                   0x00002000L
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL                        0x00002000L
+#define RBBM_DSPLY__DMI_CH2_NUM_BUFS_MASK                  0x0000c000L
+#define RBBM_DSPLY__DMI_CHANNEL_SELECT_MASK                0x00030000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0_MASK                0x00100000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0                     0x00100000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1_MASK                0x00200000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1                     0x00200000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2_MASK                0x00400000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2                     0x00400000L
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL_MASK                   0x00800000L
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL                        0x00800000L
+#define RBBM_DSPLY__DMI_CH3_NUM_BUFS_MASK                  0x03000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0_MASK                0x04000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0                     0x04000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1_MASK                0x08000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1                     0x08000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2_MASK                0x10000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2                     0x10000000L
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL_MASK                   0x20000000L
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL                        0x20000000L
+#define RBBM_DSPLY__DMI_CH4_NUM_BUFS_MASK                  0xc0000000L
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID_MASK         0x00000003L
+#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID_MASK         0x00000300L
+#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID_MASK         0x00030000L
+#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID_MASK         0x03000000L
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST_MASK                  0xffffffffL
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK            0x0000ffffL
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK           0x00ff0000L
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK               0xff000000L
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK               0xffffffffL
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0_MASK                   0x000000ffL
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1_MASK                   0x0000000fL
+#define RBBM_PERIPHID1__DESIGNER0_MASK                     0x000000f0L
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1_MASK                     0x0000000fL
+#define RBBM_PERIPHID2__REVISION_MASK                      0x000000f0L
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK           0x00000003L
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK          0x0000000cL
+#define RBBM_PERIPHID3__MH_INTERFACE_MASK                  0x00000030L
+#define RBBM_PERIPHID3__CONTINUATION_MASK                  0x00000080L
+#define RBBM_PERIPHID3__CONTINUATION                       0x00000080L
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT_MASK                       0x000000ffL
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK               0x0001ff00L
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK            0x0000001fL
+#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK                    0x000003e0L
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK                0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_CP                     0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK                0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA                     0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK                0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH                     0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK                0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC                     0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK                0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ                     0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK                0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX                     0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK               0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB                    0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK                0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC                     0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK               0x00010000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT                    0x00010000L
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK    0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE         0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK        0x00000004L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE             0x00000004L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK    0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE         0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK     0x00000010L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE          0x00000010L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK    0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE         0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE   0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE   0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK     0x00000100L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE          0x00000100L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK        0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE             0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK   0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE        0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK   0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE        0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK   0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE        0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK   0x00004000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE        0x00004000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK   0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE        0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK   0x00010000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE        0x00010000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK   0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE        0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK   0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE        0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE   0x00080000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK     0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE          0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK    0x00200000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE         0x00200000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK      0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE           0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK    0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE         0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK  0x01000000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE       0x01000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK       0x02000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE            0x02000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK    0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE         0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK        0x08000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE             0x08000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK     0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE          0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK    0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE         0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK    0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE         0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK  0x80000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE       0x80000000L
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK     0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE          0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK     0x00000004L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE          0x00000004L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK   0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE        0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE      0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK   0x00000020L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE        0x00000020L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE     0x00000040L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK      0x00000080L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE           0x00000080L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK    0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE         0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK    0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE         0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK    0x00000800L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE         0x00000800L
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK                0x0000ffffL
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK_MASK             0x003f0000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_MASK               0x01000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP                    0x01000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK                  0x02000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI                       0x02000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE_MASK      0x20000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE           0x20000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE_MASK         0x40000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE              0x40000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK             0x80000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE                  0x80000000L
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK                   0x00000001L
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE                        0x00000001L
+
+// RBBM_DEBUG_OUT
+#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT_MASK                 0xffffffffL
+
+// RBBM_DEBUG_CNTL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR_MASK               0x0000003fL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL_MASK                0x00000f00L
+#define RBBM_DEBUG_CNTL__SW_ENABLE_MASK                    0x00001000L
+#define RBBM_DEBUG_CNTL__SW_ENABLE                         0x00001000L
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR_MASK          0x003f0000L
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL_MASK           0x0f000000L
+#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB_MASK           0xf0000000L
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR_MASK                        0x00000002L
+#define RBBM_DEBUG__IGNORE_RTR                             0x00000002L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK                0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU                     0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK             0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC                  0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK             0x00000010L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI                  0x00000010L
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK         0x00000f00L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK                 0x00010000L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI                      0x00010000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK      0x00020000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI           0x00020000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK     0x00040000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI          0x00040000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK      0x00080000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI           0x00080000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK                    0x00100000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR                         0x00100000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK                   0x00200000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR                        0x00200000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK                    0x00400000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR                         0x00400000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK        0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI             0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK               0x01000000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR                    0x01000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK               0x80000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY                    0x80000000L
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS_MASK                 0x0001fffcL
+#define RBBM_READ_ERROR__READ_REQUESTER_MASK               0x40000000L
+#define RBBM_READ_ERROR__READ_REQUESTER                    0x40000000L
+#define RBBM_READ_ERROR__READ_ERROR_MASK                   0x80000000L
+#define RBBM_READ_ERROR__READ_ERROR                        0x80000000L
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK   0x000000ffL
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK                 0x00000001L
+#define RBBM_INT_CNTL__RDERR_INT_MASK                      0x00000001L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK        0x00000002L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK             0x00000002L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK              0x00080000L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK                   0x00080000L
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK               0x00000001L
+#define RBBM_INT_STATUS__RDERR_INT_STAT                    0x00000001L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK      0x00000002L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT           0x00000002L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK            0x00080000L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT                 0x00080000L
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK_MASK                   0x00000001L
+#define RBBM_INT_ACK__RDERR_INT_ACK                        0x00000001L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK          0x00000002L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK               0x00000002L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK                0x00080000L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK                     0x00080000L
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK                0x00000020L
+#define MASTER_INT_SIGNAL__MH_INT_STAT                     0x00000020L
+#define MASTER_INT_SIGNAL__SQ_INT_STAT_MASK                0x04000000L
+#define MASTER_INT_SIGNAL__SQ_INT_STAT                     0x04000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK                0x40000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT                     0x40000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK              0x80000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT                   0x80000000L
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK     0x0000003fL
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK          0xffffffffL
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK          0x0000ffffL
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE_MASK                           0xffffffe0L
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ_MASK                          0x0000003fL
+#define CP_RB_CNTL__RB_BLKSZ_MASK                          0x00003f00L
+#define CP_RB_CNTL__BUF_SWAP_MASK                          0x00030000L
+#define CP_RB_CNTL__RB_POLL_EN_MASK                        0x00100000L
+#define CP_RB_CNTL__RB_POLL_EN                             0x00100000L
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK                      0x08000000L
+#define CP_RB_CNTL__RB_NO_UPDATE                           0x08000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK                    0x80000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA                         0x80000000L
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                 0xfffffffcL
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR_MASK                           0x000fffffL
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK                     0x000fffffL
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR_MASK                           0x000fffffL
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK             0x0fffffffL
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK             0xf0000000L
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK                 0xfffffffcL
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE_MASK                         0xfffffffcL
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK                       0x000fffffL
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE_MASK                         0xfffffffcL
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK                       0x000fffffL
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE_MASK                           0xfffffffcL
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK                         0x000fffffL
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK            0x0000000fL
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK            0x00000f00L
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK             0x000f0000L
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END_MASK                    0x001f0000L
+#define CP_MEQ_THRESHOLDS__ROQ_END_MASK                    0x1f000000L
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK                    0x0000007fL
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK                     0x00007f00L
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK                     0x007f0000L
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST_MASK                      0x0000007fL
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK                         0x0000001fL
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK              0x0000007fL
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK              0x007f0000L
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK           0x0000007fL
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK           0x007f0000L
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK           0x0000007fL
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK           0x007f0000L
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK            0x00000007L
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK            0x00000700L
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK                   0x0000007fL
+#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK                   0x007f0000L
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR_MASK                         0x000003ffL
+#define CP_MEQ_STAT__MEQ_WPTR_MASK                         0x03ff0000L
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK                   0x00000001L
+#define CP_MIU_TAG_STAT__TAG_0_STAT                        0x00000001L
+#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK                   0x00000002L
+#define CP_MIU_TAG_STAT__TAG_1_STAT                        0x00000002L
+#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK                   0x00000004L
+#define CP_MIU_TAG_STAT__TAG_2_STAT                        0x00000004L
+#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK                   0x00000008L
+#define CP_MIU_TAG_STAT__TAG_3_STAT                        0x00000008L
+#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK                   0x00000010L
+#define CP_MIU_TAG_STAT__TAG_4_STAT                        0x00000010L
+#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK                   0x00000020L
+#define CP_MIU_TAG_STAT__TAG_5_STAT                        0x00000020L
+#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK                   0x00000040L
+#define CP_MIU_TAG_STAT__TAG_6_STAT                        0x00000040L
+#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK                   0x00000080L
+#define CP_MIU_TAG_STAT__TAG_7_STAT                        0x00000080L
+#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK                   0x00000100L
+#define CP_MIU_TAG_STAT__TAG_8_STAT                        0x00000100L
+#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK                   0x00000200L
+#define CP_MIU_TAG_STAT__TAG_9_STAT                        0x00000200L
+#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK                  0x00000400L
+#define CP_MIU_TAG_STAT__TAG_10_STAT                       0x00000400L
+#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK                  0x00000800L
+#define CP_MIU_TAG_STAT__TAG_11_STAT                       0x00000800L
+#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK                  0x00001000L
+#define CP_MIU_TAG_STAT__TAG_12_STAT                       0x00001000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK                  0x00002000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT                       0x00002000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK                  0x00004000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT                       0x00004000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK                  0x00008000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT                       0x00008000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK                  0x00010000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT                       0x00010000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK                  0x00020000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT                       0x00020000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK           0x80000000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG                0x80000000L
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX_MASK                       0x0000007fL
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK                   0x00030000L
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA_MASK                         0xffffffffL
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX_MASK                        0x0000ffffL
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK            0x02000000L
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY                 0x02000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK            0x04000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY                 0x04000000L
+#define CP_ME_CNTL__ME_HALT_MASK                           0x10000000L
+#define CP_ME_CNTL__ME_HALT                                0x10000000L
+#define CP_ME_CNTL__ME_BUSY_MASK                           0x20000000L
+#define CP_ME_CNTL__ME_BUSY                                0x20000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE_MASK                     0x80000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE                          0x80000000L
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA_MASK                   0xffffffffL
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK                   0xffffffffL
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR_MASK                       0xffffffffL
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK             0x007fffffL
+#define CP_DEBUG__PREDICATE_DISABLE_MASK                   0x00800000L
+#define CP_DEBUG__PREDICATE_DISABLE                        0x00800000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK                 0x01000000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE                      0x01000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK             0x02000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE                  0x02000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK                  0x04000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS                       0x04000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK                 0x08000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE                      0x08000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK              0x10000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE                   0x10000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK              0x40000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL                   0x40000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK              0x80000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE                   0x80000000L
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK                0xffffffffL
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK                0xffffffffL
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK                0xffffffffL
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK                0xffffffffL
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK                0xffffffffL
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK                0xffffffffL
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK                0xffffffffL
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK                0xffffffffL
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK_MASK                    0x000000ffL
+#define SCRATCH_UMSK__SCRATCH_SWAP_MASK                    0x00030000L
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR_MASK                    0xffffffe0L
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM                    0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR                   0x00000002L
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM                    0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR                   0x00000002L
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK               0x00000001L
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC                    0x00000001L
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK                0x00000003L
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK                0xfffffffcL
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK                0xffffffffL
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK   0x00000001L
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR        0x00000001L
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK  0x00000003L
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK  0xfffffffcL
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK  0xffffffffL
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK_MASK                      0x00080000L
+#define CP_INT_CNTL__SW_INT_MASK                           0x00080000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK             0x00800000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK                  0x00800000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK                0x01000000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK                     0x01000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK        0x02000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK             0x02000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK          0x04000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK               0x04000000L
+#define CP_INT_CNTL__IB_ERROR_MASK_MASK                    0x08000000L
+#define CP_INT_CNTL__IB_ERROR_MASK                         0x08000000L
+#define CP_INT_CNTL__IB2_INT_MASK_MASK                     0x20000000L
+#define CP_INT_CNTL__IB2_INT_MASK                          0x20000000L
+#define CP_INT_CNTL__IB1_INT_MASK_MASK                     0x40000000L
+#define CP_INT_CNTL__IB1_INT_MASK                          0x40000000L
+#define CP_INT_CNTL__RB_INT_MASK_MASK                      0x80000000L
+#define CP_INT_CNTL__RB_INT_MASK                           0x80000000L
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT_MASK                    0x00080000L
+#define CP_INT_STATUS__SW_INT_STAT                         0x00080000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK           0x00800000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT                0x00800000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK              0x01000000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT                   0x01000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK      0x02000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT           0x02000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK        0x04000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT             0x04000000L
+#define CP_INT_STATUS__IB_ERROR_STAT_MASK                  0x08000000L
+#define CP_INT_STATUS__IB_ERROR_STAT                       0x08000000L
+#define CP_INT_STATUS__IB2_INT_STAT_MASK                   0x20000000L
+#define CP_INT_STATUS__IB2_INT_STAT                        0x20000000L
+#define CP_INT_STATUS__IB1_INT_STAT_MASK                   0x40000000L
+#define CP_INT_STATUS__IB1_INT_STAT                        0x40000000L
+#define CP_INT_STATUS__RB_INT_STAT_MASK                    0x80000000L
+#define CP_INT_STATUS__RB_INT_STAT                         0x80000000L
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK_MASK                        0x00080000L
+#define CP_INT_ACK__SW_INT_ACK                             0x00080000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK               0x00800000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK                    0x00800000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK                  0x01000000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK                       0x01000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK          0x02000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK               0x02000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK            0x04000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK                 0x04000000L
+#define CP_INT_ACK__IB_ERROR_ACK_MASK                      0x08000000L
+#define CP_INT_ACK__IB_ERROR_ACK                           0x08000000L
+#define CP_INT_ACK__IB2_INT_ACK_MASK                       0x20000000L
+#define CP_INT_ACK__IB2_INT_ACK                            0x20000000L
+#define CP_INT_ACK__IB1_INT_ACK_MASK                       0x40000000L
+#define CP_INT_ACK__IB1_INT_ACK                            0x40000000L
+#define CP_INT_ACK__RB_INT_ACK_MASK                        0x80000000L
+#define CP_INT_ACK__RB_INT_ACK                             0x80000000L
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                 0x000001ffL
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK                 0x00ffffffL
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK                0x0000000fL
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK          0x00000300L
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK          0x0000003fL
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK               0xffffffffL
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK               0x0000ffffL
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK                   0xffffffffL
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK                   0xffffffffL
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK               0xffffffffL
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK               0xffffffffL
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0_MASK                      0x00000001L
+#define CP_NV_FLAGS_0__DISCARD_0                           0x00000001L
+#define CP_NV_FLAGS_0__END_RCVD_0_MASK                     0x00000002L
+#define CP_NV_FLAGS_0__END_RCVD_0                          0x00000002L
+#define CP_NV_FLAGS_0__DISCARD_1_MASK                      0x00000004L
+#define CP_NV_FLAGS_0__DISCARD_1                           0x00000004L
+#define CP_NV_FLAGS_0__END_RCVD_1_MASK                     0x00000008L
+#define CP_NV_FLAGS_0__END_RCVD_1                          0x00000008L
+#define CP_NV_FLAGS_0__DISCARD_2_MASK                      0x00000010L
+#define CP_NV_FLAGS_0__DISCARD_2                           0x00000010L
+#define CP_NV_FLAGS_0__END_RCVD_2_MASK                     0x00000020L
+#define CP_NV_FLAGS_0__END_RCVD_2                          0x00000020L
+#define CP_NV_FLAGS_0__DISCARD_3_MASK                      0x00000040L
+#define CP_NV_FLAGS_0__DISCARD_3                           0x00000040L
+#define CP_NV_FLAGS_0__END_RCVD_3_MASK                     0x00000080L
+#define CP_NV_FLAGS_0__END_RCVD_3                          0x00000080L
+#define CP_NV_FLAGS_0__DISCARD_4_MASK                      0x00000100L
+#define CP_NV_FLAGS_0__DISCARD_4                           0x00000100L
+#define CP_NV_FLAGS_0__END_RCVD_4_MASK                     0x00000200L
+#define CP_NV_FLAGS_0__END_RCVD_4                          0x00000200L
+#define CP_NV_FLAGS_0__DISCARD_5_MASK                      0x00000400L
+#define CP_NV_FLAGS_0__DISCARD_5                           0x00000400L
+#define CP_NV_FLAGS_0__END_RCVD_5_MASK                     0x00000800L
+#define CP_NV_FLAGS_0__END_RCVD_5                          0x00000800L
+#define CP_NV_FLAGS_0__DISCARD_6_MASK                      0x00001000L
+#define CP_NV_FLAGS_0__DISCARD_6                           0x00001000L
+#define CP_NV_FLAGS_0__END_RCVD_6_MASK                     0x00002000L
+#define CP_NV_FLAGS_0__END_RCVD_6                          0x00002000L
+#define CP_NV_FLAGS_0__DISCARD_7_MASK                      0x00004000L
+#define CP_NV_FLAGS_0__DISCARD_7                           0x00004000L
+#define CP_NV_FLAGS_0__END_RCVD_7_MASK                     0x00008000L
+#define CP_NV_FLAGS_0__END_RCVD_7                          0x00008000L
+#define CP_NV_FLAGS_0__DISCARD_8_MASK                      0x00010000L
+#define CP_NV_FLAGS_0__DISCARD_8                           0x00010000L
+#define CP_NV_FLAGS_0__END_RCVD_8_MASK                     0x00020000L
+#define CP_NV_FLAGS_0__END_RCVD_8                          0x00020000L
+#define CP_NV_FLAGS_0__DISCARD_9_MASK                      0x00040000L
+#define CP_NV_FLAGS_0__DISCARD_9                           0x00040000L
+#define CP_NV_FLAGS_0__END_RCVD_9_MASK                     0x00080000L
+#define CP_NV_FLAGS_0__END_RCVD_9                          0x00080000L
+#define CP_NV_FLAGS_0__DISCARD_10_MASK                     0x00100000L
+#define CP_NV_FLAGS_0__DISCARD_10                          0x00100000L
+#define CP_NV_FLAGS_0__END_RCVD_10_MASK                    0x00200000L
+#define CP_NV_FLAGS_0__END_RCVD_10                         0x00200000L
+#define CP_NV_FLAGS_0__DISCARD_11_MASK                     0x00400000L
+#define CP_NV_FLAGS_0__DISCARD_11                          0x00400000L
+#define CP_NV_FLAGS_0__END_RCVD_11_MASK                    0x00800000L
+#define CP_NV_FLAGS_0__END_RCVD_11                         0x00800000L
+#define CP_NV_FLAGS_0__DISCARD_12_MASK                     0x01000000L
+#define CP_NV_FLAGS_0__DISCARD_12                          0x01000000L
+#define CP_NV_FLAGS_0__END_RCVD_12_MASK                    0x02000000L
+#define CP_NV_FLAGS_0__END_RCVD_12                         0x02000000L
+#define CP_NV_FLAGS_0__DISCARD_13_MASK                     0x04000000L
+#define CP_NV_FLAGS_0__DISCARD_13                          0x04000000L
+#define CP_NV_FLAGS_0__END_RCVD_13_MASK                    0x08000000L
+#define CP_NV_FLAGS_0__END_RCVD_13                         0x08000000L
+#define CP_NV_FLAGS_0__DISCARD_14_MASK                     0x10000000L
+#define CP_NV_FLAGS_0__DISCARD_14                          0x10000000L
+#define CP_NV_FLAGS_0__END_RCVD_14_MASK                    0x20000000L
+#define CP_NV_FLAGS_0__END_RCVD_14                         0x20000000L
+#define CP_NV_FLAGS_0__DISCARD_15_MASK                     0x40000000L
+#define CP_NV_FLAGS_0__DISCARD_15                          0x40000000L
+#define CP_NV_FLAGS_0__END_RCVD_15_MASK                    0x80000000L
+#define CP_NV_FLAGS_0__END_RCVD_15                         0x80000000L
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16_MASK                     0x00000001L
+#define CP_NV_FLAGS_1__DISCARD_16                          0x00000001L
+#define CP_NV_FLAGS_1__END_RCVD_16_MASK                    0x00000002L
+#define CP_NV_FLAGS_1__END_RCVD_16                         0x00000002L
+#define CP_NV_FLAGS_1__DISCARD_17_MASK                     0x00000004L
+#define CP_NV_FLAGS_1__DISCARD_17                          0x00000004L
+#define CP_NV_FLAGS_1__END_RCVD_17_MASK                    0x00000008L
+#define CP_NV_FLAGS_1__END_RCVD_17                         0x00000008L
+#define CP_NV_FLAGS_1__DISCARD_18_MASK                     0x00000010L
+#define CP_NV_FLAGS_1__DISCARD_18                          0x00000010L
+#define CP_NV_FLAGS_1__END_RCVD_18_MASK                    0x00000020L
+#define CP_NV_FLAGS_1__END_RCVD_18                         0x00000020L
+#define CP_NV_FLAGS_1__DISCARD_19_MASK                     0x00000040L
+#define CP_NV_FLAGS_1__DISCARD_19                          0x00000040L
+#define CP_NV_FLAGS_1__END_RCVD_19_MASK                    0x00000080L
+#define CP_NV_FLAGS_1__END_RCVD_19                         0x00000080L
+#define CP_NV_FLAGS_1__DISCARD_20_MASK                     0x00000100L
+#define CP_NV_FLAGS_1__DISCARD_20                          0x00000100L
+#define CP_NV_FLAGS_1__END_RCVD_20_MASK                    0x00000200L
+#define CP_NV_FLAGS_1__END_RCVD_20                         0x00000200L
+#define CP_NV_FLAGS_1__DISCARD_21_MASK                     0x00000400L
+#define CP_NV_FLAGS_1__DISCARD_21                          0x00000400L
+#define CP_NV_FLAGS_1__END_RCVD_21_MASK                    0x00000800L
+#define CP_NV_FLAGS_1__END_RCVD_21                         0x00000800L
+#define CP_NV_FLAGS_1__DISCARD_22_MASK                     0x00001000L
+#define CP_NV_FLAGS_1__DISCARD_22                          0x00001000L
+#define CP_NV_FLAGS_1__END_RCVD_22_MASK                    0x00002000L
+#define CP_NV_FLAGS_1__END_RCVD_22                         0x00002000L
+#define CP_NV_FLAGS_1__DISCARD_23_MASK                     0x00004000L
+#define CP_NV_FLAGS_1__DISCARD_23                          0x00004000L
+#define CP_NV_FLAGS_1__END_RCVD_23_MASK                    0x00008000L
+#define CP_NV_FLAGS_1__END_RCVD_23                         0x00008000L
+#define CP_NV_FLAGS_1__DISCARD_24_MASK                     0x00010000L
+#define CP_NV_FLAGS_1__DISCARD_24                          0x00010000L
+#define CP_NV_FLAGS_1__END_RCVD_24_MASK                    0x00020000L
+#define CP_NV_FLAGS_1__END_RCVD_24                         0x00020000L
+#define CP_NV_FLAGS_1__DISCARD_25_MASK                     0x00040000L
+#define CP_NV_FLAGS_1__DISCARD_25                          0x00040000L
+#define CP_NV_FLAGS_1__END_RCVD_25_MASK                    0x00080000L
+#define CP_NV_FLAGS_1__END_RCVD_25                         0x00080000L
+#define CP_NV_FLAGS_1__DISCARD_26_MASK                     0x00100000L
+#define CP_NV_FLAGS_1__DISCARD_26                          0x00100000L
+#define CP_NV_FLAGS_1__END_RCVD_26_MASK                    0x00200000L
+#define CP_NV_FLAGS_1__END_RCVD_26                         0x00200000L
+#define CP_NV_FLAGS_1__DISCARD_27_MASK                     0x00400000L
+#define CP_NV_FLAGS_1__DISCARD_27                          0x00400000L
+#define CP_NV_FLAGS_1__END_RCVD_27_MASK                    0x00800000L
+#define CP_NV_FLAGS_1__END_RCVD_27                         0x00800000L
+#define CP_NV_FLAGS_1__DISCARD_28_MASK                     0x01000000L
+#define CP_NV_FLAGS_1__DISCARD_28                          0x01000000L
+#define CP_NV_FLAGS_1__END_RCVD_28_MASK                    0x02000000L
+#define CP_NV_FLAGS_1__END_RCVD_28                         0x02000000L
+#define CP_NV_FLAGS_1__DISCARD_29_MASK                     0x04000000L
+#define CP_NV_FLAGS_1__DISCARD_29                          0x04000000L
+#define CP_NV_FLAGS_1__END_RCVD_29_MASK                    0x08000000L
+#define CP_NV_FLAGS_1__END_RCVD_29                         0x08000000L
+#define CP_NV_FLAGS_1__DISCARD_30_MASK                     0x10000000L
+#define CP_NV_FLAGS_1__DISCARD_30                          0x10000000L
+#define CP_NV_FLAGS_1__END_RCVD_30_MASK                    0x20000000L
+#define CP_NV_FLAGS_1__END_RCVD_30                         0x20000000L
+#define CP_NV_FLAGS_1__DISCARD_31_MASK                     0x40000000L
+#define CP_NV_FLAGS_1__DISCARD_31                          0x40000000L
+#define CP_NV_FLAGS_1__END_RCVD_31_MASK                    0x80000000L
+#define CP_NV_FLAGS_1__END_RCVD_31                         0x80000000L
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32_MASK                     0x00000001L
+#define CP_NV_FLAGS_2__DISCARD_32                          0x00000001L
+#define CP_NV_FLAGS_2__END_RCVD_32_MASK                    0x00000002L
+#define CP_NV_FLAGS_2__END_RCVD_32                         0x00000002L
+#define CP_NV_FLAGS_2__DISCARD_33_MASK                     0x00000004L
+#define CP_NV_FLAGS_2__DISCARD_33                          0x00000004L
+#define CP_NV_FLAGS_2__END_RCVD_33_MASK                    0x00000008L
+#define CP_NV_FLAGS_2__END_RCVD_33                         0x00000008L
+#define CP_NV_FLAGS_2__DISCARD_34_MASK                     0x00000010L
+#define CP_NV_FLAGS_2__DISCARD_34                          0x00000010L
+#define CP_NV_FLAGS_2__END_RCVD_34_MASK                    0x00000020L
+#define CP_NV_FLAGS_2__END_RCVD_34                         0x00000020L
+#define CP_NV_FLAGS_2__DISCARD_35_MASK                     0x00000040L
+#define CP_NV_FLAGS_2__DISCARD_35                          0x00000040L
+#define CP_NV_FLAGS_2__END_RCVD_35_MASK                    0x00000080L
+#define CP_NV_FLAGS_2__END_RCVD_35                         0x00000080L
+#define CP_NV_FLAGS_2__DISCARD_36_MASK                     0x00000100L
+#define CP_NV_FLAGS_2__DISCARD_36                          0x00000100L
+#define CP_NV_FLAGS_2__END_RCVD_36_MASK                    0x00000200L
+#define CP_NV_FLAGS_2__END_RCVD_36                         0x00000200L
+#define CP_NV_FLAGS_2__DISCARD_37_MASK                     0x00000400L
+#define CP_NV_FLAGS_2__DISCARD_37                          0x00000400L
+#define CP_NV_FLAGS_2__END_RCVD_37_MASK                    0x00000800L
+#define CP_NV_FLAGS_2__END_RCVD_37                         0x00000800L
+#define CP_NV_FLAGS_2__DISCARD_38_MASK                     0x00001000L
+#define CP_NV_FLAGS_2__DISCARD_38                          0x00001000L
+#define CP_NV_FLAGS_2__END_RCVD_38_MASK                    0x00002000L
+#define CP_NV_FLAGS_2__END_RCVD_38                         0x00002000L
+#define CP_NV_FLAGS_2__DISCARD_39_MASK                     0x00004000L
+#define CP_NV_FLAGS_2__DISCARD_39                          0x00004000L
+#define CP_NV_FLAGS_2__END_RCVD_39_MASK                    0x00008000L
+#define CP_NV_FLAGS_2__END_RCVD_39                         0x00008000L
+#define CP_NV_FLAGS_2__DISCARD_40_MASK                     0x00010000L
+#define CP_NV_FLAGS_2__DISCARD_40                          0x00010000L
+#define CP_NV_FLAGS_2__END_RCVD_40_MASK                    0x00020000L
+#define CP_NV_FLAGS_2__END_RCVD_40                         0x00020000L
+#define CP_NV_FLAGS_2__DISCARD_41_MASK                     0x00040000L
+#define CP_NV_FLAGS_2__DISCARD_41                          0x00040000L
+#define CP_NV_FLAGS_2__END_RCVD_41_MASK                    0x00080000L
+#define CP_NV_FLAGS_2__END_RCVD_41                         0x00080000L
+#define CP_NV_FLAGS_2__DISCARD_42_MASK                     0x00100000L
+#define CP_NV_FLAGS_2__DISCARD_42                          0x00100000L
+#define CP_NV_FLAGS_2__END_RCVD_42_MASK                    0x00200000L
+#define CP_NV_FLAGS_2__END_RCVD_42                         0x00200000L
+#define CP_NV_FLAGS_2__DISCARD_43_MASK                     0x00400000L
+#define CP_NV_FLAGS_2__DISCARD_43                          0x00400000L
+#define CP_NV_FLAGS_2__END_RCVD_43_MASK                    0x00800000L
+#define CP_NV_FLAGS_2__END_RCVD_43                         0x00800000L
+#define CP_NV_FLAGS_2__DISCARD_44_MASK                     0x01000000L
+#define CP_NV_FLAGS_2__DISCARD_44                          0x01000000L
+#define CP_NV_FLAGS_2__END_RCVD_44_MASK                    0x02000000L
+#define CP_NV_FLAGS_2__END_RCVD_44                         0x02000000L
+#define CP_NV_FLAGS_2__DISCARD_45_MASK                     0x04000000L
+#define CP_NV_FLAGS_2__DISCARD_45                          0x04000000L
+#define CP_NV_FLAGS_2__END_RCVD_45_MASK                    0x08000000L
+#define CP_NV_FLAGS_2__END_RCVD_45                         0x08000000L
+#define CP_NV_FLAGS_2__DISCARD_46_MASK                     0x10000000L
+#define CP_NV_FLAGS_2__DISCARD_46                          0x10000000L
+#define CP_NV_FLAGS_2__END_RCVD_46_MASK                    0x20000000L
+#define CP_NV_FLAGS_2__END_RCVD_46                         0x20000000L
+#define CP_NV_FLAGS_2__DISCARD_47_MASK                     0x40000000L
+#define CP_NV_FLAGS_2__DISCARD_47                          0x40000000L
+#define CP_NV_FLAGS_2__END_RCVD_47_MASK                    0x80000000L
+#define CP_NV_FLAGS_2__END_RCVD_47                         0x80000000L
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48_MASK                     0x00000001L
+#define CP_NV_FLAGS_3__DISCARD_48                          0x00000001L
+#define CP_NV_FLAGS_3__END_RCVD_48_MASK                    0x00000002L
+#define CP_NV_FLAGS_3__END_RCVD_48                         0x00000002L
+#define CP_NV_FLAGS_3__DISCARD_49_MASK                     0x00000004L
+#define CP_NV_FLAGS_3__DISCARD_49                          0x00000004L
+#define CP_NV_FLAGS_3__END_RCVD_49_MASK                    0x00000008L
+#define CP_NV_FLAGS_3__END_RCVD_49                         0x00000008L
+#define CP_NV_FLAGS_3__DISCARD_50_MASK                     0x00000010L
+#define CP_NV_FLAGS_3__DISCARD_50                          0x00000010L
+#define CP_NV_FLAGS_3__END_RCVD_50_MASK                    0x00000020L
+#define CP_NV_FLAGS_3__END_RCVD_50                         0x00000020L
+#define CP_NV_FLAGS_3__DISCARD_51_MASK                     0x00000040L
+#define CP_NV_FLAGS_3__DISCARD_51                          0x00000040L
+#define CP_NV_FLAGS_3__END_RCVD_51_MASK                    0x00000080L
+#define CP_NV_FLAGS_3__END_RCVD_51                         0x00000080L
+#define CP_NV_FLAGS_3__DISCARD_52_MASK                     0x00000100L
+#define CP_NV_FLAGS_3__DISCARD_52                          0x00000100L
+#define CP_NV_FLAGS_3__END_RCVD_52_MASK                    0x00000200L
+#define CP_NV_FLAGS_3__END_RCVD_52                         0x00000200L
+#define CP_NV_FLAGS_3__DISCARD_53_MASK                     0x00000400L
+#define CP_NV_FLAGS_3__DISCARD_53                          0x00000400L
+#define CP_NV_FLAGS_3__END_RCVD_53_MASK                    0x00000800L
+#define CP_NV_FLAGS_3__END_RCVD_53                         0x00000800L
+#define CP_NV_FLAGS_3__DISCARD_54_MASK                     0x00001000L
+#define CP_NV_FLAGS_3__DISCARD_54                          0x00001000L
+#define CP_NV_FLAGS_3__END_RCVD_54_MASK                    0x00002000L
+#define CP_NV_FLAGS_3__END_RCVD_54                         0x00002000L
+#define CP_NV_FLAGS_3__DISCARD_55_MASK                     0x00004000L
+#define CP_NV_FLAGS_3__DISCARD_55                          0x00004000L
+#define CP_NV_FLAGS_3__END_RCVD_55_MASK                    0x00008000L
+#define CP_NV_FLAGS_3__END_RCVD_55                         0x00008000L
+#define CP_NV_FLAGS_3__DISCARD_56_MASK                     0x00010000L
+#define CP_NV_FLAGS_3__DISCARD_56                          0x00010000L
+#define CP_NV_FLAGS_3__END_RCVD_56_MASK                    0x00020000L
+#define CP_NV_FLAGS_3__END_RCVD_56                         0x00020000L
+#define CP_NV_FLAGS_3__DISCARD_57_MASK                     0x00040000L
+#define CP_NV_FLAGS_3__DISCARD_57                          0x00040000L
+#define CP_NV_FLAGS_3__END_RCVD_57_MASK                    0x00080000L
+#define CP_NV_FLAGS_3__END_RCVD_57                         0x00080000L
+#define CP_NV_FLAGS_3__DISCARD_58_MASK                     0x00100000L
+#define CP_NV_FLAGS_3__DISCARD_58                          0x00100000L
+#define CP_NV_FLAGS_3__END_RCVD_58_MASK                    0x00200000L
+#define CP_NV_FLAGS_3__END_RCVD_58                         0x00200000L
+#define CP_NV_FLAGS_3__DISCARD_59_MASK                     0x00400000L
+#define CP_NV_FLAGS_3__DISCARD_59                          0x00400000L
+#define CP_NV_FLAGS_3__END_RCVD_59_MASK                    0x00800000L
+#define CP_NV_FLAGS_3__END_RCVD_59                         0x00800000L
+#define CP_NV_FLAGS_3__DISCARD_60_MASK                     0x01000000L
+#define CP_NV_FLAGS_3__DISCARD_60                          0x01000000L
+#define CP_NV_FLAGS_3__END_RCVD_60_MASK                    0x02000000L
+#define CP_NV_FLAGS_3__END_RCVD_60                         0x02000000L
+#define CP_NV_FLAGS_3__DISCARD_61_MASK                     0x04000000L
+#define CP_NV_FLAGS_3__DISCARD_61                          0x04000000L
+#define CP_NV_FLAGS_3__END_RCVD_61_MASK                    0x08000000L
+#define CP_NV_FLAGS_3__END_RCVD_61                         0x08000000L
+#define CP_NV_FLAGS_3__DISCARD_62_MASK                     0x10000000L
+#define CP_NV_FLAGS_3__DISCARD_62                          0x10000000L
+#define CP_NV_FLAGS_3__END_RCVD_62_MASK                    0x20000000L
+#define CP_NV_FLAGS_3__END_RCVD_62                         0x20000000L
+#define CP_NV_FLAGS_3__DISCARD_63_MASK                     0x40000000L
+#define CP_NV_FLAGS_3__DISCARD_63                          0x40000000L
+#define CP_NV_FLAGS_3__END_RCVD_63_MASK                    0x80000000L
+#define CP_NV_FLAGS_3__END_RCVD_63                         0x80000000L
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK       0x0000001fL
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK         0xffffffffL
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER_MASK                      0xffffffffL
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY_MASK                          0x00000001L
+#define CP_STAT__MIU_WR_BUSY                               0x00000001L
+#define CP_STAT__MIU_RD_REQ_BUSY_MASK                      0x00000002L
+#define CP_STAT__MIU_RD_REQ_BUSY                           0x00000002L
+#define CP_STAT__MIU_RD_RETURN_BUSY_MASK                   0x00000004L
+#define CP_STAT__MIU_RD_RETURN_BUSY                        0x00000004L
+#define CP_STAT__RBIU_BUSY_MASK                            0x00000008L
+#define CP_STAT__RBIU_BUSY                                 0x00000008L
+#define CP_STAT__RCIU_BUSY_MASK                            0x00000010L
+#define CP_STAT__RCIU_BUSY                                 0x00000010L
+#define CP_STAT__CSF_RING_BUSY_MASK                        0x00000020L
+#define CP_STAT__CSF_RING_BUSY                             0x00000020L
+#define CP_STAT__CSF_INDIRECTS_BUSY_MASK                   0x00000040L
+#define CP_STAT__CSF_INDIRECTS_BUSY                        0x00000040L
+#define CP_STAT__CSF_INDIRECT2_BUSY_MASK                   0x00000080L
+#define CP_STAT__CSF_INDIRECT2_BUSY                        0x00000080L
+#define CP_STAT__CSF_ST_BUSY_MASK                          0x00000200L
+#define CP_STAT__CSF_ST_BUSY                               0x00000200L
+#define CP_STAT__CSF_BUSY_MASK                             0x00000400L
+#define CP_STAT__CSF_BUSY                                  0x00000400L
+#define CP_STAT__RING_QUEUE_BUSY_MASK                      0x00000800L
+#define CP_STAT__RING_QUEUE_BUSY                           0x00000800L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK                 0x00001000L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY                      0x00001000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK                 0x00002000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY                      0x00002000L
+#define CP_STAT__ST_QUEUE_BUSY_MASK                        0x00010000L
+#define CP_STAT__ST_QUEUE_BUSY                             0x00010000L
+#define CP_STAT__PFP_BUSY_MASK                             0x00020000L
+#define CP_STAT__PFP_BUSY                                  0x00020000L
+#define CP_STAT__MEQ_RING_BUSY_MASK                        0x00040000L
+#define CP_STAT__MEQ_RING_BUSY                             0x00040000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK                   0x00080000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY                        0x00080000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK                   0x00100000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY                        0x00100000L
+#define CP_STAT__MIU_WC_STALL_MASK                         0x00200000L
+#define CP_STAT__MIU_WC_STALL                              0x00200000L
+#define CP_STAT__CP_NRT_BUSY_MASK                          0x00400000L
+#define CP_STAT__CP_NRT_BUSY                               0x00400000L
+#define CP_STAT___3D_BUSY_MASK                             0x00800000L
+#define CP_STAT___3D_BUSY                                  0x00800000L
+#define CP_STAT__ME_BUSY_MASK                              0x04000000L
+#define CP_STAT__ME_BUSY                                   0x04000000L
+#define CP_STAT__ME_WC_BUSY_MASK                           0x20000000L
+#define CP_STAT__ME_WC_BUSY                                0x20000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK              0x40000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY                   0x40000000L
+#define CP_STAT__CP_BUSY_MASK                              0x80000000L
+#define CP_STAT__CP_BUSY                                   0x80000000L
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE_MASK                          0xffffffffL
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE_MASK                          0xffffffffL
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK           0x000000ffL
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK       0x00000100L
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA            0x00000100L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK             0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA                  0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK             0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA                  0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK             0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA                  0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK             0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA                  0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK             0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA                  0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK             0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA                  0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK             0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA                  0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK             0x00010000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA                  0x00010000L
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA_MASK           0x00020000L
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA                0x00020000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK               0x02000000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA                    0x02000000L
+#define COHER_STATUS_PM4__STATUS_MASK                      0x80000000L
+#define COHER_STATUS_PM4__STATUS                           0x80000000L
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE_MASK                         0xffffffffL
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE_MASK                         0xffffffffL
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK          0x000000ffL
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK      0x00000100L
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA           0x00000100L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK            0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA                 0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK            0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA                 0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK            0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA                 0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK            0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA                 0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK            0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA                 0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK            0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA                 0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK            0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA                 0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK            0x00010000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA                 0x00010000L
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA_MASK          0x00020000L
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA               0x00020000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK              0x02000000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA                   0x02000000L
+#define COHER_STATUS_HOST__STATUS_MASK                     0x80000000L
+#define COHER_STATUS_HOST__STATUS                          0x80000000L
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0_MASK                0xfffff000L
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1_MASK                0xfffff000L
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2_MASK                0xfffff000L
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3_MASK                0xfffff000L
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4_MASK                0xfffff000L
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5_MASK                0xfffff000L
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6_MASK                0xfffff000L
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7_MASK                0xfffff000L
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH_MASK                0x00003fffL
+#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK                 0x0000c000L
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT_MASK                   0x0000000fL
+#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK               0x00000030L
+#define RB_COLOR_INFO__COLOR_LINEAR_MASK                   0x00000040L
+#define RB_COLOR_INFO__COLOR_LINEAR                        0x00000040L
+#define RB_COLOR_INFO__COLOR_ENDIAN_MASK                   0x00000180L
+#define RB_COLOR_INFO__COLOR_SWAP_MASK                     0x00000600L
+#define RB_COLOR_INFO__COLOR_BASE_MASK                     0xfffff000L
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK                   0x00000001L
+#define RB_DEPTH_INFO__DEPTH_FORMAT                        0x00000001L
+#define RB_DEPTH_INFO__DEPTH_BASE_MASK                     0xfffff000L
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF_MASK                 0x000000ffL
+#define RB_STENCILREFMASK__STENCILMASK_MASK                0x0000ff00L
+#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK           0x00ff0000L
+#define RB_STENCILREFMASK__RESERVED0_MASK                  0x01000000L
+#define RB_STENCILREFMASK__RESERVED0                       0x01000000L
+#define RB_STENCILREFMASK__RESERVED1_MASK                  0x02000000L
+#define RB_STENCILREFMASK__RESERVED1                       0x02000000L
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF_MASK                       0xffffffffL
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED_MASK                      0x00000001L
+#define RB_COLOR_MASK__WRITE_RED                           0x00000001L
+#define RB_COLOR_MASK__WRITE_GREEN_MASK                    0x00000002L
+#define RB_COLOR_MASK__WRITE_GREEN                         0x00000002L
+#define RB_COLOR_MASK__WRITE_BLUE_MASK                     0x00000004L
+#define RB_COLOR_MASK__WRITE_BLUE                          0x00000004L
+#define RB_COLOR_MASK__WRITE_ALPHA_MASK                    0x00000008L
+#define RB_COLOR_MASK__WRITE_ALPHA                         0x00000008L
+#define RB_COLOR_MASK__RESERVED2_MASK                      0x00000010L
+#define RB_COLOR_MASK__RESERVED2                           0x00000010L
+#define RB_COLOR_MASK__RESERVED3_MASK                      0x00000020L
+#define RB_COLOR_MASK__RESERVED3                           0x00000020L
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED_MASK                       0x000000ffL
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN_MASK                   0x000000ffL
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE_MASK                     0x000000ffL
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK                   0x000000ffL
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED_MASK                         0x000000ffL
+#define RB_FOG_COLOR__FOG_GREEN_MASK                       0x0000ff00L
+#define RB_FOG_COLOR__FOG_BLUE_MASK                        0x00ff0000L
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK           0x000000ffL
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK          0x0000ff00L
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK     0x00ff0000L
+#define RB_STENCILREFMASK_BF__RESERVED4_MASK               0x01000000L
+#define RB_STENCILREFMASK_BF__RESERVED4                    0x01000000L
+#define RB_STENCILREFMASK_BF__RESERVED5_MASK               0x02000000L
+#define RB_STENCILREFMASK_BF__RESERVED5                    0x02000000L
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK               0x00000001L
+#define RB_DEPTHCONTROL__STENCIL_ENABLE                    0x00000001L
+#define RB_DEPTHCONTROL__Z_ENABLE_MASK                     0x00000002L
+#define RB_DEPTHCONTROL__Z_ENABLE                          0x00000002L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK               0x00000004L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE                    0x00000004L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK               0x00000008L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE                    0x00000008L
+#define RB_DEPTHCONTROL__ZFUNC_MASK                        0x00000070L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK              0x00000080L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE                   0x00000080L
+#define RB_DEPTHCONTROL__STENCILFUNC_MASK                  0x00000700L
+#define RB_DEPTHCONTROL__STENCILFAIL_MASK                  0x00003800L
+#define RB_DEPTHCONTROL__STENCILZPASS_MASK                 0x0001c000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_MASK                 0x000e0000L
+#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK               0x00700000L
+#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK               0x03800000L
+#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK              0x1c000000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK              0xe0000000L
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK               0x0000001fL
+#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK               0x000000e0L
+#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK              0x00001f00L
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK               0x001f0000L
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK               0x00e00000L
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK              0x1f000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK           0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE                0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_MASK                  0x40000000L
+#define RB_BLENDCONTROL__BLEND_FORCE                       0x40000000L
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC_MASK                   0x00000007L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK            0x00000008L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE                 0x00000008L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK         0x00000010L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE              0x00000010L
+#define RB_COLORCONTROL__BLEND_DISABLE_MASK                0x00000020L
+#define RB_COLORCONTROL__BLEND_DISABLE                     0x00000020L
+#define RB_COLORCONTROL__FOG_ENABLE_MASK                   0x00000040L
+#define RB_COLORCONTROL__FOG_ENABLE                        0x00000040L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK               0x00000080L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG                    0x00000080L
+#define RB_COLORCONTROL__ROP_CODE_MASK                     0x00000f00L
+#define RB_COLORCONTROL__DITHER_MODE_MASK                  0x00003000L
+#define RB_COLORCONTROL__DITHER_TYPE_MASK                  0x0000c000L
+#define RB_COLORCONTROL__PIXEL_FOG_MASK                    0x00010000L
+#define RB_COLORCONTROL__PIXEL_FOG                         0x00010000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK        0x03000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK        0x0c000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK        0x30000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK        0xc0000000L
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE_MASK                    0x00000007L
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK           0xffffffffL
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK           0x00000007L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK           0x00000008L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE                0x00000008L
+#define RB_COPY_CONTROL__CLEAR_MASK_MASK                   0x000000f0L
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK             0xfffff000L
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK           0x000001ffL
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK           0x00000007L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK           0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR                0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK           0x000000f0L
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK             0x00000300L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK      0x00000c00L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK      0x00003000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK        0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED             0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK      0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN           0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK       0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE            0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK      0x00020000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA           0x00020000L
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK           0x00001fffL
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK           0x03ffe000L
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK                   0xffffffffL
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK       0x00000001L
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT            0x00000001L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK        0x00000002L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT             0x00000002L
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK       0xffffffffL
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK       0x00000001L
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE            0x00000001L
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK           0x00000006L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK              0x00000008L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM                   0x00000008L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH      0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK      0x00000020L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP           0x00000020L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK      0x00000040L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP           0x00000040L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK             0x00000080L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE                  0x00000080L
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK              0x00001f00L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK              0x00004000L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE                   0x00004000L
+#define RB_BC_CONTROL__CRC_MODE_MASK                       0x00008000L
+#define RB_BC_CONTROL__CRC_MODE                            0x00008000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK        0x00010000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS             0x00010000L
+#define RB_BC_CONTROL__DISABLE_ACCUM_MASK                  0x00020000L
+#define RB_BC_CONTROL__DISABLE_ACCUM                       0x00020000L
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK               0x003c0000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK      0x00400000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE           0x00400000L
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK          0x07800000L
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK      0x18000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK  0x20000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE       0x20000000L
+#define RB_BC_CONTROL__CRC_SYSTEM_MASK                     0x40000000L
+#define RB_BC_CONTROL__CRC_SYSTEM                          0x40000000L
+#define RB_BC_CONTROL__RESERVED6_MASK                      0x80000000L
+#define RB_BC_CONTROL__RESERVED6                           0x80000000L
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE_MASK                     0x0000000fL
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK             0x00000030L
+#define RB_EDRAM_INFO__EDRAM_RANGE_MASK                    0xffffc000L
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA_MASK                      0xffffffffL
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK                0x00000001L
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE                     0x00000001L
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK_MASK                         0xffffffffL
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK               0xffffffffL
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK               0xffffffffL
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK             0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL                  0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK             0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL                  0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK             0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL                  0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK             0x00000008L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL                  0x00000008L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK            0x00000010L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL                 0x00000010L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK            0x00000020L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL                 0x00000020L
+#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK                     0x00000040L
+#define RB_DEBUG_0__RDREQ_Z1_FULL                          0x00000040L
+#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK                     0x00000080L
+#define RB_DEBUG_0__RDREQ_Z0_FULL                          0x00000080L
+#define RB_DEBUG_0__RDREQ_C1_FULL_MASK                     0x00000100L
+#define RB_DEBUG_0__RDREQ_C1_FULL                          0x00000100L
+#define RB_DEBUG_0__RDREQ_C0_FULL_MASK                     0x00000200L
+#define RB_DEBUG_0__RDREQ_C0_FULL                          0x00000200L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK            0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL                 0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK            0x00000800L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL                 0x00000800L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK            0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL                 0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK            0x00002000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL                 0x00002000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK                0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL                     0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK                0x00008000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL                     0x00008000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK                     0x00010000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL                          0x00010000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK                     0x00020000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL                          0x00020000L
+#define RB_DEBUG_0__WRREQ_C1_FULL_MASK                     0x00040000L
+#define RB_DEBUG_0__WRREQ_C1_FULL                          0x00040000L
+#define RB_DEBUG_0__WRREQ_C0_FULL_MASK                     0x00080000L
+#define RB_DEBUG_0__WRREQ_C0_FULL                          0x00080000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK              0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL                   0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK              0x00200000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL                   0x00200000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK              0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL                   0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK              0x00800000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL                   0x00800000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK           0x01000000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL                0x01000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK           0x02000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL                0x02000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL_MASK                     0x04000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL                          0x04000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL_MASK                     0x08000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL                          0x08000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK                    0x10000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL                         0x10000000L
+#define RB_DEBUG_0__C_REQ_FULL_MASK                        0x20000000L
+#define RB_DEBUG_0__C_REQ_FULL                             0x20000000L
+#define RB_DEBUG_0__C_MASK_FULL_MASK                       0x40000000L
+#define RB_DEBUG_0__C_MASK_FULL                            0x40000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK                   0x80000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL                        0x80000000L
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK                0x00000001L
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY                     0x00000001L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK                0x00000002L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY                     0x00000002L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK                0x00000004L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY                     0x00000004L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK                0x00000008L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY                     0x00000008L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK           0x00000010L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY                0x00000010L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK           0x00000020L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY                0x00000020L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK                    0x00000040L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY                         0x00000040L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK                    0x00000080L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY                         0x00000080L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK                    0x00000100L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY                         0x00000100L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK                    0x00000200L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY                         0x00000200L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK           0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY                0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK           0x00000800L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY                0x00000800L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK           0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY                0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK           0x00002000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY                0x00002000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK               0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY                    0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK               0x00008000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY                    0x00008000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK                    0x00010000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY                         0x00010000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK                    0x00020000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY                         0x00020000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK                0x00040000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY                     0x00040000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK                0x00080000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY                     0x00080000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK             0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY                  0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY                  0x00200000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY                  0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK             0x00800000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY                  0x00800000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK          0x01000000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY               0x01000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK          0x02000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY               0x02000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK                    0x04000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY                         0x04000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK                    0x08000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY                         0x08000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK                   0x10000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY                        0x10000000L
+#define RB_DEBUG_1__C_REQ_EMPTY_MASK                       0x20000000L
+#define RB_DEBUG_1__C_REQ_EMPTY                            0x20000000L
+#define RB_DEBUG_1__C_MASK_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_1__C_MASK_EMPTY                           0x40000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK                  0x80000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY                       0x80000000L
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK                   0x0000000fL
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK                 0x000007f0L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK                   0x00000800L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG                        0x00000800L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK                 0x00001000L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG                      0x00001000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK                0x00002000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT                     0x00002000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK                   0x00004000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL                        0x00004000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK                0x00008000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL                     0x00008000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK                0x00010000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL                     0x00010000L
+#define RB_DEBUG_2__Z0_MASK_FULL_MASK                      0x00020000L
+#define RB_DEBUG_2__Z0_MASK_FULL                           0x00020000L
+#define RB_DEBUG_2__Z1_MASK_FULL_MASK                      0x00040000L
+#define RB_DEBUG_2__Z1_MASK_FULL                           0x00040000L
+#define RB_DEBUG_2__Z0_REQ_FULL_MASK                       0x00080000L
+#define RB_DEBUG_2__Z0_REQ_FULL                            0x00080000L
+#define RB_DEBUG_2__Z1_REQ_FULL_MASK                       0x00100000L
+#define RB_DEBUG_2__Z1_REQ_FULL                            0x00100000L
+#define RB_DEBUG_2__Z_SAMP_FULL_MASK                       0x00200000L
+#define RB_DEBUG_2__Z_SAMP_FULL                            0x00200000L
+#define RB_DEBUG_2__Z_TILE_FULL_MASK                       0x00400000L
+#define RB_DEBUG_2__Z_TILE_FULL                            0x00400000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK                  0x00800000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY                       0x00800000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK               0x01000000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY                    0x01000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK               0x02000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY                    0x02000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK                     0x04000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY                          0x04000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK                     0x08000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY                          0x08000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK                      0x10000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY                           0x10000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK                      0x20000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY                           0x20000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY                           0x40000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY_MASK                      0x80000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY                           0x80000000L
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID_MASK                       0x0000000fL
+#define RB_DEBUG_3__ACCUM_FLUSHING_MASK                    0x000000f0L
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK           0x00003f00L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK             0x00004000L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID                  0x00004000L
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK               0x00078000L
+#define RB_DEBUG_3__SHD_FULL_MASK                          0x00080000L
+#define RB_DEBUG_3__SHD_FULL                               0x00080000L
+#define RB_DEBUG_3__SHD_EMPTY_MASK                         0x00100000L
+#define RB_DEBUG_3__SHD_EMPTY                              0x00100000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY                  0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY                  0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK              0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL                   0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK              0x01000000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL                   0x01000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK                  0x02000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY                       0x02000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK                  0x04000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY                       0x04000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK                   0x08000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL                        0x08000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK                   0x10000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL                        0x10000000L
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK               0x00000001L
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG                    0x00000001L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK               0x00000002L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG                    0x00000002L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK             0x00000004L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG                  0x00000004L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK             0x00000008L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG                  0x00000008L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK             0x00000010L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY                  0x00000010L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK            0x00000020L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY                 0x00000020L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK              0x00000040L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL                   0x00000040L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK             0x00000080L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL                  0x00000080L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK       0x00000100L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW            0x00000100L
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK               0x00001e00L
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK             0x00000001L
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR                  0x00000001L
+
+// RB_BC_SPARES
+#define RB_BC_SPARES__RESERVED_MASK                        0xffffffffL
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP   0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK     0x00000600L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h
new file mode 100644
index 000000000000..83be5f82ed8c
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h
@@ -0,0 +1,591 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _yamato_OFFSET_HEADER
+#define _yamato_OFFSET_HEADER
+
+
+// Registers from PA block
+
+#define mmPA_CL_VPORT_XSCALE           0x210F
+#define mmPA_CL_VPORT_XOFFSET          0x2110
+#define mmPA_CL_VPORT_YSCALE           0x2111
+#define mmPA_CL_VPORT_YOFFSET          0x2112
+#define mmPA_CL_VPORT_ZSCALE           0x2113
+#define mmPA_CL_VPORT_ZOFFSET          0x2114
+#define mmPA_CL_VTE_CNTL               0x2206
+#define mmPA_CL_CLIP_CNTL              0x2204
+#define mmPA_CL_GB_VERT_CLIP_ADJ       0x2303
+#define mmPA_CL_GB_VERT_DISC_ADJ       0x2304
+#define mmPA_CL_GB_HORZ_CLIP_ADJ       0x2305
+#define mmPA_CL_GB_HORZ_DISC_ADJ       0x2306
+#define mmPA_CL_ENHANCE                0x0C85
+#define mmPA_SC_ENHANCE                0x0CA5
+#define mmPA_SU_VTX_CNTL               0x2302
+#define mmPA_SU_POINT_SIZE             0x2280
+#define mmPA_SU_POINT_MINMAX           0x2281
+#define mmPA_SU_LINE_CNTL              0x2282
+#define mmPA_SU_FACE_DATA              0x0C86
+#define mmPA_SU_SC_MODE_CNTL           0x2205
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383
+#define mmPA_SU_PERFCOUNTER0_SELECT    0x0C88
+#define mmPA_SU_PERFCOUNTER1_SELECT    0x0C89
+#define mmPA_SU_PERFCOUNTER2_SELECT    0x0C8A
+#define mmPA_SU_PERFCOUNTER3_SELECT    0x0C8B
+#define mmPA_SU_PERFCOUNTER0_LOW       0x0C8C
+#define mmPA_SU_PERFCOUNTER0_HI        0x0C8D
+#define mmPA_SU_PERFCOUNTER1_LOW       0x0C8E
+#define mmPA_SU_PERFCOUNTER1_HI        0x0C8F
+#define mmPA_SU_PERFCOUNTER2_LOW       0x0C90
+#define mmPA_SU_PERFCOUNTER2_HI        0x0C91
+#define mmPA_SU_PERFCOUNTER3_LOW       0x0C92
+#define mmPA_SU_PERFCOUNTER3_HI        0x0C93
+#define mmPA_SC_WINDOW_OFFSET          0x2080
+#define mmPA_SC_AA_CONFIG              0x2301
+#define mmPA_SC_AA_MASK                0x2312
+#define mmPA_SC_LINE_STIPPLE           0x2283
+#define mmPA_SC_LINE_CNTL              0x2300
+#define mmPA_SC_WINDOW_SCISSOR_TL      0x2081
+#define mmPA_SC_WINDOW_SCISSOR_BR      0x2082
+#define mmPA_SC_SCREEN_SCISSOR_TL      0x200E
+#define mmPA_SC_SCREEN_SCISSOR_BR      0x200F
+#define mmPA_SC_VIZ_QUERY              0x2293
+#define mmPA_SC_VIZ_QUERY_STATUS       0x0C44
+#define mmPA_SC_LINE_STIPPLE_STATE     0x0C40
+#define mmPA_SC_PERFCOUNTER0_SELECT    0x0C98
+#define mmPA_SC_PERFCOUNTER0_LOW       0x0C99
+#define mmPA_SC_PERFCOUNTER0_HI        0x0C9A
+#define mmPA_CL_CNTL_STATUS            0x0C84
+#define mmPA_SU_CNTL_STATUS            0x0C94
+#define mmPA_SC_CNTL_STATUS            0x0CA4
+#define mmPA_SU_DEBUG_CNTL             0x0C80
+#define mmPA_SU_DEBUG_DATA             0x0C81
+#define mmPA_SC_DEBUG_CNTL             0x0C82
+#define mmPA_SC_DEBUG_DATA             0x0C83
+
+
+// Registers from VGT block
+
+#define mmGFX_COPY_STATE               0x21F4
+#define mmVGT_DRAW_INITIATOR           0x21FC
+#define mmVGT_EVENT_INITIATOR          0x21F9
+#define mmVGT_DMA_BASE                 0x21FA
+#define mmVGT_DMA_SIZE                 0x21FB
+#define mmVGT_BIN_BASE                 0x21FE
+#define mmVGT_BIN_SIZE                 0x21FF
+#define mmVGT_CURRENT_BIN_ID_MIN       0x2207
+#define mmVGT_CURRENT_BIN_ID_MAX       0x2203
+#define mmVGT_IMMED_DATA               0x21FD
+#define mmVGT_MAX_VTX_INDX             0x2100
+#define mmVGT_MIN_VTX_INDX             0x2101
+#define mmVGT_INDX_OFFSET              0x2102
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL  0x2316
+#define mmVGT_OUT_DEALLOC_CNTL         0x2317
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103
+#define mmVGT_ENHANCE                  0x2294
+#define mmVGT_VTX_VECT_EJECT_REG       0x0C2C
+#define mmVGT_LAST_COPY_STATE          0x0C30
+#define mmVGT_DEBUG_CNTL               0x0C38
+#define mmVGT_DEBUG_DATA               0x0C39
+#define mmVGT_CNTL_STATUS              0x0C3C
+#define mmVGT_CRC_SQ_DATA              0x0C3A
+#define mmVGT_CRC_SQ_CTRL              0x0C3B
+#define mmVGT_PERFCOUNTER0_SELECT      0x0C48
+#define mmVGT_PERFCOUNTER1_SELECT      0x0C49
+#define mmVGT_PERFCOUNTER2_SELECT      0x0C4A
+#define mmVGT_PERFCOUNTER3_SELECT      0x0C4B
+#define mmVGT_PERFCOUNTER0_LOW         0x0C4C
+#define mmVGT_PERFCOUNTER1_LOW         0x0C4E
+#define mmVGT_PERFCOUNTER2_LOW         0x0C50
+#define mmVGT_PERFCOUNTER3_LOW         0x0C52
+#define mmVGT_PERFCOUNTER0_HI          0x0C4D
+#define mmVGT_PERFCOUNTER1_HI          0x0C4F
+#define mmVGT_PERFCOUNTER2_HI          0x0C51
+#define mmVGT_PERFCOUNTER3_HI          0x0C53
+
+
+// Registers from TP block
+
+#define mmTC_CNTL_STATUS               0x0E00
+#define mmTCR_CHICKEN                  0x0E02
+#define mmTCF_CHICKEN                  0x0E03
+#define mmTCM_CHICKEN                  0x0E04
+#define mmTCR_PERFCOUNTER0_SELECT      0x0E05
+#define mmTCR_PERFCOUNTER1_SELECT      0x0E08
+#define mmTCR_PERFCOUNTER0_HI          0x0E06
+#define mmTCR_PERFCOUNTER1_HI          0x0E09
+#define mmTCR_PERFCOUNTER0_LOW         0x0E07
+#define mmTCR_PERFCOUNTER1_LOW         0x0E0A
+#define mmTP_TC_CLKGATE_CNTL           0x0E17
+#define mmTPC_CNTL_STATUS              0x0E18
+#define mmTPC_DEBUG0                   0x0E19
+#define mmTPC_DEBUG1                   0x0E1A
+#define mmTPC_CHICKEN                  0x0E1B
+#define mmTP0_CNTL_STATUS              0x0E1C
+#define mmTP0_DEBUG                    0x0E1D
+#define mmTP0_CHICKEN                  0x0E1E
+#define mmTP0_PERFCOUNTER0_SELECT      0x0E1F
+#define mmTP0_PERFCOUNTER0_HI          0x0E20
+#define mmTP0_PERFCOUNTER0_LOW         0x0E21
+#define mmTP0_PERFCOUNTER1_SELECT      0x0E22
+#define mmTP0_PERFCOUNTER1_HI          0x0E23
+#define mmTP0_PERFCOUNTER1_LOW         0x0E24
+#define mmTCM_PERFCOUNTER0_SELECT      0x0E54
+#define mmTCM_PERFCOUNTER1_SELECT      0x0E57
+#define mmTCM_PERFCOUNTER0_HI          0x0E55
+#define mmTCM_PERFCOUNTER1_HI          0x0E58
+#define mmTCM_PERFCOUNTER0_LOW         0x0E56
+#define mmTCM_PERFCOUNTER1_LOW         0x0E59
+#define mmTCF_PERFCOUNTER0_SELECT      0x0E5A
+#define mmTCF_PERFCOUNTER1_SELECT      0x0E5D
+#define mmTCF_PERFCOUNTER2_SELECT      0x0E60
+#define mmTCF_PERFCOUNTER3_SELECT      0x0E63
+#define mmTCF_PERFCOUNTER4_SELECT      0x0E66
+#define mmTCF_PERFCOUNTER5_SELECT      0x0E69
+#define mmTCF_PERFCOUNTER6_SELECT      0x0E6C
+#define mmTCF_PERFCOUNTER7_SELECT      0x0E6F
+#define mmTCF_PERFCOUNTER8_SELECT      0x0E72
+#define mmTCF_PERFCOUNTER9_SELECT      0x0E75
+#define mmTCF_PERFCOUNTER10_SELECT     0x0E78
+#define mmTCF_PERFCOUNTER11_SELECT     0x0E7B
+#define mmTCF_PERFCOUNTER0_HI          0x0E5B
+#define mmTCF_PERFCOUNTER1_HI          0x0E5E
+#define mmTCF_PERFCOUNTER2_HI          0x0E61
+#define mmTCF_PERFCOUNTER3_HI          0x0E64
+#define mmTCF_PERFCOUNTER4_HI          0x0E67
+#define mmTCF_PERFCOUNTER5_HI          0x0E6A
+#define mmTCF_PERFCOUNTER6_HI          0x0E6D
+#define mmTCF_PERFCOUNTER7_HI          0x0E70
+#define mmTCF_PERFCOUNTER8_HI          0x0E73
+#define mmTCF_PERFCOUNTER9_HI          0x0E76
+#define mmTCF_PERFCOUNTER10_HI         0x0E79
+#define mmTCF_PERFCOUNTER11_HI         0x0E7C
+#define mmTCF_PERFCOUNTER0_LOW         0x0E5C
+#define mmTCF_PERFCOUNTER1_LOW         0x0E5F
+#define mmTCF_PERFCOUNTER2_LOW         0x0E62
+#define mmTCF_PERFCOUNTER3_LOW         0x0E65
+#define mmTCF_PERFCOUNTER4_LOW         0x0E68
+#define mmTCF_PERFCOUNTER5_LOW         0x0E6B
+#define mmTCF_PERFCOUNTER6_LOW         0x0E6E
+#define mmTCF_PERFCOUNTER7_LOW         0x0E71
+#define mmTCF_PERFCOUNTER8_LOW         0x0E74
+#define mmTCF_PERFCOUNTER9_LOW         0x0E77
+#define mmTCF_PERFCOUNTER10_LOW        0x0E7A
+#define mmTCF_PERFCOUNTER11_LOW        0x0E7D
+#define mmTCF_DEBUG                    0x0EC0
+#define mmTCA_FIFO_DEBUG               0x0EC1
+#define mmTCA_PROBE_DEBUG              0x0EC2
+#define mmTCA_TPC_DEBUG                0x0EC3
+#define mmTCB_CORE_DEBUG               0x0EC4
+#define mmTCB_TAG0_DEBUG               0x0EC5
+#define mmTCB_TAG1_DEBUG               0x0EC6
+#define mmTCB_TAG2_DEBUG               0x0EC7
+#define mmTCB_TAG3_DEBUG               0x0EC8
+#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9
+#define mmTCB_FETCH_GEN_WALKER_DEBUG   0x0ECB
+#define mmTCB_FETCH_GEN_PIPE0_DEBUG    0x0ECC
+#define mmTCD_INPUT0_DEBUG             0x0ED0
+#define mmTCD_DEGAMMA_DEBUG            0x0ED4
+#define mmTCD_DXTMUX_SCTARB_DEBUG      0x0ED5
+#define mmTCD_DXTC_ARB_DEBUG           0x0ED6
+#define mmTCD_STALLS_DEBUG             0x0ED7
+#define mmTCO_STALLS_DEBUG             0x0EE0
+#define mmTCO_QUAD0_DEBUG0             0x0EE1
+#define mmTCO_QUAD0_DEBUG1             0x0EE2
+
+
+// Registers from TC block
+
+
+
+// Registers from SQ block
+
+#define mmSQ_GPR_MANAGEMENT            0x0D00
+#define mmSQ_FLOW_CONTROL              0x0D01
+#define mmSQ_INST_STORE_MANAGMENT      0x0D02
+#define mmSQ_RESOURCE_MANAGMENT        0x0D03
+#define mmSQ_EO_RT                     0x0D04
+#define mmSQ_DEBUG_MISC                0x0D05
+#define mmSQ_ACTIVITY_METER_CNTL       0x0D06
+#define mmSQ_ACTIVITY_METER_STATUS     0x0D07
+#define mmSQ_INPUT_ARB_PRIORITY        0x0D08
+#define mmSQ_THREAD_ARB_PRIORITY       0x0D09
+#define mmSQ_VS_WATCHDOG_TIMER         0x0D0A
+#define mmSQ_PS_WATCHDOG_TIMER         0x0D0B
+#define mmSQ_INT_CNTL                  0x0D34
+#define mmSQ_INT_STATUS                0x0D35
+#define mmSQ_INT_ACK                   0x0D36
+#define mmSQ_DEBUG_INPUT_FSM           0x0DAE
+#define mmSQ_DEBUG_CONST_MGR_FSM       0x0DAF
+#define mmSQ_DEBUG_TP_FSM              0x0DB0
+#define mmSQ_DEBUG_FSM_ALU_0           0x0DB1
+#define mmSQ_DEBUG_FSM_ALU_1           0x0DB2
+#define mmSQ_DEBUG_EXP_ALLOC           0x0DB3
+#define mmSQ_DEBUG_PTR_BUFF            0x0DB4
+#define mmSQ_DEBUG_GPR_VTX             0x0DB5
+#define mmSQ_DEBUG_GPR_PIX             0x0DB6
+#define mmSQ_DEBUG_TB_STATUS_SEL       0x0DB7
+#define mmSQ_DEBUG_VTX_TB_0            0x0DB8
+#define mmSQ_DEBUG_VTX_TB_1            0x0DB9
+#define mmSQ_DEBUG_VTX_TB_STATUS_REG   0x0DBA
+#define mmSQ_DEBUG_VTX_TB_STATE_MEM    0x0DBB
+#define mmSQ_DEBUG_PIX_TB_0            0x0DBC
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0
+#define mmSQ_DEBUG_PIX_TB_STATE_MEM    0x0DC1
+#define mmSQ_PERFCOUNTER0_SELECT       0x0DC8
+#define mmSQ_PERFCOUNTER1_SELECT       0x0DC9
+#define mmSQ_PERFCOUNTER2_SELECT       0x0DCA
+#define mmSQ_PERFCOUNTER3_SELECT       0x0DCB
+#define mmSQ_PERFCOUNTER0_LOW          0x0DCC
+#define mmSQ_PERFCOUNTER0_HI           0x0DCD
+#define mmSQ_PERFCOUNTER1_LOW          0x0DCE
+#define mmSQ_PERFCOUNTER1_HI           0x0DCF
+#define mmSQ_PERFCOUNTER2_LOW          0x0DD0
+#define mmSQ_PERFCOUNTER2_HI           0x0DD1
+#define mmSQ_PERFCOUNTER3_LOW          0x0DD2
+#define mmSQ_PERFCOUNTER3_HI           0x0DD3
+#define mmSX_PERFCOUNTER0_SELECT       0x0DD4
+#define mmSX_PERFCOUNTER0_LOW          0x0DD8
+#define mmSX_PERFCOUNTER0_HI           0x0DD9
+#define mmSQ_INSTRUCTION_ALU_0         0x5000
+#define mmSQ_INSTRUCTION_ALU_1         0x5001
+#define mmSQ_INSTRUCTION_ALU_2         0x5002
+#define mmSQ_INSTRUCTION_CF_EXEC_0     0x5080
+#define mmSQ_INSTRUCTION_CF_EXEC_1     0x5081
+#define mmSQ_INSTRUCTION_CF_EXEC_2     0x5082
+#define mmSQ_INSTRUCTION_CF_LOOP_0     0x5083
+#define mmSQ_INSTRUCTION_CF_LOOP_1     0x5084
+#define mmSQ_INSTRUCTION_CF_LOOP_2     0x5085
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088
+#define mmSQ_INSTRUCTION_CF_ALLOC_0    0x5089
+#define mmSQ_INSTRUCTION_CF_ALLOC_1    0x508A
+#define mmSQ_INSTRUCTION_CF_ALLOC_2    0x508B
+#define mmSQ_INSTRUCTION_TFETCH_0      0x5043
+#define mmSQ_INSTRUCTION_TFETCH_1      0x5044
+#define mmSQ_INSTRUCTION_TFETCH_2      0x5045
+#define mmSQ_INSTRUCTION_VFETCH_0      0x5040
+#define mmSQ_INSTRUCTION_VFETCH_1      0x5041
+#define mmSQ_INSTRUCTION_VFETCH_2      0x5042
+#define mmSQ_CONSTANT_0                0x4000
+#define mmSQ_CONSTANT_1                0x4001
+#define mmSQ_CONSTANT_2                0x4002
+#define mmSQ_CONSTANT_3                0x4003
+#define mmSQ_FETCH_0                   0x4800
+#define mmSQ_FETCH_1                   0x4801
+#define mmSQ_FETCH_2                   0x4802
+#define mmSQ_FETCH_3                   0x4803
+#define mmSQ_FETCH_4                   0x4804
+#define mmSQ_FETCH_5                   0x4805
+#define mmSQ_CONSTANT_VFETCH_0         0x4806
+#define mmSQ_CONSTANT_VFETCH_1         0x4808
+#define mmSQ_CONSTANT_T2               0x480C
+#define mmSQ_CONSTANT_T3               0x4812
+#define mmSQ_CF_BOOLEANS               0x4900
+#define mmSQ_CF_LOOP                   0x4908
+#define mmSQ_CONSTANT_RT_0             0x4940
+#define mmSQ_CONSTANT_RT_1             0x4941
+#define mmSQ_CONSTANT_RT_2             0x4942
+#define mmSQ_CONSTANT_RT_3             0x4943
+#define mmSQ_FETCH_RT_0                0x4D40
+#define mmSQ_FETCH_RT_1                0x4D41
+#define mmSQ_FETCH_RT_2                0x4D42
+#define mmSQ_FETCH_RT_3                0x4D43
+#define mmSQ_FETCH_RT_4                0x4D44
+#define mmSQ_FETCH_RT_5                0x4D45
+#define mmSQ_CF_RT_BOOLEANS            0x4E00
+#define mmSQ_CF_RT_LOOP                0x4E14
+#define mmSQ_VS_PROGRAM                0x21F7
+#define mmSQ_PS_PROGRAM                0x21F6
+#define mmSQ_CF_PROGRAM_SIZE           0x2315
+#define mmSQ_INTERPOLATOR_CNTL         0x2182
+#define mmSQ_PROGRAM_CNTL              0x2180
+#define mmSQ_WRAPPING_0                0x2183
+#define mmSQ_WRAPPING_1                0x2184
+#define mmSQ_VS_CONST                  0x2307
+#define mmSQ_PS_CONST                  0x2308
+#define mmSQ_CONTEXT_MISC              0x2181
+#define mmSQ_CF_RD_BASE                0x21F5
+#define mmSQ_DEBUG_MISC_0              0x2309
+#define mmSQ_DEBUG_MISC_1              0x230A
+
+
+// Registers from SX block
+
+
+
+// Registers from MH block
+
+#define mmMH_ARBITER_CONFIG            0x0A40
+#define mmMH_CLNT_AXI_ID_REUSE         0x0A41
+#define mmMH_INTERRUPT_MASK            0x0A42
+#define mmMH_INTERRUPT_STATUS          0x0A43
+#define mmMH_INTERRUPT_CLEAR           0x0A44
+#define mmMH_AXI_ERROR                 0x0A45
+#define mmMH_PERFCOUNTER0_SELECT       0x0A46
+#define mmMH_PERFCOUNTER1_SELECT       0x0A4A
+#define mmMH_PERFCOUNTER0_CONFIG       0x0A47
+#define mmMH_PERFCOUNTER1_CONFIG       0x0A4B
+#define mmMH_PERFCOUNTER0_LOW          0x0A48
+#define mmMH_PERFCOUNTER1_LOW          0x0A4C
+#define mmMH_PERFCOUNTER0_HI           0x0A49
+#define mmMH_PERFCOUNTER1_HI           0x0A4D
+#define mmMH_DEBUG_CTRL                0x0A4E
+#define mmMH_DEBUG_DATA                0x0A4F
+#define mmMH_AXI_HALT_CONTROL          0x0A50
+#define mmMH_MMU_CONFIG                0x0040
+#define mmMH_MMU_VA_RANGE              0x0041
+#define mmMH_MMU_PT_BASE               0x0042
+#define mmMH_MMU_PAGE_FAULT            0x0043
+#define mmMH_MMU_TRAN_ERROR            0x0044
+#define mmMH_MMU_INVALIDATE            0x0045
+#define mmMH_MMU_MPU_BASE              0x0046
+#define mmMH_MMU_MPU_END               0x0047
+
+
+// Registers from RBBM block
+
+#define mmWAIT_UNTIL                   0x05C8
+#define mmRBBM_ISYNC_CNTL              0x05C9
+#define mmRBBM_STATUS                  0x05D0
+#define mmRBBM_DSPLY                   0x0391
+#define mmRBBM_RENDER_LATEST           0x0392
+#define mmRBBM_RTL_RELEASE             0x0000
+#define mmRBBM_PATCH_RELEASE           0x0001
+#define mmRBBM_AUXILIARY_CONFIG        0x0002
+#define mmRBBM_PERIPHID0               0x03F8
+#define mmRBBM_PERIPHID1               0x03F9
+#define mmRBBM_PERIPHID2               0x03FA
+#define mmRBBM_PERIPHID3               0x03FB
+#define mmRBBM_CNTL                    0x003B
+#define mmRBBM_SKEW_CNTL               0x003D
+#define mmRBBM_SOFT_RESET              0x003C
+#define mmRBBM_PM_OVERRIDE1            0x039C
+#define mmRBBM_PM_OVERRIDE2            0x039D
+#define mmGC_SYS_IDLE                  0x039E
+#define mmNQWAIT_UNTIL                 0x0394
+#define mmRBBM_DEBUG_OUT               0x03A0
+#define mmRBBM_DEBUG_CNTL              0x03A1
+#define mmRBBM_DEBUG                   0x039B
+#define mmRBBM_READ_ERROR              0x03B3
+#define mmRBBM_WAIT_IDLE_CLOCKS        0x03B2
+#define mmRBBM_INT_CNTL                0x03B4
+#define mmRBBM_INT_STATUS              0x03B5
+#define mmRBBM_INT_ACK                 0x03B6
+#define mmMASTER_INT_SIGNAL            0x03B7
+#define mmRBBM_PERFCOUNTER1_SELECT     0x0395
+#define mmRBBM_PERFCOUNTER1_LO         0x0397
+#define mmRBBM_PERFCOUNTER1_HI         0x0398
+
+
+// Registers from CP block
+
+#define mmCP_RB_BASE                   0x01C0
+#define mmCP_RB_CNTL                   0x01C1
+#define mmCP_RB_RPTR_ADDR              0x01C3
+#define mmCP_RB_RPTR                   0x01C4
+#define mmCP_RB_RPTR_WR                0x01C7
+#define mmCP_RB_WPTR                   0x01C5
+#define mmCP_RB_WPTR_DELAY             0x01C6
+#define mmCP_RB_WPTR_BASE              0x01C8
+#define mmCP_IB1_BASE                  0x0458
+#define mmCP_IB1_BUFSZ                 0x0459
+#define mmCP_IB2_BASE                  0x045A
+#define mmCP_IB2_BUFSZ                 0x045B
+#define mmCP_ST_BASE                   0x044D
+#define mmCP_ST_BUFSZ                  0x044E
+#define mmCP_QUEUE_THRESHOLDS          0x01D5
+#define mmCP_MEQ_THRESHOLDS            0x01D6
+#define mmCP_CSQ_AVAIL                 0x01D7
+#define mmCP_STQ_AVAIL                 0x01D8
+#define mmCP_MEQ_AVAIL                 0x01D9
+#define mmCP_CSQ_RB_STAT               0x01FD
+#define mmCP_CSQ_IB1_STAT              0x01FE
+#define mmCP_CSQ_IB2_STAT              0x01FF
+#define mmCP_NON_PREFETCH_CNTRS        0x0440
+#define mmCP_STQ_ST_STAT               0x0443
+#define mmCP_MEQ_STAT                  0x044F
+#define mmCP_MIU_TAG_STAT              0x0452
+#define mmCP_CMD_INDEX                 0x01DA
+#define mmCP_CMD_DATA                  0x01DB
+#define mmCP_ME_CNTL                   0x01F6
+#define mmCP_ME_STATUS                 0x01F7
+#define mmCP_ME_RAM_WADDR              0x01F8
+#define mmCP_ME_RAM_RADDR              0x01F9
+#define mmCP_ME_RAM_DATA               0x01FA
+#define mmCP_ME_RDADDR                 0x01EA
+#define mmCP_DEBUG                     0x01FC
+#define mmSCRATCH_REG0                 0x0578
+#define mmGUI_SCRATCH_REG0             0x0578
+#define mmSCRATCH_REG1                 0x0579
+#define mmGUI_SCRATCH_REG1             0x0579
+#define mmSCRATCH_REG2                 0x057A
+#define mmGUI_SCRATCH_REG2             0x057A
+#define mmSCRATCH_REG3                 0x057B
+#define mmGUI_SCRATCH_REG3             0x057B
+#define mmSCRATCH_REG4                 0x057C
+#define mmGUI_SCRATCH_REG4             0x057C
+#define mmSCRATCH_REG5                 0x057D
+#define mmGUI_SCRATCH_REG5             0x057D
+#define mmSCRATCH_REG6                 0x057E
+#define mmGUI_SCRATCH_REG6             0x057E
+#define mmSCRATCH_REG7                 0x057F
+#define mmGUI_SCRATCH_REG7             0x057F
+#define mmSCRATCH_UMSK                 0x01DC
+#define mmSCRATCH_ADDR                 0x01DD
+#define mmCP_ME_VS_EVENT_SRC           0x0600
+#define mmCP_ME_VS_EVENT_ADDR          0x0601
+#define mmCP_ME_VS_EVENT_DATA          0x0602
+#define mmCP_ME_VS_EVENT_ADDR_SWM      0x0603
+#define mmCP_ME_VS_EVENT_DATA_SWM      0x0604
+#define mmCP_ME_PS_EVENT_SRC           0x0605
+#define mmCP_ME_PS_EVENT_ADDR          0x0606
+#define mmCP_ME_PS_EVENT_DATA          0x0607
+#define mmCP_ME_PS_EVENT_ADDR_SWM      0x0608
+#define mmCP_ME_PS_EVENT_DATA_SWM      0x0609
+#define mmCP_ME_CF_EVENT_SRC           0x060A
+#define mmCP_ME_CF_EVENT_ADDR          0x060B
+#define mmCP_ME_CF_EVENT_DATA          0x060C
+#define mmCP_ME_NRT_ADDR               0x060D
+#define mmCP_ME_NRT_DATA               0x060E
+#define mmCP_ME_VS_FETCH_DONE_SRC      0x0612
+#define mmCP_ME_VS_FETCH_DONE_ADDR     0x0613
+#define mmCP_ME_VS_FETCH_DONE_DATA     0x0614
+#define mmCP_INT_CNTL                  0x01F2
+#define mmCP_INT_STATUS                0x01F3
+#define mmCP_INT_ACK                   0x01F4
+#define mmCP_PFP_UCODE_ADDR            0x00C0
+#define mmCP_PFP_UCODE_DATA            0x00C1
+#define mmCP_PERFMON_CNTL              0x0444
+#define mmCP_PERFCOUNTER_SELECT        0x0445
+#define mmCP_PERFCOUNTER_LO            0x0446
+#define mmCP_PERFCOUNTER_HI            0x0447
+#define mmCP_BIN_MASK_LO               0x0454
+#define mmCP_BIN_MASK_HI               0x0455
+#define mmCP_BIN_SELECT_LO             0x0456
+#define mmCP_BIN_SELECT_HI             0x0457
+#define mmCP_NV_FLAGS_0                0x01EE
+#define mmCP_NV_FLAGS_1                0x01EF
+#define mmCP_NV_FLAGS_2                0x01F0
+#define mmCP_NV_FLAGS_3                0x01F1
+#define mmCP_STATE_DEBUG_INDEX         0x01EC
+#define mmCP_STATE_DEBUG_DATA          0x01ED
+#define mmCP_PROG_COUNTER              0x044B
+#define mmCP_STAT                      0x047F
+#define mmBIOS_0_SCRATCH               0x0004
+#define mmBIOS_1_SCRATCH               0x0005
+#define mmBIOS_2_SCRATCH               0x0006
+#define mmBIOS_3_SCRATCH               0x0007
+#define mmBIOS_4_SCRATCH               0x0008
+#define mmBIOS_5_SCRATCH               0x0009
+#define mmBIOS_6_SCRATCH               0x000A
+#define mmBIOS_7_SCRATCH               0x000B
+#define mmBIOS_8_SCRATCH               0x0580
+#define mmBIOS_9_SCRATCH               0x0581
+#define mmBIOS_10_SCRATCH              0x0582
+#define mmBIOS_11_SCRATCH              0x0583
+#define mmBIOS_12_SCRATCH              0x0584
+#define mmBIOS_13_SCRATCH              0x0585
+#define mmBIOS_14_SCRATCH              0x0586
+#define mmBIOS_15_SCRATCH              0x0587
+#define mmCOHER_SIZE_PM4               0x0A29
+#define mmCOHER_BASE_PM4               0x0A2A
+#define mmCOHER_STATUS_PM4             0x0A2B
+#define mmCOHER_SIZE_HOST              0x0A2F
+#define mmCOHER_BASE_HOST              0x0A30
+#define mmCOHER_STATUS_HOST            0x0A31
+#define mmCOHER_DEST_BASE_0            0x2006
+#define mmCOHER_DEST_BASE_1            0x2007
+#define mmCOHER_DEST_BASE_2            0x2008
+#define mmCOHER_DEST_BASE_3            0x2009
+#define mmCOHER_DEST_BASE_4            0x200A
+#define mmCOHER_DEST_BASE_5            0x200B
+#define mmCOHER_DEST_BASE_6            0x200C
+#define mmCOHER_DEST_BASE_7            0x200D
+
+
+// Registers from SC block
+
+
+
+// Registers from BC block
+
+#define mmRB_SURFACE_INFO              0x2000
+#define mmRB_COLOR_INFO                0x2001
+#define mmRB_DEPTH_INFO                0x2002
+#define mmRB_STENCILREFMASK            0x210D
+#define mmRB_ALPHA_REF                 0x210E
+#define mmRB_COLOR_MASK                0x2104
+#define mmRB_BLEND_RED                 0x2105
+#define mmRB_BLEND_GREEN               0x2106
+#define mmRB_BLEND_BLUE                0x2107
+#define mmRB_BLEND_ALPHA               0x2108
+#define mmRB_FOG_COLOR                 0x2109
+#define mmRB_STENCILREFMASK_BF         0x210C
+#define mmRB_DEPTHCONTROL              0x2200
+#define mmRB_BLENDCONTROL              0x2201
+#define mmRB_COLORCONTROL              0x2202
+#define mmRB_MODECONTROL               0x2208
+#define mmRB_COLOR_DEST_MASK           0x2326
+#define mmRB_COPY_CONTROL              0x2318
+#define mmRB_COPY_DEST_BASE            0x2319
+#define mmRB_COPY_DEST_PITCH           0x231A
+#define mmRB_COPY_DEST_INFO            0x231B
+#define mmRB_COPY_DEST_PIXEL_OFFSET    0x231C
+#define mmRB_DEPTH_CLEAR               0x231D
+#define mmRB_SAMPLE_COUNT_CTL          0x2324
+#define mmRB_SAMPLE_COUNT_ADDR         0x2325
+#define mmRB_BC_CONTROL                0x0F01
+#define mmRB_EDRAM_INFO                0x0F02
+#define mmRB_CRC_RD_PORT               0x0F0C
+#define mmRB_CRC_CONTROL               0x0F0D
+#define mmRB_CRC_MASK                  0x0F0E
+#define mmRB_PERFCOUNTER0_SELECT       0x0F04
+#define mmRB_PERFCOUNTER0_LOW          0x0F08
+#define mmRB_PERFCOUNTER0_HI           0x0F09
+#define mmRB_TOTAL_SAMPLES             0x0F0F
+#define mmRB_ZPASS_SAMPLES             0x0F10
+#define mmRB_ZFAIL_SAMPLES             0x0F11
+#define mmRB_SFAIL_SAMPLES             0x0F12
+#define mmRB_DEBUG_0                   0x0F26
+#define mmRB_DEBUG_1                   0x0F27
+#define mmRB_DEBUG_2                   0x0F28
+#define mmRB_DEBUG_3                   0x0F29
+#define mmRB_DEBUG_4                   0x0F2A
+#define mmRB_FLAG_CONTROL              0x0F2B
+#define mmRB_BC_SPARES                 0x0F2C
+#define mmBC_DUMMY_CRAYRB_ENUMS        0x0F15
+#define mmBC_DUMMY_CRAYRB_MOREENUMS    0x0F16
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h
new file mode 100644
index 000000000000..17379dcfa0e7
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h
@@ -0,0 +1,223 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_RANDOM_HEADER)
+#define _yamato_RANDOM_HEADER
+
+/*************************************************************
+ * THIS FILE IS AUTOMATICALLY CREATED.  DO NOT EDIT THIS FILE.
+ *************************************************************/
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SU_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SC_PERFCNT_SELECT>;
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRIM_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SOURCE_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_FACENESS_CULL_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_INDEX_SIZE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SMALL_INDEX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRE_FETCH_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_GRP_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_EVENT_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DMA_SWAP_MODE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCR_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TP_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCM_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCF_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SQ_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SX_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Abs_modifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Exporting>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ScalarOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SwizzleType>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<InputModifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredicateSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect1>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VectorOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect0>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Ressource_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Instruction_serial>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VC_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressing>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CFOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Allocation_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexInstOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressmode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexCoordDenorm>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SrcSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DstSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MipFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<AnisoFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ArbitraryFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SampleLocation>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VertexMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Sample_Cntl>;
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MhPerfEncode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MmuClntBeh>;
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RBBM_PERFCOUNT1_SEL>;
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CP_PERFCOUNT_SEL>;
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareFrag>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareRef>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<StencilOp>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<BlendOpX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CombFuncX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherModeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherTypeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceEndian>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramSizeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RB_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceSwap>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumber>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceTiling>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumberX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArrayX>;
+
+#endif /*_yamato_RANDOM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h
new file mode 100644
index 000000000000..bcc28f133b08
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h
@@ -0,0 +1,14280 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_REG_HEADER)
+#define _yamato_REG_HEADER
+
+    union PA_CL_VPORT_XSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_XSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_XSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_XOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_XOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_XOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_YSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_YSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_YOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_YOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_ZSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_ZSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_ZOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_ZOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VTE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int                                 : 2;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                                 : 2;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CLIP_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+        unsigned int                                 : 27;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 27;
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 28;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_VTX_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PIX_CENTER : 1;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      PIX_CENTER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          HEIGHT : 16;
+        unsigned int                           WIDTH : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           WIDTH : 16;
+        unsigned int                          HEIGHT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_MINMAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_SIZE : 16;
+        unsigned int                        MAX_SIZE : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MAX_SIZE : 16;
+        unsigned int                        MIN_SIZE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           WIDTH : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                           WIDTH : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_FACE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                       BASE_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_SC_MODE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CULL_FRONT : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                            FACE : 1;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int                                 : 1;
+        unsigned int                CLAMPED_FACENESS : 1;
+        unsigned int              ZERO_AREA_FACENESS : 1;
+        unsigned int                FACE_KILL_ENABLE : 1;
+        unsigned int               FACE_WRITE_ENABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               FACE_WRITE_ENABLE : 1;
+        unsigned int                FACE_KILL_ENABLE : 1;
+        unsigned int              ZERO_AREA_FACENESS : 1;
+        unsigned int                CLAMPED_FACENESS : 1;
+        unsigned int                                 : 1;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int                            FACE : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                      CULL_FRONT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 WINDOW_X_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_X_OFFSET : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+        unsigned int                                 : 10;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 10;
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         AA_MASK : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                         AA_MASK : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    LINE_PATTERN : 16;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                                 : 4;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                    LINE_PATTERN : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BRES_CNTL : 8;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int                       BRES_CNTL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 1;
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VIZ_QUERY_ENA : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                                 : 1;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                   VIZ_QUERY_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STATUS_BITS : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     STATUS_BITS : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CURRENT_PTR : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int                     CURRENT_PTR : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         CL_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CL_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SU_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SU_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SC_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SU_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SU_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           clip_ga_bc_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int                     ALWAYS_ZERO : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 12;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_ga_bc_fifo_write : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int                     ALWAYS_ZERO : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 8;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO1 : 21;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO1 : 21;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO0 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 6;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO3 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO0 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 24;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            clprim_in_back_event : 1;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int     clip_priority_seq_indx_load : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int     clip_priority_seq_indx_load : 2;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int            clprim_in_back_event : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int         clprim_in_back_event_id : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         clprim_in_back_event_id : 6;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+        unsigned int                     ALWAYS_ZERO : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 28;
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clip_priority_available_vte_out_clip : 2;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clip_priority_available_vte_out_clip : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               sm0_clip_vert_cnt : 4;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int               sm0_current_state : 7;
+        unsigned int                    ALWAYS_ZERO0 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 5;
+        unsigned int               sm0_current_state : 7;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int               sm0_clip_vert_cnt : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   nan_kill_flag : 4;
+        unsigned int                position_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int           sx_pending_rd_aux_sel : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           sx_pending_rd_aux_sel : 1;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                position_address : 3;
+        unsigned int                   nan_kill_flag : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                param_cache_base : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                param_cache_base : 7;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         sx_sent : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                          sx_aux : 1;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                req_active_verts : 7;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int        sx_pending_fifo_contents : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int        sx_pending_fifo_contents : 3;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int                req_active_verts : 7;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                          sx_aux : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                         sx_sent : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    vertex_fifo_entriesavailable : 4;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int                   current_state : 2;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                   current_state : 2;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int    vertex_fifo_entriesavailable : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   su_cntl_state : 5;
+        unsigned int                     pmode_state : 6;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                       geom_busy : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       geom_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     pmode_state : 6;
+        unsigned int                   su_cntl_state : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort0_gated_17_4 : 14;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int              y_sort0_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort1_gated_17_4 : 14;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int              y_sort1_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort2_gated_17_4 : 14;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int              y_sort2_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort0_gated : 11;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                      type_gated : 3;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                       eop_gated : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                       eop_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                      type_gated : 3;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int           attr_indx_sort0_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort2_gated : 11;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int                  event_id_gated : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                  event_id_gated : 5;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int           attr_indx_sort2_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SC_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SC_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    pa_freeze_b1 : 1;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                                 : 17;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 17;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                    pa_freeze_b1 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        em_state : 3;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                                 : 21;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 21;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                        em_state : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rc_rtr_dly : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                                 : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int                        event_s1 : 1;
+        unsigned int                                 : 8;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 8;
+        unsigned int                        event_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                                 : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                      rc_rtr_dly : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       x_curr_s1 : 11;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                                 : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 9;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                       x_curr_s1 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        y_end_s1 : 14;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        x_end_s1 : 14;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      z_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                           state : 3;
+        unsigned int                   state_delayed : 3;
+        unsigned int                      data_valid : 1;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                      data_valid : 1;
+        unsigned int                   state_delayed : 3;
+        unsigned int                           state : 3;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                      z_ff_empty : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      event_flag : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                       fposition : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                           state : 2;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                                 : 6;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 6;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                           state : 2;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       fposition : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                      event_flag : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     sample_last : 1;
+        unsigned int                     sample_mask : 4;
+        unsigned int                        sample_y : 2;
+        unsigned int                        sample_x : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int                       fposition : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                                 : 3;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 3;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                       fposition : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                        sample_x : 2;
+        unsigned int                        sample_y : 2;
+        unsigned int                     sample_mask : 4;
+        unsigned int                     sample_last : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rb_sc_send : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                      mask_state : 2;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_ready : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int                      mask_ready : 1;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_state : 2;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                      rb_sc_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            combined_sample_mask : 16;
+        unsigned int                                 : 15;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 15;
+        unsigned int            combined_sample_mask : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            ez_sample_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_event : 1;
+        unsigned int                      next_state : 3;
+        unsigned int                           state : 3;
+        unsigned int                           stall : 1;
+        unsigned int                                 : 16;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 16;
+        unsigned int                           stall : 1;
+        unsigned int                           state : 3;
+        unsigned int                      next_state : 3;
+        unsigned int               packer_send_event : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int            ez_sample_data_ready : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SQ_iterator_free_buff : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                                 : 7;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 7;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int           SQ_iterator_free_buff : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GFX_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DRAW_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       PRIM_TYPE : 6;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int            FACENESS_CULL_SELECT : 2;
+        unsigned int                                 : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int                     NUM_INDICES : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     NUM_INDICES : 16;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int            FACENESS_CULL_SELECT : 2;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int                       PRIM_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_EVENT_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EVENT_TYPE : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      EVENT_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                       SWAP_MODE : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SWAP_MODE : 2;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                  FACENESS_FETCH : 1;
+        unsigned int                  FACENESS_RESET : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  FACENESS_RESET : 1;
+        unsigned int                  FACENESS_FETCH : 1;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MIN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_IMMED_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MAX_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MAX_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MAX_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MIN_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MIN_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_INDX_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INDX_OFFSET : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                     INDX_OFFSET : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VERTEX_REUSE_BLOCK_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_OUT_DEALLOC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEALLOC_DIST : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    DEALLOC_DIST : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MULTI_PRIM_IB_RESET_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESET_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      RESET_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            MISC : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                            MISC : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VTX_VECT_EJECT_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PRIM_COUNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                      PRIM_COUNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_LAST_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VGT_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                  VGT_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     te_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     te_grp_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                out_te_data_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_te_data_read : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      vgt_clk_en : 1;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                      vgt_clk_en : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int                      read_block : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int                   selected_data : 8;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                           gap_q : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int                     grp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     grp_trigger : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int                           gap_q : 1;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                   selected_data : 8;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int                      read_block : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     save_read_q : 1;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                     save_read_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            prim_side_indx_valid : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                       hold_prim : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int                       hold_prim : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int            prim_side_indx_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       null_terminate_vtx_vector : 1;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int                    new_packet_q : 1;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int                                 : 4;
+        unsigned int                     out_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 4;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int                    new_packet_q : 1;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int       null_terminate_vtx_vector : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   L2_INVALIDATE : 1;
+        unsigned int                                 : 17;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 11;
+        unsigned int                         TC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 11;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 17;
+        unsigned int                   L2_INVALIDATE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int                           SPARE : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 23;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP_TC_CLKGATE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TP_BUSY_EXTEND : 3;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                  TP_BUSY_EXTEND : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TPC_INPUT_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int                        TPC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int                  TPC_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        LOD_CNTL : 2;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                                 : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                    SQ_TP_WAKEUP : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SQ_TP_WAKEUP : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                                 : 3;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 1;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                        LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          UNUSED : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                          UNUSED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 BLEND_PRECISION : 1;
+        unsigned int                           SPARE : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 31;
+        unsigned int                 BLEND_PRECISION : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TP_INPUT_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                         TP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TP_BUSY : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                   TP_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      Q_LOD_CNTL : 2;
+        unsigned int                                 : 1;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int                                 : 1;
+        unsigned int                      Q_LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TT_MODE : 1;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                           SPARE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 30;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                         TT_MODE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 6;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TPC_full : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                         tca_rts : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                         tca_rts : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                        TPC_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                                 : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_FIFO_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        tp0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tpc_full : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                        tpc_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tp0_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_PROBE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               ProbeFilter_stall : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int               ProbeFilter_stall : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_TPC_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                                 : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 18;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_CORE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       access512 : 1;
+        unsigned int                           tiled : 1;
+        unsigned int                                 : 2;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 1;
+        unsigned int                          format : 6;
+        unsigned int                                 : 2;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 3;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 3;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 2;
+        unsigned int                          format : 6;
+        unsigned int                                 : 1;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 2;
+        unsigned int                           tiled : 1;
+        unsigned int                       access512 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG1_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG2_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG3_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       left_done : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int                     update_left : 1;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int                    valid_left_q : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    valid_left_q : 1;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int                     update_left : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int                       left_done : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_WALKER_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                                 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                            busy : 1;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                            busy : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                                 : 3;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_PIPE0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     tc0_arb_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                            busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         valid_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                         valid_q : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                            busy : 1;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                     tc0_arb_rts : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_INPUT0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                                 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DEGAMMA_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTMUX_SCTARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 9;
+        unsigned int                          pstate : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int                                 : 3;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 6;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                                 : 6;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 3;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int                                 : 3;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                                 : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTC_ARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                        n0_stall : 1;
+        unsigned int                          pstate : 1;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int                 n0_dxt2_4_types : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 n0_dxt2_4_types : 1;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                        n0_stall : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 10;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_incoming_rtr : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                not_incoming_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int                                 : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             rl_sg_sector_format : 8;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                                 : 2;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int                            busy : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            busy : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 2;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int             rl_sg_sector_format : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       fifo_busy : 1;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                    write_enable : 1;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                                 : 2;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int                                 : 2;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                    write_enable : 1;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                       fifo_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_GPR_MANAGEMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     REG_DYNAMIC : 1;
+        unsigned int                                 : 3;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 3;
+        unsigned int                     REG_DYNAMIC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FLOW_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+        unsigned int                                 : 2;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 2;
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INST_STORE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   INST_BASE_PIX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_PIX : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_RESOURCE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_EO_RT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 EO_CONSTANTS_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                 EO_CONSTANTS_RT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  DB_ALUCST_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                        RESERVED : 2;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                                 : 1;
+        unsigned int                  DB_ALUCST_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TIMEBASE : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                           SPARE : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                        TIMEBASE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERCENT_BUSY : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    PERCENT_BUSY : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INPUT_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_THREAD_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                        RESERVED : 2;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_WATCHDOG_TIMER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ENABLE : 1;
+        unsigned int                   TIMEOUT_COUNT : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TIMEOUT_COUNT : 31;
+        unsigned int                          ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_WATCHDOG_TIMER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ENABLE : 1;
+        unsigned int                   TIMEOUT_COUNT : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TIMEOUT_COUNT : 31;
+        unsigned int                          ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_WATCHDOG_MASK : 1;
+        unsigned int                VS_WATCHDOG_MASK : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                VS_WATCHDOG_MASK : 1;
+        unsigned int                PS_WATCHDOG_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PS_WATCHDOG_TIMEOUT : 1;
+        unsigned int             VS_WATCHDOG_TIMEOUT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int             VS_WATCHDOG_TIMEOUT : 1;
+        unsigned int             PS_WATCHDOG_TIMEOUT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PS_WATCHDOG_ACK : 1;
+        unsigned int                 VS_WATCHDOG_ACK : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                 VS_WATCHDOG_ACK : 1;
+        unsigned int                 PS_WATCHDOG_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_INPUT_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       VC_VSR_LD : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           PC_AS : 3;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                           PC_AS : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_VSR_LD : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_CONST_MGR_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TP_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           EX_TP : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           CF_TP : 4;
+        unsigned int                           IF_TP : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           IF_TP : 3;
+        unsigned int                           CF_TP : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           EX_TP : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_EXP_ALLOC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   POS_BUF_AVAIL : 4;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                   POS_BUF_AVAIL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PTR_BUFF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   END_OF_BUFFER : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                   END_OF_BUFFER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_VTX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VTX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_PIX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TB_STATUS_SEL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int                                 : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_PTR : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                     VS_DONE_PTR : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATUS_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VS_STATUS_REG : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VS_STATUS_REG : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_HEAD_PTR : 6;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int                            BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BUSY : 1;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                    PIX_HEAD_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VECTOR_RESULT : 6;
+        unsigned int                  VECTOR_DST_REL : 1;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int                  SCALAR_DST_REL : 1;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                   SCALAR_OPCODE : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SCALAR_OPCODE : 6;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  SCALAR_DST_REL : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                  VECTOR_DST_REL : 1;
+        unsigned int                   VECTOR_RESULT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                 CONST_0_REL_ABS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CONST_0_REL_ABS : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SRC_C_REG_PTR : 6;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_A_SEL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_A_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   SRC_C_REG_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_1 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 11;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 11;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 6;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                      RESERVED_0 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                        RESERVED : 22;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                        RESERVED : 22;
+        unsigned int                         LOOP_ID : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      RESERVED_1 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 17;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 1;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_2 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_2 : 2;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                      RESERVED_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 17;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                        RESERVED : 17;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 4;
+        unsigned int                        RESERVED : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 28;
+        unsigned int                            SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 8;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                            SIZE : 4;
+        unsigned int                      RESERVED_1 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 12;
+        unsigned int                            SIZE : 4;
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                      RESERVED_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 24;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                        RESERVED : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_Z : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_SEL_Z : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               USE_REG_GRADIENTS : 1;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int               USE_REG_GRADIENTS : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                         SRC_SEL : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SRC_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          STRIDE : 8;
+        unsigned int                                 : 8;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 7;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                                 : 7;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 8;
+        unsigned int                          STRIDE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TYPE : 1;
+        unsigned int                           STATE : 1;
+        unsigned int                    BASE_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BASE_ADDRESS : 30;
+        unsigned int                           STATE : 1;
+        unsigned int                            TYPE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ENDIAN_SWAP : 2;
+        unsigned int                   LIMIT_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   LIMIT_ADDRESS : 30;
+        unsigned int                     ENDIAN_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_PROGRAM_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      VS_CF_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INTERPOLATOR_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARAM_SHADE : 16;
+        unsigned int                SAMPLING_PATTERN : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                SAMPLING_PATTERN : 16;
+        unsigned int                     PARAM_SHADE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PROGRAM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                   GEN_INDEX_VTX : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   GEN_INDEX_VTX : 1;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      VS_NUM_REG : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_0 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_7 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PARAM_WRAP_7 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_0 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_8 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_15 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PARAM_WRAP_15 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                    PARAM_WRAP_8 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONTEXT_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                                 : 4;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RD_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RD_BASE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                         RD_BASE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DB_PROB_ON : 1;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 5;
+        unsigned int                   DB_PROB_COUNT : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DB_PROB_COUNT : 8;
+        unsigned int                                 : 5;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      DB_PROB_ON : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DB_ON_PIX : 1;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                                 : 6;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                                 : 6;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                       DB_ON_PIX : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_ARBITER_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  PA_CLNT_ENABLE : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                  PA_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_CLNT_AXI_ID_REUSE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          CPw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                          PAw_ID : 3;
+        unsigned int                                 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 17;
+        unsigned int                          PAw_ID : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          CPw_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     AXI_READ_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                     AXI_READ_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           INDEX : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                           INDEX : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_HALT_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AXI_HALT : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                        AXI_HALT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                      PA_REQUEST : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                      PA_REQUEST : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                         MH_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                       CP_BLEN_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_BLEN_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       TC_BLEN_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       CP_BLEN_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_PA_writeclean : 1;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                MH_PA_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CP_MH_send : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                   CP_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CP_MH_ad_31_5 : 27;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                      CP_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG06 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 CP_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CP_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG07 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CP_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                CP_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG08 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CP_MH_be : 8;
+        unsigned int                        RB_MH_be : 8;
+        unsigned int                        PA_MH_be : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        PA_MH_be : 8;
+        unsigned int                        RB_MH_be : 8;
+        unsigned int                        CP_MH_be : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 3;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                 TC_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 TC_MH_addr_31_5 : 27;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_info : 25;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_info : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_TC_mcinfo : 25;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                    MH_TC_mcinfo : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ROQ_INFO : 25;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_INFO : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                 RB_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_addr_31_5 : 27;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 RB_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                RB_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                RB_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      PA_MH_send : 1;
+        unsigned int                 PA_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PA_MH_addr_31_5 : 27;
+        unsigned int                      PA_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG19 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PA_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PA_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PA_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PA_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG22 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG23 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                    CTRL_ARC_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CTRL_ARC_PAD : 28;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG24 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                           REG_A : 14;
+        unsigned int                          REG_RE : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                          REG_RE : 1;
+        unsigned int                           REG_A : 14;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG25 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          REG_WD : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REG_WD : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG26 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_RBBM_busy : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       BRC_VALID : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BRC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int                    MH_RBBM_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG27 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  EFF2_FP_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                  EFF2_FP_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG28 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG29 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        CLNT_REQ : 5;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_4 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RECENT_d_4 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                        CLNT_REQ : 5;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG30 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG31 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG32 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG33 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG34 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG35 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                      ROQ_ADDR_0 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_0 : 27;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG36 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                      ROQ_ADDR_1 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_1 : 27;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG37 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                      ROQ_ADDR_2 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_2 : 27;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG38 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                      ROQ_ADDR_3 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_3 : 27;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG39 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                      ROQ_ADDR_4 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_4 : 27;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG40 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                      ROQ_ADDR_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_5 : 27;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG41 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                      ROQ_ADDR_6 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_6 : 27;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG42 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                      ROQ_ADDR_7 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_7 : 27;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG43 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ARB_REG_WE_q : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                 ARB_REG_VALID_q : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                     ARB_REG_RTR : 1;
+        unsigned int                  WDAT_BURST_RTR : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                  WDB_RTR_SKID_3 : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                  WDB_RTR_SKID_3 : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                  WDAT_BURST_RTR : 1;
+        unsigned int                     ARB_REG_RTR : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                 ARB_REG_VALID_q : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                    ARB_REG_WE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG44 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ARB_WE : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                       ARB_VAD_q : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ARB_VAD_q : 28;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                          ARB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG45 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          MMU_WE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         MMU_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MMU_PAD : 28;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                          MMU_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG46 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                WDAT_REG_VALID_q : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                   WDB_WDC_WSTRB : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   WDB_WDC_WSTRB : 8;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                WDAT_REG_VALID_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG47 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG48 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG49 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG50 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG51 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG52 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          RF_MMU_CONFIG_q_1_to_0 : 2;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int         RF_MMU_CONFIG_q_25_to_4 : 22;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int               client_behavior_q : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               client_behavior_q : 2;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int         RF_MMU_CONFIG_q_25_to_4 : 22;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int          RF_MMU_CONFIG_q_1_to_0 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG53 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    stage1_valid : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                    stage1_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG54 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                    stage2_valid : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                     TAG_valid_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TAG_valid_q : 16;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                    stage2_valid : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG55 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG0_VA : 13;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                         TAG0_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG56 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG2_VA : 13;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                         TAG2_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG57 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG4_VA : 13;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                         TAG4_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG58 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG6_VA : 13;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                         TAG6_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG59 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG8_VA : 13;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                         TAG8_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG60 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG10_VA : 13;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                        TAG10_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG61 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG12_VA : 13;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                        TAG12_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG62 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG14_VA : 13;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                        TAG14_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG63 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      MMU_ENABLE : 1;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int              PA_W_CLNT_BEHAVIOR : 2;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int              PA_W_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                      MMU_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_VA_RANGE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                NUM_64KB_REGIONS : 12;
+        unsigned int                         VA_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         VA_BASE : 20;
+        unsigned int                NUM_64KB_REGIONS : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PT_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         PT_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         PT_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PAGE_FAULT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PAGE_FAULT : 1;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int                          REQ_VA : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REQ_VA : 20;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                      PAGE_FAULT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_TRAN_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                      TRAN_ERROR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      TRAN_ERROR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_INVALIDATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  INVALIDATE_ALL : 1;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                  INVALIDATE_ALL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                        MPU_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MPU_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_END {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         MPU_END : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MPU_END : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union WAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int                                 : 2;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 2;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_ISYNC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CMDFIFO_AVAIL : 5;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                      GUI_ACTIVE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      GUI_ACTIVE : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                                 : 2;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                   CMDFIFO_AVAIL : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DSPLY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SEL_DMI_ACTIVE_BUFID0 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID1 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID2 : 1;
+        unsigned int             SEL_DMI_VSYNC_VALID : 1;
+        unsigned int              DMI_CH1_USE_BUFID0 : 1;
+        unsigned int              DMI_CH1_USE_BUFID1 : 1;
+        unsigned int              DMI_CH1_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH1_SW_CNTL : 1;
+        unsigned int                DMI_CH1_NUM_BUFS : 2;
+        unsigned int              DMI_CH2_USE_BUFID0 : 1;
+        unsigned int              DMI_CH2_USE_BUFID1 : 1;
+        unsigned int              DMI_CH2_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH2_SW_CNTL : 1;
+        unsigned int                DMI_CH2_NUM_BUFS : 2;
+        unsigned int              DMI_CHANNEL_SELECT : 2;
+        unsigned int                                 : 2;
+        unsigned int              DMI_CH3_USE_BUFID0 : 1;
+        unsigned int              DMI_CH3_USE_BUFID1 : 1;
+        unsigned int              DMI_CH3_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH3_SW_CNTL : 1;
+        unsigned int                DMI_CH3_NUM_BUFS : 2;
+        unsigned int              DMI_CH4_USE_BUFID0 : 1;
+        unsigned int              DMI_CH4_USE_BUFID1 : 1;
+        unsigned int              DMI_CH4_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH4_SW_CNTL : 1;
+        unsigned int                DMI_CH4_NUM_BUFS : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                DMI_CH4_NUM_BUFS : 2;
+        unsigned int                 DMI_CH4_SW_CNTL : 1;
+        unsigned int              DMI_CH4_USE_BUFID2 : 1;
+        unsigned int              DMI_CH4_USE_BUFID1 : 1;
+        unsigned int              DMI_CH4_USE_BUFID0 : 1;
+        unsigned int                DMI_CH3_NUM_BUFS : 2;
+        unsigned int                 DMI_CH3_SW_CNTL : 1;
+        unsigned int              DMI_CH3_USE_BUFID2 : 1;
+        unsigned int              DMI_CH3_USE_BUFID1 : 1;
+        unsigned int              DMI_CH3_USE_BUFID0 : 1;
+        unsigned int                                 : 2;
+        unsigned int              DMI_CHANNEL_SELECT : 2;
+        unsigned int                DMI_CH2_NUM_BUFS : 2;
+        unsigned int                 DMI_CH2_SW_CNTL : 1;
+        unsigned int              DMI_CH2_USE_BUFID2 : 1;
+        unsigned int              DMI_CH2_USE_BUFID1 : 1;
+        unsigned int              DMI_CH2_USE_BUFID0 : 1;
+        unsigned int                DMI_CH1_NUM_BUFS : 2;
+        unsigned int                 DMI_CH1_SW_CNTL : 1;
+        unsigned int              DMI_CH1_USE_BUFID2 : 1;
+        unsigned int              DMI_CH1_USE_BUFID1 : 1;
+        unsigned int              DMI_CH1_USE_BUFID0 : 1;
+        unsigned int             SEL_DMI_VSYNC_VALID : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID2 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID1 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RENDER_LATEST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               DMI_CH1_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH2_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH3_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH4_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH4_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH3_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH2_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH1_BUFFER_ID : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RTL_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CHANGELIST : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      CHANGELIST : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PATCH_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PATCH_REVISION : 16;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                     CUSTOMER_ID : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     CUSTOMER_ID : 8;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                  PATCH_REVISION : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_AUXILIARY_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER0 : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     PARTNUMBER0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER1 : 4;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                     PARTNUMBER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DESIGNER1 : 4;
+        unsigned int                        REVISION : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        REVISION : 4;
+        unsigned int                       DESIGNER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int                                 : 1;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 1;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    READ_TIMEOUT : 8;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                    READ_TIMEOUT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SKEW_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SOFT_RESET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SOFT_RESET_CP : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                                 : 5;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 2;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                                 : 2;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 5;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_CP : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GC_SYS_IDLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+        unsigned int            GC_SYS_WAIT_DMI_MASK : 6;
+        unsigned int                                 : 2;
+        unsigned int              GC_SYS_URGENT_RAMP : 1;
+        unsigned int                 GC_SYS_WAIT_DMI : 1;
+        unsigned int                                 : 3;
+        unsigned int     GC_SYS_URGENT_RAMP_OVERRIDE : 1;
+        unsigned int        GC_SYS_WAIT_DMI_OVERRIDE : 1;
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+        unsigned int        GC_SYS_WAIT_DMI_OVERRIDE : 1;
+        unsigned int     GC_SYS_URGENT_RAMP_OVERRIDE : 1;
+        unsigned int                                 : 3;
+        unsigned int                 GC_SYS_WAIT_DMI : 1;
+        unsigned int              GC_SYS_URGENT_RAMP : 1;
+        unsigned int                                 : 2;
+        unsigned int            GC_SYS_WAIT_DMI_MASK : 6;
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union NQWAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WAIT_GUI_IDLE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                   WAIT_GUI_IDLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG_OUT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DEBUG_BUS_OUT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DEBUG_BUS_OUT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 2;
+        unsigned int                   SUB_BLOCK_SEL : 4;
+        unsigned int                       SW_ENABLE : 1;
+        unsigned int                                 : 3;
+        unsigned int             GPIO_SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 2;
+        unsigned int              GPIO_SUB_BLOCK_SEL : 4;
+        unsigned int              GPIO_BYTE_LANE_ENB : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              GPIO_BYTE_LANE_ENB : 4;
+        unsigned int              GPIO_SUB_BLOCK_SEL : 4;
+        unsigned int                                 : 2;
+        unsigned int             GPIO_SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 3;
+        unsigned int                       SW_ENABLE : 1;
+        unsigned int                   SUB_BLOCK_SEL : 4;
+        unsigned int                                 : 2;
+        unsigned int                  SUB_BLOCK_ADDR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int                                 : 3;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 4;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int                                 : 6;
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+        unsigned int                                 : 6;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int                                 : 4;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 3;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_READ_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 13;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                      READ_ERROR : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      READ_ERROR : 1;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                                 : 13;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_WAIT_IDLE_CLOCKS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_MASK : 1;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                  RDERR_INT_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_STAT : 1;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                  RDERR_INT_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   RDERR_INT_ACK : 1;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                   RDERR_INT_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MASTER_INT_SIGNAL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 20;
+        unsigned int                     SQ_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                   RBBM_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   RBBM_INT_STAT : 1;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SQ_INT_STAT : 1;
+        unsigned int                                 : 20;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNT1_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                 PERF_COUNT1_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PERF_COUNT1_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERF_COUNT1_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                         RB_BASE : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         RB_BASE : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RB_BUFSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 6;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 3;
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+        unsigned int                                 : 3;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 6;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BUFSZ : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_RPTR_SWAP : 2;
+        unsigned int                    RB_RPTR_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_RPTR_ADDR : 30;
+        unsigned int                    RB_RPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_RPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_RPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_WR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RB_RPTR_WR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                      RB_RPTR_WR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_WPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_WPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_DELAY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PRE_WRITE_TIMER : 28;
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+        unsigned int                 PRE_WRITE_TIMER : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_WPTR_SWAP : 2;
+        unsigned int                    RB_WPTR_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_WPTR_BASE : 30;
+        unsigned int                    RB_WPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB1_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB1_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB1_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB1_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB2_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB2_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB2_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB2_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                         ST_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         ST_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        ST_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        ST_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_QUEUE_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CSQ_IB1_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB1_START : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CSQ_CNT_RING : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                    CSQ_CNT_RING : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STQ_CNT_ST : 7;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                      STQ_CNT_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MEQ_CNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                         MEQ_CNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_RB_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB1_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB2_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NON_PREFETCH_CNTRS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     IB1_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB1_COUNTER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_ST_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STQ_RPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_RPTR_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MEQ_RPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_RPTR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MIU_TAG_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TAG_0_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                                 : 13;
+        unsigned int              INVALID_RETURN_TAG : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              INVALID_RETURN_TAG : 1;
+        unsigned int                                 : 13;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_0_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CMD_INDEX : 7;
+        unsigned int                                 : 9;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 9;
+        unsigned int                       CMD_INDEX : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CMD_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CMD_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ME_STATMUX : 16;
+        unsigned int                                 : 9;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   PROG_CNT_SIZE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PROG_CNT_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                                 : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 9;
+        unsigned int                      ME_STATMUX : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ME_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ME_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_WADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_WADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_WADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_RADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_RADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_RADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ME_RAM_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ME_RAM_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RDADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ME_RDADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ME_RDADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int                                 : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG4 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG4 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG5 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG5 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG6 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG6 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG7 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG7 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_UMSK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_UMSK : 8;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_UMSK : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                    SCRATCH_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_SWM : 1;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                     VS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_SWAP : 2;
+        unsigned int                    VS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_ADDR : 30;
+        unsigned int                    VS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PS_DONE_SWM : 1;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                     PS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_SWAP : 2;
+        unsigned int                    PS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_ADDR : 30;
+        unsigned int                    PS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CF_DONE_SRC : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                     CF_DONE_SRC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_SWAP : 2;
+        unsigned int                    CF_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_ADDR : 30;
+        unsigned int                    CF_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_SWAP : 2;
+        unsigned int                  NRT_WRITE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_ADDR : 30;
+        unsigned int                  NRT_WRITE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                     RB_INT_MASK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                     RB_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                      RB_INT_ACK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RB_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_ADDR : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      UCODE_ADDR : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_DATA : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      UCODE_DATA : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFMON_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFMON_STATE : 4;
+        unsigned int                                 : 4;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PERFMON_STATE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFCOUNT_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                   PERFCOUNT_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PERFCOUNT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    PERFCOUNT_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DISCARD_0 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_15 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_15 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_16 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_31 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_31 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_16 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_32 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_47 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_47 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_32 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_48 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_63 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_63 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_48 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               STATE_DEBUG_INDEX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int               STATE_DEBUG_INDEX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                STATE_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                STATE_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PROG_COUNTER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         COUNTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         COUNTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     MIU_WR_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                         CP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CP_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int                     MIU_WR_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_0_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_1_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_2_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_3_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_4_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_5_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_6_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_7_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_8_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_9_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_10_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_11_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_12_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_13_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_14_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_15_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_0 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_0 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_1 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_1 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_2 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_2 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_3 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_3 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_4 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_4 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_5 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_5 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_6 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_6 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_7 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_7 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SURFACE_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SURFACE_PITCH : 14;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                   SURFACE_PITCH : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    COLOR_FORMAT : 4;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      COLOR_BASE : 20;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_FORMAT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEPTH_FORMAT : 1;
+        unsigned int                                 : 11;
+        unsigned int                      DEPTH_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      DEPTH_BASE : 20;
+        unsigned int                                 : 11;
+        unsigned int                    DEPTH_FORMAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STENCILREF : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                      STENCILREF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ALPHA_REF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ALPHA_REF : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ALPHA_REF : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       WRITE_RED : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                       WRITE_RED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_RED {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BLEND_RED : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       BLEND_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_GREEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_GREEN : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_GREEN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_BLUE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      BLEND_BLUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      BLEND_BLUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_ALPHA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_ALPHA : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_ALPHA : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FOG_COLOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         FOG_RED : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                         FOG_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK_BF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   STENCILREF_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int                   STENCILREF_BF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTHCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  STENCIL_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                 STENCILZFAIL_BF : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 STENCILZFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  STENCIL_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLENDCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  COLOR_SRCBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                  COLOR_SRCBLEND : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLORCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ALPHA_FUNC : 3;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                                 : 7;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int                                 : 7;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int                      ALPHA_FUNC : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_MODECONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_MODE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                      EDRAM_MODE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_DEST_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COLOR_DEST_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 COLOR_DEST_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                  COPY_DEST_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  COPY_DEST_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PITCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COPY_DEST_PITCH : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                 COPY_DEST_PITCH : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                COPY_DEST_ENDIAN : 3;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_ENDIAN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PIXEL_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        OFFSET_X : 13;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                        OFFSET_X : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     DEPTH_CLEAR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEPTH_CLEAR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_CTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int                                 : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int                      CRC_SYSTEM : 1;
+        unsigned int                       RESERVED6 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       RESERVED6 : 1;
+        unsigned int                      CRC_SYSTEM : 1;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                                 : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_EDRAM_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_SIZE : 4;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                                 : 8;
+        unsigned int                     EDRAM_RANGE : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     EDRAM_RANGE : 18;
+        unsigned int                                 : 8;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                      EDRAM_SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_RD_PORT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CRC_RD_ADVANCE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                  CRC_RD_ADVANCE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_TOTAL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TOTAL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TOTAL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZPASS_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZPASS_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZPASS_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 TILE_FIFO_COUNT : 4;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z_TILE_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    Z_TILE_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 TILE_FIFO_COUNT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ACCUM_VALID : 4;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int                     ACCUM_VALID : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int                                 : 19;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 19;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FLAG_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_SPARES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_ENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_MOREENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h
new file mode 100644
index 000000000000..69677996b133
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h
@@ -0,0 +1,4184 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_SHIFT_HEADER)
+#define _yamato_SHIFT_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT          0x00000000
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT           0x00000000
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT          0x00000001
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT           0x00000002
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT          0x00000003
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT           0x00000004
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT          0x00000005
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT                  0x00000008
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT                   0x00000009
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT                  0x0000000a
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT             0x0000000b
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT               0x00000010
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT     0x00000012
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT          0x00000013
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT        0x00000014
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT                0x00000015
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT              0x00000016
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT               0x00000017
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT               0x00000018
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT         0x00000000
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT                  0x00000000
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT                  0x00000001
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT                  0x00000003
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT                    0x00000000
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT                     0x00000010
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT                0x00000000
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT                0x00000010
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT                      0x00000000
+
+// PA_SU_FACE_DATA
+#define PA_SU_FACE_DATA__BASE_ADDR__SHIFT                  0x00000005
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT              0x00000000
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT               0x00000001
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT                    0x00000002
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT               0x00000003
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT    0x00000005
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT     0x00000008
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT             0x0000000f
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT     0x00000012
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT      0x00000013
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT          0x00000014
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT       0x00000015
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT       0x00000017
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT    0x00000019
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a
+#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS__SHIFT        0x0000001c
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS__SHIFT      0x0000001d
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE__SHIFT        0x0000001e
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE__SHIFT       0x0000001f
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT        0x00000000
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT      0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT         0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT       0x00000000
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT        0x00000000
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT        0x00000010
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT           0x00000000
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT            0x0000000d
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK__SHIFT                      0x00000000
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT            0x00000000
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT            0x00000010
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT       0x0000001c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT         0x0000001d
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT                  0x00000000
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT              0x00000008
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT          0x00000009
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT                 0x0000000a
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT              0x00000000
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT               0x00000001
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT      0x00000007
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT         0x00000000
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT       0x00000000
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT     0x00000008
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT                  0x0000001f
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT  0x00000000
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT   0x00000001
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT  0x00000002
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT   0x00000003
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT     0x0000000d
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT            0x00000014
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT    0x00000013
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT            0x00000018
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT           0x00000018
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT           0x00000008
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT           0x0000001a
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT           0x00000008
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT           0x00000001
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT           0x00000016
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT           0x0000001c
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT   0x00000000
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT           0x00000006
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT           0x0000000c
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT           0x00000012
+#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT        0x00000014
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT   0x0000001c
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT    0x0000001d
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT           0x0000000a
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT           0x00000013
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT            0x00000004
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT           0x00000002
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT           0x00000016
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT      0x00000000
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT     0x00000004
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT    0x0000000e
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT      0x00000014
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT           0x0000001b
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT           0x00000000
+#define SXIFCCG_DEBUG_REG0__position_address__SHIFT        0x00000004
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG0__point_address__SHIFT           0x0000000a
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT            0x0000000d
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT            0x00000011
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT  0x00000013
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT       0x00000017
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT   0x0000001e
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT   0x0000001f
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT            0x00000000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT          0x00000002
+#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT     0x00000004
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT      0x0000000b
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT         0x0000000c
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT                 0x00000014
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT            0x00000015
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT            0x00000017
+#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT        0x00000019
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT                 0x00000000
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT            0x00000001
+#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT                  0x00000002
+#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT         0x00000003
+#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT        0x00000009
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT            0x00000012
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT            0x00000016
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT   0x0000001b
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT    0x0000001c
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT            0x00000004
+#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT     0x00000005
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT            0x00000008
+#define SXIFCCG_DEBUG_REG3__current_state__SHIFT           0x0000000c
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT       0x0000000e
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT        0x0000000f
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT  0x00000012
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT   0x00000013
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT  0x00000015
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT            0x00000016
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT             0x00000000
+#define SETUP_DEBUG_REG0__pmode_state__SHIFT               0x00000005
+#define SETUP_DEBUG_REG0__ge_stallb__SHIFT                 0x0000000b
+#define SETUP_DEBUG_REG0__geom_enable__SHIFT               0x0000000c
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT         0x0000000d
+#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT               0x0000000e
+#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT                0x0000000f
+#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT              0x00000010
+#define SETUP_DEBUG_REG0__geom_busy__SHIFT                 0x00000011
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT           0x0000000b
+#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT          0x0000000c
+#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT             0x0000000d
+#define SETUP_DEBUG_REG4__clipped_gated__SHIFT             0x00000010
+#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT        0x00000011
+#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT              0x00000014
+#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT        0x00000015
+#define SETUP_DEBUG_REG4__type_gated__SHIFT                0x00000017
+#define SETUP_DEBUG_REG4__fpov_gated__SHIFT                0x0000001a
+#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT          0x0000001b
+#define SETUP_DEBUG_REG4__event_gated__SHIFT               0x0000001c
+#define SETUP_DEBUG_REG4__eop_gated__SHIFT                 0x0000001d
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT     0x0000000b
+#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT       0x00000016
+#define SETUP_DEBUG_REG5__event_id_gated__SHIFT            0x00000018
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1__SHIFT                    0x00000000
+#define SC_DEBUG_0__pa_sc_valid__SHIFT                     0x00000001
+#define SC_DEBUG_0__pa_sc_phase__SHIFT                     0x00000002
+#define SC_DEBUG_0__cntx_cnt__SHIFT                        0x00000005
+#define SC_DEBUG_0__decr_cntx_cnt__SHIFT                   0x0000000c
+#define SC_DEBUG_0__incr_cntx_cnt__SHIFT                   0x0000000d
+#define SC_DEBUG_0__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state__SHIFT                        0x00000000
+#define SC_DEBUG_1__em1_data_ready__SHIFT                  0x00000003
+#define SC_DEBUG_1__em2_data_ready__SHIFT                  0x00000004
+#define SC_DEBUG_1__move_em1_to_em2__SHIFT                 0x00000005
+#define SC_DEBUG_1__ef_data_ready__SHIFT                   0x00000006
+#define SC_DEBUG_1__ef_state__SHIFT                        0x00000007
+#define SC_DEBUG_1__pipe_valid__SHIFT                      0x00000009
+#define SC_DEBUG_1__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly__SHIFT                      0x00000000
+#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT            0x00000001
+#define SC_DEBUG_2__pipe_freeze_b__SHIFT                   0x00000003
+#define SC_DEBUG_2__prim_rts__SHIFT                        0x00000004
+#define SC_DEBUG_2__next_prim_rts_dly__SHIFT               0x00000005
+#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT               0x00000006
+#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT               0x00000007
+#define SC_DEBUG_2__stage0_rts__SHIFT                      0x00000008
+#define SC_DEBUG_2__phase_rts_dly__SHIFT                   0x00000009
+#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT              0x0000000f
+#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT              0x00000010
+#define SC_DEBUG_2__event_id_s1__SHIFT                     0x00000011
+#define SC_DEBUG_2__event_s1__SHIFT                        0x00000016
+#define SC_DEBUG_2__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1__SHIFT                       0x00000000
+#define SC_DEBUG_3__y_curr_s1__SHIFT                       0x0000000b
+#define SC_DEBUG_3__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_4__y_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_4__y_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_4__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_5__x_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_5__x_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_5__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty__SHIFT                      0x00000000
+#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT                 0x00000001
+#define SC_DEBUG_6__xy_ff_empty__SHIFT                     0x00000002
+#define SC_DEBUG_6__event_flag__SHIFT                      0x00000003
+#define SC_DEBUG_6__z_mask_needed__SHIFT                   0x00000004
+#define SC_DEBUG_6__state__SHIFT                           0x00000005
+#define SC_DEBUG_6__state_delayed__SHIFT                   0x00000008
+#define SC_DEBUG_6__data_valid__SHIFT                      0x0000000b
+#define SC_DEBUG_6__data_valid_d__SHIFT                    0x0000000c
+#define SC_DEBUG_6__tilex_delayed__SHIFT                   0x0000000d
+#define SC_DEBUG_6__tiley_delayed__SHIFT                   0x00000016
+#define SC_DEBUG_6__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag__SHIFT                      0x00000000
+#define SC_DEBUG_7__deallocate__SHIFT                      0x00000001
+#define SC_DEBUG_7__fposition__SHIFT                       0x00000004
+#define SC_DEBUG_7__sr_prim_we__SHIFT                      0x00000005
+#define SC_DEBUG_7__last_tile__SHIFT                       0x00000006
+#define SC_DEBUG_7__tile_ff_we__SHIFT                      0x00000007
+#define SC_DEBUG_7__qs_data_valid__SHIFT                   0x00000008
+#define SC_DEBUG_7__qs_q0_y__SHIFT                         0x00000009
+#define SC_DEBUG_7__qs_q0_x__SHIFT                         0x0000000b
+#define SC_DEBUG_7__qs_q0_valid__SHIFT                     0x0000000d
+#define SC_DEBUG_7__prim_ff_we__SHIFT                      0x0000000e
+#define SC_DEBUG_7__tile_ff_re__SHIFT                      0x0000000f
+#define SC_DEBUG_7__fw_prim_data_valid__SHIFT              0x00000010
+#define SC_DEBUG_7__last_quad_of_tile__SHIFT               0x00000011
+#define SC_DEBUG_7__first_quad_of_tile__SHIFT              0x00000012
+#define SC_DEBUG_7__first_quad_of_prim__SHIFT              0x00000013
+#define SC_DEBUG_7__new_prim__SHIFT                        0x00000014
+#define SC_DEBUG_7__load_new_tile_data__SHIFT              0x00000015
+#define SC_DEBUG_7__state__SHIFT                           0x00000016
+#define SC_DEBUG_7__fifos_ready__SHIFT                     0x00000018
+#define SC_DEBUG_7__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last__SHIFT                     0x00000000
+#define SC_DEBUG_8__sample_mask__SHIFT                     0x00000001
+#define SC_DEBUG_8__sample_y__SHIFT                        0x00000005
+#define SC_DEBUG_8__sample_x__SHIFT                        0x00000007
+#define SC_DEBUG_8__sample_send__SHIFT                     0x00000009
+#define SC_DEBUG_8__next_cycle__SHIFT                      0x0000000a
+#define SC_DEBUG_8__ez_sample_ff_full__SHIFT               0x0000000c
+#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT                  0x0000000d
+#define SC_DEBUG_8__num_samples__SHIFT                     0x0000000e
+#define SC_DEBUG_8__last_quad_of_tile__SHIFT               0x00000010
+#define SC_DEBUG_8__last_quad_of_prim__SHIFT               0x00000011
+#define SC_DEBUG_8__first_quad_of_prim__SHIFT              0x00000012
+#define SC_DEBUG_8__sample_we__SHIFT                       0x00000013
+#define SC_DEBUG_8__fposition__SHIFT                       0x00000014
+#define SC_DEBUG_8__event_id__SHIFT                        0x00000015
+#define SC_DEBUG_8__event_flag__SHIFT                      0x0000001a
+#define SC_DEBUG_8__fw_prim_data_valid__SHIFT              0x0000001b
+#define SC_DEBUG_8__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send__SHIFT                      0x00000000
+#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT                   0x00000001
+#define SC_DEBUG_9__fifo_data_ready__SHIFT                 0x00000005
+#define SC_DEBUG_9__early_z_enable__SHIFT                  0x00000006
+#define SC_DEBUG_9__mask_state__SHIFT                      0x00000007
+#define SC_DEBUG_9__next_ez_mask__SHIFT                    0x00000009
+#define SC_DEBUG_9__mask_ready__SHIFT                      0x00000019
+#define SC_DEBUG_9__drop_sample__SHIFT                     0x0000001a
+#define SC_DEBUG_9__fetch_new_sample_data__SHIFT           0x0000001b
+#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT        0x0000001c
+#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT       0x0000001d
+#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT         0x0000001e
+#define SC_DEBUG_9__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask__SHIFT           0x00000000
+#define SC_DEBUG_10__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready__SHIFT           0x00000000
+#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT      0x00000001
+#define SC_DEBUG_11__ez_prim_data_ready__SHIFT             0x00000002
+#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT        0x00000003
+#define SC_DEBUG_11__iterator_input_fz__SHIFT              0x00000004
+#define SC_DEBUG_11__packer_send_quads__SHIFT              0x00000005
+#define SC_DEBUG_11__packer_send_cmd__SHIFT                0x00000006
+#define SC_DEBUG_11__packer_send_event__SHIFT              0x00000007
+#define SC_DEBUG_11__next_state__SHIFT                     0x00000008
+#define SC_DEBUG_11__state__SHIFT                          0x0000000b
+#define SC_DEBUG_11__stall__SHIFT                          0x0000000e
+#define SC_DEBUG_11__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT          0x00000000
+#define SC_DEBUG_12__event_id__SHIFT                       0x00000001
+#define SC_DEBUG_12__event_flag__SHIFT                     0x00000006
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT        0x00000007
+#define SC_DEBUG_12__itercmdfifo_full__SHIFT               0x00000008
+#define SC_DEBUG_12__itercmdfifo_empty__SHIFT              0x00000009
+#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT        0x0000000a
+#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT           0x0000000b
+#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT          0x0000000c
+#define SC_DEBUG_12__iter_qdhit0__SHIFT                    0x0000000d
+#define SC_DEBUG_12__bc_use_centers_reg__SHIFT             0x0000000e
+#define SC_DEBUG_12__bc_output_xy_reg__SHIFT               0x0000000f
+#define SC_DEBUG_12__iter_phase_out__SHIFT                 0x00000010
+#define SC_DEBUG_12__iter_phase_reg__SHIFT                 0x00000012
+#define SC_DEBUG_12__iterator_SP_valid__SHIFT              0x00000014
+#define SC_DEBUG_12__eopv_reg__SHIFT                       0x00000015
+#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT                0x00000016
+#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT            0x00000017
+#define SC_DEBUG_12__trigger__SHIFT                        0x0000001f
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT                0x00000000
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT               0x00000000
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT           0x00000006
+#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT__SHIFT    0x00000008
+#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT              0x0000000b
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT                 0x0000000c
+#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT             0x0000000d
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT   0x0000000e
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT         0x0000000f
+#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT             0x00000010
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT             0x00000000
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT                     0x00000000
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_DMA_SIZE__SWAP_MODE__SHIFT                     0x0000001e
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT                 0x00000000
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_BIN_SIZE__FACENESS_FETCH__SHIFT                0x0000001e
+#define VGT_BIN_SIZE__FACENESS_RESET__SHIFT                0x0000001f
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT                  0x00000000
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT                  0x00000000
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT                0x00000000
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT          0x00000000
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT    0x00000000
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC__SHIFT                           0x00000000
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT          0x00000000
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT           0x00000000
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT           0x00000010
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT              0x00000000
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT                   0x00000000
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT               0x00000001
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT           0x00000002
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT               0x00000003
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT                0x00000004
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT               0x00000005
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT                0x00000006
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT               0x00000007
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT          0x00000008
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy__SHIFT                 0x00000000
+#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT                 0x00000001
+#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT                 0x00000002
+#define VGT_DEBUG_REG0__dma_request_busy__SHIFT            0x00000003
+#define VGT_DEBUG_REG0__out_busy__SHIFT                    0x00000004
+#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT            0x00000005
+#define VGT_DEBUG_REG0__grp_busy__SHIFT                    0x00000006
+#define VGT_DEBUG_REG0__dma_busy__SHIFT                    0x00000007
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT       0x00000008
+#define VGT_DEBUG_REG0__rbiu_busy__SHIFT                   0x00000009
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT    0x0000000a
+#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT             0x0000000b
+#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT           0x0000000c
+#define VGT_DEBUG_REG0__vgt_busy__SHIFT                    0x0000000d
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT     0x0000000e
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT        0x0000000f
+#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT               0x00000010
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read__SHIFT            0x00000000
+#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT           0x00000001
+#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT            0x00000002
+#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT           0x00000003
+#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT            0x00000004
+#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT           0x00000005
+#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT            0x00000006
+#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT           0x00000007
+#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT            0x00000008
+#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT           0x00000009
+#define VGT_DEBUG_REG1__te_grp_read__SHIFT                 0x0000000a
+#define VGT_DEBUG_REG1__grp_te_valid__SHIFT                0x0000000b
+#define VGT_DEBUG_REG1__pt_grp_read__SHIFT                 0x0000000c
+#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT                0x0000000d
+#define VGT_DEBUG_REG1__vr_grp_read__SHIFT                 0x0000000e
+#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT                0x0000000f
+#define VGT_DEBUG_REG1__grp_dma_read__SHIFT                0x00000010
+#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT               0x00000011
+#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT            0x00000012
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT           0x00000013
+#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT                  0x00000014
+#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT                 0x00000015
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT           0x00000016
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT          0x00000017
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT           0x00000018
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT          0x00000019
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT           0x0000001a
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT          0x0000001b
+#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT                  0x0000001c
+#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT                 0x0000001d
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT              0x0000001e
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT                  0x00000000
+#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT            0x00000001
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT        0x00000000
+#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT           0x00000005
+#define VGT_DEBUG_REG6__input_data_valid__SHIFT            0x0000000a
+#define VGT_DEBUG_REG6__input_data_xfer__SHIFT             0x0000000b
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT      0x0000000c
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT      0x0000000d
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT  0x0000000e
+#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT      0x0000000f
+#define VGT_DEBUG_REG6__shifter_first_load__SHIFT          0x00000010
+#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT       0x00000013
+#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT             0x00000014
+#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT         0x00000015
+#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT        0x00000017
+#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT         0x00000018
+#define VGT_DEBUG_REG6__extract_vector__SHIFT              0x00000019
+#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT              0x0000001a
+#define VGT_DEBUG_REG6__destination_rtr__SHIFT             0x0000001b
+#define VGT_DEBUG_REG6__grp_trigger__SHIFT                 0x0000001c
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT          0x00000000
+#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT     0x00000010
+#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT        0x00000014
+#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG7__current_source_sel__SHIFT          0x0000001e
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel__SHIFT          0x00000000
+#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT            0x00000002
+#define VGT_DEBUG_REG8__input_data_cnt__SHIFT              0x00000007
+#define VGT_DEBUG_REG8__input_data_lsw__SHIFT              0x0000000c
+#define VGT_DEBUG_REG8__input_data_msw__SHIFT              0x00000011
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q__SHIFT               0x00000000
+#define VGT_DEBUG_REG9__next_stride_d__SHIFT               0x00000005
+#define VGT_DEBUG_REG9__current_shift_q__SHIFT             0x0000000a
+#define VGT_DEBUG_REG9__current_shift_d__SHIFT             0x0000000f
+#define VGT_DEBUG_REG9__current_stride_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG9__current_stride_d__SHIFT            0x00000019
+#define VGT_DEBUG_REG9__grp_trigger__SHIFT                 0x0000001e
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003
+#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT             0x00000004
+#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT        0x00000005
+#define VGT_DEBUG_REG10__bin_valid__SHIFT                  0x00000006
+#define VGT_DEBUG_REG10__read_block__SHIFT                 0x00000007
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT     0x00000008
+#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT          0x00000009
+#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG10__selected_data__SHIFT              0x0000000b
+#define VGT_DEBUG_REG10__mask_input_data__SHIFT            0x00000013
+#define VGT_DEBUG_REG10__gap_q__SHIFT                      0x0000001b
+#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT          0x0000001c
+#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT          0x0000001d
+#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT          0x0000001e
+#define VGT_DEBUG_REG10__grp_trigger__SHIFT                0x0000001f
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT       0x00000000
+#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT          0x00000005
+#define VGT_DEBUG_REG12__input_data_valid__SHIFT           0x0000000a
+#define VGT_DEBUG_REG12__input_data_xfer__SHIFT            0x0000000b
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT     0x0000000c
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT     0x0000000d
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e
+#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT     0x0000000f
+#define VGT_DEBUG_REG12__shifter_first_load__SHIFT         0x00000010
+#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT             0x00000011
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT      0x00000013
+#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT        0x00000015
+#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT       0x00000017
+#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT        0x00000018
+#define VGT_DEBUG_REG12__extract_vector__SHIFT             0x00000019
+#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT             0x0000001a
+#define VGT_DEBUG_REG12__destination_rtr__SHIFT            0x0000001b
+#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT               0x0000001c
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT         0x00000000
+#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT    0x00000010
+#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT       0x00000014
+#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT             0x00000018
+#define VGT_DEBUG_REG13__current_source_sel__SHIFT         0x0000001e
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel__SHIFT         0x00000000
+#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT           0x00000002
+#define VGT_DEBUG_REG14__input_data_cnt__SHIFT             0x00000007
+#define VGT_DEBUG_REG14__input_data_lsw__SHIFT             0x0000000c
+#define VGT_DEBUG_REG14__input_data_msw__SHIFT             0x00000011
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q__SHIFT              0x00000000
+#define VGT_DEBUG_REG15__next_stride_d__SHIFT              0x00000005
+#define VGT_DEBUG_REG15__current_shift_q__SHIFT            0x0000000a
+#define VGT_DEBUG_REG15__current_shift_d__SHIFT            0x0000000f
+#define VGT_DEBUG_REG15__current_stride_q__SHIFT           0x00000014
+#define VGT_DEBUG_REG15__current_stride_d__SHIFT           0x00000019
+#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT               0x0000001e
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT  0x00000000
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT   0x00000002
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT    0x00000003
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT   0x00000004
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT  0x00000005
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT   0x00000006
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT     0x00000007
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT         0x00000008
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT         0x00000009
+#define VGT_DEBUG_REG16__rst_last_bit__SHIFT               0x0000000a
+#define VGT_DEBUG_REG16__current_state_q__SHIFT            0x0000000b
+#define VGT_DEBUG_REG16__old_state_q__SHIFT                0x0000000c
+#define VGT_DEBUG_REG16__old_state_en__SHIFT               0x0000000d
+#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT            0x0000000e
+#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT             0x0000000f
+#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT           0x00000010
+#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT           0x00000011
+#define VGT_DEBUG_REG16__load_empty_reg__SHIFT             0x00000012
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT   0x00000013
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT   0x0000001e
+#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q__SHIFT                0x00000000
+#define VGT_DEBUG_REG17__extend_read_q__SHIFT              0x00000001
+#define VGT_DEBUG_REG17__grp_indx_size__SHIFT              0x00000002
+#define VGT_DEBUG_REG17__cull_prim_true__SHIFT             0x00000004
+#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT               0x00000005
+#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT               0x00000006
+#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT          0x00000007
+#define VGT_DEBUG_REG17__check_second_reg__SHIFT           0x00000008
+#define VGT_DEBUG_REG17__check_first_reg__SHIFT            0x00000009
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT    0x0000000b
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT    0x0000000c
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT     0x0000000d
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT     0x0000000e
+#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT            0x0000000f
+#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT            0x00000010
+#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT    0x00000000
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT    0x00000006
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d
+#define VGT_DEBUG_REG18__dma_mem_full__SHIFT               0x0000000f
+#define VGT_DEBUG_REG18__dma_ram_re__SHIFT                 0x00000010
+#define VGT_DEBUG_REG18__dma_ram_we__SHIFT                 0x00000011
+#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT              0x00000012
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT       0x00000013
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT       0x00000014
+#define VGT_DEBUG_REG18__bin_mem_full__SHIFT               0x00000015
+#define VGT_DEBUG_REG18__bin_ram_we__SHIFT                 0x00000016
+#define VGT_DEBUG_REG18__bin_ram_re__SHIFT                 0x00000017
+#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT              0x00000018
+#define VGT_DEBUG_REG18__start_bin_req__SHIFT              0x00000019
+#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT        0x0000001a
+#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT               0x0000001b
+#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT         0x0000001c
+#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT         0x0000001d
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT       0x00000000
+#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT       0x00000001
+#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT          0x00000002
+#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT          0x00000003
+#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT        0x00000004
+#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT          0x00000005
+#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT             0x00000006
+#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT             0x00000007
+#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT           0x00000008
+#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT          0x00000009
+#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT             0x0000000a
+#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT             0x0000000b
+#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT           0x0000000c
+#define VGT_DEBUG_REG20__hold_prim__SHIFT                  0x0000000d
+#define VGT_DEBUG_REG20__sent_cnt__SHIFT                   0x0000000e
+#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT        0x00000012
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT       0x00000013
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT       0x00000014
+#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT   0x00000015
+#define VGT_DEBUG_REG20__out_trigger__SHIFT                0x0000001a
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT  0x00000000
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001
+#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT            0x00000004
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT    0x00000007
+#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT    0x0000000e
+#define VGT_DEBUG_REG21__new_packet_q__SHIFT               0x00000012
+#define VGT_DEBUG_REG21__new_allocate_q__SHIFT             0x00000013
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT    0x00000014
+#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT       0x00000016
+#define VGT_DEBUG_REG21__insert_null_prim__SHIFT           0x00000017
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT      0x00000018
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT      0x00000019
+#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT       0x0000001a
+#define VGT_DEBUG_REG21__out_trigger__SHIFT                0x0000001f
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC__SHIFT                        0x00000000
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC__SHIFT                        0x00000000
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT             0x00000000
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT               0x00000000
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT              0x00000012
+#define TC_CNTL_STATUS__TC_BUSY__SHIFT                     0x0000001f
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT               0x00000008
+#define TCM_CHICKEN__SPARE__SHIFT                          0x00000009
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT          0x00000000
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT          0x00000003
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT             0x00000000
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT           0x00000001
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT        0x00000002
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT        0x00000003
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT       0x00000004
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT         0x00000005
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT            0x00000006
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT      0x00000008
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT        0x00000009
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT           0x0000000a
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT           0x0000000c
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT        0x0000000d
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT          0x0000000e
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT             0x0000000f
+#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT                  0x00000010
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT            0x00000011
+#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT                  0x00000013
+#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT                  0x00000014
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT               0x00000015
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT             0x00000016
+#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT                  0x00000017
+#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT                  0x00000018
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT               0x00000019
+#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT                  0x0000001b
+#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT                  0x0000001c
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT          0x0000001d
+#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT                  0x0000001e
+#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT                   0x0000001f
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL__SHIFT                        0x00000000
+#define TPC_DEBUG0__IC_CTR__SHIFT                          0x00000002
+#define TPC_DEBUG0__WALKER_CNTL__SHIFT                     0x00000004
+#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT                    0x00000008
+#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT             0x0000000c
+#define TPC_DEBUG0__WALKER_STATE__SHIFT                    0x00000010
+#define TPC_DEBUG0__ALIGNER_STATE__SHIFT                   0x0000001a
+#define TPC_DEBUG0__REG_CLK_EN__SHIFT                      0x0000001d
+#define TPC_DEBUG0__TPC_CLK_EN__SHIFT                      0x0000001e
+#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT                    0x0000001f
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED__SHIFT                          0x00000000
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION__SHIFT                0x00000000
+#define TPC_CHICKEN__SPARE__SHIFT                          0x00000001
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT              0x00000000
+#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT                0x00000001
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT           0x00000002
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT               0x00000003
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT         0x00000004
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT            0x00000005
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT            0x00000006
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT            0x00000007
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT              0x00000008
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT           0x00000009
+#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT                 0x0000000a
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT            0x0000000b
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT              0x0000000c
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT           0x0000000d
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT             0x0000000e
+#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT                  0x00000010
+#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT                  0x00000011
+#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT                  0x00000012
+#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT                  0x00000013
+#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT                  0x00000014
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT               0x00000015
+#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT                  0x00000016
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT               0x00000017
+#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT                  0x00000018
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT               0x00000019
+#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT                  0x0000001a
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT               0x0000001b
+#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT                  0x0000001c
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT             0x0000001d
+#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT                  0x0000001e
+#define TP0_CNTL_STATUS__TP_BUSY__SHIFT                    0x0000001f
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL__SHIFT                       0x00000000
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT                   0x00000003
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT             0x00000004
+#define TP0_DEBUG__REG_CLK_EN__SHIFT                       0x00000015
+#define TP0_DEBUG__PERF_CLK_EN__SHIFT                      0x00000016
+#define TP0_DEBUG__TP_CLK_EN__SHIFT                        0x00000017
+#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT                    0x00000018
+#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT                   0x0000001c
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE__SHIFT                        0x00000000
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT            0x00000001
+#define TP0_CHICKEN__SPARE__SHIFT                          0x00000002
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr__SHIFT                    0x00000006
+#define TCF_DEBUG__TC_MH_send__SHIFT                       0x00000007
+#define TCF_DEBUG__not_FG0_rtr__SHIFT                      0x00000008
+#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT                  0x0000000c
+#define TCF_DEBUG__TCB_ff_stall__SHIFT                     0x0000000d
+#define TCF_DEBUG__TCB_miss_stall__SHIFT                   0x0000000e
+#define TCF_DEBUG__TCA_TCB_stall__SHIFT                    0x0000000f
+#define TCF_DEBUG__PF0_stall__SHIFT                        0x00000010
+#define TCF_DEBUG__TP0_full__SHIFT                         0x00000014
+#define TCF_DEBUG__TPC_full__SHIFT                         0x00000018
+#define TCF_DEBUG__not_TPC_rtr__SHIFT                      0x00000019
+#define TCF_DEBUG__tca_state_rts__SHIFT                    0x0000001a
+#define TCF_DEBUG__tca_rts__SHIFT                          0x0000001b
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full__SHIFT                    0x00000000
+#define TCA_FIFO_DEBUG__tpc_full__SHIFT                    0x00000004
+#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT               0x00000005
+#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT               0x00000006
+#define TCA_FIFO_DEBUG__FW_full__SHIFT                     0x00000007
+#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT                 0x00000008
+#define TCA_FIFO_DEBUG__FW_rts0__SHIFT                     0x0000000c
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT              0x00000010
+#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT                  0x00000011
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT          0x00000000
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts__SHIFT             0x0000000c
+#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT              0x0000000d
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512__SHIFT                   0x00000000
+#define TCB_CORE_DEBUG__tiled__SHIFT                       0x00000001
+#define TCB_CORE_DEBUG__opcode__SHIFT                      0x00000004
+#define TCB_CORE_DEBUG__format__SHIFT                      0x00000008
+#define TCB_CORE_DEBUG__sector_format__SHIFT               0x00000010
+#define TCB_CORE_DEBUG__sector_format512__SHIFT            0x00000018
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG0_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG0_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG1_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG1_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG2_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG2_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG3_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG3_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT   0x00000004
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT    0x00000006
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT   0x0000000b
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT   0x0000000c
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT            0x0000000f
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT      0x00000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT       0x00000002
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT    0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT             0x00000017
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT         0x00000018
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT          0x00000019
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT         0x0000001a
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT          0x0000001c
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT          0x0000001e
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty__SHIFT                     0x00000010
+#define TCD_INPUT0_DEBUG__full__SHIFT                      0x00000011
+#define TCD_INPUT0_DEBUG__valid_q1__SHIFT                  0x00000014
+#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT                    0x00000015
+#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT              0x00000017
+#define TCD_INPUT0_DEBUG__ip_send__SHIFT                   0x00000018
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT            0x00000019
+#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT                0x0000001a
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT      0x00000000
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT          0x00000002
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT      0x00000003
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT           0x00000004
+#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT               0x00000005
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT              0x00000006
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT             0x00000009
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT         0x0000000a
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT           0x0000000b
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT  0x00000014
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT   0x0000001c
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT      0x0000001d
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT                0x00000004
+#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT                  0x00000005
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT    0x00000006
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT          0x00000007
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT       0x00000009
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT    0x0000000c
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT       0x00000012
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT         0x0000001e
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT         0x0000001f
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT   0x0000000a
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT   0x0000000b
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT         0x00000011
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT       0x00000012
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT          0x00000013
+#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT          0x0000001f
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT          0x00000005
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT           0x00000006
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT       0x00000007
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT       0x00000000
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT       0x00000008
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT                 0x00000009
+#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT                 0x0000000a
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT      0x0000000b
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT                0x0000000c
+#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT                0x0000000d
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT           0x00000010
+#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT              0x00000018
+#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT            0x00000019
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT  0x0000001a
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT  0x0000001b
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT  0x0000001c
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT  0x0000001d
+#define TCO_QUAD0_DEBUG0__busy__SHIFT                      0x0000001e
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT                 0x00000000
+#define TCO_QUAD0_DEBUG1__empty__SHIFT                     0x00000001
+#define TCO_QUAD0_DEBUG1__full__SHIFT                      0x00000002
+#define TCO_QUAD0_DEBUG1__write_enable__SHIFT              0x00000003
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT            0x00000004
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT             0x0000000b
+#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT           0x00000014
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT         0x00000015
+#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT           0x00000016
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT        0x00000017
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT             0x00000018
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT             0x00000019
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT                 0x0000001a
+#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT                 0x0000001b
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT                0x0000001c
+#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT                0x0000001d
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT          0x0000001e
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT              0x00000000
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT             0x00000004
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT             0x0000000c
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT   0x00000000
+#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT                 0x00000004
+#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT                    0x00000008
+#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT                 0x0000000c
+#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT                   0x00000010
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT               0x00000011
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT          0x00000012
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT      0x00000015
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT     0x00000016
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT               0x00000017
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT               0x00000018
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT           0x00000019
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT    0x0000001b
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT      0x00000000
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT      0x00000010
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT   0x00000010
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT                   0x00000000
+#define SQ_EO_RT__EO_TSTATE_RT__SHIFT                      0x00000010
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT               0x00000000
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT               0x0000000c
+#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT                  0x00000014
+#define SQ_DEBUG_MISC__RESERVED__SHIFT                     0x00000015
+#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT               0x00000017
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT              0x00000019
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT              0x0000001a
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT              0x0000001b
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT              0x0000001c
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT            0x00000000
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT       0x00000008
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT      0x00000010
+#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT               0x00000018
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT      0x00000000
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT      0x00000000
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT        0x00000003
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT      0x00000004
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT        0x00000007
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT            0x00000008
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT     0x00000000
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT       0x00000003
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT     0x00000004
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT       0x00000007
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT           0x00000008
+#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT            0x00000012
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016
+
+// SQ_VS_WATCHDOG_TIMER
+#define SQ_VS_WATCHDOG_TIMER__ENABLE__SHIFT                0x00000000
+#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT         0x00000001
+
+// SQ_PS_WATCHDOG_TIMER
+#define SQ_PS_WATCHDOG_TIMER__ENABLE__SHIFT                0x00000000
+#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT         0x00000001
+
+// SQ_INT_CNTL
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK__SHIFT               0x00000000
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK__SHIFT               0x00000001
+
+// SQ_INT_STATUS
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT__SHIFT          0x00000000
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT__SHIFT          0x00000001
+
+// SQ_INT_ACK
+#define SQ_INT_ACK__PS_WATCHDOG_ACK__SHIFT                 0x00000000
+#define SQ_INT_ACK__VS_WATCHDOG_ACK__SHIFT                 0x00000001
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT               0x00000000
+#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT                0x00000003
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT               0x00000004
+#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT                 0x00000008
+#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT                   0x0000000c
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT           0x0000000f
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT             0x00000014
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT           0x00000005
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT           0x0000000d
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT                      0x00000000
+#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT                  0x00000003
+#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT                      0x00000004
+#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT                      0x00000008
+#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT                  0x0000000b
+#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT                     0x0000000c
+#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT                  0x0000000e
+#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT                      0x00000010
+#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT                  0x00000012
+#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT                     0x00000014
+#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT                  0x00000016
+#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT                     0x00000018
+#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT                  0x0000001a
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT                  0x0000001c
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT           0x00000000
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT         0x00000004
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT            0x0000000c
+#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT                0x0000000f
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT     0x00000010
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT            0x00000000
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT              0x00000001
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT          0x00000005
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT         0x00000006
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT              0x00000009
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT               0x0000000e
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT        0x0000000f
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT                 0x00000010
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT             0x00000011
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT   0x0000001d
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT           0x00000000
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT               0x00000004
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT               0x00000008
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT        0x0000000c
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT         0x00000010
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT            0x00000014
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT                   0x00000015
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT              0x00000000
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT   0x00000000
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT     0x00000000
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT             0x00000000
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT                 0x00000006
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT                 0x0000000c
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT        0x00000013
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT          0x00000019
+#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT                     0x0000001f
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL__SHIFT        0x00000006
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT  0x00000007
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL__SHIFT        0x0000000e
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT           0x0000000f
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT        0x00000010
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT        0x00000014
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT          0x00000018
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT          0x00000019
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT         0x0000001a
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT       0x00000000
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT       0x00000002
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT       0x00000004
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT       0x00000006
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT       0x00000008
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT       0x0000000c
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT       0x0000000e
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT       0x00000010
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT       0x00000012
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT       0x00000014
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT       0x00000016
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT         0x00000019
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT           0x0000001b
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT       0x0000001e
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT       0x0000001f
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT          0x00000006
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT         0x00000007
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT          0x0000000e
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT         0x00000010
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT          0x00000016
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT         0x00000017
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT             0x0000001d
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT             0x0000001e
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT          0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT             0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT             0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT       0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT     0x00000013
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT       0x00000014
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT     0x00000015
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT       0x00000016
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT     0x00000017
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT       0x00000018
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT     0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT       0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT     0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT         0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT         0x0000001e
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT         0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT         0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT         0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT         0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT          0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT             0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT       0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT     0x00000003
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT       0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT     0x00000005
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT       0x00000006
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT     0x00000007
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT       0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT     0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT     0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT         0x0000000d
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT         0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT         0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT         0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT        0x0000000a
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT        0x00000015
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT        0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT        0x0000001a
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT          0x00000005
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT    0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT    0x0000000d
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT    0x0000000f
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT    0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT     0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT     0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT  0x0000000b
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT        0x0000000c
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT    0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT    0x0000001d
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT    0x0000001e
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT      0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT     0x00000012
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT  0x0000001b
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT        0x0000001c
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT         0x00000004
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT        0x00000008
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT    0x00000009
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT       0x0000000b
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT           0x0000000c
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT             0x00000010
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT       0x00000014
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT        0x00000018
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT    0x00000019
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT       0x0000001b
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT           0x0000001c
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT   0x00000013
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT    0x00000019
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT          0x0000001a
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT          0x0000001c
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT          0x0000001e
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT         0x00000010
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT       0x00000012
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT   0x00000015
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT     0x00000018
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT       0x0000001c
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT        0x0000001d
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT  0x00000000
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT    0x00000001
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT           0x00000002
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT             0x00000009
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT           0x00000010
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT           0x00000015
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT           0x0000001a
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT        0x00000013
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT    0x00000019
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT            0x0000001e
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT    0x0000000c
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT     0x0000000d
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT        0x00000010
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT     0x00000017
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT             0x00000010
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED__SHIFT                          0x00000000
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN__SHIFT                        0x00000000
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE__SHIFT                         0x00000000
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA__SHIFT                        0x00000000
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE__SHIFT                           0x00000000
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT                  0x00000000
+#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT                 0x00000001
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT          0x00000002
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT           0x00000000
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT         0x00000002
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE__SHIFT                       0x00000000
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE__SHIFT                       0x00000000
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT               0x00000000
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT               0x00000008
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT               0x00000010
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT               0x00000018
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT                   0x00000000
+#define SQ_CF_LOOP__CF_LOOP_START__SHIFT                   0x00000008
+#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT                    0x00000010
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED__SHIFT                       0x00000000
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN__SHIFT                     0x00000000
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE__SHIFT                      0x00000000
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA__SHIFT                     0x00000000
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE__SHIFT                        0x00000000
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT            0x00000000
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT            0x00000008
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT            0x00000010
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT            0x00000018
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT                0x00000000
+#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT                0x00000008
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT                 0x00000010
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_VS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_PS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT              0x00000000
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT              0x0000000c
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT           0x00000000
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT      0x00000010
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT                 0x00000000
+#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT                 0x00000008
+#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT                0x00000010
+#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT                0x00000011
+#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT                  0x00000012
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT              0x00000013
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT            0x00000014
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT             0x00000018
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT             0x0000001b
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT              0x0000001f
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT                 0x00000000
+#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT                 0x00000004
+#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT                 0x00000008
+#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT                 0x0000000c
+#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT                 0x00000010
+#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT                 0x00000014
+#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT                 0x00000018
+#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT                 0x0000001c
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT                 0x00000000
+#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT                 0x00000004
+#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT                0x00000008
+#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT                0x0000000c
+#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT                0x00000010
+#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT                0x00000014
+#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT                0x00000018
+#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT                0x0000001c
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_VS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_PS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT         0x00000000
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT        0x00000001
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT             0x00000002
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT              0x00000008
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT            0x00000010
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT             0x00000011
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT               0x00000012
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE__SHIFT                      0x00000000
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT                 0x00000000
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT              0x00000004
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT               0x00000008
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT              0x00000018
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT                  0x00000000
+#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT                  0x00000001
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT              0x00000008
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT              0x00000010
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT          0x00000000
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT    0x00000006
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT            0x00000007
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT       0x00000008
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT           0x00000009
+#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT                0x0000000a
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT        0x0000000d
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT       0x0000000e
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT   0x0000000f
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT          0x00000010
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT           0x00000016
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT          0x00000017
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT           0x00000018
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT           0x00000019
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT           0x0000001a
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT                0x00000000
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT             0x00000003
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT                0x00000004
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT             0x00000007
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT               0x00000008
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3__SHIFT             0x0000000b
+#define MH_CLNT_AXI_ID_REUSE__PAw_ID__SHIFT                0x0000000c
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT           0x00000000
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT          0x00000001
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT           0x00000002
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT         0x00000000
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT        0x00000001
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT         0x00000002
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT          0x00000000
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT         0x00000001
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT          0x00000002
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID__SHIFT                   0x00000000
+#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT                0x00000003
+#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT                  0x00000004
+#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT               0x00000007
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX__SHIFT                        0x00000000
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA__SHIFT                         0x00000000
+
+// MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL__AXI_HALT__SHIFT               0x00000000
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY__SHIFT                     0x00000000
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT           0x00000001
+#define MH_DEBUG_REG00__CP_REQUEST__SHIFT                  0x00000002
+#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT                 0x00000003
+#define MH_DEBUG_REG00__TC_REQUEST__SHIFT                  0x00000004
+#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT                0x00000005
+#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT                 0x00000006
+#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT                   0x00000007
+#define MH_DEBUG_REG00__TCD_FULL__SHIFT                    0x00000008
+#define MH_DEBUG_REG00__RB_REQUEST__SHIFT                  0x00000009
+#define MH_DEBUG_REG00__PA_REQUEST__SHIFT                  0x0000000a
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT             0x0000000b
+#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT                   0x0000000c
+#define MH_DEBUG_REG00__ARQ_FULL__SHIFT                    0x0000000d
+#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT                   0x0000000e
+#define MH_DEBUG_REG00__WDB_FULL__SHIFT                    0x0000000f
+#define MH_DEBUG_REG00__AXI_AVALID__SHIFT                  0x00000010
+#define MH_DEBUG_REG00__AXI_AREADY__SHIFT                  0x00000011
+#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT                 0x00000012
+#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT                 0x00000013
+#define MH_DEBUG_REG00__AXI_WVALID__SHIFT                  0x00000014
+#define MH_DEBUG_REG00__AXI_WREADY__SHIFT                  0x00000015
+#define MH_DEBUG_REG00__AXI_RVALID__SHIFT                  0x00000016
+#define MH_DEBUG_REG00__AXI_RREADY__SHIFT                  0x00000017
+#define MH_DEBUG_REG00__AXI_BVALID__SHIFT                  0x00000018
+#define MH_DEBUG_REG00__AXI_BREADY__SHIFT                  0x00000019
+#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT                0x0000001a
+#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT                0x0000001b
+#define MH_DEBUG_REG00__AXI_RDY_ENA__SHIFT                 0x0000001c
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q__SHIFT                   0x00000000
+#define MH_DEBUG_REG01__CP_RTR_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT                  0x00000002
+#define MH_DEBUG_REG01__CP_TAG_q__SHIFT                    0x00000003
+#define MH_DEBUG_REG01__CP_BLEN_q__SHIFT                   0x00000006
+#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT                  0x00000007
+#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG01__TC_SEND_q__SHIFT                   0x0000000a
+#define MH_DEBUG_REG01__TC_RTR_q__SHIFT                    0x0000000b
+#define MH_DEBUG_REG01__TC_BLEN_q__SHIFT                   0x0000000c
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT                0x0000000e
+#define MH_DEBUG_REG01__TC_MH_written__SHIFT               0x0000000f
+#define MH_DEBUG_REG01__RB_SEND_q__SHIFT                   0x00000010
+#define MH_DEBUG_REG01__RB_RTR_q__SHIFT                    0x00000011
+#define MH_DEBUG_REG01__PA_SEND_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG01__PA_RTR_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT               0x00000003
+#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT                 0x00000004
+#define MH_DEBUG_REG02__RDC_RID__SHIFT                     0x00000007
+#define MH_DEBUG_REG02__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT            0x0000000c
+#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT            0x0000000d
+#define MH_DEBUG_REG02__MH_PA_writeclean__SHIFT            0x0000000e
+#define MH_DEBUG_REG02__BRC_BID__SHIFT                     0x0000000f
+#define MH_DEBUG_REG02__BRC_BRESP__SHIFT                   0x00000012
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT           0x00000000
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT          0x00000000
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG05__CP_MH_write__SHIFT                 0x00000001
+#define MH_DEBUG_REG05__CP_MH_tag__SHIFT                   0x00000002
+#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT               0x00000005
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__CP_MH_be__SHIFT                    0x00000000
+#define MH_DEBUG_REG08__RB_MH_be__SHIFT                    0x00000008
+#define MH_DEBUG_REG08__PA_MH_be__SHIFT                    0x00000010
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG09__VGT_MH_send__SHIFT                 0x00000003
+#define MH_DEBUG_REG09__VGT_MH_tagbe__SHIFT                0x00000004
+#define MH_DEBUG_REG09__VGT_MH_ad_31_5__SHIFT              0x00000005
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG10__TC_MH_send__SHIFT                  0x00000002
+#define MH_DEBUG_REG10__TC_MH_mask__SHIFT                  0x00000003
+#define MH_DEBUG_REG10__TC_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__TC_MH_info__SHIFT                  0x00000000
+#define MH_DEBUG_REG11__TC_MH_send__SHIFT                  0x00000019
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__MH_TC_mcinfo__SHIFT                0x00000000
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send__SHIFT           0x00000019
+#define MH_DEBUG_REG12__TC_MH_written__SHIFT               0x0000001a
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT                 0x00000002
+#define MH_DEBUG_REG13__TC_ROQ_MASK__SHIFT                 0x00000003
+#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5__SHIFT            0x00000005
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__TC_ROQ_INFO__SHIFT                 0x00000000
+#define MH_DEBUG_REG14__TC_ROQ_SEND__SHIFT                 0x00000019
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG15__RB_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG15__RB_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__RB_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG18__PA_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG18__PA_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__PA_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__PA_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG21__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG21__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG21__ALEN_q_2_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG21__ARVALID_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG21__ARREADY_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG21__ARID_q__SHIFT                      0x0000000a
+#define MH_DEBUG_REG21__ARLEN_q_1_0__SHIFT                 0x0000000d
+#define MH_DEBUG_REG21__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG21__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG21__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG21__RID_q__SHIFT                       0x00000012
+#define MH_DEBUG_REG21__WVALID_q__SHIFT                    0x00000015
+#define MH_DEBUG_REG21__WREADY_q__SHIFT                    0x00000016
+#define MH_DEBUG_REG21__WLAST_q__SHIFT                     0x00000017
+#define MH_DEBUG_REG21__WID_q__SHIFT                       0x00000018
+#define MH_DEBUG_REG21__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG21__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG21__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG22__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG22__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG22__ALEN_q_1_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG22__ARVALID_q__SHIFT                   0x00000007
+#define MH_DEBUG_REG22__ARREADY_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG22__ARID_q__SHIFT                      0x00000009
+#define MH_DEBUG_REG22__ARLEN_q_1_1__SHIFT                 0x0000000c
+#define MH_DEBUG_REG22__WVALID_q__SHIFT                    0x0000000d
+#define MH_DEBUG_REG22__WREADY_q__SHIFT                    0x0000000e
+#define MH_DEBUG_REG22__WLAST_q__SHIFT                     0x0000000f
+#define MH_DEBUG_REG22__WID_q__SHIFT                       0x00000010
+#define MH_DEBUG_REG22__WSTRB_q__SHIFT                     0x00000013
+#define MH_DEBUG_REG22__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG22__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG22__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG23__CTRL_ARC_ID__SHIFT                 0x00000001
+#define MH_DEBUG_REG23__CTRL_ARC_PAD__SHIFT                0x00000004
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG24__REG_A__SHIFT                       0x00000002
+#define MH_DEBUG_REG24__REG_RE__SHIFT                      0x00000010
+#define MH_DEBUG_REG24__REG_WE__SHIFT                      0x00000011
+#define MH_DEBUG_REG24__BLOCK_RS__SHIFT                    0x00000012
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__REG_WD__SHIFT                      0x00000000
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__MH_RBBM_busy__SHIFT                0x00000000
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int__SHIFT        0x00000001
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int__SHIFT       0x00000002
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int__SHIFT     0x00000003
+#define MH_DEBUG_REG26__GAT_CLK_ENA__SHIFT                 0x00000004
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override__SHIFT     0x00000005
+#define MH_DEBUG_REG26__CNT_q__SHIFT                       0x00000006
+#define MH_DEBUG_REG26__TCD_EMPTY_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY__SHIFT                0x0000000d
+#define MH_DEBUG_REG26__MH_BUSY_d__SHIFT                   0x0000000e
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY__SHIFT               0x0000000f
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000010
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC__SHIFT 0x00000011
+#define MH_DEBUG_REG26__CP_SEND_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG26__CP_RTR_q__SHIFT                    0x00000013
+#define MH_DEBUG_REG26__VGT_SEND_q__SHIFT                  0x00000014
+#define MH_DEBUG_REG26__VGT_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT               0x00000016
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT            0x00000017
+#define MH_DEBUG_REG26__RB_SEND_q__SHIFT                   0x00000018
+#define MH_DEBUG_REG26__RB_RTR_q__SHIFT                    0x00000019
+#define MH_DEBUG_REG26__PA_SEND_q__SHIFT                   0x0000001a
+#define MH_DEBUG_REG26__PA_RTR_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG26__RDC_VALID__SHIFT                   0x0000001c
+#define MH_DEBUG_REG26__RDC_RLAST__SHIFT                   0x0000001d
+#define MH_DEBUG_REG26__TLBMISS_VALID__SHIFT               0x0000001e
+#define MH_DEBUG_REG26__BRC_VALID__SHIFT                   0x0000001f
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__EFF2_FP_WINNER__SHIFT              0x00000000
+#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out__SHIFT         0x00000003
+#define MH_DEBUG_REG27__EFF1_WINNER__SHIFT                 0x00000006
+#define MH_DEBUG_REG27__ARB_WINNER__SHIFT                  0x00000009
+#define MH_DEBUG_REG27__ARB_WINNER_q__SHIFT                0x0000000c
+#define MH_DEBUG_REG27__EFF1_WIN__SHIFT                    0x0000000f
+#define MH_DEBUG_REG27__KILL_EFF1__SHIFT                   0x00000010
+#define MH_DEBUG_REG27__ARB_HOLD__SHIFT                    0x00000011
+#define MH_DEBUG_REG27__ARB_RTR_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG27__CP_SEND_QUAL__SHIFT                0x00000013
+#define MH_DEBUG_REG27__VGT_SEND_QUAL__SHIFT               0x00000014
+#define MH_DEBUG_REG27__TC_SEND_QUAL__SHIFT                0x00000015
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL__SHIFT           0x00000016
+#define MH_DEBUG_REG27__RB_SEND_QUAL__SHIFT                0x00000017
+#define MH_DEBUG_REG27__PA_SEND_QUAL__SHIFT                0x00000018
+#define MH_DEBUG_REG27__ARB_QUAL__SHIFT                    0x00000019
+#define MH_DEBUG_REG27__CP_EFF1_REQ__SHIFT                 0x0000001a
+#define MH_DEBUG_REG27__VGT_EFF1_REQ__SHIFT                0x0000001b
+#define MH_DEBUG_REG27__TC_EFF1_REQ__SHIFT                 0x0000001c
+#define MH_DEBUG_REG27__RB_EFF1_REQ__SHIFT                 0x0000001d
+#define MH_DEBUG_REG27__TCD_NEARFULL_q__SHIFT              0x0000001e
+#define MH_DEBUG_REG27__TCHOLD_IP_q__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__EFF1_WINNER__SHIFT                 0x00000000
+#define MH_DEBUG_REG28__ARB_WINNER__SHIFT                  0x00000003
+#define MH_DEBUG_REG28__CP_SEND_QUAL__SHIFT                0x00000006
+#define MH_DEBUG_REG28__VGT_SEND_QUAL__SHIFT               0x00000007
+#define MH_DEBUG_REG28__TC_SEND_QUAL__SHIFT                0x00000008
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL__SHIFT           0x00000009
+#define MH_DEBUG_REG28__RB_SEND_QUAL__SHIFT                0x0000000a
+#define MH_DEBUG_REG28__ARB_QUAL__SHIFT                    0x0000000b
+#define MH_DEBUG_REG28__CP_EFF1_REQ__SHIFT                 0x0000000c
+#define MH_DEBUG_REG28__VGT_EFF1_REQ__SHIFT                0x0000000d
+#define MH_DEBUG_REG28__TC_EFF1_REQ__SHIFT                 0x0000000e
+#define MH_DEBUG_REG28__RB_EFF1_REQ__SHIFT                 0x0000000f
+#define MH_DEBUG_REG28__EFF1_WIN__SHIFT                    0x00000010
+#define MH_DEBUG_REG28__KILL_EFF1__SHIFT                   0x00000011
+#define MH_DEBUG_REG28__TCD_NEARFULL_q__SHIFT              0x00000012
+#define MH_DEBUG_REG28__TC_ARB_HOLD__SHIFT                 0x00000013
+#define MH_DEBUG_REG28__ARB_HOLD__SHIFT                    0x00000014
+#define MH_DEBUG_REG28__ARB_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q__SHIFT     0x00000016
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out__SHIFT         0x00000000
+#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d__SHIFT        0x00000003
+#define MH_DEBUG_REG29__LEAST_RECENT_d__SHIFT              0x00000006
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d__SHIFT       0x00000009
+#define MH_DEBUG_REG29__ARB_HOLD__SHIFT                    0x0000000a
+#define MH_DEBUG_REG29__ARB_RTR_q__SHIFT                   0x0000000b
+#define MH_DEBUG_REG29__CLNT_REQ__SHIFT                    0x0000000c
+#define MH_DEBUG_REG29__RECENT_d_0__SHIFT                  0x00000011
+#define MH_DEBUG_REG29__RECENT_d_1__SHIFT                  0x00000014
+#define MH_DEBUG_REG29__RECENT_d_2__SHIFT                  0x00000017
+#define MH_DEBUG_REG29__RECENT_d_3__SHIFT                  0x0000001a
+#define MH_DEBUG_REG29__RECENT_d_4__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__TC_ARB_HOLD__SHIFT                 0x00000000
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK__SHIFT      0x00000001
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK__SHIFT        0x00000002
+#define MH_DEBUG_REG30__TCD_NEARFULL_q__SHIFT              0x00000003
+#define MH_DEBUG_REG30__TCHOLD_IP_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG30__TCHOLD_CNT_q__SHIFT                0x00000005
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q__SHIFT            0x00000009
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q__SHIFT               0x0000000a
+#define MH_DEBUG_REG30__TC_MH_written__SHIFT               0x0000000b
+#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q__SHIFT          0x0000000c
+#define MH_DEBUG_REG30__WBURST_ACTIVE__SHIFT               0x00000013
+#define MH_DEBUG_REG30__WLAST_q__SHIFT                     0x00000014
+#define MH_DEBUG_REG30__WBURST_IP_q__SHIFT                 0x00000015
+#define MH_DEBUG_REG30__WBURST_CNT_q__SHIFT                0x00000016
+#define MH_DEBUG_REG30__CP_SEND_QUAL__SHIFT                0x00000019
+#define MH_DEBUG_REG30__CP_MH_write__SHIFT                 0x0000001a
+#define MH_DEBUG_REG30__RB_SEND_QUAL__SHIFT                0x0000001b
+#define MH_DEBUG_REG30__PA_SEND_QUAL__SHIFT                0x0000001c
+#define MH_DEBUG_REG30__ARB_WINNER__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q__SHIFT         0x00000000
+#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG32__ROQ_MARK_q__SHIFT                  0x00000008
+#define MH_DEBUG_REG32__ROQ_VALID_q__SHIFT                 0x00000010
+#define MH_DEBUG_REG32__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG32__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG32__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG32__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG33__ROQ_MARK_d__SHIFT                  0x00000008
+#define MH_DEBUG_REG33__ROQ_VALID_d__SHIFT                 0x00000010
+#define MH_DEBUG_REG33__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG33__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG33__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG33__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN__SHIFT           0x00000000
+#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ__SHIFT           0x00000008
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN__SHIFT       0x00000010
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ__SHIFT       0x00000018
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG35__ROQ_MARK_q_0__SHIFT                0x00000002
+#define MH_DEBUG_REG35__ROQ_VALID_q_0__SHIFT               0x00000003
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0__SHIFT           0x00000004
+#define MH_DEBUG_REG35__ROQ_ADDR_0__SHIFT                  0x00000005
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG36__ROQ_MARK_q_1__SHIFT                0x00000002
+#define MH_DEBUG_REG36__ROQ_VALID_q_1__SHIFT               0x00000003
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1__SHIFT           0x00000004
+#define MH_DEBUG_REG36__ROQ_ADDR_1__SHIFT                  0x00000005
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG37__ROQ_MARK_q_2__SHIFT                0x00000002
+#define MH_DEBUG_REG37__ROQ_VALID_q_2__SHIFT               0x00000003
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2__SHIFT           0x00000004
+#define MH_DEBUG_REG37__ROQ_ADDR_2__SHIFT                  0x00000005
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG38__ROQ_MARK_q_3__SHIFT                0x00000002
+#define MH_DEBUG_REG38__ROQ_VALID_q_3__SHIFT               0x00000003
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3__SHIFT           0x00000004
+#define MH_DEBUG_REG38__ROQ_ADDR_3__SHIFT                  0x00000005
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG39__ROQ_MARK_q_4__SHIFT                0x00000002
+#define MH_DEBUG_REG39__ROQ_VALID_q_4__SHIFT               0x00000003
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4__SHIFT           0x00000004
+#define MH_DEBUG_REG39__ROQ_ADDR_4__SHIFT                  0x00000005
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG40__ROQ_MARK_q_5__SHIFT                0x00000002
+#define MH_DEBUG_REG40__ROQ_VALID_q_5__SHIFT               0x00000003
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5__SHIFT           0x00000004
+#define MH_DEBUG_REG40__ROQ_ADDR_5__SHIFT                  0x00000005
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG41__ROQ_MARK_q_6__SHIFT                0x00000002
+#define MH_DEBUG_REG41__ROQ_VALID_q_6__SHIFT               0x00000003
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6__SHIFT           0x00000004
+#define MH_DEBUG_REG41__ROQ_ADDR_6__SHIFT                  0x00000005
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG42__ROQ_MARK_q_7__SHIFT                0x00000002
+#define MH_DEBUG_REG42__ROQ_VALID_q_7__SHIFT               0x00000003
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7__SHIFT           0x00000004
+#define MH_DEBUG_REG42__ROQ_ADDR_7__SHIFT                  0x00000005
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_REG_WE_q__SHIFT                0x00000000
+#define MH_DEBUG_REG43__ARB_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG43__ARB_REG_VALID_q__SHIFT             0x00000002
+#define MH_DEBUG_REG43__ARB_RTR_q__SHIFT                   0x00000003
+#define MH_DEBUG_REG43__ARB_REG_RTR__SHIFT                 0x00000004
+#define MH_DEBUG_REG43__WDAT_BURST_RTR__SHIFT              0x00000005
+#define MH_DEBUG_REG43__MMU_RTR__SHIFT                     0x00000006
+#define MH_DEBUG_REG43__ARB_ID_q__SHIFT                    0x00000007
+#define MH_DEBUG_REG43__ARB_WRITE_q__SHIFT                 0x0000000a
+#define MH_DEBUG_REG43__ARB_BLEN_q__SHIFT                  0x0000000b
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY__SHIFT              0x0000000c
+#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q__SHIFT              0x0000000d
+#define MH_DEBUG_REG43__MMU_WE__SHIFT                      0x00000010
+#define MH_DEBUG_REG43__ARQ_RTR__SHIFT                     0x00000011
+#define MH_DEBUG_REG43__MMU_ID__SHIFT                      0x00000012
+#define MH_DEBUG_REG43__MMU_WRITE__SHIFT                   0x00000015
+#define MH_DEBUG_REG43__MMU_BLEN__SHIFT                    0x00000016
+#define MH_DEBUG_REG43__WBURST_IP_q__SHIFT                 0x00000017
+#define MH_DEBUG_REG43__WDAT_REG_WE_q__SHIFT               0x00000018
+#define MH_DEBUG_REG43__WDB_WE__SHIFT                      0x00000019
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4__SHIFT              0x0000001a
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3__SHIFT              0x0000001b
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG44__ARB_ID_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG44__ARB_VAD_q__SHIFT                   0x00000004
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__MMU_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG45__MMU_ID__SHIFT                      0x00000001
+#define MH_DEBUG_REG45__MMU_PAD__SHIFT                     0x00000004
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDAT_REG_WE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG46__WDB_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q__SHIFT            0x00000002
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4__SHIFT              0x00000003
+#define MH_DEBUG_REG46__ARB_WSTRB_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG46__ARB_WLAST__SHIFT                   0x0000000c
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY__SHIFT              0x0000000d
+#define MH_DEBUG_REG46__WDB_FIFO_CNT_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG46__WDC_WDB_RE_q__SHIFT                0x00000013
+#define MH_DEBUG_REG46__WDB_WDC_WID__SHIFT                 0x00000014
+#define MH_DEBUG_REG46__WDB_WDC_WLAST__SHIFT               0x00000017
+#define MH_DEBUG_REG46__WDB_WDC_WSTRB__SHIFT               0x00000018
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0__SHIFT          0x00000000
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32__SHIFT         0x00000000
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY__SHIFT              0x00000000
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY__SHIFT             0x00000001
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY__SHIFT              0x00000002
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE__SHIFT              0x00000003
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS__SHIFT            0x00000004
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q__SHIFT           0x00000005
+#define MH_DEBUG_REG49__INFLT_LIMIT_q__SHIFT               0x00000006
+#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q__SHIFT           0x00000007
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG49__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG49__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG49__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG49__BVALID_q__SHIFT                    0x00000012
+#define MH_DEBUG_REG49__BREADY_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG50__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG50__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND__SHIFT             0x00000003
+#define MH_DEBUG_REG50__TLBMISS_VALID__SHIFT               0x00000004
+#define MH_DEBUG_REG50__RDC_VALID__SHIFT                   0x00000005
+#define MH_DEBUG_REG50__RDC_RID__SHIFT                     0x00000006
+#define MH_DEBUG_REG50__RDC_RLAST__SHIFT                   0x00000009
+#define MH_DEBUG_REG50__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS__SHIFT            0x0000000c
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q__SHIFT           0x0000000d
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q__SHIFT            0x0000000e
+#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q__SHIFT     0x0000000f
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE__SHIFT             0x00000015
+#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q__SHIFT        0x00000016
+#define MH_DEBUG_REG50__CNT_HOLD_q1__SHIFT                 0x0000001c
+#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT__SHIFT           0x00000000
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0__SHIFT      0x00000000
+#define MH_DEBUG_REG52__ARB_WE__SHIFT                      0x00000002
+#define MH_DEBUG_REG52__MMU_RTR__SHIFT                     0x00000003
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4__SHIFT     0x00000004
+#define MH_DEBUG_REG52__ARB_ID_q__SHIFT                    0x0000001a
+#define MH_DEBUG_REG52__ARB_WRITE_q__SHIFT                 0x0000001d
+#define MH_DEBUG_REG52__client_behavior_q__SHIFT           0x0000001e
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__stage1_valid__SHIFT                0x00000000
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q__SHIFT           0x00000001
+#define MH_DEBUG_REG53__pa_in_mpu_range__SHIFT             0x00000002
+#define MH_DEBUG_REG53__tag_match_q__SHIFT                 0x00000003
+#define MH_DEBUG_REG53__tag_miss_q__SHIFT                  0x00000004
+#define MH_DEBUG_REG53__va_in_range_q__SHIFT               0x00000005
+#define MH_DEBUG_REG53__MMU_MISS__SHIFT                    0x00000006
+#define MH_DEBUG_REG53__MMU_READ_MISS__SHIFT               0x00000007
+#define MH_DEBUG_REG53__MMU_WRITE_MISS__SHIFT              0x00000008
+#define MH_DEBUG_REG53__MMU_HIT__SHIFT                     0x00000009
+#define MH_DEBUG_REG53__MMU_READ_HIT__SHIFT                0x0000000a
+#define MH_DEBUG_REG53__MMU_WRITE_HIT__SHIFT               0x0000000b
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS__SHIFT      0x0000000c
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT__SHIFT       0x0000000d
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS__SHIFT   0x0000000e
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT__SHIFT    0x0000000f
+#define MH_DEBUG_REG53__REQ_VA_OFFSET_q__SHIFT             0x00000010
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__ARQ_RTR__SHIFT                     0x00000000
+#define MH_DEBUG_REG54__MMU_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q__SHIFT           0x00000002
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS__SHIFT            0x00000003
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND__SHIFT             0x00000004
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005
+#define MH_DEBUG_REG54__pa_in_mpu_range__SHIFT             0x00000006
+#define MH_DEBUG_REG54__stage1_valid__SHIFT                0x00000007
+#define MH_DEBUG_REG54__stage2_valid__SHIFT                0x00000008
+#define MH_DEBUG_REG54__client_behavior_q__SHIFT           0x00000009
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q__SHIFT           0x0000000b
+#define MH_DEBUG_REG54__tag_match_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG54__tag_miss_q__SHIFT                  0x0000000d
+#define MH_DEBUG_REG54__va_in_range_q__SHIFT               0x0000000e
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q__SHIFT        0x0000000f
+#define MH_DEBUG_REG54__TAG_valid_q__SHIFT                 0x00000010
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG0_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG55__TAG_valid_q_0__SHIFT               0x0000000d
+#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG55__TAG1_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG55__TAG_valid_q_1__SHIFT               0x0000001d
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG2_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG56__TAG_valid_q_2__SHIFT               0x0000000d
+#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG56__TAG3_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG56__TAG_valid_q_3__SHIFT               0x0000001d
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG4_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG57__TAG_valid_q_4__SHIFT               0x0000000d
+#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG57__TAG5_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG57__TAG_valid_q_5__SHIFT               0x0000001d
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG6_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG58__TAG_valid_q_6__SHIFT               0x0000000d
+#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG58__TAG7_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG58__TAG_valid_q_7__SHIFT               0x0000001d
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG8_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG59__TAG_valid_q_8__SHIFT               0x0000000d
+#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG59__TAG9_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG59__TAG_valid_q_9__SHIFT               0x0000001d
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG10_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG60__TAG_valid_q_10__SHIFT              0x0000000d
+#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG60__TAG11_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG60__TAG_valid_q_11__SHIFT              0x0000001d
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__TAG12_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG61__TAG_valid_q_12__SHIFT              0x0000000d
+#define MH_DEBUG_REG61__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG61__TAG13_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG61__TAG_valid_q_13__SHIFT              0x0000001d
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__TAG14_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG62__TAG_valid_q_14__SHIFT              0x0000000d
+#define MH_DEBUG_REG62__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG62__TAG15_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG62__TAG_valid_q_15__SHIFT              0x0000001d
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT                   0x00000000
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT            0x00000001
+#define MH_MMU_CONFIG__RESERVED1__SHIFT                    0x00000002
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT           0x00000004
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT           0x00000006
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT          0x00000008
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT          0x0000000a
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT          0x0000000c
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT          0x0000000e
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT          0x00000010
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT         0x00000012
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT         0x00000014
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT           0x00000016
+#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT           0x00000018
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT           0x00000000
+#define MH_MMU_VA_RANGE__VA_BASE__SHIFT                    0x0000000c
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE__SHIFT                     0x0000000c
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT               0x00000000
+#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT                  0x00000001
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT            0x00000002
+#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT                   0x00000004
+#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT                0x00000007
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT     0x00000009
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT    0x0000000a
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT   0x0000000b
+#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT                   0x0000000c
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT               0x00000005
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT           0x00000000
+#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT            0x00000001
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT                   0x0000000c
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END__SHIFT                     0x0000000c
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT                   0x00000001
+#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT                   0x00000002
+#define WAIT_UNTIL__WAIT_VSYNC__SHIFT                      0x00000003
+#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT                  0x00000004
+#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT                  0x00000005
+#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT                  0x00000006
+#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT                    0x0000000a
+#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT                    0x0000000e
+#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT                    0x0000000f
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT               0x00000010
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT               0x00000011
+#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT                 0x00000014
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT         0x00000004
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT    0x00000005
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT                  0x00000000
+#define RBBM_STATUS__TC_BUSY__SHIFT                        0x00000005
+#define RBBM_STATUS__HIRQ_PENDING__SHIFT                   0x00000008
+#define RBBM_STATUS__CPRQ_PENDING__SHIFT                   0x00000009
+#define RBBM_STATUS__CFRQ_PENDING__SHIFT                   0x0000000a
+#define RBBM_STATUS__PFRQ_PENDING__SHIFT                   0x0000000b
+#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT                0x0000000c
+#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT                   0x0000000e
+#define RBBM_STATUS__CP_NRT_BUSY__SHIFT                    0x00000010
+#define RBBM_STATUS__MH_BUSY__SHIFT                        0x00000012
+#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT              0x00000013
+#define RBBM_STATUS__SX_BUSY__SHIFT                        0x00000015
+#define RBBM_STATUS__TPC_BUSY__SHIFT                       0x00000016
+#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT                   0x00000018
+#define RBBM_STATUS__PA_BUSY__SHIFT                        0x00000019
+#define RBBM_STATUS__VGT_BUSY__SHIFT                       0x0000001a
+#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT                 0x0000001b
+#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT                  0x0000001c
+#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT                   0x0000001e
+#define RBBM_STATUS__GUI_ACTIVE__SHIFT                     0x0000001f
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0__SHIFT           0x00000000
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1__SHIFT           0x00000001
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2__SHIFT           0x00000002
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID__SHIFT             0x00000003
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0__SHIFT              0x00000004
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1__SHIFT              0x00000005
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2__SHIFT              0x00000006
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL__SHIFT                 0x00000007
+#define RBBM_DSPLY__DMI_CH1_NUM_BUFS__SHIFT                0x00000008
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0__SHIFT              0x0000000a
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1__SHIFT              0x0000000b
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2__SHIFT              0x0000000c
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL__SHIFT                 0x0000000d
+#define RBBM_DSPLY__DMI_CH2_NUM_BUFS__SHIFT                0x0000000e
+#define RBBM_DSPLY__DMI_CHANNEL_SELECT__SHIFT              0x00000010
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0__SHIFT              0x00000014
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1__SHIFT              0x00000015
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2__SHIFT              0x00000016
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL__SHIFT                 0x00000017
+#define RBBM_DSPLY__DMI_CH3_NUM_BUFS__SHIFT                0x00000018
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0__SHIFT              0x0000001a
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1__SHIFT              0x0000001b
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2__SHIFT              0x0000001c
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL__SHIFT                 0x0000001d
+#define RBBM_DSPLY__DMI_CH4_NUM_BUFS__SHIFT                0x0000001e
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID__SHIFT       0x00000000
+#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID__SHIFT       0x00000008
+#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID__SHIFT       0x00000010
+#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID__SHIFT       0x00000018
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT                0x00000000
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT          0x00000000
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT         0x00000010
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT             0x00000018
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT             0x00000000
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT                 0x00000000
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT                 0x00000000
+#define RBBM_PERIPHID1__DESIGNER0__SHIFT                   0x00000004
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1__SHIFT                   0x00000000
+#define RBBM_PERIPHID2__REVISION__SHIFT                    0x00000004
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT         0x00000000
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT        0x00000002
+#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT                0x00000004
+#define RBBM_PERIPHID3__CONTINUATION__SHIFT                0x00000007
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT__SHIFT                     0x00000000
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT             0x00000008
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT          0x00000000
+#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT                  0x00000005
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT              0x00000000
+#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT              0x00000002
+#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT              0x00000003
+#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT              0x00000004
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT              0x00000005
+#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT              0x00000006
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT             0x0000000c
+#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT              0x0000000f
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT             0x00000010
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000001
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT      0x00000002
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT  0x00000003
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT   0x00000004
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000005
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT   0x00000008
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT      0x00000009
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT   0x00000014
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000015
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT    0x00000016
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000017
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT     0x00000019
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001a
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT      0x0000001b
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT   0x0000001c
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001d
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT  0x0000001e
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT   0x00000001
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT   0x00000002
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT    0x00000007
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT  0x00000008
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT  0x00000009
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT  0x0000000b
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT              0x00000000
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK__SHIFT           0x00000010
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP__SHIFT             0x00000018
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI__SHIFT                0x00000019
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE__SHIFT    0x0000001d
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE__SHIFT       0x0000001e
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT           0x0000001f
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT                 0x00000000
+
+// RBBM_DEBUG_OUT
+#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT__SHIFT               0x00000000
+
+// RBBM_DEBUG_CNTL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR__SHIFT             0x00000000
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL__SHIFT              0x00000008
+#define RBBM_DEBUG_CNTL__SW_ENABLE__SHIFT                  0x0000000c
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR__SHIFT        0x00000010
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL__SHIFT         0x00000018
+#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB__SHIFT         0x0000001c
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR__SHIFT                      0x00000001
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT              0x00000002
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT           0x00000003
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT           0x00000004
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT       0x00000008
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT               0x00000010
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000011
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT   0x00000012
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000013
+#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT                  0x00000014
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT                 0x00000015
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT                  0x00000016
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT      0x00000017
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT             0x00000018
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT             0x0000001f
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT               0x00000002
+#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT             0x0000001e
+#define RBBM_READ_ERROR__READ_ERROR__SHIFT                 0x0000001f
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT               0x00000000
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT      0x00000001
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT            0x00000013
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT             0x00000000
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT    0x00000001
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT          0x00000013
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT                 0x00000000
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT        0x00000001
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT              0x00000013
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT              0x00000005
+#define MASTER_INT_SIGNAL__SQ_INT_STAT__SHIFT              0x0000001a
+#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT              0x0000001e
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT            0x0000001f
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT   0x00000000
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT        0x00000000
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT        0x00000000
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE__SHIFT                         0x00000005
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT                        0x00000000
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT                        0x00000008
+#define CP_RB_CNTL__BUF_SWAP__SHIFT                        0x00000010
+#define CP_RB_CNTL__RB_POLL_EN__SHIFT                      0x00000014
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT                    0x0000001b
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT                  0x0000001f
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT               0x00000002
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR__SHIFT                         0x00000000
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT                   0x00000000
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR__SHIFT                         0x00000000
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT           0x00000000
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT           0x0000001c
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT               0x00000002
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE__SHIFT                       0x00000002
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT                     0x00000000
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE__SHIFT                       0x00000002
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT                     0x00000000
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE__SHIFT                         0x00000002
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT                       0x00000000
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT          0x00000000
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT          0x00000008
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT           0x00000010
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT                  0x00000010
+#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT                  0x00000018
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT                  0x00000000
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT                   0x00000008
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT                   0x00000010
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT                    0x00000000
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT                       0x00000000
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT            0x00000000
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT            0x00000010
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT         0x00000000
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT         0x00000010
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT         0x00000000
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT         0x00000010
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT          0x00000000
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT          0x00000008
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT                 0x00000000
+#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT                 0x00000010
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT                       0x00000000
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT                       0x00000010
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT                 0x00000000
+#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT                 0x00000001
+#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT                 0x00000002
+#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT                 0x00000003
+#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT                 0x00000004
+#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT                 0x00000005
+#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT                 0x00000006
+#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT                 0x00000007
+#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT                 0x00000008
+#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT                 0x00000009
+#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT                0x0000000a
+#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT                0x0000000b
+#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT                0x0000000c
+#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT                0x0000000d
+#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT                0x0000000e
+#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT                0x0000000f
+#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT                0x00000010
+#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT                0x00000011
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT         0x0000001f
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT                     0x00000000
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT                 0x00000010
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA__SHIFT                       0x00000000
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX__SHIFT                      0x00000000
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT          0x00000019
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT          0x0000001a
+#define CP_ME_CNTL__ME_HALT__SHIFT                         0x0000001c
+#define CP_ME_CNTL__ME_BUSY__SHIFT                         0x0000001d
+#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT                   0x0000001f
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT                 0x00000000
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT                 0x00000000
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR__SHIFT                     0x00000000
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT           0x00000000
+#define CP_DEBUG__PREDICATE_DISABLE__SHIFT                 0x00000017
+#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT               0x00000018
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT           0x00000019
+#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT                0x0000001a
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT               0x0000001b
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT            0x0000001c
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT            0x0000001e
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT            0x0000001f
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT              0x00000000
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT              0x00000000
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT              0x00000000
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT              0x00000000
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT              0x00000000
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT              0x00000000
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT              0x00000000
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT              0x00000000
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT                  0x00000000
+#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT                  0x00000010
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT                  0x00000005
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT             0x00000000
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT              0x00000000
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT              0x00000002
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT              0x00000000
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK__SHIFT                    0x00000013
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT           0x00000017
+#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT              0x00000018
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT      0x00000019
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT        0x0000001a
+#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT                  0x0000001b
+#define CP_INT_CNTL__IB2_INT_MASK__SHIFT                   0x0000001d
+#define CP_INT_CNTL__IB1_INT_MASK__SHIFT                   0x0000001e
+#define CP_INT_CNTL__RB_INT_MASK__SHIFT                    0x0000001f
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT__SHIFT                  0x00000013
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT         0x00000017
+#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT            0x00000018
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT    0x00000019
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT      0x0000001a
+#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT                0x0000001b
+#define CP_INT_STATUS__IB2_INT_STAT__SHIFT                 0x0000001d
+#define CP_INT_STATUS__IB1_INT_STAT__SHIFT                 0x0000001e
+#define CP_INT_STATUS__RB_INT_STAT__SHIFT                  0x0000001f
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK__SHIFT                      0x00000013
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT             0x00000017
+#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT                0x00000018
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT        0x00000019
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT          0x0000001a
+#define CP_INT_ACK__IB_ERROR_ACK__SHIFT                    0x0000001b
+#define CP_INT_ACK__IB2_INT_ACK__SHIFT                     0x0000001d
+#define CP_INT_ACK__IB1_INT_ACK__SHIFT                     0x0000001e
+#define CP_INT_ACK__RB_INT_ACK__SHIFT                      0x0000001f
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT               0x00000000
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT               0x00000000
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT              0x00000000
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT        0x00000008
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT        0x00000000
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT             0x00000000
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT             0x00000000
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT                 0x00000000
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT                 0x00000000
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT             0x00000000
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT             0x00000000
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0__SHIFT                    0x00000000
+#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT                   0x00000001
+#define CP_NV_FLAGS_0__DISCARD_1__SHIFT                    0x00000002
+#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT                   0x00000003
+#define CP_NV_FLAGS_0__DISCARD_2__SHIFT                    0x00000004
+#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT                   0x00000005
+#define CP_NV_FLAGS_0__DISCARD_3__SHIFT                    0x00000006
+#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT                   0x00000007
+#define CP_NV_FLAGS_0__DISCARD_4__SHIFT                    0x00000008
+#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT                   0x00000009
+#define CP_NV_FLAGS_0__DISCARD_5__SHIFT                    0x0000000a
+#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT                   0x0000000b
+#define CP_NV_FLAGS_0__DISCARD_6__SHIFT                    0x0000000c
+#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT                   0x0000000d
+#define CP_NV_FLAGS_0__DISCARD_7__SHIFT                    0x0000000e
+#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT                   0x0000000f
+#define CP_NV_FLAGS_0__DISCARD_8__SHIFT                    0x00000010
+#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT                   0x00000011
+#define CP_NV_FLAGS_0__DISCARD_9__SHIFT                    0x00000012
+#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT                   0x00000013
+#define CP_NV_FLAGS_0__DISCARD_10__SHIFT                   0x00000014
+#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT                  0x00000015
+#define CP_NV_FLAGS_0__DISCARD_11__SHIFT                   0x00000016
+#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT                  0x00000017
+#define CP_NV_FLAGS_0__DISCARD_12__SHIFT                   0x00000018
+#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT                  0x00000019
+#define CP_NV_FLAGS_0__DISCARD_13__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_0__DISCARD_14__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_0__DISCARD_15__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16__SHIFT                   0x00000000
+#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT                  0x00000001
+#define CP_NV_FLAGS_1__DISCARD_17__SHIFT                   0x00000002
+#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT                  0x00000003
+#define CP_NV_FLAGS_1__DISCARD_18__SHIFT                   0x00000004
+#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT                  0x00000005
+#define CP_NV_FLAGS_1__DISCARD_19__SHIFT                   0x00000006
+#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT                  0x00000007
+#define CP_NV_FLAGS_1__DISCARD_20__SHIFT                   0x00000008
+#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT                  0x00000009
+#define CP_NV_FLAGS_1__DISCARD_21__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_1__DISCARD_22__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_1__DISCARD_23__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_1__DISCARD_24__SHIFT                   0x00000010
+#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT                  0x00000011
+#define CP_NV_FLAGS_1__DISCARD_25__SHIFT                   0x00000012
+#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT                  0x00000013
+#define CP_NV_FLAGS_1__DISCARD_26__SHIFT                   0x00000014
+#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT                  0x00000015
+#define CP_NV_FLAGS_1__DISCARD_27__SHIFT                   0x00000016
+#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT                  0x00000017
+#define CP_NV_FLAGS_1__DISCARD_28__SHIFT                   0x00000018
+#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT                  0x00000019
+#define CP_NV_FLAGS_1__DISCARD_29__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_1__DISCARD_30__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_1__DISCARD_31__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32__SHIFT                   0x00000000
+#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT                  0x00000001
+#define CP_NV_FLAGS_2__DISCARD_33__SHIFT                   0x00000002
+#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT                  0x00000003
+#define CP_NV_FLAGS_2__DISCARD_34__SHIFT                   0x00000004
+#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT                  0x00000005
+#define CP_NV_FLAGS_2__DISCARD_35__SHIFT                   0x00000006
+#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT                  0x00000007
+#define CP_NV_FLAGS_2__DISCARD_36__SHIFT                   0x00000008
+#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT                  0x00000009
+#define CP_NV_FLAGS_2__DISCARD_37__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_2__DISCARD_38__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_2__DISCARD_39__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_2__DISCARD_40__SHIFT                   0x00000010
+#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT                  0x00000011
+#define CP_NV_FLAGS_2__DISCARD_41__SHIFT                   0x00000012
+#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT                  0x00000013
+#define CP_NV_FLAGS_2__DISCARD_42__SHIFT                   0x00000014
+#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT                  0x00000015
+#define CP_NV_FLAGS_2__DISCARD_43__SHIFT                   0x00000016
+#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT                  0x00000017
+#define CP_NV_FLAGS_2__DISCARD_44__SHIFT                   0x00000018
+#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT                  0x00000019
+#define CP_NV_FLAGS_2__DISCARD_45__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_2__DISCARD_46__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_2__DISCARD_47__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48__SHIFT                   0x00000000
+#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT                  0x00000001
+#define CP_NV_FLAGS_3__DISCARD_49__SHIFT                   0x00000002
+#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT                  0x00000003
+#define CP_NV_FLAGS_3__DISCARD_50__SHIFT                   0x00000004
+#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT                  0x00000005
+#define CP_NV_FLAGS_3__DISCARD_51__SHIFT                   0x00000006
+#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT                  0x00000007
+#define CP_NV_FLAGS_3__DISCARD_52__SHIFT                   0x00000008
+#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT                  0x00000009
+#define CP_NV_FLAGS_3__DISCARD_53__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_3__DISCARD_54__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_3__DISCARD_55__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_3__DISCARD_56__SHIFT                   0x00000010
+#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT                  0x00000011
+#define CP_NV_FLAGS_3__DISCARD_57__SHIFT                   0x00000012
+#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT                  0x00000013
+#define CP_NV_FLAGS_3__DISCARD_58__SHIFT                   0x00000014
+#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT                  0x00000015
+#define CP_NV_FLAGS_3__DISCARD_59__SHIFT                   0x00000016
+#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT                  0x00000017
+#define CP_NV_FLAGS_3__DISCARD_60__SHIFT                   0x00000018
+#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT                  0x00000019
+#define CP_NV_FLAGS_3__DISCARD_61__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_3__DISCARD_62__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_3__DISCARD_63__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT                  0x0000001f
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT     0x00000000
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT       0x00000000
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER__SHIFT                    0x00000000
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY__SHIFT                        0x00000000
+#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT                    0x00000001
+#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT                 0x00000002
+#define CP_STAT__RBIU_BUSY__SHIFT                          0x00000003
+#define CP_STAT__RCIU_BUSY__SHIFT                          0x00000004
+#define CP_STAT__CSF_RING_BUSY__SHIFT                      0x00000005
+#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT                 0x00000006
+#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT                 0x00000007
+#define CP_STAT__CSF_ST_BUSY__SHIFT                        0x00000009
+#define CP_STAT__CSF_BUSY__SHIFT                           0x0000000a
+#define CP_STAT__RING_QUEUE_BUSY__SHIFT                    0x0000000b
+#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT               0x0000000c
+#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT               0x0000000d
+#define CP_STAT__ST_QUEUE_BUSY__SHIFT                      0x00000010
+#define CP_STAT__PFP_BUSY__SHIFT                           0x00000011
+#define CP_STAT__MEQ_RING_BUSY__SHIFT                      0x00000012
+#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT                 0x00000013
+#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT                 0x00000014
+#define CP_STAT__MIU_WC_STALL__SHIFT                       0x00000015
+#define CP_STAT__CP_NRT_BUSY__SHIFT                        0x00000016
+#define CP_STAT___3D_BUSY__SHIFT                           0x00000017
+#define CP_STAT__ME_BUSY__SHIFT                            0x0000001a
+#define CP_STAT__ME_WC_BUSY__SHIFT                         0x0000001d
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT            0x0000001e
+#define CP_STAT__CP_BUSY__SHIFT                            0x0000001f
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE__SHIFT                        0x00000000
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE__SHIFT                        0x00000000
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT         0x00000000
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT     0x00000008
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT           0x00000009
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT           0x0000000a
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT           0x0000000b
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT           0x0000000c
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT           0x0000000d
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT           0x0000000e
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT           0x0000000f
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT           0x00000010
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA__SHIFT         0x00000011
+#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT             0x00000019
+#define COHER_STATUS_PM4__STATUS__SHIFT                    0x0000001f
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE__SHIFT                       0x00000000
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE__SHIFT                       0x00000000
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT        0x00000000
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT    0x00000008
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT          0x00000009
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT          0x0000000a
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT          0x0000000b
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT          0x0000000c
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT          0x0000000d
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT          0x0000000e
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT          0x0000000f
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT          0x00000010
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA__SHIFT        0x00000011
+#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT            0x00000019
+#define COHER_STATUS_HOST__STATUS__SHIFT                   0x0000001f
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT              0x0000000c
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT              0x00000000
+#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT               0x0000000e
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT                 0x00000000
+#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT             0x00000004
+#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT                 0x00000006
+#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT                 0x00000007
+#define RB_COLOR_INFO__COLOR_SWAP__SHIFT                   0x00000009
+#define RB_COLOR_INFO__COLOR_BASE__SHIFT                   0x0000000c
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT                 0x00000000
+#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT                   0x0000000c
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF__SHIFT               0x00000000
+#define RB_STENCILREFMASK__STENCILMASK__SHIFT              0x00000008
+#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT         0x00000010
+#define RB_STENCILREFMASK__RESERVED0__SHIFT                0x00000018
+#define RB_STENCILREFMASK__RESERVED1__SHIFT                0x00000019
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF__SHIFT                     0x00000000
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED__SHIFT                    0x00000000
+#define RB_COLOR_MASK__WRITE_GREEN__SHIFT                  0x00000001
+#define RB_COLOR_MASK__WRITE_BLUE__SHIFT                   0x00000002
+#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT                  0x00000003
+#define RB_COLOR_MASK__RESERVED2__SHIFT                    0x00000004
+#define RB_COLOR_MASK__RESERVED3__SHIFT                    0x00000005
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED__SHIFT                     0x00000000
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT                 0x00000000
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT                   0x00000000
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT                 0x00000000
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED__SHIFT                       0x00000000
+#define RB_FOG_COLOR__FOG_GREEN__SHIFT                     0x00000008
+#define RB_FOG_COLOR__FOG_BLUE__SHIFT                      0x00000010
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT         0x00000000
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT        0x00000008
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT   0x00000010
+#define RB_STENCILREFMASK_BF__RESERVED4__SHIFT             0x00000018
+#define RB_STENCILREFMASK_BF__RESERVED5__SHIFT             0x00000019
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT             0x00000000
+#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT                   0x00000001
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT             0x00000002
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT             0x00000003
+#define RB_DEPTHCONTROL__ZFUNC__SHIFT                      0x00000004
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT            0x00000007
+#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT                0x00000008
+#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT                0x0000000b
+#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT               0x0000000e
+#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT               0x00000011
+#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT             0x00000014
+#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT             0x00000017
+#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT            0x0000001a
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT            0x0000001d
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT             0x00000000
+#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT             0x00000005
+#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT            0x00000008
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT             0x00000010
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT             0x00000015
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT            0x00000018
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT         0x0000001d
+#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT                0x0000001e
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT                 0x00000000
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT          0x00000003
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT       0x00000004
+#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT              0x00000005
+#define RB_COLORCONTROL__FOG_ENABLE__SHIFT                 0x00000006
+#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT             0x00000007
+#define RB_COLORCONTROL__ROP_CODE__SHIFT                   0x00000008
+#define RB_COLORCONTROL__DITHER_MODE__SHIFT                0x0000000c
+#define RB_COLORCONTROL__DITHER_TYPE__SHIFT                0x0000000e
+#define RB_COLORCONTROL__PIXEL_FOG__SHIFT                  0x00000010
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT      0x00000018
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT      0x0000001a
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT      0x0000001c
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT      0x0000001e
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE__SHIFT                  0x00000000
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT         0x00000000
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT         0x00000000
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT         0x00000003
+#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT                 0x00000004
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT           0x0000000c
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT         0x00000000
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT         0x00000000
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT         0x00000003
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT         0x00000004
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT           0x00000008
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT    0x0000000a
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT    0x0000000c
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT      0x0000000e
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT    0x0000000f
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT     0x00000010
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT    0x00000011
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT         0x00000000
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT         0x0000000d
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT                 0x00000000
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT     0x00000000
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT      0x00000001
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT     0x00000000
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT     0x00000000
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT         0x00000001
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT            0x00000003
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT    0x00000005
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT    0x00000006
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT           0x00000007
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT            0x00000008
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT            0x0000000e
+#define RB_BC_CONTROL__CRC_MODE__SHIFT                     0x0000000f
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT      0x00000010
+#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT                0x00000011
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT             0x00000012
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT    0x00000016
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT        0x00000017
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT    0x0000001b
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d
+#define RB_BC_CONTROL__CRC_SYSTEM__SHIFT                   0x0000001e
+#define RB_BC_CONTROL__RESERVED6__SHIFT                    0x0000001f
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT                   0x00000000
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT           0x00000004
+#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT                  0x0000000e
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA__SHIFT                    0x00000000
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT              0x00000000
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK__SHIFT                       0x00000000
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT             0x00000000
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT             0x00000000
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT           0x00000000
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT           0x00000001
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT           0x00000002
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT           0x00000003
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT          0x00000004
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT          0x00000005
+#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT                   0x00000006
+#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT                   0x00000007
+#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT                   0x00000008
+#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT                   0x00000009
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT          0x0000000a
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT          0x0000000b
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT          0x0000000c
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT          0x0000000d
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT              0x0000000e
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT                   0x00000010
+#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT                   0x00000011
+#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT                   0x00000012
+#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT                   0x00000013
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT            0x00000014
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT            0x00000015
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT            0x00000016
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT            0x00000017
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT         0x00000018
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT         0x00000019
+#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT                   0x0000001a
+#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT                   0x0000001b
+#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT                  0x0000001c
+#define RB_DEBUG_0__C_REQ_FULL__SHIFT                      0x0000001d
+#define RB_DEBUG_0__C_MASK_FULL__SHIFT                     0x0000001e
+#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT                 0x0000001f
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT              0x00000000
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT              0x00000001
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT              0x00000002
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT              0x00000003
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT         0x00000004
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT         0x00000005
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT                  0x00000006
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT                  0x00000007
+#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT                  0x00000008
+#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT                  0x00000009
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT         0x0000000a
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT         0x0000000b
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT         0x0000000c
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT         0x0000000d
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT             0x0000000e
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT             0x0000000f
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT                  0x00000010
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT                  0x00000011
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT              0x00000012
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT              0x00000013
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT           0x00000014
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT           0x00000017
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT        0x00000018
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT        0x00000019
+#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT                  0x0000001a
+#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT                  0x0000001b
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT                 0x0000001c
+#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT                     0x0000001d
+#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT                0x0000001f
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT                 0x00000000
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT               0x00000004
+#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT                 0x0000000b
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT               0x0000000c
+#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT              0x0000000d
+#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT                 0x0000000e
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT              0x00000010
+#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT                    0x00000011
+#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT                    0x00000012
+#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT                     0x00000013
+#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT                     0x00000014
+#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT                     0x00000015
+#define RB_DEBUG_2__Z_TILE_FULL__SHIFT                     0x00000016
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT                0x00000017
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT             0x00000018
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT             0x00000019
+#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT                   0x0000001a
+#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT                   0x0000001b
+#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT                    0x0000001c
+#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT                    0x0000001d
+#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT                    0x0000001f
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID__SHIFT                     0x00000000
+#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT                  0x00000004
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT         0x00000008
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT           0x0000000e
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT             0x0000000f
+#define RB_DEBUG_3__SHD_FULL__SHIFT                        0x00000013
+#define RB_DEBUG_3__SHD_EMPTY__SHIFT                       0x00000014
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT            0x00000017
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT            0x00000018
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT                0x00000019
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT                0x0000001a
+#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT                 0x0000001b
+#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT                 0x0000001c
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT             0x00000000
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT             0x00000001
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT           0x00000002
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT           0x00000003
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT           0x00000004
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT          0x00000005
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT            0x00000006
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT           0x00000007
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT     0x00000008
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT             0x00000009
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT           0x00000000
+
+// RB_BC_SPARES
+#define RB_BC_SPARES__RESERVED__SHIFT                      0x00000000
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT   0x00000009
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h
new file mode 100644
index 000000000000..78d4924ef79d
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h
@@ -0,0 +1,52583 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_CP_FIDDLE_H)
+#define _CP_FIDDLE_H
+
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * CP_RB_BASE struct
+ */
+
+#define CP_RB_BASE_RB_BASE_SIZE        27
+
+#define CP_RB_BASE_RB_BASE_SHIFT       5
+
+#define CP_RB_BASE_RB_BASE_MASK        0xffffffe0
+
+#define CP_RB_BASE_MASK \
+     (CP_RB_BASE_RB_BASE_MASK)
+
+#define CP_RB_BASE(rb_base) \
+     ((rb_base << CP_RB_BASE_RB_BASE_SHIFT))
+
+#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \
+     ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT)
+
+#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \
+     cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int                                : 5;
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+     } cp_rb_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+          unsigned int                                : 5;
+     } cp_rb_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_base_t f;
+} cp_rb_base_u;
+
+
+/*
+ * CP_RB_CNTL struct
+ */
+
+#define CP_RB_CNTL_RB_BUFSZ_SIZE       6
+#define CP_RB_CNTL_RB_BLKSZ_SIZE       6
+#define CP_RB_CNTL_BUF_SWAP_SIZE       2
+#define CP_RB_CNTL_RB_POLL_EN_SIZE     1
+#define CP_RB_CNTL_RB_NO_UPDATE_SIZE   1
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1
+
+#define CP_RB_CNTL_RB_BUFSZ_SHIFT      0
+#define CP_RB_CNTL_RB_BLKSZ_SHIFT      8
+#define CP_RB_CNTL_BUF_SWAP_SHIFT      16
+#define CP_RB_CNTL_RB_POLL_EN_SHIFT    20
+#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT  27
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31
+
+#define CP_RB_CNTL_RB_BUFSZ_MASK       0x0000003f
+#define CP_RB_CNTL_RB_BLKSZ_MASK       0x00003f00
+#define CP_RB_CNTL_BUF_SWAP_MASK       0x00030000
+#define CP_RB_CNTL_RB_POLL_EN_MASK     0x00100000
+#define CP_RB_CNTL_RB_NO_UPDATE_MASK   0x08000000
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000
+
+#define CP_RB_CNTL_MASK \
+     (CP_RB_CNTL_RB_BUFSZ_MASK | \
+      CP_RB_CNTL_RB_BLKSZ_MASK | \
+      CP_RB_CNTL_BUF_SWAP_MASK | \
+      CP_RB_CNTL_RB_POLL_EN_MASK | \
+      CP_RB_CNTL_RB_NO_UPDATE_MASK | \
+      CP_RB_CNTL_RB_RPTR_WR_ENA_MASK)
+
+#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \
+     ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \
+      (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \
+      (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \
+      (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \
+      (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \
+      (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT))
+
+#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+     } cp_rb_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+     } cp_rb_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_cntl_t f;
+} cp_rb_cntl_u;
+
+
+/*
+ * CP_RB_RPTR_ADDR struct
+ */
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc
+
+#define CP_RB_RPTR_ADDR_MASK \
+     (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \
+      CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK)
+
+#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \
+     ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \
+      (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT))
+
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_addr_t f;
+} cp_rb_rptr_addr_u;
+
+
+/*
+ * CP_RB_RPTR struct
+ */
+
+#define CP_RB_RPTR_RB_RPTR_SIZE        20
+
+#define CP_RB_RPTR_RB_RPTR_SHIFT       0
+
+#define CP_RB_RPTR_RB_RPTR_MASK        0x000fffff
+
+#define CP_RB_RPTR_MASK \
+     (CP_RB_RPTR_RB_RPTR_MASK)
+
+#define CP_RB_RPTR(rb_rptr) \
+     ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT))
+
+#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \
+     ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \
+     cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+     } cp_rb_rptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_t f;
+} cp_rb_rptr_u;
+
+
+/*
+ * CP_RB_RPTR_WR struct
+ */
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE  20
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK  0x000fffff
+
+#define CP_RB_RPTR_WR_MASK \
+     (CP_RB_RPTR_WR_RB_RPTR_WR_MASK)
+
+#define CP_RB_RPTR_WR(rb_rptr_wr) \
+     ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT))
+
+#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \
+     ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \
+     cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_wr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+     } cp_rb_rptr_wr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_wr_t f;
+} cp_rb_rptr_wr_u;
+
+
+/*
+ * CP_RB_WPTR struct
+ */
+
+#define CP_RB_WPTR_RB_WPTR_SIZE        20
+
+#define CP_RB_WPTR_RB_WPTR_SHIFT       0
+
+#define CP_RB_WPTR_RB_WPTR_MASK        0x000fffff
+
+#define CP_RB_WPTR_MASK \
+     (CP_RB_WPTR_RB_WPTR_MASK)
+
+#define CP_RB_WPTR(rb_wptr) \
+     ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT))
+
+#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \
+     ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \
+     cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_wptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+     } cp_rb_wptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_t f;
+} cp_rb_wptr_u;
+
+
+/*
+ * CP_RB_WPTR_DELAY struct
+ */
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000
+
+#define CP_RB_WPTR_DELAY_MASK \
+     (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \
+      CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK)
+
+#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \
+     ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \
+      (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT))
+
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_delay_t f;
+} cp_rb_wptr_delay_u;
+
+
+/*
+ * CP_RB_WPTR_BASE struct
+ */
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc
+
+#define CP_RB_WPTR_BASE_MASK \
+     (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \
+      CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK)
+
+#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \
+     ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \
+      (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT))
+
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+     } cp_rb_wptr_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+     } cp_rb_wptr_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_base_t f;
+} cp_rb_wptr_base_u;
+
+
+/*
+ * CP_IB1_BASE struct
+ */
+
+#define CP_IB1_BASE_IB1_BASE_SIZE      30
+
+#define CP_IB1_BASE_IB1_BASE_SHIFT     2
+
+#define CP_IB1_BASE_IB1_BASE_MASK      0xfffffffc
+
+#define CP_IB1_BASE_MASK \
+     (CP_IB1_BASE_IB1_BASE_MASK)
+
+#define CP_IB1_BASE(ib1_base) \
+     ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT))
+
+#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \
+     ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \
+     cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int                                : 2;
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+     } cp_ib1_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib1_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_base_t f;
+} cp_ib1_base_u;
+
+
+/*
+ * CP_IB1_BUFSZ struct
+ */
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE    20
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT   0
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK    0x000fffff
+
+#define CP_IB1_BUFSZ_MASK \
+     (CP_IB1_BUFSZ_IB1_BUFSZ_MASK)
+
+#define CP_IB1_BUFSZ(ib1_bufsz) \
+     ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT))
+
+#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \
+     ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \
+     cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib1_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+     } cp_ib1_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_bufsz_t f;
+} cp_ib1_bufsz_u;
+
+
+/*
+ * CP_IB2_BASE struct
+ */
+
+#define CP_IB2_BASE_IB2_BASE_SIZE      30
+
+#define CP_IB2_BASE_IB2_BASE_SHIFT     2
+
+#define CP_IB2_BASE_IB2_BASE_MASK      0xfffffffc
+
+#define CP_IB2_BASE_MASK \
+     (CP_IB2_BASE_IB2_BASE_MASK)
+
+#define CP_IB2_BASE(ib2_base) \
+     ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT))
+
+#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \
+     ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \
+     cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int                                : 2;
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+     } cp_ib2_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib2_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_base_t f;
+} cp_ib2_base_u;
+
+
+/*
+ * CP_IB2_BUFSZ struct
+ */
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE    20
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT   0
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK    0x000fffff
+
+#define CP_IB2_BUFSZ_MASK \
+     (CP_IB2_BUFSZ_IB2_BUFSZ_MASK)
+
+#define CP_IB2_BUFSZ(ib2_bufsz) \
+     ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT))
+
+#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \
+     ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \
+     cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib2_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+     } cp_ib2_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_bufsz_t f;
+} cp_ib2_bufsz_u;
+
+
+/*
+ * CP_ST_BASE struct
+ */
+
+#define CP_ST_BASE_ST_BASE_SIZE        30
+
+#define CP_ST_BASE_ST_BASE_SHIFT       2
+
+#define CP_ST_BASE_ST_BASE_MASK        0xfffffffc
+
+#define CP_ST_BASE_MASK \
+     (CP_ST_BASE_ST_BASE_MASK)
+
+#define CP_ST_BASE(st_base) \
+     ((st_base << CP_ST_BASE_ST_BASE_SHIFT))
+
+#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \
+     ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT)
+
+#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \
+     cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int                                : 2;
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+     } cp_st_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_st_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_base_t f;
+} cp_st_base_u;
+
+
+/*
+ * CP_ST_BUFSZ struct
+ */
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SIZE      20
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT     0
+
+#define CP_ST_BUFSZ_ST_BUFSZ_MASK      0x000fffff
+
+#define CP_ST_BUFSZ_MASK \
+     (CP_ST_BUFSZ_ST_BUFSZ_MASK)
+
+#define CP_ST_BUFSZ(st_bufsz) \
+     ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT))
+
+#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \
+     ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \
+     cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_st_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+     } cp_st_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_bufsz_t f;
+} cp_st_bufsz_u;
+
+
+/*
+ * CP_QUEUE_THRESHOLDS struct
+ */
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000
+
+#define CP_QUEUE_THRESHOLDS_MASK \
+     (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK)
+
+#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \
+     ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \
+      (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \
+      (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT))
+
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 12;
+     } cp_queue_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int                                : 12;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+     } cp_queue_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_queue_thresholds_t f;
+} cp_queue_thresholds_u;
+
+
+/*
+ * CP_MEQ_THRESHOLDS struct
+ */
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5
+#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16
+#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000
+#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000
+
+#define CP_MEQ_THRESHOLDS_MASK \
+     (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \
+      CP_MEQ_THRESHOLDS_ROQ_END_MASK)
+
+#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \
+     ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \
+      (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT))
+
+#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 16;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+     } cp_meq_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 16;
+     } cp_meq_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_thresholds_t f;
+} cp_meq_thresholds_u;
+
+
+/*
+ * CP_CSQ_AVAIL struct
+ */
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE  7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE  7
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK  0x00007f00
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK  0x007f0000
+
+#define CP_CSQ_AVAIL_MASK \
+     (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK)
+
+#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \
+     ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \
+      (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \
+      (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT))
+
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int                                : 9;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+     } cp_csq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_avail_t f;
+} cp_csq_avail_u;
+
+
+/*
+ * CP_STQ_AVAIL struct
+ */
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE   7
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT  0
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_MASK   0x0000007f
+
+#define CP_STQ_AVAIL_MASK \
+     (CP_STQ_AVAIL_STQ_CNT_ST_MASK)
+
+#define CP_STQ_AVAIL(stq_cnt_st) \
+     ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT))
+
+#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \
+     ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \
+     cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+          unsigned int                                : 25;
+     } cp_stq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int                                : 25;
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+     } cp_stq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_avail_t f;
+} cp_stq_avail_u;
+
+
+/*
+ * CP_MEQ_AVAIL struct
+ */
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SIZE      5
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT     0
+
+#define CP_MEQ_AVAIL_MEQ_CNT_MASK      0x0000001f
+
+#define CP_MEQ_AVAIL_MASK \
+     (CP_MEQ_AVAIL_MEQ_CNT_MASK)
+
+#define CP_MEQ_AVAIL(meq_cnt) \
+     ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT))
+
+#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \
+     ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \
+     cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+          unsigned int                                : 27;
+     } cp_meq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int                                : 27;
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+     } cp_meq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_avail_t f;
+} cp_meq_avail_u;
+
+
+/*
+ * CP_CSQ_RB_STAT struct
+ */
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000
+
+#define CP_CSQ_RB_STAT_MASK \
+     (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \
+      CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK)
+
+#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \
+     ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \
+      (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT))
+
+#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_rb_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+     } cp_csq_rb_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_rb_stat_t f;
+} cp_csq_rb_stat_u;
+
+
+/*
+ * CP_CSQ_IB1_STAT struct
+ */
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000
+
+#define CP_CSQ_IB1_STAT_MASK \
+     (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \
+      CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK)
+
+#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \
+     ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \
+      (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT))
+
+#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib1_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+     } cp_csq_ib1_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib1_stat_t f;
+} cp_csq_ib1_stat_u;
+
+
+/*
+ * CP_CSQ_IB2_STAT struct
+ */
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000
+
+#define CP_CSQ_IB2_STAT_MASK \
+     (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \
+      CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK)
+
+#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \
+     ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \
+      (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT))
+
+#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib2_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+     } cp_csq_ib2_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib2_stat_t f;
+} cp_csq_ib2_stat_u;
+
+
+/*
+ * CP_NON_PREFETCH_CNTRS struct
+ */
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700
+
+#define CP_NON_PREFETCH_CNTRS_MASK \
+     (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \
+      CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK)
+
+#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \
+     ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \
+      (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT))
+
+#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 21;
+     } cp_non_prefetch_cntrs_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int                                : 21;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+     } cp_non_prefetch_cntrs_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_non_prefetch_cntrs_t f;
+} cp_non_prefetch_cntrs_u;
+
+
+/*
+ * CP_STQ_ST_STAT struct
+ */
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000
+
+#define CP_STQ_ST_STAT_MASK \
+     (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \
+      CP_STQ_ST_STAT_STQ_WPTR_ST_MASK)
+
+#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \
+     ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \
+      (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT))
+
+#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+     } cp_stq_st_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+     } cp_stq_st_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_st_stat_t f;
+} cp_stq_st_stat_u;
+
+
+/*
+ * CP_MEQ_STAT struct
+ */
+
+#define CP_MEQ_STAT_MEQ_RPTR_SIZE      10
+#define CP_MEQ_STAT_MEQ_WPTR_SIZE      10
+
+#define CP_MEQ_STAT_MEQ_RPTR_SHIFT     0
+#define CP_MEQ_STAT_MEQ_WPTR_SHIFT     16
+
+#define CP_MEQ_STAT_MEQ_RPTR_MASK      0x000003ff
+#define CP_MEQ_STAT_MEQ_WPTR_MASK      0x03ff0000
+
+#define CP_MEQ_STAT_MASK \
+     (CP_MEQ_STAT_MEQ_RPTR_MASK | \
+      CP_MEQ_STAT_MEQ_WPTR_MASK)
+
+#define CP_MEQ_STAT(meq_rptr, meq_wptr) \
+     ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \
+      (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT))
+
+#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+     } cp_meq_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+     } cp_meq_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_stat_t f;
+} cp_meq_stat_u;
+
+
+/*
+ * CP_MIU_TAG_STAT struct
+ */
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001
+#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002
+#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004
+#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008
+#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010
+#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020
+#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040
+#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080
+#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100
+#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200
+#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400
+#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800
+#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000
+#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000
+#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000
+#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000
+#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000
+#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000
+
+#define CP_MIU_TAG_STAT_MASK \
+     (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \
+      CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK)
+
+#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \
+     ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \
+      (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \
+      (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \
+      (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \
+      (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \
+      (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \
+      (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \
+      (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \
+      (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \
+      (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \
+      (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \
+      (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \
+      (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \
+      (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \
+      (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \
+      (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \
+      (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \
+      (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \
+      (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT))
+
+#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int                                : 13;
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+     } cp_miu_tag_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+          unsigned int                                : 13;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+     } cp_miu_tag_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_miu_tag_stat_t f;
+} cp_miu_tag_stat_u;
+
+
+/*
+ * CP_CMD_INDEX struct
+ */
+
+#define CP_CMD_INDEX_CMD_INDEX_SIZE    7
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2
+
+#define CP_CMD_INDEX_CMD_INDEX_SHIFT   0
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16
+
+#define CP_CMD_INDEX_CMD_INDEX_MASK    0x0000007f
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000
+
+#define CP_CMD_INDEX_MASK \
+     (CP_CMD_INDEX_CMD_INDEX_MASK | \
+      CP_CMD_INDEX_CMD_QUEUE_SEL_MASK)
+
+#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \
+     ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \
+      (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT))
+
+#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 14;
+     } cp_cmd_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int                                : 14;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+     } cp_cmd_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_index_t f;
+} cp_cmd_index_u;
+
+
+/*
+ * CP_CMD_DATA struct
+ */
+
+#define CP_CMD_DATA_CMD_DATA_SIZE      32
+
+#define CP_CMD_DATA_CMD_DATA_SHIFT     0
+
+#define CP_CMD_DATA_CMD_DATA_MASK      0xffffffff
+
+#define CP_CMD_DATA_MASK \
+     (CP_CMD_DATA_CMD_DATA_MASK)
+
+#define CP_CMD_DATA(cmd_data) \
+     ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT))
+
+#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \
+     ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \
+     cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_data_t f;
+} cp_cmd_data_u;
+
+
+/*
+ * CP_ME_CNTL struct
+ */
+
+#define CP_ME_CNTL_ME_STATMUX_SIZE     16
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_ME_HALT_SIZE        1
+#define CP_ME_CNTL_ME_BUSY_SIZE        1
+#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE  1
+
+#define CP_ME_CNTL_ME_STATMUX_SHIFT    0
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26
+#define CP_ME_CNTL_ME_HALT_SHIFT       28
+#define CP_ME_CNTL_ME_BUSY_SHIFT       29
+#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31
+
+#define CP_ME_CNTL_ME_STATMUX_MASK     0x0000ffff
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000
+#define CP_ME_CNTL_ME_HALT_MASK        0x10000000
+#define CP_ME_CNTL_ME_BUSY_MASK        0x20000000
+#define CP_ME_CNTL_PROG_CNT_SIZE_MASK  0x80000000
+
+#define CP_ME_CNTL_MASK \
+     (CP_ME_CNTL_ME_STATMUX_MASK | \
+      CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_ME_HALT_MASK | \
+      CP_ME_CNTL_ME_BUSY_MASK | \
+      CP_ME_CNTL_PROG_CNT_SIZE_MASK)
+
+#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \
+     ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \
+      (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \
+      (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \
+      (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT))
+
+#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+          unsigned int                                : 9;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+     } cp_me_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 9;
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+     } cp_me_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cntl_t f;
+} cp_me_cntl_u;
+
+
+/*
+ * CP_ME_STATUS struct
+ */
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_ME_STATUS_MASK \
+     (CP_ME_STATUS_ME_DEBUG_DATA_MASK)
+
+#define CP_ME_STATUS(me_debug_data) \
+     ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT))
+
+#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \
+     ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \
+     cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_status_t f;
+} cp_me_status_u;
+
+
+/*
+ * CP_ME_RAM_WADDR struct
+ */
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_WADDR_MASK \
+     (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK)
+
+#define CP_ME_RAM_WADDR(me_ram_waddr) \
+     ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT))
+
+#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \
+     ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \
+     cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_waddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+     } cp_me_ram_waddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_waddr_t f;
+} cp_me_ram_waddr_u;
+
+
+/*
+ * CP_ME_RAM_RADDR struct
+ */
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_RADDR_MASK \
+     (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK)
+
+#define CP_ME_RAM_RADDR(me_ram_raddr) \
+     ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT))
+
+#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \
+     ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \
+     cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_raddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+     } cp_me_ram_raddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_raddr_t f;
+} cp_me_ram_raddr_u;
+
+
+/*
+ * CP_ME_RAM_DATA struct
+ */
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff
+
+#define CP_ME_RAM_DATA_MASK \
+     (CP_ME_RAM_DATA_ME_RAM_DATA_MASK)
+
+#define CP_ME_RAM_DATA(me_ram_data) \
+     ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT))
+
+#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \
+     ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \
+     cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_data_t f;
+} cp_me_ram_data_u;
+
+
+/*
+ * CP_ME_RDADDR struct
+ */
+
+#define CP_ME_RDADDR_ME_RDADDR_SIZE    32
+
+#define CP_ME_RDADDR_ME_RDADDR_SHIFT   0
+
+#define CP_ME_RDADDR_ME_RDADDR_MASK    0xffffffff
+
+#define CP_ME_RDADDR_MASK \
+     (CP_ME_RDADDR_ME_RDADDR_MASK)
+
+#define CP_ME_RDADDR(me_rdaddr) \
+     ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT))
+
+#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \
+     ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \
+     cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_rdaddr_t f;
+} cp_me_rdaddr_u;
+
+
+/*
+ * CP_DEBUG struct
+ */
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23
+#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0
+#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff
+#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000
+#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000
+#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000
+
+#define CP_DEBUG_MASK \
+     (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \
+      CP_DEBUG_PREDICATE_DISABLE_MASK | \
+      CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \
+      CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \
+      CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \
+      CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \
+      CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \
+      CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \
+      CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK)
+
+#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \
+     ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \
+      (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \
+      (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \
+      (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \
+      (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \
+      (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \
+      (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \
+      (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \
+      (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT))
+
+#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \
+     ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \
+     ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+     } cp_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+     } cp_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_debug_t f;
+} cp_debug_u;
+
+
+/*
+ * SCRATCH_REG0 struct
+ */
+
+#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32
+
+#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0
+
+#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff
+
+#define SCRATCH_REG0_MASK \
+     (SCRATCH_REG0_SCRATCH_REG0_MASK)
+
+#define SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT))
+
+#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \
+     scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg0_t f;
+} scratch_reg0_u;
+
+
+/*
+ * SCRATCH_REG1 struct
+ */
+
+#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32
+
+#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0
+
+#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff
+
+#define SCRATCH_REG1_MASK \
+     (SCRATCH_REG1_SCRATCH_REG1_MASK)
+
+#define SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT))
+
+#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \
+     scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg1_t f;
+} scratch_reg1_u;
+
+
+/*
+ * SCRATCH_REG2 struct
+ */
+
+#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32
+
+#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0
+
+#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff
+
+#define SCRATCH_REG2_MASK \
+     (SCRATCH_REG2_SCRATCH_REG2_MASK)
+
+#define SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT))
+
+#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \
+     scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg2_t f;
+} scratch_reg2_u;
+
+
+/*
+ * SCRATCH_REG3 struct
+ */
+
+#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32
+
+#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0
+
+#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff
+
+#define SCRATCH_REG3_MASK \
+     (SCRATCH_REG3_SCRATCH_REG3_MASK)
+
+#define SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT))
+
+#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \
+     scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg3_t f;
+} scratch_reg3_u;
+
+
+/*
+ * SCRATCH_REG4 struct
+ */
+
+#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32
+
+#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0
+
+#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff
+
+#define SCRATCH_REG4_MASK \
+     (SCRATCH_REG4_SCRATCH_REG4_MASK)
+
+#define SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT))
+
+#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \
+     scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg4_t f;
+} scratch_reg4_u;
+
+
+/*
+ * SCRATCH_REG5 struct
+ */
+
+#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32
+
+#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0
+
+#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff
+
+#define SCRATCH_REG5_MASK \
+     (SCRATCH_REG5_SCRATCH_REG5_MASK)
+
+#define SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT))
+
+#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \
+     scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg5_t f;
+} scratch_reg5_u;
+
+
+/*
+ * SCRATCH_REG6 struct
+ */
+
+#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32
+
+#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0
+
+#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff
+
+#define SCRATCH_REG6_MASK \
+     (SCRATCH_REG6_SCRATCH_REG6_MASK)
+
+#define SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT))
+
+#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \
+     scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg6_t f;
+} scratch_reg6_u;
+
+
+/*
+ * SCRATCH_REG7 struct
+ */
+
+#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32
+
+#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0
+
+#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff
+
+#define SCRATCH_REG7_MASK \
+     (SCRATCH_REG7_SCRATCH_REG7_MASK)
+
+#define SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT))
+
+#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \
+     scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg7_t f;
+} scratch_reg7_u;
+
+
+/*
+ * SCRATCH_UMSK struct
+ */
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8
+#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0
+#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff
+#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000
+
+#define SCRATCH_UMSK_MASK \
+     (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \
+      SCRATCH_UMSK_SCRATCH_SWAP_MASK)
+
+#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \
+     ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \
+      (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT))
+
+#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 14;
+     } scratch_umsk_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int                                : 14;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+     } scratch_umsk_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_umsk_t f;
+} scratch_umsk_u;
+
+
+/*
+ * SCRATCH_ADDR struct
+ */
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0
+
+#define SCRATCH_ADDR_MASK \
+     (SCRATCH_ADDR_SCRATCH_ADDR_MASK)
+
+#define SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT))
+
+#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \
+     scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int                                : 5;
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+     } scratch_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+          unsigned int                                : 5;
+     } scratch_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_addr_t f;
+} scratch_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_SRC struct
+ */
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_VS_EVENT_SRC_MASK \
+     (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \
+      CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK)
+
+#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \
+     ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \
+      (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_vs_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int                                : 30;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+     } cp_me_vs_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_src_t f;
+} cp_me_vs_event_src_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_MASK \
+     (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \
+      CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK)
+
+#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \
+     ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \
+      (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_t f;
+} cp_me_vs_event_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_MASK \
+     (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK)
+
+#define CP_ME_VS_EVENT_DATA(vs_done_data) \
+     ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \
+     ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \
+     cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_t f;
+} cp_me_vs_event_data_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \
+      CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \
+     ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \
+      (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_swm_t f;
+} cp_me_vs_event_addr_swm_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_SWM_MASK \
+     (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \
+     ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \
+     ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \
+     cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_swm_t f;
+} cp_me_vs_event_data_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_SRC struct
+ */
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_PS_EVENT_SRC_MASK \
+     (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \
+      CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK)
+
+#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \
+     ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \
+      (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT))
+
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_ps_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int                                : 30;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+     } cp_me_ps_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_src_t f;
+} cp_me_ps_event_src_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_MASK \
+     (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \
+      CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK)
+
+#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \
+     ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \
+      (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_t f;
+} cp_me_ps_event_addr_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_MASK \
+     (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK)
+
+#define CP_ME_PS_EVENT_DATA(ps_done_data) \
+     ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \
+     ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \
+     cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_t f;
+} cp_me_ps_event_data_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \
+      CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \
+     ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \
+      (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_swm_t f;
+} cp_me_ps_event_addr_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_SWM_MASK \
+     (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \
+     ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \
+     ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \
+     cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_swm_t f;
+} cp_me_ps_event_data_swm_u;
+
+
+/*
+ * CP_ME_CF_EVENT_SRC struct
+ */
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001
+
+#define CP_ME_CF_EVENT_SRC_MASK \
+     (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK)
+
+#define CP_ME_CF_EVENT_SRC(cf_done_src) \
+     ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT))
+
+#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \
+     ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \
+     cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+          unsigned int                                : 31;
+     } cp_me_cf_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int                                : 31;
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+     } cp_me_cf_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_src_t f;
+} cp_me_cf_event_src_u;
+
+
+/*
+ * CP_ME_CF_EVENT_ADDR struct
+ */
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_CF_EVENT_ADDR_MASK \
+     (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \
+      CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK)
+
+#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \
+     ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \
+      (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT))
+
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_addr_t f;
+} cp_me_cf_event_addr_u;
+
+
+/*
+ * CP_ME_CF_EVENT_DATA struct
+ */
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_CF_EVENT_DATA_MASK \
+     (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK)
+
+#define CP_ME_CF_EVENT_DATA(cf_done_data) \
+     ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT))
+
+#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \
+     ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \
+     cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_data_t f;
+} cp_me_cf_event_data_u;
+
+
+/*
+ * CP_ME_NRT_ADDR struct
+ */
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_NRT_ADDR_MASK \
+     (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \
+      CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK)
+
+#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \
+     ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \
+      (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT))
+
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+     } cp_me_nrt_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+     } cp_me_nrt_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_addr_t f;
+} cp_me_nrt_addr_u;
+
+
+/*
+ * CP_ME_NRT_DATA struct
+ */
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff
+
+#define CP_ME_NRT_DATA_MASK \
+     (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK)
+
+#define CP_ME_NRT_DATA(nrt_write_data) \
+     ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT))
+
+#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \
+     ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \
+     cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_data_t f;
+} cp_me_nrt_data_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_SRC struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001
+
+#define CP_ME_VS_FETCH_DONE_SRC_MASK \
+     (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \
+     ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \
+     ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \
+     cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+          unsigned int                                : 31;
+     } cp_me_vs_fetch_done_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int                                : 31;
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+     } cp_me_vs_fetch_done_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_src_t f;
+} cp_me_vs_fetch_done_src_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_ADDR struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_FETCH_DONE_ADDR_MASK \
+     (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \
+      CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \
+     ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \
+      (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_addr_t f;
+} cp_me_vs_fetch_done_addr_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_DATA struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_FETCH_DONE_DATA_MASK \
+     (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK)
+
+#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \
+     ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \
+     ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \
+     cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_data_t f;
+} cp_me_vs_fetch_done_data_u;
+
+
+/*
+ * CP_INT_CNTL struct
+ */
+
+#define CP_INT_CNTL_SW_INT_MASK_SIZE   1
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB2_INT_MASK_SIZE  1
+#define CP_INT_CNTL_IB1_INT_MASK_SIZE  1
+#define CP_INT_CNTL_RB_INT_MASK_SIZE   1
+
+#define CP_INT_CNTL_SW_INT_MASK_SHIFT  19
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26
+#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27
+#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29
+#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30
+#define CP_INT_CNTL_RB_INT_MASK_SHIFT  31
+
+#define CP_INT_CNTL_SW_INT_MASK_MASK   0x00080000
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000
+#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000
+#define CP_INT_CNTL_IB2_INT_MASK_MASK  0x20000000
+#define CP_INT_CNTL_IB1_INT_MASK_MASK  0x40000000
+#define CP_INT_CNTL_RB_INT_MASK_MASK   0x80000000
+
+#define CP_INT_CNTL_MASK \
+     (CP_INT_CNTL_SW_INT_MASK_MASK | \
+      CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \
+      CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB2_INT_MASK_MASK | \
+      CP_INT_CNTL_IB1_INT_MASK_MASK | \
+      CP_INT_CNTL_RB_INT_MASK_MASK)
+
+#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \
+     ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \
+      (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \
+      (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \
+      (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \
+      (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \
+      (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \
+      (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \
+      (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \
+      (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT))
+
+#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+     } cp_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_cntl_t f;
+} cp_int_cntl_u;
+
+
+/*
+ * CP_INT_STATUS struct
+ */
+
+#define CP_INT_STATUS_SW_INT_STAT_SIZE 1
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1
+#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1
+#define CP_INT_STATUS_RB_INT_STAT_SIZE 1
+
+#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26
+#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27
+#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29
+#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30
+#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31
+
+#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000
+#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000
+#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000
+
+#define CP_INT_STATUS_MASK \
+     (CP_INT_STATUS_SW_INT_STAT_MASK | \
+      CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \
+      CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB2_INT_STAT_MASK | \
+      CP_INT_STATUS_IB1_INT_STAT_MASK | \
+      CP_INT_STATUS_RB_INT_STAT_MASK)
+
+#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \
+     ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \
+      (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \
+      (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \
+      (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \
+      (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \
+      (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \
+      (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \
+      (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \
+      (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT))
+
+#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+     } cp_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 19;
+     } cp_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_status_t f;
+} cp_int_status_u;
+
+
+/*
+ * CP_INT_ACK struct
+ */
+
+#define CP_INT_ACK_SW_INT_ACK_SIZE     1
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_IB_ERROR_ACK_SIZE   1
+#define CP_INT_ACK_IB2_INT_ACK_SIZE    1
+#define CP_INT_ACK_IB1_INT_ACK_SIZE    1
+#define CP_INT_ACK_RB_INT_ACK_SIZE     1
+
+#define CP_INT_ACK_SW_INT_ACK_SHIFT    19
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26
+#define CP_INT_ACK_IB_ERROR_ACK_SHIFT  27
+#define CP_INT_ACK_IB2_INT_ACK_SHIFT   29
+#define CP_INT_ACK_IB1_INT_ACK_SHIFT   30
+#define CP_INT_ACK_RB_INT_ACK_SHIFT    31
+
+#define CP_INT_ACK_SW_INT_ACK_MASK     0x00080000
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000
+#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000
+#define CP_INT_ACK_IB_ERROR_ACK_MASK   0x08000000
+#define CP_INT_ACK_IB2_INT_ACK_MASK    0x20000000
+#define CP_INT_ACK_IB1_INT_ACK_MASK    0x40000000
+#define CP_INT_ACK_RB_INT_ACK_MASK     0x80000000
+
+#define CP_INT_ACK_MASK \
+     (CP_INT_ACK_SW_INT_ACK_MASK | \
+      CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \
+      CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB2_INT_ACK_MASK | \
+      CP_INT_ACK_IB1_INT_ACK_MASK | \
+      CP_INT_ACK_RB_INT_ACK_MASK)
+
+#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \
+     ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \
+      (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \
+      (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \
+      (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \
+      (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \
+      (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \
+      (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \
+      (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \
+      (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT))
+
+#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+     } cp_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_ack_t f;
+} cp_int_ack_u;
+
+
+/*
+ * CP_PFP_UCODE_ADDR struct
+ */
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff
+
+#define CP_PFP_UCODE_ADDR_MASK \
+     (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK)
+
+#define CP_PFP_UCODE_ADDR(ucode_addr) \
+     ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT))
+
+#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \
+     ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \
+     cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+          unsigned int                                : 23;
+     } cp_pfp_ucode_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int                                : 23;
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+     } cp_pfp_ucode_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_addr_t f;
+} cp_pfp_ucode_addr_u;
+
+
+/*
+ * CP_PFP_UCODE_DATA struct
+ */
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff
+
+#define CP_PFP_UCODE_DATA_MASK \
+     (CP_PFP_UCODE_DATA_UCODE_DATA_MASK)
+
+#define CP_PFP_UCODE_DATA(ucode_data) \
+     ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT))
+
+#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \
+     ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \
+     cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+          unsigned int                                : 8;
+     } cp_pfp_ucode_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int                                : 8;
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+     } cp_pfp_ucode_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_data_t f;
+} cp_pfp_ucode_data_u;
+
+
+/*
+ * CP_PERFMON_CNTL struct
+ */
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300
+
+#define CP_PERFMON_CNTL_MASK \
+     (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \
+      CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK)
+
+#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \
+     ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \
+      (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT))
+
+#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 22;
+     } cp_perfmon_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int                                : 22;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+     } cp_perfmon_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfmon_cntl_t f;
+} cp_perfmon_cntl_u;
+
+
+/*
+ * CP_PERFCOUNTER_SELECT struct
+ */
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f
+
+#define CP_PERFCOUNTER_SELECT_MASK \
+     (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK)
+
+#define CP_PERFCOUNTER_SELECT(perfcount_sel) \
+     ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT))
+
+#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \
+     ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \
+     cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+          unsigned int                                : 26;
+     } cp_perfcounter_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int                                : 26;
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+     } cp_perfcounter_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_select_t f;
+} cp_perfcounter_select_u;
+
+
+/*
+ * CP_PERFCOUNTER_LO struct
+ */
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff
+
+#define CP_PERFCOUNTER_LO_MASK \
+     (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK)
+
+#define CP_PERFCOUNTER_LO(perfcount_lo) \
+     ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT))
+
+#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \
+     ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \
+     cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_lo_t f;
+} cp_perfcounter_lo_u;
+
+
+/*
+ * CP_PERFCOUNTER_HI struct
+ */
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff
+
+#define CP_PERFCOUNTER_HI_MASK \
+     (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK)
+
+#define CP_PERFCOUNTER_HI(perfcount_hi) \
+     ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT))
+
+#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \
+     ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \
+     cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+          unsigned int                                : 16;
+     } cp_perfcounter_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+     } cp_perfcounter_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_hi_t f;
+} cp_perfcounter_hi_u;
+
+
+/*
+ * CP_BIN_MASK_LO struct
+ */
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff
+
+#define CP_BIN_MASK_LO_MASK \
+     (CP_BIN_MASK_LO_BIN_MASK_LO_MASK)
+
+#define CP_BIN_MASK_LO(bin_mask_lo) \
+     ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT))
+
+#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \
+     ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \
+     cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_lo_t f;
+} cp_bin_mask_lo_u;
+
+
+/*
+ * CP_BIN_MASK_HI struct
+ */
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff
+
+#define CP_BIN_MASK_HI_MASK \
+     (CP_BIN_MASK_HI_BIN_MASK_HI_MASK)
+
+#define CP_BIN_MASK_HI(bin_mask_hi) \
+     ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT))
+
+#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \
+     ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \
+     cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_hi_t f;
+} cp_bin_mask_hi_u;
+
+
+/*
+ * CP_BIN_SELECT_LO struct
+ */
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff
+
+#define CP_BIN_SELECT_LO_MASK \
+     (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK)
+
+#define CP_BIN_SELECT_LO(bin_select_lo) \
+     ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT))
+
+#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \
+     ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \
+     cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_lo_t f;
+} cp_bin_select_lo_u;
+
+
+/*
+ * CP_BIN_SELECT_HI struct
+ */
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff
+
+#define CP_BIN_SELECT_HI_MASK \
+     (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK)
+
+#define CP_BIN_SELECT_HI(bin_select_hi) \
+     ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT))
+
+#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \
+     ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \
+     cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_hi_t f;
+} cp_bin_select_hi_u;
+
+
+/*
+ * CP_NV_FLAGS_0 struct
+ */
+
+#define CP_NV_FLAGS_0_DISCARD_0_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_0_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_1_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_1_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_2_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_2_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_3_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_3_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_4_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_4_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_5_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_5_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_6_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_6_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_7_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_7_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_8_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_8_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_9_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_9_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_10_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_11_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_12_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_13_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_14_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_15_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1
+
+#define CP_NV_FLAGS_0_DISCARD_0_SHIFT  0
+#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1
+#define CP_NV_FLAGS_0_DISCARD_1_SHIFT  2
+#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3
+#define CP_NV_FLAGS_0_DISCARD_2_SHIFT  4
+#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5
+#define CP_NV_FLAGS_0_DISCARD_3_SHIFT  6
+#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7
+#define CP_NV_FLAGS_0_DISCARD_4_SHIFT  8
+#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9
+#define CP_NV_FLAGS_0_DISCARD_5_SHIFT  10
+#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11
+#define CP_NV_FLAGS_0_DISCARD_6_SHIFT  12
+#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13
+#define CP_NV_FLAGS_0_DISCARD_7_SHIFT  14
+#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15
+#define CP_NV_FLAGS_0_DISCARD_8_SHIFT  16
+#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17
+#define CP_NV_FLAGS_0_DISCARD_9_SHIFT  18
+#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19
+#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20
+#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21
+#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22
+#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23
+#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24
+#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25
+#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26
+#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27
+#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28
+#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29
+#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30
+#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31
+
+#define CP_NV_FLAGS_0_DISCARD_0_MASK   0x00000001
+#define CP_NV_FLAGS_0_END_RCVD_0_MASK  0x00000002
+#define CP_NV_FLAGS_0_DISCARD_1_MASK   0x00000004
+#define CP_NV_FLAGS_0_END_RCVD_1_MASK  0x00000008
+#define CP_NV_FLAGS_0_DISCARD_2_MASK   0x00000010
+#define CP_NV_FLAGS_0_END_RCVD_2_MASK  0x00000020
+#define CP_NV_FLAGS_0_DISCARD_3_MASK   0x00000040
+#define CP_NV_FLAGS_0_END_RCVD_3_MASK  0x00000080
+#define CP_NV_FLAGS_0_DISCARD_4_MASK   0x00000100
+#define CP_NV_FLAGS_0_END_RCVD_4_MASK  0x00000200
+#define CP_NV_FLAGS_0_DISCARD_5_MASK   0x00000400
+#define CP_NV_FLAGS_0_END_RCVD_5_MASK  0x00000800
+#define CP_NV_FLAGS_0_DISCARD_6_MASK   0x00001000
+#define CP_NV_FLAGS_0_END_RCVD_6_MASK  0x00002000
+#define CP_NV_FLAGS_0_DISCARD_7_MASK   0x00004000
+#define CP_NV_FLAGS_0_END_RCVD_7_MASK  0x00008000
+#define CP_NV_FLAGS_0_DISCARD_8_MASK   0x00010000
+#define CP_NV_FLAGS_0_END_RCVD_8_MASK  0x00020000
+#define CP_NV_FLAGS_0_DISCARD_9_MASK   0x00040000
+#define CP_NV_FLAGS_0_END_RCVD_9_MASK  0x00080000
+#define CP_NV_FLAGS_0_DISCARD_10_MASK  0x00100000
+#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000
+#define CP_NV_FLAGS_0_DISCARD_11_MASK  0x00400000
+#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000
+#define CP_NV_FLAGS_0_DISCARD_12_MASK  0x01000000
+#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000
+#define CP_NV_FLAGS_0_DISCARD_13_MASK  0x04000000
+#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000
+#define CP_NV_FLAGS_0_DISCARD_14_MASK  0x10000000
+#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000
+#define CP_NV_FLAGS_0_DISCARD_15_MASK  0x40000000
+#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000
+
+#define CP_NV_FLAGS_0_MASK \
+     (CP_NV_FLAGS_0_DISCARD_0_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_0_MASK | \
+      CP_NV_FLAGS_0_DISCARD_1_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_1_MASK | \
+      CP_NV_FLAGS_0_DISCARD_2_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_2_MASK | \
+      CP_NV_FLAGS_0_DISCARD_3_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_3_MASK | \
+      CP_NV_FLAGS_0_DISCARD_4_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_4_MASK | \
+      CP_NV_FLAGS_0_DISCARD_5_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_5_MASK | \
+      CP_NV_FLAGS_0_DISCARD_6_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_6_MASK | \
+      CP_NV_FLAGS_0_DISCARD_7_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_7_MASK | \
+      CP_NV_FLAGS_0_DISCARD_8_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_8_MASK | \
+      CP_NV_FLAGS_0_DISCARD_9_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_9_MASK | \
+      CP_NV_FLAGS_0_DISCARD_10_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_10_MASK | \
+      CP_NV_FLAGS_0_DISCARD_11_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_11_MASK | \
+      CP_NV_FLAGS_0_DISCARD_12_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_12_MASK | \
+      CP_NV_FLAGS_0_DISCARD_13_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_13_MASK | \
+      CP_NV_FLAGS_0_DISCARD_14_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_14_MASK | \
+      CP_NV_FLAGS_0_DISCARD_15_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_15_MASK)
+
+#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \
+     ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \
+      (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \
+      (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \
+      (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \
+      (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \
+      (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \
+      (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \
+      (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \
+      (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \
+      (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \
+      (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \
+      (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \
+      (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \
+      (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \
+      (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \
+      (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \
+      (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \
+      (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \
+      (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \
+      (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \
+      (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \
+      (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \
+      (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \
+      (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \
+      (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \
+      (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \
+      (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \
+      (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \
+      (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \
+      (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \
+      (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \
+      (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT))
+
+#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+     } cp_nv_flags_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+     } cp_nv_flags_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_0_t f;
+} cp_nv_flags_0_u;
+
+
+/*
+ * CP_NV_FLAGS_1 struct
+ */
+
+#define CP_NV_FLAGS_1_DISCARD_16_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_17_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_18_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_19_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_20_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_21_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_22_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_23_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_24_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_25_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_26_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_27_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_28_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_29_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_30_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_31_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1
+
+#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0
+#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1
+#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2
+#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3
+#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4
+#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5
+#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6
+#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7
+#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8
+#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9
+#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10
+#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11
+#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12
+#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13
+#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14
+#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15
+#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16
+#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17
+#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18
+#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19
+#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20
+#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21
+#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22
+#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23
+#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24
+#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25
+#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26
+#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27
+#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28
+#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29
+#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30
+#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31
+
+#define CP_NV_FLAGS_1_DISCARD_16_MASK  0x00000001
+#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002
+#define CP_NV_FLAGS_1_DISCARD_17_MASK  0x00000004
+#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008
+#define CP_NV_FLAGS_1_DISCARD_18_MASK  0x00000010
+#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020
+#define CP_NV_FLAGS_1_DISCARD_19_MASK  0x00000040
+#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080
+#define CP_NV_FLAGS_1_DISCARD_20_MASK  0x00000100
+#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200
+#define CP_NV_FLAGS_1_DISCARD_21_MASK  0x00000400
+#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800
+#define CP_NV_FLAGS_1_DISCARD_22_MASK  0x00001000
+#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000
+#define CP_NV_FLAGS_1_DISCARD_23_MASK  0x00004000
+#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000
+#define CP_NV_FLAGS_1_DISCARD_24_MASK  0x00010000
+#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000
+#define CP_NV_FLAGS_1_DISCARD_25_MASK  0x00040000
+#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000
+#define CP_NV_FLAGS_1_DISCARD_26_MASK  0x00100000
+#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000
+#define CP_NV_FLAGS_1_DISCARD_27_MASK  0x00400000
+#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000
+#define CP_NV_FLAGS_1_DISCARD_28_MASK  0x01000000
+#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000
+#define CP_NV_FLAGS_1_DISCARD_29_MASK  0x04000000
+#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000
+#define CP_NV_FLAGS_1_DISCARD_30_MASK  0x10000000
+#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000
+#define CP_NV_FLAGS_1_DISCARD_31_MASK  0x40000000
+#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000
+
+#define CP_NV_FLAGS_1_MASK \
+     (CP_NV_FLAGS_1_DISCARD_16_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_16_MASK | \
+      CP_NV_FLAGS_1_DISCARD_17_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_17_MASK | \
+      CP_NV_FLAGS_1_DISCARD_18_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_18_MASK | \
+      CP_NV_FLAGS_1_DISCARD_19_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_19_MASK | \
+      CP_NV_FLAGS_1_DISCARD_20_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_20_MASK | \
+      CP_NV_FLAGS_1_DISCARD_21_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_21_MASK | \
+      CP_NV_FLAGS_1_DISCARD_22_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_22_MASK | \
+      CP_NV_FLAGS_1_DISCARD_23_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_23_MASK | \
+      CP_NV_FLAGS_1_DISCARD_24_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_24_MASK | \
+      CP_NV_FLAGS_1_DISCARD_25_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_25_MASK | \
+      CP_NV_FLAGS_1_DISCARD_26_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_26_MASK | \
+      CP_NV_FLAGS_1_DISCARD_27_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_27_MASK | \
+      CP_NV_FLAGS_1_DISCARD_28_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_28_MASK | \
+      CP_NV_FLAGS_1_DISCARD_29_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_29_MASK | \
+      CP_NV_FLAGS_1_DISCARD_30_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_30_MASK | \
+      CP_NV_FLAGS_1_DISCARD_31_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_31_MASK)
+
+#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \
+     ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \
+      (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \
+      (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \
+      (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \
+      (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \
+      (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \
+      (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \
+      (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \
+      (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \
+      (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \
+      (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \
+      (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \
+      (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \
+      (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \
+      (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \
+      (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \
+      (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \
+      (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \
+      (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \
+      (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \
+      (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \
+      (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \
+      (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \
+      (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \
+      (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \
+      (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \
+      (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \
+      (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \
+      (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \
+      (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \
+      (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \
+      (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT))
+
+#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+     } cp_nv_flags_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+     } cp_nv_flags_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_1_t f;
+} cp_nv_flags_1_u;
+
+
+/*
+ * CP_NV_FLAGS_2 struct
+ */
+
+#define CP_NV_FLAGS_2_DISCARD_32_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_33_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_34_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_35_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_36_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_37_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_38_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_39_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_40_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_41_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_42_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_43_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_44_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_45_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_46_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_47_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1
+
+#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0
+#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1
+#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2
+#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3
+#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4
+#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5
+#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6
+#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7
+#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8
+#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9
+#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10
+#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11
+#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12
+#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13
+#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14
+#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15
+#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16
+#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17
+#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18
+#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19
+#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20
+#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21
+#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22
+#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23
+#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24
+#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25
+#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26
+#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27
+#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28
+#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29
+#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30
+#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31
+
+#define CP_NV_FLAGS_2_DISCARD_32_MASK  0x00000001
+#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002
+#define CP_NV_FLAGS_2_DISCARD_33_MASK  0x00000004
+#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008
+#define CP_NV_FLAGS_2_DISCARD_34_MASK  0x00000010
+#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020
+#define CP_NV_FLAGS_2_DISCARD_35_MASK  0x00000040
+#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080
+#define CP_NV_FLAGS_2_DISCARD_36_MASK  0x00000100
+#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200
+#define CP_NV_FLAGS_2_DISCARD_37_MASK  0x00000400
+#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800
+#define CP_NV_FLAGS_2_DISCARD_38_MASK  0x00001000
+#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000
+#define CP_NV_FLAGS_2_DISCARD_39_MASK  0x00004000
+#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000
+#define CP_NV_FLAGS_2_DISCARD_40_MASK  0x00010000
+#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000
+#define CP_NV_FLAGS_2_DISCARD_41_MASK  0x00040000
+#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000
+#define CP_NV_FLAGS_2_DISCARD_42_MASK  0x00100000
+#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000
+#define CP_NV_FLAGS_2_DISCARD_43_MASK  0x00400000
+#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000
+#define CP_NV_FLAGS_2_DISCARD_44_MASK  0x01000000
+#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000
+#define CP_NV_FLAGS_2_DISCARD_45_MASK  0x04000000
+#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000
+#define CP_NV_FLAGS_2_DISCARD_46_MASK  0x10000000
+#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000
+#define CP_NV_FLAGS_2_DISCARD_47_MASK  0x40000000
+#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000
+
+#define CP_NV_FLAGS_2_MASK \
+     (CP_NV_FLAGS_2_DISCARD_32_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_32_MASK | \
+      CP_NV_FLAGS_2_DISCARD_33_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_33_MASK | \
+      CP_NV_FLAGS_2_DISCARD_34_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_34_MASK | \
+      CP_NV_FLAGS_2_DISCARD_35_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_35_MASK | \
+      CP_NV_FLAGS_2_DISCARD_36_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_36_MASK | \
+      CP_NV_FLAGS_2_DISCARD_37_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_37_MASK | \
+      CP_NV_FLAGS_2_DISCARD_38_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_38_MASK | \
+      CP_NV_FLAGS_2_DISCARD_39_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_39_MASK | \
+      CP_NV_FLAGS_2_DISCARD_40_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_40_MASK | \
+      CP_NV_FLAGS_2_DISCARD_41_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_41_MASK | \
+      CP_NV_FLAGS_2_DISCARD_42_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_42_MASK | \
+      CP_NV_FLAGS_2_DISCARD_43_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_43_MASK | \
+      CP_NV_FLAGS_2_DISCARD_44_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_44_MASK | \
+      CP_NV_FLAGS_2_DISCARD_45_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_45_MASK | \
+      CP_NV_FLAGS_2_DISCARD_46_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_46_MASK | \
+      CP_NV_FLAGS_2_DISCARD_47_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_47_MASK)
+
+#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \
+     ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \
+      (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \
+      (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \
+      (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \
+      (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \
+      (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \
+      (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \
+      (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \
+      (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \
+      (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \
+      (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \
+      (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \
+      (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \
+      (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \
+      (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \
+      (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \
+      (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \
+      (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \
+      (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \
+      (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \
+      (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \
+      (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \
+      (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \
+      (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \
+      (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \
+      (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \
+      (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \
+      (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \
+      (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \
+      (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \
+      (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \
+      (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT))
+
+#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+     } cp_nv_flags_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+     } cp_nv_flags_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_2_t f;
+} cp_nv_flags_2_u;
+
+
+/*
+ * CP_NV_FLAGS_3 struct
+ */
+
+#define CP_NV_FLAGS_3_DISCARD_48_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_49_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_50_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_51_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_52_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_53_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_54_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_55_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_56_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_57_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_58_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_59_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_60_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_61_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_62_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_63_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1
+
+#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0
+#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1
+#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2
+#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3
+#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4
+#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5
+#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6
+#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7
+#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8
+#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9
+#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10
+#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11
+#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12
+#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13
+#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14
+#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15
+#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16
+#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17
+#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18
+#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19
+#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20
+#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21
+#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22
+#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23
+#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24
+#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25
+#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26
+#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27
+#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28
+#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29
+#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30
+#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31
+
+#define CP_NV_FLAGS_3_DISCARD_48_MASK  0x00000001
+#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002
+#define CP_NV_FLAGS_3_DISCARD_49_MASK  0x00000004
+#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008
+#define CP_NV_FLAGS_3_DISCARD_50_MASK  0x00000010
+#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020
+#define CP_NV_FLAGS_3_DISCARD_51_MASK  0x00000040
+#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080
+#define CP_NV_FLAGS_3_DISCARD_52_MASK  0x00000100
+#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200
+#define CP_NV_FLAGS_3_DISCARD_53_MASK  0x00000400
+#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800
+#define CP_NV_FLAGS_3_DISCARD_54_MASK  0x00001000
+#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000
+#define CP_NV_FLAGS_3_DISCARD_55_MASK  0x00004000
+#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000
+#define CP_NV_FLAGS_3_DISCARD_56_MASK  0x00010000
+#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000
+#define CP_NV_FLAGS_3_DISCARD_57_MASK  0x00040000
+#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000
+#define CP_NV_FLAGS_3_DISCARD_58_MASK  0x00100000
+#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000
+#define CP_NV_FLAGS_3_DISCARD_59_MASK  0x00400000
+#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000
+#define CP_NV_FLAGS_3_DISCARD_60_MASK  0x01000000
+#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000
+#define CP_NV_FLAGS_3_DISCARD_61_MASK  0x04000000
+#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000
+#define CP_NV_FLAGS_3_DISCARD_62_MASK  0x10000000
+#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000
+#define CP_NV_FLAGS_3_DISCARD_63_MASK  0x40000000
+#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000
+
+#define CP_NV_FLAGS_3_MASK \
+     (CP_NV_FLAGS_3_DISCARD_48_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_48_MASK | \
+      CP_NV_FLAGS_3_DISCARD_49_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_49_MASK | \
+      CP_NV_FLAGS_3_DISCARD_50_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_50_MASK | \
+      CP_NV_FLAGS_3_DISCARD_51_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_51_MASK | \
+      CP_NV_FLAGS_3_DISCARD_52_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_52_MASK | \
+      CP_NV_FLAGS_3_DISCARD_53_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_53_MASK | \
+      CP_NV_FLAGS_3_DISCARD_54_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_54_MASK | \
+      CP_NV_FLAGS_3_DISCARD_55_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_55_MASK | \
+      CP_NV_FLAGS_3_DISCARD_56_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_56_MASK | \
+      CP_NV_FLAGS_3_DISCARD_57_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_57_MASK | \
+      CP_NV_FLAGS_3_DISCARD_58_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_58_MASK | \
+      CP_NV_FLAGS_3_DISCARD_59_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_59_MASK | \
+      CP_NV_FLAGS_3_DISCARD_60_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_60_MASK | \
+      CP_NV_FLAGS_3_DISCARD_61_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_61_MASK | \
+      CP_NV_FLAGS_3_DISCARD_62_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_62_MASK | \
+      CP_NV_FLAGS_3_DISCARD_63_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_63_MASK)
+
+#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \
+     ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \
+      (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \
+      (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \
+      (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \
+      (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \
+      (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \
+      (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \
+      (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \
+      (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \
+      (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \
+      (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \
+      (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \
+      (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \
+      (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \
+      (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \
+      (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \
+      (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \
+      (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \
+      (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \
+      (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \
+      (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \
+      (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \
+      (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \
+      (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \
+      (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \
+      (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \
+      (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \
+      (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \
+      (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \
+      (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \
+      (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \
+      (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT))
+
+#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+     } cp_nv_flags_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+     } cp_nv_flags_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_3_t f;
+} cp_nv_flags_3_u;
+
+
+/*
+ * CP_STATE_DEBUG_INDEX struct
+ */
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f
+
+#define CP_STATE_DEBUG_INDEX_MASK \
+     (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK)
+
+#define CP_STATE_DEBUG_INDEX(state_debug_index) \
+     ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT))
+
+#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \
+     ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \
+     cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+          unsigned int                                : 27;
+     } cp_state_debug_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int                                : 27;
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+     } cp_state_debug_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_index_t f;
+} cp_state_debug_index_u;
+
+
+/*
+ * CP_STATE_DEBUG_DATA struct
+ */
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_STATE_DEBUG_DATA_MASK \
+     (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK)
+
+#define CP_STATE_DEBUG_DATA(state_debug_data) \
+     ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT))
+
+#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \
+     ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \
+     cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_data_t f;
+} cp_state_debug_data_u;
+
+
+/*
+ * CP_PROG_COUNTER struct
+ */
+
+#define CP_PROG_COUNTER_COUNTER_SIZE   32
+
+#define CP_PROG_COUNTER_COUNTER_SHIFT  0
+
+#define CP_PROG_COUNTER_COUNTER_MASK   0xffffffff
+
+#define CP_PROG_COUNTER_MASK \
+     (CP_PROG_COUNTER_COUNTER_MASK)
+
+#define CP_PROG_COUNTER(counter) \
+     ((counter << CP_PROG_COUNTER_COUNTER_SHIFT))
+
+#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \
+     ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \
+     cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_prog_counter_t f;
+} cp_prog_counter_u;
+
+
+/*
+ * CP_STAT struct
+ */
+
+#define CP_STAT_MIU_WR_BUSY_SIZE       1
+#define CP_STAT_MIU_RD_REQ_BUSY_SIZE   1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1
+#define CP_STAT_RBIU_BUSY_SIZE         1
+#define CP_STAT_RCIU_BUSY_SIZE         1
+#define CP_STAT_CSF_RING_BUSY_SIZE     1
+#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_CSF_ST_BUSY_SIZE       1
+#define CP_STAT_CSF_BUSY_SIZE          1
+#define CP_STAT_RING_QUEUE_BUSY_SIZE   1
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1
+#define CP_STAT_ST_QUEUE_BUSY_SIZE     1
+#define CP_STAT_PFP_BUSY_SIZE          1
+#define CP_STAT_MEQ_RING_BUSY_SIZE     1
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_MIU_WC_STALL_SIZE      1
+#define CP_STAT_CP_NRT_BUSY_SIZE       1
+#define CP_STAT__3D_BUSY_SIZE          1
+#define CP_STAT_ME_BUSY_SIZE           1
+#define CP_STAT_ME_WC_BUSY_SIZE        1
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1
+#define CP_STAT_CP_BUSY_SIZE           1
+
+#define CP_STAT_MIU_WR_BUSY_SHIFT      0
+#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT  1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2
+#define CP_STAT_RBIU_BUSY_SHIFT        3
+#define CP_STAT_RCIU_BUSY_SHIFT        4
+#define CP_STAT_CSF_RING_BUSY_SHIFT    5
+#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6
+#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7
+#define CP_STAT_CSF_ST_BUSY_SHIFT      9
+#define CP_STAT_CSF_BUSY_SHIFT         10
+#define CP_STAT_RING_QUEUE_BUSY_SHIFT  11
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13
+#define CP_STAT_ST_QUEUE_BUSY_SHIFT    16
+#define CP_STAT_PFP_BUSY_SHIFT         17
+#define CP_STAT_MEQ_RING_BUSY_SHIFT    18
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20
+#define CP_STAT_MIU_WC_STALL_SHIFT     21
+#define CP_STAT_CP_NRT_BUSY_SHIFT      22
+#define CP_STAT__3D_BUSY_SHIFT         23
+#define CP_STAT_ME_BUSY_SHIFT          26
+#define CP_STAT_ME_WC_BUSY_SHIFT       29
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30
+#define CP_STAT_CP_BUSY_SHIFT          31
+
+#define CP_STAT_MIU_WR_BUSY_MASK       0x00000001
+#define CP_STAT_MIU_RD_REQ_BUSY_MASK   0x00000002
+#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004
+#define CP_STAT_RBIU_BUSY_MASK         0x00000008
+#define CP_STAT_RCIU_BUSY_MASK         0x00000010
+#define CP_STAT_CSF_RING_BUSY_MASK     0x00000020
+#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040
+#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080
+#define CP_STAT_CSF_ST_BUSY_MASK       0x00000200
+#define CP_STAT_CSF_BUSY_MASK          0x00000400
+#define CP_STAT_RING_QUEUE_BUSY_MASK   0x00000800
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000
+#define CP_STAT_ST_QUEUE_BUSY_MASK     0x00010000
+#define CP_STAT_PFP_BUSY_MASK          0x00020000
+#define CP_STAT_MEQ_RING_BUSY_MASK     0x00040000
+#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000
+#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000
+#define CP_STAT_MIU_WC_STALL_MASK      0x00200000
+#define CP_STAT_CP_NRT_BUSY_MASK       0x00400000
+#define CP_STAT__3D_BUSY_MASK          0x00800000
+#define CP_STAT_ME_BUSY_MASK           0x04000000
+#define CP_STAT_ME_WC_BUSY_MASK        0x20000000
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000
+#define CP_STAT_CP_BUSY_MASK           0x80000000
+
+#define CP_STAT_MASK \
+     (CP_STAT_MIU_WR_BUSY_MASK | \
+      CP_STAT_MIU_RD_REQ_BUSY_MASK | \
+      CP_STAT_MIU_RD_RETURN_BUSY_MASK | \
+      CP_STAT_RBIU_BUSY_MASK | \
+      CP_STAT_RCIU_BUSY_MASK | \
+      CP_STAT_CSF_RING_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECTS_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECT2_BUSY_MASK | \
+      CP_STAT_CSF_ST_BUSY_MASK | \
+      CP_STAT_CSF_BUSY_MASK | \
+      CP_STAT_RING_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \
+      CP_STAT_ST_QUEUE_BUSY_MASK | \
+      CP_STAT_PFP_BUSY_MASK | \
+      CP_STAT_MEQ_RING_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \
+      CP_STAT_MIU_WC_STALL_MASK | \
+      CP_STAT_CP_NRT_BUSY_MASK | \
+      CP_STAT__3D_BUSY_MASK | \
+      CP_STAT_ME_BUSY_MASK | \
+      CP_STAT_ME_WC_BUSY_MASK | \
+      CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \
+      CP_STAT_CP_BUSY_MASK)
+
+#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \
+     ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \
+      (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \
+      (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \
+      (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \
+      (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \
+      (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \
+      (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \
+      (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \
+      (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \
+      (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \
+      (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \
+      (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \
+      (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \
+      (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \
+      (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \
+      (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \
+      (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \
+      (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \
+      (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \
+      (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \
+      (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \
+      (me_busy << CP_STAT_ME_BUSY_SHIFT) | \
+      (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \
+      (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \
+      (cp_busy << CP_STAT_CP_BUSY_SHIFT))
+
+#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_GET_RBIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_GET_RCIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_PFP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_GET__3D_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_GET_ME_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_GET_CP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT)
+
+#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+     } cp_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+     } cp_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stat_t f;
+} cp_stat_u;
+
+
+/*
+ * BIOS_0_SCRATCH struct
+ */
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_0_SCRATCH_MASK \
+     (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_0_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \
+     ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \
+     bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_0_scratch_t f;
+} bios_0_scratch_u;
+
+
+/*
+ * BIOS_1_SCRATCH struct
+ */
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_1_SCRATCH_MASK \
+     (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_1_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \
+     ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \
+     bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_1_scratch_t f;
+} bios_1_scratch_u;
+
+
+/*
+ * BIOS_2_SCRATCH struct
+ */
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_2_SCRATCH_MASK \
+     (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_2_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \
+     ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \
+     bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_2_scratch_t f;
+} bios_2_scratch_u;
+
+
+/*
+ * BIOS_3_SCRATCH struct
+ */
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_3_SCRATCH_MASK \
+     (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_3_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \
+     ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \
+     bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_3_scratch_t f;
+} bios_3_scratch_u;
+
+
+/*
+ * BIOS_4_SCRATCH struct
+ */
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_4_SCRATCH_MASK \
+     (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_4_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \
+     ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \
+     bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_4_scratch_t f;
+} bios_4_scratch_u;
+
+
+/*
+ * BIOS_5_SCRATCH struct
+ */
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_5_SCRATCH_MASK \
+     (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_5_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \
+     ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \
+     bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_5_scratch_t f;
+} bios_5_scratch_u;
+
+
+/*
+ * BIOS_6_SCRATCH struct
+ */
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_6_SCRATCH_MASK \
+     (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_6_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \
+     ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \
+     bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_6_scratch_t f;
+} bios_6_scratch_u;
+
+
+/*
+ * BIOS_7_SCRATCH struct
+ */
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_7_SCRATCH_MASK \
+     (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_7_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \
+     ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \
+     bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_7_scratch_t f;
+} bios_7_scratch_u;
+
+
+/*
+ * BIOS_8_SCRATCH struct
+ */
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_8_SCRATCH_MASK \
+     (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_8_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \
+     ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \
+     bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_8_scratch_t f;
+} bios_8_scratch_u;
+
+
+/*
+ * BIOS_9_SCRATCH struct
+ */
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_9_SCRATCH_MASK \
+     (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_9_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \
+     ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \
+     bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_9_scratch_t f;
+} bios_9_scratch_u;
+
+
+/*
+ * BIOS_10_SCRATCH struct
+ */
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_10_SCRATCH_MASK \
+     (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_10_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \
+     ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \
+     bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_10_scratch_t f;
+} bios_10_scratch_u;
+
+
+/*
+ * BIOS_11_SCRATCH struct
+ */
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_11_SCRATCH_MASK \
+     (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_11_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \
+     ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \
+     bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_11_scratch_t f;
+} bios_11_scratch_u;
+
+
+/*
+ * BIOS_12_SCRATCH struct
+ */
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_12_SCRATCH_MASK \
+     (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_12_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \
+     ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \
+     bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_12_scratch_t f;
+} bios_12_scratch_u;
+
+
+/*
+ * BIOS_13_SCRATCH struct
+ */
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_13_SCRATCH_MASK \
+     (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_13_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \
+     ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \
+     bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_13_scratch_t f;
+} bios_13_scratch_u;
+
+
+/*
+ * BIOS_14_SCRATCH struct
+ */
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_14_SCRATCH_MASK \
+     (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_14_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \
+     ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \
+     bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_14_scratch_t f;
+} bios_14_scratch_u;
+
+
+/*
+ * BIOS_15_SCRATCH struct
+ */
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_15_SCRATCH_MASK \
+     (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_15_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \
+     ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \
+     bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_15_scratch_t f;
+} bios_15_scratch_u;
+
+
+/*
+ * COHER_SIZE_PM4 struct
+ */
+
+#define COHER_SIZE_PM4_SIZE_SIZE       32
+
+#define COHER_SIZE_PM4_SIZE_SHIFT      0
+
+#define COHER_SIZE_PM4_SIZE_MASK       0xffffffff
+
+#define COHER_SIZE_PM4_MASK \
+     (COHER_SIZE_PM4_SIZE_MASK)
+
+#define COHER_SIZE_PM4(size) \
+     ((size << COHER_SIZE_PM4_SIZE_SHIFT))
+
+#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \
+     ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT)
+
+#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \
+     coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_pm4_t f;
+} coher_size_pm4_u;
+
+
+/*
+ * COHER_BASE_PM4 struct
+ */
+
+#define COHER_BASE_PM4_BASE_SIZE       32
+
+#define COHER_BASE_PM4_BASE_SHIFT      0
+
+#define COHER_BASE_PM4_BASE_MASK       0xffffffff
+
+#define COHER_BASE_PM4_MASK \
+     (COHER_BASE_PM4_BASE_MASK)
+
+#define COHER_BASE_PM4(base) \
+     ((base << COHER_BASE_PM4_BASE_SHIFT))
+
+#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \
+     ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT)
+
+#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \
+     coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_pm4_t f;
+} coher_base_pm4_u;
+
+
+/*
+ * COHER_STATUS_PM4 struct
+ */
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE 1
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_PM4_STATUS_SIZE   1
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT 17
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_PM4_STATUS_SHIFT  31
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK 0x00020000
+#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_PM4_STATUS_MASK   0x80000000
+
+#define COHER_STATUS_PM4_MASK \
+     (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK | \
+      COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_PM4_STATUS_MASK)
+
+#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \
+      (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_PM4_STATUS_SHIFT))
+
+#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COLOR_INFO_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT)
+
+#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COLOR_INFO_ENA(coher_status_pm4_reg, rb_color_info_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int rb_color_info_ena              : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+     } coher_status_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int rb_color_info_ena              : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+     } coher_status_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_pm4_t f;
+} coher_status_pm4_u;
+
+
+/*
+ * COHER_SIZE_HOST struct
+ */
+
+#define COHER_SIZE_HOST_SIZE_SIZE      32
+
+#define COHER_SIZE_HOST_SIZE_SHIFT     0
+
+#define COHER_SIZE_HOST_SIZE_MASK      0xffffffff
+
+#define COHER_SIZE_HOST_MASK \
+     (COHER_SIZE_HOST_SIZE_MASK)
+
+#define COHER_SIZE_HOST(size) \
+     ((size << COHER_SIZE_HOST_SIZE_SHIFT))
+
+#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \
+     ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT)
+
+#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \
+     coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_host_t f;
+} coher_size_host_u;
+
+
+/*
+ * COHER_BASE_HOST struct
+ */
+
+#define COHER_BASE_HOST_BASE_SIZE      32
+
+#define COHER_BASE_HOST_BASE_SHIFT     0
+
+#define COHER_BASE_HOST_BASE_MASK      0xffffffff
+
+#define COHER_BASE_HOST_MASK \
+     (COHER_BASE_HOST_BASE_MASK)
+
+#define COHER_BASE_HOST(base) \
+     ((base << COHER_BASE_HOST_BASE_SHIFT))
+
+#define COHER_BASE_HOST_GET_BASE(coher_base_host) \
+     ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT)
+
+#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \
+     coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_host_t f;
+} coher_base_host_u;
+
+
+/*
+ * COHER_STATUS_HOST struct
+ */
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE 1
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_HOST_STATUS_SIZE  1
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT 17
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_HOST_STATUS_SHIFT 31
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK 0x00020000
+#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_HOST_STATUS_MASK  0x80000000
+
+#define COHER_STATUS_HOST_MASK \
+     (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK | \
+      COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_HOST_STATUS_MASK)
+
+#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \
+      (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_HOST_STATUS_SHIFT))
+
+#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COLOR_INFO_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT)
+
+#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COLOR_INFO_ENA(coher_status_host_reg, rb_color_info_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int rb_color_info_ena              : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+     } coher_status_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int rb_color_info_ena              : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+     } coher_status_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_host_t f;
+} coher_status_host_u;
+
+
+/*
+ * COHER_DEST_BASE_0 struct
+ */
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000
+
+#define COHER_DEST_BASE_0_MASK \
+     (COHER_DEST_BASE_0_DEST_BASE_0_MASK)
+
+#define COHER_DEST_BASE_0(dest_base_0) \
+     ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT))
+
+#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \
+     ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \
+     coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+     } coher_dest_base_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_0_t f;
+} coher_dest_base_0_u;
+
+
+/*
+ * COHER_DEST_BASE_1 struct
+ */
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000
+
+#define COHER_DEST_BASE_1_MASK \
+     (COHER_DEST_BASE_1_DEST_BASE_1_MASK)
+
+#define COHER_DEST_BASE_1(dest_base_1) \
+     ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT))
+
+#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \
+     ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \
+     coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+     } coher_dest_base_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_1_t f;
+} coher_dest_base_1_u;
+
+
+/*
+ * COHER_DEST_BASE_2 struct
+ */
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000
+
+#define COHER_DEST_BASE_2_MASK \
+     (COHER_DEST_BASE_2_DEST_BASE_2_MASK)
+
+#define COHER_DEST_BASE_2(dest_base_2) \
+     ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT))
+
+#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \
+     ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \
+     coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+     } coher_dest_base_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_2_t f;
+} coher_dest_base_2_u;
+
+
+/*
+ * COHER_DEST_BASE_3 struct
+ */
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000
+
+#define COHER_DEST_BASE_3_MASK \
+     (COHER_DEST_BASE_3_DEST_BASE_3_MASK)
+
+#define COHER_DEST_BASE_3(dest_base_3) \
+     ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT))
+
+#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \
+     ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \
+     coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+     } coher_dest_base_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_3_t f;
+} coher_dest_base_3_u;
+
+
+/*
+ * COHER_DEST_BASE_4 struct
+ */
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000
+
+#define COHER_DEST_BASE_4_MASK \
+     (COHER_DEST_BASE_4_DEST_BASE_4_MASK)
+
+#define COHER_DEST_BASE_4(dest_base_4) \
+     ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT))
+
+#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \
+     ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \
+     coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+     } coher_dest_base_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_4_t f;
+} coher_dest_base_4_u;
+
+
+/*
+ * COHER_DEST_BASE_5 struct
+ */
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000
+
+#define COHER_DEST_BASE_5_MASK \
+     (COHER_DEST_BASE_5_DEST_BASE_5_MASK)
+
+#define COHER_DEST_BASE_5(dest_base_5) \
+     ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT))
+
+#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \
+     ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \
+     coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+     } coher_dest_base_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_5_t f;
+} coher_dest_base_5_u;
+
+
+/*
+ * COHER_DEST_BASE_6 struct
+ */
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000
+
+#define COHER_DEST_BASE_6_MASK \
+     (COHER_DEST_BASE_6_DEST_BASE_6_MASK)
+
+#define COHER_DEST_BASE_6(dest_base_6) \
+     ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT))
+
+#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \
+     ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \
+     coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+     } coher_dest_base_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_6_t f;
+} coher_dest_base_6_u;
+
+
+/*
+ * COHER_DEST_BASE_7 struct
+ */
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000
+
+#define COHER_DEST_BASE_7_MASK \
+     (COHER_DEST_BASE_7_DEST_BASE_7_MASK)
+
+#define COHER_DEST_BASE_7(dest_base_7) \
+     ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT))
+
+#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \
+     ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \
+     coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+     } coher_dest_base_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_7_t f;
+} coher_dest_base_7_u;
+
+
+#endif
+
+
+#if !defined (_RBBM_FIDDLE_H)
+#define _RBBM_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  rbbm_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * WAIT_UNTIL struct
+ */
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_VSYNC_SIZE     1
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1
+#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2
+#define WAIT_UNTIL_WAIT_VSYNC_SHIFT    3
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6
+#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT  10
+#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT  14
+#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT  15
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK  0x00000002
+#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK  0x00000004
+#define WAIT_UNTIL_WAIT_VSYNC_MASK     0x00000008
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040
+#define WAIT_UNTIL_WAIT_CMDFIFO_MASK   0x00000400
+#define WAIT_UNTIL_WAIT_2D_IDLE_MASK   0x00004000
+#define WAIT_UNTIL_WAIT_3D_IDLE_MASK   0x00008000
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000
+
+#define WAIT_UNTIL_MASK \
+     (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \
+      WAIT_UNTIL_WAIT_CMDFIFO_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_CMDFIFO_ENTRIES_MASK)
+
+#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \
+     ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \
+      (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \
+      (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \
+      (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \
+      (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \
+      (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \
+      (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \
+      (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \
+      (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \
+      (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \
+      (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \
+      (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT))
+
+#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \
+     ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 1;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int                                : 2;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 8;
+     } wait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 8;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 2;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int                                : 1;
+     } wait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     wait_until_t f;
+} wait_until_u;
+
+
+/*
+ * RBBM_ISYNC_CNTL struct
+ */
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020
+
+#define RBBM_ISYNC_CNTL_MASK \
+     (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \
+      RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK)
+
+#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \
+     ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \
+      (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT))
+
+#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 4;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int                                : 26;
+     } rbbm_isync_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 26;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int                                : 4;
+     } rbbm_isync_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_isync_cntl_t f;
+} rbbm_isync_cntl_u;
+
+
+/*
+ * RBBM_STATUS struct
+ */
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5
+#define RBBM_STATUS_TC_BUSY_SIZE       1
+#define RBBM_STATUS_HIRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CPRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_PFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1
+#define RBBM_STATUS_RBBM_WU_BUSY_SIZE  1
+#define RBBM_STATUS_CP_NRT_BUSY_SIZE   1
+#define RBBM_STATUS_MH_BUSY_SIZE       1
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1
+#define RBBM_STATUS_SX_BUSY_SIZE       1
+#define RBBM_STATUS_TPC_BUSY_SIZE      1
+#define RBBM_STATUS_SC_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_PA_BUSY_SIZE       1
+#define RBBM_STATUS_VGT_BUSY_SIZE      1
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1
+#define RBBM_STATUS_RB_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_GUI_ACTIVE_SIZE    1
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0
+#define RBBM_STATUS_TC_BUSY_SHIFT      5
+#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8
+#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9
+#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10
+#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12
+#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14
+#define RBBM_STATUS_CP_NRT_BUSY_SHIFT  16
+#define RBBM_STATUS_MH_BUSY_SHIFT      18
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19
+#define RBBM_STATUS_SX_BUSY_SHIFT      21
+#define RBBM_STATUS_TPC_BUSY_SHIFT     22
+#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24
+#define RBBM_STATUS_PA_BUSY_SHIFT      25
+#define RBBM_STATUS_VGT_BUSY_SHIFT     26
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28
+#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30
+#define RBBM_STATUS_GUI_ACTIVE_SHIFT   31
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f
+#define RBBM_STATUS_TC_BUSY_MASK       0x00000020
+#define RBBM_STATUS_HIRQ_PENDING_MASK  0x00000100
+#define RBBM_STATUS_CPRQ_PENDING_MASK  0x00000200
+#define RBBM_STATUS_CFRQ_PENDING_MASK  0x00000400
+#define RBBM_STATUS_PFRQ_PENDING_MASK  0x00000800
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000
+#define RBBM_STATUS_RBBM_WU_BUSY_MASK  0x00004000
+#define RBBM_STATUS_CP_NRT_BUSY_MASK   0x00010000
+#define RBBM_STATUS_MH_BUSY_MASK       0x00040000
+#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000
+#define RBBM_STATUS_SX_BUSY_MASK       0x00200000
+#define RBBM_STATUS_TPC_BUSY_MASK      0x00400000
+#define RBBM_STATUS_SC_CNTX_BUSY_MASK  0x01000000
+#define RBBM_STATUS_PA_BUSY_MASK       0x02000000
+#define RBBM_STATUS_VGT_BUSY_MASK      0x04000000
+#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000
+#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000
+#define RBBM_STATUS_RB_CNTX_BUSY_MASK  0x40000000
+#define RBBM_STATUS_GUI_ACTIVE_MASK    0x80000000
+
+#define RBBM_STATUS_MASK \
+     (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \
+      RBBM_STATUS_TC_BUSY_MASK | \
+      RBBM_STATUS_HIRQ_PENDING_MASK | \
+      RBBM_STATUS_CPRQ_PENDING_MASK | \
+      RBBM_STATUS_CFRQ_PENDING_MASK | \
+      RBBM_STATUS_PFRQ_PENDING_MASK | \
+      RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \
+      RBBM_STATUS_RBBM_WU_BUSY_MASK | \
+      RBBM_STATUS_CP_NRT_BUSY_MASK | \
+      RBBM_STATUS_MH_BUSY_MASK | \
+      RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \
+      RBBM_STATUS_SX_BUSY_MASK | \
+      RBBM_STATUS_TPC_BUSY_MASK | \
+      RBBM_STATUS_SC_CNTX_BUSY_MASK | \
+      RBBM_STATUS_PA_BUSY_MASK | \
+      RBBM_STATUS_VGT_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \
+      RBBM_STATUS_RB_CNTX_BUSY_MASK | \
+      RBBM_STATUS_GUI_ACTIVE_MASK)
+
+#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \
+     ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \
+      (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \
+      (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \
+      (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \
+      (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \
+      (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \
+      (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \
+      (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \
+      (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \
+      (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \
+      (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \
+      (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \
+      (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \
+      (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \
+      (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \
+      (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \
+      (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \
+      (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \
+      (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \
+      (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT))
+
+#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+     } rbbm_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int                                : 2;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+     } rbbm_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_status_t f;
+} rbbm_status_u;
+
+
+/*
+ * RBBM_DSPLY struct
+ */
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE 2
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE 2
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT 0
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT 2
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT 3
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT 4
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT 5
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT 6
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT 7
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT 8
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT 10
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT 11
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT 12
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT 13
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT 14
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT 16
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT 20
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT 21
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT 22
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT 23
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT 24
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT 26
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT 27
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT 28
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT 29
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT 30
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK 0x00000008
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK 0x00000010
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK 0x00000020
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK 0x00000040
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK 0x00000080
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK 0x00000300
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK 0x00000400
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK 0x00000800
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK 0x00001000
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK 0x00002000
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK 0x0000c000
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK 0x00030000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK 0x00100000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK 0x00200000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK 0x00400000
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK 0x00800000
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK 0x03000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK 0x04000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK 0x08000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK 0x10000000
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK 0x20000000
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK 0xc0000000
+
+#define RBBM_DSPLY_MASK \
+     (RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK | \
+      RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK | \
+      RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK | \
+      RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK)
+
+#define RBBM_DSPLY(sel_dmi_active_bufid0, sel_dmi_active_bufid1, sel_dmi_active_bufid2, sel_dmi_vsync_valid, dmi_ch1_use_bufid0, dmi_ch1_use_bufid1, dmi_ch1_use_bufid2, dmi_ch1_sw_cntl, dmi_ch1_num_bufs, dmi_ch2_use_bufid0, dmi_ch2_use_bufid1, dmi_ch2_use_bufid2, dmi_ch2_sw_cntl, dmi_ch2_num_bufs, dmi_channel_select, dmi_ch3_use_bufid0, dmi_ch3_use_bufid1, dmi_ch3_use_bufid2, dmi_ch3_sw_cntl, dmi_ch3_num_bufs, dmi_ch4_use_bufid0, dmi_ch4_use_bufid1, dmi_ch4_use_bufid2, dmi_ch4_sw_cntl, dmi_ch4_num_bufs) \
+     ((sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) | \
+      (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) | \
+      (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) | \
+      (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) | \
+      (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) | \
+      (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) | \
+      (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) | \
+      (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) | \
+      (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) | \
+      (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) | \
+      (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) | \
+      (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) | \
+      (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) | \
+      (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) | \
+      (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) | \
+      (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) | \
+      (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) | \
+      (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) | \
+      (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) | \
+      (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) | \
+      (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) | \
+      (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) | \
+      (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) | \
+      (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) | \
+      (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT))
+
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_VSYNC_VALID(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) >> RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CHANNEL_SELECT(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) >> RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)
+
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply_reg, sel_dmi_active_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) | (sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply_reg, sel_dmi_active_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) | (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply_reg, sel_dmi_active_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) | (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_VSYNC_VALID(rbbm_dsply_reg, sel_dmi_vsync_valid) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) | (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID0(rbbm_dsply_reg, dmi_ch1_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) | (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID1(rbbm_dsply_reg, dmi_ch1_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) | (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID2(rbbm_dsply_reg, dmi_ch1_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) | (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_SW_CNTL(rbbm_dsply_reg, dmi_ch1_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) | (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_NUM_BUFS(rbbm_dsply_reg, dmi_ch1_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) | (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID0(rbbm_dsply_reg, dmi_ch2_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) | (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID1(rbbm_dsply_reg, dmi_ch2_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) | (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID2(rbbm_dsply_reg, dmi_ch2_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) | (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_SW_CNTL(rbbm_dsply_reg, dmi_ch2_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) | (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_NUM_BUFS(rbbm_dsply_reg, dmi_ch2_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) | (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CHANNEL_SELECT(rbbm_dsply_reg, dmi_channel_select) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) | (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID0(rbbm_dsply_reg, dmi_ch3_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) | (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID1(rbbm_dsply_reg, dmi_ch3_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) | (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID2(rbbm_dsply_reg, dmi_ch3_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) | (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_SW_CNTL(rbbm_dsply_reg, dmi_ch3_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) | (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_NUM_BUFS(rbbm_dsply_reg, dmi_ch3_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) | (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID0(rbbm_dsply_reg, dmi_ch4_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) | (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID1(rbbm_dsply_reg, dmi_ch4_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) | (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID2(rbbm_dsply_reg, dmi_ch4_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) | (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_SW_CNTL(rbbm_dsply_reg, dmi_ch4_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) | (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_NUM_BUFS(rbbm_dsply_reg, dmi_ch4_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) | (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int sel_dmi_active_bufid0          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE;
+          unsigned int sel_dmi_active_bufid1          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE;
+          unsigned int sel_dmi_active_bufid2          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE;
+          unsigned int sel_dmi_vsync_valid            : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE;
+          unsigned int dmi_ch1_use_bufid0             : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE;
+          unsigned int dmi_ch1_use_bufid1             : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE;
+          unsigned int dmi_ch1_use_bufid2             : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE;
+          unsigned int dmi_ch1_sw_cntl                : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE;
+          unsigned int dmi_ch1_num_bufs               : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE;
+          unsigned int dmi_ch2_use_bufid0             : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE;
+          unsigned int dmi_ch2_use_bufid1             : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE;
+          unsigned int dmi_ch2_use_bufid2             : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE;
+          unsigned int dmi_ch2_sw_cntl                : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE;
+          unsigned int dmi_ch2_num_bufs               : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE;
+          unsigned int dmi_channel_select             : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE;
+          unsigned int                                : 2;
+          unsigned int dmi_ch3_use_bufid0             : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE;
+          unsigned int dmi_ch3_use_bufid1             : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE;
+          unsigned int dmi_ch3_use_bufid2             : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE;
+          unsigned int dmi_ch3_sw_cntl                : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE;
+          unsigned int dmi_ch3_num_bufs               : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE;
+          unsigned int dmi_ch4_use_bufid0             : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE;
+          unsigned int dmi_ch4_use_bufid1             : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE;
+          unsigned int dmi_ch4_use_bufid2             : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE;
+          unsigned int dmi_ch4_sw_cntl                : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE;
+          unsigned int dmi_ch4_num_bufs               : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE;
+     } rbbm_dsply_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int dmi_ch4_num_bufs               : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE;
+          unsigned int dmi_ch4_sw_cntl                : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE;
+          unsigned int dmi_ch4_use_bufid2             : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE;
+          unsigned int dmi_ch4_use_bufid1             : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE;
+          unsigned int dmi_ch4_use_bufid0             : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE;
+          unsigned int dmi_ch3_num_bufs               : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE;
+          unsigned int dmi_ch3_sw_cntl                : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE;
+          unsigned int dmi_ch3_use_bufid2             : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE;
+          unsigned int dmi_ch3_use_bufid1             : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE;
+          unsigned int dmi_ch3_use_bufid0             : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE;
+          unsigned int                                : 2;
+          unsigned int dmi_channel_select             : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE;
+          unsigned int dmi_ch2_num_bufs               : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE;
+          unsigned int dmi_ch2_sw_cntl                : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE;
+          unsigned int dmi_ch2_use_bufid2             : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE;
+          unsigned int dmi_ch2_use_bufid1             : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE;
+          unsigned int dmi_ch2_use_bufid0             : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE;
+          unsigned int dmi_ch1_num_bufs               : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE;
+          unsigned int dmi_ch1_sw_cntl                : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE;
+          unsigned int dmi_ch1_use_bufid2             : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE;
+          unsigned int dmi_ch1_use_bufid1             : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE;
+          unsigned int dmi_ch1_use_bufid0             : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE;
+          unsigned int sel_dmi_vsync_valid            : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE;
+          unsigned int sel_dmi_active_bufid2          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE;
+          unsigned int sel_dmi_active_bufid1          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE;
+          unsigned int sel_dmi_active_bufid0          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE;
+     } rbbm_dsply_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_dsply_t f;
+} rbbm_dsply_u;
+
+
+/*
+ * RBBM_RENDER_LATEST struct
+ */
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE 2
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT 0
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT 8
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT 16
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT 24
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK 0x00000003
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK 0x00000300
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK 0x00030000
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK 0x03000000
+
+#define RBBM_RENDER_LATEST_MASK \
+     (RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK)
+
+#define RBBM_RENDER_LATEST(dmi_ch1_buffer_id, dmi_ch2_buffer_id, dmi_ch3_buffer_id, dmi_ch4_buffer_id) \
+     ((dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) | \
+      (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) | \
+      (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) | \
+      (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT))
+
+#define RBBM_RENDER_LATEST_GET_DMI_CH1_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH2_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH3_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH4_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)
+
+#define RBBM_RENDER_LATEST_SET_DMI_CH1_BUFFER_ID(rbbm_render_latest_reg, dmi_ch1_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) | (dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH2_BUFFER_ID(rbbm_render_latest_reg, dmi_ch2_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) | (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH3_BUFFER_ID(rbbm_render_latest_reg, dmi_ch3_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) | (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH4_BUFFER_ID(rbbm_render_latest_reg, dmi_ch4_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) | (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int dmi_ch1_buffer_id              : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch2_buffer_id              : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch3_buffer_id              : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch4_buffer_id              : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+     } rbbm_render_latest_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int                                : 6;
+          unsigned int dmi_ch4_buffer_id              : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch3_buffer_id              : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch2_buffer_id              : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch1_buffer_id              : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE;
+     } rbbm_render_latest_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_render_latest_t f;
+} rbbm_render_latest_u;
+
+
+/*
+ * RBBM_RTL_RELEASE struct
+ */
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0
+
+#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff
+
+#define RBBM_RTL_RELEASE_MASK \
+     (RBBM_RTL_RELEASE_CHANGELIST_MASK)
+
+#define RBBM_RTL_RELEASE(changelist) \
+     ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT))
+
+#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \
+     ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \
+     rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_rtl_release_t f;
+} rbbm_rtl_release_u;
+
+
+/*
+ * RBBM_PATCH_RELEASE struct
+ */
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000
+
+#define RBBM_PATCH_RELEASE_MASK \
+     (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \
+      RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \
+      RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK)
+
+#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \
+     ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \
+      (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \
+      (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT))
+
+#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+     } rbbm_patch_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+     } rbbm_patch_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_patch_release_t f;
+} rbbm_patch_release_u;
+
+
+/*
+ * RBBM_AUXILIARY_CONFIG struct
+ */
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff
+
+#define RBBM_AUXILIARY_CONFIG_MASK \
+     (RBBM_AUXILIARY_CONFIG_RESERVED_MASK)
+
+#define RBBM_AUXILIARY_CONFIG(reserved) \
+     ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT))
+
+#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \
+     ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \
+     rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_auxiliary_config_t f;
+} rbbm_auxiliary_config_u;
+
+
+/*
+ * RBBM_PERIPHID0 struct
+ */
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0
+
+#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff
+
+#define RBBM_PERIPHID0_MASK \
+     (RBBM_PERIPHID0_PARTNUMBER0_MASK)
+
+#define RBBM_PERIPHID0(partnumber0) \
+     ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT))
+
+#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \
+     ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \
+     rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int                                : 24;
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+     } rbbm_periphid0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid0_t f;
+} rbbm_periphid0_u;
+
+
+/*
+ * RBBM_PERIPHID1 struct
+ */
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4
+#define RBBM_PERIPHID1_DESIGNER0_SIZE  4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0
+#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f
+#define RBBM_PERIPHID1_DESIGNER0_MASK  0x000000f0
+
+#define RBBM_PERIPHID1_MASK \
+     (RBBM_PERIPHID1_PARTNUMBER1_MASK | \
+      RBBM_PERIPHID1_DESIGNER0_MASK)
+
+#define RBBM_PERIPHID1(partnumber1, designer0) \
+     ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \
+      (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT))
+
+#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int                                : 24;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+     } rbbm_periphid1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid1_t f;
+} rbbm_periphid1_u;
+
+
+/*
+ * RBBM_PERIPHID2 struct
+ */
+
+#define RBBM_PERIPHID2_DESIGNER1_SIZE  4
+#define RBBM_PERIPHID2_REVISION_SIZE   4
+
+#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0
+#define RBBM_PERIPHID2_REVISION_SHIFT  4
+
+#define RBBM_PERIPHID2_DESIGNER1_MASK  0x0000000f
+#define RBBM_PERIPHID2_REVISION_MASK   0x000000f0
+
+#define RBBM_PERIPHID2_MASK \
+     (RBBM_PERIPHID2_DESIGNER1_MASK | \
+      RBBM_PERIPHID2_REVISION_MASK)
+
+#define RBBM_PERIPHID2(designer1, revision) \
+     ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \
+      (revision << RBBM_PERIPHID2_REVISION_SHIFT))
+
+#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT)
+
+#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int                                : 24;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+     } rbbm_periphid2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid2_t f;
+} rbbm_periphid2_u;
+
+
+/*
+ * RBBM_PERIPHID3 struct
+ */
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_CONTINUATION_SIZE 1
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4
+#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c
+#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030
+#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080
+
+#define RBBM_PERIPHID3_MASK \
+     (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \
+      RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \
+      RBBM_PERIPHID3_MH_INTERFACE_MASK | \
+      RBBM_PERIPHID3_CONTINUATION_MASK)
+
+#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \
+     ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \
+      (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \
+      (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \
+      (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT))
+
+#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int                                : 1;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int                                : 24;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+     } rbbm_periphid3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid3_t f;
+} rbbm_periphid3_u;
+
+
+/*
+ * RBBM_CNTL struct
+ */
+
+#define RBBM_CNTL_READ_TIMEOUT_SIZE    8
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9
+
+#define RBBM_CNTL_READ_TIMEOUT_SHIFT   0
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8
+
+#define RBBM_CNTL_READ_TIMEOUT_MASK    0x000000ff
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00
+
+#define RBBM_CNTL_MASK \
+     (RBBM_CNTL_READ_TIMEOUT_MASK | \
+      RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK)
+
+#define RBBM_CNTL(read_timeout, regclk_deassert_time) \
+     ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \
+      (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT))
+
+#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int                                : 15;
+     } rbbm_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int                                : 15;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+     } rbbm_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_cntl_t f;
+} rbbm_cntl_u;
+
+
+/*
+ * RBBM_SKEW_CNTL struct
+ */
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f
+#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0
+
+#define RBBM_SKEW_CNTL_MASK \
+     (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \
+      RBBM_SKEW_CNTL_SKEW_COUNT_MASK)
+
+#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \
+     ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \
+      (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT))
+
+#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int                                : 22;
+     } rbbm_skew_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int                                : 22;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+     } rbbm_skew_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_skew_cntl_t f;
+} rbbm_skew_cntl_u;
+
+
+/*
+ * RBBM_SOFT_RESET struct
+ */
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000
+
+#define RBBM_SOFT_RESET_MASK \
+     (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK)
+
+#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \
+     ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \
+      (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \
+      (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \
+      (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \
+      (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \
+      (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \
+      (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \
+      (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \
+      (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT))
+
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int                                : 15;
+     } rbbm_soft_reset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int                                : 15;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+     } rbbm_soft_reset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_soft_reset_t f;
+} rbbm_soft_reset_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE1 struct
+ */
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000
+
+#define RBBM_PM_OVERRIDE1_MASK \
+     (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \
+     ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override1_t f;
+} rbbm_pm_override1_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE2 struct
+ */
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800
+
+#define RBBM_PM_OVERRIDE2_MASK \
+     (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \
+     ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \
+      (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \
+      (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int                                : 20;
+     } rbbm_pm_override2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int                                : 20;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override2_t f;
+} rbbm_pm_override2_u;
+
+
+/*
+ * GC_SYS_IDLE struct
+ */
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE 6
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT 16
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT 24
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT 25
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT 29
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT 30
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK 0x01000000
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK 0x02000000
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000
+
+#define GC_SYS_IDLE_MASK \
+     (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK | \
+      GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK | \
+      GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK | \
+      GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK)
+
+#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_wait_dmi_mask, gc_sys_urgent_ramp, gc_sys_wait_dmi, gc_sys_urgent_ramp_override, gc_sys_wait_dmi_override, gc_sys_idle_override) \
+     ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \
+      (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) | \
+      (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) | \
+      (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) | \
+      (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) | \
+      (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) | \
+      (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT))
+
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle_reg, gc_sys_wait_dmi_mask) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) | (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP(gc_sys_idle_reg, gc_sys_urgent_ramp) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) | (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI(gc_sys_idle_reg, gc_sys_wait_dmi) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) | (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle_reg, gc_sys_urgent_ramp_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) | (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle_reg, gc_sys_wait_dmi_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) | (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+          unsigned int gc_sys_wait_dmi_mask           : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE;
+          unsigned int                                : 2;
+          unsigned int gc_sys_urgent_ramp             : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE;
+          unsigned int gc_sys_wait_dmi                : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE;
+          unsigned int                                : 3;
+          unsigned int gc_sys_urgent_ramp_override    : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE;
+          unsigned int gc_sys_wait_dmi_override       : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE;
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+     } gc_sys_idle_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+          unsigned int gc_sys_wait_dmi_override       : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE;
+          unsigned int gc_sys_urgent_ramp_override    : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE;
+          unsigned int                                : 3;
+          unsigned int gc_sys_wait_dmi                : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE;
+          unsigned int gc_sys_urgent_ramp             : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE;
+          unsigned int                                : 2;
+          unsigned int gc_sys_wait_dmi_mask           : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE;
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+     } gc_sys_idle_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gc_sys_idle_t f;
+} gc_sys_idle_u;
+
+
+/*
+ * NQWAIT_UNTIL struct
+ */
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001
+
+#define NQWAIT_UNTIL_MASK \
+     (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK)
+
+#define NQWAIT_UNTIL(wait_gui_idle) \
+     ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT))
+
+#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \
+     ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \
+     nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+          unsigned int                                : 31;
+     } nqwait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int                                : 31;
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+     } nqwait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     nqwait_until_t f;
+} nqwait_until_u;
+
+
+/*
+ * RBBM_DEBUG_OUT struct
+ */
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE 32
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT 0
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK 0xffffffff
+
+#define RBBM_DEBUG_OUT_MASK \
+     (RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK)
+
+#define RBBM_DEBUG_OUT(debug_bus_out) \
+     ((debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT))
+
+#define RBBM_DEBUG_OUT_GET_DEBUG_BUS_OUT(rbbm_debug_out) \
+     ((rbbm_debug_out & RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) >> RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)
+
+#define RBBM_DEBUG_OUT_SET_DEBUG_BUS_OUT(rbbm_debug_out_reg, debug_bus_out) \
+     rbbm_debug_out_reg = (rbbm_debug_out_reg & ~RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) | (debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_out_t {
+          unsigned int debug_bus_out                  : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE;
+     } rbbm_debug_out_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_out_t {
+          unsigned int debug_bus_out                  : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE;
+     } rbbm_debug_out_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_out_t f;
+} rbbm_debug_out_u;
+
+
+/*
+ * RBBM_DEBUG_CNTL struct
+ */
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE 6
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE 4
+#define RBBM_DEBUG_CNTL_SW_ENABLE_SIZE 1
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE 6
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE 4
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE 4
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT 0
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT 8
+#define RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT 12
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT 16
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT 24
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT 28
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK 0x0000003f
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK 0x00000f00
+#define RBBM_DEBUG_CNTL_SW_ENABLE_MASK 0x00001000
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK 0x0f000000
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK 0xf0000000
+
+#define RBBM_DEBUG_CNTL_MASK \
+     (RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK | \
+      RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK | \
+      RBBM_DEBUG_CNTL_SW_ENABLE_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK)
+
+#define RBBM_DEBUG_CNTL(sub_block_addr, sub_block_sel, sw_enable, gpio_sub_block_addr, gpio_sub_block_sel, gpio_byte_lane_enb) \
+     ((sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) | \
+      (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) | \
+      (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) | \
+      (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) | \
+      (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) | \
+      (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT))
+
+#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_ADDR(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_SEL(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_SW_ENABLE(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SW_ENABLE_MASK) >> RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) >> RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)
+
+#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, sub_block_addr) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) | (sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, sub_block_sel) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) | (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_SW_ENABLE(rbbm_debug_cntl_reg, sw_enable) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SW_ENABLE_MASK) | (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, gpio_sub_block_addr) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) | (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, gpio_sub_block_sel) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) | (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl_reg, gpio_byte_lane_enb) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) | (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_cntl_t {
+          unsigned int sub_block_addr                 : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 2;
+          unsigned int sub_block_sel                  : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE;
+          unsigned int sw_enable                      : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int gpio_sub_block_addr            : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 2;
+          unsigned int gpio_sub_block_sel             : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE;
+          unsigned int gpio_byte_lane_enb             : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE;
+     } rbbm_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_cntl_t {
+          unsigned int gpio_byte_lane_enb             : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE;
+          unsigned int gpio_sub_block_sel             : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE;
+          unsigned int                                : 2;
+          unsigned int gpio_sub_block_addr            : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_enable                      : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE;
+          unsigned int sub_block_sel                  : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE;
+          unsigned int                                : 2;
+          unsigned int sub_block_addr                 : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE;
+     } rbbm_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_cntl_t f;
+} rbbm_debug_cntl_u;
+
+
+/*
+ * RBBM_DEBUG struct
+ */
+
+#define RBBM_DEBUG_IGNORE_RTR_SIZE     1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1
+
+#define RBBM_DEBUG_IGNORE_RTR_SHIFT    1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31
+
+#define RBBM_DEBUG_IGNORE_RTR_MASK     0x00000002
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000
+
+#define RBBM_DEBUG_MASK \
+     (RBBM_DEBUG_IGNORE_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \
+      RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \
+      RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK)
+
+#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \
+     ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \
+      (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \
+      (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \
+      (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \
+      (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \
+      (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \
+      (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \
+      (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \
+      (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \
+      (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \
+      (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \
+      (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT))
+
+#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int                                : 1;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int                                : 3;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 4;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+     } rbbm_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+          unsigned int                                : 6;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int                                : 4;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 3;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int                                : 1;
+     } rbbm_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_t f;
+} rbbm_debug_u;
+
+
+/*
+ * RBBM_READ_ERROR struct
+ */
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15
+#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1
+#define RBBM_READ_ERROR_READ_ERROR_SIZE 1
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2
+#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30
+#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31
+
+#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc
+#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000
+#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000
+
+#define RBBM_READ_ERROR_MASK \
+     (RBBM_READ_ERROR_READ_ADDRESS_MASK | \
+      RBBM_READ_ERROR_READ_REQUESTER_MASK | \
+      RBBM_READ_ERROR_READ_ERROR_MASK)
+
+#define RBBM_READ_ERROR(read_address, read_requester, read_error) \
+     ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \
+      (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \
+      (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT))
+
+#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int                                : 2;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+     } rbbm_read_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 2;
+     } rbbm_read_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_read_error_t f;
+} rbbm_read_error_u;
+
+
+/*
+ * RBBM_WAIT_IDLE_CLOCKS struct
+ */
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff
+
+#define RBBM_WAIT_IDLE_CLOCKS_MASK \
+     (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK)
+
+#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \
+     ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT))
+
+#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \
+     ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \
+     rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+          unsigned int                                : 24;
+     } rbbm_wait_idle_clocks_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int                                : 24;
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+     } rbbm_wait_idle_clocks_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_wait_idle_clocks_t f;
+} rbbm_wait_idle_clocks_u;
+
+
+/*
+ * RBBM_INT_CNTL struct
+ */
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000
+
+#define RBBM_INT_CNTL_MASK \
+     (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \
+      RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \
+      RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK)
+
+#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \
+     ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \
+      (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \
+      (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT))
+
+#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+     } rbbm_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_cntl_t f;
+} rbbm_int_cntl_u;
+
+
+/*
+ * RBBM_INT_STATUS struct
+ */
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000
+
+#define RBBM_INT_STATUS_MASK \
+     (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \
+      RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \
+      RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK)
+
+#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \
+     ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \
+      (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \
+      (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT))
+
+#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+     } rbbm_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_status_t f;
+} rbbm_int_status_u;
+
+
+/*
+ * RBBM_INT_ACK struct
+ */
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000
+
+#define RBBM_INT_ACK_MASK \
+     (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \
+      RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \
+      RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK)
+
+#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \
+     ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \
+      (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \
+      (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT))
+
+#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+     } rbbm_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_ack_t f;
+} rbbm_int_ack_u;
+
+
+/*
+ * MASTER_INT_SIGNAL struct
+ */
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT 26
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_MASK 0x04000000
+#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000
+
+#define MASTER_INT_SIGNAL_MASK \
+     (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_SQ_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK)
+
+#define MASTER_INT_SIGNAL(mh_int_stat, sq_int_stat, cp_int_stat, rbbm_int_stat) \
+     ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \
+      (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) | \
+      (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \
+      (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT))
+
+#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_SQ_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) >> MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_SQ_INT_STAT(master_int_signal_reg, sq_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) | (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int                                : 5;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 20;
+          unsigned int sq_int_stat                    : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+     } master_int_signal_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sq_int_stat                    : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE;
+          unsigned int                                : 20;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 5;
+     } master_int_signal_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     master_int_signal_t f;
+} master_int_signal_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_SELECT struct
+ */
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f
+
+#define RBBM_PERFCOUNTER1_SELECT_MASK \
+     (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK)
+
+#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \
+     ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT))
+
+#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \
+     ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \
+     rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+          unsigned int                                : 26;
+     } rbbm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int                                : 26;
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+     } rbbm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_select_t f;
+} rbbm_perfcounter1_select_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_LO struct
+ */
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff
+
+#define RBBM_PERFCOUNTER1_LO_MASK \
+     (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK)
+
+#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \
+     ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT))
+
+#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \
+     ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \
+     rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_lo_t f;
+} rbbm_perfcounter1_lo_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_HI struct
+ */
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff
+
+#define RBBM_PERFCOUNTER1_HI_MASK \
+     (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK)
+
+#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \
+     ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT))
+
+#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \
+     ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \
+     rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+          unsigned int                                : 16;
+     } rbbm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+     } rbbm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_hi_t f;
+} rbbm_perfcounter1_hi_u;
+
+
+#endif
+
+
+#if !defined (_MH_FIDDLE_H)
+#define _MH_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  mh_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * MH_ARBITER_CONFIG struct
+ */
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE 1
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT 26
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200
+#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK 0x04000000
+
+#define MH_ARBITER_CONFIG_MASK \
+     (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \
+      MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \
+      MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK)
+
+#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable, pa_clnt_enable) \
+     ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \
+      (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \
+      (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \
+      (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \
+      (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \
+      (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \
+      (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \
+      (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \
+      (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \
+      (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \
+      (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \
+      (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \
+      (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) | \
+      (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT))
+
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PA_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)
+
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PA_CLNT_ENABLE(mh_arbiter_config_reg, pa_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) | (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int pa_clnt_enable                 : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE;
+          unsigned int                                : 5;
+     } mh_arbiter_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int                                : 5;
+          unsigned int pa_clnt_enable                 : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+     } mh_arbiter_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_arbiter_config_t f;
+} mh_arbiter_config_u;
+
+
+/*
+ * MH_CLNT_AXI_ID_REUSE struct
+ */
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE 3
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT 11
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT 12
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK 0x00000800
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK 0x00007000
+
+#define MH_CLNT_AXI_ID_REUSE_MASK \
+     (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \
+      MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK | \
+      MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK)
+
+#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id, reserved3, paw_id) \
+     ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \
+      (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \
+      (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \
+      (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \
+      (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) | \
+      (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) | \
+      (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT))
+
+#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED3(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_PAw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)
+
+#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED3(mh_clnt_axi_id_reuse_reg, reserved3) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) | (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_PAw_ID(mh_clnt_axi_id_reuse_reg, paw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) | (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved3                      : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE;
+          unsigned int paw_id                         : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE;
+          unsigned int                                : 17;
+     } mh_clnt_axi_id_reuse_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int                                : 17;
+          unsigned int paw_id                         : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE;
+          unsigned int reserved3                      : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+     } mh_clnt_axi_id_reuse_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_clnt_axi_id_reuse_t f;
+} mh_clnt_axi_id_reuse_u;
+
+
+/*
+ * MH_INTERRUPT_MASK struct
+ */
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_MASK_MASK \
+     (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_mask_t f;
+} mh_interrupt_mask_u;
+
+
+/*
+ * MH_INTERRUPT_STATUS struct
+ */
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_STATUS_MASK \
+     (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_status_t f;
+} mh_interrupt_status_u;
+
+
+/*
+ * MH_INTERRUPT_CLEAR struct
+ */
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_CLEAR_MASK \
+     (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_clear_t f;
+} mh_interrupt_clear_u;
+
+
+/*
+ * MH_AXI_ERROR struct
+ */
+
+#define MH_AXI_ERROR_AXI_READ_ID_SIZE  3
+#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1
+#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1
+
+#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0
+#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3
+#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7
+
+#define MH_AXI_ERROR_AXI_READ_ID_MASK  0x00000007
+#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008
+#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080
+
+#define MH_AXI_ERROR_MASK \
+     (MH_AXI_ERROR_AXI_READ_ID_MASK | \
+      MH_AXI_ERROR_AXI_READ_ERROR_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ID_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ERROR_MASK)
+
+#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \
+     ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \
+      (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \
+      (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT))
+
+#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int                                : 24;
+     } mh_axi_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int                                : 24;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+     } mh_axi_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_error_t f;
+} mh_axi_error_u;
+
+
+/*
+ * MH_PERFCOUNTER0_SELECT struct
+ */
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_SELECT_MASK \
+     (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \
+     ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \
+     mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_select_t f;
+} mh_perfcounter0_select_u;
+
+
+/*
+ * MH_PERFCOUNTER1_SELECT struct
+ */
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_SELECT_MASK \
+     (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \
+     ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \
+     mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_select_t f;
+} mh_perfcounter1_select_u;
+
+
+/*
+ * MH_PERFCOUNTER0_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_CONFIG_MASK \
+     (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER0_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \
+     ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \
+     mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter0_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_config_t f;
+} mh_perfcounter0_config_u;
+
+
+/*
+ * MH_PERFCOUNTER1_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_CONFIG_MASK \
+     (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER1_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \
+     ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \
+     mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter1_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_config_t f;
+} mh_perfcounter1_config_u;
+
+
+/*
+ * MH_PERFCOUNTER0_LOW struct
+ */
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER0_LOW_MASK \
+     (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER0_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \
+     ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \
+     mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_low_t f;
+} mh_perfcounter0_low_u;
+
+
+/*
+ * MH_PERFCOUNTER1_LOW struct
+ */
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER1_LOW_MASK \
+     (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER1_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \
+     ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \
+     mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_low_t f;
+} mh_perfcounter1_low_u;
+
+
+/*
+ * MH_PERFCOUNTER0_HI struct
+ */
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER0_HI_MASK \
+     (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER0_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \
+     ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \
+     mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_hi_t f;
+} mh_perfcounter0_hi_u;
+
+
+/*
+ * MH_PERFCOUNTER1_HI struct
+ */
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER1_HI_MASK \
+     (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER1_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \
+     ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \
+     mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_hi_t f;
+} mh_perfcounter1_hi_u;
+
+
+/*
+ * MH_DEBUG_CTRL struct
+ */
+
+#define MH_DEBUG_CTRL_INDEX_SIZE       6
+
+#define MH_DEBUG_CTRL_INDEX_SHIFT      0
+
+#define MH_DEBUG_CTRL_INDEX_MASK       0x0000003f
+
+#define MH_DEBUG_CTRL_MASK \
+     (MH_DEBUG_CTRL_INDEX_MASK)
+
+#define MH_DEBUG_CTRL(index) \
+     ((index << MH_DEBUG_CTRL_INDEX_SHIFT))
+
+#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \
+     ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \
+     mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+          unsigned int                                : 26;
+     } mh_debug_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int                                : 26;
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+     } mh_debug_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_ctrl_t f;
+} mh_debug_ctrl_u;
+
+
+/*
+ * MH_DEBUG_DATA struct
+ */
+
+#define MH_DEBUG_DATA_DATA_SIZE        32
+
+#define MH_DEBUG_DATA_DATA_SHIFT       0
+
+#define MH_DEBUG_DATA_DATA_MASK        0xffffffff
+
+#define MH_DEBUG_DATA_MASK \
+     (MH_DEBUG_DATA_DATA_MASK)
+
+#define MH_DEBUG_DATA(data) \
+     ((data << MH_DEBUG_DATA_DATA_SHIFT))
+
+#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \
+     ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT)
+
+#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \
+     mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_data_t f;
+} mh_debug_data_u;
+
+
+/*
+ * MH_AXI_HALT_CONTROL struct
+ */
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_SIZE 1
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT 0
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_MASK 0x00000001
+
+#define MH_AXI_HALT_CONTROL_MASK \
+     (MH_AXI_HALT_CONTROL_AXI_HALT_MASK)
+
+#define MH_AXI_HALT_CONTROL(axi_halt) \
+     ((axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT))
+
+#define MH_AXI_HALT_CONTROL_GET_AXI_HALT(mh_axi_halt_control) \
+     ((mh_axi_halt_control & MH_AXI_HALT_CONTROL_AXI_HALT_MASK) >> MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)
+
+#define MH_AXI_HALT_CONTROL_SET_AXI_HALT(mh_axi_halt_control_reg, axi_halt) \
+     mh_axi_halt_control_reg = (mh_axi_halt_control_reg & ~MH_AXI_HALT_CONTROL_AXI_HALT_MASK) | (axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_halt_control_t {
+          unsigned int axi_halt                       : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE;
+          unsigned int                                : 31;
+     } mh_axi_halt_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_halt_control_t {
+          unsigned int                                : 31;
+          unsigned int axi_halt                       : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE;
+     } mh_axi_halt_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_halt_control_t f;
+} mh_axi_halt_control_u;
+
+
+/*
+ * MH_DEBUG_REG00 struct
+ */
+
+#define MH_DEBUG_REG00_MH_BUSY_SIZE    1
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1
+#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1
+#define MH_DEBUG_REG00_TCD_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_TCD_FULL_SIZE   1
+#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_PA_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1
+#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_ARQ_FULL_SIZE   1
+#define MH_DEBUG_REG00_WDB_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_WDB_FULL_SIZE   1
+#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1
+#define MH_DEBUG_REG00_AXI_RDY_ENA_SIZE 1
+
+#define MH_DEBUG_REG00_MH_BUSY_SHIFT   0
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1
+#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2
+#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3
+#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5
+#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6
+#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7
+#define MH_DEBUG_REG00_TCD_FULL_SHIFT  8
+#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9
+#define MH_DEBUG_REG00_PA_REQUEST_SHIFT 10
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 11
+#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 12
+#define MH_DEBUG_REG00_ARQ_FULL_SHIFT  13
+#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 14
+#define MH_DEBUG_REG00_WDB_FULL_SHIFT  15
+#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 16
+#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 17
+#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 18
+#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 19
+#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 20
+#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 21
+#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 22
+#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 23
+#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 24
+#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 25
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 26
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 27
+#define MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT 28
+
+#define MH_DEBUG_REG00_MH_BUSY_MASK    0x00000001
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002
+#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004
+#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008
+#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020
+#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040
+#define MH_DEBUG_REG00_TCD_EMPTY_MASK  0x00000080
+#define MH_DEBUG_REG00_TCD_FULL_MASK   0x00000100
+#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200
+#define MH_DEBUG_REG00_PA_REQUEST_MASK 0x00000400
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000800
+#define MH_DEBUG_REG00_ARQ_EMPTY_MASK  0x00001000
+#define MH_DEBUG_REG00_ARQ_FULL_MASK   0x00002000
+#define MH_DEBUG_REG00_WDB_EMPTY_MASK  0x00004000
+#define MH_DEBUG_REG00_WDB_FULL_MASK   0x00008000
+#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00010000
+#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00020000
+#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00040000
+#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00080000
+#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00100000
+#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00200000
+#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00400000
+#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00800000
+#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x01000000
+#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x02000000
+#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x04000000
+#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x08000000
+#define MH_DEBUG_REG00_AXI_RDY_ENA_MASK 0x10000000
+
+#define MH_DEBUG_REG00_MASK \
+     (MH_DEBUG_REG00_MH_BUSY_MASK | \
+      MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \
+      MH_DEBUG_REG00_CP_REQUEST_MASK | \
+      MH_DEBUG_REG00_VGT_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \
+      MH_DEBUG_REG00_TC_CAM_FULL_MASK | \
+      MH_DEBUG_REG00_TCD_EMPTY_MASK | \
+      MH_DEBUG_REG00_TCD_FULL_MASK | \
+      MH_DEBUG_REG00_RB_REQUEST_MASK | \
+      MH_DEBUG_REG00_PA_REQUEST_MASK | \
+      MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \
+      MH_DEBUG_REG00_ARQ_EMPTY_MASK | \
+      MH_DEBUG_REG00_ARQ_FULL_MASK | \
+      MH_DEBUG_REG00_WDB_EMPTY_MASK | \
+      MH_DEBUG_REG00_WDB_FULL_MASK | \
+      MH_DEBUG_REG00_AXI_AVALID_MASK | \
+      MH_DEBUG_REG00_AXI_AREADY_MASK | \
+      MH_DEBUG_REG00_AXI_ARVALID_MASK | \
+      MH_DEBUG_REG00_AXI_ARREADY_MASK | \
+      MH_DEBUG_REG00_AXI_WVALID_MASK | \
+      MH_DEBUG_REG00_AXI_WREADY_MASK | \
+      MH_DEBUG_REG00_AXI_RVALID_MASK | \
+      MH_DEBUG_REG00_AXI_RREADY_MASK | \
+      MH_DEBUG_REG00_AXI_BVALID_MASK | \
+      MH_DEBUG_REG00_AXI_BREADY_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_ACK_MASK | \
+      MH_DEBUG_REG00_AXI_RDY_ENA_MASK)
+
+#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, pa_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack, axi_rdy_ena) \
+     ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \
+      (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \
+      (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \
+      (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \
+      (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \
+      (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \
+      (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \
+      (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \
+      (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \
+      (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \
+      (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) | \
+      (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \
+      (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \
+      (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \
+      (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \
+      (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \
+      (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \
+      (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \
+      (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \
+      (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \
+      (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \
+      (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \
+      (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \
+      (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \
+      (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \
+      (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \
+      (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \
+      (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) | \
+      (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT))
+
+#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_PA_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_PA_REQUEST_MASK) >> MH_DEBUG_REG00_PA_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RDY_ENA(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)
+
+#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_PA_REQUEST(mh_debug_reg00_reg, pa_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_PA_REQUEST_MASK) | (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RDY_ENA(mh_debug_reg00_reg, axi_rdy_ena) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int pa_request                     : MH_DEBUG_REG00_PA_REQUEST_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int                                : 3;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int pa_request                     : MH_DEBUG_REG00_PA_REQUEST_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+     } mh_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg00_t f;
+} mh_debug_reg00_u;
+
+
+/*
+ * MH_DEBUG_REG01 struct
+ */
+
+#define MH_DEBUG_REG01_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1
+#define MH_DEBUG_REG01_CP_TAG_q_SIZE   3
+#define MH_DEBUG_REG01_CP_BLEN_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_TAG_q_SIZE  1
+#define MH_DEBUG_REG01_TC_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_TC_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_TC_BLEN_q_SIZE  1
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG01_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG01_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_PA_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_PA_RTR_q_SIZE   1
+
+#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0
+#define MH_DEBUG_REG01_CP_RTR_q_SHIFT  1
+#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2
+#define MH_DEBUG_REG01_CP_TAG_q_SHIFT  3
+#define MH_DEBUG_REG01_CP_BLEN_q_SHIFT 6
+#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 7
+#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 8
+#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 9
+#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 10
+#define MH_DEBUG_REG01_TC_RTR_q_SHIFT  11
+#define MH_DEBUG_REG01_TC_BLEN_q_SHIFT 12
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 13
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 14
+#define MH_DEBUG_REG01_TC_MH_written_SHIFT 15
+#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 16
+#define MH_DEBUG_REG01_RB_RTR_q_SHIFT  17
+#define MH_DEBUG_REG01_PA_SEND_q_SHIFT 18
+#define MH_DEBUG_REG01_PA_RTR_q_SHIFT  19
+
+#define MH_DEBUG_REG01_CP_SEND_q_MASK  0x00000001
+#define MH_DEBUG_REG01_CP_RTR_q_MASK   0x00000002
+#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004
+#define MH_DEBUG_REG01_CP_TAG_q_MASK   0x00000038
+#define MH_DEBUG_REG01_CP_BLEN_q_MASK  0x00000040
+#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00000080
+#define MH_DEBUG_REG01_VGT_RTR_q_MASK  0x00000100
+#define MH_DEBUG_REG01_VGT_TAG_q_MASK  0x00000200
+#define MH_DEBUG_REG01_TC_SEND_q_MASK  0x00000400
+#define MH_DEBUG_REG01_TC_RTR_q_MASK   0x00000800
+#define MH_DEBUG_REG01_TC_BLEN_q_MASK  0x00001000
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00002000
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00004000
+#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00008000
+#define MH_DEBUG_REG01_RB_SEND_q_MASK  0x00010000
+#define MH_DEBUG_REG01_RB_RTR_q_MASK   0x00020000
+#define MH_DEBUG_REG01_PA_SEND_q_MASK  0x00040000
+#define MH_DEBUG_REG01_PA_RTR_q_MASK   0x00080000
+
+#define MH_DEBUG_REG01_MASK \
+     (MH_DEBUG_REG01_CP_SEND_q_MASK | \
+      MH_DEBUG_REG01_CP_RTR_q_MASK | \
+      MH_DEBUG_REG01_CP_WRITE_q_MASK | \
+      MH_DEBUG_REG01_CP_TAG_q_MASK | \
+      MH_DEBUG_REG01_CP_BLEN_q_MASK | \
+      MH_DEBUG_REG01_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG01_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG01_VGT_TAG_q_MASK | \
+      MH_DEBUG_REG01_TC_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_BLEN_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_MH_written_MASK | \
+      MH_DEBUG_REG01_RB_SEND_q_MASK | \
+      MH_DEBUG_REG01_RB_RTR_q_MASK | \
+      MH_DEBUG_REG01_PA_SEND_q_MASK | \
+      MH_DEBUG_REG01_PA_RTR_q_MASK)
+
+#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_blen_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_blen_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q) \
+     ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \
+      (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \
+      (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \
+      (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \
+      (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \
+      (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \
+      (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \
+      (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \
+      (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) | \
+      (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT))
+
+#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_BLEN_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BLEN_q_MASK) >> MH_DEBUG_REG01_CP_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_BLEN_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_BLEN_q_MASK) >> MH_DEBUG_REG01_TC_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_PA_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_PA_SEND_q_MASK) >> MH_DEBUG_REG01_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_PA_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_PA_RTR_q_MASK) >> MH_DEBUG_REG01_PA_RTR_q_SHIFT)
+
+#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_BLEN_q(mh_debug_reg01_reg, cp_blen_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BLEN_q_MASK) | (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_BLEN_q(mh_debug_reg01_reg, tc_blen_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_BLEN_q_MASK) | (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_PA_SEND_q(mh_debug_reg01_reg, pa_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_PA_RTR_q(mh_debug_reg01_reg, pa_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_blen_q                      : MH_DEBUG_REG01_CP_BLEN_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_blen_q                      : MH_DEBUG_REG01_TC_BLEN_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG01_PA_SEND_q_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG01_PA_RTR_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int                                : 12;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG01_PA_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG01_PA_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_blen_q                      : MH_DEBUG_REG01_TC_BLEN_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int cp_blen_q                      : MH_DEBUG_REG01_CP_BLEN_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+     } mh_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg01_t f;
+} mh_debug_reg01_u;
+
+
+/*
+ * MH_DEBUG_REG02 struct
+ */
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3
+#define MH_DEBUG_REG02_RDC_RID_SIZE    3
+#define MH_DEBUG_REG02_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_PA_writeclean_SIZE 1
+#define MH_DEBUG_REG02_BRC_BID_SIZE    3
+#define MH_DEBUG_REG02_BRC_BRESP_SIZE  2
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3
+#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4
+#define MH_DEBUG_REG02_RDC_RID_SHIFT   7
+#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12
+#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13
+#define MH_DEBUG_REG02_MH_PA_writeclean_SHIFT 14
+#define MH_DEBUG_REG02_BRC_BID_SHIFT   15
+#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 18
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008
+#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070
+#define MH_DEBUG_REG02_RDC_RID_MASK    0x00000380
+#define MH_DEBUG_REG02_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000
+#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000
+#define MH_DEBUG_REG02_MH_PA_writeclean_MASK 0x00004000
+#define MH_DEBUG_REG02_BRC_BID_MASK    0x00038000
+#define MH_DEBUG_REG02_BRC_BRESP_MASK  0x000c0000
+
+#define MH_DEBUG_REG02_MASK \
+     (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_tag_MASK | \
+      MH_DEBUG_REG02_RDC_RID_MASK | \
+      MH_DEBUG_REG02_RDC_RRESP_MASK | \
+      MH_DEBUG_REG02_MH_CP_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_RB_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_PA_writeclean_MASK | \
+      MH_DEBUG_REG02_BRC_BID_MASK | \
+      MH_DEBUG_REG02_BRC_BRESP_MASK)
+
+#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, mh_pa_writeclean, brc_bid, brc_bresp) \
+     ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \
+      (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \
+      (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \
+      (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \
+      (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \
+      (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) | \
+      (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \
+      (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT))
+
+#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_PA_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_PA_writeclean_MASK) >> MH_DEBUG_REG02_MH_PA_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_PA_writeclean(mh_debug_reg02_reg, mh_pa_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_PA_writeclean_MASK) | (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_pa_writeclean               : MH_DEBUG_REG02_MH_PA_writeclean_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int                                : 12;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int mh_pa_writeclean               : MH_DEBUG_REG02_MH_PA_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+     } mh_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg02_t f;
+} mh_debug_reg02_u;
+
+
+/*
+ * MH_DEBUG_REG03 struct
+ */
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG03_MASK \
+     (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK)
+
+#define MH_DEBUG_REG03(mh_clnt_data_31_0) \
+     ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \
+     ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \
+     mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg03_t f;
+} mh_debug_reg03_u;
+
+
+/*
+ * MH_DEBUG_REG04 struct
+ */
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG04_MASK \
+     (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK)
+
+#define MH_DEBUG_REG04(mh_clnt_data_63_32) \
+     ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \
+     ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \
+     mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg04_t f;
+} mh_debug_reg04_u;
+
+
+/*
+ * MH_DEBUG_REG05 struct
+ */
+
+#define MH_DEBUG_REG05_CP_MH_send_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_tag_SIZE  3
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0
+#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1
+#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002
+#define MH_DEBUG_REG05_CP_MH_tag_MASK  0x0000001c
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG05_MASK \
+     (MH_DEBUG_REG05_CP_MH_send_MASK | \
+      MH_DEBUG_REG05_CP_MH_write_MASK | \
+      MH_DEBUG_REG05_CP_MH_tag_MASK | \
+      MH_DEBUG_REG05_CP_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \
+     ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \
+      (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \
+      (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+     } mh_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+     } mh_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg05_t f;
+} mh_debug_reg05_u;
+
+
+/*
+ * MH_DEBUG_REG06 struct
+ */
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG06_MASK \
+     (MH_DEBUG_REG06_CP_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG06(cp_mh_data_31_0) \
+     ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \
+     ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \
+     mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg06_t f;
+} mh_debug_reg06_u;
+
+
+/*
+ * MH_DEBUG_REG07 struct
+ */
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG07_MASK \
+     (MH_DEBUG_REG07_CP_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG07(cp_mh_data_63_32) \
+     ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \
+     ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \
+     mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg07_t f;
+} mh_debug_reg07_u;
+
+
+/*
+ * MH_DEBUG_REG08 struct
+ */
+
+#define MH_DEBUG_REG08_CP_MH_be_SIZE   8
+#define MH_DEBUG_REG08_RB_MH_be_SIZE   8
+#define MH_DEBUG_REG08_PA_MH_be_SIZE   8
+
+#define MH_DEBUG_REG08_CP_MH_be_SHIFT  0
+#define MH_DEBUG_REG08_RB_MH_be_SHIFT  8
+#define MH_DEBUG_REG08_PA_MH_be_SHIFT  16
+
+#define MH_DEBUG_REG08_CP_MH_be_MASK   0x000000ff
+#define MH_DEBUG_REG08_RB_MH_be_MASK   0x0000ff00
+#define MH_DEBUG_REG08_PA_MH_be_MASK   0x00ff0000
+
+#define MH_DEBUG_REG08_MASK \
+     (MH_DEBUG_REG08_CP_MH_be_MASK | \
+      MH_DEBUG_REG08_RB_MH_be_MASK | \
+      MH_DEBUG_REG08_PA_MH_be_MASK)
+
+#define MH_DEBUG_REG08(cp_mh_be, rb_mh_be, pa_mh_be) \
+     ((cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) | \
+      (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) | \
+      (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT))
+
+#define MH_DEBUG_REG08_GET_CP_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_CP_MH_be_MASK) >> MH_DEBUG_REG08_CP_MH_be_SHIFT)
+#define MH_DEBUG_REG08_GET_RB_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_RB_MH_be_MASK) >> MH_DEBUG_REG08_RB_MH_be_SHIFT)
+#define MH_DEBUG_REG08_GET_PA_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_PA_MH_be_MASK) >> MH_DEBUG_REG08_PA_MH_be_SHIFT)
+
+#define MH_DEBUG_REG08_SET_CP_MH_be(mh_debug_reg08_reg, cp_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_CP_MH_be_MASK) | (cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT)
+#define MH_DEBUG_REG08_SET_RB_MH_be(mh_debug_reg08_reg, rb_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_RB_MH_be_MASK) | (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT)
+#define MH_DEBUG_REG08_SET_PA_MH_be(mh_debug_reg08_reg, pa_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_PA_MH_be_MASK) | (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int cp_mh_be                       : MH_DEBUG_REG08_CP_MH_be_SIZE;
+          unsigned int rb_mh_be                       : MH_DEBUG_REG08_RB_MH_be_SIZE;
+          unsigned int pa_mh_be                       : MH_DEBUG_REG08_PA_MH_be_SIZE;
+          unsigned int                                : 8;
+     } mh_debug_reg08_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int                                : 8;
+          unsigned int pa_mh_be                       : MH_DEBUG_REG08_PA_MH_be_SIZE;
+          unsigned int rb_mh_be                       : MH_DEBUG_REG08_RB_MH_be_SIZE;
+          unsigned int cp_mh_be                       : MH_DEBUG_REG08_CP_MH_be_SIZE;
+     } mh_debug_reg08_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg08_t f;
+} mh_debug_reg08_u;
+
+
+/*
+ * MH_DEBUG_REG09 struct
+ */
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 3
+#define MH_DEBUG_REG09_VGT_MH_send_SIZE 1
+#define MH_DEBUG_REG09_VGT_MH_tagbe_SIZE 1
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG09_VGT_MH_send_SHIFT 3
+#define MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT 4
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000007
+#define MH_DEBUG_REG09_VGT_MH_send_MASK 0x00000008
+#define MH_DEBUG_REG09_VGT_MH_tagbe_MASK 0x00000010
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG09_MASK \
+     (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG09_VGT_MH_send_MASK | \
+      MH_DEBUG_REG09_VGT_MH_tagbe_MASK | \
+      MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG09(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \
+     ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \
+      (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) | \
+      (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) | \
+      (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_send(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_send_MASK) >> MH_DEBUG_REG09_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_tagbe(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_ad_31_5(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_send(mh_debug_reg09_reg, vgt_mh_send) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_tagbe(mh_debug_reg09_reg, vgt_mh_tagbe) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_ad_31_5(mh_debug_reg09_reg, vgt_mh_ad_31_5) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG09_VGT_MH_send_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE;
+     } mh_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG09_VGT_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg09_t f;
+} mh_debug_reg09_u;
+
+
+/*
+ * MH_DEBUG_REG10 struct
+ */
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG10_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG10_TC_MH_mask_SIZE 2
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG10_TC_MH_send_SHIFT 2
+#define MH_DEBUG_REG10_TC_MH_mask_SHIFT 3
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG10_TC_MH_send_MASK 0x00000004
+#define MH_DEBUG_REG10_TC_MH_mask_MASK 0x00000018
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG10_MASK \
+     (MH_DEBUG_REG10_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG10_TC_MH_send_MASK | \
+      MH_DEBUG_REG10_TC_MH_mask_MASK | \
+      MH_DEBUG_REG10_TC_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG10(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) | \
+      (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) | \
+      (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG10_GET_ALWAYS_ZERO(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_mask(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_mask_MASK) >> MH_DEBUG_REG10_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_addr_31_5(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG10_SET_ALWAYS_ZERO(mh_debug_reg10_reg, always_zero) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_mask(mh_debug_reg10_reg, tc_mh_mask) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_addr_31_5(mh_debug_reg10_reg, tc_mh_addr_31_5) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int always_zero                    : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG10_TC_MH_mask_SIZE;
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE;
+     } mh_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG10_TC_MH_mask_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg10_t f;
+} mh_debug_reg10_u;
+
+
+/*
+ * MH_DEBUG_REG11 struct
+ */
+
+#define MH_DEBUG_REG11_TC_MH_info_SIZE 25
+#define MH_DEBUG_REG11_TC_MH_send_SIZE 1
+
+#define MH_DEBUG_REG11_TC_MH_info_SHIFT 0
+#define MH_DEBUG_REG11_TC_MH_send_SHIFT 25
+
+#define MH_DEBUG_REG11_TC_MH_info_MASK 0x01ffffff
+#define MH_DEBUG_REG11_TC_MH_send_MASK 0x02000000
+
+#define MH_DEBUG_REG11_MASK \
+     (MH_DEBUG_REG11_TC_MH_info_MASK | \
+      MH_DEBUG_REG11_TC_MH_send_MASK)
+
+#define MH_DEBUG_REG11(tc_mh_info, tc_mh_send) \
+     ((tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT))
+
+#define MH_DEBUG_REG11_GET_TC_MH_info(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_info_MASK) >> MH_DEBUG_REG11_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG11_GET_TC_MH_send(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_send_MASK) >> MH_DEBUG_REG11_TC_MH_send_SHIFT)
+
+#define MH_DEBUG_REG11_SET_TC_MH_info(mh_debug_reg11_reg, tc_mh_info) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG11_SET_TC_MH_send(mh_debug_reg11_reg, tc_mh_send) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int tc_mh_info                     : MH_DEBUG_REG11_TC_MH_info_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG11_TC_MH_send_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int                                : 6;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG11_TC_MH_send_SIZE;
+          unsigned int tc_mh_info                     : MH_DEBUG_REG11_TC_MH_info_SIZE;
+     } mh_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg11_t f;
+} mh_debug_reg11_u;
+
+
+/*
+ * MH_DEBUG_REG12 struct
+ */
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_SIZE 25
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE 1
+#define MH_DEBUG_REG12_TC_MH_written_SIZE 1
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT 0
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT 25
+#define MH_DEBUG_REG12_TC_MH_written_SHIFT 26
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_MASK 0x01ffffff
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK 0x02000000
+#define MH_DEBUG_REG12_TC_MH_written_MASK 0x04000000
+
+#define MH_DEBUG_REG12_MASK \
+     (MH_DEBUG_REG12_MH_TC_mcinfo_MASK | \
+      MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK | \
+      MH_DEBUG_REG12_TC_MH_written_MASK)
+
+#define MH_DEBUG_REG12(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \
+     ((mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) | \
+      (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT))
+
+#define MH_DEBUG_REG12_GET_MH_TC_mcinfo(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG12_GET_MH_TC_mcinfo_send(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_MH_written(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_MH_written_MASK) >> MH_DEBUG_REG12_TC_MH_written_SHIFT)
+
+#define MH_DEBUG_REG12_SET_MH_TC_mcinfo(mh_debug_reg12_reg, mh_tc_mcinfo) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG12_SET_MH_TC_mcinfo_send(mh_debug_reg12_reg, mh_tc_mcinfo_send) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_MH_written(mh_debug_reg12_reg, tc_mh_written) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG12_TC_MH_written_SIZE;
+          unsigned int                                : 5;
+     } mh_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int                                : 5;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG12_TC_MH_written_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE;
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE;
+     } mh_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg12_t f;
+} mh_debug_reg12_u;
+
+
+/*
+ * MH_DEBUG_REG13 struct
+ */
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1
+#define MH_DEBUG_REG13_TC_ROQ_MASK_SIZE 2
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE 27
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 2
+#define MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT 3
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT 5
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x00000004
+#define MH_DEBUG_REG13_TC_ROQ_MASK_MASK 0x00000018
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG13_MASK \
+     (MH_DEBUG_REG13_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_SEND_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_MASK_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK)
+
+#define MH_DEBUG_REG13(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) | \
+      (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) | \
+      (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT))
+
+#define MH_DEBUG_REG13_GET_ALWAYS_ZERO(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_MASK(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_ADDR_31_5(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)
+
+#define MH_DEBUG_REG13_SET_ALWAYS_ZERO(mh_debug_reg13_reg, always_zero) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_MASK(mh_debug_reg13_reg, tc_roq_mask) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_ADDR_31_5(mh_debug_reg13_reg, tc_roq_addr_31_5) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int always_zero                    : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE;
+     } mh_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg13_t f;
+} mh_debug_reg13_u;
+
+
+/*
+ * MH_DEBUG_REG14 struct
+ */
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_SIZE 25
+#define MH_DEBUG_REG14_TC_ROQ_SEND_SIZE 1
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT 0
+#define MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT 25
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_MASK 0x01ffffff
+#define MH_DEBUG_REG14_TC_ROQ_SEND_MASK 0x02000000
+
+#define MH_DEBUG_REG14_MASK \
+     (MH_DEBUG_REG14_TC_ROQ_INFO_MASK | \
+      MH_DEBUG_REG14_TC_ROQ_SEND_MASK)
+
+#define MH_DEBUG_REG14(tc_roq_info, tc_roq_send) \
+     ((tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT))
+
+#define MH_DEBUG_REG14_GET_TC_ROQ_INFO(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG14_GET_TC_ROQ_SEND(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)
+
+#define MH_DEBUG_REG14_SET_TC_ROQ_INFO(mh_debug_reg14_reg, tc_roq_info) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG14_SET_TC_ROQ_SEND(mh_debug_reg14_reg, tc_roq_send) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int tc_roq_info                    : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int                                : 6;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_info                    : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE;
+     } mh_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg14_t f;
+} mh_debug_reg14_u;
+
+
+/*
+ * MH_DEBUG_REG15 struct
+ */
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG15_RB_MH_send_SIZE 1
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG15_RB_MH_send_SHIFT 4
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG15_RB_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG15_MASK \
+     (MH_DEBUG_REG15_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG15_RB_MH_send_MASK | \
+      MH_DEBUG_REG15_RB_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG15(always_zero, rb_mh_send, rb_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) | \
+      (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) | \
+      (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG15_GET_ALWAYS_ZERO(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG15_GET_RB_MH_send(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_send_MASK) >> MH_DEBUG_REG15_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG15_GET_RB_MH_addr_31_5(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG15_SET_ALWAYS_ZERO(mh_debug_reg15_reg, always_zero) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG15_SET_RB_MH_send(mh_debug_reg15_reg, rb_mh_send) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG15_SET_RB_MH_addr_31_5(mh_debug_reg15_reg, rb_mh_addr_31_5) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int always_zero                    : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG15_RB_MH_send_SIZE;
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE;
+     } mh_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG15_RB_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg15_t f;
+} mh_debug_reg15_u;
+
+
+/*
+ * MH_DEBUG_REG16 struct
+ */
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG16_MASK \
+     (MH_DEBUG_REG16_RB_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG16(rb_mh_data_31_0) \
+     ((rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG16_GET_RB_MH_data_31_0(mh_debug_reg16) \
+     ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG16_SET_RB_MH_data_31_0(mh_debug_reg16_reg, rb_mh_data_31_0) \
+     mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg16_t f;
+} mh_debug_reg16_u;
+
+
+/*
+ * MH_DEBUG_REG17 struct
+ */
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG17_MASK \
+     (MH_DEBUG_REG17_RB_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG17(rb_mh_data_63_32) \
+     ((rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG17_GET_RB_MH_data_63_32(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG17_SET_RB_MH_data_63_32(mh_debug_reg17_reg, rb_mh_data_63_32) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg17_t f;
+} mh_debug_reg17_u;
+
+
+/*
+ * MH_DEBUG_REG18 struct
+ */
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG18_PA_MH_send_SIZE 1
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG18_PA_MH_send_SHIFT 4
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG18_PA_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG18_MASK \
+     (MH_DEBUG_REG18_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG18_PA_MH_send_MASK | \
+      MH_DEBUG_REG18_PA_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG18(always_zero, pa_mh_send, pa_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) | \
+      (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) | \
+      (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG18_GET_ALWAYS_ZERO(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG18_GET_PA_MH_send(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_send_MASK) >> MH_DEBUG_REG18_PA_MH_send_SHIFT)
+#define MH_DEBUG_REG18_GET_PA_MH_addr_31_5(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) >> MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG18_SET_ALWAYS_ZERO(mh_debug_reg18_reg, always_zero) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG18_SET_PA_MH_send(mh_debug_reg18_reg, pa_mh_send) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_send_MASK) | (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT)
+#define MH_DEBUG_REG18_SET_PA_MH_addr_31_5(mh_debug_reg18_reg, pa_mh_addr_31_5) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) | (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int always_zero                    : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE;
+          unsigned int pa_mh_send                     : MH_DEBUG_REG18_PA_MH_send_SIZE;
+          unsigned int pa_mh_addr_31_5                : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE;
+     } mh_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int pa_mh_addr_31_5                : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE;
+          unsigned int pa_mh_send                     : MH_DEBUG_REG18_PA_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg18_t f;
+} mh_debug_reg18_u;
+
+
+/*
+ * MH_DEBUG_REG19 struct
+ */
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG19_MASK \
+     (MH_DEBUG_REG19_PA_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG19(pa_mh_data_31_0) \
+     ((pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG19_GET_PA_MH_data_31_0(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_PA_MH_data_31_0_MASK) >> MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG19_SET_PA_MH_data_31_0(mh_debug_reg19_reg, pa_mh_data_31_0) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_PA_MH_data_31_0_MASK) | (pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int pa_mh_data_31_0                : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE;
+     } mh_debug_reg19_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int pa_mh_data_31_0                : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE;
+     } mh_debug_reg19_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg19_t f;
+} mh_debug_reg19_u;
+
+
+/*
+ * MH_DEBUG_REG20 struct
+ */
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG20_MASK \
+     (MH_DEBUG_REG20_PA_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG20(pa_mh_data_63_32) \
+     ((pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG20_GET_PA_MH_data_63_32(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_PA_MH_data_63_32_MASK) >> MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG20_SET_PA_MH_data_63_32(mh_debug_reg20_reg, pa_mh_data_63_32) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_PA_MH_data_63_32_MASK) | (pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int pa_mh_data_63_32               : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE;
+     } mh_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int pa_mh_data_63_32               : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE;
+     } mh_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg20_t f;
+} mh_debug_reg20_u;
+
+
+/*
+ * MH_DEBUG_REG21 struct
+ */
+
+#define MH_DEBUG_REG21_AVALID_q_SIZE   1
+#define MH_DEBUG_REG21_AREADY_q_SIZE   1
+#define MH_DEBUG_REG21_AID_q_SIZE      3
+#define MH_DEBUG_REG21_ALEN_q_2_0_SIZE 3
+#define MH_DEBUG_REG21_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG21_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG21_ARID_q_SIZE     3
+#define MH_DEBUG_REG21_ARLEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG21_RVALID_q_SIZE   1
+#define MH_DEBUG_REG21_RREADY_q_SIZE   1
+#define MH_DEBUG_REG21_RLAST_q_SIZE    1
+#define MH_DEBUG_REG21_RID_q_SIZE      3
+#define MH_DEBUG_REG21_WVALID_q_SIZE   1
+#define MH_DEBUG_REG21_WREADY_q_SIZE   1
+#define MH_DEBUG_REG21_WLAST_q_SIZE    1
+#define MH_DEBUG_REG21_WID_q_SIZE      3
+#define MH_DEBUG_REG21_BVALID_q_SIZE   1
+#define MH_DEBUG_REG21_BREADY_q_SIZE   1
+#define MH_DEBUG_REG21_BID_q_SIZE      3
+
+#define MH_DEBUG_REG21_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG21_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG21_AID_q_SHIFT     2
+#define MH_DEBUG_REG21_ALEN_q_2_0_SHIFT 5
+#define MH_DEBUG_REG21_ARVALID_q_SHIFT 8
+#define MH_DEBUG_REG21_ARREADY_q_SHIFT 9
+#define MH_DEBUG_REG21_ARID_q_SHIFT    10
+#define MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT 13
+#define MH_DEBUG_REG21_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG21_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG21_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG21_RID_q_SHIFT     18
+#define MH_DEBUG_REG21_WVALID_q_SHIFT  21
+#define MH_DEBUG_REG21_WREADY_q_SHIFT  22
+#define MH_DEBUG_REG21_WLAST_q_SHIFT   23
+#define MH_DEBUG_REG21_WID_q_SHIFT     24
+#define MH_DEBUG_REG21_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG21_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG21_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG21_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG21_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG21_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG21_ALEN_q_2_0_MASK 0x000000e0
+#define MH_DEBUG_REG21_ARVALID_q_MASK  0x00000100
+#define MH_DEBUG_REG21_ARREADY_q_MASK  0x00000200
+#define MH_DEBUG_REG21_ARID_q_MASK     0x00001c00
+#define MH_DEBUG_REG21_ARLEN_q_1_0_MASK 0x00006000
+#define MH_DEBUG_REG21_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG21_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG21_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG21_RID_q_MASK      0x001c0000
+#define MH_DEBUG_REG21_WVALID_q_MASK   0x00200000
+#define MH_DEBUG_REG21_WREADY_q_MASK   0x00400000
+#define MH_DEBUG_REG21_WLAST_q_MASK    0x00800000
+#define MH_DEBUG_REG21_WID_q_MASK      0x07000000
+#define MH_DEBUG_REG21_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG21_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG21_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG21_MASK \
+     (MH_DEBUG_REG21_AVALID_q_MASK | \
+      MH_DEBUG_REG21_AREADY_q_MASK | \
+      MH_DEBUG_REG21_AID_q_MASK | \
+      MH_DEBUG_REG21_ALEN_q_2_0_MASK | \
+      MH_DEBUG_REG21_ARVALID_q_MASK | \
+      MH_DEBUG_REG21_ARREADY_q_MASK | \
+      MH_DEBUG_REG21_ARID_q_MASK | \
+      MH_DEBUG_REG21_ARLEN_q_1_0_MASK | \
+      MH_DEBUG_REG21_RVALID_q_MASK | \
+      MH_DEBUG_REG21_RREADY_q_MASK | \
+      MH_DEBUG_REG21_RLAST_q_MASK | \
+      MH_DEBUG_REG21_RID_q_MASK | \
+      MH_DEBUG_REG21_WVALID_q_MASK | \
+      MH_DEBUG_REG21_WREADY_q_MASK | \
+      MH_DEBUG_REG21_WLAST_q_MASK | \
+      MH_DEBUG_REG21_WID_q_MASK | \
+      MH_DEBUG_REG21_BVALID_q_MASK | \
+      MH_DEBUG_REG21_BREADY_q_MASK | \
+      MH_DEBUG_REG21_BID_q_MASK)
+
+#define MH_DEBUG_REG21(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) | \
+      (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) | \
+      (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) | \
+      (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG21_BID_q_SHIFT))
+
+#define MH_DEBUG_REG21_GET_AVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AVALID_q_MASK) >> MH_DEBUG_REG21_AVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_AREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AREADY_q_MASK) >> MH_DEBUG_REG21_AREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_AID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AID_q_MASK) >> MH_DEBUG_REG21_AID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ALEN_q_2_0(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ALEN_q_2_0_MASK) >> MH_DEBUG_REG21_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG21_GET_ARVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARVALID_q_MASK) >> MH_DEBUG_REG21_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARREADY_q_MASK) >> MH_DEBUG_REG21_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARID_q_MASK) >> MH_DEBUG_REG21_ARID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARLEN_q_1_0(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG21_GET_RVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RVALID_q_MASK) >> MH_DEBUG_REG21_RVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RREADY_q_MASK) >> MH_DEBUG_REG21_RREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RLAST_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RLAST_q_MASK) >> MH_DEBUG_REG21_RLAST_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RID_q_MASK) >> MH_DEBUG_REG21_RID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WVALID_q_MASK) >> MH_DEBUG_REG21_WVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WREADY_q_MASK) >> MH_DEBUG_REG21_WREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WLAST_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WLAST_q_MASK) >> MH_DEBUG_REG21_WLAST_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WID_q_MASK) >> MH_DEBUG_REG21_WID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BVALID_q_MASK) >> MH_DEBUG_REG21_BVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BREADY_q_MASK) >> MH_DEBUG_REG21_BREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BID_q_MASK) >> MH_DEBUG_REG21_BID_q_SHIFT)
+
+#define MH_DEBUG_REG21_SET_AVALID_q(mh_debug_reg21_reg, avalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_AREADY_q(mh_debug_reg21_reg, aready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_AID_q(mh_debug_reg21_reg, aid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AID_q_MASK) | (aid_q << MH_DEBUG_REG21_AID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ALEN_q_2_0(mh_debug_reg21_reg, alen_q_2_0) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG21_SET_ARVALID_q(mh_debug_reg21_reg, arvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARREADY_q(mh_debug_reg21_reg, arready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARID_q(mh_debug_reg21_reg, arid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARID_q_MASK) | (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARLEN_q_1_0(mh_debug_reg21_reg, arlen_q_1_0) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG21_SET_RVALID_q(mh_debug_reg21_reg, rvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RREADY_q(mh_debug_reg21_reg, rready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RLAST_q(mh_debug_reg21_reg, rlast_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RID_q(mh_debug_reg21_reg, rid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RID_q_MASK) | (rid_q << MH_DEBUG_REG21_RID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WVALID_q(mh_debug_reg21_reg, wvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WREADY_q(mh_debug_reg21_reg, wready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WLAST_q(mh_debug_reg21_reg, wlast_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WID_q(mh_debug_reg21_reg, wid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WID_q_MASK) | (wid_q << MH_DEBUG_REG21_WID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BVALID_q(mh_debug_reg21_reg, bvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BREADY_q(mh_debug_reg21_reg, bready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BID_q(mh_debug_reg21_reg, bid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BID_q_MASK) | (bid_q << MH_DEBUG_REG21_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG21_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG21_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG21_AID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG21_ALEN_q_2_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG21_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG21_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG21_ARID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG21_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG21_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG21_RLAST_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG21_RID_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG21_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG21_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG21_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG21_WID_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG21_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG21_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG21_BID_q_SIZE;
+     } mh_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int bid_q                          : MH_DEBUG_REG21_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG21_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG21_BVALID_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG21_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG21_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG21_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG21_WVALID_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG21_RID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG21_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG21_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG21_RVALID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG21_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG21_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG21_ARVALID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG21_ALEN_q_2_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG21_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG21_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG21_AVALID_q_SIZE;
+     } mh_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg21_t f;
+} mh_debug_reg21_u;
+
+
+/*
+ * MH_DEBUG_REG22 struct
+ */
+
+#define MH_DEBUG_REG22_AVALID_q_SIZE   1
+#define MH_DEBUG_REG22_AREADY_q_SIZE   1
+#define MH_DEBUG_REG22_AID_q_SIZE      3
+#define MH_DEBUG_REG22_ALEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG22_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG22_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG22_ARID_q_SIZE     3
+#define MH_DEBUG_REG22_ARLEN_q_1_1_SIZE 1
+#define MH_DEBUG_REG22_WVALID_q_SIZE   1
+#define MH_DEBUG_REG22_WREADY_q_SIZE   1
+#define MH_DEBUG_REG22_WLAST_q_SIZE    1
+#define MH_DEBUG_REG22_WID_q_SIZE      3
+#define MH_DEBUG_REG22_WSTRB_q_SIZE    8
+#define MH_DEBUG_REG22_BVALID_q_SIZE   1
+#define MH_DEBUG_REG22_BREADY_q_SIZE   1
+#define MH_DEBUG_REG22_BID_q_SIZE      3
+
+#define MH_DEBUG_REG22_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG22_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG22_AID_q_SHIFT     2
+#define MH_DEBUG_REG22_ALEN_q_1_0_SHIFT 5
+#define MH_DEBUG_REG22_ARVALID_q_SHIFT 7
+#define MH_DEBUG_REG22_ARREADY_q_SHIFT 8
+#define MH_DEBUG_REG22_ARID_q_SHIFT    9
+#define MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT 12
+#define MH_DEBUG_REG22_WVALID_q_SHIFT  13
+#define MH_DEBUG_REG22_WREADY_q_SHIFT  14
+#define MH_DEBUG_REG22_WLAST_q_SHIFT   15
+#define MH_DEBUG_REG22_WID_q_SHIFT     16
+#define MH_DEBUG_REG22_WSTRB_q_SHIFT   19
+#define MH_DEBUG_REG22_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG22_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG22_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG22_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG22_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG22_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG22_ALEN_q_1_0_MASK 0x00000060
+#define MH_DEBUG_REG22_ARVALID_q_MASK  0x00000080
+#define MH_DEBUG_REG22_ARREADY_q_MASK  0x00000100
+#define MH_DEBUG_REG22_ARID_q_MASK     0x00000e00
+#define MH_DEBUG_REG22_ARLEN_q_1_1_MASK 0x00001000
+#define MH_DEBUG_REG22_WVALID_q_MASK   0x00002000
+#define MH_DEBUG_REG22_WREADY_q_MASK   0x00004000
+#define MH_DEBUG_REG22_WLAST_q_MASK    0x00008000
+#define MH_DEBUG_REG22_WID_q_MASK      0x00070000
+#define MH_DEBUG_REG22_WSTRB_q_MASK    0x07f80000
+#define MH_DEBUG_REG22_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG22_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG22_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG22_MASK \
+     (MH_DEBUG_REG22_AVALID_q_MASK | \
+      MH_DEBUG_REG22_AREADY_q_MASK | \
+      MH_DEBUG_REG22_AID_q_MASK | \
+      MH_DEBUG_REG22_ALEN_q_1_0_MASK | \
+      MH_DEBUG_REG22_ARVALID_q_MASK | \
+      MH_DEBUG_REG22_ARREADY_q_MASK | \
+      MH_DEBUG_REG22_ARID_q_MASK | \
+      MH_DEBUG_REG22_ARLEN_q_1_1_MASK | \
+      MH_DEBUG_REG22_WVALID_q_MASK | \
+      MH_DEBUG_REG22_WREADY_q_MASK | \
+      MH_DEBUG_REG22_WLAST_q_MASK | \
+      MH_DEBUG_REG22_WID_q_MASK | \
+      MH_DEBUG_REG22_WSTRB_q_MASK | \
+      MH_DEBUG_REG22_BVALID_q_MASK | \
+      MH_DEBUG_REG22_BREADY_q_MASK | \
+      MH_DEBUG_REG22_BID_q_MASK)
+
+#define MH_DEBUG_REG22(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) | \
+      (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) | \
+      (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) | \
+      (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG22_BID_q_SHIFT))
+
+#define MH_DEBUG_REG22_GET_AVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AVALID_q_MASK) >> MH_DEBUG_REG22_AVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_AREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AREADY_q_MASK) >> MH_DEBUG_REG22_AREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_AID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AID_q_MASK) >> MH_DEBUG_REG22_AID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ALEN_q_1_0(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ALEN_q_1_0_MASK) >> MH_DEBUG_REG22_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG22_GET_ARVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARVALID_q_MASK) >> MH_DEBUG_REG22_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARREADY_q_MASK) >> MH_DEBUG_REG22_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARID_q_MASK) >> MH_DEBUG_REG22_ARID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARLEN_q_1_1(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG22_GET_WVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WVALID_q_MASK) >> MH_DEBUG_REG22_WVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WREADY_q_MASK) >> MH_DEBUG_REG22_WREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WLAST_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WLAST_q_MASK) >> MH_DEBUG_REG22_WLAST_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WID_q_MASK) >> MH_DEBUG_REG22_WID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WSTRB_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WSTRB_q_MASK) >> MH_DEBUG_REG22_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BVALID_q_MASK) >> MH_DEBUG_REG22_BVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BREADY_q_MASK) >> MH_DEBUG_REG22_BREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BID_q_MASK) >> MH_DEBUG_REG22_BID_q_SHIFT)
+
+#define MH_DEBUG_REG22_SET_AVALID_q(mh_debug_reg22_reg, avalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_AREADY_q(mh_debug_reg22_reg, aready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_AID_q(mh_debug_reg22_reg, aid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AID_q_MASK) | (aid_q << MH_DEBUG_REG22_AID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ALEN_q_1_0(mh_debug_reg22_reg, alen_q_1_0) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG22_SET_ARVALID_q(mh_debug_reg22_reg, arvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARREADY_q(mh_debug_reg22_reg, arready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARID_q(mh_debug_reg22_reg, arid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARID_q_MASK) | (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARLEN_q_1_1(mh_debug_reg22_reg, arlen_q_1_1) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG22_SET_WVALID_q(mh_debug_reg22_reg, wvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WREADY_q(mh_debug_reg22_reg, wready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WLAST_q(mh_debug_reg22_reg, wlast_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WID_q(mh_debug_reg22_reg, wid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WID_q_MASK) | (wid_q << MH_DEBUG_REG22_WID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WSTRB_q(mh_debug_reg22_reg, wstrb_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BVALID_q(mh_debug_reg22_reg, bvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BREADY_q(mh_debug_reg22_reg, bready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BID_q(mh_debug_reg22_reg, bid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BID_q_MASK) | (bid_q << MH_DEBUG_REG22_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG22_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG22_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG22_AID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG22_ALEN_q_1_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG22_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG22_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG22_ARID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG22_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG22_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG22_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG22_WID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG22_WSTRB_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG22_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG22_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG22_BID_q_SIZE;
+     } mh_debug_reg22_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int bid_q                          : MH_DEBUG_REG22_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG22_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG22_BVALID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG22_WSTRB_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG22_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG22_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG22_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG22_WVALID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG22_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG22_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG22_ARVALID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG22_ALEN_q_1_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG22_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG22_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG22_AVALID_q_SIZE;
+     } mh_debug_reg22_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg22_t f;
+} mh_debug_reg22_u;
+
+
+/*
+ * MH_DEBUG_REG23 struct
+ */
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG23_CTRL_ARC_ID_SIZE 3
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE 28
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT 0
+#define MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT 1
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT 4
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK 0x00000001
+#define MH_DEBUG_REG23_CTRL_ARC_ID_MASK 0x0000000e
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_MASK 0xfffffff0
+
+#define MH_DEBUG_REG23_MASK \
+     (MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG23_CTRL_ARC_ID_MASK | \
+      MH_DEBUG_REG23_CTRL_ARC_PAD_MASK)
+
+#define MH_DEBUG_REG23(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \
+     ((arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) | \
+      (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) | \
+      (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT))
+
+#define MH_DEBUG_REG23_GET_ARC_CTRL_RE_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG23_GET_CTRL_ARC_ID(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG23_GET_CTRL_ARC_PAD(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)
+
+#define MH_DEBUG_REG23_SET_ARC_CTRL_RE_q(mh_debug_reg23_reg, arc_ctrl_re_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG23_SET_CTRL_ARC_ID(mh_debug_reg23_reg, ctrl_arc_id) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG23_SET_CTRL_ARC_PAD(mh_debug_reg23_reg, ctrl_arc_pad) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE;
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE;
+     } mh_debug_reg23_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE;
+     } mh_debug_reg23_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg23_t f;
+} mh_debug_reg23_u;
+
+
+/*
+ * MH_DEBUG_REG24 struct
+ */
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG24_REG_A_SIZE      14
+#define MH_DEBUG_REG24_REG_RE_SIZE     1
+#define MH_DEBUG_REG24_REG_WE_SIZE     1
+#define MH_DEBUG_REG24_BLOCK_RS_SIZE   1
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG24_REG_A_SHIFT     2
+#define MH_DEBUG_REG24_REG_RE_SHIFT    16
+#define MH_DEBUG_REG24_REG_WE_SHIFT    17
+#define MH_DEBUG_REG24_BLOCK_RS_SHIFT  18
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG24_REG_A_MASK      0x0000fffc
+#define MH_DEBUG_REG24_REG_RE_MASK     0x00010000
+#define MH_DEBUG_REG24_REG_WE_MASK     0x00020000
+#define MH_DEBUG_REG24_BLOCK_RS_MASK   0x00040000
+
+#define MH_DEBUG_REG24_MASK \
+     (MH_DEBUG_REG24_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG24_REG_A_MASK | \
+      MH_DEBUG_REG24_REG_RE_MASK | \
+      MH_DEBUG_REG24_REG_WE_MASK | \
+      MH_DEBUG_REG24_BLOCK_RS_MASK)
+
+#define MH_DEBUG_REG24(always_zero, reg_a, reg_re, reg_we, block_rs) \
+     ((always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) | \
+      (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) | \
+      (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) | \
+      (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) | \
+      (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT))
+
+#define MH_DEBUG_REG24_GET_ALWAYS_ZERO(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_A(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_A_MASK) >> MH_DEBUG_REG24_REG_A_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_RE(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_RE_MASK) >> MH_DEBUG_REG24_REG_RE_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_WE(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_WE_MASK) >> MH_DEBUG_REG24_REG_WE_SHIFT)
+#define MH_DEBUG_REG24_GET_BLOCK_RS(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_BLOCK_RS_MASK) >> MH_DEBUG_REG24_BLOCK_RS_SHIFT)
+
+#define MH_DEBUG_REG24_SET_ALWAYS_ZERO(mh_debug_reg24_reg, always_zero) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_A(mh_debug_reg24_reg, reg_a) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_A_MASK) | (reg_a << MH_DEBUG_REG24_REG_A_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_RE(mh_debug_reg24_reg, reg_re) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_RE_MASK) | (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_WE(mh_debug_reg24_reg, reg_we) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_WE_MASK) | (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT)
+#define MH_DEBUG_REG24_SET_BLOCK_RS(mh_debug_reg24_reg, block_rs) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int always_zero                    : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG24_REG_A_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG24_REG_RE_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG24_REG_WE_SIZE;
+          unsigned int block_rs                       : MH_DEBUG_REG24_BLOCK_RS_SIZE;
+          unsigned int                                : 13;
+     } mh_debug_reg24_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int                                : 13;
+          unsigned int block_rs                       : MH_DEBUG_REG24_BLOCK_RS_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG24_REG_WE_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG24_REG_RE_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG24_REG_A_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg24_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg24_t f;
+} mh_debug_reg24_u;
+
+
+/*
+ * MH_DEBUG_REG25 struct
+ */
+
+#define MH_DEBUG_REG25_REG_WD_SIZE     32
+
+#define MH_DEBUG_REG25_REG_WD_SHIFT    0
+
+#define MH_DEBUG_REG25_REG_WD_MASK     0xffffffff
+
+#define MH_DEBUG_REG25_MASK \
+     (MH_DEBUG_REG25_REG_WD_MASK)
+
+#define MH_DEBUG_REG25(reg_wd) \
+     ((reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT))
+
+#define MH_DEBUG_REG25_GET_REG_WD(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_REG_WD_MASK) >> MH_DEBUG_REG25_REG_WD_SHIFT)
+
+#define MH_DEBUG_REG25_SET_REG_WD(mh_debug_reg25_reg, reg_wd) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG25_REG_WD_SIZE;
+     } mh_debug_reg25_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG25_REG_WD_SIZE;
+     } mh_debug_reg25_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg25_t f;
+} mh_debug_reg25_u;
+
+
+/*
+ * MH_DEBUG_REG26 struct
+ */
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_GAT_CLK_ENA_SIZE 1
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE 1
+#define MH_DEBUG_REG26_CNT_q_SIZE      6
+#define MH_DEBUG_REG26_TCD_EMPTY_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG26_MH_BUSY_d_SIZE  1
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE 1
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+#define MH_DEBUG_REG26_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG26_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_PA_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_PA_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG26_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG26_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG26_BRC_VALID_SIZE  1
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_SHIFT 0
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT 1
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT 2
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT 3
+#define MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT 4
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT 5
+#define MH_DEBUG_REG26_CNT_q_SHIFT     6
+#define MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT 12
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT 13
+#define MH_DEBUG_REG26_MH_BUSY_d_SHIFT 14
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT 15
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 16
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 17
+#define MH_DEBUG_REG26_CP_SEND_q_SHIFT 18
+#define MH_DEBUG_REG26_CP_RTR_q_SHIFT  19
+#define MH_DEBUG_REG26_VGT_SEND_q_SHIFT 20
+#define MH_DEBUG_REG26_VGT_RTR_q_SHIFT 21
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 22
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 23
+#define MH_DEBUG_REG26_RB_SEND_q_SHIFT 24
+#define MH_DEBUG_REG26_RB_RTR_q_SHIFT  25
+#define MH_DEBUG_REG26_PA_SEND_q_SHIFT 26
+#define MH_DEBUG_REG26_PA_RTR_q_SHIFT  27
+#define MH_DEBUG_REG26_RDC_VALID_SHIFT 28
+#define MH_DEBUG_REG26_RDC_RLAST_SHIFT 29
+#define MH_DEBUG_REG26_TLBMISS_VALID_SHIFT 30
+#define MH_DEBUG_REG26_BRC_VALID_SHIFT 31
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_MASK 0x00000001
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK 0x00000002
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK 0x00000004
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK 0x00000008
+#define MH_DEBUG_REG26_GAT_CLK_ENA_MASK 0x00000010
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK 0x00000020
+#define MH_DEBUG_REG26_CNT_q_MASK      0x00000fc0
+#define MH_DEBUG_REG26_TCD_EMPTY_q_MASK 0x00001000
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK 0x00002000
+#define MH_DEBUG_REG26_MH_BUSY_d_MASK  0x00004000
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK 0x00008000
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000
+#define MH_DEBUG_REG26_CP_SEND_q_MASK  0x00040000
+#define MH_DEBUG_REG26_CP_RTR_q_MASK   0x00080000
+#define MH_DEBUG_REG26_VGT_SEND_q_MASK 0x00100000
+#define MH_DEBUG_REG26_VGT_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00400000
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00800000
+#define MH_DEBUG_REG26_RB_SEND_q_MASK  0x01000000
+#define MH_DEBUG_REG26_RB_RTR_q_MASK   0x02000000
+#define MH_DEBUG_REG26_PA_SEND_q_MASK  0x04000000
+#define MH_DEBUG_REG26_PA_RTR_q_MASK   0x08000000
+#define MH_DEBUG_REG26_RDC_VALID_MASK  0x10000000
+#define MH_DEBUG_REG26_RDC_RLAST_MASK  0x20000000
+#define MH_DEBUG_REG26_TLBMISS_VALID_MASK 0x40000000
+#define MH_DEBUG_REG26_BRC_VALID_MASK  0x80000000
+
+#define MH_DEBUG_REG26_MASK \
+     (MH_DEBUG_REG26_MH_RBBM_busy_MASK | \
+      MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK | \
+      MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK | \
+      MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK | \
+      MH_DEBUG_REG26_GAT_CLK_ENA_MASK | \
+      MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK | \
+      MH_DEBUG_REG26_CNT_q_MASK | \
+      MH_DEBUG_REG26_TCD_EMPTY_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG26_MH_BUSY_d_MASK | \
+      MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK | \
+      MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK | \
+      MH_DEBUG_REG26_CP_SEND_q_MASK | \
+      MH_DEBUG_REG26_CP_RTR_q_MASK | \
+      MH_DEBUG_REG26_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG26_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG26_RB_SEND_q_MASK | \
+      MH_DEBUG_REG26_RB_RTR_q_MASK | \
+      MH_DEBUG_REG26_PA_SEND_q_MASK | \
+      MH_DEBUG_REG26_PA_RTR_q_MASK | \
+      MH_DEBUG_REG26_RDC_VALID_MASK | \
+      MH_DEBUG_REG26_RDC_RLAST_MASK | \
+      MH_DEBUG_REG26_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG26_BRC_VALID_MASK)
+
+#define MH_DEBUG_REG26(mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, mh_mmu_invalidate_invalidate_tc, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_dbg_q, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \
+     ((mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) | \
+      (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) | \
+      (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) | \
+      (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) | \
+      (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) | \
+      (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) | \
+      (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) | \
+      (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) | \
+      (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) | \
+      (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) | \
+      (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) | \
+      (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) | \
+      (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) | \
+      (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT))
+
+#define MH_DEBUG_REG26_GET_MH_RBBM_busy(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_RBBM_busy_MASK) >> MH_DEBUG_REG26_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_mh_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_GAT_CLK_ENA(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG26_GET_RBBM_MH_clk_en_override(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG26_GET_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CNT_q_MASK) >> MH_DEBUG_REG26_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TCD_EMPTY_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_EMPTY(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_BUSY_d(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_BUSY_d_MASK) >> MH_DEBUG_REG26_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG26_GET_ANY_CLNT_BUSY(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_q_MASK) >> MH_DEBUG_REG26_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_RTR_q_MASK) >> MH_DEBUG_REG26_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_VGT_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_SEND_q_MASK) >> MH_DEBUG_REG26_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_VGT_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_RTR_q_MASK) >> MH_DEBUG_REG26_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_q_MASK) >> MH_DEBUG_REG26_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_RTR_q_MASK) >> MH_DEBUG_REG26_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_PA_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_PA_SEND_q_MASK) >> MH_DEBUG_REG26_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_PA_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_PA_RTR_q_MASK) >> MH_DEBUG_REG26_PA_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RDC_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_VALID_MASK) >> MH_DEBUG_REG26_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG26_GET_RDC_RLAST(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_RLAST_MASK) >> MH_DEBUG_REG26_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG26_GET_TLBMISS_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TLBMISS_VALID_MASK) >> MH_DEBUG_REG26_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG26_GET_BRC_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_BRC_VALID_MASK) >> MH_DEBUG_REG26_BRC_VALID_SHIFT)
+
+#define MH_DEBUG_REG26_SET_MH_RBBM_busy(mh_debug_reg26_reg, mh_rbbm_busy) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_mh_clk_en_int(mh_debug_reg26_reg, mh_cib_mh_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg26_reg, mh_cib_mmu_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26_reg, mh_cib_tcroq_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_GAT_CLK_ENA(mh_debug_reg26_reg, gat_clk_ena) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG26_SET_RBBM_MH_clk_en_override(mh_debug_reg26_reg, rbbm_mh_clk_en_override) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG26_SET_CNT_q(mh_debug_reg26_reg, cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TCD_EMPTY_q(mh_debug_reg26_reg, tcd_empty_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_EMPTY(mh_debug_reg26_reg, tc_roq_empty) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_BUSY_d(mh_debug_reg26_reg, mh_busy_d) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG26_SET_ANY_CLNT_BUSY(mh_debug_reg26_reg, any_clnt_busy) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_all) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_tc) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_SEND_q(mh_debug_reg26_reg, cp_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_RTR_q(mh_debug_reg26_reg, cp_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_VGT_SEND_q(mh_debug_reg26_reg, vgt_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_VGT_RTR_q(mh_debug_reg26_reg, vgt_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_SEND_q(mh_debug_reg26_reg, rb_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_RTR_q(mh_debug_reg26_reg, rb_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_PA_SEND_q(mh_debug_reg26_reg, pa_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_PA_RTR_q(mh_debug_reg26_reg, pa_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RDC_VALID(mh_debug_reg26_reg, rdc_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG26_SET_RDC_RLAST(mh_debug_reg26_reg, rdc_rlast) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG26_SET_TLBMISS_VALID(mh_debug_reg26_reg, tlbmiss_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG26_SET_BRC_VALID(mh_debug_reg26_reg, brc_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG26_MH_RBBM_busy_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG26_CNT_q_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG26_MH_BUSY_d_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG26_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG26_CP_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG26_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG26_VGT_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG26_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG26_RB_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG26_PA_SEND_q_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG26_PA_RTR_q_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG26_RDC_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG26_RDC_RLAST_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG26_TLBMISS_VALID_SIZE;
+          unsigned int brc_valid                      : MH_DEBUG_REG26_BRC_VALID_SIZE;
+     } mh_debug_reg26_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int brc_valid                      : MH_DEBUG_REG26_BRC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG26_TLBMISS_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG26_RDC_RLAST_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG26_RDC_VALID_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG26_PA_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG26_PA_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG26_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG26_RB_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG26_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG26_VGT_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG26_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG26_CP_SEND_q_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG26_MH_BUSY_d_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG26_CNT_q_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG26_MH_RBBM_busy_SIZE;
+     } mh_debug_reg26_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg26_t f;
+} mh_debug_reg26_u;
+
+
+/*
+ * MH_DEBUG_REG27 struct
+ */
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE 3
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG27_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG27_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG27_ARB_WINNER_q_SIZE 3
+#define MH_DEBUG_REG27_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG27_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG27_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG27_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG27_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG27_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_PA_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG27_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG27_TCHOLD_IP_q_SIZE 1
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT 0
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT 3
+#define MH_DEBUG_REG27_EFF1_WINNER_SHIFT 6
+#define MH_DEBUG_REG27_ARB_WINNER_SHIFT 9
+#define MH_DEBUG_REG27_ARB_WINNER_q_SHIFT 12
+#define MH_DEBUG_REG27_EFF1_WIN_SHIFT  15
+#define MH_DEBUG_REG27_KILL_EFF1_SHIFT 16
+#define MH_DEBUG_REG27_ARB_HOLD_SHIFT  17
+#define MH_DEBUG_REG27_ARB_RTR_q_SHIFT 18
+#define MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT 19
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT 20
+#define MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT 21
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT 22
+#define MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT 23
+#define MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT 24
+#define MH_DEBUG_REG27_ARB_QUAL_SHIFT  25
+#define MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT 26
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT 27
+#define MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT 28
+#define MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT 29
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT 30
+#define MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT 31
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK 0x00000038
+#define MH_DEBUG_REG27_EFF1_WINNER_MASK 0x000001c0
+#define MH_DEBUG_REG27_ARB_WINNER_MASK 0x00000e00
+#define MH_DEBUG_REG27_ARB_WINNER_q_MASK 0x00007000
+#define MH_DEBUG_REG27_EFF1_WIN_MASK   0x00008000
+#define MH_DEBUG_REG27_KILL_EFF1_MASK  0x00010000
+#define MH_DEBUG_REG27_ARB_HOLD_MASK   0x00020000
+#define MH_DEBUG_REG27_ARB_RTR_q_MASK  0x00040000
+#define MH_DEBUG_REG27_CP_SEND_QUAL_MASK 0x00080000
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_MASK 0x00100000
+#define MH_DEBUG_REG27_TC_SEND_QUAL_MASK 0x00200000
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK 0x00400000
+#define MH_DEBUG_REG27_RB_SEND_QUAL_MASK 0x00800000
+#define MH_DEBUG_REG27_PA_SEND_QUAL_MASK 0x01000000
+#define MH_DEBUG_REG27_ARB_QUAL_MASK   0x02000000
+#define MH_DEBUG_REG27_CP_EFF1_REQ_MASK 0x04000000
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_MASK 0x08000000
+#define MH_DEBUG_REG27_TC_EFF1_REQ_MASK 0x10000000
+#define MH_DEBUG_REG27_RB_EFF1_REQ_MASK 0x20000000
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_MASK 0x40000000
+#define MH_DEBUG_REG27_TCHOLD_IP_q_MASK 0x80000000
+
+#define MH_DEBUG_REG27_MASK \
+     (MH_DEBUG_REG27_EFF2_FP_WINNER_MASK | \
+      MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG27_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG27_ARB_WINNER_MASK | \
+      MH_DEBUG_REG27_ARB_WINNER_q_MASK | \
+      MH_DEBUG_REG27_EFF1_WIN_MASK | \
+      MH_DEBUG_REG27_KILL_EFF1_MASK | \
+      MH_DEBUG_REG27_ARB_HOLD_MASK | \
+      MH_DEBUG_REG27_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG27_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG27_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_PA_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_ARB_QUAL_MASK | \
+      MH_DEBUG_REG27_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG27_TCHOLD_IP_q_MASK)
+
+#define MH_DEBUG_REG27(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, pa_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, tcd_nearfull_q, tchold_ip_q) \
+     ((eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) | \
+      (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) | \
+      (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) | \
+      (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) | \
+      (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT))
+
+#define MH_DEBUG_REG27_GET_EFF2_FP_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF2_LRU_WINNER_out(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF1_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WINNER_MASK) >> MH_DEBUG_REG27_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_MASK) >> MH_DEBUG_REG27_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_WINNER_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_q_MASK) >> MH_DEBUG_REG27_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF1_WIN(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WIN_MASK) >> MH_DEBUG_REG27_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG27_GET_KILL_EFF1(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_KILL_EFF1_MASK) >> MH_DEBUG_REG27_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_HOLD(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_HOLD_MASK) >> MH_DEBUG_REG27_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_RTR_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_RTR_q_MASK) >> MH_DEBUG_REG27_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG27_GET_CP_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_VGT_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_SEND_EFF1_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_RB_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_PA_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_QUAL_MASK) >> MH_DEBUG_REG27_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_CP_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_VGT_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_RB_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_TCD_NEARFULL_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG27_GET_TCHOLD_IP_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)
+
+#define MH_DEBUG_REG27_SET_EFF2_FP_WINNER(mh_debug_reg27_reg, eff2_fp_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF2_LRU_WINNER_out(mh_debug_reg27_reg, eff2_lru_winner_out) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF1_WINNER(mh_debug_reg27_reg, eff1_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_WINNER(mh_debug_reg27_reg, arb_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_WINNER_q(mh_debug_reg27_reg, arb_winner_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF1_WIN(mh_debug_reg27_reg, eff1_win) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG27_SET_KILL_EFF1(mh_debug_reg27_reg, kill_eff1) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_HOLD(mh_debug_reg27_reg, arb_hold) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_RTR_q(mh_debug_reg27_reg, arb_rtr_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG27_SET_CP_SEND_QUAL(mh_debug_reg27_reg, cp_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_VGT_SEND_QUAL(mh_debug_reg27_reg, vgt_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_SEND_QUAL(mh_debug_reg27_reg, tc_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_SEND_EFF1_QUAL(mh_debug_reg27_reg, tc_send_eff1_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_RB_SEND_QUAL(mh_debug_reg27_reg, rb_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_PA_SEND_QUAL(mh_debug_reg27_reg, pa_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_QUAL(mh_debug_reg27_reg, arb_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_CP_EFF1_REQ(mh_debug_reg27_reg, cp_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_VGT_EFF1_REQ(mh_debug_reg27_reg, vgt_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_EFF1_REQ(mh_debug_reg27_reg, tc_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_RB_EFF1_REQ(mh_debug_reg27_reg, rb_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_TCD_NEARFULL_q(mh_debug_reg27_reg, tcd_nearfull_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG27_SET_TCHOLD_IP_q(mh_debug_reg27_reg, tchold_ip_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG27_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG27_ARB_WINNER_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG27_ARB_WINNER_q_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG27_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG27_KILL_EFF1_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG27_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG27_ARB_RTR_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG27_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE;
+     } mh_debug_reg27_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG27_ARB_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG27_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG27_ARB_HOLD_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG27_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG27_EFF1_WIN_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG27_ARB_WINNER_q_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG27_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG27_EFF1_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE;
+     } mh_debug_reg27_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg27_t f;
+} mh_debug_reg27_u;
+
+
+/*
+ * MH_DEBUG_REG28 struct
+ */
+
+#define MH_DEBUG_REG28_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG28_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG28_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG28_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG28_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG28_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG28_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG28_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG28_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE 10
+
+#define MH_DEBUG_REG28_EFF1_WINNER_SHIFT 0
+#define MH_DEBUG_REG28_ARB_WINNER_SHIFT 3
+#define MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT 6
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT 7
+#define MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT 8
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT 9
+#define MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT 10
+#define MH_DEBUG_REG28_ARB_QUAL_SHIFT  11
+#define MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT 12
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT 13
+#define MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT 14
+#define MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT 15
+#define MH_DEBUG_REG28_EFF1_WIN_SHIFT  16
+#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 17
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT 18
+#define MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT 19
+#define MH_DEBUG_REG28_ARB_HOLD_SHIFT  20
+#define MH_DEBUG_REG28_ARB_RTR_q_SHIFT 21
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22
+
+#define MH_DEBUG_REG28_EFF1_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG28_ARB_WINNER_MASK 0x00000038
+#define MH_DEBUG_REG28_CP_SEND_QUAL_MASK 0x00000040
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_MASK 0x00000080
+#define MH_DEBUG_REG28_TC_SEND_QUAL_MASK 0x00000100
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK 0x00000200
+#define MH_DEBUG_REG28_RB_SEND_QUAL_MASK 0x00000400
+#define MH_DEBUG_REG28_ARB_QUAL_MASK   0x00000800
+#define MH_DEBUG_REG28_CP_EFF1_REQ_MASK 0x00001000
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_MASK 0x00002000
+#define MH_DEBUG_REG28_TC_EFF1_REQ_MASK 0x00004000
+#define MH_DEBUG_REG28_RB_EFF1_REQ_MASK 0x00008000
+#define MH_DEBUG_REG28_EFF1_WIN_MASK   0x00010000
+#define MH_DEBUG_REG28_KILL_EFF1_MASK  0x00020000
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_MASK 0x00040000
+#define MH_DEBUG_REG28_TC_ARB_HOLD_MASK 0x00080000
+#define MH_DEBUG_REG28_ARB_HOLD_MASK   0x00100000
+#define MH_DEBUG_REG28_ARB_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000
+
+#define MH_DEBUG_REG28_MASK \
+     (MH_DEBUG_REG28_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG28_ARB_WINNER_MASK | \
+      MH_DEBUG_REG28_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG28_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_ARB_QUAL_MASK | \
+      MH_DEBUG_REG28_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_EFF1_WIN_MASK | \
+      MH_DEBUG_REG28_KILL_EFF1_MASK | \
+      MH_DEBUG_REG28_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG28_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG28_ARB_HOLD_MASK | \
+      MH_DEBUG_REG28_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK)
+
+#define MH_DEBUG_REG28(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \
+     ((eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) | \
+      (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) | \
+      (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT))
+
+#define MH_DEBUG_REG28_GET_EFF1_WINNER(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WINNER_MASK) >> MH_DEBUG_REG28_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_WINNER(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_WINNER_MASK) >> MH_DEBUG_REG28_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG28_GET_CP_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_VGT_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_SEND_EFF1_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_RB_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_QUAL_MASK) >> MH_DEBUG_REG28_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_CP_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_VGT_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_RB_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_EFF1_WIN(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WIN_MASK) >> MH_DEBUG_REG28_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_GET_TCD_NEARFULL_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ARB_HOLD(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_HOLD(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_HOLD_MASK) >> MH_DEBUG_REG28_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_RTR_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_RTR_q_MASK) >> MH_DEBUG_REG28_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#define MH_DEBUG_REG28_SET_EFF1_WINNER(mh_debug_reg28_reg, eff1_winner) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_WINNER(mh_debug_reg28_reg, arb_winner) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG28_SET_CP_SEND_QUAL(mh_debug_reg28_reg, cp_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_VGT_SEND_QUAL(mh_debug_reg28_reg, vgt_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_SEND_QUAL(mh_debug_reg28_reg, tc_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_SEND_EFF1_QUAL(mh_debug_reg28_reg, tc_send_eff1_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_RB_SEND_QUAL(mh_debug_reg28_reg, rb_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_QUAL(mh_debug_reg28_reg, arb_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_CP_EFF1_REQ(mh_debug_reg28_reg, cp_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_VGT_EFF1_REQ(mh_debug_reg28_reg, vgt_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_EFF1_REQ(mh_debug_reg28_reg, tc_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_RB_EFF1_REQ(mh_debug_reg28_reg, rb_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_EFF1_WIN(mh_debug_reg28_reg, eff1_win) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_SET_TCD_NEARFULL_q(mh_debug_reg28_reg, tcd_nearfull_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ARB_HOLD(mh_debug_reg28_reg, tc_arb_hold) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_HOLD(mh_debug_reg28_reg, arb_hold) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_RTR_q(mh_debug_reg28_reg, arb_rtr_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28_reg, same_page_limit_count_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int eff1_winner                    : MH_DEBUG_REG28_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG28_ARB_WINNER_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG28_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG28_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG28_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG28_ARB_RTR_q_SIZE;
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+     } mh_debug_reg28_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG28_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG28_ARB_HOLD_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG28_EFF1_WIN_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG28_ARB_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG28_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG28_EFF1_WINNER_SIZE;
+     } mh_debug_reg28_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg28_t f;
+} mh_debug_reg28_u;
+
+
+/*
+ * MH_DEBUG_REG29 struct
+ */
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE 3
+#define MH_DEBUG_REG29_LEAST_RECENT_d_SIZE 3
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE 1
+#define MH_DEBUG_REG29_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG29_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG29_CLNT_REQ_SIZE   5
+#define MH_DEBUG_REG29_RECENT_d_0_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_1_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_2_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_3_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_4_SIZE 3
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT 0
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT 3
+#define MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT 6
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT 9
+#define MH_DEBUG_REG29_ARB_HOLD_SHIFT  10
+#define MH_DEBUG_REG29_ARB_RTR_q_SHIFT 11
+#define MH_DEBUG_REG29_CLNT_REQ_SHIFT  12
+#define MH_DEBUG_REG29_RECENT_d_0_SHIFT 17
+#define MH_DEBUG_REG29_RECENT_d_1_SHIFT 20
+#define MH_DEBUG_REG29_RECENT_d_2_SHIFT 23
+#define MH_DEBUG_REG29_RECENT_d_3_SHIFT 26
+#define MH_DEBUG_REG29_RECENT_d_4_SHIFT 29
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK 0x00000007
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK 0x00000038
+#define MH_DEBUG_REG29_LEAST_RECENT_d_MASK 0x000001c0
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK 0x00000200
+#define MH_DEBUG_REG29_ARB_HOLD_MASK   0x00000400
+#define MH_DEBUG_REG29_ARB_RTR_q_MASK  0x00000800
+#define MH_DEBUG_REG29_CLNT_REQ_MASK   0x0001f000
+#define MH_DEBUG_REG29_RECENT_d_0_MASK 0x000e0000
+#define MH_DEBUG_REG29_RECENT_d_1_MASK 0x00700000
+#define MH_DEBUG_REG29_RECENT_d_2_MASK 0x03800000
+#define MH_DEBUG_REG29_RECENT_d_3_MASK 0x1c000000
+#define MH_DEBUG_REG29_RECENT_d_4_MASK 0xe0000000
+
+#define MH_DEBUG_REG29_MASK \
+     (MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK | \
+      MH_DEBUG_REG29_LEAST_RECENT_d_MASK | \
+      MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK | \
+      MH_DEBUG_REG29_ARB_HOLD_MASK | \
+      MH_DEBUG_REG29_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG29_CLNT_REQ_MASK | \
+      MH_DEBUG_REG29_RECENT_d_0_MASK | \
+      MH_DEBUG_REG29_RECENT_d_1_MASK | \
+      MH_DEBUG_REG29_RECENT_d_2_MASK | \
+      MH_DEBUG_REG29_RECENT_d_3_MASK | \
+      MH_DEBUG_REG29_RECENT_d_4_MASK)
+
+#define MH_DEBUG_REG29(eff2_lru_winner_out, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3, recent_d_4) \
+     ((eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) | \
+      (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) | \
+      (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) | \
+      (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) | \
+      (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) | \
+      (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) | \
+      (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) | \
+      (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) | \
+      (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) | \
+      (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT))
+
+#define MH_DEBUG_REG29_GET_EFF2_LRU_WINNER_out(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG29_GET_LEAST_RECENT_INDEX_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG29_GET_LEAST_RECENT_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG29_GET_UPDATE_RECENT_STACK_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG29_GET_ARB_HOLD(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_HOLD_MASK) >> MH_DEBUG_REG29_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG29_GET_ARB_RTR_q(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_RTR_q_MASK) >> MH_DEBUG_REG29_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_GET_CLNT_REQ(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_CLNT_REQ_MASK) >> MH_DEBUG_REG29_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_0(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_0_MASK) >> MH_DEBUG_REG29_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_1(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_1_MASK) >> MH_DEBUG_REG29_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_2(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_2_MASK) >> MH_DEBUG_REG29_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_3(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_3_MASK) >> MH_DEBUG_REG29_RECENT_d_3_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_4(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_4_MASK) >> MH_DEBUG_REG29_RECENT_d_4_SHIFT)
+
+#define MH_DEBUG_REG29_SET_EFF2_LRU_WINNER_out(mh_debug_reg29_reg, eff2_lru_winner_out) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG29_SET_LEAST_RECENT_INDEX_d(mh_debug_reg29_reg, least_recent_index_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG29_SET_LEAST_RECENT_d(mh_debug_reg29_reg, least_recent_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG29_SET_UPDATE_RECENT_STACK_d(mh_debug_reg29_reg, update_recent_stack_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG29_SET_ARB_HOLD(mh_debug_reg29_reg, arb_hold) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG29_SET_ARB_RTR_q(mh_debug_reg29_reg, arb_rtr_q) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_SET_CLNT_REQ(mh_debug_reg29_reg, clnt_req) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_0(mh_debug_reg29_reg, recent_d_0) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_1(mh_debug_reg29_reg, recent_d_1) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_2(mh_debug_reg29_reg, recent_d_2) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_3(mh_debug_reg29_reg, recent_d_3) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_4(mh_debug_reg29_reg, recent_d_4) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_4_MASK) | (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG29_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG29_ARB_RTR_q_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG29_CLNT_REQ_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG29_RECENT_d_0_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG29_RECENT_d_1_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG29_RECENT_d_2_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG29_RECENT_d_3_SIZE;
+          unsigned int recent_d_4                     : MH_DEBUG_REG29_RECENT_d_4_SIZE;
+     } mh_debug_reg29_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int recent_d_4                     : MH_DEBUG_REG29_RECENT_d_4_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG29_RECENT_d_3_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG29_RECENT_d_2_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG29_RECENT_d_1_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG29_RECENT_d_0_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG29_CLNT_REQ_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG29_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG29_ARB_HOLD_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE;
+     } mh_debug_reg29_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg29_t f;
+} mh_debug_reg29_u;
+
+
+/*
+ * MH_DEBUG_REG30 struct
+ */
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG30_TCHOLD_IP_q_SIZE 1
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE 3
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG30_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE 7
+#define MH_DEBUG_REG30_WBURST_ACTIVE_SIZE 1
+#define MH_DEBUG_REG30_WLAST_q_SIZE    1
+#define MH_DEBUG_REG30_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG30_WBURST_CNT_q_SIZE 3
+#define MH_DEBUG_REG30_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG30_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_PA_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_ARB_WINNER_SIZE 3
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT 0
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT 1
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT 2
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT 3
+#define MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT 4
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT 5
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT 9
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT 10
+#define MH_DEBUG_REG30_TC_MH_written_SHIFT 11
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT 12
+#define MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT 19
+#define MH_DEBUG_REG30_WLAST_q_SHIFT   20
+#define MH_DEBUG_REG30_WBURST_IP_q_SHIFT 21
+#define MH_DEBUG_REG30_WBURST_CNT_q_SHIFT 22
+#define MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT 25
+#define MH_DEBUG_REG30_CP_MH_write_SHIFT 26
+#define MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT 27
+#define MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT 28
+#define MH_DEBUG_REG30_ARB_WINNER_SHIFT 29
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_MASK 0x00000001
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_MASK 0x00000008
+#define MH_DEBUG_REG30_TCHOLD_IP_q_MASK 0x00000010
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_MASK 0x000000e0
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK 0x00000200
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK 0x00000400
+#define MH_DEBUG_REG30_TC_MH_written_MASK 0x00000800
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK 0x0007f000
+#define MH_DEBUG_REG30_WBURST_ACTIVE_MASK 0x00080000
+#define MH_DEBUG_REG30_WLAST_q_MASK    0x00100000
+#define MH_DEBUG_REG30_WBURST_IP_q_MASK 0x00200000
+#define MH_DEBUG_REG30_WBURST_CNT_q_MASK 0x01c00000
+#define MH_DEBUG_REG30_CP_SEND_QUAL_MASK 0x02000000
+#define MH_DEBUG_REG30_CP_MH_write_MASK 0x04000000
+#define MH_DEBUG_REG30_RB_SEND_QUAL_MASK 0x08000000
+#define MH_DEBUG_REG30_PA_SEND_QUAL_MASK 0x10000000
+#define MH_DEBUG_REG30_ARB_WINNER_MASK 0xe0000000
+
+#define MH_DEBUG_REG30_MASK \
+     (MH_DEBUG_REG30_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG30_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG30_TCHOLD_IP_q_MASK | \
+      MH_DEBUG_REG30_TCHOLD_CNT_q_MASK | \
+      MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG30_TC_MH_written_MASK | \
+      MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK | \
+      MH_DEBUG_REG30_WBURST_ACTIVE_MASK | \
+      MH_DEBUG_REG30_WLAST_q_MASK | \
+      MH_DEBUG_REG30_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG30_WBURST_CNT_q_MASK | \
+      MH_DEBUG_REG30_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_CP_MH_write_MASK | \
+      MH_DEBUG_REG30_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_PA_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_ARB_WINNER_MASK)
+
+#define MH_DEBUG_REG30(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, pa_send_qual, arb_winner) \
+     ((tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) | \
+      (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \
+      (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) | \
+      (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) | \
+      (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) | \
+      (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) | \
+      (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) | \
+      (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) | \
+      (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT))
+
+#define MH_DEBUG_REG30_GET_TC_ARB_HOLD(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_GET_TCD_NEARFULL_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TCHOLD_IP_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TCHOLD_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_SEND_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_MH_written(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_MH_written_MASK) >> MH_DEBUG_REG30_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG30_GET_TCD_FULLNESS_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_ACTIVE(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG30_GET_WLAST_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WLAST_q_MASK) >> MH_DEBUG_REG30_WLAST_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_IP_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_IP_q_MASK) >> MH_DEBUG_REG30_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_CNT_q_MASK) >> MH_DEBUG_REG30_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_CP_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_CP_MH_write(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_CP_MH_write_MASK) >> MH_DEBUG_REG30_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG30_GET_RB_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_PA_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_ARB_WINNER(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_ARB_WINNER_MASK) >> MH_DEBUG_REG30_ARB_WINNER_SHIFT)
+
+#define MH_DEBUG_REG30_SET_TC_ARB_HOLD(mh_debug_reg30_reg, tc_arb_hold) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_noroq_same_row_bank) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_roq_same_row_bank) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_SET_TCD_NEARFULL_q(mh_debug_reg30_reg, tcd_nearfull_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TCHOLD_IP_q(mh_debug_reg30_reg, tchold_ip_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TCHOLD_CNT_q(mh_debug_reg30_reg, tchold_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30_reg, mh_arbiter_config_tc_reorder_enable) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg30_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_SEND_q(mh_debug_reg30_reg, tc_roq_send_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_MH_written(mh_debug_reg30_reg, tc_mh_written) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG30_SET_TCD_FULLNESS_CNT_q(mh_debug_reg30_reg, tcd_fullness_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_ACTIVE(mh_debug_reg30_reg, wburst_active) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG30_SET_WLAST_q(mh_debug_reg30_reg, wlast_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_IP_q(mh_debug_reg30_reg, wburst_ip_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_CNT_q(mh_debug_reg30_reg, wburst_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_CP_SEND_QUAL(mh_debug_reg30_reg, cp_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_CP_MH_write(mh_debug_reg30_reg, cp_mh_write) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG30_SET_RB_SEND_QUAL(mh_debug_reg30_reg, rb_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_PA_SEND_QUAL(mh_debug_reg30_reg, pa_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_ARB_WINNER(mh_debug_reg30_reg, arb_winner) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG30_TC_MH_written_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG30_WLAST_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG30_WBURST_IP_q_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG30_WBURST_CNT_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG30_CP_MH_write_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG30_ARB_WINNER_SIZE;
+     } mh_debug_reg30_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int arb_winner                     : MH_DEBUG_REG30_ARB_WINNER_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG30_CP_MH_write_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG30_WBURST_CNT_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG30_WBURST_IP_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG30_WLAST_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG30_TC_MH_written_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE;
+     } mh_debug_reg30_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg30_t f;
+} mh_debug_reg30_u;
+
+
+/*
+ * MH_DEBUG_REG31 struct
+ */
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE 26
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT 0
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK 0x03ffffff
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000
+
+#define MH_DEBUG_REG31_MASK \
+     (MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK | \
+      MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG31(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \
+     ((rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG31_GET_RF_ARBITER_CONFIG_q(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG31_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG31_SET_RF_ARBITER_CONFIG_q(mh_debug_reg31_reg, rf_arbiter_config_q) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG31_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg31_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int                                : 3;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE;
+     } mh_debug_reg31_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg31_t f;
+} mh_debug_reg31_u;
+
+
+/*
+ * MH_DEBUG_REG32 struct
+ */
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG32_ROQ_MARK_q_SIZE 8
+#define MH_DEBUG_REG32_ROQ_VALID_q_SIZE 8
+#define MH_DEBUG_REG32_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG32_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG32_ROQ_MARK_q_SHIFT 8
+#define MH_DEBUG_REG32_ROQ_VALID_q_SHIFT 16
+#define MH_DEBUG_REG32_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG32_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG32_ROQ_MARK_q_MASK 0x0000ff00
+#define MH_DEBUG_REG32_ROQ_VALID_q_MASK 0x00ff0000
+#define MH_DEBUG_REG32_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG32_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG32_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG32_MASK \
+     (MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG32_ROQ_MARK_q_MASK | \
+      MH_DEBUG_REG32_ROQ_VALID_q_MASK | \
+      MH_DEBUG_REG32_TC_MH_send_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG32_KILL_EFF1_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG32_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG32(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) | \
+      (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_MARK_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_VALID_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_GET_KILL_EFF1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_KILL_EFF1_MASK) >> MH_DEBUG_REG32_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG32_GET_ANY_SAME_ROW_BANK(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_EFF1_QUAL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_EMPTY(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_FULL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q(mh_debug_reg32_reg, same_row_bank_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_MARK_q(mh_debug_reg32_reg, roq_mark_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_VALID_q(mh_debug_reg32_reg, roq_valid_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_SET_KILL_EFF1(mh_debug_reg32_reg, kill_eff1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG32_SET_ANY_SAME_ROW_BANK(mh_debug_reg32_reg, any_same_row_bank) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_EFF1_QUAL(mh_debug_reg32_reg, tc_eff1_qual) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_EMPTY(mh_debug_reg32_reg, tc_roq_empty) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_FULL(mh_debug_reg32_reg, tc_roq_full) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG32_ROQ_MARK_q_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG32_ROQ_VALID_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG32_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg32_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG32_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG32_ROQ_VALID_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG32_ROQ_MARK_q_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg32_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg32_t f;
+} mh_debug_reg32_u;
+
+
+/*
+ * MH_DEBUG_REG33 struct
+ */
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG33_ROQ_MARK_d_SIZE 8
+#define MH_DEBUG_REG33_ROQ_VALID_d_SIZE 8
+#define MH_DEBUG_REG33_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG33_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG33_ROQ_MARK_d_SHIFT 8
+#define MH_DEBUG_REG33_ROQ_VALID_d_SHIFT 16
+#define MH_DEBUG_REG33_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG33_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG33_ROQ_MARK_d_MASK 0x0000ff00
+#define MH_DEBUG_REG33_ROQ_VALID_d_MASK 0x00ff0000
+#define MH_DEBUG_REG33_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG33_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG33_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG33_MASK \
+     (MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG33_ROQ_MARK_d_MASK | \
+      MH_DEBUG_REG33_ROQ_VALID_d_MASK | \
+      MH_DEBUG_REG33_TC_MH_send_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG33_KILL_EFF1_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG33_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG33(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) | \
+      (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_MARK_d(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_d_MASK) >> MH_DEBUG_REG33_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_VALID_d(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_d_MASK) >> MH_DEBUG_REG33_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_GET_KILL_EFF1(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_KILL_EFF1_MASK) >> MH_DEBUG_REG33_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG33_GET_ANY_SAME_ROW_BANK(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_EFF1_QUAL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_EMPTY(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_FULL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q(mh_debug_reg33_reg, same_row_bank_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_MARK_d(mh_debug_reg33_reg, roq_mark_d) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_VALID_d(mh_debug_reg33_reg, roq_valid_d) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_SET_KILL_EFF1(mh_debug_reg33_reg, kill_eff1) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG33_SET_ANY_SAME_ROW_BANK(mh_debug_reg33_reg, any_same_row_bank) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_EFF1_QUAL(mh_debug_reg33_reg, tc_eff1_qual) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_EMPTY(mh_debug_reg33_reg, tc_roq_empty) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_FULL(mh_debug_reg33_reg, tc_roq_full) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG33_ROQ_MARK_d_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG33_ROQ_VALID_d_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG33_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg33_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG33_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG33_ROQ_VALID_d_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG33_ROQ_MARK_d_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg33_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg33_t f;
+} mh_debug_reg33_u;
+
+
+/*
+ * MH_DEBUG_REG34 struct
+ */
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE 8
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT 0
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT 16
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT 24
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK 0x000000ff
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK 0x0000ff00
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK 0xff000000
+
+#define MH_DEBUG_REG34_MASK \
+     (MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK | \
+      MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK)
+
+#define MH_DEBUG_REG34(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \
+     ((same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) | \
+      (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) | \
+      (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) | \
+      (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT))
+
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_WIN(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_REQ(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, same_row_bank_win) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, same_row_bank_req) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, non_same_row_bank_win) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, non_same_row_bank_req) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int same_row_bank_win              : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE;
+     } mh_debug_reg34_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int same_row_bank_win              : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE;
+     } mh_debug_reg34_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg34_t f;
+} mh_debug_reg34_u;
+
+
+/*
+ * MH_DEBUG_REG35 struct
+ */
+
+#define MH_DEBUG_REG35_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE 1
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE 1
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE 1
+#define MH_DEBUG_REG35_ROQ_ADDR_0_SIZE 27
+
+#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT 2
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT 3
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT 4
+#define MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT 5
+
+#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_MASK 0x00000004
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_MASK 0x00000008
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK 0x00000010
+#define MH_DEBUG_REG35_ROQ_ADDR_0_MASK 0xffffffe0
+
+#define MH_DEBUG_REG35_MASK \
+     (MH_DEBUG_REG35_TC_MH_send_MASK | \
+      MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG35_ROQ_MARK_q_0_MASK | \
+      MH_DEBUG_REG35_ROQ_VALID_q_0_MASK | \
+      MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK | \
+      MH_DEBUG_REG35_ROQ_ADDR_0_MASK)
+
+#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \
+     ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) | \
+      (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) | \
+      (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) | \
+      (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT))
+
+#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_MARK_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_VALID_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_ADDR_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)
+
+#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_MARK_q_0(mh_debug_reg35_reg, roq_mark_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_VALID_q_0(mh_debug_reg35_reg, roq_valid_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_0(mh_debug_reg35_reg, same_row_bank_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_ADDR_0(mh_debug_reg35_reg, roq_addr_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_addr_0                     : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE;
+     } mh_debug_reg35_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int roq_addr_0                     : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+     } mh_debug_reg35_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg35_t f;
+} mh_debug_reg35_u;
+
+
+/*
+ * MH_DEBUG_REG36 struct
+ */
+
+#define MH_DEBUG_REG36_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE 1
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE 1
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE 1
+#define MH_DEBUG_REG36_ROQ_ADDR_1_SIZE 27
+
+#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT 2
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT 3
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT 4
+#define MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT 5
+
+#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_MASK 0x00000004
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_MASK 0x00000008
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK 0x00000010
+#define MH_DEBUG_REG36_ROQ_ADDR_1_MASK 0xffffffe0
+
+#define MH_DEBUG_REG36_MASK \
+     (MH_DEBUG_REG36_TC_MH_send_MASK | \
+      MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG36_ROQ_MARK_q_1_MASK | \
+      MH_DEBUG_REG36_ROQ_VALID_q_1_MASK | \
+      MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK | \
+      MH_DEBUG_REG36_ROQ_ADDR_1_MASK)
+
+#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \
+     ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) | \
+      (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) | \
+      (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) | \
+      (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT))
+
+#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_MARK_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_VALID_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_ADDR_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)
+
+#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_MARK_q_1(mh_debug_reg36_reg, roq_mark_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_VALID_q_1(mh_debug_reg36_reg, roq_valid_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_1(mh_debug_reg36_reg, same_row_bank_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_ADDR_1(mh_debug_reg36_reg, roq_addr_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_addr_1                     : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE;
+     } mh_debug_reg36_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int roq_addr_1                     : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+     } mh_debug_reg36_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg36_t f;
+} mh_debug_reg36_u;
+
+
+/*
+ * MH_DEBUG_REG37 struct
+ */
+
+#define MH_DEBUG_REG37_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE 1
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE 1
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE 1
+#define MH_DEBUG_REG37_ROQ_ADDR_2_SIZE 27
+
+#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT 2
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT 3
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT 4
+#define MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT 5
+
+#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_MASK 0x00000004
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_MASK 0x00000008
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK 0x00000010
+#define MH_DEBUG_REG37_ROQ_ADDR_2_MASK 0xffffffe0
+
+#define MH_DEBUG_REG37_MASK \
+     (MH_DEBUG_REG37_TC_MH_send_MASK | \
+      MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG37_ROQ_MARK_q_2_MASK | \
+      MH_DEBUG_REG37_ROQ_VALID_q_2_MASK | \
+      MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK | \
+      MH_DEBUG_REG37_ROQ_ADDR_2_MASK)
+
+#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \
+     ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) | \
+      (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) | \
+      (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) | \
+      (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT))
+
+#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_MARK_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_VALID_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_ADDR_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)
+
+#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_MARK_q_2(mh_debug_reg37_reg, roq_mark_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_VALID_q_2(mh_debug_reg37_reg, roq_valid_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_2(mh_debug_reg37_reg, same_row_bank_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_ADDR_2(mh_debug_reg37_reg, roq_addr_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_addr_2                     : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE;
+     } mh_debug_reg37_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int roq_addr_2                     : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+     } mh_debug_reg37_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg37_t f;
+} mh_debug_reg37_u;
+
+
+/*
+ * MH_DEBUG_REG38 struct
+ */
+
+#define MH_DEBUG_REG38_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE 1
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE 1
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE 1
+#define MH_DEBUG_REG38_ROQ_ADDR_3_SIZE 27
+
+#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT 2
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT 3
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT 4
+#define MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT 5
+
+#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_MASK 0x00000004
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_MASK 0x00000008
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK 0x00000010
+#define MH_DEBUG_REG38_ROQ_ADDR_3_MASK 0xffffffe0
+
+#define MH_DEBUG_REG38_MASK \
+     (MH_DEBUG_REG38_TC_MH_send_MASK | \
+      MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG38_ROQ_MARK_q_3_MASK | \
+      MH_DEBUG_REG38_ROQ_VALID_q_3_MASK | \
+      MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK | \
+      MH_DEBUG_REG38_ROQ_ADDR_3_MASK)
+
+#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \
+     ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) | \
+      (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) | \
+      (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) | \
+      (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT))
+
+#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_MARK_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_VALID_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_ADDR_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)
+
+#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_MARK_q_3(mh_debug_reg38_reg, roq_mark_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_VALID_q_3(mh_debug_reg38_reg, roq_valid_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_3(mh_debug_reg38_reg, same_row_bank_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_ADDR_3(mh_debug_reg38_reg, roq_addr_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_addr_3                     : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE;
+     } mh_debug_reg38_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int roq_addr_3                     : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+     } mh_debug_reg38_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg38_t f;
+} mh_debug_reg38_u;
+
+
+/*
+ * MH_DEBUG_REG39 struct
+ */
+
+#define MH_DEBUG_REG39_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE 1
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE 1
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE 1
+#define MH_DEBUG_REG39_ROQ_ADDR_4_SIZE 27
+
+#define MH_DEBUG_REG39_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT 2
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT 3
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT 4
+#define MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT 5
+
+#define MH_DEBUG_REG39_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_MASK 0x00000004
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_MASK 0x00000008
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK 0x00000010
+#define MH_DEBUG_REG39_ROQ_ADDR_4_MASK 0xffffffe0
+
+#define MH_DEBUG_REG39_MASK \
+     (MH_DEBUG_REG39_TC_MH_send_MASK | \
+      MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG39_ROQ_MARK_q_4_MASK | \
+      MH_DEBUG_REG39_ROQ_VALID_q_4_MASK | \
+      MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK | \
+      MH_DEBUG_REG39_ROQ_ADDR_4_MASK)
+
+#define MH_DEBUG_REG39(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \
+     ((tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) | \
+      (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) | \
+      (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) | \
+      (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT))
+
+#define MH_DEBUG_REG39_GET_TC_MH_send(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_TC_MH_send_MASK) >> MH_DEBUG_REG39_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG39_GET_TC_ROQ_RTR_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_MARK_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_VALID_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_SAME_ROW_BANK_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_ADDR_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)
+
+#define MH_DEBUG_REG39_SET_TC_MH_send(mh_debug_reg39_reg, tc_mh_send) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG39_SET_TC_ROQ_RTR_q(mh_debug_reg39_reg, tc_roq_rtr_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_MARK_q_4(mh_debug_reg39_reg, roq_mark_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_VALID_q_4(mh_debug_reg39_reg, roq_valid_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_SAME_ROW_BANK_q_4(mh_debug_reg39_reg, same_row_bank_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_ADDR_4(mh_debug_reg39_reg, roq_addr_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG39_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_addr_4                     : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE;
+     } mh_debug_reg39_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int roq_addr_4                     : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG39_TC_MH_send_SIZE;
+     } mh_debug_reg39_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg39_t f;
+} mh_debug_reg39_u;
+
+
+/*
+ * MH_DEBUG_REG40 struct
+ */
+
+#define MH_DEBUG_REG40_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE 1
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE 1
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE 1
+#define MH_DEBUG_REG40_ROQ_ADDR_5_SIZE 27
+
+#define MH_DEBUG_REG40_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT 2
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT 3
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT 4
+#define MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT 5
+
+#define MH_DEBUG_REG40_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_MASK 0x00000004
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_MASK 0x00000008
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK 0x00000010
+#define MH_DEBUG_REG40_ROQ_ADDR_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG40_MASK \
+     (MH_DEBUG_REG40_TC_MH_send_MASK | \
+      MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG40_ROQ_MARK_q_5_MASK | \
+      MH_DEBUG_REG40_ROQ_VALID_q_5_MASK | \
+      MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK | \
+      MH_DEBUG_REG40_ROQ_ADDR_5_MASK)
+
+#define MH_DEBUG_REG40(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \
+     ((tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) | \
+      (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) | \
+      (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) | \
+      (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT))
+
+#define MH_DEBUG_REG40_GET_TC_MH_send(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_TC_MH_send_MASK) >> MH_DEBUG_REG40_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG40_GET_TC_ROQ_RTR_q(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_MARK_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_VALID_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_SAME_ROW_BANK_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_ADDR_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)
+
+#define MH_DEBUG_REG40_SET_TC_MH_send(mh_debug_reg40_reg, tc_mh_send) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG40_SET_TC_ROQ_RTR_q(mh_debug_reg40_reg, tc_roq_rtr_q) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_MARK_q_5(mh_debug_reg40_reg, roq_mark_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_VALID_q_5(mh_debug_reg40_reg, roq_valid_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_SAME_ROW_BANK_q_5(mh_debug_reg40_reg, same_row_bank_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_ADDR_5(mh_debug_reg40_reg, roq_addr_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG40_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_addr_5                     : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE;
+     } mh_debug_reg40_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int roq_addr_5                     : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG40_TC_MH_send_SIZE;
+     } mh_debug_reg40_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg40_t f;
+} mh_debug_reg40_u;
+
+
+/*
+ * MH_DEBUG_REG41 struct
+ */
+
+#define MH_DEBUG_REG41_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE 1
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE 1
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE 1
+#define MH_DEBUG_REG41_ROQ_ADDR_6_SIZE 27
+
+#define MH_DEBUG_REG41_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT 2
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT 3
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT 4
+#define MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT 5
+
+#define MH_DEBUG_REG41_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_MASK 0x00000004
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_MASK 0x00000008
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK 0x00000010
+#define MH_DEBUG_REG41_ROQ_ADDR_6_MASK 0xffffffe0
+
+#define MH_DEBUG_REG41_MASK \
+     (MH_DEBUG_REG41_TC_MH_send_MASK | \
+      MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG41_ROQ_MARK_q_6_MASK | \
+      MH_DEBUG_REG41_ROQ_VALID_q_6_MASK | \
+      MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK | \
+      MH_DEBUG_REG41_ROQ_ADDR_6_MASK)
+
+#define MH_DEBUG_REG41(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \
+     ((tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) | \
+      (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) | \
+      (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) | \
+      (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT))
+
+#define MH_DEBUG_REG41_GET_TC_MH_send(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_TC_MH_send_MASK) >> MH_DEBUG_REG41_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG41_GET_TC_ROQ_RTR_q(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_MARK_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_VALID_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_SAME_ROW_BANK_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_ADDR_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)
+
+#define MH_DEBUG_REG41_SET_TC_MH_send(mh_debug_reg41_reg, tc_mh_send) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG41_SET_TC_ROQ_RTR_q(mh_debug_reg41_reg, tc_roq_rtr_q) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_MARK_q_6(mh_debug_reg41_reg, roq_mark_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_VALID_q_6(mh_debug_reg41_reg, roq_valid_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_SAME_ROW_BANK_q_6(mh_debug_reg41_reg, same_row_bank_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_ADDR_6(mh_debug_reg41_reg, roq_addr_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG41_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_addr_6                     : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE;
+     } mh_debug_reg41_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int roq_addr_6                     : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG41_TC_MH_send_SIZE;
+     } mh_debug_reg41_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg41_t f;
+} mh_debug_reg41_u;
+
+
+/*
+ * MH_DEBUG_REG42 struct
+ */
+
+#define MH_DEBUG_REG42_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE 1
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE 1
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE 1
+#define MH_DEBUG_REG42_ROQ_ADDR_7_SIZE 27
+
+#define MH_DEBUG_REG42_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT 2
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT 3
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT 4
+#define MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT 5
+
+#define MH_DEBUG_REG42_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_MASK 0x00000004
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_MASK 0x00000008
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK 0x00000010
+#define MH_DEBUG_REG42_ROQ_ADDR_7_MASK 0xffffffe0
+
+#define MH_DEBUG_REG42_MASK \
+     (MH_DEBUG_REG42_TC_MH_send_MASK | \
+      MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG42_ROQ_MARK_q_7_MASK | \
+      MH_DEBUG_REG42_ROQ_VALID_q_7_MASK | \
+      MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK | \
+      MH_DEBUG_REG42_ROQ_ADDR_7_MASK)
+
+#define MH_DEBUG_REG42(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \
+     ((tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) | \
+      (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) | \
+      (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) | \
+      (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT))
+
+#define MH_DEBUG_REG42_GET_TC_MH_send(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_TC_MH_send_MASK) >> MH_DEBUG_REG42_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG42_GET_TC_ROQ_RTR_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_MARK_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_VALID_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_SAME_ROW_BANK_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_ADDR_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)
+
+#define MH_DEBUG_REG42_SET_TC_MH_send(mh_debug_reg42_reg, tc_mh_send) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG42_SET_TC_ROQ_RTR_q(mh_debug_reg42_reg, tc_roq_rtr_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_MARK_q_7(mh_debug_reg42_reg, roq_mark_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_VALID_q_7(mh_debug_reg42_reg, roq_valid_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_SAME_ROW_BANK_q_7(mh_debug_reg42_reg, same_row_bank_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_ADDR_7(mh_debug_reg42_reg, roq_addr_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG42_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_addr_7                     : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE;
+     } mh_debug_reg42_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int roq_addr_7                     : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG42_TC_MH_send_SIZE;
+     } mh_debug_reg42_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg42_t f;
+} mh_debug_reg42_u;
+
+
+/*
+ * MH_DEBUG_REG43 struct
+ */
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_WE_SIZE     1
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG43_ARB_REG_RTR_SIZE 1
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE 1
+#define MH_DEBUG_REG43_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG43_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG43_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_BLEN_q_SIZE 1
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE 3
+#define MH_DEBUG_REG43_MMU_WE_SIZE     1
+#define MH_DEBUG_REG43_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG43_MMU_ID_SIZE     3
+#define MH_DEBUG_REG43_MMU_WRITE_SIZE  1
+#define MH_DEBUG_REG43_MMU_BLEN_SIZE   1
+#define MH_DEBUG_REG43_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG43_WDB_WE_SIZE     1
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE 1
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE 1
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT 0
+#define MH_DEBUG_REG43_ARB_WE_SHIFT    1
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT 2
+#define MH_DEBUG_REG43_ARB_RTR_q_SHIFT 3
+#define MH_DEBUG_REG43_ARB_REG_RTR_SHIFT 4
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT 5
+#define MH_DEBUG_REG43_MMU_RTR_SHIFT   6
+#define MH_DEBUG_REG43_ARB_ID_q_SHIFT  7
+#define MH_DEBUG_REG43_ARB_WRITE_q_SHIFT 10
+#define MH_DEBUG_REG43_ARB_BLEN_q_SHIFT 11
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT 12
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT 13
+#define MH_DEBUG_REG43_MMU_WE_SHIFT    16
+#define MH_DEBUG_REG43_ARQ_RTR_SHIFT   17
+#define MH_DEBUG_REG43_MMU_ID_SHIFT    18
+#define MH_DEBUG_REG43_MMU_WRITE_SHIFT 21
+#define MH_DEBUG_REG43_MMU_BLEN_SHIFT  22
+#define MH_DEBUG_REG43_WBURST_IP_q_SHIFT 23
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT 24
+#define MH_DEBUG_REG43_WDB_WE_SHIFT    25
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT 26
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT 27
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_MASK 0x00000001
+#define MH_DEBUG_REG43_ARB_WE_MASK     0x00000002
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_MASK 0x00000004
+#define MH_DEBUG_REG43_ARB_RTR_q_MASK  0x00000008
+#define MH_DEBUG_REG43_ARB_REG_RTR_MASK 0x00000010
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_MASK 0x00000020
+#define MH_DEBUG_REG43_MMU_RTR_MASK    0x00000040
+#define MH_DEBUG_REG43_ARB_ID_q_MASK   0x00000380
+#define MH_DEBUG_REG43_ARB_WRITE_q_MASK 0x00000400
+#define MH_DEBUG_REG43_ARB_BLEN_q_MASK 0x00000800
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK 0x00001000
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK 0x0000e000
+#define MH_DEBUG_REG43_MMU_WE_MASK     0x00010000
+#define MH_DEBUG_REG43_ARQ_RTR_MASK    0x00020000
+#define MH_DEBUG_REG43_MMU_ID_MASK     0x001c0000
+#define MH_DEBUG_REG43_MMU_WRITE_MASK  0x00200000
+#define MH_DEBUG_REG43_MMU_BLEN_MASK   0x00400000
+#define MH_DEBUG_REG43_WBURST_IP_q_MASK 0x00800000
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_MASK 0x01000000
+#define MH_DEBUG_REG43_WDB_WE_MASK     0x02000000
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK 0x04000000
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK 0x08000000
+
+#define MH_DEBUG_REG43_MASK \
+     (MH_DEBUG_REG43_ARB_REG_WE_q_MASK | \
+      MH_DEBUG_REG43_ARB_WE_MASK | \
+      MH_DEBUG_REG43_ARB_REG_VALID_q_MASK | \
+      MH_DEBUG_REG43_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG43_ARB_REG_RTR_MASK | \
+      MH_DEBUG_REG43_WDAT_BURST_RTR_MASK | \
+      MH_DEBUG_REG43_MMU_RTR_MASK | \
+      MH_DEBUG_REG43_ARB_ID_q_MASK | \
+      MH_DEBUG_REG43_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG43_ARB_BLEN_q_MASK | \
+      MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG43_MMU_WE_MASK | \
+      MH_DEBUG_REG43_ARQ_RTR_MASK | \
+      MH_DEBUG_REG43_MMU_ID_MASK | \
+      MH_DEBUG_REG43_MMU_WRITE_MASK | \
+      MH_DEBUG_REG43_MMU_BLEN_MASK | \
+      MH_DEBUG_REG43_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG43_WDAT_REG_WE_q_MASK | \
+      MH_DEBUG_REG43_WDB_WE_MASK | \
+      MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK | \
+      MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK)
+
+#define MH_DEBUG_REG43(arb_reg_we_q, arb_we, arb_reg_valid_q, arb_rtr_q, arb_reg_rtr, wdat_burst_rtr, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen, wburst_ip_q, wdat_reg_we_q, wdb_we, wdb_rtr_skid_4, wdb_rtr_skid_3) \
+     ((arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) | \
+      (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) | \
+      (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) | \
+      (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) | \
+      (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) | \
+      (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) | \
+      (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) | \
+      (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) | \
+      (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) | \
+      (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) | \
+      (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) | \
+      (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) | \
+      (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT))
+
+#define MH_DEBUG_REG43_GET_ARB_REG_WE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_WE_q_MASK) >> MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WE_MASK) >> MH_DEBUG_REG43_ARB_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_REG_VALID_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) >> MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_RTR_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_RTR_q_MASK) >> MH_DEBUG_REG43_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_REG_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_RTR_MASK) >> MH_DEBUG_REG43_ARB_REG_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_WDAT_BURST_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) >> MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_RTR_MASK) >> MH_DEBUG_REG43_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_ID_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_ID_q_MASK) >> MH_DEBUG_REG43_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_WRITE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WRITE_q_MASK) >> MH_DEBUG_REG43_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_BLEN_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_BLEN_q_MASK) >> MH_DEBUG_REG43_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_CTRL_EMPTY(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_FIFO_CNT_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WE_MASK) >> MH_DEBUG_REG43_MMU_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_RTR_MASK) >> MH_DEBUG_REG43_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_ID(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_ID_MASK) >> MH_DEBUG_REG43_MMU_ID_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_WRITE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WRITE_MASK) >> MH_DEBUG_REG43_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_BLEN(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_BLEN_MASK) >> MH_DEBUG_REG43_MMU_BLEN_SHIFT)
+#define MH_DEBUG_REG43_GET_WBURST_IP_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WBURST_IP_q_MASK) >> MH_DEBUG_REG43_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG43_GET_WDAT_REG_WE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_WE_MASK) >> MH_DEBUG_REG43_WDB_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_4(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_3(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)
+
+#define MH_DEBUG_REG43_SET_ARB_REG_WE_q(mh_debug_reg43_reg, arb_reg_we_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_WE_q_MASK) | (arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_WE(mh_debug_reg43_reg, arb_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_REG_VALID_q(mh_debug_reg43_reg, arb_reg_valid_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) | (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_RTR_q(mh_debug_reg43_reg, arb_rtr_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_REG_RTR(mh_debug_reg43_reg, arb_reg_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_RTR_MASK) | (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_WDAT_BURST_RTR(mh_debug_reg43_reg, wdat_burst_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) | (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_RTR(mh_debug_reg43_reg, mmu_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_ID_q(mh_debug_reg43_reg, arb_id_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_WRITE_q(mh_debug_reg43_reg, arb_write_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_BLEN_q(mh_debug_reg43_reg, arb_blen_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_CTRL_EMPTY(mh_debug_reg43_reg, arq_ctrl_empty) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_FIFO_CNT_q(mh_debug_reg43_reg, arq_fifo_cnt_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_WE(mh_debug_reg43_reg, mmu_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_RTR(mh_debug_reg43_reg, arq_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_ID(mh_debug_reg43_reg, mmu_id) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_WRITE(mh_debug_reg43_reg, mmu_write) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_BLEN(mh_debug_reg43_reg, mmu_blen) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT)
+#define MH_DEBUG_REG43_SET_WBURST_IP_q(mh_debug_reg43_reg, wburst_ip_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG43_SET_WDAT_REG_WE_q(mh_debug_reg43_reg, wdat_reg_we_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_WE(mh_debug_reg43_reg, wdb_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_4(mh_debug_reg43_reg, wdb_rtr_skid_4) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_3(mh_debug_reg43_reg, wdb_rtr_skid_3) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) | (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int arb_reg_we_q                   : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG43_ARB_WE_SIZE;
+          unsigned int arb_reg_valid_q                : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG43_ARB_RTR_q_SIZE;
+          unsigned int arb_reg_rtr                    : MH_DEBUG_REG43_ARB_REG_RTR_SIZE;
+          unsigned int wdat_burst_rtr                 : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG43_MMU_RTR_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG43_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG43_ARB_WRITE_q_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG43_ARB_BLEN_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG43_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG43_ARQ_RTR_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG43_MMU_ID_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG43_MMU_WRITE_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG43_MMU_BLEN_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG43_WBURST_IP_q_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG43_WDB_WE_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdb_rtr_skid_3                 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE;
+          unsigned int                                : 4;
+     } mh_debug_reg43_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int                                : 4;
+          unsigned int wdb_rtr_skid_3                 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG43_WDB_WE_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG43_WBURST_IP_q_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG43_MMU_BLEN_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG43_MMU_WRITE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG43_MMU_ID_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG43_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG43_MMU_WE_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG43_ARB_BLEN_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG43_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG43_ARB_ID_q_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG43_MMU_RTR_SIZE;
+          unsigned int wdat_burst_rtr                 : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE;
+          unsigned int arb_reg_rtr                    : MH_DEBUG_REG43_ARB_REG_RTR_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG43_ARB_RTR_q_SIZE;
+          unsigned int arb_reg_valid_q                : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG43_ARB_WE_SIZE;
+          unsigned int arb_reg_we_q                   : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE;
+     } mh_debug_reg43_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg43_t f;
+} mh_debug_reg43_u;
+
+
+/*
+ * MH_DEBUG_REG44 struct
+ */
+
+#define MH_DEBUG_REG44_ARB_WE_SIZE     1
+#define MH_DEBUG_REG44_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG44_ARB_VAD_q_SIZE  28
+
+#define MH_DEBUG_REG44_ARB_WE_SHIFT    0
+#define MH_DEBUG_REG44_ARB_ID_q_SHIFT  1
+#define MH_DEBUG_REG44_ARB_VAD_q_SHIFT 4
+
+#define MH_DEBUG_REG44_ARB_WE_MASK     0x00000001
+#define MH_DEBUG_REG44_ARB_ID_q_MASK   0x0000000e
+#define MH_DEBUG_REG44_ARB_VAD_q_MASK  0xfffffff0
+
+#define MH_DEBUG_REG44_MASK \
+     (MH_DEBUG_REG44_ARB_WE_MASK | \
+      MH_DEBUG_REG44_ARB_ID_q_MASK | \
+      MH_DEBUG_REG44_ARB_VAD_q_MASK)
+
+#define MH_DEBUG_REG44(arb_we, arb_id_q, arb_vad_q) \
+     ((arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) | \
+      (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT))
+
+#define MH_DEBUG_REG44_GET_ARB_WE(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WE_MASK) >> MH_DEBUG_REG44_ARB_WE_SHIFT)
+#define MH_DEBUG_REG44_GET_ARB_ID_q(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_ID_q_MASK) >> MH_DEBUG_REG44_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG44_GET_ARB_VAD_q(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_VAD_q_MASK) >> MH_DEBUG_REG44_ARB_VAD_q_SHIFT)
+
+#define MH_DEBUG_REG44_SET_ARB_WE(mh_debug_reg44_reg, arb_we) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT)
+#define MH_DEBUG_REG44_SET_ARB_ID_q(mh_debug_reg44_reg, arb_id_q) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG44_SET_ARB_VAD_q(mh_debug_reg44_reg, arb_vad_q) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_we                         : MH_DEBUG_REG44_ARB_WE_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG44_ARB_ID_q_SIZE;
+          unsigned int arb_vad_q                      : MH_DEBUG_REG44_ARB_VAD_q_SIZE;
+     } mh_debug_reg44_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_vad_q                      : MH_DEBUG_REG44_ARB_VAD_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG44_ARB_ID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG44_ARB_WE_SIZE;
+     } mh_debug_reg44_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg44_t f;
+} mh_debug_reg44_u;
+
+
+/*
+ * MH_DEBUG_REG45 struct
+ */
+
+#define MH_DEBUG_REG45_MMU_WE_SIZE     1
+#define MH_DEBUG_REG45_MMU_ID_SIZE     3
+#define MH_DEBUG_REG45_MMU_PAD_SIZE    28
+
+#define MH_DEBUG_REG45_MMU_WE_SHIFT    0
+#define MH_DEBUG_REG45_MMU_ID_SHIFT    1
+#define MH_DEBUG_REG45_MMU_PAD_SHIFT   4
+
+#define MH_DEBUG_REG45_MMU_WE_MASK     0x00000001
+#define MH_DEBUG_REG45_MMU_ID_MASK     0x0000000e
+#define MH_DEBUG_REG45_MMU_PAD_MASK    0xfffffff0
+
+#define MH_DEBUG_REG45_MASK \
+     (MH_DEBUG_REG45_MMU_WE_MASK | \
+      MH_DEBUG_REG45_MMU_ID_MASK | \
+      MH_DEBUG_REG45_MMU_PAD_MASK)
+
+#define MH_DEBUG_REG45(mmu_we, mmu_id, mmu_pad) \
+     ((mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) | \
+      (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT))
+
+#define MH_DEBUG_REG45_GET_MMU_WE(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_WE_MASK) >> MH_DEBUG_REG45_MMU_WE_SHIFT)
+#define MH_DEBUG_REG45_GET_MMU_ID(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_ID_MASK) >> MH_DEBUG_REG45_MMU_ID_SHIFT)
+#define MH_DEBUG_REG45_GET_MMU_PAD(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_PAD_MASK) >> MH_DEBUG_REG45_MMU_PAD_SHIFT)
+
+#define MH_DEBUG_REG45_SET_MMU_WE(mh_debug_reg45_reg, mmu_we) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT)
+#define MH_DEBUG_REG45_SET_MMU_ID(mh_debug_reg45_reg, mmu_id) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT)
+#define MH_DEBUG_REG45_SET_MMU_PAD(mh_debug_reg45_reg, mmu_pad) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int mmu_we                         : MH_DEBUG_REG45_MMU_WE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG45_MMU_ID_SIZE;
+          unsigned int mmu_pad                        : MH_DEBUG_REG45_MMU_PAD_SIZE;
+     } mh_debug_reg45_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int mmu_pad                        : MH_DEBUG_REG45_MMU_PAD_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG45_MMU_ID_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG45_MMU_WE_SIZE;
+     } mh_debug_reg45_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg45_t f;
+} mh_debug_reg45_u;
+
+
+/*
+ * MH_DEBUG_REG46 struct
+ */
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_WE_SIZE     1
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE 1
+#define MH_DEBUG_REG46_ARB_WSTRB_q_SIZE 8
+#define MH_DEBUG_REG46_ARB_WLAST_SIZE  1
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE 5
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_WDC_WID_SIZE 3
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE 1
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE 8
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT 0
+#define MH_DEBUG_REG46_WDB_WE_SHIFT    1
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT 2
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT 3
+#define MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT 4
+#define MH_DEBUG_REG46_ARB_WLAST_SHIFT 12
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT 13
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT 14
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT 19
+#define MH_DEBUG_REG46_WDB_WDC_WID_SHIFT 20
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT 23
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT 24
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_MASK 0x00000001
+#define MH_DEBUG_REG46_WDB_WE_MASK     0x00000002
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK 0x00000004
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK 0x00000008
+#define MH_DEBUG_REG46_ARB_WSTRB_q_MASK 0x00000ff0
+#define MH_DEBUG_REG46_ARB_WLAST_MASK  0x00001000
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK 0x00002000
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK 0x0007c000
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_MASK 0x00080000
+#define MH_DEBUG_REG46_WDB_WDC_WID_MASK 0x00700000
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_MASK 0x00800000
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK 0xff000000
+
+#define MH_DEBUG_REG46_MASK \
+     (MH_DEBUG_REG46_WDAT_REG_WE_q_MASK | \
+      MH_DEBUG_REG46_WDB_WE_MASK | \
+      MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK | \
+      MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK | \
+      MH_DEBUG_REG46_ARB_WSTRB_q_MASK | \
+      MH_DEBUG_REG46_ARB_WLAST_MASK | \
+      MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG46_WDC_WDB_RE_q_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WID_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WLAST_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK)
+
+#define MH_DEBUG_REG46(wdat_reg_we_q, wdb_we, wdat_reg_valid_q, wdb_rtr_skid_4, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \
+     ((wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) | \
+      (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) | \
+      (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) | \
+      (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) | \
+      (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) | \
+      (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) | \
+      (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) | \
+      (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) | \
+      (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) | \
+      (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) | \
+      (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) | \
+      (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT))
+
+#define MH_DEBUG_REG46_GET_WDAT_REG_WE_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WE(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WE_MASK) >> MH_DEBUG_REG46_WDB_WE_SHIFT)
+#define MH_DEBUG_REG46_GET_WDAT_REG_VALID_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_RTR_SKID_4(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG46_GET_ARB_WSTRB_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG46_GET_ARB_WLAST(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WLAST_MASK) >> MH_DEBUG_REG46_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_CTRL_EMPTY(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_FIFO_CNT_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDC_WDB_RE_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WID(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WID_MASK) >> MH_DEBUG_REG46_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WLAST(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WSTRB(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)
+
+#define MH_DEBUG_REG46_SET_WDAT_REG_WE_q(mh_debug_reg46_reg, wdat_reg_we_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WE(mh_debug_reg46_reg, wdb_we) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT)
+#define MH_DEBUG_REG46_SET_WDAT_REG_VALID_q(mh_debug_reg46_reg, wdat_reg_valid_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) | (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_RTR_SKID_4(mh_debug_reg46_reg, wdb_rtr_skid_4) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG46_SET_ARB_WSTRB_q(mh_debug_reg46_reg, arb_wstrb_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG46_SET_ARB_WLAST(mh_debug_reg46_reg, arb_wlast) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_CTRL_EMPTY(mh_debug_reg46_reg, wdb_ctrl_empty) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_FIFO_CNT_q(mh_debug_reg46_reg, wdb_fifo_cnt_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDC_WDB_RE_q(mh_debug_reg46_reg, wdc_wdb_re_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WID(mh_debug_reg46_reg, wdb_wdc_wid) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WLAST(mh_debug_reg46_reg, wdb_wdc_wlast) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WSTRB(mh_debug_reg46_reg, wdb_wdc_wstrb) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG46_WDB_WE_SIZE;
+          unsigned int wdat_reg_valid_q               : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG46_ARB_WLAST_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG46_WDB_WDC_WID_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE;
+     } mh_debug_reg46_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG46_WDB_WDC_WID_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG46_ARB_WLAST_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdat_reg_valid_q               : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG46_WDB_WE_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE;
+     } mh_debug_reg46_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg46_t f;
+} mh_debug_reg46_u;
+
+
+/*
+ * MH_DEBUG_REG47 struct
+ */
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE 32
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT 0
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG47_MASK \
+     (MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK)
+
+#define MH_DEBUG_REG47(wdb_wdc_wdata_31_0) \
+     ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT))
+
+#define MH_DEBUG_REG47_GET_WDB_WDC_WDATA_31_0(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)
+
+#define MH_DEBUG_REG47_SET_WDB_WDC_WDATA_31_0(mh_debug_reg47_reg, wdb_wdc_wdata_31_0) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg47_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg47_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg47_t f;
+} mh_debug_reg47_u;
+
+
+/*
+ * MH_DEBUG_REG48 struct
+ */
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE 32
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT 0
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG48_MASK \
+     (MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK)
+
+#define MH_DEBUG_REG48(wdb_wdc_wdata_63_32) \
+     ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT))
+
+#define MH_DEBUG_REG48_GET_WDB_WDC_WDATA_63_32(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)
+
+#define MH_DEBUG_REG48_SET_WDB_WDC_WDATA_63_32(mh_debug_reg48_reg, wdb_wdc_wdata_63_32) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg48_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg48_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg48_t f;
+} mh_debug_reg48_u;
+
+
+/*
+ * MH_DEBUG_REG49 struct
+ */
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE 1
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE 1
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE 6
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG49_RVALID_q_SIZE   1
+#define MH_DEBUG_REG49_RREADY_q_SIZE   1
+#define MH_DEBUG_REG49_RLAST_q_SIZE    1
+#define MH_DEBUG_REG49_BVALID_q_SIZE   1
+#define MH_DEBUG_REG49_BREADY_q_SIZE   1
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT 0
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT 1
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT 2
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT 3
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT 4
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT 5
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT 6
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT 7
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT 13
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT 14
+#define MH_DEBUG_REG49_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG49_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG49_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG49_BVALID_q_SHIFT  18
+#define MH_DEBUG_REG49_BREADY_q_SHIFT  19
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK 0x00000001
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK 0x00000002
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK 0x00000004
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK 0x00000008
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK 0x00000010
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK 0x00000020
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_MASK 0x00000040
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK 0x00001f80
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK 0x00004000
+#define MH_DEBUG_REG49_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG49_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG49_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG49_BVALID_q_MASK   0x00040000
+#define MH_DEBUG_REG49_BREADY_q_MASK   0x00080000
+
+#define MH_DEBUG_REG49_MASK \
+     (MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK | \
+      MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK | \
+      MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK | \
+      MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG49_INFLT_LIMIT_q_MASK | \
+      MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK | \
+      MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG49_RVALID_q_MASK | \
+      MH_DEBUG_REG49_RREADY_q_MASK | \
+      MH_DEBUG_REG49_RLAST_q_MASK | \
+      MH_DEBUG_REG49_BVALID_q_MASK | \
+      MH_DEBUG_REG49_BREADY_q_MASK)
+
+#define MH_DEBUG_REG49(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \
+     ((ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) | \
+      (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) | \
+      (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) | \
+      (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) | \
+      (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT))
+
+#define MH_DEBUG_REG49_GET_CTRL_ARC_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_CTRL_RARC_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_ARQ_CTRL_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_ARQ_CTRL_WRITE(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG49_GET_TLBMISS_CTRL_RTS(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG49_GET_CTRL_TLBMISS_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_INFLT_LIMIT_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG49_GET_INFLT_LIMIT_CNT_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG49_GET_ARC_CTRL_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RARC_CTRL_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RVALID_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RVALID_q_MASK) >> MH_DEBUG_REG49_RVALID_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RREADY_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RREADY_q_MASK) >> MH_DEBUG_REG49_RREADY_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RLAST_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RLAST_q_MASK) >> MH_DEBUG_REG49_RLAST_q_SHIFT)
+#define MH_DEBUG_REG49_GET_BVALID_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_BVALID_q_MASK) >> MH_DEBUG_REG49_BVALID_q_SHIFT)
+#define MH_DEBUG_REG49_GET_BREADY_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_BREADY_q_MASK) >> MH_DEBUG_REG49_BREADY_q_SHIFT)
+
+#define MH_DEBUG_REG49_SET_CTRL_ARC_EMPTY(mh_debug_reg49_reg, ctrl_arc_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_CTRL_RARC_EMPTY(mh_debug_reg49_reg, ctrl_rarc_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_ARQ_CTRL_EMPTY(mh_debug_reg49_reg, arq_ctrl_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_ARQ_CTRL_WRITE(mh_debug_reg49_reg, arq_ctrl_write) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG49_SET_TLBMISS_CTRL_RTS(mh_debug_reg49_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG49_SET_CTRL_TLBMISS_RE_q(mh_debug_reg49_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_INFLT_LIMIT_q(mh_debug_reg49_reg, inflt_limit_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG49_SET_INFLT_LIMIT_CNT_q(mh_debug_reg49_reg, inflt_limit_cnt_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG49_SET_ARC_CTRL_RE_q(mh_debug_reg49_reg, arc_ctrl_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RARC_CTRL_RE_q(mh_debug_reg49_reg, rarc_ctrl_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RVALID_q(mh_debug_reg49_reg, rvalid_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RREADY_q(mh_debug_reg49_reg, rready_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RLAST_q(mh_debug_reg49_reg, rlast_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT)
+#define MH_DEBUG_REG49_SET_BVALID_q(mh_debug_reg49_reg, bvalid_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT)
+#define MH_DEBUG_REG49_SET_BREADY_q(mh_debug_reg49_reg, bready_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG49_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG49_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG49_RLAST_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG49_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG49_BREADY_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg49_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int                                : 12;
+          unsigned int bready_q                       : MH_DEBUG_REG49_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG49_BVALID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG49_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG49_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG49_RVALID_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE;
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE;
+     } mh_debug_reg49_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg49_t f;
+} mh_debug_reg49_u;
+
+
+/*
+ * MH_DEBUG_REG50 struct
+ */
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG50_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG50_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG50_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG50_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG50_RDC_RID_SIZE    3
+#define MH_DEBUG_REG50_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG50_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE 1
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE 6
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE 1
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE 6
+#define MH_DEBUG_REG50_CNT_HOLD_q1_SIZE 1
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG50_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT 3
+#define MH_DEBUG_REG50_TLBMISS_VALID_SHIFT 4
+#define MH_DEBUG_REG50_RDC_VALID_SHIFT 5
+#define MH_DEBUG_REG50_RDC_RID_SHIFT   6
+#define MH_DEBUG_REG50_RDC_RLAST_SHIFT 9
+#define MH_DEBUG_REG50_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT 12
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT 13
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT 14
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT 15
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT 21
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT 22
+#define MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT 28
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG50_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG50_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK 0x00000008
+#define MH_DEBUG_REG50_TLBMISS_VALID_MASK 0x00000010
+#define MH_DEBUG_REG50_RDC_VALID_MASK  0x00000020
+#define MH_DEBUG_REG50_RDC_RID_MASK    0x000001c0
+#define MH_DEBUG_REG50_RDC_RLAST_MASK  0x00000200
+#define MH_DEBUG_REG50_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK 0x00001000
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK 0x00004000
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK 0x00200000
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000
+#define MH_DEBUG_REG50_CNT_HOLD_q1_MASK 0x10000000
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000
+
+#define MH_DEBUG_REG50_MASK \
+     (MH_DEBUG_REG50_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG50_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG50_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG50_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG50_RDC_VALID_MASK | \
+      MH_DEBUG_REG50_RDC_RID_MASK | \
+      MH_DEBUG_REG50_RDC_RLAST_MASK | \
+      MH_DEBUG_REG50_RDC_RRESP_MASK | \
+      MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK | \
+      MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK | \
+      MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK | \
+      MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK | \
+      MH_DEBUG_REG50_CNT_HOLD_q1_MASK | \
+      MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG50(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \
+     ((mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) | \
+      (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) | \
+      (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) | \
+      (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) | \
+      (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG50_GET_MH_CP_grb_send(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CP_grb_send_MASK) >> MH_DEBUG_REG50_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_VGT_grb_send(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_TC_mcsend(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TC_mcsend_MASK) >> MH_DEBUG_REG50_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_TLBMISS_SEND(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_VALID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_VALID_MASK) >> MH_DEBUG_REG50_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_VALID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_VALID_MASK) >> MH_DEBUG_REG50_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RID_MASK) >> MH_DEBUG_REG50_RDC_RID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RLAST(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RLAST_MASK) >> MH_DEBUG_REG50_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RRESP(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RRESP_MASK) >> MH_DEBUG_REG50_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_CTRL_RTS(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG50_GET_CTRL_TLBMISS_RE_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_ID_REQUEST_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG50_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_ID_RESPONSE(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_GET_CNT_HOLD_q1(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG50_SET_MH_CP_grb_send(mh_debug_reg50_reg, mh_cp_grb_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_VGT_grb_send(mh_debug_reg50_reg, mh_vgt_grb_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_TC_mcsend(mh_debug_reg50_reg, mh_tc_mcsend) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_TLBMISS_SEND(mh_debug_reg50_reg, mh_tlbmiss_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_VALID(mh_debug_reg50_reg, tlbmiss_valid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_VALID(mh_debug_reg50_reg, rdc_valid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RID(mh_debug_reg50_reg, rdc_rid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RLAST(mh_debug_reg50_reg, rdc_rlast) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RRESP(mh_debug_reg50_reg, rdc_rresp) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_CTRL_RTS(mh_debug_reg50_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG50_SET_CTRL_TLBMISS_RE_q(mh_debug_reg50_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_ID_REQUEST_q(mh_debug_reg50_reg, mmu_id_request_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG50_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50_reg, outstanding_mmuid_cnt_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_ID_RESPONSE(mh_debug_reg50_reg, mmu_id_response) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg50_reg, tlbmiss_return_cnt_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_SET_CNT_HOLD_q1(mh_debug_reg50_reg, cnt_hold_q1) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG50_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG50_MH_TC_mcsend_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG50_TLBMISS_VALID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG50_RDC_VALID_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG50_RDC_RID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG50_RDC_RLAST_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG50_RDC_RRESP_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+     } mh_debug_reg50_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG50_RDC_RRESP_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG50_RDC_RLAST_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG50_RDC_RID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG50_RDC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG50_TLBMISS_VALID_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG50_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG50_MH_CP_grb_send_SIZE;
+     } mh_debug_reg50_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg50_t f;
+} mh_debug_reg50_u;
+
+
+/*
+ * MH_DEBUG_REG51 struct
+ */
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE 32
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT 0
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG51_MASK \
+     (MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK)
+
+#define MH_DEBUG_REG51(rf_mmu_page_fault) \
+     ((rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_DEBUG_REG51_GET_RF_MMU_PAGE_FAULT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_DEBUG_REG51_SET_RF_MMU_PAGE_FAULT(mh_debug_reg51_reg, rf_mmu_page_fault) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg51_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg51_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg51_t f;
+} mh_debug_reg51_u;
+
+
+/*
+ * MH_DEBUG_REG52 struct
+ */
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE 2
+#define MH_DEBUG_REG52_ARB_WE_SIZE     1
+#define MH_DEBUG_REG52_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE 22
+#define MH_DEBUG_REG52_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG52_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG52_client_behavior_q_SIZE 2
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT 0
+#define MH_DEBUG_REG52_ARB_WE_SHIFT    2
+#define MH_DEBUG_REG52_MMU_RTR_SHIFT   3
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT 4
+#define MH_DEBUG_REG52_ARB_ID_q_SHIFT  26
+#define MH_DEBUG_REG52_ARB_WRITE_q_SHIFT 29
+#define MH_DEBUG_REG52_client_behavior_q_SHIFT 30
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003
+#define MH_DEBUG_REG52_ARB_WE_MASK     0x00000004
+#define MH_DEBUG_REG52_MMU_RTR_MASK    0x00000008
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0
+#define MH_DEBUG_REG52_ARB_ID_q_MASK   0x1c000000
+#define MH_DEBUG_REG52_ARB_WRITE_q_MASK 0x20000000
+#define MH_DEBUG_REG52_client_behavior_q_MASK 0xc0000000
+
+#define MH_DEBUG_REG52_MASK \
+     (MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK | \
+      MH_DEBUG_REG52_ARB_WE_MASK | \
+      MH_DEBUG_REG52_MMU_RTR_MASK | \
+      MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK | \
+      MH_DEBUG_REG52_ARB_ID_q_MASK | \
+      MH_DEBUG_REG52_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG52_client_behavior_q_MASK)
+
+#define MH_DEBUG_REG52(rf_mmu_config_q_1_to_0, arb_we, mmu_rtr, rf_mmu_config_q_25_to_4, arb_id_q, arb_write_q, client_behavior_q) \
+     ((rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) | \
+      (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) | \
+      (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT))
+
+#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_WE(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WE_MASK) >> MH_DEBUG_REG52_ARB_WE_SHIFT)
+#define MH_DEBUG_REG52_GET_MMU_RTR(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_RTR_MASK) >> MH_DEBUG_REG52_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_ID_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_ID_q_MASK) >> MH_DEBUG_REG52_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_WRITE_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WRITE_q_MASK) >> MH_DEBUG_REG52_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT)
+
+#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52_reg, rf_mmu_config_q_1_to_0) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) | (rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_WE(mh_debug_reg52_reg, arb_we) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT)
+#define MH_DEBUG_REG52_SET_MMU_RTR(mh_debug_reg52_reg, mmu_rtr) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52_reg, rf_mmu_config_q_25_to_4) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) | (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_ID_q(mh_debug_reg52_reg, arb_id_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_WRITE_q(mh_debug_reg52_reg, arb_write_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int rf_mmu_config_q_1_to_0         : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG52_ARB_WE_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG52_MMU_RTR_SIZE;
+          unsigned int rf_mmu_config_q_25_to_4        : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG52_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG52_ARB_WRITE_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+     } mh_debug_reg52_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG52_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG52_ARB_ID_q_SIZE;
+          unsigned int rf_mmu_config_q_25_to_4        : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG52_MMU_RTR_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG52_ARB_WE_SIZE;
+          unsigned int rf_mmu_config_q_1_to_0         : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE;
+     } mh_debug_reg52_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg52_t f;
+} mh_debug_reg52_u;
+
+
+/*
+ * MH_DEBUG_REG53 struct
+ */
+
+#define MH_DEBUG_REG53_stage1_valid_SIZE 1
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG53_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG53_tag_match_q_SIZE 1
+#define MH_DEBUG_REG53_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG53_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG53_MMU_MISS_SIZE   1
+#define MH_DEBUG_REG53_MMU_READ_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_HIT_SIZE    1
+#define MH_DEBUG_REG53_MMU_READ_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE 16
+
+#define MH_DEBUG_REG53_stage1_valid_SHIFT 0
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT 1
+#define MH_DEBUG_REG53_pa_in_mpu_range_SHIFT 2
+#define MH_DEBUG_REG53_tag_match_q_SHIFT 3
+#define MH_DEBUG_REG53_tag_miss_q_SHIFT 4
+#define MH_DEBUG_REG53_va_in_range_q_SHIFT 5
+#define MH_DEBUG_REG53_MMU_MISS_SHIFT  6
+#define MH_DEBUG_REG53_MMU_READ_MISS_SHIFT 7
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT 8
+#define MH_DEBUG_REG53_MMU_HIT_SHIFT   9
+#define MH_DEBUG_REG53_MMU_READ_HIT_SHIFT 10
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT 11
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT 12
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT 13
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT 16
+
+#define MH_DEBUG_REG53_stage1_valid_MASK 0x00000001
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK 0x00000002
+#define MH_DEBUG_REG53_pa_in_mpu_range_MASK 0x00000004
+#define MH_DEBUG_REG53_tag_match_q_MASK 0x00000008
+#define MH_DEBUG_REG53_tag_miss_q_MASK 0x00000010
+#define MH_DEBUG_REG53_va_in_range_q_MASK 0x00000020
+#define MH_DEBUG_REG53_MMU_MISS_MASK   0x00000040
+#define MH_DEBUG_REG53_MMU_READ_MISS_MASK 0x00000080
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_MASK 0x00000100
+#define MH_DEBUG_REG53_MMU_HIT_MASK    0x00000200
+#define MH_DEBUG_REG53_MMU_READ_HIT_MASK 0x00000400
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_MASK 0x00000800
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG53_MASK \
+     (MH_DEBUG_REG53_stage1_valid_MASK | \
+      MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG53_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG53_tag_match_q_MASK | \
+      MH_DEBUG_REG53_tag_miss_q_MASK | \
+      MH_DEBUG_REG53_va_in_range_q_MASK | \
+      MH_DEBUG_REG53_MMU_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_READ_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_WRITE_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_READ_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_WRITE_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK | \
+      MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK)
+
+#define MH_DEBUG_REG53(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \
+     ((stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) | \
+      (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) | \
+      (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) | \
+      (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) | \
+      (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) | \
+      (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) | \
+      (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) | \
+      (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \
+      (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \
+      (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \
+      (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \
+      (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT))
+
+#define MH_DEBUG_REG53_GET_stage1_valid(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_stage1_valid_MASK) >> MH_DEBUG_REG53_stage1_valid_SHIFT)
+#define MH_DEBUG_REG53_GET_IGNORE_TAG_MISS_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG53_GET_pa_in_mpu_range(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_pa_in_mpu_range_MASK) >> MH_DEBUG_REG53_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG53_GET_tag_match_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_tag_match_q_MASK) >> MH_DEBUG_REG53_tag_match_q_SHIFT)
+#define MH_DEBUG_REG53_GET_tag_miss_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_tag_miss_q_MASK) >> MH_DEBUG_REG53_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG53_GET_va_in_range_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_va_in_range_q_MASK) >> MH_DEBUG_REG53_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_MISS_MASK) >> MH_DEBUG_REG53_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_READ_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_MISS_MASK) >> MH_DEBUG_REG53_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_WRITE_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_HIT_MASK) >> MH_DEBUG_REG53_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_READ_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_HIT_MASK) >> MH_DEBUG_REG53_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_WRITE_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_REQ_VA_OFFSET_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)
+
+#define MH_DEBUG_REG53_SET_stage1_valid(mh_debug_reg53_reg, stage1_valid) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT)
+#define MH_DEBUG_REG53_SET_IGNORE_TAG_MISS_q(mh_debug_reg53_reg, ignore_tag_miss_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG53_SET_pa_in_mpu_range(mh_debug_reg53_reg, pa_in_mpu_range) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG53_SET_tag_match_q(mh_debug_reg53_reg, tag_match_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT)
+#define MH_DEBUG_REG53_SET_tag_miss_q(mh_debug_reg53_reg, tag_miss_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG53_SET_va_in_range_q(mh_debug_reg53_reg, va_in_range_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_MISS(mh_debug_reg53_reg, mmu_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_READ_MISS(mh_debug_reg53_reg, mmu_read_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_WRITE_MISS(mh_debug_reg53_reg, mmu_write_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_HIT(mh_debug_reg53_reg, mmu_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_READ_HIT(mh_debug_reg53_reg, mmu_read_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_WRITE_HIT(mh_debug_reg53_reg, mmu_write_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53_reg, mmu_split_mode_tc_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53_reg, mmu_split_mode_tc_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53_reg, mmu_split_mode_nontc_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53_reg, mmu_split_mode_nontc_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_REQ_VA_OFFSET_q(mh_debug_reg53_reg, req_va_offset_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int stage1_valid                   : MH_DEBUG_REG53_stage1_valid_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG53_pa_in_mpu_range_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG53_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG53_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG53_va_in_range_q_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG53_MMU_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG53_MMU_READ_MISS_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG53_MMU_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG53_MMU_READ_HIT_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int req_va_offset_q                : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE;
+     } mh_debug_reg53_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int req_va_offset_q                : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG53_MMU_READ_HIT_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG53_MMU_HIT_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG53_MMU_READ_MISS_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG53_MMU_MISS_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG53_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG53_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG53_tag_match_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG53_pa_in_mpu_range_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG53_stage1_valid_SIZE;
+     } mh_debug_reg53_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg53_t f;
+} mh_debug_reg53_u;
+
+
+/*
+ * MH_DEBUG_REG54 struct
+ */
+
+#define MH_DEBUG_REG54_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG54_MMU_WE_SIZE     1
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1
+#define MH_DEBUG_REG54_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG54_stage1_valid_SIZE 1
+#define MH_DEBUG_REG54_stage2_valid_SIZE 1
+#define MH_DEBUG_REG54_client_behavior_q_SIZE 2
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG54_tag_match_q_SIZE 1
+#define MH_DEBUG_REG54_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG54_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE 1
+#define MH_DEBUG_REG54_TAG_valid_q_SIZE 16
+
+#define MH_DEBUG_REG54_ARQ_RTR_SHIFT   0
+#define MH_DEBUG_REG54_MMU_WE_SHIFT    1
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT 2
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT 3
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT 4
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5
+#define MH_DEBUG_REG54_pa_in_mpu_range_SHIFT 6
+#define MH_DEBUG_REG54_stage1_valid_SHIFT 7
+#define MH_DEBUG_REG54_stage2_valid_SHIFT 8
+#define MH_DEBUG_REG54_client_behavior_q_SHIFT 9
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT 11
+#define MH_DEBUG_REG54_tag_match_q_SHIFT 12
+#define MH_DEBUG_REG54_tag_miss_q_SHIFT 13
+#define MH_DEBUG_REG54_va_in_range_q_SHIFT 14
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT 15
+#define MH_DEBUG_REG54_TAG_valid_q_SHIFT 16
+
+#define MH_DEBUG_REG54_ARQ_RTR_MASK    0x00000001
+#define MH_DEBUG_REG54_MMU_WE_MASK     0x00000002
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK 0x00000004
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK 0x00000008
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK 0x00000010
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020
+#define MH_DEBUG_REG54_pa_in_mpu_range_MASK 0x00000040
+#define MH_DEBUG_REG54_stage1_valid_MASK 0x00000080
+#define MH_DEBUG_REG54_stage2_valid_MASK 0x00000100
+#define MH_DEBUG_REG54_client_behavior_q_MASK 0x00000600
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK 0x00000800
+#define MH_DEBUG_REG54_tag_match_q_MASK 0x00001000
+#define MH_DEBUG_REG54_tag_miss_q_MASK 0x00002000
+#define MH_DEBUG_REG54_va_in_range_q_MASK 0x00004000
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK 0x00008000
+#define MH_DEBUG_REG54_TAG_valid_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG54_MASK \
+     (MH_DEBUG_REG54_ARQ_RTR_MASK | \
+      MH_DEBUG_REG54_MMU_WE_MASK | \
+      MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \
+      MH_DEBUG_REG54_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG54_stage1_valid_MASK | \
+      MH_DEBUG_REG54_stage2_valid_MASK | \
+      MH_DEBUG_REG54_client_behavior_q_MASK | \
+      MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG54_tag_match_q_MASK | \
+      MH_DEBUG_REG54_tag_miss_q_MASK | \
+      MH_DEBUG_REG54_va_in_range_q_MASK | \
+      MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK | \
+      MH_DEBUG_REG54_TAG_valid_q_MASK)
+
+#define MH_DEBUG_REG54(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \
+     ((arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) | \
+      (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) | \
+      (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) | \
+      (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) | \
+      (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) | \
+      (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT))
+
+#define MH_DEBUG_REG54_GET_ARQ_RTR(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_ARQ_RTR_MASK) >> MH_DEBUG_REG54_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG54_GET_MMU_WE(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_WE_MASK) >> MH_DEBUG_REG54_MMU_WE_SHIFT)
+#define MH_DEBUG_REG54_GET_CTRL_TLBMISS_RE_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG54_GET_TLBMISS_CTRL_RTS(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG54_GET_MH_TLBMISS_SEND(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG54_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG54_GET_pa_in_mpu_range(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_pa_in_mpu_range_MASK) >> MH_DEBUG_REG54_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG54_GET_stage1_valid(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_stage1_valid_MASK) >> MH_DEBUG_REG54_stage1_valid_SHIFT)
+#define MH_DEBUG_REG54_GET_stage2_valid(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_stage2_valid_MASK) >> MH_DEBUG_REG54_stage2_valid_SHIFT)
+#define MH_DEBUG_REG54_GET_client_behavior_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_client_behavior_q_MASK) >> MH_DEBUG_REG54_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG54_GET_IGNORE_TAG_MISS_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG54_GET_tag_match_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_tag_match_q_MASK) >> MH_DEBUG_REG54_tag_match_q_SHIFT)
+#define MH_DEBUG_REG54_GET_tag_miss_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_tag_miss_q_MASK) >> MH_DEBUG_REG54_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG54_GET_va_in_range_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_va_in_range_q_MASK) >> MH_DEBUG_REG54_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG54_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG_valid_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_MASK) >> MH_DEBUG_REG54_TAG_valid_q_SHIFT)
+
+#define MH_DEBUG_REG54_SET_ARQ_RTR(mh_debug_reg54_reg, arq_rtr) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG54_SET_MMU_WE(mh_debug_reg54_reg, mmu_we) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT)
+#define MH_DEBUG_REG54_SET_CTRL_TLBMISS_RE_q(mh_debug_reg54_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG54_SET_TLBMISS_CTRL_RTS(mh_debug_reg54_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG54_SET_MH_TLBMISS_SEND(mh_debug_reg54_reg, mh_tlbmiss_send) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG54_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54_reg, mmu_stall_awaiting_tlb_miss_fetch) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG54_SET_pa_in_mpu_range(mh_debug_reg54_reg, pa_in_mpu_range) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG54_SET_stage1_valid(mh_debug_reg54_reg, stage1_valid) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT)
+#define MH_DEBUG_REG54_SET_stage2_valid(mh_debug_reg54_reg, stage2_valid) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT)
+#define MH_DEBUG_REG54_SET_client_behavior_q(mh_debug_reg54_reg, client_behavior_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG54_SET_IGNORE_TAG_MISS_q(mh_debug_reg54_reg, ignore_tag_miss_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG54_SET_tag_match_q(mh_debug_reg54_reg, tag_match_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT)
+#define MH_DEBUG_REG54_SET_tag_miss_q(mh_debug_reg54_reg, tag_miss_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG54_SET_va_in_range_q(mh_debug_reg54_reg, va_in_range_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG54_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg54_reg, pte_fetch_complete_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG_valid_q(mh_debug_reg54_reg, tag_valid_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int arq_rtr                        : MH_DEBUG_REG54_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG54_MMU_WE_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG54_pa_in_mpu_range_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG54_stage1_valid_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG54_stage2_valid_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG54_client_behavior_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG54_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG54_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG54_va_in_range_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int tag_valid_q                    : MH_DEBUG_REG54_TAG_valid_q_SIZE;
+     } mh_debug_reg54_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int tag_valid_q                    : MH_DEBUG_REG54_TAG_valid_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG54_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG54_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG54_tag_match_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG54_client_behavior_q_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG54_stage2_valid_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG54_stage1_valid_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG54_pa_in_mpu_range_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG54_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG54_ARQ_RTR_SIZE;
+     } mh_debug_reg54_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg54_t f;
+} mh_debug_reg54_u;
+
+
+/*
+ * MH_DEBUG_REG55 struct
+ */
+
+#define MH_DEBUG_REG55_TAG0_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_0_SIZE 1
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG55_TAG1_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_1_SIZE 1
+
+#define MH_DEBUG_REG55_TAG0_VA_SHIFT   0
+#define MH_DEBUG_REG55_TAG_valid_q_0_SHIFT 13
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG55_TAG1_VA_SHIFT   16
+#define MH_DEBUG_REG55_TAG_valid_q_1_SHIFT 29
+
+#define MH_DEBUG_REG55_TAG0_VA_MASK    0x00001fff
+#define MH_DEBUG_REG55_TAG_valid_q_0_MASK 0x00002000
+#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG55_TAG1_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG55_TAG_valid_q_1_MASK 0x20000000
+
+#define MH_DEBUG_REG55_MASK \
+     (MH_DEBUG_REG55_TAG0_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_0_MASK | \
+      MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG55_TAG1_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_1_MASK)
+
+#define MH_DEBUG_REG55(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \
+     ((tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) | \
+      (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) | \
+      (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \
+      (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) | \
+      (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT))
+
+#define MH_DEBUG_REG55_GET_TAG0_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG0_VA_MASK) >> MH_DEBUG_REG55_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_0(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_0_MASK) >> MH_DEBUG_REG55_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG1_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG1_VA_MASK) >> MH_DEBUG_REG55_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_1(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_1_MASK) >> MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)
+
+#define MH_DEBUG_REG55_SET_TAG0_VA(mh_debug_reg55_reg, tag0_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_0(mh_debug_reg55_reg, tag_valid_q_0) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG1_VA(mh_debug_reg55_reg, tag1_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_1(mh_debug_reg55_reg, tag_valid_q_1) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int tag0_va                        : MH_DEBUG_REG55_TAG0_VA_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG55_TAG_valid_q_0_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG55_TAG1_VA_SIZE;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG55_TAG_valid_q_1_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg55_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG55_TAG_valid_q_1_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG55_TAG1_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG55_TAG_valid_q_0_SIZE;
+          unsigned int tag0_va                        : MH_DEBUG_REG55_TAG0_VA_SIZE;
+     } mh_debug_reg55_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg55_t f;
+} mh_debug_reg55_u;
+
+
+/*
+ * MH_DEBUG_REG56 struct
+ */
+
+#define MH_DEBUG_REG56_TAG2_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_2_SIZE 1
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG56_TAG3_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_3_SIZE 1
+
+#define MH_DEBUG_REG56_TAG2_VA_SHIFT   0
+#define MH_DEBUG_REG56_TAG_valid_q_2_SHIFT 13
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG56_TAG3_VA_SHIFT   16
+#define MH_DEBUG_REG56_TAG_valid_q_3_SHIFT 29
+
+#define MH_DEBUG_REG56_TAG2_VA_MASK    0x00001fff
+#define MH_DEBUG_REG56_TAG_valid_q_2_MASK 0x00002000
+#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG56_TAG3_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG56_TAG_valid_q_3_MASK 0x20000000
+
+#define MH_DEBUG_REG56_MASK \
+     (MH_DEBUG_REG56_TAG2_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_2_MASK | \
+      MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG56_TAG3_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_3_MASK)
+
+#define MH_DEBUG_REG56(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \
+     ((tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) | \
+      (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) | \
+      (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \
+      (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) | \
+      (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT))
+
+#define MH_DEBUG_REG56_GET_TAG2_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG2_VA_MASK) >> MH_DEBUG_REG56_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_2(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_2_MASK) >> MH_DEBUG_REG56_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG3_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG3_VA_MASK) >> MH_DEBUG_REG56_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_3(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_3_MASK) >> MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)
+
+#define MH_DEBUG_REG56_SET_TAG2_VA(mh_debug_reg56_reg, tag2_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_2(mh_debug_reg56_reg, tag_valid_q_2) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG3_VA(mh_debug_reg56_reg, tag3_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_3(mh_debug_reg56_reg, tag_valid_q_3) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int tag2_va                        : MH_DEBUG_REG56_TAG2_VA_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG56_TAG_valid_q_2_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG56_TAG3_VA_SIZE;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG56_TAG_valid_q_3_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg56_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG56_TAG_valid_q_3_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG56_TAG3_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG56_TAG_valid_q_2_SIZE;
+          unsigned int tag2_va                        : MH_DEBUG_REG56_TAG2_VA_SIZE;
+     } mh_debug_reg56_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg56_t f;
+} mh_debug_reg56_u;
+
+
+/*
+ * MH_DEBUG_REG57 struct
+ */
+
+#define MH_DEBUG_REG57_TAG4_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_4_SIZE 1
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG57_TAG5_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_5_SIZE 1
+
+#define MH_DEBUG_REG57_TAG4_VA_SHIFT   0
+#define MH_DEBUG_REG57_TAG_valid_q_4_SHIFT 13
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG57_TAG5_VA_SHIFT   16
+#define MH_DEBUG_REG57_TAG_valid_q_5_SHIFT 29
+
+#define MH_DEBUG_REG57_TAG4_VA_MASK    0x00001fff
+#define MH_DEBUG_REG57_TAG_valid_q_4_MASK 0x00002000
+#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG57_TAG5_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG57_TAG_valid_q_5_MASK 0x20000000
+
+#define MH_DEBUG_REG57_MASK \
+     (MH_DEBUG_REG57_TAG4_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_4_MASK | \
+      MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG57_TAG5_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_5_MASK)
+
+#define MH_DEBUG_REG57(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \
+     ((tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) | \
+      (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) | \
+      (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \
+      (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) | \
+      (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT))
+
+#define MH_DEBUG_REG57_GET_TAG4_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG4_VA_MASK) >> MH_DEBUG_REG57_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_4(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_4_MASK) >> MH_DEBUG_REG57_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG5_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG5_VA_MASK) >> MH_DEBUG_REG57_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_5(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_5_MASK) >> MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)
+
+#define MH_DEBUG_REG57_SET_TAG4_VA(mh_debug_reg57_reg, tag4_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_4(mh_debug_reg57_reg, tag_valid_q_4) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG5_VA(mh_debug_reg57_reg, tag5_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_5(mh_debug_reg57_reg, tag_valid_q_5) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int tag4_va                        : MH_DEBUG_REG57_TAG4_VA_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG57_TAG_valid_q_4_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG57_TAG5_VA_SIZE;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG57_TAG_valid_q_5_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg57_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG57_TAG_valid_q_5_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG57_TAG5_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG57_TAG_valid_q_4_SIZE;
+          unsigned int tag4_va                        : MH_DEBUG_REG57_TAG4_VA_SIZE;
+     } mh_debug_reg57_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg57_t f;
+} mh_debug_reg57_u;
+
+
+/*
+ * MH_DEBUG_REG58 struct
+ */
+
+#define MH_DEBUG_REG58_TAG6_VA_SIZE    13
+#define MH_DEBUG_REG58_TAG_valid_q_6_SIZE 1
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG58_TAG7_VA_SIZE    13
+#define MH_DEBUG_REG58_TAG_valid_q_7_SIZE 1
+
+#define MH_DEBUG_REG58_TAG6_VA_SHIFT   0
+#define MH_DEBUG_REG58_TAG_valid_q_6_SHIFT 13
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG58_TAG7_VA_SHIFT   16
+#define MH_DEBUG_REG58_TAG_valid_q_7_SHIFT 29
+
+#define MH_DEBUG_REG58_TAG6_VA_MASK    0x00001fff
+#define MH_DEBUG_REG58_TAG_valid_q_6_MASK 0x00002000
+#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG58_TAG7_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG58_TAG_valid_q_7_MASK 0x20000000
+
+#define MH_DEBUG_REG58_MASK \
+     (MH_DEBUG_REG58_TAG6_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_6_MASK | \
+      MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG58_TAG7_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_7_MASK)
+
+#define MH_DEBUG_REG58(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \
+     ((tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) | \
+      (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) | \
+      (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \
+      (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) | \
+      (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT))
+
+#define MH_DEBUG_REG58_GET_TAG6_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG6_VA_MASK) >> MH_DEBUG_REG58_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_6(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_6_MASK) >> MH_DEBUG_REG58_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG7_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG7_VA_MASK) >> MH_DEBUG_REG58_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_7(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_7_MASK) >> MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)
+
+#define MH_DEBUG_REG58_SET_TAG6_VA(mh_debug_reg58_reg, tag6_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_6(mh_debug_reg58_reg, tag_valid_q_6) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG7_VA(mh_debug_reg58_reg, tag7_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_7(mh_debug_reg58_reg, tag_valid_q_7) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int tag6_va                        : MH_DEBUG_REG58_TAG6_VA_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG58_TAG_valid_q_6_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG58_TAG7_VA_SIZE;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG58_TAG_valid_q_7_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg58_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG58_TAG_valid_q_7_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG58_TAG7_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG58_TAG_valid_q_6_SIZE;
+          unsigned int tag6_va                        : MH_DEBUG_REG58_TAG6_VA_SIZE;
+     } mh_debug_reg58_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg58_t f;
+} mh_debug_reg58_u;
+
+
+/*
+ * MH_DEBUG_REG59 struct
+ */
+
+#define MH_DEBUG_REG59_TAG8_VA_SIZE    13
+#define MH_DEBUG_REG59_TAG_valid_q_8_SIZE 1
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG59_TAG9_VA_SIZE    13
+#define MH_DEBUG_REG59_TAG_valid_q_9_SIZE 1
+
+#define MH_DEBUG_REG59_TAG8_VA_SHIFT   0
+#define MH_DEBUG_REG59_TAG_valid_q_8_SHIFT 13
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG59_TAG9_VA_SHIFT   16
+#define MH_DEBUG_REG59_TAG_valid_q_9_SHIFT 29
+
+#define MH_DEBUG_REG59_TAG8_VA_MASK    0x00001fff
+#define MH_DEBUG_REG59_TAG_valid_q_8_MASK 0x00002000
+#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG59_TAG9_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG59_TAG_valid_q_9_MASK 0x20000000
+
+#define MH_DEBUG_REG59_MASK \
+     (MH_DEBUG_REG59_TAG8_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_8_MASK | \
+      MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG59_TAG9_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_9_MASK)
+
+#define MH_DEBUG_REG59(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \
+     ((tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) | \
+      (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) | \
+      (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \
+      (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) | \
+      (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT))
+
+#define MH_DEBUG_REG59_GET_TAG8_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG8_VA_MASK) >> MH_DEBUG_REG59_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_8(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_8_MASK) >> MH_DEBUG_REG59_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG9_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG9_VA_MASK) >> MH_DEBUG_REG59_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_9(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_9_MASK) >> MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)
+
+#define MH_DEBUG_REG59_SET_TAG8_VA(mh_debug_reg59_reg, tag8_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_8(mh_debug_reg59_reg, tag_valid_q_8) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG9_VA(mh_debug_reg59_reg, tag9_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_9(mh_debug_reg59_reg, tag_valid_q_9) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int tag8_va                        : MH_DEBUG_REG59_TAG8_VA_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG59_TAG_valid_q_8_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG59_TAG9_VA_SIZE;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG59_TAG_valid_q_9_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg59_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG59_TAG_valid_q_9_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG59_TAG9_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG59_TAG_valid_q_8_SIZE;
+          unsigned int tag8_va                        : MH_DEBUG_REG59_TAG8_VA_SIZE;
+     } mh_debug_reg59_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg59_t f;
+} mh_debug_reg59_u;
+
+
+/*
+ * MH_DEBUG_REG60 struct
+ */
+
+#define MH_DEBUG_REG60_TAG10_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_10_SIZE 1
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG60_TAG11_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_11_SIZE 1
+
+#define MH_DEBUG_REG60_TAG10_VA_SHIFT  0
+#define MH_DEBUG_REG60_TAG_valid_q_10_SHIFT 13
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG60_TAG11_VA_SHIFT  16
+#define MH_DEBUG_REG60_TAG_valid_q_11_SHIFT 29
+
+#define MH_DEBUG_REG60_TAG10_VA_MASK   0x00001fff
+#define MH_DEBUG_REG60_TAG_valid_q_10_MASK 0x00002000
+#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG60_TAG11_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG60_TAG_valid_q_11_MASK 0x20000000
+
+#define MH_DEBUG_REG60_MASK \
+     (MH_DEBUG_REG60_TAG10_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_10_MASK | \
+      MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG60_TAG11_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_11_MASK)
+
+#define MH_DEBUG_REG60(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \
+     ((tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) | \
+      (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) | \
+      (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \
+      (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) | \
+      (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT))
+
+#define MH_DEBUG_REG60_GET_TAG10_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG10_VA_MASK) >> MH_DEBUG_REG60_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_10(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_10_MASK) >> MH_DEBUG_REG60_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG11_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG11_VA_MASK) >> MH_DEBUG_REG60_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_11(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_11_MASK) >> MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)
+
+#define MH_DEBUG_REG60_SET_TAG10_VA(mh_debug_reg60_reg, tag10_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_10(mh_debug_reg60_reg, tag_valid_q_10) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG11_VA(mh_debug_reg60_reg, tag11_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_11(mh_debug_reg60_reg, tag_valid_q_11) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int tag10_va                       : MH_DEBUG_REG60_TAG10_VA_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG60_TAG11_VA_SIZE;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg60_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG60_TAG11_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE;
+          unsigned int tag10_va                       : MH_DEBUG_REG60_TAG10_VA_SIZE;
+     } mh_debug_reg60_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg60_t f;
+} mh_debug_reg60_u;
+
+
+/*
+ * MH_DEBUG_REG61 struct
+ */
+
+#define MH_DEBUG_REG61_TAG12_VA_SIZE   13
+#define MH_DEBUG_REG61_TAG_valid_q_12_SIZE 1
+#define MH_DEBUG_REG61_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG61_TAG13_VA_SIZE   13
+#define MH_DEBUG_REG61_TAG_valid_q_13_SIZE 1
+
+#define MH_DEBUG_REG61_TAG12_VA_SHIFT  0
+#define MH_DEBUG_REG61_TAG_valid_q_12_SHIFT 13
+#define MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG61_TAG13_VA_SHIFT  16
+#define MH_DEBUG_REG61_TAG_valid_q_13_SHIFT 29
+
+#define MH_DEBUG_REG61_TAG12_VA_MASK   0x00001fff
+#define MH_DEBUG_REG61_TAG_valid_q_12_MASK 0x00002000
+#define MH_DEBUG_REG61_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG61_TAG13_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG61_TAG_valid_q_13_MASK 0x20000000
+
+#define MH_DEBUG_REG61_MASK \
+     (MH_DEBUG_REG61_TAG12_VA_MASK | \
+      MH_DEBUG_REG61_TAG_valid_q_12_MASK | \
+      MH_DEBUG_REG61_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG61_TAG13_VA_MASK | \
+      MH_DEBUG_REG61_TAG_valid_q_13_MASK)
+
+#define MH_DEBUG_REG61(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \
+     ((tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) | \
+      (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) | \
+      (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) | \
+      (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) | \
+      (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT))
+
+#define MH_DEBUG_REG61_GET_TAG12_VA(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG12_VA_MASK) >> MH_DEBUG_REG61_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG_valid_q_12(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_12_MASK) >> MH_DEBUG_REG61_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG61_GET_ALWAYS_ZERO(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG13_VA(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG13_VA_MASK) >> MH_DEBUG_REG61_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG_valid_q_13(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_13_MASK) >> MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)
+
+#define MH_DEBUG_REG61_SET_TAG12_VA(mh_debug_reg61_reg, tag12_va) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG_valid_q_12(mh_debug_reg61_reg, tag_valid_q_12) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG61_SET_ALWAYS_ZERO(mh_debug_reg61_reg, always_zero) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG13_VA(mh_debug_reg61_reg, tag13_va) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG_valid_q_13(mh_debug_reg61_reg, tag_valid_q_13) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int tag12_va                       : MH_DEBUG_REG61_TAG12_VA_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG61_TAG13_VA_SIZE;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg61_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG61_TAG13_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE;
+          unsigned int tag12_va                       : MH_DEBUG_REG61_TAG12_VA_SIZE;
+     } mh_debug_reg61_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg61_t f;
+} mh_debug_reg61_u;
+
+
+/*
+ * MH_DEBUG_REG62 struct
+ */
+
+#define MH_DEBUG_REG62_TAG14_VA_SIZE   13
+#define MH_DEBUG_REG62_TAG_valid_q_14_SIZE 1
+#define MH_DEBUG_REG62_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG62_TAG15_VA_SIZE   13
+#define MH_DEBUG_REG62_TAG_valid_q_15_SIZE 1
+
+#define MH_DEBUG_REG62_TAG14_VA_SHIFT  0
+#define MH_DEBUG_REG62_TAG_valid_q_14_SHIFT 13
+#define MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG62_TAG15_VA_SHIFT  16
+#define MH_DEBUG_REG62_TAG_valid_q_15_SHIFT 29
+
+#define MH_DEBUG_REG62_TAG14_VA_MASK   0x00001fff
+#define MH_DEBUG_REG62_TAG_valid_q_14_MASK 0x00002000
+#define MH_DEBUG_REG62_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG62_TAG15_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG62_TAG_valid_q_15_MASK 0x20000000
+
+#define MH_DEBUG_REG62_MASK \
+     (MH_DEBUG_REG62_TAG14_VA_MASK | \
+      MH_DEBUG_REG62_TAG_valid_q_14_MASK | \
+      MH_DEBUG_REG62_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG62_TAG15_VA_MASK | \
+      MH_DEBUG_REG62_TAG_valid_q_15_MASK)
+
+#define MH_DEBUG_REG62(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \
+     ((tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) | \
+      (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) | \
+      (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) | \
+      (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) | \
+      (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT))
+
+#define MH_DEBUG_REG62_GET_TAG14_VA(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG14_VA_MASK) >> MH_DEBUG_REG62_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG_valid_q_14(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_14_MASK) >> MH_DEBUG_REG62_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG62_GET_ALWAYS_ZERO(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG15_VA(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG15_VA_MASK) >> MH_DEBUG_REG62_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG_valid_q_15(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_15_MASK) >> MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)
+
+#define MH_DEBUG_REG62_SET_TAG14_VA(mh_debug_reg62_reg, tag14_va) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG_valid_q_14(mh_debug_reg62_reg, tag_valid_q_14) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG62_SET_ALWAYS_ZERO(mh_debug_reg62_reg, always_zero) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG15_VA(mh_debug_reg62_reg, tag15_va) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG_valid_q_15(mh_debug_reg62_reg, tag_valid_q_15) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int tag14_va                       : MH_DEBUG_REG62_TAG14_VA_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG62_TAG15_VA_SIZE;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg62_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG62_TAG15_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE;
+          unsigned int tag14_va                       : MH_DEBUG_REG62_TAG14_VA_SIZE;
+     } mh_debug_reg62_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg62_t f;
+} mh_debug_reg62_u;
+
+
+/*
+ * MH_DEBUG_REG63 struct
+ */
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG63_MASK \
+     (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG63(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \
+     ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \
+     mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg63_t f;
+} mh_debug_reg63_u;
+
+
+/*
+ * MH_MMU_CONFIG struct
+ */
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SIZE  1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1
+#define MH_MMU_CONFIG_RESERVED1_SIZE   2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE 2
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1
+#define MH_MMU_CONFIG_RESERVED1_SHIFT  2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT 24
+
+#define MH_MMU_CONFIG_MMU_ENABLE_MASK  0x00000001
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002
+#define MH_MMU_CONFIG_RESERVED1_MASK   0x0000000c
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK 0x03000000
+
+#define MH_MMU_CONFIG_MASK \
+     (MH_MMU_CONFIG_MMU_ENABLE_MASK | \
+      MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \
+      MH_MMU_CONFIG_RESERVED1_MASK | \
+      MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK)
+
+#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior, pa_w_clnt_behavior) \
+     ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \
+      (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \
+      (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \
+      (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) | \
+      (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT))
+
+#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_PA_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)
+
+#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_PA_W_CLNT_BEHAVIOR(mh_mmu_config_reg, pa_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) | (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int pa_w_clnt_behavior             : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int                                : 6;
+     } mh_mmu_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int                                : 6;
+          unsigned int pa_w_clnt_behavior             : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+     } mh_mmu_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_config_t f;
+} mh_mmu_config_u;
+
+
+/*
+ * MH_MMU_VA_RANGE struct
+ */
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12
+#define MH_MMU_VA_RANGE_VA_BASE_SIZE   20
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0
+#define MH_MMU_VA_RANGE_VA_BASE_SHIFT  12
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff
+#define MH_MMU_VA_RANGE_VA_BASE_MASK   0xfffff000
+
+#define MH_MMU_VA_RANGE_MASK \
+     (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \
+      MH_MMU_VA_RANGE_VA_BASE_MASK)
+
+#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \
+     ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \
+      (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT))
+
+#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+     } mh_mmu_va_range_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+     } mh_mmu_va_range_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_va_range_t f;
+} mh_mmu_va_range_u;
+
+
+/*
+ * MH_MMU_PT_BASE struct
+ */
+
+#define MH_MMU_PT_BASE_PT_BASE_SIZE    20
+
+#define MH_MMU_PT_BASE_PT_BASE_SHIFT   12
+
+#define MH_MMU_PT_BASE_PT_BASE_MASK    0xfffff000
+
+#define MH_MMU_PT_BASE_MASK \
+     (MH_MMU_PT_BASE_PT_BASE_MASK)
+
+#define MH_MMU_PT_BASE(pt_base) \
+     ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT))
+
+#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \
+     ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \
+     mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int                                : 12;
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+     } mh_mmu_pt_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_pt_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_pt_base_t f;
+} mh_mmu_pt_base_u;
+
+
+/*
+ * MH_MMU_PAGE_FAULT struct
+ */
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE  3
+#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE  20
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4
+#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11
+#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001
+#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c
+#define MH_MMU_PAGE_FAULT_AXI_ID_MASK  0x00000070
+#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800
+#define MH_MMU_PAGE_FAULT_REQ_VA_MASK  0xfffff000
+
+#define MH_MMU_PAGE_FAULT_MASK \
+     (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \
+      MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \
+      MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_PAGE_FAULT_AXI_ID_MASK | \
+      MH_MMU_PAGE_FAULT_RESERVED1_MASK | \
+      MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_REQ_VA_MASK)
+
+#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \
+     ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \
+      (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \
+      (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \
+      (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \
+      (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \
+      (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \
+      (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \
+      (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT))
+
+#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+     } mh_mmu_page_fault_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+     } mh_mmu_page_fault_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_page_fault_t f;
+} mh_mmu_page_fault_u;
+
+
+/*
+ * MH_MMU_TRAN_ERROR struct
+ */
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0
+
+#define MH_MMU_TRAN_ERROR_MASK \
+     (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK)
+
+#define MH_MMU_TRAN_ERROR(tran_error) \
+     ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT))
+
+#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \
+     ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \
+     mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int                                : 5;
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+     } mh_mmu_tran_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+          unsigned int                                : 5;
+     } mh_mmu_tran_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_tran_error_t f;
+} mh_mmu_tran_error_u;
+
+
+/*
+ * MH_MMU_INVALIDATE struct
+ */
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002
+
+#define MH_MMU_INVALIDATE_MASK \
+     (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_MMU_INVALIDATE_INVALIDATE_TC_MASK)
+
+#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \
+     ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT))
+
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int                                : 30;
+     } mh_mmu_invalidate_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int                                : 30;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+     } mh_mmu_invalidate_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_invalidate_t f;
+} mh_mmu_invalidate_u;
+
+
+/*
+ * MH_MMU_MPU_BASE struct
+ */
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SIZE  20
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12
+
+#define MH_MMU_MPU_BASE_MPU_BASE_MASK  0xfffff000
+
+#define MH_MMU_MPU_BASE_MASK \
+     (MH_MMU_MPU_BASE_MPU_BASE_MASK)
+
+#define MH_MMU_MPU_BASE(mpu_base) \
+     ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT))
+
+#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \
+     ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \
+     mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int                                : 12;
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+     } mh_mmu_mpu_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_base_t f;
+} mh_mmu_mpu_base_u;
+
+
+/*
+ * MH_MMU_MPU_END struct
+ */
+
+#define MH_MMU_MPU_END_MPU_END_SIZE    20
+
+#define MH_MMU_MPU_END_MPU_END_SHIFT   12
+
+#define MH_MMU_MPU_END_MPU_END_MASK    0xfffff000
+
+#define MH_MMU_MPU_END_MASK \
+     (MH_MMU_MPU_END_MPU_END_MASK)
+
+#define MH_MMU_MPU_END(mpu_end) \
+     ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT))
+
+#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \
+     ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \
+     mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int                                : 12;
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+     } mh_mmu_mpu_end_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_end_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_end_t f;
+} mh_mmu_mpu_end_u;
+
+
+#endif
+
+
+#if !defined (_PA_FIDDLE_H)
+#define _PA_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  pa_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * PA_CL_VPORT_XSCALE struct
+ */
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_XSCALE_MASK \
+     (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK)
+
+#define PA_CL_VPORT_XSCALE(vport_xscale) \
+     ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT))
+
+#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \
+     ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \
+     pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xscale_t f;
+} pa_cl_vport_xscale_u;
+
+
+/*
+ * PA_CL_VPORT_XOFFSET struct
+ */
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_XOFFSET_MASK \
+     (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK)
+
+#define PA_CL_VPORT_XOFFSET(vport_xoffset) \
+     ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT))
+
+#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \
+     ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \
+     pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xoffset_t f;
+} pa_cl_vport_xoffset_u;
+
+
+/*
+ * PA_CL_VPORT_YSCALE struct
+ */
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_YSCALE_MASK \
+     (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK)
+
+#define PA_CL_VPORT_YSCALE(vport_yscale) \
+     ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT))
+
+#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \
+     ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \
+     pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yscale_t f;
+} pa_cl_vport_yscale_u;
+
+
+/*
+ * PA_CL_VPORT_YOFFSET struct
+ */
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_YOFFSET_MASK \
+     (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK)
+
+#define PA_CL_VPORT_YOFFSET(vport_yoffset) \
+     ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT))
+
+#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \
+     ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \
+     pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yoffset_t f;
+} pa_cl_vport_yoffset_u;
+
+
+/*
+ * PA_CL_VPORT_ZSCALE struct
+ */
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZSCALE_MASK \
+     (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK)
+
+#define PA_CL_VPORT_ZSCALE(vport_zscale) \
+     ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT))
+
+#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \
+     ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \
+     pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zscale_t f;
+} pa_cl_vport_zscale_u;
+
+
+/*
+ * PA_CL_VPORT_ZOFFSET struct
+ */
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZOFFSET_MASK \
+     (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK)
+
+#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \
+     ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT))
+
+#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \
+     ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \
+     pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zoffset_t f;
+} pa_cl_vport_zoffset_u;
+
+
+/*
+ * PA_CL_VTE_CNTL struct
+ */
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE  1
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK  0x00000200
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800
+
+#define PA_CL_VTE_CNTL_MASK \
+     (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \
+      PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK)
+
+#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \
+     ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \
+      (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \
+      (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \
+      (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \
+      (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \
+      (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \
+      (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \
+      (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \
+      (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \
+      (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT))
+
+#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int                                : 2;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int                                : 20;
+     } pa_cl_vte_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int                                : 20;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int                                : 2;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+     } pa_cl_vte_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vte_cntl_t f;
+} pa_cl_vte_cntl_u;
+
+
+/*
+ * PA_CL_CLIP_CNTL struct
+ */
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000
+
+#define PA_CL_CLIP_CNTL_MASK \
+     (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \
+      PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \
+      PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \
+      PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \
+      PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \
+      PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK)
+
+#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \
+     ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \
+      (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \
+      (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \
+      (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \
+      (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \
+      (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \
+      (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \
+      (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT))
+
+#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 16;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int                                : 7;
+     } pa_cl_clip_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 7;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 16;
+     } pa_cl_clip_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_clip_cntl_t f;
+} pa_cl_clip_cntl_u;
+
+
+/*
+ * PA_CL_GB_VERT_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_CLIP_ADJ_MASK \
+     (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \
+     ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \
+     pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_clip_adj_t f;
+} pa_cl_gb_vert_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_VERT_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_DISC_ADJ_MASK \
+     (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \
+     ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \
+     pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_disc_adj_t f;
+} pa_cl_gb_vert_disc_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \
+     (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \
+     ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \
+     pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_clip_adj_t f;
+} pa_cl_gb_horz_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_DISC_ADJ_MASK \
+     (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \
+     ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \
+     pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_disc_adj_t f;
+} pa_cl_gb_horz_disc_adj_u;
+
+
+/*
+ * PA_CL_ENHANCE struct
+ */
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1
+#define PA_CL_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0
+#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001
+#define PA_CL_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_CL_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_CL_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_CL_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_CL_ENHANCE_MASK \
+     (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE3_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE2_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE1_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \
+      (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+          unsigned int                                : 27;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_cl_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 27;
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+     } pa_cl_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_enhance_t f;
+} pa_cl_enhance_u;
+
+
+/*
+ * PA_SC_ENHANCE struct
+ */
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_SC_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_SC_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_SC_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_SC_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_SC_ENHANCE_MASK \
+     (PA_SC_ENHANCE_ECO_SPARE3_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE2_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE1_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int                                : 28;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_sc_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 28;
+     } pa_sc_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_enhance_t f;
+} pa_sc_enhance_u;
+
+
+/*
+ * PA_SU_VTX_CNTL struct
+ */
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1
+#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2
+#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0
+#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1
+#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001
+#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006
+#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038
+
+#define PA_SU_VTX_CNTL_MASK \
+     (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \
+      PA_SU_VTX_CNTL_ROUND_MODE_MASK | \
+      PA_SU_VTX_CNTL_QUANT_MODE_MASK)
+
+#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \
+     ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \
+      (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \
+      (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT))
+
+#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int                                : 26;
+     } pa_su_vtx_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int                                : 26;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+     } pa_su_vtx_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_vtx_cntl_t f;
+} pa_su_vtx_cntl_u;
+
+
+/*
+ * PA_SU_POINT_SIZE struct
+ */
+
+#define PA_SU_POINT_SIZE_HEIGHT_SIZE   16
+#define PA_SU_POINT_SIZE_WIDTH_SIZE    16
+
+#define PA_SU_POINT_SIZE_HEIGHT_SHIFT  0
+#define PA_SU_POINT_SIZE_WIDTH_SHIFT   16
+
+#define PA_SU_POINT_SIZE_HEIGHT_MASK   0x0000ffff
+#define PA_SU_POINT_SIZE_WIDTH_MASK    0xffff0000
+
+#define PA_SU_POINT_SIZE_MASK \
+     (PA_SU_POINT_SIZE_HEIGHT_MASK | \
+      PA_SU_POINT_SIZE_WIDTH_MASK)
+
+#define PA_SU_POINT_SIZE(height, width) \
+     ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \
+      (width << PA_SU_POINT_SIZE_WIDTH_SHIFT))
+
+#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+     } pa_su_point_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+     } pa_su_point_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_size_t f;
+} pa_su_point_size_u;
+
+
+/*
+ * PA_SU_POINT_MINMAX struct
+ */
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff
+#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000
+
+#define PA_SU_POINT_MINMAX_MASK \
+     (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \
+      PA_SU_POINT_MINMAX_MAX_SIZE_MASK)
+
+#define PA_SU_POINT_MINMAX(min_size, max_size) \
+     ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \
+      (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT))
+
+#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_minmax_t f;
+} pa_su_point_minmax_u;
+
+
+/*
+ * PA_SU_LINE_CNTL struct
+ */
+
+#define PA_SU_LINE_CNTL_WIDTH_SIZE     16
+
+#define PA_SU_LINE_CNTL_WIDTH_SHIFT    0
+
+#define PA_SU_LINE_CNTL_WIDTH_MASK     0x0000ffff
+
+#define PA_SU_LINE_CNTL_MASK \
+     (PA_SU_LINE_CNTL_WIDTH_MASK)
+
+#define PA_SU_LINE_CNTL(width) \
+     ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT))
+
+#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \
+     ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \
+     pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+          unsigned int                                : 16;
+     } pa_su_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int                                : 16;
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+     } pa_su_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_line_cntl_t f;
+} pa_su_line_cntl_u;
+
+
+/*
+ * PA_SU_FACE_DATA struct
+ */
+
+#define PA_SU_FACE_DATA_BASE_ADDR_SIZE 27
+
+#define PA_SU_FACE_DATA_BASE_ADDR_SHIFT 5
+
+#define PA_SU_FACE_DATA_BASE_ADDR_MASK 0xffffffe0
+
+#define PA_SU_FACE_DATA_MASK \
+     (PA_SU_FACE_DATA_BASE_ADDR_MASK)
+
+#define PA_SU_FACE_DATA(base_addr) \
+     ((base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT))
+
+#define PA_SU_FACE_DATA_GET_BASE_ADDR(pa_su_face_data) \
+     ((pa_su_face_data & PA_SU_FACE_DATA_BASE_ADDR_MASK) >> PA_SU_FACE_DATA_BASE_ADDR_SHIFT)
+
+#define PA_SU_FACE_DATA_SET_BASE_ADDR(pa_su_face_data_reg, base_addr) \
+     pa_su_face_data_reg = (pa_su_face_data_reg & ~PA_SU_FACE_DATA_BASE_ADDR_MASK) | (base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_face_data_t {
+          unsigned int                                : 5;
+          unsigned int base_addr                      : PA_SU_FACE_DATA_BASE_ADDR_SIZE;
+     } pa_su_face_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_face_data_t {
+          unsigned int base_addr                      : PA_SU_FACE_DATA_BASE_ADDR_SIZE;
+          unsigned int                                : 5;
+     } pa_su_face_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_face_data_t f;
+} pa_su_face_data_u;
+
+
+/*
+ * PA_SU_SC_MODE_CNTL struct
+ */
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_SIZE   1
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE 1
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1
+#define PA_SU_SC_MODE_CNTL_FACE_SHIFT  2
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26
+#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT 28
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT 29
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT 30
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT 31
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002
+#define PA_SU_SC_MODE_CNTL_FACE_MASK   0x00000004
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000
+#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK 0x10000000
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK 0x20000000
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK 0x40000000
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK 0x80000000
+
+#define PA_SU_SC_MODE_CNTL_MASK \
+     (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \
+      PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \
+      PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \
+      PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \
+      PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK | \
+      PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK | \
+      PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK)
+
+#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state, clamped_faceness, zero_area_faceness, face_kill_enable, face_write_enable) \
+     ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \
+      (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \
+      (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \
+      (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \
+      (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \
+      (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \
+      (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \
+      (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \
+      (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \
+      (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \
+      (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \
+      (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \
+      (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \
+      (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \
+      (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \
+      (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \
+      (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \
+      (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) | \
+      (clamped_faceness << PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT) | \
+      (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) | \
+      (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) | \
+      (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT))
+
+#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_CLAMPED_FACENESS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)
+
+#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_CLAMPED_FACENESS(pa_su_sc_mode_cntl_reg, clamped_faceness) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK) | (clamped_faceness << PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl_reg, zero_area_faceness) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) | (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl_reg, face_kill_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) | (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl_reg, face_write_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) | (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int clamped_faceness               : PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE;
+          unsigned int zero_area_faceness             : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE;
+          unsigned int face_kill_enable               : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE;
+          unsigned int face_write_enable              : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int face_write_enable              : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE;
+          unsigned int face_kill_enable               : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE;
+          unsigned int zero_area_faceness             : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE;
+          unsigned int clamped_faceness               : PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE;
+          unsigned int                                : 1;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_sc_mode_cntl_t f;
+} pa_su_sc_mode_cntl_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \
+     ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \
+     pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_scale_t f;
+} pa_su_poly_offset_front_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \
+     ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \
+     pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_offset_t f;
+} pa_su_poly_offset_front_offset_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \
+     ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \
+     pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_scale_t f;
+} pa_su_poly_offset_back_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \
+     ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \
+     pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_offset_t f;
+} pa_su_poly_offset_back_offset_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER0_SELECT_MASK \
+     (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \
+     ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \
+     pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_select_t f;
+} pa_su_perfcounter0_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER1_SELECT_MASK \
+     (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \
+     ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \
+     pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_select_t f;
+} pa_su_perfcounter1_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER2_SELECT_MASK \
+     (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \
+     ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \
+     pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_select_t f;
+} pa_su_perfcounter2_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER3_SELECT_MASK \
+     (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \
+     ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \
+     pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_select_t f;
+} pa_su_perfcounter3_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER0_LOW_MASK \
+     (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \
+     ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \
+     pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_low_t f;
+} pa_su_perfcounter0_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER0_HI_MASK \
+     (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \
+     ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \
+     pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_hi_t f;
+} pa_su_perfcounter0_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER1_LOW_MASK \
+     (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \
+     ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \
+     pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_low_t f;
+} pa_su_perfcounter1_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER1_HI_MASK \
+     (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \
+     ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \
+     pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_hi_t f;
+} pa_su_perfcounter1_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER2_LOW_MASK \
+     (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \
+     ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \
+     pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_low_t f;
+} pa_su_perfcounter2_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER2_HI_MASK \
+     (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \
+     ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \
+     pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_hi_t f;
+} pa_su_perfcounter2_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER3_LOW_MASK \
+     (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \
+     ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \
+     pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_low_t f;
+} pa_su_perfcounter3_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER3_HI_MASK \
+     (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \
+     ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \
+     pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_hi_t f;
+} pa_su_perfcounter3_hi_u;
+
+
+/*
+ * PA_SC_WINDOW_OFFSET struct
+ */
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000
+
+#define PA_SC_WINDOW_OFFSET_MASK \
+     (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \
+      PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK)
+
+#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \
+     ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \
+      (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT))
+
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_window_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+     } pa_sc_window_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_offset_t f;
+} pa_sc_window_offset_u;
+
+
+/*
+ * PA_SC_AA_CONFIG struct
+ */
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000
+
+#define PA_SC_AA_CONFIG_MASK \
+     (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \
+      PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK)
+
+#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \
+     ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \
+      (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT))
+
+#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+          unsigned int                                : 10;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 15;
+     } pa_sc_aa_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int                                : 15;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 10;
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+     } pa_sc_aa_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_config_t f;
+} pa_sc_aa_config_u;
+
+
+/*
+ * PA_SC_AA_MASK struct
+ */
+
+#define PA_SC_AA_MASK_AA_MASK_SIZE     16
+
+#define PA_SC_AA_MASK_AA_MASK_SHIFT    0
+
+#define PA_SC_AA_MASK_AA_MASK_MASK     0x0000ffff
+
+#define PA_SC_AA_MASK_MASK \
+     (PA_SC_AA_MASK_AA_MASK_MASK)
+
+#define PA_SC_AA_MASK(aa_mask) \
+     ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT))
+
+#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \
+     ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \
+     pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_aa_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int                                : 16;
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+     } pa_sc_aa_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_mask_t f;
+} pa_sc_aa_mask_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000
+
+#define PA_SC_LINE_STIPPLE_MASK \
+     (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \
+      PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \
+      PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \
+      PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK)
+
+#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \
+     ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \
+      (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \
+      (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \
+      (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_line_stipple_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int                                : 1;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int                                : 4;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+     } pa_sc_line_stipple_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_t f;
+} pa_sc_line_stipple_u;
+
+
+/*
+ * PA_SC_LINE_CNTL struct
+ */
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200
+#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400
+
+#define PA_SC_LINE_CNTL_MASK \
+     (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \
+      PA_SC_LINE_CNTL_LAST_PIXEL_MASK)
+
+#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \
+     ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \
+      (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \
+      (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \
+      (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT))
+
+#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int                                : 21;
+     } pa_sc_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int                                : 21;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+     } pa_sc_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_cntl_t f;
+} pa_sc_line_cntl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_TL struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000
+
+#define PA_SC_WINDOW_SCISSOR_TL_MASK \
+     (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \
+     ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \
+      (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_tl_t f;
+} pa_sc_window_scissor_tl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_BR struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000
+
+#define PA_SC_WINDOW_SCISSOR_BR_MASK \
+     (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+     } pa_sc_window_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_window_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_br_t f;
+} pa_sc_window_scissor_br_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_TL struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_TL_MASK \
+     (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \
+     ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_screen_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_tl_t f;
+} pa_sc_screen_scissor_tl_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_BR struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_BR_MASK \
+     (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_screen_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_br_t f;
+} pa_sc_screen_scissor_br_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY struct
+ */
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080
+
+#define PA_SC_VIZ_QUERY_MASK \
+     (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \
+      PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \
+      PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK)
+
+#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \
+     ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \
+      (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \
+      (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT))
+
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int                                : 1;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_viz_query_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int                                : 24;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 1;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+     } pa_sc_viz_query_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_t f;
+} pa_sc_viz_query_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY_STATUS struct
+ */
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff
+
+#define PA_SC_VIZ_QUERY_STATUS_MASK \
+     (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK)
+
+#define PA_SC_VIZ_QUERY_STATUS(status_bits) \
+     ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT))
+
+#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \
+     ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \
+     pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_status_t f;
+} pa_sc_viz_query_status_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE_STATE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00
+
+#define PA_SC_LINE_STIPPLE_STATE_MASK \
+     (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \
+      PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK)
+
+#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \
+     ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \
+      (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_line_stipple_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int                                : 16;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+     } pa_sc_line_stipple_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_state_t f;
+} pa_sc_line_stipple_state_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SC_PERFCOUNTER0_SELECT_MASK \
+     (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \
+     ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \
+     pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_sc_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_select_t f;
+} pa_sc_perfcounter0_select_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SC_PERFCOUNTER0_LOW_MASK \
+     (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \
+     ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \
+     pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_low_t f;
+} pa_sc_perfcounter0_low_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SC_PERFCOUNTER0_HI_MASK \
+     (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \
+     ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \
+     pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_hi_t f;
+} pa_sc_perfcounter0_hi_u;
+
+
+/*
+ * PA_CL_CNTL_STATUS struct
+ */
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000
+
+#define PA_CL_CNTL_STATUS_MASK \
+     (PA_CL_CNTL_STATUS_CL_BUSY_MASK)
+
+#define PA_CL_CNTL_STATUS(cl_busy) \
+     ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT))
+
+#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \
+     ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \
+     pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+     } pa_cl_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_cl_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_cntl_status_t f;
+} pa_cl_cntl_status_u;
+
+
+/*
+ * PA_SU_CNTL_STATUS struct
+ */
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000
+
+#define PA_SU_CNTL_STATUS_MASK \
+     (PA_SU_CNTL_STATUS_SU_BUSY_MASK)
+
+#define PA_SU_CNTL_STATUS(su_busy) \
+     ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT))
+
+#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \
+     ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \
+     pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+     } pa_su_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_su_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_cntl_status_t f;
+} pa_su_cntl_status_u;
+
+
+/*
+ * PA_SC_CNTL_STATUS struct
+ */
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000
+
+#define PA_SC_CNTL_STATUS_MASK \
+     (PA_SC_CNTL_STATUS_SC_BUSY_MASK)
+
+#define PA_SC_CNTL_STATUS(sc_busy) \
+     ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT))
+
+#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \
+     ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \
+     pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+     } pa_sc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_sc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_cntl_status_t f;
+} pa_sc_cntl_status_u;
+
+
+/*
+ * PA_SU_DEBUG_CNTL struct
+ */
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SU_DEBUG_CNTL_MASK \
+     (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK)
+
+#define PA_SU_DEBUG_CNTL(su_debug_indx) \
+     ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT))
+
+#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \
+     ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \
+     pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_su_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+     } pa_su_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_cntl_t f;
+} pa_su_debug_cntl_u;
+
+
+/*
+ * PA_SU_DEBUG_DATA struct
+ */
+
+#define PA_SU_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SU_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SU_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SU_DEBUG_DATA_MASK \
+     (PA_SU_DEBUG_DATA_DATA_MASK)
+
+#define PA_SU_DEBUG_DATA(data) \
+     ((data << PA_SU_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \
+     ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \
+     pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_data_t f;
+} pa_su_debug_data_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG00 struct
+ */
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000
+
+#define CLIPPER_DEBUG_REG00_MASK \
+     (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \
+     ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \
+      (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \
+      (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \
+      (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \
+      (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \
+      (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \
+      (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \
+      (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \
+      (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \
+      (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \
+      (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \
+      (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \
+      (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \
+      (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \
+      (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \
+      (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \
+      (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \
+      (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \
+      (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \
+      (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+     } clipper_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg00_t f;
+} clipper_debug_reg00_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG01 struct
+ */
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000
+
+#define CLIPPER_DEBUG_REG01_MASK \
+     (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \
+      CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \
+     ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \
+      (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \
+      (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \
+      (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \
+      (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \
+      (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \
+      (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+     } clipper_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg01_t f;
+} clipper_debug_reg01_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG02 struct
+ */
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+
+#define CLIPPER_DEBUG_REG02_MASK \
+     (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \
+      CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK)
+
+#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \
+     ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \
+      (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT))
+
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+     } clipper_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+     } clipper_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg02_t f;
+} clipper_debug_reg02_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG03 struct
+ */
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG03_MASK \
+     (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \
+     ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+     } clipper_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg03_t f;
+} clipper_debug_reg03_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG04 struct
+ */
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00
+
+#define CLIPPER_DEBUG_REG04_MASK \
+     (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \
+     ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+     } clipper_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg04_t f;
+} clipper_debug_reg04_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG05 struct
+ */
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000
+
+#define CLIPPER_DEBUG_REG05_MASK \
+     (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \
+     ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \
+      (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+     } clipper_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg05_t f;
+} clipper_debug_reg05_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG09 struct
+ */
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000
+#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000
+
+#define CLIPPER_DEBUG_REG09_MASK \
+     (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \
+      CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK)
+
+#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \
+     ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \
+      (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \
+      (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \
+      (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \
+      (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \
+      (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \
+      (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \
+      (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \
+      (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT))
+
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+     } clipper_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+     } clipper_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg09_t f;
+} clipper_debug_reg09_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG10 struct
+ */
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG10_MASK \
+     (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK)
+
+#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \
+     ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \
+      (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \
+      (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \
+      (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \
+      (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT))
+
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+     } clipper_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+     } clipper_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg10_t f;
+} clipper_debug_reg10_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG11 struct
+ */
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0
+
+#define CLIPPER_DEBUG_REG11_MASK \
+     (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \
+      CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \
+     ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+     } clipper_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg11_t f;
+} clipper_debug_reg11_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG12 struct
+ */
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define CLIPPER_DEBUG_REG12_MASK \
+     (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \
+      CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \
+     ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \
+      (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \
+      (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \
+      (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \
+      (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \
+      (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+     } clipper_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg12_t f;
+} clipper_debug_reg12_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG13 struct
+ */
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000
+#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000
+
+#define CLIPPER_DEBUG_REG13_MASK \
+     (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \
+     ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \
+      (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \
+      (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \
+      (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+     } clipper_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg13_t f;
+} clipper_debug_reg13_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG0 struct
+ */
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4
+#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3
+#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0
+#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380
+#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000
+
+#define SXIFCCG_DEBUG_REG0_MASK \
+     (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \
+      SXIFCCG_DEBUG_REG0_position_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG0_point_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK)
+
+#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \
+     ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \
+      (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \
+      (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \
+      (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \
+      (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \
+      (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \
+      (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \
+      (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT))
+
+#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg0_t f;
+} sxifccg_debug_reg0_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG1 struct
+ */
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4
+#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c
+#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000
+#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000
+#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000
+
+#define SXIFCCG_DEBUG_REG1_MASK \
+     (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \
+      SXIFCCG_DEBUG_REG1_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \
+      SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG1_aux_sel_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \
+      SXIFCCG_DEBUG_REG1_param_cache_base_MASK)
+
+#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \
+     ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \
+      (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \
+      (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \
+      (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \
+      (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \
+      (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \
+      (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \
+      (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT))
+
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg1_t f;
+} sxifccg_debug_reg1_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG2 struct
+ */
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002
+#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8
+#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000
+
+#define SXIFCCG_DEBUG_REG2_MASK \
+     (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_aux_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK)
+
+#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \
+     ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \
+      (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \
+      (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \
+      (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \
+      (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \
+      (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \
+      (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \
+      (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \
+      (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \
+      (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT))
+
+#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg2_t f;
+} sxifccg_debug_reg2_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG3 struct
+ */
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4
+#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8
+#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010
+#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00
+#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define SXIFCCG_DEBUG_REG3_MASK \
+     (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG3_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG3_current_state_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK)
+
+#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \
+     ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \
+      (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \
+      (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \
+      (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \
+      (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \
+      (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \
+      (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \
+      (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT))
+
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg3_t f;
+} sxifccg_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG0 struct
+ */
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5
+#define SETUP_DEBUG_REG0_pmode_state_SIZE 6
+#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1
+#define SETUP_DEBUG_REG0_geom_enable_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1
+#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1
+#define SETUP_DEBUG_REG0_geom_busy_SIZE 1
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0
+#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5
+#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11
+#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13
+#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14
+#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15
+#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16
+#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17
+
+#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f
+#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0
+#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800
+#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000
+#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000
+#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000
+#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000
+#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000
+
+#define SETUP_DEBUG_REG0_MASK \
+     (SETUP_DEBUG_REG0_su_cntl_state_MASK | \
+      SETUP_DEBUG_REG0_pmode_state_MASK | \
+      SETUP_DEBUG_REG0_ge_stallb_MASK | \
+      SETUP_DEBUG_REG0_geom_enable_MASK | \
+      SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \
+      SETUP_DEBUG_REG0_su_clip_rtr_MASK | \
+      SETUP_DEBUG_REG0_pfifo_busy_MASK | \
+      SETUP_DEBUG_REG0_su_cntl_busy_MASK | \
+      SETUP_DEBUG_REG0_geom_busy_MASK)
+
+#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \
+     ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \
+      (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \
+      (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \
+      (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \
+      (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \
+      (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \
+      (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \
+      (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \
+      (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT))
+
+#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int                                : 14;
+     } setup_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int                                : 14;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+     } setup_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg0_t f;
+} setup_debug_reg0_u;
+
+
+/*
+ * SETUP_DEBUG_REG1 struct
+ */
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG1_MASK \
+     (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \
+      SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \
+     ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \
+      (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int                                : 4;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+     } setup_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg1_t f;
+} setup_debug_reg1_u;
+
+
+/*
+ * SETUP_DEBUG_REG2 struct
+ */
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG2_MASK \
+     (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \
+      SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \
+     ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \
+      (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int                                : 4;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+     } setup_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg2_t f;
+} setup_debug_reg2_u;
+
+
+/*
+ * SETUP_DEBUG_REG3 struct
+ */
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG3_MASK \
+     (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \
+      SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \
+     ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \
+      (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int                                : 4;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+     } setup_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg3_t f;
+} setup_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG4 struct
+ */
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11
+#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1
+#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3
+#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3
+#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2
+#define SETUP_DEBUG_REG4_type_gated_SIZE 3
+#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_event_gated_SIZE 1
+#define SETUP_DEBUG_REG4_eop_gated_SIZE 1
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0
+#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11
+#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12
+#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13
+#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17
+#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21
+#define SETUP_DEBUG_REG4_type_gated_SHIFT 23
+#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27
+#define SETUP_DEBUG_REG4_event_gated_SHIFT 28
+#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800
+#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000
+#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000
+#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000
+#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000
+#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000
+#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000
+#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000
+#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000
+#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000
+#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000
+
+#define SETUP_DEBUG_REG4_MASK \
+     (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \
+      SETUP_DEBUG_REG4_null_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_backfacing_gated_MASK | \
+      SETUP_DEBUG_REG4_st_indx_gated_MASK | \
+      SETUP_DEBUG_REG4_clipped_gated_MASK | \
+      SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \
+      SETUP_DEBUG_REG4_xmajor_gated_MASK | \
+      SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \
+      SETUP_DEBUG_REG4_type_gated_MASK | \
+      SETUP_DEBUG_REG4_fpov_gated_MASK | \
+      SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_event_gated_MASK | \
+      SETUP_DEBUG_REG4_eop_gated_MASK)
+
+#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \
+     ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \
+      (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \
+      (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \
+      (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \
+      (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \
+      (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \
+      (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \
+      (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \
+      (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \
+      (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \
+      (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \
+      (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \
+      (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT))
+
+#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int                                : 2;
+     } setup_debug_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int                                : 2;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+     } setup_debug_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg4_t f;
+} setup_debug_reg4_u;
+
+
+/*
+ * SETUP_DEBUG_REG5 struct
+ */
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2
+#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22
+#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000
+#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000
+
+#define SETUP_DEBUG_REG5_MASK \
+     (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \
+      SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \
+      SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \
+      SETUP_DEBUG_REG5_event_id_gated_MASK)
+
+#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \
+     ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \
+      (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \
+      (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \
+      (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT))
+
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int                                : 3;
+     } setup_debug_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int                                : 3;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+     } setup_debug_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg5_t f;
+} setup_debug_reg5_u;
+
+
+/*
+ * PA_SC_DEBUG_CNTL struct
+ */
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SC_DEBUG_CNTL_MASK \
+     (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK)
+
+#define PA_SC_DEBUG_CNTL(sc_debug_indx) \
+     ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT))
+
+#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \
+     ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \
+     pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_sc_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+     } pa_sc_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_cntl_t f;
+} pa_sc_debug_cntl_u;
+
+
+/*
+ * PA_SC_DEBUG_DATA struct
+ */
+
+#define PA_SC_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SC_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SC_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SC_DEBUG_DATA_MASK \
+     (PA_SC_DEBUG_DATA_DATA_MASK)
+
+#define PA_SC_DEBUG_DATA(data) \
+     ((data << PA_SC_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \
+     ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \
+     pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_data_t f;
+} pa_sc_debug_data_u;
+
+
+/*
+ * SC_DEBUG_0 struct
+ */
+
+#define SC_DEBUG_0_pa_freeze_b1_SIZE   1
+#define SC_DEBUG_0_pa_sc_valid_SIZE    1
+#define SC_DEBUG_0_pa_sc_phase_SIZE    3
+#define SC_DEBUG_0_cntx_cnt_SIZE       7
+#define SC_DEBUG_0_decr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_incr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_trigger_SIZE        1
+
+#define SC_DEBUG_0_pa_freeze_b1_SHIFT  0
+#define SC_DEBUG_0_pa_sc_valid_SHIFT   1
+#define SC_DEBUG_0_pa_sc_phase_SHIFT   2
+#define SC_DEBUG_0_cntx_cnt_SHIFT      5
+#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12
+#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13
+#define SC_DEBUG_0_trigger_SHIFT       31
+
+#define SC_DEBUG_0_pa_freeze_b1_MASK   0x00000001
+#define SC_DEBUG_0_pa_sc_valid_MASK    0x00000002
+#define SC_DEBUG_0_pa_sc_phase_MASK    0x0000001c
+#define SC_DEBUG_0_cntx_cnt_MASK       0x00000fe0
+#define SC_DEBUG_0_decr_cntx_cnt_MASK  0x00001000
+#define SC_DEBUG_0_incr_cntx_cnt_MASK  0x00002000
+#define SC_DEBUG_0_trigger_MASK        0x80000000
+
+#define SC_DEBUG_0_MASK \
+     (SC_DEBUG_0_pa_freeze_b1_MASK | \
+      SC_DEBUG_0_pa_sc_valid_MASK | \
+      SC_DEBUG_0_pa_sc_phase_MASK | \
+      SC_DEBUG_0_cntx_cnt_MASK | \
+      SC_DEBUG_0_decr_cntx_cnt_MASK | \
+      SC_DEBUG_0_incr_cntx_cnt_MASK | \
+      SC_DEBUG_0_trigger_MASK)
+
+#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \
+     ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \
+      (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \
+      (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \
+      (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \
+      (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \
+      (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \
+      (trigger << SC_DEBUG_0_trigger_SHIFT))
+
+#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_trigger(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT)
+
+#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int                                : 17;
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+     } sc_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+          unsigned int                                : 17;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+     } sc_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_0_t f;
+} sc_debug_0_u;
+
+
+/*
+ * SC_DEBUG_1 struct
+ */
+
+#define SC_DEBUG_1_em_state_SIZE       3
+#define SC_DEBUG_1_em1_data_ready_SIZE 1
+#define SC_DEBUG_1_em2_data_ready_SIZE 1
+#define SC_DEBUG_1_move_em1_to_em2_SIZE 1
+#define SC_DEBUG_1_ef_data_ready_SIZE  1
+#define SC_DEBUG_1_ef_state_SIZE       2
+#define SC_DEBUG_1_pipe_valid_SIZE     1
+#define SC_DEBUG_1_trigger_SIZE        1
+
+#define SC_DEBUG_1_em_state_SHIFT      0
+#define SC_DEBUG_1_em1_data_ready_SHIFT 3
+#define SC_DEBUG_1_em2_data_ready_SHIFT 4
+#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5
+#define SC_DEBUG_1_ef_data_ready_SHIFT 6
+#define SC_DEBUG_1_ef_state_SHIFT      7
+#define SC_DEBUG_1_pipe_valid_SHIFT    9
+#define SC_DEBUG_1_trigger_SHIFT       31
+
+#define SC_DEBUG_1_em_state_MASK       0x00000007
+#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008
+#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010
+#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020
+#define SC_DEBUG_1_ef_data_ready_MASK  0x00000040
+#define SC_DEBUG_1_ef_state_MASK       0x00000180
+#define SC_DEBUG_1_pipe_valid_MASK     0x00000200
+#define SC_DEBUG_1_trigger_MASK        0x80000000
+
+#define SC_DEBUG_1_MASK \
+     (SC_DEBUG_1_em_state_MASK | \
+      SC_DEBUG_1_em1_data_ready_MASK | \
+      SC_DEBUG_1_em2_data_ready_MASK | \
+      SC_DEBUG_1_move_em1_to_em2_MASK | \
+      SC_DEBUG_1_ef_data_ready_MASK | \
+      SC_DEBUG_1_ef_state_MASK | \
+      SC_DEBUG_1_pipe_valid_MASK | \
+      SC_DEBUG_1_trigger_MASK)
+
+#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \
+     ((em_state << SC_DEBUG_1_em_state_SHIFT) | \
+      (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \
+      (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \
+      (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \
+      (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \
+      (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \
+      (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \
+      (trigger << SC_DEBUG_1_trigger_SHIFT))
+
+#define SC_DEBUG_1_GET_em_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_GET_trigger(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT)
+
+#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int                                : 21;
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+     } sc_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+          unsigned int                                : 21;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+     } sc_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_1_t f;
+} sc_debug_1_u;
+
+
+/*
+ * SC_DEBUG_2 struct
+ */
+
+#define SC_DEBUG_2_rc_rtr_dly_SIZE     1
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1
+#define SC_DEBUG_2_pipe_freeze_b_SIZE  1
+#define SC_DEBUG_2_prim_rts_SIZE       1
+#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1
+#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1
+#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1
+#define SC_DEBUG_2_stage0_rts_SIZE     1
+#define SC_DEBUG_2_phase_rts_dly_SIZE  1
+#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1
+#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1
+#define SC_DEBUG_2_event_id_s1_SIZE    5
+#define SC_DEBUG_2_event_s1_SIZE       1
+#define SC_DEBUG_2_trigger_SIZE        1
+
+#define SC_DEBUG_2_rc_rtr_dly_SHIFT    0
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1
+#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3
+#define SC_DEBUG_2_prim_rts_SHIFT      4
+#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5
+#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6
+#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7
+#define SC_DEBUG_2_stage0_rts_SHIFT    8
+#define SC_DEBUG_2_phase_rts_dly_SHIFT 9
+#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15
+#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16
+#define SC_DEBUG_2_event_id_s1_SHIFT   17
+#define SC_DEBUG_2_event_s1_SHIFT      22
+#define SC_DEBUG_2_trigger_SHIFT       31
+
+#define SC_DEBUG_2_rc_rtr_dly_MASK     0x00000001
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002
+#define SC_DEBUG_2_pipe_freeze_b_MASK  0x00000008
+#define SC_DEBUG_2_prim_rts_MASK       0x00000010
+#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020
+#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040
+#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080
+#define SC_DEBUG_2_stage0_rts_MASK     0x00000100
+#define SC_DEBUG_2_phase_rts_dly_MASK  0x00000200
+#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000
+#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000
+#define SC_DEBUG_2_event_id_s1_MASK    0x003e0000
+#define SC_DEBUG_2_event_s1_MASK       0x00400000
+#define SC_DEBUG_2_trigger_MASK        0x80000000
+
+#define SC_DEBUG_2_MASK \
+     (SC_DEBUG_2_rc_rtr_dly_MASK | \
+      SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \
+      SC_DEBUG_2_pipe_freeze_b_MASK | \
+      SC_DEBUG_2_prim_rts_MASK | \
+      SC_DEBUG_2_next_prim_rts_dly_MASK | \
+      SC_DEBUG_2_next_prim_rtr_dly_MASK | \
+      SC_DEBUG_2_pre_stage1_rts_d1_MASK | \
+      SC_DEBUG_2_stage0_rts_MASK | \
+      SC_DEBUG_2_phase_rts_dly_MASK | \
+      SC_DEBUG_2_end_of_prim_s1_dly_MASK | \
+      SC_DEBUG_2_pass_empty_prim_s1_MASK | \
+      SC_DEBUG_2_event_id_s1_MASK | \
+      SC_DEBUG_2_event_s1_MASK | \
+      SC_DEBUG_2_trigger_MASK)
+
+#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \
+     ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \
+      (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \
+      (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \
+      (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \
+      (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \
+      (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \
+      (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \
+      (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \
+      (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \
+      (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \
+      (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \
+      (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \
+      (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \
+      (trigger << SC_DEBUG_2_trigger_SHIFT))
+
+#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_GET_trigger(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT)
+
+#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int                                : 1;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int                                : 8;
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+     } sc_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+          unsigned int                                : 8;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int                                : 1;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+     } sc_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_2_t f;
+} sc_debug_2_u;
+
+
+/*
+ * SC_DEBUG_3 struct
+ */
+
+#define SC_DEBUG_3_x_curr_s1_SIZE      11
+#define SC_DEBUG_3_y_curr_s1_SIZE      11
+#define SC_DEBUG_3_trigger_SIZE        1
+
+#define SC_DEBUG_3_x_curr_s1_SHIFT     0
+#define SC_DEBUG_3_y_curr_s1_SHIFT     11
+#define SC_DEBUG_3_trigger_SHIFT       31
+
+#define SC_DEBUG_3_x_curr_s1_MASK      0x000007ff
+#define SC_DEBUG_3_y_curr_s1_MASK      0x003ff800
+#define SC_DEBUG_3_trigger_MASK        0x80000000
+
+#define SC_DEBUG_3_MASK \
+     (SC_DEBUG_3_x_curr_s1_MASK | \
+      SC_DEBUG_3_y_curr_s1_MASK | \
+      SC_DEBUG_3_trigger_MASK)
+
+#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \
+     ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \
+      (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \
+      (trigger << SC_DEBUG_3_trigger_SHIFT))
+
+#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_trigger(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT)
+
+#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int                                : 9;
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+     } sc_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+          unsigned int                                : 9;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+     } sc_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_3_t f;
+} sc_debug_3_u;
+
+
+/*
+ * SC_DEBUG_4 struct
+ */
+
+#define SC_DEBUG_4_y_end_s1_SIZE       14
+#define SC_DEBUG_4_y_start_s1_SIZE     14
+#define SC_DEBUG_4_y_dir_s1_SIZE       1
+#define SC_DEBUG_4_trigger_SIZE        1
+
+#define SC_DEBUG_4_y_end_s1_SHIFT      0
+#define SC_DEBUG_4_y_start_s1_SHIFT    14
+#define SC_DEBUG_4_y_dir_s1_SHIFT      28
+#define SC_DEBUG_4_trigger_SHIFT       31
+
+#define SC_DEBUG_4_y_end_s1_MASK       0x00003fff
+#define SC_DEBUG_4_y_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_4_y_dir_s1_MASK       0x10000000
+#define SC_DEBUG_4_trigger_MASK        0x80000000
+
+#define SC_DEBUG_4_MASK \
+     (SC_DEBUG_4_y_end_s1_MASK | \
+      SC_DEBUG_4_y_start_s1_MASK | \
+      SC_DEBUG_4_y_dir_s1_MASK | \
+      SC_DEBUG_4_trigger_MASK)
+
+#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \
+     ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \
+      (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \
+      (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_4_trigger_SHIFT))
+
+#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_GET_trigger(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT)
+
+#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+     } sc_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+     } sc_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_4_t f;
+} sc_debug_4_u;
+
+
+/*
+ * SC_DEBUG_5 struct
+ */
+
+#define SC_DEBUG_5_x_end_s1_SIZE       14
+#define SC_DEBUG_5_x_start_s1_SIZE     14
+#define SC_DEBUG_5_x_dir_s1_SIZE       1
+#define SC_DEBUG_5_trigger_SIZE        1
+
+#define SC_DEBUG_5_x_end_s1_SHIFT      0
+#define SC_DEBUG_5_x_start_s1_SHIFT    14
+#define SC_DEBUG_5_x_dir_s1_SHIFT      28
+#define SC_DEBUG_5_trigger_SHIFT       31
+
+#define SC_DEBUG_5_x_end_s1_MASK       0x00003fff
+#define SC_DEBUG_5_x_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_5_x_dir_s1_MASK       0x10000000
+#define SC_DEBUG_5_trigger_MASK        0x80000000
+
+#define SC_DEBUG_5_MASK \
+     (SC_DEBUG_5_x_end_s1_MASK | \
+      SC_DEBUG_5_x_start_s1_MASK | \
+      SC_DEBUG_5_x_dir_s1_MASK | \
+      SC_DEBUG_5_trigger_MASK)
+
+#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \
+     ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \
+      (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \
+      (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_5_trigger_SHIFT))
+
+#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_GET_trigger(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT)
+
+#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+     } sc_debug_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+     } sc_debug_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_5_t f;
+} sc_debug_5_u;
+
+
+/*
+ * SC_DEBUG_6 struct
+ */
+
+#define SC_DEBUG_6_z_ff_empty_SIZE     1
+#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1
+#define SC_DEBUG_6_xy_ff_empty_SIZE    1
+#define SC_DEBUG_6_event_flag_SIZE     1
+#define SC_DEBUG_6_z_mask_needed_SIZE  1
+#define SC_DEBUG_6_state_SIZE          3
+#define SC_DEBUG_6_state_delayed_SIZE  3
+#define SC_DEBUG_6_data_valid_SIZE     1
+#define SC_DEBUG_6_data_valid_d_SIZE   1
+#define SC_DEBUG_6_tilex_delayed_SIZE  9
+#define SC_DEBUG_6_tiley_delayed_SIZE  9
+#define SC_DEBUG_6_trigger_SIZE        1
+
+#define SC_DEBUG_6_z_ff_empty_SHIFT    0
+#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1
+#define SC_DEBUG_6_xy_ff_empty_SHIFT   2
+#define SC_DEBUG_6_event_flag_SHIFT    3
+#define SC_DEBUG_6_z_mask_needed_SHIFT 4
+#define SC_DEBUG_6_state_SHIFT         5
+#define SC_DEBUG_6_state_delayed_SHIFT 8
+#define SC_DEBUG_6_data_valid_SHIFT    11
+#define SC_DEBUG_6_data_valid_d_SHIFT  12
+#define SC_DEBUG_6_tilex_delayed_SHIFT 13
+#define SC_DEBUG_6_tiley_delayed_SHIFT 22
+#define SC_DEBUG_6_trigger_SHIFT       31
+
+#define SC_DEBUG_6_z_ff_empty_MASK     0x00000001
+#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002
+#define SC_DEBUG_6_xy_ff_empty_MASK    0x00000004
+#define SC_DEBUG_6_event_flag_MASK     0x00000008
+#define SC_DEBUG_6_z_mask_needed_MASK  0x00000010
+#define SC_DEBUG_6_state_MASK          0x000000e0
+#define SC_DEBUG_6_state_delayed_MASK  0x00000700
+#define SC_DEBUG_6_data_valid_MASK     0x00000800
+#define SC_DEBUG_6_data_valid_d_MASK   0x00001000
+#define SC_DEBUG_6_tilex_delayed_MASK  0x003fe000
+#define SC_DEBUG_6_tiley_delayed_MASK  0x7fc00000
+#define SC_DEBUG_6_trigger_MASK        0x80000000
+
+#define SC_DEBUG_6_MASK \
+     (SC_DEBUG_6_z_ff_empty_MASK | \
+      SC_DEBUG_6_qmcntl_ff_empty_MASK | \
+      SC_DEBUG_6_xy_ff_empty_MASK | \
+      SC_DEBUG_6_event_flag_MASK | \
+      SC_DEBUG_6_z_mask_needed_MASK | \
+      SC_DEBUG_6_state_MASK | \
+      SC_DEBUG_6_state_delayed_MASK | \
+      SC_DEBUG_6_data_valid_MASK | \
+      SC_DEBUG_6_data_valid_d_MASK | \
+      SC_DEBUG_6_tilex_delayed_MASK | \
+      SC_DEBUG_6_tiley_delayed_MASK | \
+      SC_DEBUG_6_trigger_MASK)
+
+#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \
+     ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \
+      (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \
+      (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \
+      (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \
+      (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \
+      (state << SC_DEBUG_6_state_SHIFT) | \
+      (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \
+      (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \
+      (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \
+      (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \
+      (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \
+      (trigger << SC_DEBUG_6_trigger_SHIFT))
+
+#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_GET_state(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_GET_trigger(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT)
+
+#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+     } sc_debug_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+     } sc_debug_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_6_t f;
+} sc_debug_6_u;
+
+
+/*
+ * SC_DEBUG_7 struct
+ */
+
+#define SC_DEBUG_7_event_flag_SIZE     1
+#define SC_DEBUG_7_deallocate_SIZE     3
+#define SC_DEBUG_7_fposition_SIZE      1
+#define SC_DEBUG_7_sr_prim_we_SIZE     1
+#define SC_DEBUG_7_last_tile_SIZE      1
+#define SC_DEBUG_7_tile_ff_we_SIZE     1
+#define SC_DEBUG_7_qs_data_valid_SIZE  1
+#define SC_DEBUG_7_qs_q0_y_SIZE        2
+#define SC_DEBUG_7_qs_q0_x_SIZE        2
+#define SC_DEBUG_7_qs_q0_valid_SIZE    1
+#define SC_DEBUG_7_prim_ff_we_SIZE     1
+#define SC_DEBUG_7_tile_ff_re_SIZE     1
+#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_7_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_7_new_prim_SIZE       1
+#define SC_DEBUG_7_load_new_tile_data_SIZE 1
+#define SC_DEBUG_7_state_SIZE          2
+#define SC_DEBUG_7_fifos_ready_SIZE    1
+#define SC_DEBUG_7_trigger_SIZE        1
+
+#define SC_DEBUG_7_event_flag_SHIFT    0
+#define SC_DEBUG_7_deallocate_SHIFT    1
+#define SC_DEBUG_7_fposition_SHIFT     4
+#define SC_DEBUG_7_sr_prim_we_SHIFT    5
+#define SC_DEBUG_7_last_tile_SHIFT     6
+#define SC_DEBUG_7_tile_ff_we_SHIFT    7
+#define SC_DEBUG_7_qs_data_valid_SHIFT 8
+#define SC_DEBUG_7_qs_q0_y_SHIFT       9
+#define SC_DEBUG_7_qs_q0_x_SHIFT       11
+#define SC_DEBUG_7_qs_q0_valid_SHIFT   13
+#define SC_DEBUG_7_prim_ff_we_SHIFT    14
+#define SC_DEBUG_7_tile_ff_re_SHIFT    15
+#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16
+#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17
+#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18
+#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19
+#define SC_DEBUG_7_new_prim_SHIFT      20
+#define SC_DEBUG_7_load_new_tile_data_SHIFT 21
+#define SC_DEBUG_7_state_SHIFT         22
+#define SC_DEBUG_7_fifos_ready_SHIFT   24
+#define SC_DEBUG_7_trigger_SHIFT       31
+
+#define SC_DEBUG_7_event_flag_MASK     0x00000001
+#define SC_DEBUG_7_deallocate_MASK     0x0000000e
+#define SC_DEBUG_7_fposition_MASK      0x00000010
+#define SC_DEBUG_7_sr_prim_we_MASK     0x00000020
+#define SC_DEBUG_7_last_tile_MASK      0x00000040
+#define SC_DEBUG_7_tile_ff_we_MASK     0x00000080
+#define SC_DEBUG_7_qs_data_valid_MASK  0x00000100
+#define SC_DEBUG_7_qs_q0_y_MASK        0x00000600
+#define SC_DEBUG_7_qs_q0_x_MASK        0x00001800
+#define SC_DEBUG_7_qs_q0_valid_MASK    0x00002000
+#define SC_DEBUG_7_prim_ff_we_MASK     0x00004000
+#define SC_DEBUG_7_tile_ff_re_MASK     0x00008000
+#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000
+#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000
+#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000
+#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000
+#define SC_DEBUG_7_new_prim_MASK       0x00100000
+#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000
+#define SC_DEBUG_7_state_MASK          0x00c00000
+#define SC_DEBUG_7_fifos_ready_MASK    0x01000000
+#define SC_DEBUG_7_trigger_MASK        0x80000000
+
+#define SC_DEBUG_7_MASK \
+     (SC_DEBUG_7_event_flag_MASK | \
+      SC_DEBUG_7_deallocate_MASK | \
+      SC_DEBUG_7_fposition_MASK | \
+      SC_DEBUG_7_sr_prim_we_MASK | \
+      SC_DEBUG_7_last_tile_MASK | \
+      SC_DEBUG_7_tile_ff_we_MASK | \
+      SC_DEBUG_7_qs_data_valid_MASK | \
+      SC_DEBUG_7_qs_q0_y_MASK | \
+      SC_DEBUG_7_qs_q0_x_MASK | \
+      SC_DEBUG_7_qs_q0_valid_MASK | \
+      SC_DEBUG_7_prim_ff_we_MASK | \
+      SC_DEBUG_7_tile_ff_re_MASK | \
+      SC_DEBUG_7_fw_prim_data_valid_MASK | \
+      SC_DEBUG_7_last_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_prim_MASK | \
+      SC_DEBUG_7_new_prim_MASK | \
+      SC_DEBUG_7_load_new_tile_data_MASK | \
+      SC_DEBUG_7_state_MASK | \
+      SC_DEBUG_7_fifos_ready_MASK | \
+      SC_DEBUG_7_trigger_MASK)
+
+#define SC_DEBUG_7(event_flag, deallocate, fposition, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \
+     ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \
+      (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \
+      (fposition << SC_DEBUG_7_fposition_SHIFT) | \
+      (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \
+      (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \
+      (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \
+      (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \
+      (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \
+      (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \
+      (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \
+      (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \
+      (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \
+      (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \
+      (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \
+      (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \
+      (state << SC_DEBUG_7_state_SHIFT) | \
+      (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \
+      (trigger << SC_DEBUG_7_trigger_SHIFT))
+
+#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_GET_fposition(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fposition_MASK) >> SC_DEBUG_7_fposition_SHIFT)
+#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_GET_state(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_GET_trigger(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT)
+
+#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_SET_fposition(sc_debug_7_reg, fposition) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fposition_MASK) | (fposition << SC_DEBUG_7_fposition_SHIFT)
+#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int fposition                      : SC_DEBUG_7_fposition_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int                                : 6;
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+     } sc_debug_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+          unsigned int                                : 6;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int fposition                      : SC_DEBUG_7_fposition_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+     } sc_debug_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_7_t f;
+} sc_debug_7_u;
+
+
+/*
+ * SC_DEBUG_8 struct
+ */
+
+#define SC_DEBUG_8_sample_last_SIZE    1
+#define SC_DEBUG_8_sample_mask_SIZE    4
+#define SC_DEBUG_8_sample_y_SIZE       2
+#define SC_DEBUG_8_sample_x_SIZE       2
+#define SC_DEBUG_8_sample_send_SIZE    1
+#define SC_DEBUG_8_next_cycle_SIZE     2
+#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1
+#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1
+#define SC_DEBUG_8_num_samples_SIZE    2
+#define SC_DEBUG_8_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_8_last_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_sample_we_SIZE      1
+#define SC_DEBUG_8_fposition_SIZE      1
+#define SC_DEBUG_8_event_id_SIZE       5
+#define SC_DEBUG_8_event_flag_SIZE     1
+#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_8_trigger_SIZE        1
+
+#define SC_DEBUG_8_sample_last_SHIFT   0
+#define SC_DEBUG_8_sample_mask_SHIFT   1
+#define SC_DEBUG_8_sample_y_SHIFT      5
+#define SC_DEBUG_8_sample_x_SHIFT      7
+#define SC_DEBUG_8_sample_send_SHIFT   9
+#define SC_DEBUG_8_next_cycle_SHIFT    10
+#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12
+#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13
+#define SC_DEBUG_8_num_samples_SHIFT   14
+#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16
+#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17
+#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18
+#define SC_DEBUG_8_sample_we_SHIFT     19
+#define SC_DEBUG_8_fposition_SHIFT     20
+#define SC_DEBUG_8_event_id_SHIFT      21
+#define SC_DEBUG_8_event_flag_SHIFT    26
+#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27
+#define SC_DEBUG_8_trigger_SHIFT       31
+
+#define SC_DEBUG_8_sample_last_MASK    0x00000001
+#define SC_DEBUG_8_sample_mask_MASK    0x0000001e
+#define SC_DEBUG_8_sample_y_MASK       0x00000060
+#define SC_DEBUG_8_sample_x_MASK       0x00000180
+#define SC_DEBUG_8_sample_send_MASK    0x00000200
+#define SC_DEBUG_8_next_cycle_MASK     0x00000c00
+#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000
+#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000
+#define SC_DEBUG_8_num_samples_MASK    0x0000c000
+#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000
+#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000
+#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000
+#define SC_DEBUG_8_sample_we_MASK      0x00080000
+#define SC_DEBUG_8_fposition_MASK      0x00100000
+#define SC_DEBUG_8_event_id_MASK       0x03e00000
+#define SC_DEBUG_8_event_flag_MASK     0x04000000
+#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000
+#define SC_DEBUG_8_trigger_MASK        0x80000000
+
+#define SC_DEBUG_8_MASK \
+     (SC_DEBUG_8_sample_last_MASK | \
+      SC_DEBUG_8_sample_mask_MASK | \
+      SC_DEBUG_8_sample_y_MASK | \
+      SC_DEBUG_8_sample_x_MASK | \
+      SC_DEBUG_8_sample_send_MASK | \
+      SC_DEBUG_8_next_cycle_MASK | \
+      SC_DEBUG_8_ez_sample_ff_full_MASK | \
+      SC_DEBUG_8_rb_sc_samp_rtr_MASK | \
+      SC_DEBUG_8_num_samples_MASK | \
+      SC_DEBUG_8_last_quad_of_tile_MASK | \
+      SC_DEBUG_8_last_quad_of_prim_MASK | \
+      SC_DEBUG_8_first_quad_of_prim_MASK | \
+      SC_DEBUG_8_sample_we_MASK | \
+      SC_DEBUG_8_fposition_MASK | \
+      SC_DEBUG_8_event_id_MASK | \
+      SC_DEBUG_8_event_flag_MASK | \
+      SC_DEBUG_8_fw_prim_data_valid_MASK | \
+      SC_DEBUG_8_trigger_MASK)
+
+#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fposition, event_id, event_flag, fw_prim_data_valid, trigger) \
+     ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \
+      (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \
+      (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \
+      (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \
+      (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \
+      (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \
+      (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \
+      (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \
+      (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \
+      (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \
+      (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \
+      (fposition << SC_DEBUG_8_fposition_SHIFT) | \
+      (event_id << SC_DEBUG_8_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \
+      (trigger << SC_DEBUG_8_trigger_SHIFT))
+
+#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_GET_fposition(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fposition_MASK) >> SC_DEBUG_8_fposition_SHIFT)
+#define SC_DEBUG_8_GET_event_id(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_GET_trigger(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT)
+
+#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_SET_fposition(sc_debug_8_reg, fposition) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fposition_MASK) | (fposition << SC_DEBUG_8_fposition_SHIFT)
+#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int fposition                      : SC_DEBUG_8_fposition_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int                                : 3;
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+     } sc_debug_8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int fposition                      : SC_DEBUG_8_fposition_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+     } sc_debug_8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_8_t f;
+} sc_debug_8_u;
+
+
+/*
+ * SC_DEBUG_9 struct
+ */
+
+#define SC_DEBUG_9_rb_sc_send_SIZE     1
+#define SC_DEBUG_9_rb_sc_ez_mask_SIZE  4
+#define SC_DEBUG_9_fifo_data_ready_SIZE 1
+#define SC_DEBUG_9_early_z_enable_SIZE 1
+#define SC_DEBUG_9_mask_state_SIZE     2
+#define SC_DEBUG_9_next_ez_mask_SIZE   16
+#define SC_DEBUG_9_mask_ready_SIZE     1
+#define SC_DEBUG_9_drop_sample_SIZE    1
+#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_9_trigger_SIZE        1
+
+#define SC_DEBUG_9_rb_sc_send_SHIFT    0
+#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1
+#define SC_DEBUG_9_fifo_data_ready_SHIFT 5
+#define SC_DEBUG_9_early_z_enable_SHIFT 6
+#define SC_DEBUG_9_mask_state_SHIFT    7
+#define SC_DEBUG_9_next_ez_mask_SHIFT  9
+#define SC_DEBUG_9_mask_ready_SHIFT    25
+#define SC_DEBUG_9_drop_sample_SHIFT   26
+#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30
+#define SC_DEBUG_9_trigger_SHIFT       31
+
+#define SC_DEBUG_9_rb_sc_send_MASK     0x00000001
+#define SC_DEBUG_9_rb_sc_ez_mask_MASK  0x0000001e
+#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020
+#define SC_DEBUG_9_early_z_enable_MASK 0x00000040
+#define SC_DEBUG_9_mask_state_MASK     0x00000180
+#define SC_DEBUG_9_next_ez_mask_MASK   0x01fffe00
+#define SC_DEBUG_9_mask_ready_MASK     0x02000000
+#define SC_DEBUG_9_drop_sample_MASK    0x04000000
+#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000
+#define SC_DEBUG_9_trigger_MASK        0x80000000
+
+#define SC_DEBUG_9_MASK \
+     (SC_DEBUG_9_rb_sc_send_MASK | \
+      SC_DEBUG_9_rb_sc_ez_mask_MASK | \
+      SC_DEBUG_9_fifo_data_ready_MASK | \
+      SC_DEBUG_9_early_z_enable_MASK | \
+      SC_DEBUG_9_mask_state_MASK | \
+      SC_DEBUG_9_next_ez_mask_MASK | \
+      SC_DEBUG_9_mask_ready_MASK | \
+      SC_DEBUG_9_drop_sample_MASK | \
+      SC_DEBUG_9_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_9_trigger_MASK)
+
+#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \
+     ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \
+      (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \
+      (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \
+      (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \
+      (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \
+      (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \
+      (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \
+      (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \
+      (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \
+      (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \
+      (trigger << SC_DEBUG_9_trigger_SHIFT))
+
+#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_GET_trigger(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT)
+
+#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+     } sc_debug_9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+     } sc_debug_9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_9_t f;
+} sc_debug_9_u;
+
+
+/*
+ * SC_DEBUG_10 struct
+ */
+
+#define SC_DEBUG_10_combined_sample_mask_SIZE 16
+#define SC_DEBUG_10_trigger_SIZE       1
+
+#define SC_DEBUG_10_combined_sample_mask_SHIFT 0
+#define SC_DEBUG_10_trigger_SHIFT      31
+
+#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff
+#define SC_DEBUG_10_trigger_MASK       0x80000000
+
+#define SC_DEBUG_10_MASK \
+     (SC_DEBUG_10_combined_sample_mask_MASK | \
+      SC_DEBUG_10_trigger_MASK)
+
+#define SC_DEBUG_10(combined_sample_mask, trigger) \
+     ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \
+      (trigger << SC_DEBUG_10_trigger_SHIFT))
+
+#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_GET_trigger(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT)
+
+#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+          unsigned int                                : 15;
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+     } sc_debug_10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+          unsigned int                                : 15;
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+     } sc_debug_10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_10_t f;
+} sc_debug_10_u;
+
+
+/*
+ * SC_DEBUG_11 struct
+ */
+
+#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_11_iterator_input_fz_SIZE 1
+#define SC_DEBUG_11_packer_send_quads_SIZE 1
+#define SC_DEBUG_11_packer_send_cmd_SIZE 1
+#define SC_DEBUG_11_packer_send_event_SIZE 1
+#define SC_DEBUG_11_next_state_SIZE    3
+#define SC_DEBUG_11_state_SIZE         3
+#define SC_DEBUG_11_stall_SIZE         1
+#define SC_DEBUG_11_trigger_SIZE       1
+
+#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1
+#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3
+#define SC_DEBUG_11_iterator_input_fz_SHIFT 4
+#define SC_DEBUG_11_packer_send_quads_SHIFT 5
+#define SC_DEBUG_11_packer_send_cmd_SHIFT 6
+#define SC_DEBUG_11_packer_send_event_SHIFT 7
+#define SC_DEBUG_11_next_state_SHIFT   8
+#define SC_DEBUG_11_state_SHIFT        11
+#define SC_DEBUG_11_stall_SHIFT        14
+#define SC_DEBUG_11_trigger_SHIFT      31
+
+#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002
+#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008
+#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010
+#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020
+#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040
+#define SC_DEBUG_11_packer_send_event_MASK 0x00000080
+#define SC_DEBUG_11_next_state_MASK    0x00000700
+#define SC_DEBUG_11_state_MASK         0x00003800
+#define SC_DEBUG_11_stall_MASK         0x00004000
+#define SC_DEBUG_11_trigger_MASK       0x80000000
+
+#define SC_DEBUG_11_MASK \
+     (SC_DEBUG_11_ez_sample_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_11_ez_prim_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_11_iterator_input_fz_MASK | \
+      SC_DEBUG_11_packer_send_quads_MASK | \
+      SC_DEBUG_11_packer_send_cmd_MASK | \
+      SC_DEBUG_11_packer_send_event_MASK | \
+      SC_DEBUG_11_next_state_MASK | \
+      SC_DEBUG_11_state_MASK | \
+      SC_DEBUG_11_stall_MASK | \
+      SC_DEBUG_11_trigger_MASK)
+
+#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \
+     ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \
+      (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \
+      (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \
+      (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \
+      (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \
+      (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \
+      (next_state << SC_DEBUG_11_next_state_SHIFT) | \
+      (state << SC_DEBUG_11_state_SHIFT) | \
+      (stall << SC_DEBUG_11_stall_SHIFT) | \
+      (trigger << SC_DEBUG_11_trigger_SHIFT))
+
+#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_GET_next_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_GET_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_GET_stall(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_GET_trigger(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT)
+
+#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int                                : 16;
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+     } sc_debug_11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+          unsigned int                                : 16;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+     } sc_debug_11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_11_t f;
+} sc_debug_11_u;
+
+
+/*
+ * SC_DEBUG_12 struct
+ */
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1
+#define SC_DEBUG_12_event_id_SIZE      5
+#define SC_DEBUG_12_event_flag_SIZE    1
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_full_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1
+#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1
+#define SC_DEBUG_12_iter_qdhit0_SIZE   1
+#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1
+#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1
+#define SC_DEBUG_12_iter_phase_out_SIZE 2
+#define SC_DEBUG_12_iter_phase_reg_SIZE 2
+#define SC_DEBUG_12_iterator_SP_valid_SIZE 1
+#define SC_DEBUG_12_eopv_reg_SIZE      1
+#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1
+#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1
+#define SC_DEBUG_12_trigger_SIZE       1
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0
+#define SC_DEBUG_12_event_id_SHIFT     1
+#define SC_DEBUG_12_event_flag_SHIFT   6
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7
+#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8
+#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9
+#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11
+#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12
+#define SC_DEBUG_12_iter_qdhit0_SHIFT  13
+#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14
+#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15
+#define SC_DEBUG_12_iter_phase_out_SHIFT 16
+#define SC_DEBUG_12_iter_phase_reg_SHIFT 18
+#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20
+#define SC_DEBUG_12_eopv_reg_SHIFT     21
+#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22
+#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23
+#define SC_DEBUG_12_trigger_SHIFT      31
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001
+#define SC_DEBUG_12_event_id_MASK      0x0000003e
+#define SC_DEBUG_12_event_flag_MASK    0x00000040
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080
+#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100
+#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200
+#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400
+#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800
+#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000
+#define SC_DEBUG_12_iter_qdhit0_MASK   0x00002000
+#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000
+#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000
+#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000
+#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000
+#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000
+#define SC_DEBUG_12_eopv_reg_MASK      0x00200000
+#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000
+#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000
+#define SC_DEBUG_12_trigger_MASK       0x80000000
+
+#define SC_DEBUG_12_MASK \
+     (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \
+      SC_DEBUG_12_event_id_MASK | \
+      SC_DEBUG_12_event_flag_MASK | \
+      SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \
+      SC_DEBUG_12_itercmdfifo_full_MASK | \
+      SC_DEBUG_12_itercmdfifo_empty_MASK | \
+      SC_DEBUG_12_iter_ds_one_clk_command_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_vector_MASK | \
+      SC_DEBUG_12_iter_qdhit0_MASK | \
+      SC_DEBUG_12_bc_use_centers_reg_MASK | \
+      SC_DEBUG_12_bc_output_xy_reg_MASK | \
+      SC_DEBUG_12_iter_phase_out_MASK | \
+      SC_DEBUG_12_iter_phase_reg_MASK | \
+      SC_DEBUG_12_iterator_SP_valid_MASK | \
+      SC_DEBUG_12_eopv_reg_MASK | \
+      SC_DEBUG_12_one_clk_cmd_reg_MASK | \
+      SC_DEBUG_12_iter_dx_end_of_prim_MASK | \
+      SC_DEBUG_12_trigger_MASK)
+
+#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \
+     ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \
+      (event_id << SC_DEBUG_12_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \
+      (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \
+      (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \
+      (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \
+      (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \
+      (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \
+      (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \
+      (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \
+      (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \
+      (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \
+      (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \
+      (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \
+      (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \
+      (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \
+      (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \
+      (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \
+      (trigger << SC_DEBUG_12_trigger_SHIFT))
+
+#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_GET_event_id(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_GET_trigger(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT)
+
+#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int                                : 7;
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+     } sc_debug_12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+          unsigned int                                : 7;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+     } sc_debug_12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_12_t f;
+} sc_debug_12_u;
+
+
+#endif
+
+
+#if !defined (_VGT_FIDDLE_H)
+#define _VGT_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  vgt_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+/*
+ * VGT_OUT_PRIM_TYPE enum
+ */
+
+#define VGT_OUT_POINT                  0x00000000
+#define VGT_OUT_LINE                   0x00000001
+#define VGT_OUT_TRI                    0x00000002
+#define VGT_OUT_RECT_V0                0x00000003
+#define VGT_OUT_RECT_V1                0x00000004
+#define VGT_OUT_RECT_V2                0x00000005
+#define VGT_OUT_RECT_V3                0x00000006
+#define VGT_OUT_RESERVED               0x00000007
+#define VGT_TE_QUAD                    0x00000008
+#define VGT_TE_PRIM_INDEX_LINE         0x00000009
+#define VGT_TE_PRIM_INDEX_TRI          0x0000000a
+#define VGT_TE_PRIM_INDEX_QUAD         0x0000000b
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * GFX_COPY_STATE struct
+ */
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0
+
+#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+
+#define GFX_COPY_STATE_MASK \
+     (GFX_COPY_STATE_SRC_STATE_ID_MASK)
+
+#define GFX_COPY_STATE(src_state_id) \
+     ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT))
+
+#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \
+     ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \
+     gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 31;
+     } gfx_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int                                : 31;
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+     } gfx_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gfx_copy_state_t f;
+} gfx_copy_state_u;
+
+
+/*
+ * VGT_DRAW_INITIATOR struct
+ */
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1
+#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT 8
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11
+#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK 0x00000300
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800
+#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000
+#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000
+
+#define VGT_DRAW_INITIATOR_MASK \
+     (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \
+      VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \
+      VGT_DRAW_INITIATOR_NOT_EOP_MASK | \
+      VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \
+      VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_NUM_INDICES_MASK)
+
+#define VGT_DRAW_INITIATOR(prim_type, source_select, faceness_cull_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \
+     ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \
+      (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \
+      (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) | \
+      (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \
+      (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \
+      (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \
+      (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \
+      (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \
+      (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT))
+
+#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_FACENESS_CULL_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) >> VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_FACENESS_CULL_SELECT(vgt_draw_initiator_reg, faceness_cull_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) | (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int faceness_cull_select           : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+     } vgt_draw_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int faceness_cull_select           : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+     } vgt_draw_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_draw_initiator_t f;
+} vgt_draw_initiator_u;
+
+
+/*
+ * VGT_EVENT_INITIATOR struct
+ */
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f
+
+#define VGT_EVENT_INITIATOR_MASK \
+     (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK)
+
+#define VGT_EVENT_INITIATOR(event_type) \
+     ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT))
+
+#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \
+     ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \
+     vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+          unsigned int                                : 26;
+     } vgt_event_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int                                : 26;
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+     } vgt_event_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_event_initiator_t f;
+} vgt_event_initiator_u;
+
+
+/*
+ * VGT_DMA_BASE struct
+ */
+
+#define VGT_DMA_BASE_BASE_ADDR_SIZE    32
+
+#define VGT_DMA_BASE_BASE_ADDR_SHIFT   0
+
+#define VGT_DMA_BASE_BASE_ADDR_MASK    0xffffffff
+
+#define VGT_DMA_BASE_MASK \
+     (VGT_DMA_BASE_BASE_ADDR_MASK)
+
+#define VGT_DMA_BASE(base_addr) \
+     ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT))
+
+#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \
+     ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \
+     vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_base_t f;
+} vgt_dma_base_u;
+
+
+/*
+ * VGT_DMA_SIZE struct
+ */
+
+#define VGT_DMA_SIZE_NUM_WORDS_SIZE    24
+#define VGT_DMA_SIZE_SWAP_MODE_SIZE    2
+
+#define VGT_DMA_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_DMA_SIZE_SWAP_MODE_SHIFT   30
+
+#define VGT_DMA_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_DMA_SIZE_SWAP_MODE_MASK    0xc0000000
+
+#define VGT_DMA_SIZE_MASK \
+     (VGT_DMA_SIZE_NUM_WORDS_MASK | \
+      VGT_DMA_SIZE_SWAP_MODE_MASK)
+
+#define VGT_DMA_SIZE(num_words, swap_mode) \
+     ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \
+      (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT))
+
+#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+     } vgt_dma_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+     } vgt_dma_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_size_t f;
+} vgt_dma_size_u;
+
+
+/*
+ * VGT_BIN_BASE struct
+ */
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff
+
+#define VGT_BIN_BASE_MASK \
+     (VGT_BIN_BASE_BIN_BASE_ADDR_MASK)
+
+#define VGT_BIN_BASE(bin_base_addr) \
+     ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT))
+
+#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \
+     ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \
+     vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_base_t f;
+} vgt_bin_base_u;
+
+
+/*
+ * VGT_BIN_SIZE struct
+ */
+
+#define VGT_BIN_SIZE_NUM_WORDS_SIZE    24
+#define VGT_BIN_SIZE_FACENESS_FETCH_SIZE 1
+#define VGT_BIN_SIZE_FACENESS_RESET_SIZE 1
+
+#define VGT_BIN_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_BIN_SIZE_FACENESS_FETCH_SHIFT 30
+#define VGT_BIN_SIZE_FACENESS_RESET_SHIFT 31
+
+#define VGT_BIN_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_BIN_SIZE_FACENESS_FETCH_MASK 0x40000000
+#define VGT_BIN_SIZE_FACENESS_RESET_MASK 0x80000000
+
+#define VGT_BIN_SIZE_MASK \
+     (VGT_BIN_SIZE_NUM_WORDS_MASK | \
+      VGT_BIN_SIZE_FACENESS_FETCH_MASK | \
+      VGT_BIN_SIZE_FACENESS_RESET_MASK)
+
+#define VGT_BIN_SIZE(num_words, faceness_fetch, faceness_reset) \
+     ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) | \
+      (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) | \
+      (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT))
+
+#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+#define VGT_BIN_SIZE_GET_FACENESS_FETCH(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_FETCH_MASK) >> VGT_BIN_SIZE_FACENESS_FETCH_SHIFT)
+#define VGT_BIN_SIZE_GET_FACENESS_RESET(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_RESET_MASK) >> VGT_BIN_SIZE_FACENESS_RESET_SHIFT)
+
+#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+#define VGT_BIN_SIZE_SET_FACENESS_FETCH(vgt_bin_size_reg, faceness_fetch) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_FETCH_MASK) | (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT)
+#define VGT_BIN_SIZE_SET_FACENESS_RESET(vgt_bin_size_reg, faceness_reset) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_RESET_MASK) | (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int faceness_fetch                 : VGT_BIN_SIZE_FACENESS_FETCH_SIZE;
+          unsigned int faceness_reset                 : VGT_BIN_SIZE_FACENESS_RESET_SIZE;
+     } vgt_bin_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int faceness_reset                 : VGT_BIN_SIZE_FACENESS_RESET_SIZE;
+          unsigned int faceness_fetch                 : VGT_BIN_SIZE_FACENESS_FETCH_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+     } vgt_bin_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_size_t f;
+} vgt_bin_size_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MIN struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MIN_MASK \
+     (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_min_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+     } vgt_current_bin_id_min_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_min_t f;
+} vgt_current_bin_id_min_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MAX struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MAX_MASK \
+     (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_max_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+     } vgt_current_bin_id_max_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_max_t f;
+} vgt_current_bin_id_max_u;
+
+
+/*
+ * VGT_IMMED_DATA struct
+ */
+
+#define VGT_IMMED_DATA_DATA_SIZE       32
+
+#define VGT_IMMED_DATA_DATA_SHIFT      0
+
+#define VGT_IMMED_DATA_DATA_MASK       0xffffffff
+
+#define VGT_IMMED_DATA_MASK \
+     (VGT_IMMED_DATA_DATA_MASK)
+
+#define VGT_IMMED_DATA(data) \
+     ((data << VGT_IMMED_DATA_DATA_SHIFT))
+
+#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \
+     ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT)
+
+#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \
+     vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_immed_data_t f;
+} vgt_immed_data_u;
+
+
+/*
+ * VGT_MAX_VTX_INDX struct
+ */
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff
+
+#define VGT_MAX_VTX_INDX_MASK \
+     (VGT_MAX_VTX_INDX_MAX_INDX_MASK)
+
+#define VGT_MAX_VTX_INDX(max_indx) \
+     ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT))
+
+#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \
+     ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \
+     vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_max_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+     } vgt_max_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_max_vtx_indx_t f;
+} vgt_max_vtx_indx_u;
+
+
+/*
+ * VGT_MIN_VTX_INDX struct
+ */
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff
+
+#define VGT_MIN_VTX_INDX_MASK \
+     (VGT_MIN_VTX_INDX_MIN_INDX_MASK)
+
+#define VGT_MIN_VTX_INDX(min_indx) \
+     ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT))
+
+#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \
+     ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \
+     vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_min_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+     } vgt_min_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_min_vtx_indx_t f;
+} vgt_min_vtx_indx_u;
+
+
+/*
+ * VGT_INDX_OFFSET struct
+ */
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff
+
+#define VGT_INDX_OFFSET_MASK \
+     (VGT_INDX_OFFSET_INDX_OFFSET_MASK)
+
+#define VGT_INDX_OFFSET(indx_offset) \
+     ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT))
+
+#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \
+     ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \
+     vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+          unsigned int                                : 8;
+     } vgt_indx_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int                                : 8;
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+     } vgt_indx_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_indx_offset_t f;
+} vgt_indx_offset_u;
+
+
+/*
+ * VGT_VERTEX_REUSE_BLOCK_CNTL struct
+ */
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \
+     (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \
+     ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT))
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \
+     ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \
+     vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+          unsigned int                                : 29;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int                                : 29;
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vertex_reuse_block_cntl_t f;
+} vgt_vertex_reuse_block_cntl_u;
+
+
+/*
+ * VGT_OUT_DEALLOC_CNTL struct
+ */
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003
+
+#define VGT_OUT_DEALLOC_CNTL_MASK \
+     (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK)
+
+#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \
+     ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT))
+
+#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \
+     ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \
+     vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+          unsigned int                                : 30;
+     } vgt_out_dealloc_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int                                : 30;
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+     } vgt_out_dealloc_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_out_dealloc_cntl_t f;
+} vgt_out_dealloc_cntl_u;
+
+
+/*
+ * VGT_MULTI_PRIM_IB_RESET_INDX struct
+ */
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \
+     (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \
+     ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT))
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \
+     ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \
+     vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int                                : 8;
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_multi_prim_ib_reset_indx_t f;
+} vgt_multi_prim_ib_reset_indx_u;
+
+
+/*
+ * VGT_ENHANCE struct
+ */
+
+#define VGT_ENHANCE_MISC_SIZE          16
+
+#define VGT_ENHANCE_MISC_SHIFT         0
+
+#define VGT_ENHANCE_MISC_MASK          0x0000ffff
+
+#define VGT_ENHANCE_MASK \
+     (VGT_ENHANCE_MISC_MASK)
+
+#define VGT_ENHANCE(misc) \
+     ((misc << VGT_ENHANCE_MISC_SHIFT))
+
+#define VGT_ENHANCE_GET_MISC(vgt_enhance) \
+     ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT)
+
+#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \
+     vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+          unsigned int                                : 16;
+     } vgt_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int                                : 16;
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+     } vgt_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_enhance_t f;
+} vgt_enhance_u;
+
+
+/*
+ * VGT_VTX_VECT_EJECT_REG struct
+ */
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f
+
+#define VGT_VTX_VECT_EJECT_REG_MASK \
+     (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK)
+
+#define VGT_VTX_VECT_EJECT_REG(prim_count) \
+     ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT))
+
+#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \
+     ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \
+     vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+          unsigned int                                : 27;
+     } vgt_vtx_vect_eject_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int                                : 27;
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+     } vgt_vtx_vect_eject_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vtx_vect_eject_reg_t f;
+} vgt_vtx_vect_eject_reg_u;
+
+
+/*
+ * VGT_LAST_COPY_STATE struct
+ */
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000
+
+#define VGT_LAST_COPY_STATE_MASK \
+     (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \
+      VGT_LAST_COPY_STATE_DST_STATE_ID_MASK)
+
+#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \
+     ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \
+      (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT))
+
+#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+     } vgt_last_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+     } vgt_last_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_last_copy_state_t f;
+} vgt_last_copy_state_u;
+
+
+/*
+ * VGT_DEBUG_CNTL struct
+ */
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f
+
+#define VGT_DEBUG_CNTL_MASK \
+     (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK)
+
+#define VGT_DEBUG_CNTL(vgt_debug_indx) \
+     ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT))
+
+#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \
+     ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \
+     vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } vgt_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+     } vgt_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_cntl_t f;
+} vgt_debug_cntl_u;
+
+
+/*
+ * VGT_DEBUG_DATA struct
+ */
+
+#define VGT_DEBUG_DATA_DATA_SIZE       32
+
+#define VGT_DEBUG_DATA_DATA_SHIFT      0
+
+#define VGT_DEBUG_DATA_DATA_MASK       0xffffffff
+
+#define VGT_DEBUG_DATA_MASK \
+     (VGT_DEBUG_DATA_DATA_MASK)
+
+#define VGT_DEBUG_DATA(data) \
+     ((data << VGT_DEBUG_DATA_DATA_SHIFT))
+
+#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \
+     ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT)
+
+#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \
+     vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_data_t f;
+} vgt_debug_data_u;
+
+
+/*
+ * VGT_CNTL_STATUS struct
+ */
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SIZE  1
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8
+
+#define VGT_CNTL_STATUS_VGT_BUSY_MASK  0x00000001
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100
+
+#define VGT_CNTL_STATUS_MASK \
+     (VGT_CNTL_STATUS_VGT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK)
+
+#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \
+     ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \
+      (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \
+      (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \
+      (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \
+      (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \
+      (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \
+      (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \
+      (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \
+      (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT))
+
+#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int                                : 23;
+     } vgt_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int                                : 23;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+     } vgt_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_cntl_status_t f;
+} vgt_cntl_status_u;
+
+
+/*
+ * VGT_DEBUG_REG0 struct
+ */
+
+#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_out_busy_SIZE   1
+#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1
+#define VGT_DEBUG_REG0_grp_busy_SIZE   1
+#define VGT_DEBUG_REG0_dma_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_rbiu_busy_SIZE  1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1
+
+#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0
+#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2
+#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3
+#define VGT_DEBUG_REG0_out_busy_SHIFT  4
+#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5
+#define VGT_DEBUG_REG0_grp_busy_SHIFT  6
+#define VGT_DEBUG_REG0_dma_busy_SHIFT  7
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8
+#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11
+#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12
+#define VGT_DEBUG_REG0_vgt_busy_SHIFT  13
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16
+
+#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001
+#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002
+#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004
+#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008
+#define VGT_DEBUG_REG0_out_busy_MASK   0x00000010
+#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020
+#define VGT_DEBUG_REG0_grp_busy_MASK   0x00000040
+#define VGT_DEBUG_REG0_dma_busy_MASK   0x00000080
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100
+#define VGT_DEBUG_REG0_rbiu_busy_MASK  0x00000200
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800
+#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000
+#define VGT_DEBUG_REG0_vgt_busy_MASK   0x00002000
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000
+
+#define VGT_DEBUG_REG0_MASK \
+     (VGT_DEBUG_REG0_te_grp_busy_MASK | \
+      VGT_DEBUG_REG0_pt_grp_busy_MASK | \
+      VGT_DEBUG_REG0_vr_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_out_busy_MASK | \
+      VGT_DEBUG_REG0_grp_backend_busy_MASK | \
+      VGT_DEBUG_REG0_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_MASK | \
+      VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_busy_MASK)
+
+#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \
+     ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \
+      (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \
+      (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \
+      (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \
+      (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \
+      (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \
+      (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \
+      (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \
+      (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \
+      (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \
+      (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \
+      (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \
+      (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \
+      (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \
+      (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \
+      (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \
+      (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT))
+
+#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int                                : 15;
+     } vgt_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int                                : 15;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+     } vgt_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg0_t f;
+} vgt_debug_reg0_u;
+
+
+/*
+ * VGT_DEBUG_REG1 struct
+ */
+
+#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1
+#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_te_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1
+#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1
+#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1
+#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1
+
+#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0
+#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3
+#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5
+#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7
+#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9
+#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10
+#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11
+#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12
+#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13
+#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14
+#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15
+#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16
+#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20
+#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28
+#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30
+
+#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001
+#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002
+#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004
+#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008
+#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010
+#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020
+#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040
+#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080
+#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100
+#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200
+#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400
+#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800
+#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000
+#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000
+#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000
+#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000
+#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000
+#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000
+#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000
+#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000
+
+#define VGT_DEBUG_REG1_MASK \
+     (VGT_DEBUG_REG1_out_te_data_read_MASK | \
+      VGT_DEBUG_REG1_te_out_data_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_prim_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_data_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_prim_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_indx_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_te_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_te_valid_MASK | \
+      VGT_DEBUG_REG1_pt_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_pt_valid_MASK | \
+      VGT_DEBUG_REG1_vr_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_vr_valid_MASK | \
+      VGT_DEBUG_REG1_grp_dma_read_MASK | \
+      VGT_DEBUG_REG1_dma_grp_valid_MASK | \
+      VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \
+      VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \
+      VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_MH_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \
+      VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_SQ_send_MASK | \
+      VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK)
+
+#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \
+     ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \
+      (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \
+      (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \
+      (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \
+      (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \
+      (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \
+      (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \
+      (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \
+      (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \
+      (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \
+      (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \
+      (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \
+      (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \
+      (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \
+      (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \
+      (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \
+      (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \
+      (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \
+      (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \
+      (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \
+      (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \
+      (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \
+      (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \
+      (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \
+      (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \
+      (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \
+      (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \
+      (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \
+      (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \
+      (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \
+      (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT))
+
+#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int                                : 1;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+     } vgt_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg1_t f;
+} vgt_debug_reg1_u;
+
+
+/*
+ * VGT_DEBUG_REG3 struct
+ */
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002
+
+#define VGT_DEBUG_REG3_MASK \
+     (VGT_DEBUG_REG3_vgt_clk_en_MASK | \
+      VGT_DEBUG_REG3_reg_fifos_clk_en_MASK)
+
+#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \
+     ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \
+      (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT))
+
+#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int                                : 30;
+     } vgt_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int                                : 30;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+     } vgt_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg3_t f;
+} vgt_debug_reg3_u;
+
+
+/*
+ * VGT_DEBUG_REG6 struct
+ */
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG6_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_extract_vector_SIZE 1
+#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG6_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG6_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG6_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG6_MASK \
+     (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG6_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG6_input_data_valid_MASK | \
+      VGT_DEBUG_REG6_input_data_xfer_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG6_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG6_shifter_first_load_MASK | \
+      VGT_DEBUG_REG6_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG6_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG6_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG6_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG6_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG6_extract_vector_MASK | \
+      VGT_DEBUG_REG6_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG6_destination_rtr_MASK | \
+      VGT_DEBUG_REG6_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int                                : 3;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg6_t f;
+} vgt_debug_reg6_u;
+
+
+/*
+ * VGT_DEBUG_REG7 struct
+ */
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG7_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG7_MASK \
+     (VGT_DEBUG_REG7_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG7_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG7_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG7_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+     } vgt_debug_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+     } vgt_debug_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg7_t f;
+} vgt_debug_reg7_u;
+
+
+/*
+ * VGT_DEBUG_REG8 struct
+ */
+
+#define VGT_DEBUG_REG8_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG8_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG8_MASK \
+     (VGT_DEBUG_REG8_current_source_sel_MASK | \
+      VGT_DEBUG_REG8_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG8_input_data_cnt_MASK | \
+      VGT_DEBUG_REG8_input_data_lsw_MASK | \
+      VGT_DEBUG_REG8_input_data_msw_MASK | \
+      VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+     } vgt_debug_reg8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg8_t f;
+} vgt_debug_reg8_u;
+
+
+/*
+ * VGT_DEBUG_REG9 struct
+ */
+
+#define VGT_DEBUG_REG9_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG9_MASK \
+     (VGT_DEBUG_REG9_next_stride_q_MASK | \
+      VGT_DEBUG_REG9_next_stride_d_MASK | \
+      VGT_DEBUG_REG9_current_shift_q_MASK | \
+      VGT_DEBUG_REG9_current_shift_d_MASK | \
+      VGT_DEBUG_REG9_current_stride_q_MASK | \
+      VGT_DEBUG_REG9_current_stride_d_MASK | \
+      VGT_DEBUG_REG9_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int                                : 1;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+     } vgt_debug_reg9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg9_t f;
+} vgt_debug_reg9_u;
+
+
+/*
+ * VGT_DEBUG_REG10 struct
+ */
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG10_bin_valid_SIZE 1
+#define VGT_DEBUG_REG10_read_block_SIZE 1
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1
+#define VGT_DEBUG_REG10_selected_data_SIZE 8
+#define VGT_DEBUG_REG10_mask_input_data_SIZE 8
+#define VGT_DEBUG_REG10_gap_q_SIZE     1
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1
+#define VGT_DEBUG_REG10_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3
+#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4
+#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5
+#define VGT_DEBUG_REG10_bin_valid_SHIFT 6
+#define VGT_DEBUG_REG10_read_block_SHIFT 7
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8
+#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10
+#define VGT_DEBUG_REG10_selected_data_SHIFT 11
+#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19
+#define VGT_DEBUG_REG10_gap_q_SHIFT    27
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30
+#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008
+#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010
+#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020
+#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040
+#define VGT_DEBUG_REG10_read_block_MASK 0x00000080
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100
+#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200
+#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400
+#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800
+#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000
+#define VGT_DEBUG_REG10_gap_q_MASK     0x08000000
+#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000
+#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000
+#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000
+#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG10_MASK \
+     (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG10_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG10_bin_valid_MASK | \
+      VGT_DEBUG_REG10_read_block_MASK | \
+      VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \
+      VGT_DEBUG_REG10_last_bit_enable_q_MASK | \
+      VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \
+      VGT_DEBUG_REG10_selected_data_MASK | \
+      VGT_DEBUG_REG10_mask_input_data_MASK | \
+      VGT_DEBUG_REG10_gap_q_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \
+      VGT_DEBUG_REG10_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \
+     ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \
+      (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \
+      (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \
+      (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \
+      (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \
+      (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \
+      (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \
+      (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \
+      (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \
+      (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \
+      (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \
+      (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \
+      (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \
+      (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \
+      (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+     } vgt_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+     } vgt_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg10_t f;
+} vgt_debug_reg10_u;
+
+
+/*
+ * VGT_DEBUG_REG12 struct
+ */
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG12_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_extract_vector_SIZE 1
+#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG12_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG12_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG12_MASK \
+     (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG12_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG12_input_data_valid_MASK | \
+      VGT_DEBUG_REG12_input_data_xfer_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG12_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG12_shifter_first_load_MASK | \
+      VGT_DEBUG_REG12_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG12_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG12_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG12_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG12_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG12_extract_vector_MASK | \
+      VGT_DEBUG_REG12_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG12_destination_rtr_MASK | \
+      VGT_DEBUG_REG12_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int                                : 3;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg12_t f;
+} vgt_debug_reg12_u;
+
+
+/*
+ * VGT_DEBUG_REG13 struct
+ */
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG13_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG13_MASK \
+     (VGT_DEBUG_REG13_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG13_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG13_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG13_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+     } vgt_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+     } vgt_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg13_t f;
+} vgt_debug_reg13_u;
+
+
+/*
+ * VGT_DEBUG_REG14 struct
+ */
+
+#define VGT_DEBUG_REG14_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG14_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG14_MASK \
+     (VGT_DEBUG_REG14_current_source_sel_MASK | \
+      VGT_DEBUG_REG14_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG14_input_data_cnt_MASK | \
+      VGT_DEBUG_REG14_input_data_lsw_MASK | \
+      VGT_DEBUG_REG14_input_data_msw_MASK | \
+      VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+     } vgt_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg14_t f;
+} vgt_debug_reg14_u;
+
+
+/*
+ * VGT_DEBUG_REG15 struct
+ */
+
+#define VGT_DEBUG_REG15_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG15_MASK \
+     (VGT_DEBUG_REG15_next_stride_q_MASK | \
+      VGT_DEBUG_REG15_next_stride_d_MASK | \
+      VGT_DEBUG_REG15_current_shift_q_MASK | \
+      VGT_DEBUG_REG15_current_shift_d_MASK | \
+      VGT_DEBUG_REG15_current_stride_q_MASK | \
+      VGT_DEBUG_REG15_current_stride_d_MASK | \
+      VGT_DEBUG_REG15_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int                                : 1;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+     } vgt_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg15_t f;
+} vgt_debug_reg15_u;
+
+
+/*
+ * VGT_DEBUG_REG16 struct
+ */
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1
+#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1
+#define VGT_DEBUG_REG16_current_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_en_SIZE 1
+#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1
+#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9
+#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10
+#define VGT_DEBUG_REG16_current_state_q_SHIFT 11
+#define VGT_DEBUG_REG16_old_state_q_SHIFT 12
+#define VGT_DEBUG_REG16_old_state_en_SHIFT 13
+#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15
+#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17
+#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30
+#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200
+#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400
+#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800
+#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000
+#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000
+#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000
+#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000
+#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000
+#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000
+#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000
+#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG16_MASK \
+     (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \
+      VGT_DEBUG_REG16_rst_last_bit_MASK | \
+      VGT_DEBUG_REG16_current_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_en_MASK | \
+      VGT_DEBUG_REG16_prev_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_last_bit_block_q_MASK | \
+      VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \
+      VGT_DEBUG_REG16_load_empty_reg_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \
+      VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \
+     ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \
+      (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \
+      (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \
+      (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \
+      (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \
+      (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \
+      (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \
+      (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \
+      (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \
+      (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \
+      (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \
+      (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \
+      (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \
+      (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \
+      (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \
+      (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \
+      (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \
+      (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \
+      (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \
+      (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \
+      (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+     } vgt_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+     } vgt_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg16_t f;
+} vgt_debug_reg16_u;
+
+
+/*
+ * VGT_DEBUG_REG17 struct
+ */
+
+#define VGT_DEBUG_REG17_save_read_q_SIZE 1
+#define VGT_DEBUG_REG17_extend_read_q_SIZE 1
+#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2
+#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1
+#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1
+#define VGT_DEBUG_REG17_check_second_reg_SIZE 1
+#define VGT_DEBUG_REG17_check_first_reg_SIZE 1
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1
+#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG17_save_read_q_SHIFT 0
+#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1
+#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2
+#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4
+#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5
+#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6
+#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7
+#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8
+#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14
+#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15
+#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24
+#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001
+#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002
+#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c
+#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010
+#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020
+#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040
+#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080
+#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100
+#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000
+#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000
+#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000
+#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000
+#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000
+#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG17_MASK \
+     (VGT_DEBUG_REG17_save_read_q_MASK | \
+      VGT_DEBUG_REG17_extend_read_q_MASK | \
+      VGT_DEBUG_REG17_grp_indx_size_MASK | \
+      VGT_DEBUG_REG17_cull_prim_true_MASK | \
+      VGT_DEBUG_REG17_reset_bit2_q_MASK | \
+      VGT_DEBUG_REG17_reset_bit1_q_MASK | \
+      VGT_DEBUG_REG17_first_reg_first_q_MASK | \
+      VGT_DEBUG_REG17_check_second_reg_MASK | \
+      VGT_DEBUG_REG17_check_first_reg_MASK | \
+      VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \
+      VGT_DEBUG_REG17_to_second_reg_q_MASK | \
+      VGT_DEBUG_REG17_roll_over_msk_q_MASK | \
+      VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \
+     ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \
+      (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \
+      (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \
+      (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \
+      (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \
+      (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \
+      (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \
+      (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \
+      (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \
+      (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \
+      (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \
+      (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \
+      (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \
+      (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \
+      (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \
+      (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \
+      (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \
+      (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+     } vgt_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+     } vgt_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg17_t f;
+} vgt_debug_reg17_u;
+
+
+/*
+ * VGT_DEBUG_REG18 struct
+ */
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_start_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1
+#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13
+#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15
+#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16
+#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17
+#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20
+#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21
+#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22
+#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23
+#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24
+#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26
+#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27
+#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28
+#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000
+#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000
+#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000
+#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000
+#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000
+#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000
+#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000
+#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000
+#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000
+#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000
+#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000
+#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000
+#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000
+#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000
+
+#define VGT_DEBUG_REG18_MASK \
+     (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG18_dma_mem_full_MASK | \
+      VGT_DEBUG_REG18_dma_ram_re_MASK | \
+      VGT_DEBUG_REG18_dma_ram_we_MASK | \
+      VGT_DEBUG_REG18_dma_mem_empty_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \
+      VGT_DEBUG_REG18_bin_mem_full_MASK | \
+      VGT_DEBUG_REG18_bin_ram_we_MASK | \
+      VGT_DEBUG_REG18_bin_ram_re_MASK | \
+      VGT_DEBUG_REG18_bin_mem_empty_MASK | \
+      VGT_DEBUG_REG18_start_bin_req_MASK | \
+      VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \
+      VGT_DEBUG_REG18_dma_req_xfer_MASK | \
+      VGT_DEBUG_REG18_have_valid_bin_req_MASK | \
+      VGT_DEBUG_REG18_have_valid_dma_req_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK)
+
+#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \
+     ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \
+      (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \
+      (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \
+      (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \
+      (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \
+      (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \
+      (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \
+      (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \
+      (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \
+      (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \
+      (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \
+      (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \
+      (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \
+      (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \
+      (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \
+      (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \
+      (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \
+      (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \
+      (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT))
+
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+     } vgt_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+     } vgt_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg18_t f;
+} vgt_debug_reg18_u;
+
+
+/*
+ * VGT_DEBUG_REG20 struct
+ */
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_sent_cnt_SIZE  4
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5
+#define VGT_DEBUG_REG20_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5
+#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6
+#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7
+#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8
+#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9
+#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10
+#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11
+#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12
+#define VGT_DEBUG_REG20_hold_prim_SHIFT 13
+#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21
+#define VGT_DEBUG_REG20_out_trigger_SHIFT 26
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004
+#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020
+#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040
+#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080
+#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100
+#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200
+#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400
+#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800
+#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000
+#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000
+#define VGT_DEBUG_REG20_sent_cnt_MASK  0x0003c000
+#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000
+#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000
+#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000
+
+#define VGT_DEBUG_REG20_MASK \
+     (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_re_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_we_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_full_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_re_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_we_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_full_MASK | \
+      VGT_DEBUG_REG20_hold_prim_MASK | \
+      VGT_DEBUG_REG20_sent_cnt_MASK | \
+      VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \
+      VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \
+      VGT_DEBUG_REG20_out_trigger_MASK)
+
+#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \
+     ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \
+      (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \
+      (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \
+      (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \
+      (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \
+      (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \
+      (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \
+      (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \
+      (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \
+      (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \
+      (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \
+      (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \
+      (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \
+      (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \
+      (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \
+      (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \
+      (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \
+      (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \
+      (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int                                : 5;
+     } vgt_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int                                : 5;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+     } vgt_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg20_t f;
+} vgt_debug_reg20_u;
+
+
+/*
+ * VGT_DEBUG_REG21 struct
+ */
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3
+#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4
+#define VGT_DEBUG_REG21_new_packet_q_SIZE 1
+#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1
+#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1
+#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1
+#define VGT_DEBUG_REG21_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1
+#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14
+#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18
+#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22
+#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25
+#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26
+#define VGT_DEBUG_REG21_out_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e
+#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380
+#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000
+#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000
+#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000
+#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000
+#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000
+#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000
+#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG21_MASK \
+     (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \
+      VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \
+      VGT_DEBUG_REG21_alloc_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \
+      VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \
+      VGT_DEBUG_REG21_new_packet_q_MASK | \
+      VGT_DEBUG_REG21_new_allocate_q_MASK | \
+      VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \
+      VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \
+      VGT_DEBUG_REG21_insert_null_prim_MASK | \
+      VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \
+      VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \
+      VGT_DEBUG_REG21_buffered_thread_size_MASK | \
+      VGT_DEBUG_REG21_out_trigger_MASK)
+
+#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \
+     ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \
+      (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \
+      (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \
+      (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \
+      (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \
+      (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \
+      (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \
+      (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \
+      (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \
+      (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \
+      (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \
+      (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \
+      (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \
+      (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int                                : 4;
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+     } vgt_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+          unsigned int                                : 4;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+     } vgt_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg21_t f;
+} vgt_debug_reg21_u;
+
+
+/*
+ * VGT_CRC_SQ_DATA struct
+ */
+
+#define VGT_CRC_SQ_DATA_CRC_SIZE       32
+
+#define VGT_CRC_SQ_DATA_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_DATA_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_DATA_MASK \
+     (VGT_CRC_SQ_DATA_CRC_MASK)
+
+#define VGT_CRC_SQ_DATA(crc) \
+     ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT))
+
+#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \
+     ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \
+     vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_data_t f;
+} vgt_crc_sq_data_u;
+
+
+/*
+ * VGT_CRC_SQ_CTRL struct
+ */
+
+#define VGT_CRC_SQ_CTRL_CRC_SIZE       32
+
+#define VGT_CRC_SQ_CTRL_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_CTRL_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_CTRL_MASK \
+     (VGT_CRC_SQ_CTRL_CRC_MASK)
+
+#define VGT_CRC_SQ_CTRL(crc) \
+     ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT))
+
+#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \
+     ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \
+     vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_ctrl_t f;
+} vgt_crc_sq_ctrl_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER0_SELECT_MASK \
+     (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \
+     ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \
+     vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_select_t f;
+} vgt_perfcounter0_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER1_SELECT_MASK \
+     (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \
+     ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \
+     vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_select_t f;
+} vgt_perfcounter1_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER2_SELECT_MASK \
+     (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \
+     ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \
+     vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_select_t f;
+} vgt_perfcounter2_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER3_SELECT_MASK \
+     (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \
+     ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \
+     vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_select_t f;
+} vgt_perfcounter3_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_LOW struct
+ */
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER0_LOW_MASK \
+     (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \
+     ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \
+     vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_low_t f;
+} vgt_perfcounter0_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_LOW struct
+ */
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER1_LOW_MASK \
+     (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \
+     ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \
+     vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_low_t f;
+} vgt_perfcounter1_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_LOW struct
+ */
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER2_LOW_MASK \
+     (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \
+     ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \
+     vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_low_t f;
+} vgt_perfcounter2_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_LOW struct
+ */
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER3_LOW_MASK \
+     (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \
+     ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \
+     vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_low_t f;
+} vgt_perfcounter3_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_HI struct
+ */
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER0_HI_MASK \
+     (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \
+     ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \
+     vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_hi_t f;
+} vgt_perfcounter0_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_HI struct
+ */
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER1_HI_MASK \
+     (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \
+     ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \
+     vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_hi_t f;
+} vgt_perfcounter1_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_HI struct
+ */
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER2_HI_MASK \
+     (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \
+     ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \
+     vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_hi_t f;
+} vgt_perfcounter2_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_HI struct
+ */
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER3_HI_MASK \
+     (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \
+     ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \
+     vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_hi_t f;
+} vgt_perfcounter3_hi_u;
+
+
+#endif
+
+
+#if !defined (_SQ_FIDDLE_H)
+#define _SQ_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sq_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * SQ_GPR_MANAGEMENT struct
+ */
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000
+
+#define SQ_GPR_MANAGEMENT_MASK \
+     (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK)
+
+#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \
+     ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \
+      (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \
+      (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT))
+
+#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 13;
+     } sq_gpr_management_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int                                : 13;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+     } sq_gpr_management_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_gpr_management_t f;
+} sq_gpr_management_u;
+
+
+/*
+ * SQ_FLOW_CONTROL struct
+ */
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1
+#define SQ_FLOW_CONTROL_ONE_ALU_SIZE   1
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4
+#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE  1
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0
+#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4
+#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT  8
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12
+#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003
+#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010
+#define SQ_FLOW_CONTROL_ONE_ALU_MASK   0x00000100
+#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000
+#define SQ_FLOW_CONTROL_NO_PV_PS_MASK  0x00010000
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000
+
+#define SQ_FLOW_CONTROL_MASK \
+     (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ONE_THREAD_MASK | \
+      SQ_FLOW_CONTROL_ONE_ALU_MASK | \
+      SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \
+      SQ_FLOW_CONTROL_NO_PV_PS_MASK | \
+      SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \
+      SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \
+      SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \
+      SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \
+      SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \
+      SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \
+      SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK)
+
+#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \
+     ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \
+      (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \
+      (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \
+      (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \
+      (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \
+      (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \
+      (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \
+      (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \
+      (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \
+      (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \
+      (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \
+      (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \
+      (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \
+      (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \
+      (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT))
+
+#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+          unsigned int                                : 2;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int                                : 4;
+     } sq_flow_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int                                : 4;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 2;
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+     } sq_flow_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_flow_control_t f;
+} sq_flow_control_u;
+
+
+/*
+ * SQ_INST_STORE_MANAGMENT struct
+ */
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000
+
+#define SQ_INST_STORE_MANAGMENT_MASK \
+     (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \
+      SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK)
+
+#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \
+     ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \
+      (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT))
+
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+     } sq_inst_store_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+     } sq_inst_store_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_inst_store_managment_t f;
+} sq_inst_store_managment_u;
+
+
+/*
+ * SQ_RESOURCE_MANAGMENT struct
+ */
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000
+
+#define SQ_RESOURCE_MANAGMENT_MASK \
+     (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK)
+
+#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \
+     ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT))
+
+#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int                                : 7;
+     } sq_resource_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int                                : 7;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+     } sq_resource_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_resource_managment_t f;
+} sq_resource_managment_u;
+
+
+/*
+ * SQ_EO_RT struct
+ */
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE  8
+#define SQ_EO_RT_EO_TSTATE_RT_SIZE     8
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0
+#define SQ_EO_RT_EO_TSTATE_RT_SHIFT    16
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_MASK  0x000000ff
+#define SQ_EO_RT_EO_TSTATE_RT_MASK     0x00ff0000
+
+#define SQ_EO_RT_MASK \
+     (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \
+      SQ_EO_RT_EO_TSTATE_RT_MASK)
+
+#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \
+     ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \
+      (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT))
+
+#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+     } sq_eo_rt_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+     } sq_eo_rt_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_eo_rt_t f;
+} sq_eo_rt_u;
+
+
+/*
+ * SQ_DEBUG_MISC struct
+ */
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8
+#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1
+#define SQ_DEBUG_MISC_RESERVED_SIZE    2
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12
+#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20
+#define SQ_DEBUG_MISC_RESERVED_SHIFT   21
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000
+#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000
+#define SQ_DEBUG_MISC_RESERVED_MASK    0x00600000
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000
+
+#define SQ_DEBUG_MISC_MASK \
+     (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_READ_CTX_MASK | \
+      SQ_DEBUG_MISC_RESERVED_MASK | \
+      SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK)
+
+#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \
+     ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \
+      (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \
+      (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \
+      (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \
+      (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \
+      (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \
+      (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \
+      (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \
+      (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT))
+
+#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int                                : 3;
+     } sq_debug_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int                                : 3;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+     } sq_debug_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_t f;
+} sq_debug_misc_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_CNTL struct
+ */
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000
+#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000
+
+#define SQ_ACTIVITY_METER_CNTL_MASK \
+     (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \
+      SQ_ACTIVITY_METER_CNTL_SPARE_MASK)
+
+#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \
+     ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \
+      (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \
+      (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \
+      (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT))
+
+#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_cntl_t f;
+} sq_activity_meter_cntl_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_STATUS struct
+ */
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff
+
+#define SQ_ACTIVITY_METER_STATUS_MASK \
+     (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK)
+
+#define SQ_ACTIVITY_METER_STATUS(percent_busy) \
+     ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT))
+
+#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \
+     ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \
+     sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+          unsigned int                                : 24;
+     } sq_activity_meter_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int                                : 24;
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+     } sq_activity_meter_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_status_t f;
+} sq_activity_meter_status_u;
+
+
+/*
+ * SQ_INPUT_ARB_PRIORITY struct
+ */
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+
+#define SQ_INPUT_ARB_PRIORITY_MASK \
+     (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK)
+
+#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \
+     ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT))
+
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int                                : 14;
+     } sq_input_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int                                : 14;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_input_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_input_arb_priority_t f;
+} sq_input_arb_priority_u;
+
+
+/*
+ * SQ_THREAD_ARB_PRIORITY struct
+ */
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000
+
+#define SQ_THREAD_ARB_PRIORITY_MASK \
+     (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \
+      SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \
+      SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK)
+
+#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \
+     ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \
+      (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \
+      (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \
+      (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \
+      (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT))
+
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int                                : 9;
+     } sq_thread_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int                                : 9;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_thread_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_thread_arb_priority_t f;
+} sq_thread_arb_priority_u;
+
+
+/*
+ * SQ_VS_WATCHDOG_TIMER struct
+ */
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE 1
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT 0
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe
+
+#define SQ_VS_WATCHDOG_TIMER_MASK \
+     (SQ_VS_WATCHDOG_TIMER_ENABLE_MASK | \
+      SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK)
+
+#define SQ_VS_WATCHDOG_TIMER(enable, timeout_count) \
+     ((enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) | \
+      (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT))
+
+#define SQ_VS_WATCHDOG_TIMER_GET_ENABLE(sq_vs_watchdog_timer) \
+     ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_VS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_vs_watchdog_timer) \
+     ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#define SQ_VS_WATCHDOG_TIMER_SET_ENABLE(sq_vs_watchdog_timer_reg, enable) \
+     sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_VS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_vs_watchdog_timer_reg, timeout_count) \
+     sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_watchdog_timer_t {
+          unsigned int enable                         : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE;
+          unsigned int timeout_count                  : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+     } sq_vs_watchdog_timer_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_watchdog_timer_t {
+          unsigned int timeout_count                  : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+          unsigned int enable                         : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE;
+     } sq_vs_watchdog_timer_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_watchdog_timer_t f;
+} sq_vs_watchdog_timer_u;
+
+
+/*
+ * SQ_PS_WATCHDOG_TIMER struct
+ */
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE 1
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT 0
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe
+
+#define SQ_PS_WATCHDOG_TIMER_MASK \
+     (SQ_PS_WATCHDOG_TIMER_ENABLE_MASK | \
+      SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK)
+
+#define SQ_PS_WATCHDOG_TIMER(enable, timeout_count) \
+     ((enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) | \
+      (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT))
+
+#define SQ_PS_WATCHDOG_TIMER_GET_ENABLE(sq_ps_watchdog_timer) \
+     ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_PS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_ps_watchdog_timer) \
+     ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#define SQ_PS_WATCHDOG_TIMER_SET_ENABLE(sq_ps_watchdog_timer_reg, enable) \
+     sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_PS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_ps_watchdog_timer_reg, timeout_count) \
+     sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_watchdog_timer_t {
+          unsigned int enable                         : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE;
+          unsigned int timeout_count                  : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+     } sq_ps_watchdog_timer_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_watchdog_timer_t {
+          unsigned int timeout_count                  : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+          unsigned int enable                         : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE;
+     } sq_ps_watchdog_timer_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_watchdog_timer_t f;
+} sq_ps_watchdog_timer_u;
+
+
+/*
+ * SQ_INT_CNTL struct
+ */
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE 1
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE 1
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT 0
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT 1
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK 0x00000001
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK 0x00000002
+
+#define SQ_INT_CNTL_MASK \
+     (SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK | \
+      SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK)
+
+#define SQ_INT_CNTL(ps_watchdog_mask, vs_watchdog_mask) \
+     ((ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) | \
+      (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT))
+
+#define SQ_INT_CNTL_GET_PS_WATCHDOG_MASK(sq_int_cntl) \
+     ((sq_int_cntl & SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT)
+#define SQ_INT_CNTL_GET_VS_WATCHDOG_MASK(sq_int_cntl) \
+     ((sq_int_cntl & SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)
+
+#define SQ_INT_CNTL_SET_PS_WATCHDOG_MASK(sq_int_cntl_reg, ps_watchdog_mask) \
+     sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) | (ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT)
+#define SQ_INT_CNTL_SET_VS_WATCHDOG_MASK(sq_int_cntl_reg, vs_watchdog_mask) \
+     sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) | (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_cntl_t {
+          unsigned int ps_watchdog_mask               : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE;
+          unsigned int vs_watchdog_mask               : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE;
+          unsigned int                                : 30;
+     } sq_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_cntl_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_mask               : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE;
+          unsigned int ps_watchdog_mask               : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE;
+     } sq_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_cntl_t f;
+} sq_int_cntl_u;
+
+
+/*
+ * SQ_INT_STATUS struct
+ */
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE 1
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE 1
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT 0
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT 1
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK 0x00000001
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK 0x00000002
+
+#define SQ_INT_STATUS_MASK \
+     (SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK | \
+      SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK)
+
+#define SQ_INT_STATUS(ps_watchdog_timeout, vs_watchdog_timeout) \
+     ((ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) | \
+      (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT))
+
+#define SQ_INT_STATUS_GET_PS_WATCHDOG_TIMEOUT(sq_int_status) \
+     ((sq_int_status & SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT)
+#define SQ_INT_STATUS_GET_VS_WATCHDOG_TIMEOUT(sq_int_status) \
+     ((sq_int_status & SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)
+
+#define SQ_INT_STATUS_SET_PS_WATCHDOG_TIMEOUT(sq_int_status_reg, ps_watchdog_timeout) \
+     sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) | (ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT)
+#define SQ_INT_STATUS_SET_VS_WATCHDOG_TIMEOUT(sq_int_status_reg, vs_watchdog_timeout) \
+     sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) | (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_status_t {
+          unsigned int ps_watchdog_timeout            : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int vs_watchdog_timeout            : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int                                : 30;
+     } sq_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_status_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_timeout            : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int ps_watchdog_timeout            : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE;
+     } sq_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_status_t f;
+} sq_int_status_u;
+
+
+/*
+ * SQ_INT_ACK struct
+ */
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE 1
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE 1
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT 0
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT 1
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_MASK 0x00000001
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_MASK 0x00000002
+
+#define SQ_INT_ACK_MASK \
+     (SQ_INT_ACK_PS_WATCHDOG_ACK_MASK | \
+      SQ_INT_ACK_VS_WATCHDOG_ACK_MASK)
+
+#define SQ_INT_ACK(ps_watchdog_ack, vs_watchdog_ack) \
+     ((ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) | \
+      (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT))
+
+#define SQ_INT_ACK_GET_PS_WATCHDOG_ACK(sq_int_ack) \
+     ((sq_int_ack & SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT)
+#define SQ_INT_ACK_GET_VS_WATCHDOG_ACK(sq_int_ack) \
+     ((sq_int_ack & SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)
+
+#define SQ_INT_ACK_SET_PS_WATCHDOG_ACK(sq_int_ack_reg, ps_watchdog_ack) \
+     sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) | (ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT)
+#define SQ_INT_ACK_SET_VS_WATCHDOG_ACK(sq_int_ack_reg, vs_watchdog_ack) \
+     sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) | (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_ack_t {
+          unsigned int ps_watchdog_ack                : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE;
+          unsigned int vs_watchdog_ack                : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE;
+          unsigned int                                : 30;
+     } sq_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_ack_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_ack                : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE;
+          unsigned int ps_watchdog_ack                : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE;
+     } sq_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_ack_t f;
+} sq_int_ack_u;
+
+
+/*
+ * SQ_DEBUG_INPUT_FSM struct
+ */
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE  3
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007
+#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK  0x00007000
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000
+
+#define SQ_DEBUG_INPUT_FSM_MASK \
+     (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \
+      SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK)
+
+#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \
+     ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \
+      (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \
+      (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \
+      (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \
+      (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \
+      (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \
+      (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \
+      (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT))
+
+#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_input_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int                                : 4;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+     } sq_debug_input_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_input_fsm_t f;
+} sq_debug_input_fsm_u;
+
+
+/*
+ * SQ_DEBUG_CONST_MGR_FSM struct
+ */
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000
+
+#define SQ_DEBUG_CONST_MGR_FSM_MASK \
+     (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK)
+
+#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \
+     ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \
+      (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \
+      (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \
+      (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \
+      (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \
+      (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \
+      (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \
+      (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \
+      (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \
+      (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT))
+
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int                                : 8;
+     } sq_debug_const_mgr_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int                                : 8;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+     } sq_debug_const_mgr_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_const_mgr_fsm_t f;
+} sq_debug_const_mgr_fsm_u;
+
+
+/*
+ * SQ_DEBUG_TP_FSM struct
+ */
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1
+#define SQ_DEBUG_TP_FSM_CF_TP_SIZE     4
+#define SQ_DEBUG_TP_FSM_IF_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2
+#define SQ_DEBUG_TP_FSM_GS_TP_SIZE     2
+#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT    0
+#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3
+#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT    4
+#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT    8
+#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT   12
+#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14
+#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT    16
+#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18
+#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT   20
+#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22
+#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT   24
+#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28
+
+#define SQ_DEBUG_TP_FSM_EX_TP_MASK     0x00000007
+#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_TP_FSM_CF_TP_MASK     0x000000f0
+#define SQ_DEBUG_TP_FSM_IF_TP_MASK     0x00000700
+#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_TP_FSM_TIS_TP_MASK    0x00003000
+#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000
+#define SQ_DEBUG_TP_FSM_GS_TP_MASK     0x00030000
+#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000
+#define SQ_DEBUG_TP_FSM_FCR_TP_MASK    0x00300000
+#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000
+#define SQ_DEBUG_TP_FSM_FCS_TP_MASK    0x03000000
+#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000
+
+#define SQ_DEBUG_TP_FSM_MASK \
+     (SQ_DEBUG_TP_FSM_EX_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED0_MASK | \
+      SQ_DEBUG_TP_FSM_CF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_IF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_TP_FSM_TIS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_TP_FSM_GS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED3_MASK | \
+      SQ_DEBUG_TP_FSM_FCR_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED4_MASK | \
+      SQ_DEBUG_TP_FSM_FCS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED5_MASK | \
+      SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK)
+
+#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \
+     ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \
+      (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \
+      (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \
+      (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \
+      (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \
+      (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \
+      (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \
+      (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \
+      (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \
+      (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \
+      (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \
+      (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \
+      (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \
+      (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT))
+
+#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_tp_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+     } sq_debug_tp_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tp_fsm_t f;
+} sq_debug_tp_fsm_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_0 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_0_MASK \
+     (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_0_t f;
+} sq_debug_fsm_alu_0_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_1 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_1_MASK \
+     (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_1_t f;
+} sq_debug_fsm_alu_1_u;
+
+
+/*
+ * SQ_DEBUG_EXP_ALLOC struct
+ */
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000
+
+#define SQ_DEBUG_EXP_ALLOC_MASK \
+     (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \
+      SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK)
+
+#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \
+     ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \
+      (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \
+      (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \
+      (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \
+      (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT))
+
+#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_exp_alloc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int                                : 10;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+     } sq_debug_exp_alloc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_exp_alloc_t f;
+} sq_debug_exp_alloc_u;
+
+
+/*
+ * SQ_DEBUG_PTR_BUFF struct
+ */
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000
+
+#define SQ_DEBUG_PTR_BUFF_MASK \
+     (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \
+      SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \
+      SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \
+      SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \
+      SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \
+      SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK)
+
+#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \
+     ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \
+      (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \
+      (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \
+      (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \
+      (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \
+      (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \
+      (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \
+      (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \
+      (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT))
+
+#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_ptr_buff_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int                                : 4;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+     } sq_debug_ptr_buff_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_ptr_buff_t f;
+} sq_debug_ptr_buff_u;
+
+
+/*
+ * SQ_DEBUG_GPR_VTX struct
+ */
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_VTX_MASK \
+     (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \
+     ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \
+      (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \
+      (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \
+      (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_vtx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int                                : 1;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_vtx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_vtx_t f;
+} sq_debug_gpr_vtx_u;
+
+
+/*
+ * SQ_DEBUG_GPR_PIX struct
+ */
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_PIX_MASK \
+     (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \
+     ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \
+      (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \
+      (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \
+      (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_pix_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int                                : 1;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_pix_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_pix_t f;
+} sq_debug_gpr_pix_u;
+
+
+/*
+ * SQ_DEBUG_TB_STATUS_SEL struct
+ */
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000
+
+#define SQ_DEBUG_TB_STATUS_SEL_MASK \
+     (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK)
+
+#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \
+     ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \
+      (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \
+      (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \
+      (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \
+      (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT))
+
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tb_status_sel_t f;
+} sq_debug_tb_status_sel_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_0 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE  1
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK  0x00200000
+
+#define SQ_DEBUG_VTX_TB_0_MASK \
+     (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \
+      SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK)
+
+#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \
+     ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \
+      (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \
+      (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \
+      (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \
+      (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \
+      (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \
+      (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_vtx_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int                                : 10;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+     } sq_debug_vtx_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_0_t f;
+} sq_debug_vtx_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_1 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff
+
+#define SQ_DEBUG_VTX_TB_1_MASK \
+     (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK)
+
+#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \
+     ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \
+     ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \
+     sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+          unsigned int                                : 16;
+     } sq_debug_vtx_tb_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int                                : 16;
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+     } sq_debug_vtx_tb_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_1_t f;
+} sq_debug_vtx_tb_1_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATUS_REG struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \
+     (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \
+     ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \
+     ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \
+     sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_status_reg_t f;
+} sq_debug_vtx_tb_status_reg_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \
+     ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \
+     ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \
+     sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_state_mem_t f;
+} sq_debug_vtx_tb_state_mem_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE    1
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25
+#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT   31
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000
+#define SQ_DEBUG_PIX_TB_0_BUSY_MASK    0x80000000
+
+#define SQ_DEBUG_PIX_TB_0_MASK \
+     (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_BUSY_MASK)
+
+#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \
+     ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \
+      (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \
+      (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \
+      (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \
+      (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \
+      (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_0_t f;
+} sq_debug_pix_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \
+     ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \
+     ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \
+     sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_0_t f;
+} sq_debug_pix_tb_status_reg_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \
+     ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \
+     ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \
+     sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_1_t f;
+} sq_debug_pix_tb_status_reg_1_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \
+     ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \
+     ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \
+     sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_2_t f;
+} sq_debug_pix_tb_status_reg_2_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \
+     ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \
+     ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \
+     sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_3_t f;
+} sq_debug_pix_tb_status_reg_3_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \
+     ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \
+     ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \
+     sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_state_mem_t f;
+} sq_debug_pix_tb_state_mem_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER0_SELECT_MASK \
+     (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \
+     ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \
+     sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_select_t f;
+} sq_perfcounter0_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER1_SELECT_MASK \
+     (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \
+     ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \
+     sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_select_t f;
+} sq_perfcounter1_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER2_SELECT_MASK \
+     (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \
+     ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \
+     sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_select_t f;
+} sq_perfcounter2_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER3_SELECT_MASK \
+     (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \
+     ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \
+     sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_select_t f;
+} sq_perfcounter3_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_LOW struct
+ */
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER0_LOW_MASK \
+     (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \
+     ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \
+     sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_low_t f;
+} sq_perfcounter0_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_HI struct
+ */
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER0_HI_MASK \
+     (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \
+     ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \
+     sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_hi_t f;
+} sq_perfcounter0_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_LOW struct
+ */
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER1_LOW_MASK \
+     (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \
+     ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \
+     sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_low_t f;
+} sq_perfcounter1_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_HI struct
+ */
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER1_HI_MASK \
+     (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \
+     ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \
+     sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_hi_t f;
+} sq_perfcounter1_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_LOW struct
+ */
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER2_LOW_MASK \
+     (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \
+     ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \
+     sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_low_t f;
+} sq_perfcounter2_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_HI struct
+ */
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER2_HI_MASK \
+     (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \
+     ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \
+     sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_hi_t f;
+} sq_perfcounter2_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_LOW struct
+ */
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER3_LOW_MASK \
+     (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \
+     ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \
+     sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_low_t f;
+} sq_perfcounter3_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_HI struct
+ */
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER3_HI_MASK \
+     (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \
+     ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \
+     sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_hi_t f;
+} sq_perfcounter3_hi_u;
+
+
+/*
+ * SX_PERFCOUNTER0_SELECT struct
+ */
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SX_PERFCOUNTER0_SELECT_MASK \
+     (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SX_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \
+     ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \
+     sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sx_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sx_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_select_t f;
+} sx_perfcounter0_select_u;
+
+
+/*
+ * SX_PERFCOUNTER0_LOW struct
+ */
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SX_PERFCOUNTER0_LOW_MASK \
+     (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \
+     ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \
+     sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_low_t f;
+} sx_perfcounter0_low_u;
+
+
+/*
+ * SX_PERFCOUNTER0_HI struct
+ */
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SX_PERFCOUNTER0_HI_MASK \
+     (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \
+     ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \
+     sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sx_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sx_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_hi_t f;
+} sx_perfcounter0_hi_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_0 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT 6
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT 14
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_ALU_0_MASK \
+     (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK | \
+      SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK | \
+      SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_ALU_0(vector_result, vector_dst_rel, low_precision_16b_fp, scalar_result, scalar_dst_rel, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \
+     ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \
+      (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) | \
+      (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \
+      (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \
+      (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) | \
+      (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \
+      (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \
+      (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \
+      (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \
+      (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \
+      (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_DST_REL(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_DST_REL(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_DST_REL(sq_instruction_alu_0_reg, vector_dst_rel) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) | (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_DST_REL(sq_instruction_alu_0_reg, scalar_dst_rel) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) | (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+          unsigned int vector_dst_rel                 : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int scalar_dst_rel                 : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+     } sq_instruction_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int scalar_dst_rel                 : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int vector_dst_rel                 : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE;
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+     } sq_instruction_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_0_t f;
+} sq_instruction_alu_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_1 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_1_MASK \
+     (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \
+      SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK)
+
+#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \
+     ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \
+      (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \
+      (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \
+      (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \
+      (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \
+      (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \
+      (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \
+      (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \
+      (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \
+      (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \
+      (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \
+      (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \
+      (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \
+      (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \
+      (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \
+      (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \
+      (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \
+      (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+     } sq_instruction_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+     } sq_instruction_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_1_t f;
+} sq_instruction_alu_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_2 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_2_MASK \
+     (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK)
+
+#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \
+     ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \
+      (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \
+      (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \
+      (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \
+      (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \
+      (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \
+      (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \
+      (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \
+      (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \
+      (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \
+      (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \
+      (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \
+      (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+     } sq_instruction_alu_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+     } sq_instruction_alu_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_2_t f;
+} sq_instruction_alu_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_0_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \
+     ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \
+      (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_0_t f;
+} sq_instruction_cf_exec_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_1_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \
+     ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_1_t f;
+} sq_instruction_cf_exec_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_EXEC_2_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \
+     ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \
+      (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_2_t f;
+} sq_instruction_cf_exec_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000
+
+#define SQ_INSTRUCTION_CF_LOOP_0_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \
+      (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_0_t f;
+} sq_instruction_cf_loop_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_CF_LOOP_1_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_1_t f;
+} sq_instruction_cf_loop_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_LOOP_2_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \
+     ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_2_t f;
+} sq_instruction_cf_loop_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \
+      (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_0_t f;
+} sq_instruction_cf_jmp_call_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \
+      (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_1_t f;
+} sq_instruction_cf_jmp_call_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_2_t f;
+} sq_instruction_cf_jmp_call_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \
+     ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_0_t f;
+} sq_instruction_cf_alloc_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \
+      (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_1_t f;
+} sq_instruction_cf_alloc_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_2_t f;
+} sq_instruction_cf_alloc_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_TFETCH_0_MASK \
+     (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \
+     ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \
+      (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \
+      (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \
+      (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \
+      (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \
+      (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_0_t f;
+} sq_instruction_tfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_1_MASK \
+     (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \
+      (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \
+      (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \
+      (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \
+      (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \
+      (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \
+      (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \
+      (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \
+      (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \
+      (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_1_t f;
+} sq_instruction_tfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_2_MASK \
+     (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \
+     ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \
+      (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \
+      (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \
+      (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \
+      (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \
+      (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \
+      (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_2_t f;
+} sq_instruction_tfetch_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_VFETCH_0_MASK \
+     (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \
+     ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \
+      (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \
+      (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \
+      (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_0_t f;
+} sq_instruction_vfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_1_MASK \
+     (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \
+      (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \
+      (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \
+      (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \
+      (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \
+      (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_1_t f;
+} sq_instruction_vfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_2_MASK \
+     (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \
+     ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \
+      (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+          unsigned int                                : 8;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 7;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int                                : 7;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 8;
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_2_t f;
+} sq_instruction_vfetch_2_u;
+
+
+/*
+ * SQ_CONSTANT_0 struct
+ */
+
+#define SQ_CONSTANT_0_RED_SIZE         32
+
+#define SQ_CONSTANT_0_RED_SHIFT        0
+
+#define SQ_CONSTANT_0_RED_MASK         0xffffffff
+
+#define SQ_CONSTANT_0_MASK \
+     (SQ_CONSTANT_0_RED_MASK)
+
+#define SQ_CONSTANT_0(red) \
+     ((red << SQ_CONSTANT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \
+     ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \
+     sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_0_t f;
+} sq_constant_0_u;
+
+
+/*
+ * SQ_CONSTANT_1 struct
+ */
+
+#define SQ_CONSTANT_1_GREEN_SIZE       32
+
+#define SQ_CONSTANT_1_GREEN_SHIFT      0
+
+#define SQ_CONSTANT_1_GREEN_MASK       0xffffffff
+
+#define SQ_CONSTANT_1_MASK \
+     (SQ_CONSTANT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_1(green) \
+     ((green << SQ_CONSTANT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \
+     ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \
+     sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_1_t f;
+} sq_constant_1_u;
+
+
+/*
+ * SQ_CONSTANT_2 struct
+ */
+
+#define SQ_CONSTANT_2_BLUE_SIZE        32
+
+#define SQ_CONSTANT_2_BLUE_SHIFT       0
+
+#define SQ_CONSTANT_2_BLUE_MASK        0xffffffff
+
+#define SQ_CONSTANT_2_MASK \
+     (SQ_CONSTANT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_2(blue) \
+     ((blue << SQ_CONSTANT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \
+     ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \
+     sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_2_t f;
+} sq_constant_2_u;
+
+
+/*
+ * SQ_CONSTANT_3 struct
+ */
+
+#define SQ_CONSTANT_3_ALPHA_SIZE       32
+
+#define SQ_CONSTANT_3_ALPHA_SHIFT      0
+
+#define SQ_CONSTANT_3_ALPHA_MASK       0xffffffff
+
+#define SQ_CONSTANT_3_MASK \
+     (SQ_CONSTANT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_3(alpha) \
+     ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \
+     ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \
+     sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_3_t f;
+} sq_constant_3_u;
+
+
+/*
+ * SQ_FETCH_0 struct
+ */
+
+#define SQ_FETCH_0_VALUE_SIZE          32
+
+#define SQ_FETCH_0_VALUE_SHIFT         0
+
+#define SQ_FETCH_0_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_0_MASK \
+     (SQ_FETCH_0_VALUE_MASK)
+
+#define SQ_FETCH_0(value) \
+     ((value << SQ_FETCH_0_VALUE_SHIFT))
+
+#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \
+     ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT)
+
+#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \
+     sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_0_t f;
+} sq_fetch_0_u;
+
+
+/*
+ * SQ_FETCH_1 struct
+ */
+
+#define SQ_FETCH_1_VALUE_SIZE          32
+
+#define SQ_FETCH_1_VALUE_SHIFT         0
+
+#define SQ_FETCH_1_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_1_MASK \
+     (SQ_FETCH_1_VALUE_MASK)
+
+#define SQ_FETCH_1(value) \
+     ((value << SQ_FETCH_1_VALUE_SHIFT))
+
+#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \
+     ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT)
+
+#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \
+     sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_1_t f;
+} sq_fetch_1_u;
+
+
+/*
+ * SQ_FETCH_2 struct
+ */
+
+#define SQ_FETCH_2_VALUE_SIZE          32
+
+#define SQ_FETCH_2_VALUE_SHIFT         0
+
+#define SQ_FETCH_2_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_2_MASK \
+     (SQ_FETCH_2_VALUE_MASK)
+
+#define SQ_FETCH_2(value) \
+     ((value << SQ_FETCH_2_VALUE_SHIFT))
+
+#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \
+     ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT)
+
+#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \
+     sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_2_t f;
+} sq_fetch_2_u;
+
+
+/*
+ * SQ_FETCH_3 struct
+ */
+
+#define SQ_FETCH_3_VALUE_SIZE          32
+
+#define SQ_FETCH_3_VALUE_SHIFT         0
+
+#define SQ_FETCH_3_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_3_MASK \
+     (SQ_FETCH_3_VALUE_MASK)
+
+#define SQ_FETCH_3(value) \
+     ((value << SQ_FETCH_3_VALUE_SHIFT))
+
+#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \
+     ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT)
+
+#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \
+     sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_3_t f;
+} sq_fetch_3_u;
+
+
+/*
+ * SQ_FETCH_4 struct
+ */
+
+#define SQ_FETCH_4_VALUE_SIZE          32
+
+#define SQ_FETCH_4_VALUE_SHIFT         0
+
+#define SQ_FETCH_4_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_4_MASK \
+     (SQ_FETCH_4_VALUE_MASK)
+
+#define SQ_FETCH_4(value) \
+     ((value << SQ_FETCH_4_VALUE_SHIFT))
+
+#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \
+     ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT)
+
+#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \
+     sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_4_t f;
+} sq_fetch_4_u;
+
+
+/*
+ * SQ_FETCH_5 struct
+ */
+
+#define SQ_FETCH_5_VALUE_SIZE          32
+
+#define SQ_FETCH_5_VALUE_SHIFT         0
+
+#define SQ_FETCH_5_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_5_MASK \
+     (SQ_FETCH_5_VALUE_MASK)
+
+#define SQ_FETCH_5(value) \
+     ((value << SQ_FETCH_5_VALUE_SHIFT))
+
+#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \
+     ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT)
+
+#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \
+     sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_5_t f;
+} sq_fetch_5_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_0 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0
+#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001
+#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_0_MASK \
+     (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \
+      SQ_CONSTANT_VFETCH_0_STATE_MASK | \
+      SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \
+     ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \
+      (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \
+      (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_0_t f;
+} sq_constant_vfetch_0_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_1 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_1_MASK \
+     (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \
+      SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \
+     ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \
+      (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_1_t f;
+} sq_constant_vfetch_1_u;
+
+
+/*
+ * SQ_CONSTANT_T2 struct
+ */
+
+#define SQ_CONSTANT_T2_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T2_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T2_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T2_MASK \
+     (SQ_CONSTANT_T2_VALUE_MASK)
+
+#define SQ_CONSTANT_T2(value) \
+     ((value << SQ_CONSTANT_T2_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \
+     ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \
+     sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t2_t f;
+} sq_constant_t2_u;
+
+
+/*
+ * SQ_CONSTANT_T3 struct
+ */
+
+#define SQ_CONSTANT_T3_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T3_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T3_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T3_MASK \
+     (SQ_CONSTANT_T3_VALUE_MASK)
+
+#define SQ_CONSTANT_T3(value) \
+     ((value << SQ_CONSTANT_T3_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \
+     ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \
+     sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t3_t f;
+} sq_constant_t3_u;
+
+
+/*
+ * SQ_CF_BOOLEANS struct
+ */
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_BOOLEANS_MASK \
+     (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_booleans_t f;
+} sq_cf_booleans_u;
+
+
+/*
+ * SQ_CF_LOOP struct
+ */
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_START_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE   8
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT  16
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK  0x000000ff
+#define SQ_CF_LOOP_CF_LOOP_START_MASK  0x0000ff00
+#define SQ_CF_LOOP_CF_LOOP_STEP_MASK   0x00ff0000
+
+#define SQ_CF_LOOP_MASK \
+     (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_loop_t f;
+} sq_cf_loop_u;
+
+
+/*
+ * SQ_CONSTANT_RT_0 struct
+ */
+
+#define SQ_CONSTANT_RT_0_RED_SIZE      32
+
+#define SQ_CONSTANT_RT_0_RED_SHIFT     0
+
+#define SQ_CONSTANT_RT_0_RED_MASK      0xffffffff
+
+#define SQ_CONSTANT_RT_0_MASK \
+     (SQ_CONSTANT_RT_0_RED_MASK)
+
+#define SQ_CONSTANT_RT_0(red) \
+     ((red << SQ_CONSTANT_RT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \
+     ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \
+     sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_0_t f;
+} sq_constant_rt_0_u;
+
+
+/*
+ * SQ_CONSTANT_RT_1 struct
+ */
+
+#define SQ_CONSTANT_RT_1_GREEN_SIZE    32
+
+#define SQ_CONSTANT_RT_1_GREEN_SHIFT   0
+
+#define SQ_CONSTANT_RT_1_GREEN_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_1_MASK \
+     (SQ_CONSTANT_RT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_RT_1(green) \
+     ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \
+     ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \
+     sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_1_t f;
+} sq_constant_rt_1_u;
+
+
+/*
+ * SQ_CONSTANT_RT_2 struct
+ */
+
+#define SQ_CONSTANT_RT_2_BLUE_SIZE     32
+
+#define SQ_CONSTANT_RT_2_BLUE_SHIFT    0
+
+#define SQ_CONSTANT_RT_2_BLUE_MASK     0xffffffff
+
+#define SQ_CONSTANT_RT_2_MASK \
+     (SQ_CONSTANT_RT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_RT_2(blue) \
+     ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \
+     ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \
+     sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_2_t f;
+} sq_constant_rt_2_u;
+
+
+/*
+ * SQ_CONSTANT_RT_3 struct
+ */
+
+#define SQ_CONSTANT_RT_3_ALPHA_SIZE    32
+
+#define SQ_CONSTANT_RT_3_ALPHA_SHIFT   0
+
+#define SQ_CONSTANT_RT_3_ALPHA_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_3_MASK \
+     (SQ_CONSTANT_RT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_RT_3(alpha) \
+     ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \
+     ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \
+     sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_3_t f;
+} sq_constant_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_0 struct
+ */
+
+#define SQ_FETCH_RT_0_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_0_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_0_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_0_MASK \
+     (SQ_FETCH_RT_0_VALUE_MASK)
+
+#define SQ_FETCH_RT_0(value) \
+     ((value << SQ_FETCH_RT_0_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \
+     ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \
+     sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_0_t f;
+} sq_fetch_rt_0_u;
+
+
+/*
+ * SQ_FETCH_RT_1 struct
+ */
+
+#define SQ_FETCH_RT_1_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_1_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_1_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_1_MASK \
+     (SQ_FETCH_RT_1_VALUE_MASK)
+
+#define SQ_FETCH_RT_1(value) \
+     ((value << SQ_FETCH_RT_1_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \
+     ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \
+     sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_1_t f;
+} sq_fetch_rt_1_u;
+
+
+/*
+ * SQ_FETCH_RT_2 struct
+ */
+
+#define SQ_FETCH_RT_2_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_2_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_2_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_2_MASK \
+     (SQ_FETCH_RT_2_VALUE_MASK)
+
+#define SQ_FETCH_RT_2(value) \
+     ((value << SQ_FETCH_RT_2_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \
+     ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \
+     sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_2_t f;
+} sq_fetch_rt_2_u;
+
+
+/*
+ * SQ_FETCH_RT_3 struct
+ */
+
+#define SQ_FETCH_RT_3_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_3_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_3_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_3_MASK \
+     (SQ_FETCH_RT_3_VALUE_MASK)
+
+#define SQ_FETCH_RT_3(value) \
+     ((value << SQ_FETCH_RT_3_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \
+     ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \
+     sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_3_t f;
+} sq_fetch_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_4 struct
+ */
+
+#define SQ_FETCH_RT_4_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_4_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_4_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_4_MASK \
+     (SQ_FETCH_RT_4_VALUE_MASK)
+
+#define SQ_FETCH_RT_4(value) \
+     ((value << SQ_FETCH_RT_4_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \
+     ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \
+     sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_4_t f;
+} sq_fetch_rt_4_u;
+
+
+/*
+ * SQ_FETCH_RT_5 struct
+ */
+
+#define SQ_FETCH_RT_5_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_5_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_5_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_5_MASK \
+     (SQ_FETCH_RT_5_VALUE_MASK)
+
+#define SQ_FETCH_RT_5(value) \
+     ((value << SQ_FETCH_RT_5_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \
+     ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \
+     sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_5_t f;
+} sq_fetch_rt_5_u;
+
+
+/*
+ * SQ_CF_RT_BOOLEANS struct
+ */
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_RT_BOOLEANS_MASK \
+     (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_booleans_t f;
+} sq_cf_rt_booleans_u;
+
+
+/*
+ * SQ_CF_RT_LOOP struct
+ */
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff
+#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000
+
+#define SQ_CF_RT_LOOP_MASK \
+     (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_rt_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_rt_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_loop_t f;
+} sq_cf_rt_loop_u;
+
+
+/*
+ * SQ_VS_PROGRAM struct
+ */
+
+#define SQ_VS_PROGRAM_BASE_SIZE        12
+#define SQ_VS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_VS_PROGRAM_BASE_SHIFT       0
+#define SQ_VS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_VS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_VS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_VS_PROGRAM_MASK \
+     (SQ_VS_PROGRAM_BASE_MASK | \
+      SQ_VS_PROGRAM_SIZE_MASK)
+
+#define SQ_VS_PROGRAM(base, size) \
+     ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_VS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_vs_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+     } sq_vs_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_program_t f;
+} sq_vs_program_u;
+
+
+/*
+ * SQ_PS_PROGRAM struct
+ */
+
+#define SQ_PS_PROGRAM_BASE_SIZE        12
+#define SQ_PS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_PS_PROGRAM_BASE_SHIFT       0
+#define SQ_PS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_PS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_PS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_PS_PROGRAM_MASK \
+     (SQ_PS_PROGRAM_BASE_MASK | \
+      SQ_PS_PROGRAM_SIZE_MASK)
+
+#define SQ_PS_PROGRAM(base, size) \
+     ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_PS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_ps_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+     } sq_ps_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_program_t f;
+} sq_ps_program_u;
+
+
+/*
+ * SQ_CF_PROGRAM_SIZE struct
+ */
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000
+
+#define SQ_CF_PROGRAM_SIZE_MASK \
+     (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \
+      SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK)
+
+#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \
+     ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \
+      (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT))
+
+#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 9;
+     } sq_cf_program_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int                                : 9;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+     } sq_cf_program_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_program_size_t f;
+} sq_cf_program_size_u;
+
+
+/*
+ * SQ_INTERPOLATOR_CNTL struct
+ */
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000
+
+#define SQ_INTERPOLATOR_CNTL_MASK \
+     (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \
+      SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK)
+
+#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \
+     ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \
+      (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT))
+
+#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+     } sq_interpolator_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+     } sq_interpolator_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_interpolator_cntl_t f;
+} sq_interpolator_cntl_u;
+
+
+/*
+ * SQ_PROGRAM_CNTL struct
+ */
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000
+#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000
+
+#define SQ_PROGRAM_CNTL_MASK \
+     (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK)
+
+#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \
+     ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \
+      (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \
+      (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \
+      (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \
+      (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \
+      (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \
+      (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \
+      (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \
+      (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \
+      (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT))
+
+#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+     } sq_program_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+     } sq_program_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_program_cntl_t f;
+} sq_program_cntl_u;
+
+
+/*
+ * SQ_WRAPPING_0 struct
+ */
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f
+#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0
+#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00
+#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000
+#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000
+#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000
+#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000
+#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000
+
+#define SQ_WRAPPING_0_MASK \
+     (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_7_MASK)
+
+#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \
+     ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \
+      (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \
+      (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \
+      (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \
+      (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \
+      (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \
+      (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \
+      (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT))
+
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+     } sq_wrapping_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+     } sq_wrapping_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_0_t f;
+} sq_wrapping_0_u;
+
+
+/*
+ * SQ_WRAPPING_1 struct
+ */
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f
+#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0
+#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00
+#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000
+#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000
+#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000
+#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000
+#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000
+
+#define SQ_WRAPPING_1_MASK \
+     (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_15_MASK)
+
+#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \
+     ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \
+      (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \
+      (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \
+      (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \
+      (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \
+      (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \
+      (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \
+      (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT))
+
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+     } sq_wrapping_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+     } sq_wrapping_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_1_t f;
+} sq_wrapping_1_u;
+
+
+/*
+ * SQ_VS_CONST struct
+ */
+
+#define SQ_VS_CONST_BASE_SIZE          9
+#define SQ_VS_CONST_SIZE_SIZE          9
+
+#define SQ_VS_CONST_BASE_SHIFT         0
+#define SQ_VS_CONST_SIZE_SHIFT         12
+
+#define SQ_VS_CONST_BASE_MASK          0x000001ff
+#define SQ_VS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_VS_CONST_MASK \
+     (SQ_VS_CONST_BASE_MASK | \
+      SQ_VS_CONST_SIZE_MASK)
+
+#define SQ_VS_CONST(base, size) \
+     ((base << SQ_VS_CONST_BASE_SHIFT) | \
+      (size << SQ_VS_CONST_SIZE_SHIFT))
+
+#define SQ_VS_CONST_GET_BASE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT)
+
+#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_vs_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+     } sq_vs_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_const_t f;
+} sq_vs_const_u;
+
+
+/*
+ * SQ_PS_CONST struct
+ */
+
+#define SQ_PS_CONST_BASE_SIZE          9
+#define SQ_PS_CONST_SIZE_SIZE          9
+
+#define SQ_PS_CONST_BASE_SHIFT         0
+#define SQ_PS_CONST_SIZE_SHIFT         12
+
+#define SQ_PS_CONST_BASE_MASK          0x000001ff
+#define SQ_PS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_PS_CONST_MASK \
+     (SQ_PS_CONST_BASE_MASK | \
+      SQ_PS_CONST_SIZE_MASK)
+
+#define SQ_PS_CONST(base, size) \
+     ((base << SQ_PS_CONST_BASE_SHIFT) | \
+      (size << SQ_PS_CONST_SIZE_SHIFT))
+
+#define SQ_PS_CONST_GET_BASE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT)
+
+#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_ps_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+     } sq_ps_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_const_t f;
+} sq_ps_const_u;
+
+
+/*
+ * SQ_CONTEXT_MISC struct
+ */
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000
+
+#define SQ_CONTEXT_MISC_MASK \
+     (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \
+      SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \
+      SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \
+      SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \
+      SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK)
+
+#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \
+     ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \
+      (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \
+      (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \
+      (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \
+      (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \
+      (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \
+      (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT))
+
+#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int                                : 4;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int                                : 13;
+     } sq_context_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int                                : 13;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int                                : 4;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+     } sq_context_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_context_misc_t f;
+} sq_context_misc_u;
+
+
+/*
+ * SQ_CF_RD_BASE struct
+ */
+
+#define SQ_CF_RD_BASE_RD_BASE_SIZE     3
+
+#define SQ_CF_RD_BASE_RD_BASE_SHIFT    0
+
+#define SQ_CF_RD_BASE_RD_BASE_MASK     0x00000007
+
+#define SQ_CF_RD_BASE_MASK \
+     (SQ_CF_RD_BASE_RD_BASE_MASK)
+
+#define SQ_CF_RD_BASE(rd_base) \
+     ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT))
+
+#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \
+     ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \
+     sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+          unsigned int                                : 29;
+     } sq_cf_rd_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int                                : 29;
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+     } sq_cf_rd_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rd_base_t f;
+} sq_cf_rd_base_u;
+
+
+/*
+ * SQ_DEBUG_MISC_0 struct
+ */
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000
+
+#define SQ_DEBUG_MISC_0_MASK \
+     (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK)
+
+#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \
+     ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \
+      (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \
+      (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \
+      (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT))
+
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+     } sq_debug_misc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+     } sq_debug_misc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_0_t f;
+} sq_debug_misc_0_u;
+
+
+/*
+ * SQ_DEBUG_MISC_1 struct
+ */
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000
+
+#define SQ_DEBUG_MISC_1_MASK \
+     (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \
+      SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \
+      SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \
+      SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK)
+
+#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \
+     ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \
+      (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \
+      (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \
+      (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT))
+
+#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int                                : 5;
+     } sq_debug_misc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int                                : 5;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+     } sq_debug_misc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_1_t f;
+} sq_debug_misc_1_u;
+
+
+#endif
+
+
+#if !defined (_SX_FIDDLE_H)
+#define _SX_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sx_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_TP_FIDDLE_H)
+#define _TP_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  tp_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * TC_CNTL_STATUS struct
+ */
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2
+#define TC_CNTL_STATUS_TC_BUSY_SIZE    1
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18
+#define TC_CNTL_STATUS_TC_BUSY_SHIFT   31
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000
+#define TC_CNTL_STATUS_TC_BUSY_MASK    0x80000000
+
+#define TC_CNTL_STATUS_MASK \
+     (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \
+      TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \
+      TC_CNTL_STATUS_TC_BUSY_MASK)
+
+#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \
+     ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \
+      (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \
+      (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT))
+
+#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+          unsigned int                                : 17;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+     } tc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 17;
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+     } tc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tc_cntl_status_t f;
+} tc_cntl_status_u;
+
+
+/*
+ * TCR_CHICKEN struct
+ */
+
+#define TCR_CHICKEN_SPARE_SIZE         32
+
+#define TCR_CHICKEN_SPARE_SHIFT        0
+
+#define TCR_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCR_CHICKEN_MASK \
+     (TCR_CHICKEN_SPARE_MASK)
+
+#define TCR_CHICKEN(spare) \
+     ((spare << TCR_CHICKEN_SPARE_SHIFT))
+
+#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \
+     ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT)
+
+#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \
+     tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_chicken_t f;
+} tcr_chicken_u;
+
+
+/*
+ * TCF_CHICKEN struct
+ */
+
+#define TCF_CHICKEN_SPARE_SIZE         32
+
+#define TCF_CHICKEN_SPARE_SHIFT        0
+
+#define TCF_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCF_CHICKEN_MASK \
+     (TCF_CHICKEN_SPARE_MASK)
+
+#define TCF_CHICKEN(spare) \
+     ((spare << TCF_CHICKEN_SPARE_SHIFT))
+
+#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \
+     ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT)
+
+#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \
+     tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_chicken_t f;
+} tcf_chicken_u;
+
+
+/*
+ * TCM_CHICKEN struct
+ */
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1
+#define TCM_CHICKEN_SPARE_SIZE         23
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8
+#define TCM_CHICKEN_SPARE_SHIFT        9
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100
+#define TCM_CHICKEN_SPARE_MASK         0xfffffe00
+
+#define TCM_CHICKEN_MASK \
+     (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \
+      TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \
+      TCM_CHICKEN_SPARE_MASK)
+
+#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \
+     ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \
+      (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \
+      (spare << TCM_CHICKEN_SPARE_SHIFT))
+
+#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT)
+
+#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+     } tcm_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+     } tcm_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_chicken_t f;
+} tcm_chicken_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER0_SELECT_MASK \
+     (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \
+     ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \
+     tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_select_t f;
+} tcr_perfcounter0_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER1_SELECT_MASK \
+     (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \
+     ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \
+     tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_select_t f;
+} tcr_perfcounter1_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_HI struct
+ */
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER0_HI_MASK \
+     (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \
+     ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \
+     tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_hi_t f;
+} tcr_perfcounter0_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_HI struct
+ */
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER1_HI_MASK \
+     (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \
+     ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \
+     tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_hi_t f;
+} tcr_perfcounter1_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_LOW struct
+ */
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER0_LOW_MASK \
+     (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \
+     ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \
+     tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_low_t f;
+} tcr_perfcounter0_low_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_LOW struct
+ */
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER1_LOW_MASK \
+     (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \
+     ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \
+     tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_low_t f;
+} tcr_perfcounter1_low_u;
+
+
+/*
+ * TP_TC_CLKGATE_CNTL struct
+ */
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038
+
+#define TP_TC_CLKGATE_CNTL_MASK \
+     (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \
+      TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK)
+
+#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \
+     ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \
+      (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT))
+
+#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int                                : 26;
+     } tp_tc_clkgate_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int                                : 26;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+     } tp_tc_clkgate_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp_tc_clkgate_cntl_t f;
+} tp_tc_clkgate_cntl_u;
+
+
+/*
+ * TPC_CNTL_STATUS struct
+ */
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BUSY_SIZE  1
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15
+#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17
+#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19
+#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22
+#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23
+#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25
+#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27
+#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30
+#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000
+#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000
+#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000
+#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000
+#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000
+#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000
+#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000
+#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000
+#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000
+#define TPC_CNTL_STATUS_TPC_BUSY_MASK  0x80000000
+
+#define TPC_CNTL_STATUS_MASK \
+     (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTR_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TF_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \
+      TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \
+      TPC_CNTL_STATUS_TPC_BUSY_MASK)
+
+#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \
+     ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \
+      (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \
+      (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \
+      (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \
+      (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \
+      (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \
+      (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \
+      (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \
+      (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \
+      (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \
+      (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \
+      (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \
+      (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \
+      (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \
+      (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \
+      (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \
+      (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \
+      (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \
+      (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \
+      (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \
+      (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \
+      (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \
+      (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT))
+
+#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_cntl_status_t f;
+} tpc_cntl_status_u;
+
+
+/*
+ * TPC_DEBUG0 struct
+ */
+
+#define TPC_DEBUG0_LOD_CNTL_SIZE       2
+#define TPC_DEBUG0_IC_CTR_SIZE         2
+#define TPC_DEBUG0_WALKER_CNTL_SIZE    4
+#define TPC_DEBUG0_ALIGNER_CNTL_SIZE   3
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1
+#define TPC_DEBUG0_WALKER_STATE_SIZE   10
+#define TPC_DEBUG0_ALIGNER_STATE_SIZE  2
+#define TPC_DEBUG0_REG_CLK_EN_SIZE     1
+#define TPC_DEBUG0_TPC_CLK_EN_SIZE     1
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE   1
+
+#define TPC_DEBUG0_LOD_CNTL_SHIFT      0
+#define TPC_DEBUG0_IC_CTR_SHIFT        2
+#define TPC_DEBUG0_WALKER_CNTL_SHIFT   4
+#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT  8
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12
+#define TPC_DEBUG0_WALKER_STATE_SHIFT  16
+#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26
+#define TPC_DEBUG0_REG_CLK_EN_SHIFT    29
+#define TPC_DEBUG0_TPC_CLK_EN_SHIFT    30
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT  31
+
+#define TPC_DEBUG0_LOD_CNTL_MASK       0x00000003
+#define TPC_DEBUG0_IC_CTR_MASK         0x0000000c
+#define TPC_DEBUG0_WALKER_CNTL_MASK    0x000000f0
+#define TPC_DEBUG0_ALIGNER_CNTL_MASK   0x00000700
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000
+#define TPC_DEBUG0_WALKER_STATE_MASK   0x03ff0000
+#define TPC_DEBUG0_ALIGNER_STATE_MASK  0x0c000000
+#define TPC_DEBUG0_REG_CLK_EN_MASK     0x20000000
+#define TPC_DEBUG0_TPC_CLK_EN_MASK     0x40000000
+#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK   0x80000000
+
+#define TPC_DEBUG0_MASK \
+     (TPC_DEBUG0_LOD_CNTL_MASK | \
+      TPC_DEBUG0_IC_CTR_MASK | \
+      TPC_DEBUG0_WALKER_CNTL_MASK | \
+      TPC_DEBUG0_ALIGNER_CNTL_MASK | \
+      TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \
+      TPC_DEBUG0_WALKER_STATE_MASK | \
+      TPC_DEBUG0_ALIGNER_STATE_MASK | \
+      TPC_DEBUG0_REG_CLK_EN_MASK | \
+      TPC_DEBUG0_TPC_CLK_EN_MASK | \
+      TPC_DEBUG0_SQ_TP_WAKEUP_MASK)
+
+#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \
+     ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \
+      (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \
+      (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \
+      (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \
+      (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \
+      (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \
+      (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \
+      (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \
+      (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \
+      (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT))
+
+#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 3;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+     } tpc_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+     } tpc_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug0_t f;
+} tpc_debug0_u;
+
+
+/*
+ * TPC_DEBUG1 struct
+ */
+
+#define TPC_DEBUG1_UNUSED_SIZE         1
+
+#define TPC_DEBUG1_UNUSED_SHIFT        0
+
+#define TPC_DEBUG1_UNUSED_MASK         0x00000001
+
+#define TPC_DEBUG1_MASK \
+     (TPC_DEBUG1_UNUSED_MASK)
+
+#define TPC_DEBUG1(unused) \
+     ((unused << TPC_DEBUG1_UNUSED_SHIFT))
+
+#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \
+     ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT)
+
+#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \
+     tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+          unsigned int                                : 31;
+     } tpc_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int                                : 31;
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+     } tpc_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug1_t f;
+} tpc_debug1_u;
+
+
+/*
+ * TPC_CHICKEN struct
+ */
+
+#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1
+#define TPC_CHICKEN_SPARE_SIZE         31
+
+#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0
+#define TPC_CHICKEN_SPARE_SHIFT        1
+
+#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001
+#define TPC_CHICKEN_SPARE_MASK         0xfffffffe
+
+#define TPC_CHICKEN_MASK \
+     (TPC_CHICKEN_BLEND_PRECISION_MASK | \
+      TPC_CHICKEN_SPARE_MASK)
+
+#define TPC_CHICKEN(blend_precision, spare) \
+     ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \
+      (spare << TPC_CHICKEN_SPARE_SHIFT))
+
+#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT)
+
+#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+     } tpc_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+     } tpc_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_chicken_t f;
+} tpc_chicken_u;
+
+
+/*
+ * TP0_CNTL_STATUS struct
+ */
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1
+#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TP_BUSY_SIZE   1
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14
+#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16
+#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17
+#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18
+#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19
+#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21
+#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23
+#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25
+#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27
+#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29
+#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30
+#define TP0_CNTL_STATUS_TP_BUSY_SHIFT  31
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200
+#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000
+#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000
+#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000
+#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000
+#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000
+#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000
+#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000
+#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000
+#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000
+#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000
+#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000
+#define TP0_CNTL_STATUS_TP_BUSY_MASK   0x80000000
+
+#define TP0_CNTL_STATUS_MASK \
+     (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_IN_LC_RTS_MASK | \
+      TP0_CNTL_STATUS_LC_LA_RTS_MASK | \
+      TP0_CNTL_STATUS_LA_FL_RTS_MASK | \
+      TP0_CNTL_STATUS_FL_TA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \
+      TP0_CNTL_STATUS_TB_TO_RTS_MASK | \
+      TP0_CNTL_STATUS_TP_BUSY_MASK)
+
+#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \
+     ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \
+      (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \
+      (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \
+      (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \
+      (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \
+      (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \
+      (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \
+      (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \
+      (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \
+      (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \
+      (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \
+      (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \
+      (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \
+      (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \
+      (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \
+      (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \
+      (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \
+      (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \
+      (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \
+      (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \
+      (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \
+      (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \
+      (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \
+      (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \
+      (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \
+      (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \
+      (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \
+      (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \
+      (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \
+      (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT))
+
+#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_cntl_status_t f;
+} tp0_cntl_status_u;
+
+
+/*
+ * TP0_DEBUG struct
+ */
+
+#define TP0_DEBUG_Q_LOD_CNTL_SIZE      2
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE  1
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17
+#define TP0_DEBUG_REG_CLK_EN_SIZE      1
+#define TP0_DEBUG_PERF_CLK_EN_SIZE     1
+#define TP0_DEBUG_TP_CLK_EN_SIZE       1
+#define TP0_DEBUG_Q_WALKER_CNTL_SIZE   4
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE  3
+
+#define TP0_DEBUG_Q_LOD_CNTL_SHIFT     0
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4
+#define TP0_DEBUG_REG_CLK_EN_SHIFT     21
+#define TP0_DEBUG_PERF_CLK_EN_SHIFT    22
+#define TP0_DEBUG_TP_CLK_EN_SHIFT      23
+#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT  24
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28
+
+#define TP0_DEBUG_Q_LOD_CNTL_MASK      0x00000003
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK  0x00000008
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0
+#define TP0_DEBUG_REG_CLK_EN_MASK      0x00200000
+#define TP0_DEBUG_PERF_CLK_EN_MASK     0x00400000
+#define TP0_DEBUG_TP_CLK_EN_MASK       0x00800000
+#define TP0_DEBUG_Q_WALKER_CNTL_MASK   0x0f000000
+#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK  0x70000000
+
+#define TP0_DEBUG_MASK \
+     (TP0_DEBUG_Q_LOD_CNTL_MASK | \
+      TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \
+      TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \
+      TP0_DEBUG_REG_CLK_EN_MASK | \
+      TP0_DEBUG_PERF_CLK_EN_MASK | \
+      TP0_DEBUG_TP_CLK_EN_MASK | \
+      TP0_DEBUG_Q_WALKER_CNTL_MASK | \
+      TP0_DEBUG_Q_ALIGNER_CNTL_MASK)
+
+#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \
+     ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \
+      (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \
+      (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \
+      (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \
+      (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \
+      (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \
+      (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \
+      (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT))
+
+#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+     } tp0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int                                : 1;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+     } tp0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_debug_t f;
+} tp0_debug_u;
+
+
+/*
+ * TP0_CHICKEN struct
+ */
+
+#define TP0_CHICKEN_TT_MODE_SIZE       1
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1
+#define TP0_CHICKEN_SPARE_SIZE         30
+
+#define TP0_CHICKEN_TT_MODE_SHIFT      0
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1
+#define TP0_CHICKEN_SPARE_SHIFT        2
+
+#define TP0_CHICKEN_TT_MODE_MASK       0x00000001
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002
+#define TP0_CHICKEN_SPARE_MASK         0xfffffffc
+
+#define TP0_CHICKEN_MASK \
+     (TP0_CHICKEN_TT_MODE_MASK | \
+      TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \
+      TP0_CHICKEN_SPARE_MASK)
+
+#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \
+     ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \
+      (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \
+      (spare << TP0_CHICKEN_SPARE_SHIFT))
+
+#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT)
+
+#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+     } tp0_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+     } tp0_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_chicken_t f;
+} tp0_chicken_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER0_SELECT_MASK \
+     (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \
+     ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \
+     tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_select_t f;
+} tp0_perfcounter0_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_HI struct
+ */
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER0_HI_MASK \
+     (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \
+     ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \
+     tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_hi_t f;
+} tp0_perfcounter0_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_LOW struct
+ */
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER0_LOW_MASK \
+     (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \
+     ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \
+     tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_low_t f;
+} tp0_perfcounter0_low_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER1_SELECT_MASK \
+     (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \
+     ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \
+     tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_select_t f;
+} tp0_perfcounter1_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_HI struct
+ */
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER1_HI_MASK \
+     (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \
+     ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \
+     tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_hi_t f;
+} tp0_perfcounter1_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_LOW struct
+ */
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER1_LOW_MASK \
+     (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \
+     ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \
+     tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_low_t f;
+} tp0_perfcounter1_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER0_SELECT_MASK \
+     (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \
+     ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \
+     tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_select_t f;
+} tcm_perfcounter0_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER1_SELECT_MASK \
+     (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \
+     ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \
+     tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_select_t f;
+} tcm_perfcounter1_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_HI struct
+ */
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER0_HI_MASK \
+     (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \
+     ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \
+     tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_hi_t f;
+} tcm_perfcounter0_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_HI struct
+ */
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER1_HI_MASK \
+     (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \
+     ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \
+     tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_hi_t f;
+} tcm_perfcounter1_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_LOW struct
+ */
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER0_LOW_MASK \
+     (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \
+     ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \
+     tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_low_t f;
+} tcm_perfcounter0_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_LOW struct
+ */
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER1_LOW_MASK \
+     (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \
+     ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \
+     tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_low_t f;
+} tcm_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER0_SELECT_MASK \
+     (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \
+     ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \
+     tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_select_t f;
+} tcf_perfcounter0_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER1_SELECT_MASK \
+     (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \
+     ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \
+     tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_select_t f;
+} tcf_perfcounter1_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER2_SELECT_MASK \
+     (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \
+     ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \
+     tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_select_t f;
+} tcf_perfcounter2_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER3_SELECT_MASK \
+     (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \
+     ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \
+     tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_select_t f;
+} tcf_perfcounter3_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER4_SELECT_MASK \
+     (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \
+     ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \
+     tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter4_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter4_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_select_t f;
+} tcf_perfcounter4_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER5_SELECT_MASK \
+     (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \
+     ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \
+     tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter5_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter5_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_select_t f;
+} tcf_perfcounter5_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER6_SELECT_MASK \
+     (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \
+     ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \
+     tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter6_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter6_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_select_t f;
+} tcf_perfcounter6_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER7_SELECT_MASK \
+     (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \
+     ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \
+     tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter7_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter7_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_select_t f;
+} tcf_perfcounter7_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER8_SELECT_MASK \
+     (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \
+     ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \
+     tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter8_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter8_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_select_t f;
+} tcf_perfcounter8_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER9_SELECT_MASK \
+     (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \
+     ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \
+     tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter9_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter9_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_select_t f;
+} tcf_perfcounter9_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER10_SELECT_MASK \
+     (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \
+     ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \
+     tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter10_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter10_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_select_t f;
+} tcf_perfcounter10_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER11_SELECT_MASK \
+     (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \
+     ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \
+     tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter11_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter11_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_select_t f;
+} tcf_perfcounter11_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_HI struct
+ */
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER0_HI_MASK \
+     (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \
+     ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \
+     tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_hi_t f;
+} tcf_perfcounter0_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_HI struct
+ */
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER1_HI_MASK \
+     (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \
+     ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \
+     tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_hi_t f;
+} tcf_perfcounter1_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_HI struct
+ */
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER2_HI_MASK \
+     (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \
+     ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \
+     tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_hi_t f;
+} tcf_perfcounter2_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_HI struct
+ */
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER3_HI_MASK \
+     (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \
+     ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \
+     tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_hi_t f;
+} tcf_perfcounter3_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_HI struct
+ */
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER4_HI_MASK \
+     (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \
+     ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \
+     tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter4_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter4_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_hi_t f;
+} tcf_perfcounter4_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_HI struct
+ */
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER5_HI_MASK \
+     (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \
+     ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \
+     tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter5_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter5_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_hi_t f;
+} tcf_perfcounter5_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_HI struct
+ */
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER6_HI_MASK \
+     (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \
+     ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \
+     tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter6_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter6_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_hi_t f;
+} tcf_perfcounter6_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_HI struct
+ */
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER7_HI_MASK \
+     (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \
+     ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \
+     tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter7_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter7_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_hi_t f;
+} tcf_perfcounter7_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_HI struct
+ */
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER8_HI_MASK \
+     (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \
+     ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \
+     tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter8_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter8_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_hi_t f;
+} tcf_perfcounter8_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_HI struct
+ */
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER9_HI_MASK \
+     (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \
+     ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \
+     tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter9_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter9_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_hi_t f;
+} tcf_perfcounter9_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_HI struct
+ */
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER10_HI_MASK \
+     (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \
+     ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \
+     tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter10_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter10_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_hi_t f;
+} tcf_perfcounter10_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_HI struct
+ */
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER11_HI_MASK \
+     (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \
+     ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \
+     tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter11_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter11_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_hi_t f;
+} tcf_perfcounter11_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_LOW struct
+ */
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER0_LOW_MASK \
+     (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \
+     ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \
+     tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_low_t f;
+} tcf_perfcounter0_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_LOW struct
+ */
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER1_LOW_MASK \
+     (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \
+     ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \
+     tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_low_t f;
+} tcf_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_LOW struct
+ */
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER2_LOW_MASK \
+     (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \
+     ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \
+     tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_low_t f;
+} tcf_perfcounter2_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_LOW struct
+ */
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER3_LOW_MASK \
+     (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \
+     ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \
+     tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_low_t f;
+} tcf_perfcounter3_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_LOW struct
+ */
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER4_LOW_MASK \
+     (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \
+     ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \
+     tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_low_t f;
+} tcf_perfcounter4_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_LOW struct
+ */
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER5_LOW_MASK \
+     (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \
+     ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \
+     tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_low_t f;
+} tcf_perfcounter5_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_LOW struct
+ */
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER6_LOW_MASK \
+     (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \
+     ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \
+     tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_low_t f;
+} tcf_perfcounter6_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_LOW struct
+ */
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER7_LOW_MASK \
+     (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \
+     ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \
+     tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_low_t f;
+} tcf_perfcounter7_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_LOW struct
+ */
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER8_LOW_MASK \
+     (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \
+     ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \
+     tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_low_t f;
+} tcf_perfcounter8_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_LOW struct
+ */
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER9_LOW_MASK \
+     (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \
+     ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \
+     tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_low_t f;
+} tcf_perfcounter9_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_LOW struct
+ */
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER10_LOW_MASK \
+     (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \
+     ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \
+     tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_low_t f;
+} tcf_perfcounter10_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_LOW struct
+ */
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER11_LOW_MASK \
+     (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \
+     ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \
+     tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_low_t f;
+} tcf_perfcounter11_low_u;
+
+
+/*
+ * TCF_DEBUG struct
+ */
+
+#define TCF_DEBUG_not_MH_TC_rtr_SIZE   1
+#define TCF_DEBUG_TC_MH_send_SIZE      1
+#define TCF_DEBUG_not_FG0_rtr_SIZE     1
+#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1
+#define TCF_DEBUG_TCB_ff_stall_SIZE    1
+#define TCF_DEBUG_TCB_miss_stall_SIZE  1
+#define TCF_DEBUG_TCA_TCB_stall_SIZE   1
+#define TCF_DEBUG_PF0_stall_SIZE       1
+#define TCF_DEBUG_TP0_full_SIZE        1
+#define TCF_DEBUG_TPC_full_SIZE        1
+#define TCF_DEBUG_not_TPC_rtr_SIZE     1
+#define TCF_DEBUG_tca_state_rts_SIZE   1
+#define TCF_DEBUG_tca_rts_SIZE         1
+
+#define TCF_DEBUG_not_MH_TC_rtr_SHIFT  6
+#define TCF_DEBUG_TC_MH_send_SHIFT     7
+#define TCF_DEBUG_not_FG0_rtr_SHIFT    8
+#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12
+#define TCF_DEBUG_TCB_ff_stall_SHIFT   13
+#define TCF_DEBUG_TCB_miss_stall_SHIFT 14
+#define TCF_DEBUG_TCA_TCB_stall_SHIFT  15
+#define TCF_DEBUG_PF0_stall_SHIFT      16
+#define TCF_DEBUG_TP0_full_SHIFT       20
+#define TCF_DEBUG_TPC_full_SHIFT       24
+#define TCF_DEBUG_not_TPC_rtr_SHIFT    25
+#define TCF_DEBUG_tca_state_rts_SHIFT  26
+#define TCF_DEBUG_tca_rts_SHIFT        27
+
+#define TCF_DEBUG_not_MH_TC_rtr_MASK   0x00000040
+#define TCF_DEBUG_TC_MH_send_MASK      0x00000080
+#define TCF_DEBUG_not_FG0_rtr_MASK     0x00000100
+#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000
+#define TCF_DEBUG_TCB_ff_stall_MASK    0x00002000
+#define TCF_DEBUG_TCB_miss_stall_MASK  0x00004000
+#define TCF_DEBUG_TCA_TCB_stall_MASK   0x00008000
+#define TCF_DEBUG_PF0_stall_MASK       0x00010000
+#define TCF_DEBUG_TP0_full_MASK        0x00100000
+#define TCF_DEBUG_TPC_full_MASK        0x01000000
+#define TCF_DEBUG_not_TPC_rtr_MASK     0x02000000
+#define TCF_DEBUG_tca_state_rts_MASK   0x04000000
+#define TCF_DEBUG_tca_rts_MASK         0x08000000
+
+#define TCF_DEBUG_MASK \
+     (TCF_DEBUG_not_MH_TC_rtr_MASK | \
+      TCF_DEBUG_TC_MH_send_MASK | \
+      TCF_DEBUG_not_FG0_rtr_MASK | \
+      TCF_DEBUG_not_TCB_TCO_rtr_MASK | \
+      TCF_DEBUG_TCB_ff_stall_MASK | \
+      TCF_DEBUG_TCB_miss_stall_MASK | \
+      TCF_DEBUG_TCA_TCB_stall_MASK | \
+      TCF_DEBUG_PF0_stall_MASK | \
+      TCF_DEBUG_TP0_full_MASK | \
+      TCF_DEBUG_TPC_full_MASK | \
+      TCF_DEBUG_not_TPC_rtr_MASK | \
+      TCF_DEBUG_tca_state_rts_MASK | \
+      TCF_DEBUG_tca_rts_MASK)
+
+#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \
+     ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \
+      (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \
+      (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \
+      (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \
+      (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \
+      (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \
+      (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \
+      (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \
+      (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \
+      (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \
+      (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \
+      (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \
+      (tca_rts << TCF_DEBUG_tca_rts_SHIFT))
+
+#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_GET_TP0_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_GET_TPC_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_GET_tca_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT)
+
+#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 6;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int                                : 4;
+     } tcf_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 4;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int                                : 6;
+     } tcf_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_debug_t f;
+} tcf_debug_u;
+
+
+/*
+ * TCA_FIFO_DEBUG struct
+ */
+
+#define TCA_FIFO_DEBUG_tp0_full_SIZE   1
+#define TCA_FIFO_DEBUG_tpc_full_SIZE   1
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1
+#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1
+#define TCA_FIFO_DEBUG_FW_full_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1
+#define TCA_FIFO_DEBUG_FW_rts0_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1
+
+#define TCA_FIFO_DEBUG_tp0_full_SHIFT  0
+#define TCA_FIFO_DEBUG_tpc_full_SHIFT  4
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5
+#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6
+#define TCA_FIFO_DEBUG_FW_full_SHIFT   7
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8
+#define TCA_FIFO_DEBUG_FW_rts0_SHIFT   12
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17
+
+#define TCA_FIFO_DEBUG_tp0_full_MASK   0x00000001
+#define TCA_FIFO_DEBUG_tpc_full_MASK   0x00000010
+#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020
+#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040
+#define TCA_FIFO_DEBUG_FW_full_MASK    0x00000080
+#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100
+#define TCA_FIFO_DEBUG_FW_rts0_MASK    0x00001000
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000
+#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000
+
+#define TCA_FIFO_DEBUG_MASK \
+     (TCA_FIFO_DEBUG_tp0_full_MASK | \
+      TCA_FIFO_DEBUG_tpc_full_MASK | \
+      TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \
+      TCA_FIFO_DEBUG_load_tp_fifos_MASK | \
+      TCA_FIFO_DEBUG_FW_full_MASK | \
+      TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \
+      TCA_FIFO_DEBUG_FW_rts0_MASK | \
+      TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \
+      TCA_FIFO_DEBUG_FW_tpc_rts_MASK)
+
+#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \
+     ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \
+      (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \
+      (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \
+      (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \
+      (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \
+      (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \
+      (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \
+      (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \
+      (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT))
+
+#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int                                : 14;
+     } tca_fifo_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int                                : 14;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+     } tca_fifo_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_fifo_debug_t f;
+} tca_fifo_debug_u;
+
+
+/*
+ * TCA_PROBE_DEBUG struct
+ */
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001
+
+#define TCA_PROBE_DEBUG_MASK \
+     (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK)
+
+#define TCA_PROBE_DEBUG(probefilter_stall) \
+     ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT))
+
+#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \
+     ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \
+     tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+          unsigned int                                : 31;
+     } tca_probe_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int                                : 31;
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+     } tca_probe_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_probe_debug_t f;
+} tca_probe_debug_u;
+
+
+/*
+ * TCA_TPC_DEBUG struct
+ */
+
+#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1
+#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1
+
+#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12
+#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13
+
+#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000
+#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000
+
+#define TCA_TPC_DEBUG_MASK \
+     (TCA_TPC_DEBUG_captue_state_rts_MASK | \
+      TCA_TPC_DEBUG_capture_tca_rts_MASK)
+
+#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \
+     ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \
+      (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT))
+
+#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 12;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int                                : 18;
+     } tca_tpc_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 18;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int                                : 12;
+     } tca_tpc_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_tpc_debug_t f;
+} tca_tpc_debug_u;
+
+
+/*
+ * TCB_CORE_DEBUG struct
+ */
+
+#define TCB_CORE_DEBUG_access512_SIZE  1
+#define TCB_CORE_DEBUG_tiled_SIZE      1
+#define TCB_CORE_DEBUG_opcode_SIZE     3
+#define TCB_CORE_DEBUG_format_SIZE     6
+#define TCB_CORE_DEBUG_sector_format_SIZE 5
+#define TCB_CORE_DEBUG_sector_format512_SIZE 3
+
+#define TCB_CORE_DEBUG_access512_SHIFT 0
+#define TCB_CORE_DEBUG_tiled_SHIFT     1
+#define TCB_CORE_DEBUG_opcode_SHIFT    4
+#define TCB_CORE_DEBUG_format_SHIFT    8
+#define TCB_CORE_DEBUG_sector_format_SHIFT 16
+#define TCB_CORE_DEBUG_sector_format512_SHIFT 24
+
+#define TCB_CORE_DEBUG_access512_MASK  0x00000001
+#define TCB_CORE_DEBUG_tiled_MASK      0x00000002
+#define TCB_CORE_DEBUG_opcode_MASK     0x00000070
+#define TCB_CORE_DEBUG_format_MASK     0x00003f00
+#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000
+#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000
+
+#define TCB_CORE_DEBUG_MASK \
+     (TCB_CORE_DEBUG_access512_MASK | \
+      TCB_CORE_DEBUG_tiled_MASK | \
+      TCB_CORE_DEBUG_opcode_MASK | \
+      TCB_CORE_DEBUG_format_MASK | \
+      TCB_CORE_DEBUG_sector_format_MASK | \
+      TCB_CORE_DEBUG_sector_format512_MASK)
+
+#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \
+     ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \
+      (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \
+      (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \
+      (format << TCB_CORE_DEBUG_format_SHIFT) | \
+      (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \
+      (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT))
+
+#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int                                : 2;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 1;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 5;
+     } tcb_core_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int                                : 5;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 2;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+     } tcb_core_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_core_debug_t f;
+} tcb_core_debug_u;
+
+
+/*
+ * TCB_TAG0_DEBUG struct
+ */
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG0_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG0_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG0_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG0_DEBUG_MASK \
+     (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG0_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG0_DEBUG_miss_stall_MASK | \
+      TCB_TAG0_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG0_DEBUG_max_misses_MASK)
+
+#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+     } tcb_tag0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag0_debug_t f;
+} tcb_tag0_debug_u;
+
+
+/*
+ * TCB_TAG1_DEBUG struct
+ */
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG1_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG1_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG1_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG1_DEBUG_MASK \
+     (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG1_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG1_DEBUG_miss_stall_MASK | \
+      TCB_TAG1_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG1_DEBUG_max_misses_MASK)
+
+#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+     } tcb_tag1_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag1_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag1_debug_t f;
+} tcb_tag1_debug_u;
+
+
+/*
+ * TCB_TAG2_DEBUG struct
+ */
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG2_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG2_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG2_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG2_DEBUG_MASK \
+     (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG2_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG2_DEBUG_miss_stall_MASK | \
+      TCB_TAG2_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG2_DEBUG_max_misses_MASK)
+
+#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+     } tcb_tag2_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag2_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag2_debug_t f;
+} tcb_tag2_debug_u;
+
+
+/*
+ * TCB_TAG3_DEBUG struct
+ */
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG3_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG3_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG3_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG3_DEBUG_MASK \
+     (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG3_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG3_DEBUG_miss_stall_MASK | \
+      TCB_TAG3_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG3_DEBUG_max_misses_MASK)
+
+#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+     } tcb_tag3_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag3_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag3_debug_t f;
+} tcb_tag3_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \
+     (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \
+     ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \
+      (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \
+      (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \
+      (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \
+      (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \
+      (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \
+      (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \
+      (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT))
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int                                : 3;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int                                : 3;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_sector_walker0_debug_t f;
+} tcb_fetch_gen_sector_walker0_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_WALKER_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \
+     (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \
+     ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \
+      (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \
+      (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \
+      (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \
+      (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \
+      (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT))
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 4;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int                                : 12;
+     } tcb_fetch_gen_walker_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 12;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int                                : 4;
+     } tcb_fetch_gen_walker_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_walker_debug_t f;
+} tcb_fetch_gen_walker_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_PIPE0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \
+     (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \
+     ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \
+      (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \
+      (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \
+      (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \
+      (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \
+      (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \
+      (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \
+      (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \
+      (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \
+      (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \
+      (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT))
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_pipe0_debug_t f;
+} tcb_fetch_gen_pipe0_debug_u;
+
+
+/*
+ * TCD_INPUT0_DEBUG struct
+ */
+
+#define TCD_INPUT0_DEBUG_empty_SIZE    1
+#define TCD_INPUT0_DEBUG_full_SIZE     1
+#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_cnt_q1_SIZE   2
+#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_ip_send_SIZE  1
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1
+
+#define TCD_INPUT0_DEBUG_empty_SHIFT   16
+#define TCD_INPUT0_DEBUG_full_SHIFT    17
+#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20
+#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT  21
+#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23
+#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26
+
+#define TCD_INPUT0_DEBUG_empty_MASK    0x00010000
+#define TCD_INPUT0_DEBUG_full_MASK     0x00020000
+#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000
+#define TCD_INPUT0_DEBUG_cnt_q1_MASK   0x00600000
+#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000
+#define TCD_INPUT0_DEBUG_ip_send_MASK  0x01000000
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000
+#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000
+
+#define TCD_INPUT0_DEBUG_MASK \
+     (TCD_INPUT0_DEBUG_empty_MASK | \
+      TCD_INPUT0_DEBUG_full_MASK | \
+      TCD_INPUT0_DEBUG_valid_q1_MASK | \
+      TCD_INPUT0_DEBUG_cnt_q1_MASK | \
+      TCD_INPUT0_DEBUG_last_send_q1_MASK | \
+      TCD_INPUT0_DEBUG_ip_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_busy_MASK)
+
+#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \
+     ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \
+      (full << TCD_INPUT0_DEBUG_full_SHIFT) | \
+      (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \
+      (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \
+      (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \
+      (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \
+      (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \
+      (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT))
+
+#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 16;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int                                : 2;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int                                : 5;
+     } tcd_input0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 5;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int                                : 2;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int                                : 16;
+     } tcd_input0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_input0_debug_t f;
+} tcd_input0_debug_u;
+
+
+/*
+ * TCD_DEGAMMA_DEBUG struct
+ */
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040
+
+#define TCD_DEGAMMA_DEBUG_MASK \
+     (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK)
+
+#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \
+     ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \
+      (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \
+      (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \
+      (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \
+      (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \
+      (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT))
+
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int                                : 25;
+     } tcd_degamma_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int                                : 25;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+     } tcd_degamma_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_degamma_debug_t f;
+} tcd_degamma_debug_u;
+
+
+/*
+ * TCD_DXTMUX_SCTARB_DEBUG struct
+ */
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000
+
+#define TCD_DXTMUX_SCTARB_DEBUG_MASK \
+     (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK)
+
+#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \
+     ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \
+      (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \
+      (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \
+      (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \
+      (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \
+      (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \
+      (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \
+      (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \
+      (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT))
+
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 9;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int                                : 2;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 2;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int                                : 9;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtmux_sctarb_debug_t f;
+} tcd_dxtmux_sctarb_debug_u;
+
+
+/*
+ * TCD_DXTC_ARB_DEBUG struct
+ */
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4
+#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010
+#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000
+
+#define TCD_DXTC_ARB_DEBUG_MASK \
+     (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \
+      TCD_DXTC_ARB_DEBUG_pstate_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK)
+
+#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \
+     ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \
+      (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \
+      (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \
+      (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \
+      (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \
+      (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \
+      (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \
+      (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \
+      (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT))
+
+#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int                                : 4;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+     } tcd_dxtc_arb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int                                : 4;
+     } tcd_dxtc_arb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtc_arb_debug_t f;
+} tcd_dxtc_arb_debug_u;
+
+
+/*
+ * TCD_STALLS_DEBUG struct
+ */
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000
+#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000
+
+#define TCD_STALLS_DEBUG_MASK \
+     (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_incoming_rtr_MASK)
+
+#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \
+     ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \
+      (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \
+      (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \
+      (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \
+      (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \
+      (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT))
+
+#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int                                : 10;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+     } tcd_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int                                : 10;
+     } tcd_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_stalls_debug_t f;
+} tcd_stalls_debug_u;
+
+
+/*
+ * TCO_STALLS_DEBUG struct
+ */
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080
+
+#define TCO_STALLS_DEBUG_MASK \
+     (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK)
+
+#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \
+     ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \
+      (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \
+      (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT))
+
+#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 5;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int                                : 24;
+     } tco_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 24;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int                                : 5;
+     } tco_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_stalls_debug_t f;
+} tco_stalls_debug_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG0 struct
+ */
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1
+#define TCO_QUAD0_DEBUG0_busy_SIZE     1
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16
+#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29
+#define TCO_QUAD0_DEBUG0_busy_SHIFT    30
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000
+#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000
+#define TCO_QUAD0_DEBUG0_busy_MASK     0x40000000
+
+#define TCO_QUAD0_DEBUG0_MASK \
+     (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \
+      TCO_QUAD0_DEBUG0_read_cache_q_MASK | \
+      TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \
+      TCO_QUAD0_DEBUG0_busy_MASK)
+
+#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \
+     ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \
+      (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \
+      (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \
+      (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \
+      (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \
+      (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \
+      (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \
+      (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \
+      (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \
+      (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \
+      (busy << TCO_QUAD0_DEBUG0_busy_SHIFT))
+
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int                                : 2;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int                                : 1;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 2;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+     } tco_quad0_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug0_t f;
+} tco_quad0_debug0_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG1 struct
+ */
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_empty_SIZE    1
+#define TCO_QUAD0_DEBUG1_full_SIZE     1
+#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0
+#define TCO_QUAD0_DEBUG1_empty_SHIFT   1
+#define TCO_QUAD0_DEBUG1_full_SHIFT    2
+#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001
+#define TCO_QUAD0_DEBUG1_empty_MASK    0x00000002
+#define TCO_QUAD0_DEBUG1_full_MASK     0x00000004
+#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800
+#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000
+#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000
+
+#define TCO_QUAD0_DEBUG1_MASK \
+     (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_empty_MASK | \
+      TCO_QUAD0_DEBUG1_full_MASK | \
+      TCO_QUAD0_DEBUG1_write_enable_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \
+      TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \
+      TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK)
+
+#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \
+     ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \
+      (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \
+      (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \
+      (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \
+      (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \
+      (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \
+      (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \
+      (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \
+      (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \
+      (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \
+      (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \
+      (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \
+      (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT))
+
+#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int                                : 2;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int                                : 1;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int                                : 2;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+     } tco_quad0_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug1_t f;
+} tco_quad0_debug1_u;
+
+
+#endif
+
+
+#if !defined (_TC_FIDDLE_H)
+#define _TC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  tc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_SC_FIDDLE_H)
+#define _SC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_BC_FIDDLE_H)
+#define _BC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  bc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * RB_SURFACE_INFO struct
+ */
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff
+#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000
+
+#define RB_SURFACE_INFO_MASK \
+     (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \
+      RB_SURFACE_INFO_MSAA_SAMPLES_MASK)
+
+#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \
+     ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \
+      (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT))
+
+#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int                                : 16;
+     } rb_surface_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int                                : 16;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+     } rb_surface_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_surface_info_t f;
+} rb_surface_info_u;
+
+
+/*
+ * RB_COLOR_INFO struct
+ */
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2
+#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1
+#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2
+#define RB_COLOR_INFO_COLOR_SWAP_SIZE  2
+#define RB_COLOR_INFO_COLOR_BASE_SIZE  20
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4
+#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6
+#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7
+#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9
+#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12
+
+#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030
+#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040
+#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180
+#define RB_COLOR_INFO_COLOR_SWAP_MASK  0x00000600
+#define RB_COLOR_INFO_COLOR_BASE_MASK  0xfffff000
+
+#define RB_COLOR_INFO_MASK \
+     (RB_COLOR_INFO_COLOR_FORMAT_MASK | \
+      RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \
+      RB_COLOR_INFO_COLOR_LINEAR_MASK | \
+      RB_COLOR_INFO_COLOR_ENDIAN_MASK | \
+      RB_COLOR_INFO_COLOR_SWAP_MASK | \
+      RB_COLOR_INFO_COLOR_BASE_MASK)
+
+#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \
+     ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \
+      (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \
+      (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \
+      (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \
+      (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \
+      (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT))
+
+#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+     } rb_color_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+     } rb_color_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_info_t f;
+} rb_color_info_u;
+
+
+/*
+ * RB_DEPTH_INFO struct
+ */
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1
+#define RB_DEPTH_INFO_DEPTH_BASE_SIZE  20
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0
+#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001
+#define RB_DEPTH_INFO_DEPTH_BASE_MASK  0xfffff000
+
+#define RB_DEPTH_INFO_MASK \
+     (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \
+      RB_DEPTH_INFO_DEPTH_BASE_MASK)
+
+#define RB_DEPTH_INFO(depth_format, depth_base) \
+     ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \
+      (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT))
+
+#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+     } rb_depth_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+     } rb_depth_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_info_t f;
+} rb_depth_info_u;
+
+
+/*
+ * RB_STENCILREFMASK struct
+ */
+
+#define RB_STENCILREFMASK_STENCILREF_SIZE 8
+#define RB_STENCILREFMASK_STENCILMASK_SIZE 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8
+#define RB_STENCILREFMASK_RESERVED0_SIZE 1
+#define RB_STENCILREFMASK_RESERVED1_SIZE 1
+
+#define RB_STENCILREFMASK_STENCILREF_SHIFT 0
+#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16
+#define RB_STENCILREFMASK_RESERVED0_SHIFT 24
+#define RB_STENCILREFMASK_RESERVED1_SHIFT 25
+
+#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff
+#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00
+#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000
+#define RB_STENCILREFMASK_RESERVED0_MASK 0x01000000
+#define RB_STENCILREFMASK_RESERVED1_MASK 0x02000000
+
+#define RB_STENCILREFMASK_MASK \
+     (RB_STENCILREFMASK_STENCILREF_MASK | \
+      RB_STENCILREFMASK_STENCILMASK_MASK | \
+      RB_STENCILREFMASK_STENCILWRITEMASK_MASK | \
+      RB_STENCILREFMASK_RESERVED0_MASK | \
+      RB_STENCILREFMASK_RESERVED1_MASK)
+
+#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask, reserved0, reserved1) \
+     ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \
+      (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \
+      (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) | \
+      (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) | \
+      (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT))
+
+#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_RESERVED0(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED0_MASK) >> RB_STENCILREFMASK_RESERVED0_SHIFT)
+#define RB_STENCILREFMASK_GET_RESERVED1(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED1_MASK) >> RB_STENCILREFMASK_RESERVED1_SHIFT)
+
+#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_RESERVED0(rb_stencilrefmask_reg, reserved0) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED0_MASK) | (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT)
+#define RB_STENCILREFMASK_SET_RESERVED1(rb_stencilrefmask_reg, reserved1) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED1_MASK) | (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int reserved0                      : RB_STENCILREFMASK_RESERVED0_SIZE;
+          unsigned int reserved1                      : RB_STENCILREFMASK_RESERVED1_SIZE;
+          unsigned int                                : 6;
+     } rb_stencilrefmask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int                                : 6;
+          unsigned int reserved1                      : RB_STENCILREFMASK_RESERVED1_SIZE;
+          unsigned int reserved0                      : RB_STENCILREFMASK_RESERVED0_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+     } rb_stencilrefmask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_t f;
+} rb_stencilrefmask_u;
+
+
+/*
+ * RB_ALPHA_REF struct
+ */
+
+#define RB_ALPHA_REF_ALPHA_REF_SIZE    32
+
+#define RB_ALPHA_REF_ALPHA_REF_SHIFT   0
+
+#define RB_ALPHA_REF_ALPHA_REF_MASK    0xffffffff
+
+#define RB_ALPHA_REF_MASK \
+     (RB_ALPHA_REF_ALPHA_REF_MASK)
+
+#define RB_ALPHA_REF(alpha_ref) \
+     ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT))
+
+#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \
+     ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \
+     rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_alpha_ref_t f;
+} rb_alpha_ref_u;
+
+
+/*
+ * RB_COLOR_MASK struct
+ */
+
+#define RB_COLOR_MASK_WRITE_RED_SIZE   1
+#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1
+#define RB_COLOR_MASK_WRITE_BLUE_SIZE  1
+#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1
+#define RB_COLOR_MASK_RESERVED2_SIZE   1
+#define RB_COLOR_MASK_RESERVED3_SIZE   1
+
+#define RB_COLOR_MASK_WRITE_RED_SHIFT  0
+#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1
+#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2
+#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3
+#define RB_COLOR_MASK_RESERVED2_SHIFT  4
+#define RB_COLOR_MASK_RESERVED3_SHIFT  5
+
+#define RB_COLOR_MASK_WRITE_RED_MASK   0x00000001
+#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002
+#define RB_COLOR_MASK_WRITE_BLUE_MASK  0x00000004
+#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008
+#define RB_COLOR_MASK_RESERVED2_MASK   0x00000010
+#define RB_COLOR_MASK_RESERVED3_MASK   0x00000020
+
+#define RB_COLOR_MASK_MASK \
+     (RB_COLOR_MASK_WRITE_RED_MASK | \
+      RB_COLOR_MASK_WRITE_GREEN_MASK | \
+      RB_COLOR_MASK_WRITE_BLUE_MASK | \
+      RB_COLOR_MASK_WRITE_ALPHA_MASK | \
+      RB_COLOR_MASK_RESERVED2_MASK | \
+      RB_COLOR_MASK_RESERVED3_MASK)
+
+#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha, reserved2, reserved3) \
+     ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \
+      (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \
+      (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \
+      (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) | \
+      (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) | \
+      (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT))
+
+#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+#define RB_COLOR_MASK_GET_RESERVED2(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_RESERVED2_MASK) >> RB_COLOR_MASK_RESERVED2_SHIFT)
+#define RB_COLOR_MASK_GET_RESERVED3(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_RESERVED3_MASK) >> RB_COLOR_MASK_RESERVED3_SHIFT)
+
+#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+#define RB_COLOR_MASK_SET_RESERVED2(rb_color_mask_reg, reserved2) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED2_MASK) | (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT)
+#define RB_COLOR_MASK_SET_RESERVED3(rb_color_mask_reg, reserved3) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED3_MASK) | (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int reserved2                      : RB_COLOR_MASK_RESERVED2_SIZE;
+          unsigned int reserved3                      : RB_COLOR_MASK_RESERVED3_SIZE;
+          unsigned int                                : 26;
+     } rb_color_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int                                : 26;
+          unsigned int reserved3                      : RB_COLOR_MASK_RESERVED3_SIZE;
+          unsigned int reserved2                      : RB_COLOR_MASK_RESERVED2_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+     } rb_color_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_mask_t f;
+} rb_color_mask_u;
+
+
+/*
+ * RB_BLEND_RED struct
+ */
+
+#define RB_BLEND_RED_BLEND_RED_SIZE    8
+
+#define RB_BLEND_RED_BLEND_RED_SHIFT   0
+
+#define RB_BLEND_RED_BLEND_RED_MASK    0x000000ff
+
+#define RB_BLEND_RED_MASK \
+     (RB_BLEND_RED_BLEND_RED_MASK)
+
+#define RB_BLEND_RED(blend_red) \
+     ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT))
+
+#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \
+     ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \
+     rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_red_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int                                : 24;
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+     } rb_blend_red_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_red_t f;
+} rb_blend_red_u;
+
+
+/*
+ * RB_BLEND_GREEN struct
+ */
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0
+
+#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff
+
+#define RB_BLEND_GREEN_MASK \
+     (RB_BLEND_GREEN_BLEND_GREEN_MASK)
+
+#define RB_BLEND_GREEN(blend_green) \
+     ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT))
+
+#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \
+     ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \
+     rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_green_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int                                : 24;
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+     } rb_blend_green_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_green_t f;
+} rb_blend_green_u;
+
+
+/*
+ * RB_BLEND_BLUE struct
+ */
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SIZE  8
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0
+
+#define RB_BLEND_BLUE_BLEND_BLUE_MASK  0x000000ff
+
+#define RB_BLEND_BLUE_MASK \
+     (RB_BLEND_BLUE_BLEND_BLUE_MASK)
+
+#define RB_BLEND_BLUE(blend_blue) \
+     ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT))
+
+#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \
+     ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \
+     rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_blue_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int                                : 24;
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+     } rb_blend_blue_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_blue_t f;
+} rb_blend_blue_u;
+
+
+/*
+ * RB_BLEND_ALPHA struct
+ */
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff
+
+#define RB_BLEND_ALPHA_MASK \
+     (RB_BLEND_ALPHA_BLEND_ALPHA_MASK)
+
+#define RB_BLEND_ALPHA(blend_alpha) \
+     ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT))
+
+#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \
+     ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \
+     rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_alpha_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int                                : 24;
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+     } rb_blend_alpha_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_alpha_t f;
+} rb_blend_alpha_u;
+
+
+/*
+ * RB_FOG_COLOR struct
+ */
+
+#define RB_FOG_COLOR_FOG_RED_SIZE      8
+#define RB_FOG_COLOR_FOG_GREEN_SIZE    8
+#define RB_FOG_COLOR_FOG_BLUE_SIZE     8
+
+#define RB_FOG_COLOR_FOG_RED_SHIFT     0
+#define RB_FOG_COLOR_FOG_GREEN_SHIFT   8
+#define RB_FOG_COLOR_FOG_BLUE_SHIFT    16
+
+#define RB_FOG_COLOR_FOG_RED_MASK      0x000000ff
+#define RB_FOG_COLOR_FOG_GREEN_MASK    0x0000ff00
+#define RB_FOG_COLOR_FOG_BLUE_MASK     0x00ff0000
+
+#define RB_FOG_COLOR_MASK \
+     (RB_FOG_COLOR_FOG_RED_MASK | \
+      RB_FOG_COLOR_FOG_GREEN_MASK | \
+      RB_FOG_COLOR_FOG_BLUE_MASK)
+
+#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \
+     ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \
+      (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \
+      (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT))
+
+#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int                                : 8;
+     } rb_fog_color_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int                                : 8;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+     } rb_fog_color_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_fog_color_t f;
+} rb_fog_color_u;
+
+
+/*
+ * RB_STENCILREFMASK_BF struct
+ */
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_RESERVED4_SIZE 1
+#define RB_STENCILREFMASK_BF_RESERVED5_SIZE 1
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16
+#define RB_STENCILREFMASK_BF_RESERVED4_SHIFT 24
+#define RB_STENCILREFMASK_BF_RESERVED5_SHIFT 25
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000
+#define RB_STENCILREFMASK_BF_RESERVED4_MASK 0x01000000
+#define RB_STENCILREFMASK_BF_RESERVED5_MASK 0x02000000
+
+#define RB_STENCILREFMASK_BF_MASK \
+     (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_RESERVED4_MASK | \
+      RB_STENCILREFMASK_BF_RESERVED5_MASK)
+
+#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf, reserved4, reserved5) \
+     ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \
+      (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \
+      (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) | \
+      (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) | \
+      (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT))
+
+#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_RESERVED4(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED4_MASK) >> RB_STENCILREFMASK_BF_RESERVED4_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_RESERVED5(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED5_MASK) >> RB_STENCILREFMASK_BF_RESERVED5_SHIFT)
+
+#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_RESERVED4(rb_stencilrefmask_bf_reg, reserved4) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED4_MASK) | (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_RESERVED5(rb_stencilrefmask_bf_reg, reserved5) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED5_MASK) | (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int reserved4                      : RB_STENCILREFMASK_BF_RESERVED4_SIZE;
+          unsigned int reserved5                      : RB_STENCILREFMASK_BF_RESERVED5_SIZE;
+          unsigned int                                : 6;
+     } rb_stencilrefmask_bf_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int                                : 6;
+          unsigned int reserved5                      : RB_STENCILREFMASK_BF_RESERVED5_SIZE;
+          unsigned int reserved4                      : RB_STENCILREFMASK_BF_RESERVED4_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+     } rb_stencilrefmask_bf_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_bf_t f;
+} rb_stencilrefmask_bf_u;
+
+
+/*
+ * RB_DEPTHCONTROL struct
+ */
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_Z_ENABLE_SIZE  1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_ZFUNC_SIZE     3
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0
+#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3
+#define RB_DEPTHCONTROL_ZFUNC_SHIFT    4
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7
+#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8
+#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11
+#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14
+#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001
+#define RB_DEPTHCONTROL_Z_ENABLE_MASK  0x00000002
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008
+#define RB_DEPTHCONTROL_ZFUNC_MASK     0x00000070
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080
+#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700
+#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800
+#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000
+#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000
+
+#define RB_DEPTHCONTROL_MASK \
+     (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_ZFUNC_MASK | \
+      RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK)
+
+#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \
+     ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \
+      (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \
+      (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \
+      (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \
+      (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \
+      (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \
+      (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \
+      (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \
+      (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \
+      (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \
+      (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \
+      (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \
+      (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \
+      (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT))
+
+#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+     } rb_depthcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+     } rb_depthcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depthcontrol_t f;
+} rb_depthcontrol_u;
+
+
+/*
+ * RB_BLENDCONTROL struct
+ */
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1
+#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29
+#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000
+#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000
+
+#define RB_BLENDCONTROL_MASK \
+     (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_MASK)
+
+#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \
+     ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \
+      (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \
+      (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \
+      (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \
+      (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \
+      (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \
+      (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \
+      (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT))
+
+#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int                                : 1;
+     } rb_blendcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int                                : 1;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+     } rb_blendcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blendcontrol_t f;
+} rb_blendcontrol_u;
+
+
+/*
+ * RB_COLORCONTROL struct
+ */
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1
+#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1
+#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1
+#define RB_COLORCONTROL_ROP_CODE_SIZE  4
+#define RB_COLORCONTROL_DITHER_MODE_SIZE 2
+#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2
+#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4
+#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5
+#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7
+#define RB_COLORCONTROL_ROP_CODE_SHIFT 8
+#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12
+#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14
+#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30
+
+#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010
+#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020
+#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080
+#define RB_COLORCONTROL_ROP_CODE_MASK  0x00000f00
+#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000
+#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000
+#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000
+
+#define RB_COLORCONTROL_MASK \
+     (RB_COLORCONTROL_ALPHA_FUNC_MASK | \
+      RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \
+      RB_COLORCONTROL_BLEND_DISABLE_MASK | \
+      RB_COLORCONTROL_FOG_ENABLE_MASK | \
+      RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \
+      RB_COLORCONTROL_ROP_CODE_MASK | \
+      RB_COLORCONTROL_DITHER_MODE_MASK | \
+      RB_COLORCONTROL_DITHER_TYPE_MASK | \
+      RB_COLORCONTROL_PIXEL_FOG_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK)
+
+#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \
+     ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \
+      (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \
+      (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \
+      (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \
+      (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \
+      (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \
+      (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \
+      (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \
+      (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \
+      (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \
+      (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \
+      (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \
+      (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \
+      (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT))
+
+#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int                                : 7;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+     } rb_colorcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int                                : 7;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+     } rb_colorcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_colorcontrol_t f;
+} rb_colorcontrol_u;
+
+
+/*
+ * RB_MODECONTROL struct
+ */
+
+#define RB_MODECONTROL_EDRAM_MODE_SIZE 3
+
+#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0
+
+#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007
+
+#define RB_MODECONTROL_MASK \
+     (RB_MODECONTROL_EDRAM_MODE_MASK)
+
+#define RB_MODECONTROL(edram_mode) \
+     ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT))
+
+#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \
+     ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \
+     rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+          unsigned int                                : 29;
+     } rb_modecontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int                                : 29;
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+     } rb_modecontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_modecontrol_t f;
+} rb_modecontrol_u;
+
+
+/*
+ * RB_COLOR_DEST_MASK struct
+ */
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff
+
+#define RB_COLOR_DEST_MASK_MASK \
+     (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK)
+
+#define RB_COLOR_DEST_MASK(color_dest_mask) \
+     ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT))
+
+#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \
+     ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \
+     rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_dest_mask_t f;
+} rb_color_dest_mask_u;
+
+
+/*
+ * RB_COPY_CONTROL struct
+ */
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1
+#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3
+#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008
+#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0
+
+#define RB_COPY_CONTROL_MASK \
+     (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \
+      RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \
+      RB_COPY_CONTROL_CLEAR_MASK_MASK)
+
+#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \
+     ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \
+      (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \
+      (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT))
+
+#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int                                : 24;
+     } rb_copy_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int                                : 24;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+     } rb_copy_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_control_t f;
+} rb_copy_control_u;
+
+
+/*
+ * RB_COPY_DEST_BASE struct
+ */
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000
+
+#define RB_COPY_DEST_BASE_MASK \
+     (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK)
+
+#define RB_COPY_DEST_BASE(copy_dest_base) \
+     ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT))
+
+#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \
+     ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \
+     rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int                                : 12;
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+     } rb_copy_dest_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+          unsigned int                                : 12;
+     } rb_copy_dest_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_base_t f;
+} rb_copy_dest_base_u;
+
+
+/*
+ * RB_COPY_DEST_PITCH struct
+ */
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff
+
+#define RB_COPY_DEST_PITCH_MASK \
+     (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK)
+
+#define RB_COPY_DEST_PITCH(copy_dest_pitch) \
+     ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT))
+
+#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \
+     ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \
+     rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+          unsigned int                                : 23;
+     } rb_copy_dest_pitch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int                                : 23;
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+     } rb_copy_dest_pitch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pitch_t f;
+} rb_copy_dest_pitch_u;
+
+
+/*
+ * RB_COPY_DEST_INFO struct
+ */
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000
+
+#define RB_COPY_DEST_INFO_MASK \
+     (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK)
+
+#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \
+     ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \
+      (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \
+      (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \
+      (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \
+      (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \
+      (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \
+      (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \
+      (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \
+      (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \
+      (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT))
+
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int                                : 14;
+     } rb_copy_dest_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int                                : 14;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+     } rb_copy_dest_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_info_t f;
+} rb_copy_dest_info_u;
+
+
+/*
+ * RB_COPY_DEST_PIXEL_OFFSET struct
+ */
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000
+
+#define RB_COPY_DEST_PIXEL_OFFSET_MASK \
+     (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \
+      RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK)
+
+#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \
+     ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \
+      (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT))
+
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int                                : 6;
+     } rb_copy_dest_pixel_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int                                : 6;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+     } rb_copy_dest_pixel_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pixel_offset_t f;
+} rb_copy_dest_pixel_offset_u;
+
+
+/*
+ * RB_DEPTH_CLEAR struct
+ */
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff
+
+#define RB_DEPTH_CLEAR_MASK \
+     (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK)
+
+#define RB_DEPTH_CLEAR(depth_clear) \
+     ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT))
+
+#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \
+     ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \
+     rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_clear_t f;
+} rb_depth_clear_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_CTL struct
+ */
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002
+
+#define RB_SAMPLE_COUNT_CTL_MASK \
+     (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \
+      RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK)
+
+#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \
+     ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \
+      (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT))
+
+#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int                                : 30;
+     } rb_sample_count_ctl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int                                : 30;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+     } rb_sample_count_ctl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_ctl_t f;
+} rb_sample_count_ctl_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_ADDR struct
+ */
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff
+
+#define RB_SAMPLE_COUNT_ADDR_MASK \
+     (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK)
+
+#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \
+     ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT))
+
+#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \
+     ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \
+     rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_addr_t f;
+} rb_sample_count_addr_u;
+
+
+/*
+ * RB_BC_CONTROL struct
+ */
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1
+#define RB_BC_CONTROL_CRC_MODE_SIZE    1
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1
+#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_CRC_SYSTEM_SIZE  1
+#define RB_BC_CONTROL_RESERVED6_SIZE   1
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14
+#define RB_BC_CONTROL_CRC_MODE_SHIFT   15
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16
+#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29
+#define RB_BC_CONTROL_CRC_SYSTEM_SHIFT 30
+#define RB_BC_CONTROL_RESERVED6_SHIFT  31
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000
+#define RB_BC_CONTROL_CRC_MODE_MASK    0x00008000
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000
+#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000
+#define RB_BC_CONTROL_CRC_SYSTEM_MASK  0x40000000
+#define RB_BC_CONTROL_RESERVED6_MASK   0x80000000
+
+#define RB_BC_CONTROL_MASK \
+     (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \
+      RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \
+      RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \
+      RB_BC_CONTROL_CRC_MODE_MASK | \
+      RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \
+      RB_BC_CONTROL_DISABLE_ACCUM_MASK | \
+      RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \
+      RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_CRC_SYSTEM_MASK | \
+      RB_BC_CONTROL_RESERVED6_MASK)
+
+#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, crc_system, reserved6) \
+     ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \
+      (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \
+      (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \
+      (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \
+      (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \
+      (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \
+      (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \
+      (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \
+      (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \
+      (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \
+      (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \
+      (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \
+      (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \
+      (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \
+      (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \
+      (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \
+      (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \
+      (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) | \
+      (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT))
+
+#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_SYSTEM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_SYSTEM_MASK) >> RB_BC_CONTROL_CRC_SYSTEM_SHIFT)
+#define RB_BC_CONTROL_GET_RESERVED6(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_RESERVED6_MASK) >> RB_BC_CONTROL_RESERVED6_SHIFT)
+
+#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_SYSTEM(rb_bc_control_reg, crc_system) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_SYSTEM_MASK) | (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT)
+#define RB_BC_CONTROL_SET_RESERVED6(rb_bc_control_reg, reserved6) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED6_MASK) | (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int                                : 1;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int crc_system                     : RB_BC_CONTROL_CRC_SYSTEM_SIZE;
+          unsigned int reserved6                      : RB_BC_CONTROL_RESERVED6_SIZE;
+     } rb_bc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int reserved6                      : RB_BC_CONTROL_RESERVED6_SIZE;
+          unsigned int crc_system                     : RB_BC_CONTROL_CRC_SYSTEM_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+     } rb_bc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_control_t f;
+} rb_bc_control_u;
+
+
+/*
+ * RB_EDRAM_INFO struct
+ */
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE  4
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2
+#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4
+#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_MASK  0x0000000f
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030
+#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000
+
+#define RB_EDRAM_INFO_MASK \
+     (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \
+      RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \
+      RB_EDRAM_INFO_EDRAM_RANGE_MASK)
+
+#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \
+     ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \
+      (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \
+      (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT))
+
+#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+     } rb_edram_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+     } rb_edram_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_edram_info_t f;
+} rb_edram_info_u;
+
+
+/*
+ * RB_CRC_RD_PORT struct
+ */
+
+#define RB_CRC_RD_PORT_CRC_DATA_SIZE   32
+
+#define RB_CRC_RD_PORT_CRC_DATA_SHIFT  0
+
+#define RB_CRC_RD_PORT_CRC_DATA_MASK   0xffffffff
+
+#define RB_CRC_RD_PORT_MASK \
+     (RB_CRC_RD_PORT_CRC_DATA_MASK)
+
+#define RB_CRC_RD_PORT(crc_data) \
+     ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT))
+
+#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \
+     ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \
+     rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_rd_port_t f;
+} rb_crc_rd_port_u;
+
+
+/*
+ * RB_CRC_CONTROL struct
+ */
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001
+
+#define RB_CRC_CONTROL_MASK \
+     (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK)
+
+#define RB_CRC_CONTROL(crc_rd_advance) \
+     ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT))
+
+#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \
+     ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \
+     rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+          unsigned int                                : 31;
+     } rb_crc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int                                : 31;
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+     } rb_crc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_control_t f;
+} rb_crc_control_u;
+
+
+/*
+ * RB_CRC_MASK struct
+ */
+
+#define RB_CRC_MASK_CRC_MASK_SIZE      32
+
+#define RB_CRC_MASK_CRC_MASK_SHIFT     0
+
+#define RB_CRC_MASK_CRC_MASK_MASK      0xffffffff
+
+#define RB_CRC_MASK_MASK \
+     (RB_CRC_MASK_CRC_MASK_MASK)
+
+#define RB_CRC_MASK(crc_mask) \
+     ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT))
+
+#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \
+     ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \
+     rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_mask_t f;
+} rb_crc_mask_u;
+
+
+/*
+ * RB_PERFCOUNTER0_SELECT struct
+ */
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define RB_PERFCOUNTER0_SELECT_MASK \
+     (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define RB_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \
+     ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \
+     rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } rb_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } rb_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_select_t f;
+} rb_perfcounter0_select_u;
+
+
+/*
+ * RB_PERFCOUNTER0_LOW struct
+ */
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define RB_PERFCOUNTER0_LOW_MASK \
+     (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \
+     ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \
+     rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_low_t f;
+} rb_perfcounter0_low_u;
+
+
+/*
+ * RB_PERFCOUNTER0_HI struct
+ */
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define RB_PERFCOUNTER0_HI_MASK \
+     (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \
+     ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \
+     rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } rb_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } rb_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_hi_t f;
+} rb_perfcounter0_hi_u;
+
+
+/*
+ * RB_TOTAL_SAMPLES struct
+ */
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff
+
+#define RB_TOTAL_SAMPLES_MASK \
+     (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK)
+
+#define RB_TOTAL_SAMPLES(total_samples) \
+     ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT))
+
+#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \
+     ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \
+     rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_total_samples_t f;
+} rb_total_samples_u;
+
+
+/*
+ * RB_ZPASS_SAMPLES struct
+ */
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff
+
+#define RB_ZPASS_SAMPLES_MASK \
+     (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK)
+
+#define RB_ZPASS_SAMPLES(zpass_samples) \
+     ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT))
+
+#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \
+     ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \
+     rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zpass_samples_t f;
+} rb_zpass_samples_u;
+
+
+/*
+ * RB_ZFAIL_SAMPLES struct
+ */
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_ZFAIL_SAMPLES_MASK \
+     (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK)
+
+#define RB_ZFAIL_SAMPLES(zfail_samples) \
+     ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT))
+
+#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \
+     ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \
+     rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zfail_samples_t f;
+} rb_zfail_samples_u;
+
+
+/*
+ * RB_SFAIL_SAMPLES struct
+ */
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_SFAIL_SAMPLES_MASK \
+     (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK)
+
+#define RB_SFAIL_SAMPLES(sfail_samples) \
+     ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT))
+
+#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \
+     ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \
+     rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sfail_samples_t f;
+} rb_sfail_samples_u;
+
+
+/*
+ * RB_DEBUG_0 struct
+ */
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE  1
+#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE  1
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1
+#define RB_DEBUG_0_C_REQ_FULL_SIZE     1
+#define RB_DEBUG_0_C_MASK_FULL_SIZE    1
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7
+#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8
+#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17
+#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18
+#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25
+#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26
+#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28
+#define RB_DEBUG_0_C_REQ_FULL_SHIFT    29
+#define RB_DEBUG_0_C_MASK_FULL_SHIFT   30
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020
+#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK  0x00000040
+#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK  0x00000080
+#define RB_DEBUG_0_RDREQ_C1_FULL_MASK  0x00000100
+#define RB_DEBUG_0_RDREQ_C0_FULL_MASK  0x00000200
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000
+#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK  0x00010000
+#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK  0x00020000
+#define RB_DEBUG_0_WRREQ_C1_FULL_MASK  0x00040000
+#define RB_DEBUG_0_WRREQ_C0_FULL_MASK  0x00080000
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000
+#define RB_DEBUG_0_C_SX_LAT_FULL_MASK  0x04000000
+#define RB_DEBUG_0_C_SX_CMD_FULL_MASK  0x08000000
+#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000
+#define RB_DEBUG_0_C_REQ_FULL_MASK     0x20000000
+#define RB_DEBUG_0_C_MASK_FULL_MASK    0x40000000
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000
+
+#define RB_DEBUG_0_MASK \
+     (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_C_SX_LAT_FULL_MASK | \
+      RB_DEBUG_0_C_SX_CMD_FULL_MASK | \
+      RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \
+      RB_DEBUG_0_C_REQ_FULL_MASK | \
+      RB_DEBUG_0_C_MASK_FULL_MASK | \
+      RB_DEBUG_0_EZ_INFSAMP_FULL_MASK)
+
+#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \
+     ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \
+      (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \
+      (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \
+      (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \
+      (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \
+      (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \
+      (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \
+      (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \
+      (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \
+      (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \
+      (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \
+      (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \
+      (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \
+      (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \
+      (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \
+      (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \
+      (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \
+      (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \
+      (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \
+      (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \
+      (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT))
+
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+     } rb_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+     } rb_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_0_t f;
+} rb_debug_0_u;
+
+
+/*
+ * RB_DEBUG_1 struct
+ */
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_REQ_EMPTY_SIZE    1
+#define RB_DEBUG_1_C_MASK_EMPTY_SIZE   1
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28
+#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT   29
+#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT  30
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000
+#define RB_DEBUG_1_C_REQ_EMPTY_MASK    0x20000000
+#define RB_DEBUG_1_C_MASK_EMPTY_MASK   0x40000000
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000
+
+#define RB_DEBUG_1_MASK \
+     (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \
+      RB_DEBUG_1_C_REQ_EMPTY_MASK | \
+      RB_DEBUG_1_C_MASK_EMPTY_MASK | \
+      RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK)
+
+#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \
+     ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \
+      (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \
+      (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \
+      (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \
+      (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \
+      (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \
+      (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \
+      (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \
+      (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \
+      (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \
+      (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \
+      (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \
+      (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \
+      (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \
+      (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \
+      (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \
+      (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \
+      (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \
+      (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \
+      (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \
+      (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT))
+
+#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_1_t f;
+} rb_debug_1_u;
+
+
+/*
+ * RB_DEBUG_2 struct
+ */
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z1_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z0_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z1_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z_SAMP_FULL_SIZE    1
+#define RB_DEBUG_2_Z_TILE_FULL_SIZE    1
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE   1
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16
+#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT  17
+#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT  18
+#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT   19
+#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT   20
+#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT   21
+#define RB_DEBUG_2_Z_TILE_FULL_SHIFT   22
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT  28
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT  29
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT  30
+#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT  31
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000
+#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000
+#define RB_DEBUG_2_Z0_MASK_FULL_MASK   0x00020000
+#define RB_DEBUG_2_Z1_MASK_FULL_MASK   0x00040000
+#define RB_DEBUG_2_Z0_REQ_FULL_MASK    0x00080000
+#define RB_DEBUG_2_Z1_REQ_FULL_MASK    0x00100000
+#define RB_DEBUG_2_Z_SAMP_FULL_MASK    0x00200000
+#define RB_DEBUG_2_Z_TILE_FULL_MASK    0x00400000
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK  0x04000000
+#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK  0x08000000
+#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK   0x10000000
+#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK   0x20000000
+#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK   0x40000000
+#define RB_DEBUG_2_Z_TILE_EMPTY_MASK   0x80000000
+
+#define RB_DEBUG_2_MASK \
+     (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \
+      RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \
+      RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \
+      RB_DEBUG_2_Z0_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z1_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z0_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z1_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z_SAMP_FULL_MASK | \
+      RB_DEBUG_2_Z_TILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \
+      RB_DEBUG_2_Z_TILE_EMPTY_MASK)
+
+#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \
+     ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \
+      (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \
+      (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \
+      (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \
+      (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \
+      (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \
+      (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \
+      (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \
+      (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \
+      (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \
+      (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \
+      (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \
+      (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \
+      (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \
+      (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \
+      (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \
+      (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \
+      (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \
+      (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \
+      (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \
+      (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \
+      (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \
+      (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT))
+
+#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+     } rb_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+     } rb_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_2_t f;
+} rb_debug_2_u;
+
+
+/*
+ * RB_DEBUG_3 struct
+ */
+
+#define RB_DEBUG_3_ACCUM_VALID_SIZE    4
+#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4
+#define RB_DEBUG_3_SHD_FULL_SIZE       1
+#define RB_DEBUG_3_SHD_EMPTY_SIZE      1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1
+
+#define RB_DEBUG_3_ACCUM_VALID_SHIFT   0
+#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15
+#define RB_DEBUG_3_SHD_FULL_SHIFT      19
+#define RB_DEBUG_3_SHD_EMPTY_SHIFT     20
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28
+
+#define RB_DEBUG_3_ACCUM_VALID_MASK    0x0000000f
+#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000
+#define RB_DEBUG_3_SHD_FULL_MASK       0x00080000
+#define RB_DEBUG_3_SHD_EMPTY_MASK      0x00100000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000
+
+#define RB_DEBUG_3_MASK \
+     (RB_DEBUG_3_ACCUM_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_FLUSHING_MASK | \
+      RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \
+      RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \
+      RB_DEBUG_3_SHD_FULL_MASK | \
+      RB_DEBUG_3_SHD_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_FULL_MASK)
+
+#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \
+     ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \
+      (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \
+      (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \
+      (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \
+      (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \
+      (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \
+      (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \
+      (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \
+      (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \
+      (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \
+      (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \
+      (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \
+      (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \
+      (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \
+      (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT))
+
+#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int                                : 3;
+     } rb_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int                                : 3;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+     } rb_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_3_t f;
+} rb_debug_3_u;
+
+
+/*
+ * RB_DEBUG_4 struct
+ */
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00
+
+#define RB_DEBUG_4_MASK \
+     (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \
+      RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \
+      RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK)
+
+#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \
+     ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \
+      (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \
+      (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \
+      (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \
+      (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \
+      (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT))
+
+#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int                                : 19;
+     } rb_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int                                : 19;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+     } rb_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_4_t f;
+} rb_debug_4_u;
+
+
+/*
+ * RB_FLAG_CONTROL struct
+ */
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001
+
+#define RB_FLAG_CONTROL_MASK \
+     (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK)
+
+#define RB_FLAG_CONTROL(debug_flag_clear) \
+     ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT))
+
+#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \
+     ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \
+     rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+          unsigned int                                : 31;
+     } rb_flag_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int                                : 31;
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+     } rb_flag_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_flag_control_t f;
+} rb_flag_control_u;
+
+
+/*
+ * RB_BC_SPARES struct
+ */
+
+#define RB_BC_SPARES_RESERVED_SIZE     32
+
+#define RB_BC_SPARES_RESERVED_SHIFT    0
+
+#define RB_BC_SPARES_RESERVED_MASK     0xffffffff
+
+#define RB_BC_SPARES_MASK \
+     (RB_BC_SPARES_RESERVED_MASK)
+
+#define RB_BC_SPARES(reserved) \
+     ((reserved << RB_BC_SPARES_RESERVED_SHIFT))
+
+#define RB_BC_SPARES_GET_RESERVED(rb_bc_spares) \
+     ((rb_bc_spares & RB_BC_SPARES_RESERVED_MASK) >> RB_BC_SPARES_RESERVED_SHIFT)
+
+#define RB_BC_SPARES_SET_RESERVED(rb_bc_spares_reg, reserved) \
+     rb_bc_spares_reg = (rb_bc_spares_reg & ~RB_BC_SPARES_RESERVED_MASK) | (reserved << RB_BC_SPARES_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_spares_t {
+          unsigned int reserved                       : RB_BC_SPARES_RESERVED_SIZE;
+     } rb_bc_spares_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_spares_t {
+          unsigned int reserved                       : RB_BC_SPARES_RESERVED_SIZE;
+     } rb_bc_spares_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_spares_t f;
+} rb_bc_spares_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_ENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000
+
+#define BC_DUMMY_CRAYRB_ENUMS_MASK \
+     (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK)
+
+#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \
+     ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \
+      (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \
+      (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \
+      (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \
+      (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \
+      (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \
+      (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT))
+
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_enums_t f;
+} bc_dummy_crayrb_enums_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_MOREENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \
+     (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \
+     ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT))
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \
+     ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \
+     bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+          unsigned int                                : 30;
+     } bc_dummy_crayrb_moreenums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int                                : 30;
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+     } bc_dummy_crayrb_moreenums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_moreenums_t f;
+} bc_dummy_crayrb_moreenums_u;
+
+
+#endif
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h
new file mode 100644
index 000000000000..6968abb48bd7
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h
@@ -0,0 +1,550 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_TYPEDEF_HEADER)
+#define _yamato_TYPEDEF_HEADER
+
+#include "yamato_registers.h"
+
+typedef union PA_CL_VPORT_XSCALE                regPA_CL_VPORT_XSCALE;
+typedef union PA_CL_VPORT_XOFFSET               regPA_CL_VPORT_XOFFSET;
+typedef union PA_CL_VPORT_YSCALE                regPA_CL_VPORT_YSCALE;
+typedef union PA_CL_VPORT_YOFFSET               regPA_CL_VPORT_YOFFSET;
+typedef union PA_CL_VPORT_ZSCALE                regPA_CL_VPORT_ZSCALE;
+typedef union PA_CL_VPORT_ZOFFSET               regPA_CL_VPORT_ZOFFSET;
+typedef union PA_CL_VTE_CNTL                    regPA_CL_VTE_CNTL;
+typedef union PA_CL_CLIP_CNTL                   regPA_CL_CLIP_CNTL;
+typedef union PA_CL_GB_VERT_CLIP_ADJ            regPA_CL_GB_VERT_CLIP_ADJ;
+typedef union PA_CL_GB_VERT_DISC_ADJ            regPA_CL_GB_VERT_DISC_ADJ;
+typedef union PA_CL_GB_HORZ_CLIP_ADJ            regPA_CL_GB_HORZ_CLIP_ADJ;
+typedef union PA_CL_GB_HORZ_DISC_ADJ            regPA_CL_GB_HORZ_DISC_ADJ;
+typedef union PA_CL_ENHANCE                     regPA_CL_ENHANCE;
+typedef union PA_SC_ENHANCE                     regPA_SC_ENHANCE;
+typedef union PA_SU_VTX_CNTL                    regPA_SU_VTX_CNTL;
+typedef union PA_SU_POINT_SIZE                  regPA_SU_POINT_SIZE;
+typedef union PA_SU_POINT_MINMAX                regPA_SU_POINT_MINMAX;
+typedef union PA_SU_LINE_CNTL                   regPA_SU_LINE_CNTL;
+typedef union PA_SU_FACE_DATA                   regPA_SU_FACE_DATA;
+typedef union PA_SU_SC_MODE_CNTL                regPA_SU_SC_MODE_CNTL;
+typedef union PA_SU_POLY_OFFSET_FRONT_SCALE     regPA_SU_POLY_OFFSET_FRONT_SCALE;
+typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET    regPA_SU_POLY_OFFSET_FRONT_OFFSET;
+typedef union PA_SU_POLY_OFFSET_BACK_SCALE      regPA_SU_POLY_OFFSET_BACK_SCALE;
+typedef union PA_SU_POLY_OFFSET_BACK_OFFSET     regPA_SU_POLY_OFFSET_BACK_OFFSET;
+typedef union PA_SU_PERFCOUNTER0_SELECT         regPA_SU_PERFCOUNTER0_SELECT;
+typedef union PA_SU_PERFCOUNTER1_SELECT         regPA_SU_PERFCOUNTER1_SELECT;
+typedef union PA_SU_PERFCOUNTER2_SELECT         regPA_SU_PERFCOUNTER2_SELECT;
+typedef union PA_SU_PERFCOUNTER3_SELECT         regPA_SU_PERFCOUNTER3_SELECT;
+typedef union PA_SU_PERFCOUNTER0_LOW            regPA_SU_PERFCOUNTER0_LOW;
+typedef union PA_SU_PERFCOUNTER0_HI             regPA_SU_PERFCOUNTER0_HI;
+typedef union PA_SU_PERFCOUNTER1_LOW            regPA_SU_PERFCOUNTER1_LOW;
+typedef union PA_SU_PERFCOUNTER1_HI             regPA_SU_PERFCOUNTER1_HI;
+typedef union PA_SU_PERFCOUNTER2_LOW            regPA_SU_PERFCOUNTER2_LOW;
+typedef union PA_SU_PERFCOUNTER2_HI             regPA_SU_PERFCOUNTER2_HI;
+typedef union PA_SU_PERFCOUNTER3_LOW            regPA_SU_PERFCOUNTER3_LOW;
+typedef union PA_SU_PERFCOUNTER3_HI             regPA_SU_PERFCOUNTER3_HI;
+typedef union PA_SC_WINDOW_OFFSET               regPA_SC_WINDOW_OFFSET;
+typedef union PA_SC_AA_CONFIG                   regPA_SC_AA_CONFIG;
+typedef union PA_SC_AA_MASK                     regPA_SC_AA_MASK;
+typedef union PA_SC_LINE_STIPPLE                regPA_SC_LINE_STIPPLE;
+typedef union PA_SC_LINE_CNTL                   regPA_SC_LINE_CNTL;
+typedef union PA_SC_WINDOW_SCISSOR_TL           regPA_SC_WINDOW_SCISSOR_TL;
+typedef union PA_SC_WINDOW_SCISSOR_BR           regPA_SC_WINDOW_SCISSOR_BR;
+typedef union PA_SC_SCREEN_SCISSOR_TL           regPA_SC_SCREEN_SCISSOR_TL;
+typedef union PA_SC_SCREEN_SCISSOR_BR           regPA_SC_SCREEN_SCISSOR_BR;
+typedef union PA_SC_VIZ_QUERY                   regPA_SC_VIZ_QUERY;
+typedef union PA_SC_VIZ_QUERY_STATUS            regPA_SC_VIZ_QUERY_STATUS;
+typedef union PA_SC_LINE_STIPPLE_STATE          regPA_SC_LINE_STIPPLE_STATE;
+typedef union PA_SC_PERFCOUNTER0_SELECT         regPA_SC_PERFCOUNTER0_SELECT;
+typedef union PA_SC_PERFCOUNTER0_LOW            regPA_SC_PERFCOUNTER0_LOW;
+typedef union PA_SC_PERFCOUNTER0_HI             regPA_SC_PERFCOUNTER0_HI;
+typedef union PA_CL_CNTL_STATUS                 regPA_CL_CNTL_STATUS;
+typedef union PA_SU_CNTL_STATUS                 regPA_SU_CNTL_STATUS;
+typedef union PA_SC_CNTL_STATUS                 regPA_SC_CNTL_STATUS;
+typedef union PA_SU_DEBUG_CNTL                  regPA_SU_DEBUG_CNTL;
+typedef union PA_SU_DEBUG_DATA                  regPA_SU_DEBUG_DATA;
+typedef union PA_SC_DEBUG_CNTL                  regPA_SC_DEBUG_CNTL;
+typedef union PA_SC_DEBUG_DATA                  regPA_SC_DEBUG_DATA;
+typedef union GFX_COPY_STATE                    regGFX_COPY_STATE;
+typedef union VGT_DRAW_INITIATOR                regVGT_DRAW_INITIATOR;
+typedef union VGT_EVENT_INITIATOR               regVGT_EVENT_INITIATOR;
+typedef union VGT_DMA_BASE                      regVGT_DMA_BASE;
+typedef union VGT_DMA_SIZE                      regVGT_DMA_SIZE;
+typedef union VGT_BIN_BASE                      regVGT_BIN_BASE;
+typedef union VGT_BIN_SIZE                      regVGT_BIN_SIZE;
+typedef union VGT_CURRENT_BIN_ID_MIN            regVGT_CURRENT_BIN_ID_MIN;
+typedef union VGT_CURRENT_BIN_ID_MAX            regVGT_CURRENT_BIN_ID_MAX;
+typedef union VGT_IMMED_DATA                    regVGT_IMMED_DATA;
+typedef union VGT_MAX_VTX_INDX                  regVGT_MAX_VTX_INDX;
+typedef union VGT_MIN_VTX_INDX                  regVGT_MIN_VTX_INDX;
+typedef union VGT_INDX_OFFSET                   regVGT_INDX_OFFSET;
+typedef union VGT_VERTEX_REUSE_BLOCK_CNTL       regVGT_VERTEX_REUSE_BLOCK_CNTL;
+typedef union VGT_OUT_DEALLOC_CNTL              regVGT_OUT_DEALLOC_CNTL;
+typedef union VGT_MULTI_PRIM_IB_RESET_INDX      regVGT_MULTI_PRIM_IB_RESET_INDX;
+typedef union VGT_ENHANCE                       regVGT_ENHANCE;
+typedef union VGT_VTX_VECT_EJECT_REG            regVGT_VTX_VECT_EJECT_REG;
+typedef union VGT_LAST_COPY_STATE               regVGT_LAST_COPY_STATE;
+typedef union VGT_DEBUG_CNTL                    regVGT_DEBUG_CNTL;
+typedef union VGT_DEBUG_DATA                    regVGT_DEBUG_DATA;
+typedef union VGT_CNTL_STATUS                   regVGT_CNTL_STATUS;
+typedef union VGT_CRC_SQ_DATA                   regVGT_CRC_SQ_DATA;
+typedef union VGT_CRC_SQ_CTRL                   regVGT_CRC_SQ_CTRL;
+typedef union VGT_PERFCOUNTER0_SELECT           regVGT_PERFCOUNTER0_SELECT;
+typedef union VGT_PERFCOUNTER1_SELECT           regVGT_PERFCOUNTER1_SELECT;
+typedef union VGT_PERFCOUNTER2_SELECT           regVGT_PERFCOUNTER2_SELECT;
+typedef union VGT_PERFCOUNTER3_SELECT           regVGT_PERFCOUNTER3_SELECT;
+typedef union VGT_PERFCOUNTER0_LOW              regVGT_PERFCOUNTER0_LOW;
+typedef union VGT_PERFCOUNTER1_LOW              regVGT_PERFCOUNTER1_LOW;
+typedef union VGT_PERFCOUNTER2_LOW              regVGT_PERFCOUNTER2_LOW;
+typedef union VGT_PERFCOUNTER3_LOW              regVGT_PERFCOUNTER3_LOW;
+typedef union VGT_PERFCOUNTER0_HI               regVGT_PERFCOUNTER0_HI;
+typedef union VGT_PERFCOUNTER1_HI               regVGT_PERFCOUNTER1_HI;
+typedef union VGT_PERFCOUNTER2_HI               regVGT_PERFCOUNTER2_HI;
+typedef union VGT_PERFCOUNTER3_HI               regVGT_PERFCOUNTER3_HI;
+typedef union TC_CNTL_STATUS                    regTC_CNTL_STATUS;
+typedef union TCR_CHICKEN                       regTCR_CHICKEN;
+typedef union TCF_CHICKEN                       regTCF_CHICKEN;
+typedef union TCM_CHICKEN                       regTCM_CHICKEN;
+typedef union TCR_PERFCOUNTER0_SELECT           regTCR_PERFCOUNTER0_SELECT;
+typedef union TCR_PERFCOUNTER1_SELECT           regTCR_PERFCOUNTER1_SELECT;
+typedef union TCR_PERFCOUNTER0_HI               regTCR_PERFCOUNTER0_HI;
+typedef union TCR_PERFCOUNTER1_HI               regTCR_PERFCOUNTER1_HI;
+typedef union TCR_PERFCOUNTER0_LOW              regTCR_PERFCOUNTER0_LOW;
+typedef union TCR_PERFCOUNTER1_LOW              regTCR_PERFCOUNTER1_LOW;
+typedef union TP_TC_CLKGATE_CNTL                regTP_TC_CLKGATE_CNTL;
+typedef union TPC_CNTL_STATUS                   regTPC_CNTL_STATUS;
+typedef union TPC_DEBUG0                        regTPC_DEBUG0;
+typedef union TPC_DEBUG1                        regTPC_DEBUG1;
+typedef union TPC_CHICKEN                       regTPC_CHICKEN;
+typedef union TP0_CNTL_STATUS                   regTP0_CNTL_STATUS;
+typedef union TP0_DEBUG                         regTP0_DEBUG;
+typedef union TP0_CHICKEN                       regTP0_CHICKEN;
+typedef union TP0_PERFCOUNTER0_SELECT           regTP0_PERFCOUNTER0_SELECT;
+typedef union TP0_PERFCOUNTER0_HI               regTP0_PERFCOUNTER0_HI;
+typedef union TP0_PERFCOUNTER0_LOW              regTP0_PERFCOUNTER0_LOW;
+typedef union TP0_PERFCOUNTER1_SELECT           regTP0_PERFCOUNTER1_SELECT;
+typedef union TP0_PERFCOUNTER1_HI               regTP0_PERFCOUNTER1_HI;
+typedef union TP0_PERFCOUNTER1_LOW              regTP0_PERFCOUNTER1_LOW;
+typedef union TCM_PERFCOUNTER0_SELECT           regTCM_PERFCOUNTER0_SELECT;
+typedef union TCM_PERFCOUNTER1_SELECT           regTCM_PERFCOUNTER1_SELECT;
+typedef union TCM_PERFCOUNTER0_HI               regTCM_PERFCOUNTER0_HI;
+typedef union TCM_PERFCOUNTER1_HI               regTCM_PERFCOUNTER1_HI;
+typedef union TCM_PERFCOUNTER0_LOW              regTCM_PERFCOUNTER0_LOW;
+typedef union TCM_PERFCOUNTER1_LOW              regTCM_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER0_SELECT           regTCF_PERFCOUNTER0_SELECT;
+typedef union TCF_PERFCOUNTER1_SELECT           regTCF_PERFCOUNTER1_SELECT;
+typedef union TCF_PERFCOUNTER2_SELECT           regTCF_PERFCOUNTER2_SELECT;
+typedef union TCF_PERFCOUNTER3_SELECT           regTCF_PERFCOUNTER3_SELECT;
+typedef union TCF_PERFCOUNTER4_SELECT           regTCF_PERFCOUNTER4_SELECT;
+typedef union TCF_PERFCOUNTER5_SELECT           regTCF_PERFCOUNTER5_SELECT;
+typedef union TCF_PERFCOUNTER6_SELECT           regTCF_PERFCOUNTER6_SELECT;
+typedef union TCF_PERFCOUNTER7_SELECT           regTCF_PERFCOUNTER7_SELECT;
+typedef union TCF_PERFCOUNTER8_SELECT           regTCF_PERFCOUNTER8_SELECT;
+typedef union TCF_PERFCOUNTER9_SELECT           regTCF_PERFCOUNTER9_SELECT;
+typedef union TCF_PERFCOUNTER10_SELECT          regTCF_PERFCOUNTER10_SELECT;
+typedef union TCF_PERFCOUNTER11_SELECT          regTCF_PERFCOUNTER11_SELECT;
+typedef union TCF_PERFCOUNTER0_HI               regTCF_PERFCOUNTER0_HI;
+typedef union TCF_PERFCOUNTER1_HI               regTCF_PERFCOUNTER1_HI;
+typedef union TCF_PERFCOUNTER2_HI               regTCF_PERFCOUNTER2_HI;
+typedef union TCF_PERFCOUNTER3_HI               regTCF_PERFCOUNTER3_HI;
+typedef union TCF_PERFCOUNTER4_HI               regTCF_PERFCOUNTER4_HI;
+typedef union TCF_PERFCOUNTER5_HI               regTCF_PERFCOUNTER5_HI;
+typedef union TCF_PERFCOUNTER6_HI               regTCF_PERFCOUNTER6_HI;
+typedef union TCF_PERFCOUNTER7_HI               regTCF_PERFCOUNTER7_HI;
+typedef union TCF_PERFCOUNTER8_HI               regTCF_PERFCOUNTER8_HI;
+typedef union TCF_PERFCOUNTER9_HI               regTCF_PERFCOUNTER9_HI;
+typedef union TCF_PERFCOUNTER10_HI              regTCF_PERFCOUNTER10_HI;
+typedef union TCF_PERFCOUNTER11_HI              regTCF_PERFCOUNTER11_HI;
+typedef union TCF_PERFCOUNTER0_LOW              regTCF_PERFCOUNTER0_LOW;
+typedef union TCF_PERFCOUNTER1_LOW              regTCF_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER2_LOW              regTCF_PERFCOUNTER2_LOW;
+typedef union TCF_PERFCOUNTER3_LOW              regTCF_PERFCOUNTER3_LOW;
+typedef union TCF_PERFCOUNTER4_LOW              regTCF_PERFCOUNTER4_LOW;
+typedef union TCF_PERFCOUNTER5_LOW              regTCF_PERFCOUNTER5_LOW;
+typedef union TCF_PERFCOUNTER6_LOW              regTCF_PERFCOUNTER6_LOW;
+typedef union TCF_PERFCOUNTER7_LOW              regTCF_PERFCOUNTER7_LOW;
+typedef union TCF_PERFCOUNTER8_LOW              regTCF_PERFCOUNTER8_LOW;
+typedef union TCF_PERFCOUNTER9_LOW              regTCF_PERFCOUNTER9_LOW;
+typedef union TCF_PERFCOUNTER10_LOW             regTCF_PERFCOUNTER10_LOW;
+typedef union TCF_PERFCOUNTER11_LOW             regTCF_PERFCOUNTER11_LOW;
+typedef union TCF_DEBUG                         regTCF_DEBUG;
+typedef union TCA_FIFO_DEBUG                    regTCA_FIFO_DEBUG;
+typedef union TCA_PROBE_DEBUG                   regTCA_PROBE_DEBUG;
+typedef union TCA_TPC_DEBUG                     regTCA_TPC_DEBUG;
+typedef union TCB_CORE_DEBUG                    regTCB_CORE_DEBUG;
+typedef union TCB_TAG0_DEBUG                    regTCB_TAG0_DEBUG;
+typedef union TCB_TAG1_DEBUG                    regTCB_TAG1_DEBUG;
+typedef union TCB_TAG2_DEBUG                    regTCB_TAG2_DEBUG;
+typedef union TCB_TAG3_DEBUG                    regTCB_TAG3_DEBUG;
+typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG;
+typedef union TCB_FETCH_GEN_WALKER_DEBUG        regTCB_FETCH_GEN_WALKER_DEBUG;
+typedef union TCB_FETCH_GEN_PIPE0_DEBUG         regTCB_FETCH_GEN_PIPE0_DEBUG;
+typedef union TCD_INPUT0_DEBUG                  regTCD_INPUT0_DEBUG;
+typedef union TCD_DEGAMMA_DEBUG                 regTCD_DEGAMMA_DEBUG;
+typedef union TCD_DXTMUX_SCTARB_DEBUG           regTCD_DXTMUX_SCTARB_DEBUG;
+typedef union TCD_DXTC_ARB_DEBUG                regTCD_DXTC_ARB_DEBUG;
+typedef union TCD_STALLS_DEBUG                  regTCD_STALLS_DEBUG;
+typedef union TCO_STALLS_DEBUG                  regTCO_STALLS_DEBUG;
+typedef union TCO_QUAD0_DEBUG0                  regTCO_QUAD0_DEBUG0;
+typedef union TCO_QUAD0_DEBUG1                  regTCO_QUAD0_DEBUG1;
+typedef union SQ_GPR_MANAGEMENT                 regSQ_GPR_MANAGEMENT;
+typedef union SQ_FLOW_CONTROL                   regSQ_FLOW_CONTROL;
+typedef union SQ_INST_STORE_MANAGMENT           regSQ_INST_STORE_MANAGMENT;
+typedef union SQ_RESOURCE_MANAGMENT             regSQ_RESOURCE_MANAGMENT;
+typedef union SQ_EO_RT                          regSQ_EO_RT;
+typedef union SQ_DEBUG_MISC                     regSQ_DEBUG_MISC;
+typedef union SQ_ACTIVITY_METER_CNTL            regSQ_ACTIVITY_METER_CNTL;
+typedef union SQ_ACTIVITY_METER_STATUS          regSQ_ACTIVITY_METER_STATUS;
+typedef union SQ_INPUT_ARB_PRIORITY             regSQ_INPUT_ARB_PRIORITY;
+typedef union SQ_THREAD_ARB_PRIORITY            regSQ_THREAD_ARB_PRIORITY;
+typedef union SQ_VS_WATCHDOG_TIMER              regSQ_VS_WATCHDOG_TIMER;
+typedef union SQ_PS_WATCHDOG_TIMER              regSQ_PS_WATCHDOG_TIMER;
+typedef union SQ_INT_CNTL                       regSQ_INT_CNTL;
+typedef union SQ_INT_STATUS                     regSQ_INT_STATUS;
+typedef union SQ_INT_ACK                        regSQ_INT_ACK;
+typedef union SQ_DEBUG_INPUT_FSM                regSQ_DEBUG_INPUT_FSM;
+typedef union SQ_DEBUG_CONST_MGR_FSM            regSQ_DEBUG_CONST_MGR_FSM;
+typedef union SQ_DEBUG_TP_FSM                   regSQ_DEBUG_TP_FSM;
+typedef union SQ_DEBUG_FSM_ALU_0                regSQ_DEBUG_FSM_ALU_0;
+typedef union SQ_DEBUG_FSM_ALU_1                regSQ_DEBUG_FSM_ALU_1;
+typedef union SQ_DEBUG_EXP_ALLOC                regSQ_DEBUG_EXP_ALLOC;
+typedef union SQ_DEBUG_PTR_BUFF                 regSQ_DEBUG_PTR_BUFF;
+typedef union SQ_DEBUG_GPR_VTX                  regSQ_DEBUG_GPR_VTX;
+typedef union SQ_DEBUG_GPR_PIX                  regSQ_DEBUG_GPR_PIX;
+typedef union SQ_DEBUG_TB_STATUS_SEL            regSQ_DEBUG_TB_STATUS_SEL;
+typedef union SQ_DEBUG_VTX_TB_0                 regSQ_DEBUG_VTX_TB_0;
+typedef union SQ_DEBUG_VTX_TB_1                 regSQ_DEBUG_VTX_TB_1;
+typedef union SQ_DEBUG_VTX_TB_STATUS_REG        regSQ_DEBUG_VTX_TB_STATUS_REG;
+typedef union SQ_DEBUG_VTX_TB_STATE_MEM         regSQ_DEBUG_VTX_TB_STATE_MEM;
+typedef union SQ_DEBUG_PIX_TB_0                 regSQ_DEBUG_PIX_TB_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0      regSQ_DEBUG_PIX_TB_STATUS_REG_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1      regSQ_DEBUG_PIX_TB_STATUS_REG_1;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2      regSQ_DEBUG_PIX_TB_STATUS_REG_2;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3      regSQ_DEBUG_PIX_TB_STATUS_REG_3;
+typedef union SQ_DEBUG_PIX_TB_STATE_MEM         regSQ_DEBUG_PIX_TB_STATE_MEM;
+typedef union SQ_PERFCOUNTER0_SELECT            regSQ_PERFCOUNTER0_SELECT;
+typedef union SQ_PERFCOUNTER1_SELECT            regSQ_PERFCOUNTER1_SELECT;
+typedef union SQ_PERFCOUNTER2_SELECT            regSQ_PERFCOUNTER2_SELECT;
+typedef union SQ_PERFCOUNTER3_SELECT            regSQ_PERFCOUNTER3_SELECT;
+typedef union SQ_PERFCOUNTER0_LOW               regSQ_PERFCOUNTER0_LOW;
+typedef union SQ_PERFCOUNTER0_HI                regSQ_PERFCOUNTER0_HI;
+typedef union SQ_PERFCOUNTER1_LOW               regSQ_PERFCOUNTER1_LOW;
+typedef union SQ_PERFCOUNTER1_HI                regSQ_PERFCOUNTER1_HI;
+typedef union SQ_PERFCOUNTER2_LOW               regSQ_PERFCOUNTER2_LOW;
+typedef union SQ_PERFCOUNTER2_HI                regSQ_PERFCOUNTER2_HI;
+typedef union SQ_PERFCOUNTER3_LOW               regSQ_PERFCOUNTER3_LOW;
+typedef union SQ_PERFCOUNTER3_HI                regSQ_PERFCOUNTER3_HI;
+typedef union SX_PERFCOUNTER0_SELECT            regSX_PERFCOUNTER0_SELECT;
+typedef union SX_PERFCOUNTER0_LOW               regSX_PERFCOUNTER0_LOW;
+typedef union SX_PERFCOUNTER0_HI                regSX_PERFCOUNTER0_HI;
+typedef union SQ_INSTRUCTION_ALU_0              regSQ_INSTRUCTION_ALU_0;
+typedef union SQ_INSTRUCTION_ALU_1              regSQ_INSTRUCTION_ALU_1;
+typedef union SQ_INSTRUCTION_ALU_2              regSQ_INSTRUCTION_ALU_2;
+typedef union SQ_INSTRUCTION_CF_EXEC_0          regSQ_INSTRUCTION_CF_EXEC_0;
+typedef union SQ_INSTRUCTION_CF_EXEC_1          regSQ_INSTRUCTION_CF_EXEC_1;
+typedef union SQ_INSTRUCTION_CF_EXEC_2          regSQ_INSTRUCTION_CF_EXEC_2;
+typedef union SQ_INSTRUCTION_CF_LOOP_0          regSQ_INSTRUCTION_CF_LOOP_0;
+typedef union SQ_INSTRUCTION_CF_LOOP_1          regSQ_INSTRUCTION_CF_LOOP_1;
+typedef union SQ_INSTRUCTION_CF_LOOP_2          regSQ_INSTRUCTION_CF_LOOP_2;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_0      regSQ_INSTRUCTION_CF_JMP_CALL_0;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_1      regSQ_INSTRUCTION_CF_JMP_CALL_1;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_2      regSQ_INSTRUCTION_CF_JMP_CALL_2;
+typedef union SQ_INSTRUCTION_CF_ALLOC_0         regSQ_INSTRUCTION_CF_ALLOC_0;
+typedef union SQ_INSTRUCTION_CF_ALLOC_1         regSQ_INSTRUCTION_CF_ALLOC_1;
+typedef union SQ_INSTRUCTION_CF_ALLOC_2         regSQ_INSTRUCTION_CF_ALLOC_2;
+typedef union SQ_INSTRUCTION_TFETCH_0           regSQ_INSTRUCTION_TFETCH_0;
+typedef union SQ_INSTRUCTION_TFETCH_1           regSQ_INSTRUCTION_TFETCH_1;
+typedef union SQ_INSTRUCTION_TFETCH_2           regSQ_INSTRUCTION_TFETCH_2;
+typedef union SQ_INSTRUCTION_VFETCH_0           regSQ_INSTRUCTION_VFETCH_0;
+typedef union SQ_INSTRUCTION_VFETCH_1           regSQ_INSTRUCTION_VFETCH_1;
+typedef union SQ_INSTRUCTION_VFETCH_2           regSQ_INSTRUCTION_VFETCH_2;
+typedef union SQ_CONSTANT_0                     regSQ_CONSTANT_0;
+typedef union SQ_CONSTANT_1                     regSQ_CONSTANT_1;
+typedef union SQ_CONSTANT_2                     regSQ_CONSTANT_2;
+typedef union SQ_CONSTANT_3                     regSQ_CONSTANT_3;
+typedef union SQ_FETCH_0                        regSQ_FETCH_0;
+typedef union SQ_FETCH_1                        regSQ_FETCH_1;
+typedef union SQ_FETCH_2                        regSQ_FETCH_2;
+typedef union SQ_FETCH_3                        regSQ_FETCH_3;
+typedef union SQ_FETCH_4                        regSQ_FETCH_4;
+typedef union SQ_FETCH_5                        regSQ_FETCH_5;
+typedef union SQ_CONSTANT_VFETCH_0              regSQ_CONSTANT_VFETCH_0;
+typedef union SQ_CONSTANT_VFETCH_1              regSQ_CONSTANT_VFETCH_1;
+typedef union SQ_CONSTANT_T2                    regSQ_CONSTANT_T2;
+typedef union SQ_CONSTANT_T3                    regSQ_CONSTANT_T3;
+typedef union SQ_CF_BOOLEANS                    regSQ_CF_BOOLEANS;
+typedef union SQ_CF_LOOP                        regSQ_CF_LOOP;
+typedef union SQ_CONSTANT_RT_0                  regSQ_CONSTANT_RT_0;
+typedef union SQ_CONSTANT_RT_1                  regSQ_CONSTANT_RT_1;
+typedef union SQ_CONSTANT_RT_2                  regSQ_CONSTANT_RT_2;
+typedef union SQ_CONSTANT_RT_3                  regSQ_CONSTANT_RT_3;
+typedef union SQ_FETCH_RT_0                     regSQ_FETCH_RT_0;
+typedef union SQ_FETCH_RT_1                     regSQ_FETCH_RT_1;
+typedef union SQ_FETCH_RT_2                     regSQ_FETCH_RT_2;
+typedef union SQ_FETCH_RT_3                     regSQ_FETCH_RT_3;
+typedef union SQ_FETCH_RT_4                     regSQ_FETCH_RT_4;
+typedef union SQ_FETCH_RT_5                     regSQ_FETCH_RT_5;
+typedef union SQ_CF_RT_BOOLEANS                 regSQ_CF_RT_BOOLEANS;
+typedef union SQ_CF_RT_LOOP                     regSQ_CF_RT_LOOP;
+typedef union SQ_VS_PROGRAM                     regSQ_VS_PROGRAM;
+typedef union SQ_PS_PROGRAM                     regSQ_PS_PROGRAM;
+typedef union SQ_CF_PROGRAM_SIZE                regSQ_CF_PROGRAM_SIZE;
+typedef union SQ_INTERPOLATOR_CNTL              regSQ_INTERPOLATOR_CNTL;
+typedef union SQ_PROGRAM_CNTL                   regSQ_PROGRAM_CNTL;
+typedef union SQ_WRAPPING_0                     regSQ_WRAPPING_0;
+typedef union SQ_WRAPPING_1                     regSQ_WRAPPING_1;
+typedef union SQ_VS_CONST                       regSQ_VS_CONST;
+typedef union SQ_PS_CONST                       regSQ_PS_CONST;
+typedef union SQ_CONTEXT_MISC                   regSQ_CONTEXT_MISC;
+typedef union SQ_CF_RD_BASE                     regSQ_CF_RD_BASE;
+typedef union SQ_DEBUG_MISC_0                   regSQ_DEBUG_MISC_0;
+typedef union SQ_DEBUG_MISC_1                   regSQ_DEBUG_MISC_1;
+typedef union MH_ARBITER_CONFIG                 regMH_ARBITER_CONFIG;
+typedef union MH_CLNT_AXI_ID_REUSE              regMH_CLNT_AXI_ID_REUSE;
+typedef union MH_INTERRUPT_MASK                 regMH_INTERRUPT_MASK;
+typedef union MH_INTERRUPT_STATUS               regMH_INTERRUPT_STATUS;
+typedef union MH_INTERRUPT_CLEAR                regMH_INTERRUPT_CLEAR;
+typedef union MH_AXI_ERROR                      regMH_AXI_ERROR;
+typedef union MH_PERFCOUNTER0_SELECT            regMH_PERFCOUNTER0_SELECT;
+typedef union MH_PERFCOUNTER1_SELECT            regMH_PERFCOUNTER1_SELECT;
+typedef union MH_PERFCOUNTER0_CONFIG            regMH_PERFCOUNTER0_CONFIG;
+typedef union MH_PERFCOUNTER1_CONFIG            regMH_PERFCOUNTER1_CONFIG;
+typedef union MH_PERFCOUNTER0_LOW               regMH_PERFCOUNTER0_LOW;
+typedef union MH_PERFCOUNTER1_LOW               regMH_PERFCOUNTER1_LOW;
+typedef union MH_PERFCOUNTER0_HI                regMH_PERFCOUNTER0_HI;
+typedef union MH_PERFCOUNTER1_HI                regMH_PERFCOUNTER1_HI;
+typedef union MH_DEBUG_CTRL                     regMH_DEBUG_CTRL;
+typedef union MH_DEBUG_DATA                     regMH_DEBUG_DATA;
+typedef union MH_AXI_HALT_CONTROL               regMH_AXI_HALT_CONTROL;
+typedef union MH_MMU_CONFIG                     regMH_MMU_CONFIG;
+typedef union MH_MMU_VA_RANGE                   regMH_MMU_VA_RANGE;
+typedef union MH_MMU_PT_BASE                    regMH_MMU_PT_BASE;
+typedef union MH_MMU_PAGE_FAULT                 regMH_MMU_PAGE_FAULT;
+typedef union MH_MMU_TRAN_ERROR                 regMH_MMU_TRAN_ERROR;
+typedef union MH_MMU_INVALIDATE                 regMH_MMU_INVALIDATE;
+typedef union MH_MMU_MPU_BASE                   regMH_MMU_MPU_BASE;
+typedef union MH_MMU_MPU_END                    regMH_MMU_MPU_END;
+typedef union WAIT_UNTIL                        regWAIT_UNTIL;
+typedef union RBBM_ISYNC_CNTL                   regRBBM_ISYNC_CNTL;
+typedef union RBBM_STATUS                       regRBBM_STATUS;
+typedef union RBBM_DSPLY                        regRBBM_DSPLY;
+typedef union RBBM_RENDER_LATEST                regRBBM_RENDER_LATEST;
+typedef union RBBM_RTL_RELEASE                  regRBBM_RTL_RELEASE;
+typedef union RBBM_PATCH_RELEASE                regRBBM_PATCH_RELEASE;
+typedef union RBBM_AUXILIARY_CONFIG             regRBBM_AUXILIARY_CONFIG;
+typedef union RBBM_PERIPHID0                    regRBBM_PERIPHID0;
+typedef union RBBM_PERIPHID1                    regRBBM_PERIPHID1;
+typedef union RBBM_PERIPHID2                    regRBBM_PERIPHID2;
+typedef union RBBM_PERIPHID3                    regRBBM_PERIPHID3;
+typedef union RBBM_CNTL                         regRBBM_CNTL;
+typedef union RBBM_SKEW_CNTL                    regRBBM_SKEW_CNTL;
+typedef union RBBM_SOFT_RESET                   regRBBM_SOFT_RESET;
+typedef union RBBM_PM_OVERRIDE1                 regRBBM_PM_OVERRIDE1;
+typedef union RBBM_PM_OVERRIDE2                 regRBBM_PM_OVERRIDE2;
+typedef union GC_SYS_IDLE                       regGC_SYS_IDLE;
+typedef union NQWAIT_UNTIL                      regNQWAIT_UNTIL;
+typedef union RBBM_DEBUG_OUT                    regRBBM_DEBUG_OUT;
+typedef union RBBM_DEBUG_CNTL                   regRBBM_DEBUG_CNTL;
+typedef union RBBM_DEBUG                        regRBBM_DEBUG;
+typedef union RBBM_READ_ERROR                   regRBBM_READ_ERROR;
+typedef union RBBM_WAIT_IDLE_CLOCKS             regRBBM_WAIT_IDLE_CLOCKS;
+typedef union RBBM_INT_CNTL                     regRBBM_INT_CNTL;
+typedef union RBBM_INT_STATUS                   regRBBM_INT_STATUS;
+typedef union RBBM_INT_ACK                      regRBBM_INT_ACK;
+typedef union MASTER_INT_SIGNAL                 regMASTER_INT_SIGNAL;
+typedef union RBBM_PERFCOUNTER1_SELECT          regRBBM_PERFCOUNTER1_SELECT;
+typedef union RBBM_PERFCOUNTER1_LO              regRBBM_PERFCOUNTER1_LO;
+typedef union RBBM_PERFCOUNTER1_HI              regRBBM_PERFCOUNTER1_HI;
+typedef union CP_RB_BASE                        regCP_RB_BASE;
+typedef union CP_RB_CNTL                        regCP_RB_CNTL;
+typedef union CP_RB_RPTR_ADDR                   regCP_RB_RPTR_ADDR;
+typedef union CP_RB_RPTR                        regCP_RB_RPTR;
+typedef union CP_RB_RPTR_WR                     regCP_RB_RPTR_WR;
+typedef union CP_RB_WPTR                        regCP_RB_WPTR;
+typedef union CP_RB_WPTR_DELAY                  regCP_RB_WPTR_DELAY;
+typedef union CP_RB_WPTR_BASE                   regCP_RB_WPTR_BASE;
+typedef union CP_IB1_BASE                       regCP_IB1_BASE;
+typedef union CP_IB1_BUFSZ                      regCP_IB1_BUFSZ;
+typedef union CP_IB2_BASE                       regCP_IB2_BASE;
+typedef union CP_IB2_BUFSZ                      regCP_IB2_BUFSZ;
+typedef union CP_ST_BASE                        regCP_ST_BASE;
+typedef union CP_ST_BUFSZ                       regCP_ST_BUFSZ;
+typedef union CP_QUEUE_THRESHOLDS               regCP_QUEUE_THRESHOLDS;
+typedef union CP_MEQ_THRESHOLDS                 regCP_MEQ_THRESHOLDS;
+typedef union CP_CSQ_AVAIL                      regCP_CSQ_AVAIL;
+typedef union CP_STQ_AVAIL                      regCP_STQ_AVAIL;
+typedef union CP_MEQ_AVAIL                      regCP_MEQ_AVAIL;
+typedef union CP_CSQ_RB_STAT                    regCP_CSQ_RB_STAT;
+typedef union CP_CSQ_IB1_STAT                   regCP_CSQ_IB1_STAT;
+typedef union CP_CSQ_IB2_STAT                   regCP_CSQ_IB2_STAT;
+typedef union CP_NON_PREFETCH_CNTRS             regCP_NON_PREFETCH_CNTRS;
+typedef union CP_STQ_ST_STAT                    regCP_STQ_ST_STAT;
+typedef union CP_MEQ_STAT                       regCP_MEQ_STAT;
+typedef union CP_MIU_TAG_STAT                   regCP_MIU_TAG_STAT;
+typedef union CP_CMD_INDEX                      regCP_CMD_INDEX;
+typedef union CP_CMD_DATA                       regCP_CMD_DATA;
+typedef union CP_ME_CNTL                        regCP_ME_CNTL;
+typedef union CP_ME_STATUS                      regCP_ME_STATUS;
+typedef union CP_ME_RAM_WADDR                   regCP_ME_RAM_WADDR;
+typedef union CP_ME_RAM_RADDR                   regCP_ME_RAM_RADDR;
+typedef union CP_ME_RAM_DATA                    regCP_ME_RAM_DATA;
+typedef union CP_ME_RDADDR                      regCP_ME_RDADDR;
+typedef union CP_DEBUG                          regCP_DEBUG;
+typedef union SCRATCH_REG0                      regSCRATCH_REG0;
+typedef union GUI_SCRATCH_REG0                  regGUI_SCRATCH_REG0;
+typedef union SCRATCH_REG1                      regSCRATCH_REG1;
+typedef union GUI_SCRATCH_REG1                  regGUI_SCRATCH_REG1;
+typedef union SCRATCH_REG2                      regSCRATCH_REG2;
+typedef union GUI_SCRATCH_REG2                  regGUI_SCRATCH_REG2;
+typedef union SCRATCH_REG3                      regSCRATCH_REG3;
+typedef union GUI_SCRATCH_REG3                  regGUI_SCRATCH_REG3;
+typedef union SCRATCH_REG4                      regSCRATCH_REG4;
+typedef union GUI_SCRATCH_REG4                  regGUI_SCRATCH_REG4;
+typedef union SCRATCH_REG5                      regSCRATCH_REG5;
+typedef union GUI_SCRATCH_REG5                  regGUI_SCRATCH_REG5;
+typedef union SCRATCH_REG6                      regSCRATCH_REG6;
+typedef union GUI_SCRATCH_REG6                  regGUI_SCRATCH_REG6;
+typedef union SCRATCH_REG7                      regSCRATCH_REG7;
+typedef union GUI_SCRATCH_REG7                  regGUI_SCRATCH_REG7;
+typedef union SCRATCH_UMSK                      regSCRATCH_UMSK;
+typedef union SCRATCH_ADDR                      regSCRATCH_ADDR;
+typedef union CP_ME_VS_EVENT_SRC                regCP_ME_VS_EVENT_SRC;
+typedef union CP_ME_VS_EVENT_ADDR               regCP_ME_VS_EVENT_ADDR;
+typedef union CP_ME_VS_EVENT_DATA               regCP_ME_VS_EVENT_DATA;
+typedef union CP_ME_VS_EVENT_ADDR_SWM           regCP_ME_VS_EVENT_ADDR_SWM;
+typedef union CP_ME_VS_EVENT_DATA_SWM           regCP_ME_VS_EVENT_DATA_SWM;
+typedef union CP_ME_PS_EVENT_SRC                regCP_ME_PS_EVENT_SRC;
+typedef union CP_ME_PS_EVENT_ADDR               regCP_ME_PS_EVENT_ADDR;
+typedef union CP_ME_PS_EVENT_DATA               regCP_ME_PS_EVENT_DATA;
+typedef union CP_ME_PS_EVENT_ADDR_SWM           regCP_ME_PS_EVENT_ADDR_SWM;
+typedef union CP_ME_PS_EVENT_DATA_SWM           regCP_ME_PS_EVENT_DATA_SWM;
+typedef union CP_ME_CF_EVENT_SRC                regCP_ME_CF_EVENT_SRC;
+typedef union CP_ME_CF_EVENT_ADDR               regCP_ME_CF_EVENT_ADDR;
+typedef union CP_ME_CF_EVENT_DATA               regCP_ME_CF_EVENT_DATA;
+typedef union CP_ME_NRT_ADDR                    regCP_ME_NRT_ADDR;
+typedef union CP_ME_NRT_DATA                    regCP_ME_NRT_DATA;
+typedef union CP_ME_VS_FETCH_DONE_SRC           regCP_ME_VS_FETCH_DONE_SRC;
+typedef union CP_ME_VS_FETCH_DONE_ADDR          regCP_ME_VS_FETCH_DONE_ADDR;
+typedef union CP_ME_VS_FETCH_DONE_DATA          regCP_ME_VS_FETCH_DONE_DATA;
+typedef union CP_INT_CNTL                       regCP_INT_CNTL;
+typedef union CP_INT_STATUS                     regCP_INT_STATUS;
+typedef union CP_INT_ACK                        regCP_INT_ACK;
+typedef union CP_PFP_UCODE_ADDR                 regCP_PFP_UCODE_ADDR;
+typedef union CP_PFP_UCODE_DATA                 regCP_PFP_UCODE_DATA;
+typedef union CP_PERFMON_CNTL                   regCP_PERFMON_CNTL;
+typedef union CP_PERFCOUNTER_SELECT             regCP_PERFCOUNTER_SELECT;
+typedef union CP_PERFCOUNTER_LO                 regCP_PERFCOUNTER_LO;
+typedef union CP_PERFCOUNTER_HI                 regCP_PERFCOUNTER_HI;
+typedef union CP_BIN_MASK_LO                    regCP_BIN_MASK_LO;
+typedef union CP_BIN_MASK_HI                    regCP_BIN_MASK_HI;
+typedef union CP_BIN_SELECT_LO                  regCP_BIN_SELECT_LO;
+typedef union CP_BIN_SELECT_HI                  regCP_BIN_SELECT_HI;
+typedef union CP_NV_FLAGS_0                     regCP_NV_FLAGS_0;
+typedef union CP_NV_FLAGS_1                     regCP_NV_FLAGS_1;
+typedef union CP_NV_FLAGS_2                     regCP_NV_FLAGS_2;
+typedef union CP_NV_FLAGS_3                     regCP_NV_FLAGS_3;
+typedef union CP_STATE_DEBUG_INDEX              regCP_STATE_DEBUG_INDEX;
+typedef union CP_STATE_DEBUG_DATA               regCP_STATE_DEBUG_DATA;
+typedef union CP_PROG_COUNTER                   regCP_PROG_COUNTER;
+typedef union CP_STAT                           regCP_STAT;
+typedef union BIOS_0_SCRATCH                    regBIOS_0_SCRATCH;
+typedef union BIOS_1_SCRATCH                    regBIOS_1_SCRATCH;
+typedef union BIOS_2_SCRATCH                    regBIOS_2_SCRATCH;
+typedef union BIOS_3_SCRATCH                    regBIOS_3_SCRATCH;
+typedef union BIOS_4_SCRATCH                    regBIOS_4_SCRATCH;
+typedef union BIOS_5_SCRATCH                    regBIOS_5_SCRATCH;
+typedef union BIOS_6_SCRATCH                    regBIOS_6_SCRATCH;
+typedef union BIOS_7_SCRATCH                    regBIOS_7_SCRATCH;
+typedef union BIOS_8_SCRATCH                    regBIOS_8_SCRATCH;
+typedef union BIOS_9_SCRATCH                    regBIOS_9_SCRATCH;
+typedef union BIOS_10_SCRATCH                   regBIOS_10_SCRATCH;
+typedef union BIOS_11_SCRATCH                   regBIOS_11_SCRATCH;
+typedef union BIOS_12_SCRATCH                   regBIOS_12_SCRATCH;
+typedef union BIOS_13_SCRATCH                   regBIOS_13_SCRATCH;
+typedef union BIOS_14_SCRATCH                   regBIOS_14_SCRATCH;
+typedef union BIOS_15_SCRATCH                   regBIOS_15_SCRATCH;
+typedef union COHER_SIZE_PM4                    regCOHER_SIZE_PM4;
+typedef union COHER_BASE_PM4                    regCOHER_BASE_PM4;
+typedef union COHER_STATUS_PM4                  regCOHER_STATUS_PM4;
+typedef union COHER_SIZE_HOST                   regCOHER_SIZE_HOST;
+typedef union COHER_BASE_HOST                   regCOHER_BASE_HOST;
+typedef union COHER_STATUS_HOST                 regCOHER_STATUS_HOST;
+typedef union COHER_DEST_BASE_0                 regCOHER_DEST_BASE_0;
+typedef union COHER_DEST_BASE_1                 regCOHER_DEST_BASE_1;
+typedef union COHER_DEST_BASE_2                 regCOHER_DEST_BASE_2;
+typedef union COHER_DEST_BASE_3                 regCOHER_DEST_BASE_3;
+typedef union COHER_DEST_BASE_4                 regCOHER_DEST_BASE_4;
+typedef union COHER_DEST_BASE_5                 regCOHER_DEST_BASE_5;
+typedef union COHER_DEST_BASE_6                 regCOHER_DEST_BASE_6;
+typedef union COHER_DEST_BASE_7                 regCOHER_DEST_BASE_7;
+typedef union RB_SURFACE_INFO                   regRB_SURFACE_INFO;
+typedef union RB_COLOR_INFO                     regRB_COLOR_INFO;
+typedef union RB_DEPTH_INFO                     regRB_DEPTH_INFO;
+typedef union RB_STENCILREFMASK                 regRB_STENCILREFMASK;
+typedef union RB_ALPHA_REF                      regRB_ALPHA_REF;
+typedef union RB_COLOR_MASK                     regRB_COLOR_MASK;
+typedef union RB_BLEND_RED                      regRB_BLEND_RED;
+typedef union RB_BLEND_GREEN                    regRB_BLEND_GREEN;
+typedef union RB_BLEND_BLUE                     regRB_BLEND_BLUE;
+typedef union RB_BLEND_ALPHA                    regRB_BLEND_ALPHA;
+typedef union RB_FOG_COLOR                      regRB_FOG_COLOR;
+typedef union RB_STENCILREFMASK_BF              regRB_STENCILREFMASK_BF;
+typedef union RB_DEPTHCONTROL                   regRB_DEPTHCONTROL;
+typedef union RB_BLENDCONTROL                   regRB_BLENDCONTROL;
+typedef union RB_COLORCONTROL                   regRB_COLORCONTROL;
+typedef union RB_MODECONTROL                    regRB_MODECONTROL;
+typedef union RB_COLOR_DEST_MASK                regRB_COLOR_DEST_MASK;
+typedef union RB_COPY_CONTROL                   regRB_COPY_CONTROL;
+typedef union RB_COPY_DEST_BASE                 regRB_COPY_DEST_BASE;
+typedef union RB_COPY_DEST_PITCH                regRB_COPY_DEST_PITCH;
+typedef union RB_COPY_DEST_INFO                 regRB_COPY_DEST_INFO;
+typedef union RB_COPY_DEST_PIXEL_OFFSET         regRB_COPY_DEST_PIXEL_OFFSET;
+typedef union RB_DEPTH_CLEAR                    regRB_DEPTH_CLEAR;
+typedef union RB_SAMPLE_COUNT_CTL               regRB_SAMPLE_COUNT_CTL;
+typedef union RB_SAMPLE_COUNT_ADDR              regRB_SAMPLE_COUNT_ADDR;
+typedef union RB_BC_CONTROL                     regRB_BC_CONTROL;
+typedef union RB_EDRAM_INFO                     regRB_EDRAM_INFO;
+typedef union RB_CRC_RD_PORT                    regRB_CRC_RD_PORT;
+typedef union RB_CRC_CONTROL                    regRB_CRC_CONTROL;
+typedef union RB_CRC_MASK                       regRB_CRC_MASK;
+typedef union RB_PERFCOUNTER0_SELECT            regRB_PERFCOUNTER0_SELECT;
+typedef union RB_PERFCOUNTER0_LOW               regRB_PERFCOUNTER0_LOW;
+typedef union RB_PERFCOUNTER0_HI                regRB_PERFCOUNTER0_HI;
+typedef union RB_TOTAL_SAMPLES                  regRB_TOTAL_SAMPLES;
+typedef union RB_ZPASS_SAMPLES                  regRB_ZPASS_SAMPLES;
+typedef union RB_ZFAIL_SAMPLES                  regRB_ZFAIL_SAMPLES;
+typedef union RB_SFAIL_SAMPLES                  regRB_SFAIL_SAMPLES;
+typedef union RB_DEBUG_0                        regRB_DEBUG_0;
+typedef union RB_DEBUG_1                        regRB_DEBUG_1;
+typedef union RB_DEBUG_2                        regRB_DEBUG_2;
+typedef union RB_DEBUG_3                        regRB_DEBUG_3;
+typedef union RB_DEBUG_4                        regRB_DEBUG_4;
+typedef union RB_FLAG_CONTROL                   regRB_FLAG_CONTROL;
+typedef union RB_BC_SPARES                      regRB_BC_SPARES;
+typedef union BC_DUMMY_CRAYRB_ENUMS             regBC_DUMMY_CRAYRB_ENUMS;
+typedef union BC_DUMMY_CRAYRB_MOREENUMS         regBC_DUMMY_CRAYRB_MOREENUMS;
+#endif
diff --git a/drivers/mxc/amd-gpu/os/include/os_types.h b/drivers/mxc/amd-gpu/os/include/os_types.h
new file mode 100644
index 000000000000..e7ecd90f8952
--- /dev/null
+++ b/drivers/mxc/amd-gpu/os/include/os_types.h
@@ -0,0 +1,138 @@
+ /* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of QUALCOMM Incorporated nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __OSTYPES_H
+#define __OSTYPES_H
+
+//////////////////////////////////////////////////////////////////////////////
+//   status
+//////////////////////////////////////////////////////////////////////////////
+#define OS_SUCCESS                       0
+#define OS_FAILURE                      -1
+#define OS_FAILURE_SYSTEMERROR          -2
+#define OS_FAILURE_DEVICEERROR          -3
+#define OS_FAILURE_OUTOFMEM             -4
+#define OS_FAILURE_BADPARAM             -5
+#define OS_FAILURE_NOTSUPPORTED         -6
+#define OS_FAILURE_NOMOREAVAILABLE      -7
+#define OS_FAILURE_NOTINITIALIZED       -8
+#define OS_FAILURE_ALREADYINITIALIZED   -9
+#define OS_FAILURE_TIMEOUT              -10
+
+
+//////////////////////////////////////////////////////////////////////////////
+// inline
+//////////////////////////////////////////////////////////////////////////////
+#ifndef OSINLINE
+#ifdef _LINUX
+#define OSINLINE    static __inline
+#else
+#define OSINLINE    __inline
+#endif
+#endif // OSINLINE
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  values
+//////////////////////////////////////////////////////////////////////////////
+#define OS_INFINITE             0xFFFFFFFF
+#define OS_TLS_OUTOFINDEXES     0xFFFFFFFF
+#define OS_TRUE                         1
+#define OS_FALSE                        0
+
+#ifndef NULL
+#define NULL                    (void *)0x0
+#endif  // !NULL
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+
+//
+// oshandle_t
+//
+typedef void *          oshandle_t;
+#define OS_HANDLE_NULL  (oshandle_t)0x0
+
+//
+// os_sysinfo_t
+//
+typedef struct _os_sysinfo_t {
+    int     cpu_mhz;
+    int     cpu_type;
+    int     cpu_version;
+    int     os_type;
+    int     os_version;
+    int     sysmem_size;
+    int     page_size;
+    int     max_path;
+    int     tls_slots;
+    int     endianness;     // 0 == little_endian, 1 == big_endian
+} os_sysinfo_t;
+
+
+//
+// os_stats_t
+//
+#ifdef _LINUX
+typedef long long __int64;
+typedef unsigned long long __uint64;
+#else
+typedef unsigned __int64 __uint64;
+#endif
+
+typedef struct _os_stats_t {
+    __int64     heap_allocs;
+    __int64     heap_frees;
+    __int64     heap_alloc_bytes;
+    __int64     shared_heap_allocs;
+    __int64     shared_heap_frees;
+    __int64     shared_heap_alloc_bytes;
+    __int64     objects_alloc;
+    __int64     objects_free;
+} os_stats_t;
+
+
+typedef enum {
+    OS_PROTECTION_GLOBAL,   // inter process
+    OS_PROTECTION_LOCAL,    // process local
+    OS_PROTECTION_NONE,     // none
+} os_protection_t;
+
+typedef struct _os_cputimer_t {
+    int refcount;                   // Reference count
+    int enabled;                    // Counter is enabled
+    int size;                       // Number of counters
+    __int64  start_time;            // start time in cpu ticks
+    __int64  end_time;              // end time in cpu ticks
+    __int64  timer_frequency;       // cpu ticks per second
+    __int64  *counter_array;        // number of ticks for each counter
+} os_cputimer_t;
+
+#endif  // __OSTYPES_H
diff --git a/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h b/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h
new file mode 100644
index 000000000000..a02c396c22a9
--- /dev/null
+++ b/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h
@@ -0,0 +1,813 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __KOSAPI_H
+#define __KOSAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include "os_types.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//   entrypoint abstraction
+//////////////////////////////////////////////////////////////////////////////
+
+
+#if defined(_WIN32) && !defined (_WIN32_WCE) && !defined(__SYMBIAN32__)
+#define KOS_DLLEXPORT   __declspec(dllexport)
+#define KOS_DLLIMPORT   __declspec(dllimport)
+#elif defined(_WIN32) && defined (_WIN32_WCE)
+#define KOS_DLLEXPORT   __declspec(dllexport)   
+#define KOS_DLLIMPORT
+#else
+#define KOS_DLLEXPORT   extern
+#define KOS_DLLIMPORT   
+#endif // _WIN32
+
+
+//////////////////////////////////////////////////////////////////////////////
+//   KOS lib entrypoints
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __KOSLIB_EXPORTS
+#define KOS_API         KOS_DLLEXPORT
+#else
+#define KOS_API         KOS_DLLIMPORT
+#endif // __KOSLIB_EXPORTS
+
+//////////////////////////////////////////////////////////////////////////////
+//                             assert API
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void                    kos_assert_hook(const char* file, int line, int expression);
+
+#if defined(DEBUG) || defined(DBG) || defined (_DBG) || defined (_DEBUG)
+
+#if defined(_WIN32) && !defined(__SYMBIAN32__) || defined(_WIN32_WCE)
+#include <assert.h>
+#define KOS_ASSERT(expression)  assert(expression)
+#elif defined(_BREW)
+#include <assert.h>
+#define KOS_ASSERT(expression)  kos_assert_hook(__FILE__, __LINE__, expression)
+#elif defined(__SYMBIAN32__)
+//#include <assert.h>
+//#define   KOS_ASSERT(expression)  assert(expression)
+#define KOS_ASSERT(expression)  /**/
+#elif defined(__ARM__)
+#define KOS_ASSERT(expression)
+#elif defined(_LINUX)
+#define KOS_ASSERT(expression) //kos_assert_hook(__FILE__, __LINE__, (int)(expression))
+#endif
+
+#else
+
+#define KOS_ASSERT(expression)
+
+#endif // DEBUG || DBG || _DBG
+
+#if defined(_WIN32) && defined(_DEBUG) && !defined(_WIN32_WCE) && !defined(__SYMBIAN32__)
+#pragma warning ( push, 3 )
+#include <crtdbg.h>
+#pragma warning  (pop)
+#define KOS_MALLOC_DBG(size)    _malloc_dbg(size, _NORMAL_BLOCK, __FILE__, __LINE__)
+#else
+#define KOS_MALLOC_DBG(size)    kos_malloc(int size)
+#endif // _WIN32 _DEBUG
+
+#define kos_assert(expression)  KOS_ASSERT(expression)
+#define kos_malloc_dbg(size)    KOS_MALLOC_DBG(size)
+
+#ifdef UNDER_CE
+#define KOS_PAGE_SIZE 0x1000
+#endif
+
+typedef enum mutexIndex mutexIndex_t;
+//////////////////////////////////////////////////////////////////////////////
+//  Interprocess shared memory initialization 
+//////////////////////////////////////////////////////////////////////////////
+// TODO: still valid?
+KOS_API int             kos_sharedmem_create(unsigned int map_addr, unsigned int size);
+KOS_API int             kos_sharedmem_destroy(void);
+
+//////////////////////////////////////////////////////////////////////////////
+//  heap API (per process)
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate memory for a kernel side process.
+ *
+ *
+ * \param   int size    Amount of bytes to be allocated.
+ * \return  Pointer to the reserved memory, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_malloc(int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate memory for a kernel side process. Clears the reserved memory.
+ *
+ *
+ * \param   int num     Number of elements to allocate.
+ * \param   int size    Element size in bytes.
+ * \return  Pointer to the reserved memory, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_calloc(int num, int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Re-allocate an existing memory for a kernel side process.
+ *          Contents of the old block will be copied to the new block
+ *          taking the sizes of both blocks into account.
+ *
+ *
+ * \param   void* memblock  Pointer to the old memory block.
+ * \param   int size        Size of the new block in bytes.
+ * \return  Pointer to the new memory block, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_realloc(void* memblock, int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free a reserved memory block from the kernel side process.
+ *
+ *
+ * \param   void* memblock  Pointer to the memory block.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void            kos_free(void* memblock);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Enable automatic memory leak checking performed at program exit.
+ *
+ *
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void            kos_enable_memoryleakcheck(void);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  shared heap API (cross process)
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate memory that can be shared between user and kernel
+ *          side processes.
+ *
+ *
+ * \param   int size    Amount of bytes to be allocated.
+ * \return  Pointer to the new memory block, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_shared_malloc(int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate memory that can be shared between user and kernel
+ *          side processes. Clears the reserved memory.
+ *
+ *
+ * \param   int num Number of elements to allocate.
+ * \param   int size    Element size in bytes.
+ * \return  Pointer to the reserved memory, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_shared_calloc(int num, int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Re-allocate an existing user/kernel shared memory block.
+ *          Contents of the old block will be copied to the new block
+ *          taking the sizes of both blocks into account.
+ *
+ *
+ * \param   void* ptr   Pointer to the old memory block.
+ * \param   int size    Size of the new block in bytes.
+ * \return  Pointer to the new memory block, NULL if any error.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_shared_realloc(void* ptr, int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free a reserved shared memory block.
+ *
+ *
+ * \param   void* ptr   Pointer to the memory block.
+ *//*-------------------------------------------------------------------*/
+ KOS_API void           kos_shared_free(void* ptr);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  memory API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Copies the values of num bytes from the location pointed by src
+ *          directly to the memory block pointed by dst.
+ *
+ *
+ * \param   void* dst   Pointer to the destination memory block.
+ * \param   void* src   Pointer to the source memory block.
+ * \param   void* count Amount of bytes to copy.
+ * \return  Returns the dst pointer, NULL if any error.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_memcpy(void* dst, const void* src, int count);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Fills the destination memory block with the given value.
+ *
+ *
+ * \param   void* dst   Pointer to the destination memory block.
+ * \param   int value   Value to be written to each destination address.
+ * \param   void* count Number of bytes to be set to the value.
+ * \return  Returns the dst pointer, NULL if any error.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_memset(void* dst, int value, int count);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Compares two memory blocks.
+ *
+ *
+ * \param   void* dst   Pointer to the destination memory block.
+ * \param   void* src   Pointer to the source memory block.
+ * \param   void* count Number of bytes to compare.
+ * \return  Zero if identical, >0 if first nonmatching byte is greater in dst.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_memcmp(void* dst, void* src, int count);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  physical memory API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocates a physically contiguous memory block.
+ *
+ *
+ * \param   void** virt_addr    Pointer where to store the virtual address of the reserved block.
+ * \param   void** phys_addr    Pointer where to store the physical address of the reserved block.
+ * \param   int pages           Number of pages to reserve (default page size = 4096 bytes).
+ * \return  Zero if ok, othervise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_alloc_physical(void** virt_addr, void** phys_addr, int pages);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free a physically contiguous allocated memory block.
+ *
+ *
+ * \param   void* virt_addr     Virtual address of the memory block.
+ * \param   int pages           Number of pages.
+ * \return  Zero if ok, othervise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_free_physical(void* virt_addr, int pages);
+
+KOS_API void            kos_memoryfence(void);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  string API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Perform a string copy.
+ *
+ *
+ * \param   void* strdestination    Pointer to destination memory.
+ * \param   void* strsource     Pointer to the source string.
+ * \return  Zero if ok, othervise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API char*           kos_strcpy(char* strdestination, const char* strsource);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Perform a string copy with given length.
+ *
+ *
+ * \param   void* destination   Pointer to destination memory.
+ * \param   void* source        Pointer to the source string.
+ * \param   int length          Amount of bytes to copy.
+ * \return  Returns the destination pointer.
+ *//*-------------------------------------------------------------------*/
+KOS_API char*           kos_strncpy(char* destination, const char* source, int length);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Append source string to destination string.
+ *
+ *
+ * \param   void* strdestination    Pointer to destination string.
+ * \param   void* strsource         Pointer to the source string.
+ * \return  Returns the destination pointer.
+ *//*-------------------------------------------------------------------*/
+KOS_API char*           kos_strcat(char* strdestination, const char* strsource);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Compare two strings.
+ *
+ *
+ * \param   void* string1   Pointer to first string.
+ * \param   void* string2   Pointer to second string.
+ * \param   void* length    Number of bytes to compare.
+ * \return  Zero if identical, >0 if first string is lexically greater <0 if not.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_strcmp(const char* string1, const char* string2);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Compares two strings of given length.
+ *
+ *
+ * \param   void* string1   Pointer to first string.
+ * \param   void* string2   Pointer to second string.
+ * \param   void* length    Number of bytes to compare.
+ * \return  Zero if identical, >0 if first string is lexically greater <0 if not.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_strncmp(const char* string1, const char* string2, int length);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Calculates the length of a string..
+ *
+ *
+ * \param   void* string    Pointer to the string.
+ * \return  Lenght of the string in bytes.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_strlen(const char* string);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Convert an numeric ascii string to integer value.
+ *
+ *
+ * \param   void* string    Pointer to the string.
+ * \return  Integer value extracted from the string.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_atoi(const char* string);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Convert string to unsigned long integer.
+ *
+ *
+ * \param   void* nptr      Pointer to the string.
+ * \param   char** endptr   If not null, will be set to point to the next character after the number.
+ * \param   int base        Base defining the type of the numeric string.
+ * \return  Unsigned integer value extracted from the string.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_strtoul(const char* nptr, char** endptr, int base);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  sync API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Create a mutex instance.
+ *
+ *
+ * \param   void* name      Name string for the new mutex.
+ * \return  Returns a handle to the mutex.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_mutex_create(const char* name);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get a handle to an already existing mutex.
+ *
+ *
+ * \param   void* name      Name string for the new mutex.
+ * \return  Returns a handle to the mutex.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_mutex_open(const char* name);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free the given mutex.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_free(oshandle_t mutexhandle);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Lock the given mutex.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_lock(oshandle_t mutexhandle);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Try to lock the given mutex, if already locked returns immediately.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_locktry(oshandle_t mutexhandle);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Try to lock the given mutex by waiting for its release. Returns without locking if the
+ * mutex is already locked and cannot be acquired within the given period.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \param   int millisecondstowait  Time to wait for the mutex to be available.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_lockwait(oshandle_t mutexhandle, int millisecondstowait);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Unlock the given mutex.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_unlock(oshandle_t mutexhandle);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Increments (increases by one) the value of the specified 32-bit variable as an atomic operation.
+ *
+ *
+ * \param   int* ptr Pointer to the value to be incremented.
+ * \return  Returns the new incremented value.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_incr(int* ptr);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Decrements (decreases by one) the value of the specified 32-bit variable as an atomic operation.
+ *
+ *
+ * \param   int* ptr Pointer to the value to be decremented.
+ * \return  Returns the new decremented value.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_decr(int* ptr);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Atomic replacement of a value.
+ *
+ *
+ * \param   int* ptr Pointer to the value to be replaced.
+ * \param   int value The new value.
+ * \return  Returns the old value.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_xchg(int* ptr, int value);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Perform an atomic compare-and-exchange operation on the specified values. Compares the two specified 32-bit values and exchanges
+* with another 32-bit value based on the outcome of the comparison.
+ *
+ *
+ * \param   int* ptr Pointer to the value to be replaced.
+ * \param   int value The new value.
+ * \param   int compvalue Value to be compared with.
+ * \return  Returns the initial value of the first given parameter.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_compxchg(int* ptr, int value, int compvalue);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Atomic addition of two 32-bit values.
+ *
+ *
+ * \param   int* ptr Pointer to the target value.
+ * \param   int value Value to be added to the target.
+ * \return  Returns the initial value of the target.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_xchgadd(int* ptr, int value);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Create an event semaphore.
+ *
+ *
+ * \param   int a_manualReset Selection for performing reset manually (or by the system).
+ * \return  Returns an handle to the created semaphore.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_event_create(int a_manualReset);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Destroy an event semaphore.
+ *
+ *
+ * \param   oshandle_t a_event Handle to the semaphore.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_event_destroy(oshandle_t a_event);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Signal an event semaphore.
+ *
+ *
+ * \param   oshandle_t a_event Handle to the semaphore.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_event_signal(oshandle_t a_event);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Reset an event semaphore.
+ *
+ *
+ * \param   oshandle_t a_event Handle to the semaphore.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_event_reset(oshandle_t a_event);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Wait for an event semaphore to be freed and acquire it.
+ *
+ *
+ * \param   oshandle_t a_event Handle to the semaphore.
+ * \param   int a_milliSeconds Time to wait.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_event_wait(oshandle_t a_event, int a_milliSeconds);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  interrupt handler API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Enable an interrupt with specified id.
+ *
+ *
+ * \param   int interrupt   Identification number for the interrupt.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interrupt_enable(int interrupt);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Disable an interrupt with specified id.
+ *
+ *
+ * \param   int interrupt   Identification number for the interrupt.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interrupt_disable(int interrupt);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Set the callback function for an interrupt.
+ *
+ *
+ * \param   int interrupt   Identification number for the interrupt.
+ * \param   void* handler   Pointer to the callback function.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interrupt_setcallback(int interrupt, void* handler);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Remove a callback function from an interrupt.
+ *
+ *
+ * \param   int interrupt   Identification number for the interrupt.
+ * \param   void* handler   Pointer to the callback function.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interrupt_clearcallback(int interrupt, void* handler);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  thread and process API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate an entry from the thread local storage table.
+ *
+ *
+ * \return  Index of the reserved entry.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_tls_alloc(void);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free an entry from the thread local storage table.
+ *
+ *
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_tls_free(unsigned int tlsindex);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Read the value of an entry in the thread local storage table.
+ *
+ *
+ * \param   unsigned int tlsindex   Index of the entry.
+ * \return  Returns the value of the entry.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_tls_read(unsigned int tlsindex);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Write a value to an entry in the thread local storage table.
+ *
+ *
+ * \param   unsigned int tlsindex   Index of the entry.
+ * \param   void* tlsvalue          Value to be written.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_tls_write(unsigned int tlsindex, void* tlsvalue);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Put the thread to sleep for the given time period.
+ *
+ *
+ * \param   unsigned int milliseconds   Time in milliseconds.
+ *//*-------------------------------------------------------------------*/
+KOS_API void            kos_sleep(unsigned int milliseconds);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the id of the current process.
+ *
+ *
+ * \return  Returns the process id.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_process_getid(void);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the id of the current caller process.
+ *
+ *
+ * \return  Returns the caller process id.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_callerprocess_getid(void);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the id of the current thread.
+ *
+ *
+ * \return  Returns the thread id.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_thread_getid(void);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Create a new thread.
+ *
+ *
+ * \param   oshandle_t a_function Handle to the function to be executed in the thread.
+ * \param   unsigned int* a_threadId Pointer to a value where to store the ID of the new thread.
+ * \return  Returns an handle to the created thread.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_thread_create(oshandle_t a_function, unsigned int* a_threadId);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Destroy the given thread.
+ *
+ *
+ * \param   oshandle_t a_task Handle to the thread to be destroyed.
+ *//*-------------------------------------------------------------------*/
+KOS_API void            kos_thread_destroy( oshandle_t a_task );
+
+//////////////////////////////////////////////////////////////////////////////
+//  timing API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the current time as a timestamp.
+ *
+ *
+ * \return  Returns the timestamp.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_timestamp(void);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  libary API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Map the given library (not required an all OS'es).
+ *
+ *
+ * \param   char* libraryname   The name string of the lib.
+ * \return  Returns a handle for the lib.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_lib_map(char* libraryname);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Unmap the given library.
+ *
+ * \param   oshandle_t libhandle Handle to the lib.
+ * \return  Returns an error code incase of an error.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_lib_unmap(oshandle_t libhandle);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the address of a lib.
+ *
+ * \param   oshandle_t libhandle Handle to the lib.
+ * \return  Returns a pointer to the lib.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_lib_getaddr(oshandle_t libhandle, char* procname);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  query API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get device system info.
+ *
+ * \param   os_sysinfo_t* sysinfo   Pointer to the destination sysinfo structure.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_get_sysinfo(os_sysinfo_t* sysinfo);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get system status info.
+ *
+ * \param   os_stats_t* stats   Pointer to the destination stats structure.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_get_stats(os_stats_t* stats);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block start
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_syncblock_start(void);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block end
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_syncblock_end(void);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block start with argument
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int kos_syncblock_start_ex( mutexIndex_t a_index );
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block start with argument
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int kos_syncblock_end_ex( mutexIndex_t a_index );
+
+//////////////////////////////////////////////////////////////////////////////
+//  file API
+//////////////////////////////////////////////////////////////////////////////
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Opens a file
+ *
+ * \param   const char* filename    Name of the file to open.
+ * \param   const char* mode        Mode used for file opening. See fopen.
+ * \return  Returns file handle or NULL if error.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_fopen(const char* filename, const char* mode);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Writes to a file
+ *
+ * \param   oshandle_t file     Handle of the file to write to.
+ * \param   const char* format  Format string. See fprintf.
+ * \return  Returns the number of bytes written
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_fprintf(oshandle_t file, const char* format, ...);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Closes a file
+ *
+ * \param   oshandle_t file     Handle of the file to close.
+ * \return  Returns zero if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_fclose(oshandle_t file);
+
+#ifdef  __SYMBIAN32__
+KOS_API void kos_create_dfc(void);
+KOS_API void kos_signal_dfc(void);
+KOS_API void kos_enter_critical_section();
+KOS_API void kos_leave_critical_section();
+#endif  // __SYMBIAN32__
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif  // __KOSAPI_H
diff --git a/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c b/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c
new file mode 100644
index 000000000000..4ead84ffe0dc
--- /dev/null
+++ b/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c
@@ -0,0 +1,661 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/limits.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/mutex.h>
+#include <asm/atomic.h>
+#include <asm/current.h>
+#include <linux/sched.h>
+#include <linux/jiffies.h>
+#include <linux/kthread.h>
+#include "kos_libapi.h"
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+//#define KOS_STATS_ENABLE
+
+//////////////////////////////////////////////////////////////////////////////
+//  macros
+//////////////////////////////////////////////////////////////////////////////
+#define KOS_MALLOC(s)               kmalloc(s, GFP_KERNEL)
+#define KOS_CALLOC(num, size)       kcalloc(num, size, GFP_KERNEL)
+#define KOS_REALLOC(p, s)           krealloc(p, s, GFP_KERNEL)
+#define KOS_FREE(p)                 kfree(p); p = 0
+#define KOS_DBGFLAGS_SET(flag)
+
+//////////////////////////////////////////////////////////////////////////////
+// stats
+//////////////////////////////////////////////////////////////////////////////
+#ifdef KOS_STATS_ENABLE
+os_stats_t kos_stats = {0, 0, 0, 0, 0, 0, 0, 0};
+#define KOS_STATS(x) x
+#else
+#define KOS_STATS(x)
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+//  assert API
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void
+kos_assert_hook(const char* file, int line, int expression)
+{
+    if (expression)
+    {
+        return;
+    }
+    else
+    {
+        printk(KERN_ERR "Assertion failed at %s:%d!\n", file, line);
+        //BUG();
+    }
+
+    // put breakpoint here
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  heap API (per process)
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void*
+kos_malloc(int size)
+{
+    void* ptr = KOS_MALLOC(size);
+
+    KOS_ASSERT(ptr);
+    KOS_STATS(kos_stats.heap_allocs++);
+    KOS_STATS(kos_stats.heap_alloc_bytes += size);
+
+    return (ptr);
+}
+
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_calloc(int num, int size)
+{
+    void* ptr = KOS_CALLOC(num, size);
+
+    KOS_ASSERT(ptr);
+    KOS_STATS(kos_stats.heap_allocs++);
+    KOS_STATS(kos_stats.heap_alloc_bytes += (size * num));
+
+    return (ptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_realloc(void* ptr, int size)
+{
+    void* newptr;
+
+    KOS_ASSERT(ptr);
+    newptr = KOS_REALLOC(ptr, size);
+
+    KOS_ASSERT(newptr);
+
+    return (newptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_free(void* ptr)
+{
+    KOS_STATS(kos_stats.heap_frees++);
+
+    KOS_FREE(ptr);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  shared heap API (cross process)
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void*
+kos_shared_malloc(int size)
+{
+    void* ptr;
+
+    ptr = NULL; // shared alloc
+
+    KOS_ASSERT(ptr);
+    KOS_STATS(kos_stats.shared_heap_allocs++);
+    KOS_STATS(kos_stats.shared_heap_alloc_bytes += size);
+
+    return (ptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_shared_calloc(int num, int size)
+{
+    void* ptr;
+
+    ptr = NULL; // shared calloc
+
+    KOS_ASSERT(ptr);
+    KOS_STATS(kos_stats.shared_heap_allocs++);
+    KOS_STATS(kos_stats.shared_heap_alloc_bytes += (size * num));
+    return (ptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_shared_realloc(void* ptr, int size)
+{
+    void* newptr;
+    (void) ptr;      // unreferenced formal parameter
+    (void) size;     // unreferenced formal parameter
+
+    newptr = NULL; // shared realloc
+
+    KOS_ASSERT(newptr);
+
+    return (newptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_shared_free(void* ptr)
+{
+    (void) ptr;      // unreferenced formal parameter
+    KOS_ASSERT(0);   // not implemented
+
+    KOS_STATS(kos_stats.shared_heap_frees++);
+
+    // shared free
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  memory access API
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void*
+kos_memcpy(void* dst, const void* src, int count)
+{
+    KOS_ASSERT(src);
+    KOS_ASSERT(dst);
+    return memcpy(dst, src, count);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_memset(void* dst, int value, int count)
+{
+    KOS_ASSERT(dst);
+    return memset(dst, value, count);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_memcmp(void* dst, void* src, int count)
+{
+    KOS_ASSERT(src);
+    KOS_ASSERT(dst);
+    return memcmp(dst, src, count);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  physical memory API
+//////////////////////////////////////////////////////////////////////////////
+KOS_API int
+kos_alloc_physical(void** virt_addr, void** phys_addr, int pages)
+{
+    *virt_addr = dma_alloc_coherent(NULL, pages*PAGE_SIZE, (dma_addr_t*)*phys_addr, GFP_DMA | GFP_KERNEL);
+    return *virt_addr ? OS_SUCCESS : OS_FAILURE;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_free_physical(void* virt_addr, int pages)
+{
+    (void) virt_addr;      // unreferenced formal parameter
+    (void) pages;         // unreferenced formal parameter
+
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_map_physical(void** virt_addr, void** phys_addr, int pages)
+{
+    (void) virt_addr;      // unreferenced formal parameter
+    (void) phys_addr;     // unreferenced formal parameter
+    (void) pages;         // unreferenced formal parameter
+
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_unmap_physical(void* virt_addr, int pages)
+{
+    (void) virt_addr;      // unreferenced formal parameter
+    (void) pages;         // unreferenced formal parameter
+
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_memoryfence(void)
+{
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_enable_memoryleakcheck(void)
+{
+    // perform automatic leak checking at program exit
+    KOS_DBGFLAGS_SET(_CRTDBG_ALLOC_MEM_DF | _CRTDBG_LEAK_CHECK_DF);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  string API
+//////////////////////////////////////////////////////////////////////////////
+
+KOS_API char*
+kos_strcpy(char* strdestination, const char* strsource)
+{
+    KOS_ASSERT(strdestination);
+    KOS_ASSERT(strsource);
+    return strcpy(strdestination, strsource);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API char*
+kos_strncpy(char* destination, const char* source, int length)
+{
+    KOS_ASSERT(destination);
+    KOS_ASSERT(source);
+    return strncpy(destination, source, length);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API char*
+kos_strcat(char* strdestination, const char* strsource)
+{
+    KOS_ASSERT(strdestination);
+    KOS_ASSERT(strsource);
+    return strcat(strdestination, strsource);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_strcmp(const char* string1, const char* string2)
+{
+    KOS_ASSERT(string1);
+    KOS_ASSERT(string2);
+    return strcmp(string1, string2);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_strncmp(const char* string1, const char* string2, int length)
+{
+    KOS_ASSERT(string1);
+    KOS_ASSERT(string2);
+    return strncmp(string1, string2, length);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_strlen(const char* string)
+{
+    KOS_ASSERT(string);
+    return strlen(string);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  sync API
+//////////////////////////////////////////////////////////////////////////////
+
+KOS_API oshandle_t
+kos_mutex_create(const char *name)
+{
+	struct mutex *mutex = KOS_MALLOC(sizeof(struct mutex));
+	if (!mutex)
+		return 0;
+	mutex_init(mutex);
+	return mutex;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API oshandle_t
+kos_mutex_open(const char *name)
+{
+	// not implemented
+	return 0;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_mutex_free(oshandle_t mutexhandle)
+{
+	struct mutex *mutex = (struct mutex *)mutexhandle;
+	if (!mutex)
+		return OS_FAILURE;
+	KOS_FREE(mutex);
+	return OS_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_mutex_lock(oshandle_t mutexhandle)
+{
+	struct mutex *mutex = (struct mutex *)mutexhandle;
+	if (!mutex)
+		return OS_FAILURE;
+	if (mutex_lock_interruptible(mutex) == -EINTR)
+		return OS_FAILURE;
+	return OS_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_mutex_locktry(oshandle_t mutexhandle)
+{
+	struct mutex *mutex = (struct mutex *)mutexhandle;
+	if (!mutex)
+		return OS_FAILURE;
+	if (!mutex_trylock(mutex))
+		return OS_FAILURE;
+	return OS_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_mutex_unlock(oshandle_t mutexhandle)
+{
+	struct mutex *mutex = (struct mutex *)mutexhandle;
+	if (!mutex)
+		return OS_FAILURE;
+	KOS_ASSERT(mutex_is_locked(mutex));
+	mutex_unlock(mutex);
+	return OS_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API unsigned int
+kos_process_getid(void)
+{
+	return current->tgid;
+}
+
+//----------------------------------------------------------------------------
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Creates new event semaphore
+ * \param           uint32 a_manualReset
+ *                  When this param is zero, system automatically resets the
+ *                  event state to nonsignaled after waiting thread has been
+ *                  released
+ * \return          oshandle_t
+*//* ------------------------------------------------------------------- */
+KOS_API oshandle_t
+kos_event_create(int a_manualReset)
+{
+    struct completion *comp = KOS_MALLOC(sizeof(struct completion));
+
+    KOS_ASSERT(comp);
+    if(!comp)
+    {
+        return (oshandle_t)NULL;
+    }
+
+    init_completion(comp);
+
+    return (oshandle_t)comp;
+}
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Frees event semaphore
+ * \param           oshandle_t a_event, event semaphore
+ * \return          int
+*//* ------------------------------------------------------------------- */
+KOS_API int
+kos_event_destroy(oshandle_t a_event)
+{
+    struct completion *comp = (struct completion *)a_event;
+
+    KOS_ASSERT(comp);
+//  KOS_ASSERT(completion_done(comp));
+
+    KOS_FREE(comp);
+    return (OS_SUCCESS);
+}
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Signals event semaphore
+ * \param           oshandle_t a_event, event semaphore
+ * \return          int
+*//* ------------------------------------------------------------------- */
+KOS_API int
+kos_event_signal(oshandle_t a_event)
+{
+    struct completion *comp = (struct completion *)a_event;
+
+    KOS_ASSERT(comp);
+    complete_all(comp);     // perhaps complete_all?
+    return (OS_SUCCESS);
+}
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Resets event semaphore state to nonsignaled
+ * \param           oshandle_t a_event, event semaphore
+ * \return          int
+*//* ------------------------------------------------------------------- */
+KOS_API int
+kos_event_reset(oshandle_t a_event)
+{
+    struct completion *comp = (struct completion *)a_event;
+
+    KOS_ASSERT(comp);
+    INIT_COMPLETION(*comp);
+    return (OS_SUCCESS);
+}
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Waits event semaphore to be signaled
+ * \param           oshandle_t a_event, event semaphore
+ * \return          int
+*//* ------------------------------------------------------------------- */
+KOS_API int
+kos_event_wait(oshandle_t a_event, int a_milliSeconds)
+{
+    struct completion *comp = (struct completion *)a_event;
+
+    KOS_ASSERT(comp);
+    if(a_milliSeconds == OS_INFINITE)
+    {
+        wait_for_completion_killable(comp);
+    }
+    else
+    {
+        // should interpret milliseconds really to jiffies?
+        if(!wait_for_completion_timeout(comp, msecs_to_jiffies(a_milliSeconds)))
+        {
+            return (OS_FAILURE);
+        }
+    }
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_sleep(unsigned int milliseconds)
+{
+    msleep(milliseconds);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  query API
+//////////////////////////////////////////////////////////////////////////////
+
+static int
+kos_get_endianness(void)
+{
+    int  value;
+    char* ptr;
+
+    value = 0x01FFFF00;
+
+    ptr = (char*)&value;
+
+    KOS_ASSERT((*ptr == 0x00) || (*ptr == 0x01));
+
+    return (int)*ptr;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_get_sysinfo(os_sysinfo_t* sysinfo)
+{
+    KOS_ASSERT(sysinfo);
+    if (!sysinfo) return (OS_FAILURE);
+
+    sysinfo->cpu_mhz            = 0;
+    sysinfo->cpu_type           = 0;
+    sysinfo->cpu_version        = 0;
+    sysinfo->os_type            = 0;
+    sysinfo->os_version         = 0;
+    sysinfo->sysmem_size        = 0;
+    sysinfo->page_size          = 0x1000;
+    sysinfo->max_path           = PATH_MAX;
+//  sysinfo->tls_slots          = TLS_MINIMUM_AVAILABLE - 1;
+    sysinfo->endianness         = kos_get_endianness();
+
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef KOS_STATS_ENABLE
+KOS_API int
+kos_get_stats(os_stats_t* stats)
+{
+    kos_memcpy(stats, &kos_stats, sizeof(os_stats_t));
+    return (OS_SUCCESS);
+}
+#else
+KOS_API int
+kos_get_stats(os_stats_t* stats)
+{
+    return (OS_FAILURE);
+}
+#endif // KOS_STATS
+
+/*-------------------------------------------------------------------*//*!
+ * \brief Sync block API
+ *        Same mutex needed from different blocks of driver
+ *//*-------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block start
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+
+static struct mutex* syncblock_mutex = 0;
+
+KOS_API int kos_syncblock_start(void)
+{
+    int return_value;
+
+    if(!syncblock_mutex)
+    {
+        syncblock_mutex = kos_mutex_create("syncblock");
+    }
+
+    if(syncblock_mutex)
+    {
+        return_value = kos_mutex_lock(syncblock_mutex);
+    }
+    else
+    {
+        return_value = -1;
+    }
+
+    return return_value;
+}
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block end
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int kos_syncblock_end(void)
+{
+    int return_value;
+
+    if(syncblock_mutex)
+    {
+        return_value = kos_mutex_unlock(syncblock_mutex);
+    }
+    else
+    {
+        return_value = -1;
+    }
+
+    return return_value;
+}
+
+KOS_API oshandle_t kos_thread_create(oshandle_t a_function, unsigned int* a_threadId)
+{
+	struct task_struct *task = kthread_run(a_function, 0, "kos_thread_%p", a_threadId);
+	*a_threadId = (unsigned int)task;
+	return (oshandle_t)task;
+}
+
+KOS_API void kos_thread_destroy( oshandle_t a_task )
+{
+	kthread_stop((struct task_struct *)a_task);
+}
diff --git a/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_buildconfig.h b/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_buildconfig.h
new file mode 100644
index 000000000000..9cfe9fe5b3b8
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_buildconfig.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL__BUILDCONFIG_H
+#define __GSL__BUILDCONFIG_H
+
+#define GSL_BLD_G12
+
+#define GSL_LOCKING_COURSEGRAIN
+#define GSL_MMU_TRANSLATION_ENABLED
+//#define GSL_MMU_PAGETABLE_PERPROCESS
+
+#if defined(_WIN32_WCE) && (_WIN32_WCE >= 600)
+#define GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+#endif
+
+//#define GSL_LOG
+
+#define GSL_STATS_MEM
+#define GSL_STATS_RINGBUFFER
+#define GSL_STATS_MMU
+
+#define GSL_RB_USE_MEM_RPTR
+#define GSL_RB_USE_MEM_TIMESTAMP
+//#define GSL_RB_USE_WPTR_POLLING
+
+
+#define GSL_CALLER_PROCESS_MAX      10
+#define GSL_SHMEM_MAX_APERTURES     3
+
+#ifdef _WIN32
+#ifndef _CRT_SECURE_NO_DEPRECATE
+#define _CRT_SECURE_NO_DEPRECATE
+#endif
+#endif // _WIN32
+
+#endif // __GSL__BUILDCONFIG_H
diff --git a/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_config.h b/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_config.h
new file mode 100644
index 000000000000..58a38c608de9
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_config.h
@@ -0,0 +1,195 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL__CONFIG_H
+#define __GSL__CONFIG_H
+
+
+// ---------------------
+// G12 MH arbiter config
+// ---------------------
+static const REG_MH_ARBITER_CONFIG gsl_cfg_g12_mharb = 
+{
+    0x10,   // SAME_PAGE_LIMIT
+    0,      // SAME_PAGE_GRANULARITY 
+    1,      // L1_ARB_ENABLE
+    1,      // L1_ARB_HOLD_ENABLE
+    0,      // L2_ARB_CONTROL
+    1,      // PAGE_SIZE
+    1,      // TC_REORDER_ENABLE
+    1,      // TC_ARB_HOLD_ENABLE
+    0,      // IN_FLIGHT_LIMIT_ENABLE
+    0x8,    // IN_FLIGHT_LIMIT
+    1,      // CP_CLNT_ENABLE
+    1,      // VGT_CLNT_ENABLE
+    1,      // TC_CLNT_ENABLE
+    1,      // RB_CLNT_ENABLE
+    1,      // PA_CLNT_ENABLE
+};
+
+// -----------------------------
+// interrupt block register data
+// -----------------------------
+static const gsl_intrblock_reg_t gsl_cfg_intrblock_reg[GSL_INTR_BLOCK_COUNT] =
+{
+    {   // Yamato MH
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+    },
+    {   // Yamato CP
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+    },
+    {   // Yamato RBBM
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+    },
+    {   // Yamato SQ
+        0,
+        0,
+        0,
+        0,
+        0,
+        0
+    },
+    {   // G12
+        GSL_INTR_BLOCK_G12,
+        GSL_INTR_G12_MH,
+#ifndef _Z180
+        GSL_INTR_G12_FBC,
+#else
+        GSL_INTR_G12_FIFO,
+#endif //_Z180
+        (ADDR_VGC_IRQSTATUS >> 2),
+        (ADDR_VGC_IRQSTATUS >> 2),
+        (ADDR_VGC_IRQENABLE >> 2)
+    },
+    {   // G12 MH
+        GSL_INTR_BLOCK_G12_MH,
+        GSL_INTR_G12_MH_AXI_READ_ERROR,
+        GSL_INTR_G12_MH_MMU_PAGE_FAULT,
+        ADDR_MH_INTERRUPT_STATUS,       // G12 MH offsets are considered to be dword based, therefore no down shift
+        ADDR_MH_INTERRUPT_CLEAR,
+        ADDR_MH_INTERRUPT_MASK
+    },
+};
+
+// -----------------------
+// interrupt mask bit data
+// -----------------------
+static const int gsl_cfg_intr_mask[GSL_INTR_COUNT] =
+{
+    0,
+    0,
+    0,
+
+    0,
+    0,
+    0,
+    0,
+    0,
+    0,
+    0,
+    0,
+    0,
+
+    0,
+    0,
+    0,
+
+    0,
+    0,
+
+    (1 << VGC_IRQENABLE_MH_FSHIFT),
+    (1 << VGC_IRQENABLE_G2D_FSHIFT),
+    (1 << VGC_IRQENABLE_FIFO_FSHIFT),
+#ifndef _Z180
+    (1 << VGC_IRQENABLE_FBC_FSHIFT),
+#endif
+    0,
+    0,
+    0,
+};
+
+// -----------------
+// mmu register data
+// -----------------
+static const gsl_mmu_reg_t gsl_cfg_mmu_reg[GSL_DEVICE_MAX] =
+{
+    {   // Yamato
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+    },
+    {   // G12 - MH offsets are considered to be dword based, therefore no down shift
+        ADDR_MH_MMU_CONFIG,
+        ADDR_MH_MMU_MPU_BASE,
+        ADDR_MH_MMU_MPU_END,
+        ADDR_MH_MMU_VA_RANGE,
+        ADDR_MH_MMU_PT_BASE,
+        ADDR_MH_MMU_PAGE_FAULT,
+        ADDR_MH_MMU_TRAN_ERROR,
+        ADDR_MH_MMU_INVALIDATE,
+    }
+};
+
+// -----------------
+// mh interrupt data
+// -----------------
+static const gsl_mh_intr_t gsl_cfg_mh_intr[GSL_DEVICE_MAX] =
+{
+    {   // Yamato
+        0,
+        0,
+        0,
+    },
+    {   // G12
+        GSL_INTR_G12_MH_AXI_READ_ERROR,
+        GSL_INTR_G12_MH_AXI_WRITE_ERROR,
+        GSL_INTR_G12_MH_MMU_PAGE_FAULT,
+    }
+};
+
+#endif // __GSL__CONFIG_H
diff --git a/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_halconfig.h b/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_halconfig.h
new file mode 100644
index 000000000000..011041236013
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_halconfig.h
@@ -0,0 +1,63 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_HALCONFIG_H
+#define __GSL_HALCONFIG_H
+
+
+
+#define GSL_HAL_PLATFORM                "i.MX35G"
+
+
+#define GSL_HAL_GPUBASE_GMEM            0x00100000          // 1MB
+#define GSL_HAL_GPUBASE_GMEM_PHYS       0x20000000          // 1MB
+
+#define GSL_HAL_GPUBASE_REG_YDX         0x30000000
+#define GSL_HAL_GPUBASE_REG_G12         0x20000000
+
+#define GSL_HAL_SIZE_REG_YDX            0x00020000            // 128KB
+#define GSL_HAL_SIZE_REG_G12            0x00001000            // 4KB
+#define GSL_HAL_SIZE_GMEM               0x00040000          // 256KB - 0 to 384KB in 128KB increments
+
+#if defined(_LINUX) && defined(GSL_MMU_TRANSLATION_ENABLED)
+#define GSL_HAL_SHMEM_SIZE_EMEM1        0x02400000            // 36MB
+#define GSL_HAL_SHMEM_SIZE_EMEM2        0x00400000            // 4MB
+#define GSL_HAL_SHMEM_SIZE_PHYS         0x00400000            // 4MB
+#elif defined(_LINUX) //MX35 Linux can able to allocate only 4MB
+#define GSL_HAL_SHMEM_SIZE_EMEM1        0x00400000          // 4MB
+#define GSL_HAL_SHMEM_SIZE_EMEM2        0x00200000          // 2MB
+#define GSL_HAL_SHMEM_SIZE_PHYS         0x00200000          // 2MB
+#else //Not possible to allocate 24 MB on WinCE
+#define GSL_HAL_SHMEM_SIZE_EMEM1        0x00D00000          // 13MB
+#define GSL_HAL_SHMEM_SIZE_EMEM2        0x00200000          // 2MB
+#define GSL_HAL_SHMEM_SIZE_PHYS         0x00100000          // 1MB
+#endif
+
+#define MX35_G12_INTERRUPT              16
+
+#endif  // __GSL_HALCONFIG_H
diff --git a/drivers/mxc/amd-gpu/platform/hal/MX35/linux/gsl_hal.c b/drivers/mxc/amd-gpu/platform/hal/MX35/linux/gsl_hal.c
new file mode 100644
index 000000000000..294cd9eb5af9
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/MX35/linux/gsl_hal.c
@@ -0,0 +1,524 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl_hal.h"
+#include "gsl_halconfig.h"
+#include "gsl_linux_map.h"
+
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/vmalloc.h>
+
+#include <asm/atomic.h>
+#include <asm/uaccess.h>
+#include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
+
+//////////////////////////////////////////////////////////////////////////////
+// constants
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// defines
+//////////////////////////////////////////////////////////////////////////////
+
+#define GSL_HAL_MEM1                        0
+#define GSL_HAL_MEM2                        1   
+#define GSL_HAL_MEM3                        2
+
+//#define GSL_HAL_DEBUG
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+typedef struct _gsl_hal_t {
+    gsl_memregion_t z160_regspace;
+#if 0   
+    gsl_memregion_t z430_regspace;
+#endif  
+    gsl_memregion_t memchunk;
+    gsl_memregion_t memspace[GSL_SHMEM_MAX_APERTURES];
+} gsl_hal_t;
+
+//////////////////////////////////////////////////////////////////////////////
+//  functions
+//////////////////////////////////////////////////////////////////////////////
+
+KGSLHAL_API int
+kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[])
+{
+    //
+    // allocate physically contiguous memory
+    //
+    
+	int i;
+	void *va;
+
+	va = (void*)gsl_linux_map_alloc(virtaddr, numpages*PAGE_SIZE);
+
+	if (!va)
+		return (GSL_FAILURE_OUTOFMEM);
+
+	for(i = 0; i < numpages; i++)
+	{
+		scattergatterlist[i] = page_to_phys(vmalloc_to_page(va));
+		va += PAGE_SIZE;
+	}
+
+	return (GSL_SUCCESS);
+}
+
+// ---------------------------------------------------------------------------
+
+KGSLHAL_API int
+kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[])
+{
+    //
+    // free physical memory
+    //
+
+	gsl_linux_map_free(virtaddr);
+
+    return(GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KGSLHAL_API int 
+kgsl_hal_init(void)
+{
+    gsl_hal_t *hal;
+    unsigned long totalsize, mem1size;
+    unsigned int va, pa;
+
+    if (gsl_driver.hal)
+    {
+        return (GSL_FAILURE_ALREADYINITIALIZED);
+    }
+
+    gsl_driver.hal = (void *)kos_malloc(sizeof(gsl_hal_t));
+
+    if (!gsl_driver.hal)
+    {
+        return (GSL_FAILURE_OUTOFMEM);
+    }
+
+    kos_memset(gsl_driver.hal, 0, sizeof(gsl_hal_t));
+
+
+    // overlay structure on hal memory
+    hal = (gsl_hal_t *) gsl_driver.hal;
+
+#if 0
+    // setup register space
+    hal->z430_regspace.mmio_phys_base   = GSL_HAL_GPUBASE_REG_YDX;
+    hal->z430_regspace.sizebytes        = GSL_HAL_SIZE_REG_YDX;
+    hal->z430_regspace.mmio_virt_base   = (unsigned char*)ioremap(hal->z430_regspace.mmio_phys_base, hal->z430_regspace.sizebytes);
+
+    if (hal->z430_regspace.mmio_virt_base == NULL) 
+    {
+        return (GSL_FAILURE_SYSTEMERROR);
+    }
+
+#ifdef GSL_HAL_DEBUG
+    printk(KERN_INFO "%s: hal->z430_regspace.mmio_phys_base = 0x%p\n", __func__, (void*)hal->z430_regspace.mmio_phys_base);
+    printk(KERN_INFO "%s: hal->z430_regspace.mmio_virt_base = 0x%p\n", __func__, (void*)hal->z430_regspace.mmio_virt_base);
+    printk(KERN_INFO "%s: hal->z430_regspace.sizebytes      = 0x%08x\n", __func__, hal->z430_regspace.sizebytes);
+#endif
+#endif
+
+    hal->z160_regspace.mmio_phys_base   = GSL_HAL_GPUBASE_REG_G12;
+    hal->z160_regspace.sizebytes        = GSL_HAL_SIZE_REG_G12;
+    hal->z160_regspace.mmio_virt_base   = (unsigned char*)ioremap(hal->z160_regspace.mmio_phys_base, hal->z160_regspace.sizebytes);
+
+    if (hal->z160_regspace.mmio_virt_base == NULL) 
+    {
+        return (GSL_FAILURE_SYSTEMERROR);
+    }
+
+#ifdef GSL_HAL_DEBUG
+    printk(KERN_INFO "%s: hal->z160_regspace.mmio_phys_base = 0x%p\n", __func__, (void*)hal->z160_regspace.mmio_phys_base);
+    printk(KERN_INFO "%s: hal->z160_regspace.mmio_virt_base = 0x%p\n", __func__, (void*)hal->z160_regspace.mmio_virt_base);
+    printk(KERN_INFO "%s: hal->z160_regspace.sizebytes      = 0x%08x\n", __func__, hal->z160_regspace.sizebytes);
+#endif
+    
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+    totalsize = GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS;
+    mem1size = GSL_HAL_SHMEM_SIZE_EMEM1;
+#else
+    totalsize = GSL_HAL_SHMEM_SIZE_EMEM1 + GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS;
+	mem1size = GSL_HAL_SHMEM_SIZE_EMEM1;
+#endif
+
+    // allocate a single chunk of physical memory
+    va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL);
+    
+    if (va)
+    {
+        kos_memset((void *)va, 0, totalsize);
+    
+        hal->memchunk.mmio_virt_base = (void *)va;
+        hal->memchunk.mmio_phys_base = pa;
+        hal->memchunk.sizebytes      = totalsize;
+
+#ifdef GSL_HAL_DEBUG
+        printk(KERN_INFO "%s: hal->memchunk.mmio_phys_base = 0x%p\n", __func__, (void*)hal->memchunk.mmio_phys_base);
+        printk(KERN_INFO "%s: hal->memchunk.mmio_virt_base = 0x%p\n", __func__, (void*)hal->memchunk.mmio_virt_base);
+        printk(KERN_INFO "%s: hal->memchunk.sizebytes      = 0x%08x\n", __func__, hal->memchunk.sizebytes);
+#endif
+        
+        hal->memspace[GSL_HAL_MEM2].mmio_virt_base = (void *) va;
+        hal->memspace[GSL_HAL_MEM2].gpu_base       = pa;
+        hal->memspace[GSL_HAL_MEM2].sizebytes      = GSL_HAL_SHMEM_SIZE_EMEM2;
+        va += GSL_HAL_SHMEM_SIZE_EMEM2;
+        pa += GSL_HAL_SHMEM_SIZE_EMEM2;
+
+#ifdef GSL_HAL_DEBUG
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].gpu_base       = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM2].gpu_base);
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].mmio_virt_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM2].mmio_virt_base);
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].sizebytes      = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM2].sizebytes);
+#endif
+        
+        hal->memspace[GSL_HAL_MEM3].mmio_virt_base  = (void *) va;
+        hal->memspace[GSL_HAL_MEM3].gpu_base        = pa;
+        hal->memspace[GSL_HAL_MEM3].sizebytes       = GSL_HAL_SHMEM_SIZE_PHYS;
+        va += GSL_HAL_SHMEM_SIZE_PHYS;
+        pa += GSL_HAL_SHMEM_SIZE_PHYS;
+
+#ifdef GSL_HAL_DEBUG
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].gpu_base       = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM3].gpu_base);
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].mmio_virt_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM3].mmio_virt_base);
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].sizebytes      = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM3].sizebytes);
+#endif
+        
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+		gsl_linux_map_init();
+		hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *)GSL_LINUX_MAP_RANGE_START;
+		hal->memspace[GSL_HAL_MEM1].gpu_base       = GSL_LINUX_MAP_RANGE_START;
+		hal->memspace[GSL_HAL_MEM1].sizebytes      = mem1size;
+#else
+        hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *) va;
+        hal->memspace[GSL_HAL_MEM1].gpu_base       = pa;
+        hal->memspace[GSL_HAL_MEM1].sizebytes      = mem1size;
+#endif
+
+#ifdef GSL_HAL_DEBUG
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].gpu_base       = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM1].gpu_base);
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].mmio_virt_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM1].mmio_virt_base);
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].sizebytes      = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM1].sizebytes);
+#endif
+    }
+    else
+    {
+        kgsl_hal_close();
+        return (GSL_FAILURE_SYSTEMERROR);
+    }
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+KGSLHAL_API int 
+kgsl_hal_close(void)
+{
+    gsl_hal_t  *hal;
+
+    if (gsl_driver.hal)
+    {
+        // overlay structure on hal memory
+        hal = (gsl_hal_t *) gsl_driver.hal;
+
+        // unmap registers
+#if 0
+        if (hal->z430_regspace.mmio_virt_base)
+        {
+            iounmap(hal->z430_regspace.mmio_virt_base);
+        }
+#endif
+        if (hal->z160_regspace.mmio_virt_base)
+        {
+            iounmap(hal->z160_regspace.mmio_virt_base);
+        }
+        
+        // free physical block
+        if (hal->memchunk.mmio_virt_base)
+        {
+            dma_free_coherent(0, hal->memchunk.sizebytes, hal->memchunk.mmio_virt_base, hal->memchunk.mmio_phys_base);
+        }
+
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+		gsl_linux_map_destroy();
+#endif
+
+        // release hal struct
+        kos_memset(hal, 0, sizeof(gsl_hal_t));
+        kos_free(gsl_driver.hal);
+        gsl_driver.hal = NULL;
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KGSLHAL_API int
+kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config)
+{ 
+    int        status = GSL_FAILURE_DEVICEERROR;
+    gsl_hal_t  *hal   = (gsl_hal_t *) gsl_driver.hal;
+
+    kos_memset(config, 0, sizeof(gsl_shmemconfig_t));
+
+    if (hal)
+    {
+        config->numapertures = GSL_SHMEM_MAX_APERTURES;
+
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+        config->apertures[0].id        = GSL_APERTURE_MMU;
+#else
+        config->apertures[0].id        = GSL_APERTURE_EMEM;
+#endif
+        config->apertures[0].channel   = GSL_CHANNEL_1;
+        config->apertures[0].hostbase  = (unsigned int)hal->memspace[GSL_HAL_MEM1].mmio_virt_base;
+        config->apertures[0].gpubase   = hal->memspace[GSL_HAL_MEM1].gpu_base;
+        config->apertures[0].sizebytes = hal->memspace[GSL_HAL_MEM1].sizebytes;
+
+        config->apertures[1].id        = GSL_APERTURE_EMEM;
+        config->apertures[1].channel   = GSL_CHANNEL_2;
+        config->apertures[1].hostbase  = (unsigned int)hal->memspace[GSL_HAL_MEM2].mmio_virt_base;
+        config->apertures[1].gpubase   = hal->memspace[GSL_HAL_MEM2].gpu_base;
+        config->apertures[1].sizebytes = hal->memspace[GSL_HAL_MEM2].sizebytes;
+
+        config->apertures[2].id        = GSL_APERTURE_PHYS;
+        config->apertures[2].channel   = GSL_CHANNEL_1;
+        config->apertures[2].hostbase  = (unsigned int)hal->memspace[GSL_HAL_MEM3].mmio_virt_base;
+        config->apertures[2].gpubase   = hal->memspace[GSL_HAL_MEM3].gpu_base;
+        config->apertures[2].sizebytes = hal->memspace[GSL_HAL_MEM3].sizebytes;
+
+        status = GSL_SUCCESS;
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSLHAL_API int
+kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config)
+{ 
+    int        status = GSL_FAILURE_DEVICEERROR;
+    gsl_hal_t  *hal   = (gsl_hal_t *) gsl_driver.hal;
+
+    kos_memset(config, 0, sizeof(gsl_devconfig_t));
+
+    if (hal)
+    {
+        switch (device_id)
+        {
+            case GSL_DEVICE_YAMATO:
+            {
+#if 0           
+                mh_mmu_config_u      mmu_config   = {0};
+
+                config->gmemspace.gpu_base        = 0;
+                config->gmemspace.mmio_virt_base  = 0;
+                config->gmemspace.mmio_phys_base  = 0;
+                config->gmemspace.sizebytes       = GSL_HAL_SIZE_GMEM;
+
+                config->regspace.gpu_base         = 0;
+                config->regspace.mmio_virt_base   = (unsigned char *)hal->z430_regspace.mmio_virt_base;
+                config->regspace.mmio_phys_base   = (unsigned int) hal->z430_regspace.mmio_phys_base;
+                config->regspace.sizebytes        = GSL_HAL_SIZE_REG_YDX;
+
+                mmu_config.f.mmu_enable           = 1;
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+                mmu_config.f.split_mode_enable    = 0;
+                mmu_config.f.rb_w_clnt_behavior   = 1;
+                mmu_config.f.cp_w_clnt_behavior   = 1;
+                mmu_config.f.cp_r0_clnt_behavior  = 1;
+                mmu_config.f.cp_r1_clnt_behavior  = 1;
+                mmu_config.f.cp_r2_clnt_behavior  = 1;
+                mmu_config.f.cp_r3_clnt_behavior  = 1;
+                mmu_config.f.cp_r4_clnt_behavior  = 1;
+                mmu_config.f.vgt_r0_clnt_behavior = 1;
+                mmu_config.f.vgt_r1_clnt_behavior = 1;
+                mmu_config.f.tc_r_clnt_behavior   = 1;
+                mmu_config.f.pa_w_clnt_behavior   = 1;
+#endif // GSL_MMU_TRANSLATION_ENABLED
+
+                config->mmu_config                = mmu_config.val;
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+                config->va_base                   = hal->memspace[GSL_HAL_MEM1].gpu_base;
+                config->va_range                  = hal->memspace[GSL_HAL_MEM1].sizebytes;
+#else
+                config->va_base                   = 0x00000000;
+                config->va_range                  = 0x00000000;
+#endif // GSL_MMU_TRANSLATION_ENABLED
+        
+                // turn off memory protection unit by setting acceptable physical address range to include all pages
+                config->mpu_base                  = 0x00000000; // hal->memchunk.mmio_virt_base;
+                config->mpu_range                 = 0xFFFFF000; // hal->memchunk.sizebytes;
+
+                status = GSL_SUCCESS;
+#endif
+                break;
+            }
+
+            case GSL_DEVICE_G12:
+            {
+#ifndef GSL_MMU_TRANSLATION_ENABLED
+                unsigned int mmu_config = {0};
+#endif
+                config->regspace.gpu_base       = 0;
+                config->regspace.mmio_virt_base = (unsigned char *)hal->z160_regspace.mmio_virt_base;
+                config->regspace.mmio_phys_base = (unsigned int) hal->z160_regspace.mmio_phys_base;
+                config->regspace.sizebytes      = GSL_HAL_SIZE_REG_G12;
+
+                
+
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+                config->mmu_config              = 0x00555551;
+                config->va_base                 = hal->memspace[GSL_HAL_MEM1].gpu_base;
+                config->va_range                = hal->memspace[GSL_HAL_MEM1].sizebytes;
+#else
+                config->mmu_config              = mmu_config;
+                config->va_base                 = 0x00000000;
+                config->va_range                = 0x00000000;
+#endif // GSL_MMU_TRANSLATION_ENABLED
+
+                config->mpu_base                = 0x00000000; //(unsigned int) hal->memchunk.mmio_virt_base;
+                config->mpu_range               = 0xFFFFF000; //hal->memchunk.sizebytes;
+
+                status = GSL_SUCCESS;
+                break;
+            }
+
+            default:
+
+                break;
+        }
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+//
+// kgsl_hal_getchipid
+//
+// The proper platform method, build from RBBM_PERIPHIDx and RBBM_PATCH_RELEASE
+//
+KGSLHAL_API gsl_chipid_t
+kgsl_hal_getchipid(gsl_deviceid_t device_id)
+{
+    return (0);
+}
+
+//----------------------------------------------------------------------------
+
+KGSLHAL_API int 
+kgsl_hal_getplatformtype(char *platform)
+{
+    if (gsl_driver.hal)
+    {
+        kos_strcpy(platform, GSL_HAL_PLATFORM);
+        return (GSL_SUCCESS);
+    }
+    else
+    {
+        return (GSL_FAILURE_NOTINITIALIZED);
+    }
+}
+
+//---------------------------------------------------------------------------
+
+KGSLHAL_API int
+kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value)
+{
+	gsl_device_t *device = &gsl_driver.device[device_id-1];        // device_id is 1 based
+	struct clk *gpu_clk = 0;
+
+    // unreferenced formal parameters
+    (void) value;
+	
+	switch (device_id)
+	{
+	case GSL_DEVICE_G12:
+		gpu_clk = clk_get(0, "gpu2d_clk");
+		break;
+	default:
+		return (GSL_FAILURE_DEVICEERROR);
+	}
+	
+	if (!gpu_clk)
+		return (GSL_FAILURE_DEVICEERROR);
+
+    switch (state)
+    {
+	case GSL_PWRFLAGS_CLK_ON:
+	    break;
+	case GSL_PWRFLAGS_POWER_ON:
+		clk_enable(gpu_clk);
+		kgsl_device_autogate_init(&gsl_driver.device[device_id-1]);
+		break;
+	case GSL_PWRFLAGS_CLK_OFF:
+	    break;
+	case GSL_PWRFLAGS_POWER_OFF:
+		if (device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT) != GSL_SUCCESS)
+		{
+			return (GSL_FAILURE_DEVICEERROR);
+		}
+		kgsl_device_autogate_exit(&gsl_driver.device[device_id-1]);
+		clk_disable(gpu_clk);
+		break;
+	default:
+		break;
+    }
+	
+    return (GSL_SUCCESS);
+}
+
+KGSLHAL_API int kgsl_clock(gsl_deviceid_t dev, int enable)
+{
+	struct clk *gpu_clk = 0;
+
+	switch (dev)
+	{
+	case GSL_DEVICE_G12:
+		gpu_clk = clk_get(0, "gpu2d_clk");
+		break;
+	default:
+		printk(KERN_ERR "GPU device %d is invalid!\n", dev);
+		return (GSL_FAILURE_DEVICEERROR);
+	}
+
+	if (IS_ERR(gpu_clk)) {
+		printk(KERN_ERR "%s: GPU clock get failed!\n", __func__);
+		return (GSL_FAILURE_DEVICEERROR);
+	}
+
+	if (enable) 
+		clk_enable(gpu_clk);
+	else
+		clk_disable(gpu_clk);
+
+	return (GSL_SUCCESS);
+}
diff --git a/drivers/mxc/amd-gpu/platform/hal/MX35/memcfg/gsl_memcfg.c b/drivers/mxc/amd-gpu/platform/hal/MX35/memcfg/gsl_memcfg.c
new file mode 100644
index 000000000000..f3ca6191d7c2
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/MX35/memcfg/gsl_memcfg.c
@@ -0,0 +1,31 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "kos_libapi.h"
+
+//
+//  Return the maximum amount of memory that can be allocated to the Z160.  This number
+//  will be constrained to 2MB as a minimum and the original hardcoded value for the caller
+//  as a maximum.  If the return value is outside of this range, then the original value in 
+//  the caller will be used.  For this reason, returning 0 is used to signify to use the
+//  original value as the default.
+//
+KOS_DLLEXPORT unsigned long kgsl_get_z160_memory_amount(void)
+{
+    return(0);
+}
diff --git a/drivers/mxc/amd-gpu/platform/hal/MX35/memcfg/gsl_memcfg.h b/drivers/mxc/amd-gpu/platform/hal/MX35/memcfg/gsl_memcfg.h
new file mode 100644
index 000000000000..164a17c925c4
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/MX35/memcfg/gsl_memcfg.h
@@ -0,0 +1,41 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef GSL_MEMCFG_H
+#define GSL_MEMCFG_H
+
+//
+//  Return the maximum amount of memory that can be allocated to the Z430.  This number
+//  will be constrained to 2MB as a minimum and the original hardcoded value for the caller
+//  as a maximum.  If the return value is outside of this range, then the original value in 
+//  the caller will be used.  For this reason, returning 0 is used to signify to use the
+//  original value as the default.
+//
+KOS_DLLEXPORT unsigned long kgsl_get_z160_memory_amount(void);
+
+#endif
diff --git a/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_buildconfig.h b/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_buildconfig.h
new file mode 100644
index 000000000000..82824f511d5e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_buildconfig.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL__BUILDCONFIG_H
+#define __GSL__BUILDCONFIG_H
+
+#define GSL_BLD_YAMATO
+#define GSL_BLD_G12
+
+#define GSL_LOCKING_COURSEGRAIN
+
+#define GSL_STATS_MEM
+#define GSL_STATS_RINGBUFFER
+#define GSL_STATS_MMU
+
+#define GSL_RB_USE_MEM_RPTR
+#define GSL_RB_USE_MEM_TIMESTAMP
+#define GSL_RB_TIMESTAMP_INTERUPT
+//#define GSL_RB_USE_WPTR_POLLING
+
+#if defined(_WIN32_WCE) && (_WIN32_WCE >= 600)
+#define GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+#endif
+
+//#define GSL_MMU_TRANSLATION_ENABLED
+//#define GSL_MMU_PAGETABLE_PERPROCESS
+
+#define GSL_CALLER_PROCESS_MAX      10
+#define GSL_SHMEM_MAX_APERTURES     3
+
+#ifdef _WIN32
+#ifndef _CRT_SECURE_NO_DEPRECATE
+#define _CRT_SECURE_NO_DEPRECATE
+#endif
+#endif // _WIN32
+
+#endif // __GSL__BUILDCONFIG_H
diff --git a/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_config.h b/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_config.h
new file mode 100644
index 000000000000..6fad1d01277f
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_config.h
@@ -0,0 +1,222 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL__CONFIG_H
+#define __GSL__CONFIG_H
+
+// ------------------------
+// Yamato ringbuffer config
+// ------------------------
+static const unsigned int gsl_cfg_rb_sizelog2quadwords = GSL_RB_SIZE_32K;
+static const unsigned int gsl_cfg_rb_blksizequadwords  = GSL_RB_SIZE_16;
+
+// ------------------------
+// Yamato MH arbiter config
+// ------------------------
+static const mh_arbiter_config_t  gsl_cfg_yamato_mharb = 
+{
+    0x10,   // same_page_limit
+    0,      // same_page_granularity 
+    1,      // l1_arb_enable
+    1,      // l1_arb_hold_enable
+    0,      // l2_arb_control
+    1,      // page_size
+    1,      // tc_reorder_enable
+    1,      // tc_arb_hold_enable
+    1,      // in_flight_limit_enable
+    0x8,    // in_flight_limit
+    1,      // cp_clnt_enable
+    1,      // vgt_clnt_enable
+    1,      // tc_clnt_enable
+    1,      // rb_clnt_enable
+    1,      // pa_clnt_enable
+};
+
+// ---------------------
+// G12 MH arbiter config
+// ---------------------
+static const REG_MH_ARBITER_CONFIG gsl_cfg_g12_mharb = 
+{
+    0x10,   // SAME_PAGE_LIMIT
+    0,      // SAME_PAGE_GRANULARITY 
+    1,      // L1_ARB_ENABLE
+    1,      // L1_ARB_HOLD_ENABLE
+    0,      // L2_ARB_CONTROL
+    1,      // PAGE_SIZE
+    1,      // TC_REORDER_ENABLE
+    1,      // TC_ARB_HOLD_ENABLE
+    0,      // IN_FLIGHT_LIMIT_ENABLE
+    0x8,    // IN_FLIGHT_LIMIT
+    1,      // CP_CLNT_ENABLE
+    1,      // VGT_CLNT_ENABLE
+    1,      // TC_CLNT_ENABLE
+    1,      // RB_CLNT_ENABLE
+    1,      // PA_CLNT_ENABLE
+};
+
+// -----------------------------
+// interrupt block register data
+// -----------------------------
+static const gsl_intrblock_reg_t gsl_cfg_intrblock_reg[GSL_INTR_BLOCK_COUNT] =
+{
+    {   // Yamato MH
+        GSL_INTR_BLOCK_YDX_MH,
+        GSL_INTR_YDX_MH_AXI_READ_ERROR,
+        GSL_INTR_YDX_MH_MMU_PAGE_FAULT,
+        mmMH_INTERRUPT_STATUS,
+        mmMH_INTERRUPT_CLEAR,
+        mmMH_INTERRUPT_MASK
+    },
+    {   // Yamato CP
+        GSL_INTR_BLOCK_YDX_CP,
+        GSL_INTR_YDX_CP_SW_INT,
+        GSL_INTR_YDX_CP_RING_BUFFER,
+        mmCP_INT_STATUS,
+        mmCP_INT_ACK,
+        mmCP_INT_CNTL
+    },
+    {   // Yamato RBBM
+        GSL_INTR_BLOCK_YDX_RBBM,
+        GSL_INTR_YDX_RBBM_READ_ERROR,
+        GSL_INTR_YDX_RBBM_GUI_IDLE,
+        mmRBBM_INT_STATUS,
+        mmRBBM_INT_ACK,
+        mmRBBM_INT_CNTL
+    },
+    {   // Yamato SQ
+        GSL_INTR_BLOCK_YDX_SQ,
+        GSL_INTR_YDX_SQ_PS_WATCHDOG,
+        GSL_INTR_YDX_SQ_VS_WATCHDOG,
+        mmSQ_INT_STATUS,
+        mmSQ_INT_ACK,
+        mmSQ_INT_CNTL
+    },
+    {   // G12
+        GSL_INTR_BLOCK_G12,
+        GSL_INTR_G12_MH,
+#ifndef _Z180
+        GSL_INTR_G12_FBC,
+#else
+        GSL_INTR_G12_FIFO,
+#endif //_Z180
+        (ADDR_VGC_IRQSTATUS >> 2),
+        (ADDR_VGC_IRQSTATUS >> 2),
+        (ADDR_VGC_IRQENABLE >> 2)
+    },
+    {   // G12 MH
+        GSL_INTR_BLOCK_G12_MH,
+        GSL_INTR_G12_MH_AXI_READ_ERROR,
+        GSL_INTR_G12_MH_MMU_PAGE_FAULT,
+        ADDR_MH_INTERRUPT_STATUS,       // G12 MH offsets are considered to be dword based, therefore no down shift
+        ADDR_MH_INTERRUPT_CLEAR,
+        ADDR_MH_INTERRUPT_MASK
+    },
+};
+
+// -----------------------
+// interrupt mask bit data
+// -----------------------
+static const int gsl_cfg_intr_mask[GSL_INTR_COUNT] =
+{
+    MH_INTERRUPT_MASK__AXI_READ_ERROR,
+    MH_INTERRUPT_MASK__AXI_WRITE_ERROR,
+    MH_INTERRUPT_MASK__MMU_PAGE_FAULT,
+
+    CP_INT_CNTL__SW_INT_MASK,
+    CP_INT_CNTL__T0_PACKET_IN_IB_MASK,
+    CP_INT_CNTL__OPCODE_ERROR_MASK,
+    CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK,
+    CP_INT_CNTL__RESERVED_BIT_ERROR_MASK,
+    CP_INT_CNTL__IB_ERROR_MASK,
+    CP_INT_CNTL__IB2_INT_MASK,
+    CP_INT_CNTL__IB1_INT_MASK,
+    CP_INT_CNTL__RB_INT_MASK,
+
+    RBBM_INT_CNTL__RDERR_INT_MASK,
+    RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK,
+    RBBM_INT_CNTL__GUI_IDLE_INT_MASK,
+
+    SQ_INT_CNTL__PS_WATCHDOG_MASK,
+    SQ_INT_CNTL__VS_WATCHDOG_MASK,
+
+    (1 << VGC_IRQENABLE_MH_FSHIFT),
+    (1 << VGC_IRQENABLE_G2D_FSHIFT),
+    (1 << VGC_IRQENABLE_FIFO_FSHIFT),
+#ifndef _Z180
+    (1 << VGC_IRQENABLE_FBC_FSHIFT),
+#endif
+    (1 << MH_INTERRUPT_MASK_AXI_READ_ERROR_FSHIFT),
+    (1 << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FSHIFT),
+    (1 << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FSHIFT),
+};
+
+// -----------------
+// mmu register data
+// -----------------
+static const gsl_mmu_reg_t gsl_cfg_mmu_reg[GSL_DEVICE_MAX] =
+{
+    {   // Yamato
+        mmMH_MMU_CONFIG,
+        mmMH_MMU_MPU_BASE,
+        mmMH_MMU_MPU_END,
+        mmMH_MMU_VA_RANGE,
+        mmMH_MMU_PT_BASE,
+        mmMH_MMU_PAGE_FAULT,
+        mmMH_MMU_TRAN_ERROR,
+        mmMH_MMU_INVALIDATE,
+    },
+    {   // G12 - MH offsets are considered to be dword based, therefore no down shift
+        ADDR_MH_MMU_CONFIG,
+        ADDR_MH_MMU_MPU_BASE,
+        ADDR_MH_MMU_MPU_END,
+        ADDR_MH_MMU_VA_RANGE,
+        ADDR_MH_MMU_PT_BASE,
+        ADDR_MH_MMU_PAGE_FAULT,
+        ADDR_MH_MMU_TRAN_ERROR,
+        ADDR_MH_MMU_INVALIDATE,
+    }
+};
+
+// -----------------
+// mh interrupt data
+// -----------------
+static const gsl_mh_intr_t gsl_cfg_mh_intr[GSL_DEVICE_MAX] =
+{
+    {   // Yamato
+        GSL_INTR_YDX_MH_AXI_READ_ERROR,
+        GSL_INTR_YDX_MH_AXI_WRITE_ERROR,
+        GSL_INTR_YDX_MH_MMU_PAGE_FAULT,
+    },
+    {   // G12
+        GSL_INTR_G12_MH_AXI_READ_ERROR,
+        GSL_INTR_G12_MH_AXI_WRITE_ERROR,
+        GSL_INTR_G12_MH_MMU_PAGE_FAULT,
+    }
+};
+
+#endif // __GSL__CONFIG_H
diff --git a/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_halconfig.h b/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_halconfig.h
new file mode 100644
index 000000000000..589c56fa9bfa
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_halconfig.h
@@ -0,0 +1,58 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_HALCONFIG_H
+#define __GSL_HALCONFIG_H
+
+
+#define GSL_HAL_PLATFORM                "i.MX51"
+
+#define GSL_HAL_GPUBASE_GMEM            0x00100000            // 1MB
+#define GSL_HAL_GPUBASE_GMEM_PHYS       0x20000000            // 1MB
+
+#define GSL_HAL_GPUBASE_REG_YDX         0x30000000
+#define GSL_HAL_GPUBASE_REG_G12         0xD0000000
+
+#define GSL_HAL_SIZE_REG_YDX            0x00020000            // 128KB
+#define GSL_HAL_SIZE_REG_G12            0x00001000            // 4KB
+#define GSL_HAL_SIZE_GMEM               0x00020000            // 128KB - 0 to 384KB in 128KB increments
+
+#if defined(GSL_MMU_TRANSLATION_ENABLED)
+#define GSL_HAL_SHMEM_SIZE_EMEM1        0x02400000            // 36MB
+#define GSL_HAL_SHMEM_SIZE_EMEM2        0x00400000            // 4MB
+#define GSL_HAL_SHMEM_SIZE_PHYS         0x00400000            // 4MB
+#else
+#define GSL_HAL_SHMEM_SIZE_EMEM1        0x00D00000            // 13MB
+#define GSL_HAL_SHMEM_SIZE_EMEM2        0x00200000            // 2MB
+#define GSL_HAL_SHMEM_SIZE_PHYS         0x00100000            // 1MB
+#endif
+
+#define MX51_G12_INTERRUPT              84                    // Interrupt line taken from Reference Manual
+#define MX51_YDX_INTERRUPT              12                    // Interrupt line taken from Reference Manual
+
+#endif  // __GSL_HALCONFIG_H
diff --git a/drivers/mxc/amd-gpu/platform/hal/MX51/linux/gsl_hal.c b/drivers/mxc/amd-gpu/platform/hal/MX51/linux/gsl_hal.c
new file mode 100644
index 000000000000..965416b59ec1
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/MX51/linux/gsl_hal.c
@@ -0,0 +1,598 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl_hal.h"
+#include "gsl_halconfig.h"
+#include "gsl_memcfg.h"
+#include "gsl_linux_map.h"
+
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/vmalloc.h>
+
+#include <asm/atomic.h>
+#include <asm/uaccess.h>
+#include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
+
+//////////////////////////////////////////////////////////////////////////////
+// constants
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// defines
+//////////////////////////////////////////////////////////////////////////////
+
+#define GSL_HAL_MEM1                        0
+#define GSL_HAL_MEM2                        1   
+#define GSL_HAL_MEM3                        2
+
+//#define GSL_HAL_DEBUG
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+typedef struct _gsl_hal_t {
+    gsl_memregion_t z160_regspace;
+    gsl_memregion_t z430_regspace;
+    gsl_memregion_t memchunk;
+    gsl_memregion_t memspace[GSL_SHMEM_MAX_APERTURES];
+} gsl_hal_t;
+
+extern phys_addr_t gpu_2d_regbase;
+extern int gpu_2d_regsize;
+extern phys_addr_t gpu_3d_regbase;
+extern int gpu_3d_regsize;
+extern int gmem_size;
+extern phys_addr_t gpu_reserved_mem;
+extern int gpu_reserved_mem_size;
+
+//////////////////////////////////////////////////////////////////////////////
+//  functions
+//////////////////////////////////////////////////////////////////////////////
+
+KGSLHAL_API int
+kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[])
+{
+    //
+    // allocate physically contiguous memory
+    //
+    
+	int i;
+	void *va;
+
+	va = gsl_linux_map_alloc(virtaddr, numpages*PAGE_SIZE);
+
+	if (!va)
+		return (GSL_FAILURE_OUTOFMEM);
+
+	for(i = 0; i < numpages; i++)
+	{
+		scattergatterlist[i] = page_to_phys(vmalloc_to_page(va));
+		va += PAGE_SIZE;
+	}
+
+	return (GSL_SUCCESS);
+}
+
+// ---------------------------------------------------------------------------
+
+KGSLHAL_API int
+kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[])
+{
+    //
+    // free physical memory
+    //
+
+	gsl_linux_map_free(virtaddr);
+
+    return(GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KGSLHAL_API int 
+kgsl_hal_init(void)
+{
+    gsl_hal_t *hal;
+    unsigned long totalsize, mem1size;
+    unsigned int va, pa;
+
+    if (gsl_driver.hal)
+    {
+        return (GSL_FAILURE_ALREADYINITIALIZED);
+    }
+
+    gsl_driver.hal = (void *)kos_malloc(sizeof(gsl_hal_t));
+
+    if (!gsl_driver.hal)
+    {
+        return (GSL_FAILURE_OUTOFMEM);
+    }
+
+    kos_memset(gsl_driver.hal, 0, sizeof(gsl_hal_t));
+
+
+    // overlay structure on hal memory
+    hal = (gsl_hal_t *) gsl_driver.hal;
+
+    // setup register space
+    if(gpu_3d_regbase && gpu_3d_regsize){
+        hal->z430_regspace.mmio_phys_base = gpu_3d_regbase;
+        hal->z430_regspace.sizebytes = gpu_3d_regsize;
+    }else{
+        hal->z430_regspace.mmio_phys_base   = GSL_HAL_GPUBASE_REG_YDX;
+        hal->z430_regspace.sizebytes        = GSL_HAL_SIZE_REG_YDX;
+    }
+    hal->z430_regspace.mmio_virt_base   = (unsigned char*)ioremap(hal->z430_regspace.mmio_phys_base, hal->z430_regspace.sizebytes);
+
+    if (hal->z430_regspace.mmio_virt_base == NULL) 
+    {
+        return (GSL_FAILURE_SYSTEMERROR);
+    }
+
+#ifdef GSL_HAL_DEBUG
+    printk(KERN_INFO "%s: hal->z430_regspace.mmio_phys_base = 0x%p\n", __func__, (void*)hal->z430_regspace.mmio_phys_base);
+    printk(KERN_INFO "%s: hal->z430_regspace.mmio_virt_base = 0x%p\n", __func__, (void*)hal->z430_regspace.mmio_virt_base);
+    printk(KERN_INFO "%s: hal->z430_regspace.sizebytes      = 0x%08x\n", __func__, hal->z430_regspace.sizebytes);
+#endif
+
+    if(gpu_2d_regbase && gpu_2d_regsize){
+        hal->z160_regspace.mmio_phys_base = gpu_2d_regbase;
+        hal->z160_regspace.sizebytes = gpu_2d_regsize;
+    }else{
+        hal->z160_regspace.mmio_phys_base   = GSL_HAL_GPUBASE_REG_G12;
+        hal->z160_regspace.sizebytes        = GSL_HAL_SIZE_REG_G12;
+    }
+    hal->z160_regspace.mmio_virt_base   = (unsigned char*)ioremap(hal->z160_regspace.mmio_phys_base, hal->z160_regspace.sizebytes);
+
+    if (hal->z160_regspace.mmio_virt_base == NULL) 
+    {
+        return (GSL_FAILURE_SYSTEMERROR);
+    }
+
+#ifdef GSL_HAL_DEBUG
+    printk(KERN_INFO "%s: hal->z160_regspace.mmio_phys_base = 0x%p\n", __func__, (void*)hal->z160_regspace.mmio_phys_base);
+    printk(KERN_INFO "%s: hal->z160_regspace.mmio_virt_base = 0x%p\n", __func__, (void*)hal->z160_regspace.mmio_virt_base);
+    printk(KERN_INFO "%s: hal->z160_regspace.sizebytes      = 0x%08x\n", __func__, hal->z160_regspace.sizebytes);
+#endif
+    
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+    totalsize = GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS;
+    mem1size = GSL_HAL_SHMEM_SIZE_EMEM1;
+    if (gpu_reserved_mem && gpu_reserved_mem_size >= totalsize)
+    {
+        pa = gpu_reserved_mem;
+        va = (unsigned int)ioremap(gpu_reserved_mem, totalsize);
+    }
+    else
+    {
+        va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL);
+    }
+#else
+    if(gpu_reserved_mem && gpu_reserved_mem_size >= SZ_8M){
+        totalsize = gpu_reserved_mem_size;
+        pa = gpu_reserved_mem;
+        va = (unsigned int)ioremap(gpu_reserved_mem, gpu_reserved_mem_size);
+    }else{
+        gpu_reserved_mem = 0;
+        totalsize = GSL_HAL_SHMEM_SIZE_EMEM1 + GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS;
+        va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL);
+    }
+    mem1size = totalsize - (GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS);
+#endif
+    
+    if (va)
+    {
+        kos_memset((void *)va, 0, totalsize);
+    
+        hal->memchunk.mmio_virt_base = (void *)va;
+        hal->memchunk.mmio_phys_base = pa;
+        hal->memchunk.sizebytes      = totalsize;
+
+#ifdef GSL_HAL_DEBUG
+        printk(KERN_INFO "%s: hal->memchunk.mmio_phys_base = 0x%p\n", __func__, (void*)hal->memchunk.mmio_phys_base);
+        printk(KERN_INFO "%s: hal->memchunk.mmio_virt_base = 0x%p\n", __func__, (void*)hal->memchunk.mmio_virt_base);
+        printk(KERN_INFO "%s: hal->memchunk.sizebytes      = 0x%08x\n", __func__, hal->memchunk.sizebytes);
+#endif
+        
+        hal->memspace[GSL_HAL_MEM2].mmio_virt_base = (void *) va;
+        hal->memspace[GSL_HAL_MEM2].gpu_base       = pa;
+        hal->memspace[GSL_HAL_MEM2].sizebytes      = GSL_HAL_SHMEM_SIZE_EMEM2;
+        va += GSL_HAL_SHMEM_SIZE_EMEM2;
+        pa += GSL_HAL_SHMEM_SIZE_EMEM2;
+
+#ifdef GSL_HAL_DEBUG
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].gpu_base       = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM2].gpu_base);
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].mmio_virt_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM2].mmio_virt_base);
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].sizebytes      = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM2].sizebytes);
+#endif
+        
+        hal->memspace[GSL_HAL_MEM3].mmio_virt_base  = (void *) va;
+        hal->memspace[GSL_HAL_MEM3].gpu_base        = pa;
+        hal->memspace[GSL_HAL_MEM3].sizebytes       = GSL_HAL_SHMEM_SIZE_PHYS;
+        va += GSL_HAL_SHMEM_SIZE_PHYS;
+        pa += GSL_HAL_SHMEM_SIZE_PHYS;
+
+#ifdef GSL_HAL_DEBUG
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].gpu_base       = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM3].gpu_base);
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].mmio_virt_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM3].mmio_virt_base);
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].sizebytes      = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM3].sizebytes);
+#endif
+        
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+        gsl_linux_map_init();
+        hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *)GSL_LINUX_MAP_RANGE_START;
+        hal->memspace[GSL_HAL_MEM1].gpu_base       = GSL_LINUX_MAP_RANGE_START;
+        hal->memspace[GSL_HAL_MEM1].sizebytes      = mem1size;
+#else
+        hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *) va;
+        hal->memspace[GSL_HAL_MEM1].gpu_base       = pa;
+        hal->memspace[GSL_HAL_MEM1].sizebytes      = mem1size;
+#endif
+
+#ifdef GSL_HAL_DEBUG
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].gpu_base       = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM1].gpu_base);
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].mmio_virt_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM1].mmio_virt_base);
+        printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].sizebytes      = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM1].sizebytes);
+#endif
+    }
+    else
+    {
+        kgsl_hal_close();
+        return (GSL_FAILURE_SYSTEMERROR);
+    }
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+KGSLHAL_API int 
+kgsl_hal_close(void)
+{
+    gsl_hal_t  *hal;
+
+    if (gsl_driver.hal)
+    {
+        // overlay structure on hal memory
+        hal = (gsl_hal_t *) gsl_driver.hal;
+
+        // unmap registers
+        if (hal->z430_regspace.mmio_virt_base)
+        {
+            iounmap(hal->z430_regspace.mmio_virt_base);
+        }
+        if (hal->z160_regspace.mmio_virt_base)
+        {
+            iounmap(hal->z160_regspace.mmio_virt_base);
+        }
+        
+        // free physical block
+        if (hal->memchunk.mmio_virt_base && gpu_reserved_mem)
+        {
+            iounmap(hal->memchunk.mmio_virt_base);
+        }
+        else
+        {
+            dma_free_coherent(0, hal->memchunk.sizebytes, hal->memchunk.mmio_virt_base, hal->memchunk.mmio_phys_base);
+        }
+
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+		gsl_linux_map_destroy();
+#endif
+
+        // release hal struct
+        kos_memset(hal, 0, sizeof(gsl_hal_t));
+        kos_free(gsl_driver.hal);
+        gsl_driver.hal = NULL;
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KGSLHAL_API int
+kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config)
+{ 
+    int        status = GSL_FAILURE_DEVICEERROR;
+    gsl_hal_t  *hal   = (gsl_hal_t *) gsl_driver.hal;
+
+    kos_memset(config, 0, sizeof(gsl_shmemconfig_t));
+
+    if (hal)
+    {
+        config->numapertures = GSL_SHMEM_MAX_APERTURES;
+
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+        config->apertures[0].id        = GSL_APERTURE_MMU;
+#else
+        config->apertures[0].id        = GSL_APERTURE_EMEM;
+#endif
+        config->apertures[0].channel   = GSL_CHANNEL_1;
+        config->apertures[0].hostbase  = (unsigned int)hal->memspace[GSL_HAL_MEM1].mmio_virt_base;
+        config->apertures[0].gpubase   = hal->memspace[GSL_HAL_MEM1].gpu_base;
+        config->apertures[0].sizebytes = hal->memspace[GSL_HAL_MEM1].sizebytes;
+
+        config->apertures[1].id        = GSL_APERTURE_EMEM;
+        config->apertures[1].channel   = GSL_CHANNEL_2;
+        config->apertures[1].hostbase  = (unsigned int)hal->memspace[GSL_HAL_MEM2].mmio_virt_base;
+        config->apertures[1].gpubase   = hal->memspace[GSL_HAL_MEM2].gpu_base;
+        config->apertures[1].sizebytes = hal->memspace[GSL_HAL_MEM2].sizebytes;
+
+        config->apertures[2].id        = GSL_APERTURE_PHYS;
+        config->apertures[2].channel   = GSL_CHANNEL_1;
+        config->apertures[2].hostbase  = (unsigned int)hal->memspace[GSL_HAL_MEM3].mmio_virt_base;
+        config->apertures[2].gpubase   = hal->memspace[GSL_HAL_MEM3].gpu_base;
+        config->apertures[2].sizebytes = hal->memspace[GSL_HAL_MEM3].sizebytes;
+
+        status = GSL_SUCCESS;
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSLHAL_API int
+kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config)
+{ 
+    int        status = GSL_FAILURE_DEVICEERROR;
+    gsl_hal_t  *hal   = (gsl_hal_t *) gsl_driver.hal;
+
+    kos_memset(config, 0, sizeof(gsl_devconfig_t));
+
+    if (hal)
+    {
+        switch (device_id)
+        {
+            case GSL_DEVICE_YAMATO:
+            {
+                mh_mmu_config_u      mmu_config   = {0};
+
+                config->gmemspace.gpu_base        = 0;
+                config->gmemspace.mmio_virt_base  = 0;
+                config->gmemspace.mmio_phys_base  = 0;
+                if(gmem_size){
+                    config->gmemspace.sizebytes = gmem_size;
+                }else{
+                    config->gmemspace.sizebytes = GSL_HAL_SIZE_GMEM;
+                }
+
+                config->regspace.gpu_base         = 0;
+                config->regspace.mmio_virt_base   = (unsigned char *)hal->z430_regspace.mmio_virt_base;
+                config->regspace.mmio_phys_base   = (unsigned int) hal->z430_regspace.mmio_phys_base;
+                config->regspace.sizebytes        = GSL_HAL_SIZE_REG_YDX;
+
+                mmu_config.f.mmu_enable           = 1;
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+                mmu_config.f.split_mode_enable    = 0;
+                mmu_config.f.rb_w_clnt_behavior   = 1;
+                mmu_config.f.cp_w_clnt_behavior   = 1;
+                mmu_config.f.cp_r0_clnt_behavior  = 1;
+                mmu_config.f.cp_r1_clnt_behavior  = 1;
+                mmu_config.f.cp_r2_clnt_behavior  = 1;
+                mmu_config.f.cp_r3_clnt_behavior  = 1;
+                mmu_config.f.cp_r4_clnt_behavior  = 1;
+                mmu_config.f.vgt_r0_clnt_behavior = 1;
+                mmu_config.f.vgt_r1_clnt_behavior = 1;
+                mmu_config.f.tc_r_clnt_behavior   = 1;
+                mmu_config.f.pa_w_clnt_behavior   = 1;
+#endif // GSL_MMU_TRANSLATION_ENABLED
+
+                config->mmu_config                = mmu_config.val;
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+                config->va_base                   = hal->memspace[GSL_HAL_MEM1].gpu_base;
+                config->va_range                  = hal->memspace[GSL_HAL_MEM1].sizebytes;
+#else
+                config->va_base                   = 0x00000000;
+                config->va_range                  = 0x00000000;
+#endif // GSL_MMU_TRANSLATION_ENABLED
+        
+                // turn off memory protection unit by setting acceptable physical address range to include all pages
+                config->mpu_base                  = 0x00000000; // hal->memchunk.mmio_virt_base;
+                config->mpu_range                 = 0xFFFFF000; // hal->memchunk.sizebytes;
+
+                status = GSL_SUCCESS;
+                break;
+            }
+
+            case GSL_DEVICE_G12:
+            {
+                mh_mmu_config_u      mmu_config   = {0};
+
+                config->regspace.gpu_base       = 0;
+                config->regspace.mmio_virt_base = (unsigned char *)hal->z160_regspace.mmio_virt_base;
+                config->regspace.mmio_phys_base = (unsigned int) hal->z160_regspace.mmio_phys_base;
+                config->regspace.sizebytes      = GSL_HAL_SIZE_REG_G12;
+
+                mmu_config.f.mmu_enable           = 1;
+
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+                config->mmu_config              = 0x00555551;
+                config->va_base                 = hal->memspace[GSL_HAL_MEM1].gpu_base;
+                config->va_range                = hal->memspace[GSL_HAL_MEM1].sizebytes;
+#else
+                config->mmu_config              = mmu_config.val;
+                config->va_base                 = 0x00000000;
+                config->va_range                = 0x00000000;
+#endif // GSL_MMU_TRANSLATION_ENABLED
+
+                config->mpu_base                = 0x00000000; //(unsigned int) hal->memchunk.mmio_virt_base;
+                config->mpu_range               = 0xFFFFF000; //hal->memchunk.sizebytes;
+
+                status = GSL_SUCCESS;
+                break;
+            }
+
+            default:
+
+                break;
+        }
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+//
+// kgsl_hal_getchipid
+//
+// The proper platform method, build from RBBM_PERIPHIDx and RBBM_PATCH_RELEASE
+//
+KGSLHAL_API gsl_chipid_t
+kgsl_hal_getchipid(gsl_deviceid_t device_id)
+{
+    gsl_device_t *device = &gsl_driver.device[device_id-1]; 
+    gsl_chipid_t chipid;
+    unsigned int coreid, majorid, minorid, patchid, revid;
+
+    // YDX
+    device->ftbl.device_regread(device, mmRBBM_PERIPHID1, &coreid);
+    coreid &= 0xF;
+
+    // 2.
+    device->ftbl.device_regread(device, mmRBBM_PERIPHID2, &majorid);
+    majorid = (majorid >> 4) & 0xF;
+
+    device->ftbl.device_regread(device, mmRBBM_PATCH_RELEASE, &revid);
+    
+    //   2.
+    minorid = ((revid >> 0)  & 0xFF); // this is a 16bit field, but extremely unlikely it would ever get this high
+    
+    //     1
+    patchid = ((revid >> 16) & 0xFF);
+
+    chipid = ((coreid << 24) | (majorid << 16) | (minorid << 8) | (patchid << 0)); 
+
+    return (chipid);
+}
+
+//----------------------------------------------------------------------------
+
+KGSLHAL_API int 
+kgsl_hal_getplatformtype(char *platform)
+{
+    if (gsl_driver.hal)
+    {
+        kos_strcpy(platform, GSL_HAL_PLATFORM);
+        return (GSL_SUCCESS);
+    }
+    else
+    {
+        return (GSL_FAILURE_NOTINITIALIZED);
+    }
+}
+
+//---------------------------------------------------------------------------
+
+KGSLHAL_API int
+kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value)
+{
+	gsl_device_t *device = &gsl_driver.device[device_id-1];
+	struct clk *gpu_clk = 0;
+	struct clk *garb_clk = clk_get(0, "garb_clk");
+	struct clk *emi_garb_clk = clk_get(0, "emi_garb_clk");
+
+    // unreferenced formal parameters
+    (void) value;
+	
+	switch (device_id)
+	{
+	case GSL_DEVICE_G12:
+		gpu_clk = clk_get(0, "gpu2d_clk");
+		break;
+	case GSL_DEVICE_YAMATO:
+		gpu_clk = clk_get(0, "gpu3d_clk");
+		break;
+	default:
+		return (GSL_FAILURE_DEVICEERROR);
+	}
+	
+	if (!gpu_clk)
+		return (GSL_FAILURE_DEVICEERROR);
+
+    switch (state)
+    {
+	case GSL_PWRFLAGS_CLK_ON:
+		break;
+	case GSL_PWRFLAGS_POWER_ON:
+		clk_enable(gpu_clk);
+		clk_enable(garb_clk);
+		clk_enable(emi_garb_clk);
+		kgsl_device_autogate_init(&gsl_driver.device[device_id-1]);
+		break;
+	case GSL_PWRFLAGS_CLK_OFF:
+		break;
+	case GSL_PWRFLAGS_POWER_OFF:
+		if (device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT) != GSL_SUCCESS)
+		{
+			return (GSL_FAILURE_DEVICEERROR);
+		}
+		kgsl_device_autogate_exit(&gsl_driver.device[device_id-1]);
+		clk_disable(gpu_clk);
+		clk_disable(garb_clk);
+		clk_disable(emi_garb_clk);
+		break;
+	default:
+		break;
+    }
+	
+    return (GSL_SUCCESS);
+}
+
+KGSLHAL_API int kgsl_clock(gsl_deviceid_t dev, int enable)
+{
+	struct clk *gpu_clk;
+	struct clk *garb_clk = clk_get(0, "garb_clk");
+	struct clk *emi_garb_clk = clk_get(0, "emi_garb_clk");
+
+	switch (dev)
+	{
+	case GSL_DEVICE_G12:
+		gpu_clk = clk_get(0, "gpu2d_clk");
+		break;
+	case GSL_DEVICE_YAMATO:
+		gpu_clk = clk_get(0, "gpu3d_clk");
+		break;
+	default:
+		printk(KERN_ERR "GPU device %d is invalid!\n", dev);
+		return (GSL_FAILURE_DEVICEERROR);
+	}
+
+	if (IS_ERR(gpu_clk)) {
+		printk(KERN_ERR "%s: GPU clock get failed!\n", __func__);
+		return (GSL_FAILURE_DEVICEERROR);
+	}
+
+	if (enable) {
+		clk_enable(gpu_clk);
+		clk_enable(garb_clk);
+		clk_enable(emi_garb_clk);
+	} else {
+		clk_disable(gpu_clk);
+		clk_disable(garb_clk);
+		clk_disable(emi_garb_clk);
+	}
+
+	return (GSL_SUCCESS);
+}
diff --git a/drivers/mxc/amd-gpu/platform/hal/MX51/memcfg/gsl_memcfg.c b/drivers/mxc/amd-gpu/platform/hal/MX51/memcfg/gsl_memcfg.c
new file mode 100644
index 000000000000..93fab327a830
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/MX51/memcfg/gsl_memcfg.c
@@ -0,0 +1,31 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "kos_libapi.h"
+
+//
+//  Return the maximum amount of memory that can be allocated to the Z430.  This number
+//  will be constrained to 2MB as a minimum and the original hardcoded value for the caller
+//  as a maximum.  If the return value is outside of this range, then the original value in 
+//  the caller will be used.  For this reason, returning 0 is used to signify to use the
+//  original value as the default.
+//
+KOS_DLLEXPORT unsigned long kgsl_get_z430_memory_amount(void)
+{
+    return(0);
+}
diff --git a/drivers/mxc/amd-gpu/platform/hal/MX51/memcfg/gsl_memcfg.h b/drivers/mxc/amd-gpu/platform/hal/MX51/memcfg/gsl_memcfg.h
new file mode 100644
index 000000000000..e68387f1609a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/MX51/memcfg/gsl_memcfg.h
@@ -0,0 +1,40 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef GSL_MEMCFG_H
+#define GSL_MEMCFG_H
+
+//
+//  Return the maximum amount of memory that can be allocated to the Z430.  This number
+//  will be constrained to 2MB as a minimum and the original hardcoded value for the caller
+//  as a maximum.  If the return value is outside of this range, then the original value in 
+//  the caller will be used.  For this reason, returning 0 is used to signify to use the
+//  original value as the default.
+//
+KOS_DLLEXPORT unsigned long kgsl_get_z430_memory_amount(void);
+#endif
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h
new file mode 100644
index 000000000000..65eadb1e79cf
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h
@@ -0,0 +1,155 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_HWACCESS_LINUX_H
+#define __GSL_HWACCESS_LINUX_H
+
+#ifdef _LINUX
+#include "gsl_linux_map.h"
+#endif
+
+#include <linux/io.h>
+#include <asm/system.h>
+#include <asm/uaccess.h>
+
+OSINLINE void
+kgsl_hwaccess_memread(void *dst, unsigned int gpubase, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace)
+{
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+    if(gpubase >= GSL_LINUX_MAP_RANGE_START && gpubase < GSL_LINUX_MAP_RANGE_END)
+    {
+        gsl_linux_map_read(dst, gpubase+gpuoffset, sizebytes, touserspace);
+    }
+    else
+#endif
+    {
+        mb();
+        dsb();
+        if (touserspace)
+        {
+            if (copy_to_user(dst, (void *)(gpubase + gpuoffset), sizebytes))
+            {
+                return;
+            }
+        }
+        else
+        {
+            kos_memcpy(dst, (void *) (gpubase + gpuoffset), sizebytes);
+        }
+        mb();
+        dsb();
+    }
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_hwaccess_memwrite(unsigned int gpubase, unsigned int gpuoffset, void *src, unsigned int sizebytes, unsigned int fromuserspace)
+{
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+    if(gpubase >= GSL_LINUX_MAP_RANGE_START && gpubase < GSL_LINUX_MAP_RANGE_END)
+    {
+        gsl_linux_map_write(src, gpubase+gpuoffset, sizebytes, fromuserspace);
+    }
+    else
+#endif
+    {
+        mb();
+        dsb();
+        if (fromuserspace)
+        {
+            if (copy_from_user((void *)(gpubase + gpuoffset), src, sizebytes))
+            {
+                return;
+            }
+        }
+        else
+        {
+            kos_memcpy((void *)(gpubase + gpuoffset), src, sizebytes);
+        }
+        mb();
+        dsb();
+    }
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_hwaccess_memset(unsigned int gpubase, unsigned int gpuoffset, unsigned int value, unsigned int sizebytes)
+{
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+	if(gpubase >= GSL_LINUX_MAP_RANGE_START && gpubase < GSL_LINUX_MAP_RANGE_END)
+		gsl_linux_map_set(gpuoffset+gpubase, value, sizebytes);
+	else
+#endif
+    {
+        mb();
+        dsb();
+        kos_memset((void *)(gpubase + gpuoffset), value, sizebytes);
+        mb();
+        dsb();
+    }
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_hwaccess_regread(gsl_deviceid_t device_id, unsigned int gpubase, unsigned int offsetwords, unsigned int *data)
+{
+    unsigned int *reg;
+
+    // unreferenced formal parameter
+    (void) device_id;
+
+    reg = (unsigned int *)(gpubase + (offsetwords << 2));
+    
+    mb();
+    dsb();
+    *data = __raw_readl(reg);
+    mb();
+    dsb();
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_hwaccess_regwrite(gsl_deviceid_t device_id, unsigned int gpubase, unsigned int offsetwords, unsigned int data)
+{
+    unsigned int *reg;
+
+    // unreferenced formal parameter
+    (void) device_id;
+
+    reg = (unsigned int *)(gpubase + (offsetwords << 2));
+    mb();
+    dsb();
+    __raw_writel(data, reg);
+    mb();
+    dsb();
+}
+#endif  // __GSL_HWACCESS_WINCE_MX51_H
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c
new file mode 100644
index 000000000000..30f783e1cf12
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c
@@ -0,0 +1,973 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl_types.h"
+#include "gsl.h"
+#include "gsl_buildconfig.h"
+#include "gsl_halconfig.h"
+#include "gsl_ioctl.h"
+#include "gsl_kmod_cleanup.h"
+#include "gsl_linux_map.h"
+
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <asm/uaccess.h>
+#include <linux/mm.h>
+#include <linux/mutex.h>
+#include <linux/cdev.h>
+
+#include <linux/platform_device.h>
+#include <linux/vmalloc.h>
+
+static int gpu_2d_irq, gpu_3d_irq;
+
+phys_addr_t gpu_2d_regbase;
+int gpu_2d_regsize;
+phys_addr_t gpu_3d_regbase;
+int gpu_3d_regsize;
+int gmem_size;
+phys_addr_t gpu_reserved_mem;
+int gpu_reserved_mem_size;
+
+static ssize_t gsl_kmod_read(struct file *fd, char __user *buf, size_t len, loff_t *ptr);
+static ssize_t gsl_kmod_write(struct file *fd, const char __user *buf, size_t len, loff_t *ptr);
+static int gsl_kmod_ioctl(struct inode *inode, struct file *fd, unsigned int cmd, unsigned long arg);
+static int gsl_kmod_mmap(struct file *fd, struct vm_area_struct *vma);
+static int gsl_kmod_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
+static int gsl_kmod_open(struct inode *inode, struct file *fd);
+static int gsl_kmod_release(struct inode *inode, struct file *fd);
+static irqreturn_t z160_irq_handler(int irq, void *dev_id);
+#if defined(MX51)
+static irqreturn_t z430_irq_handler(int irq, void *dev_id);
+#endif
+
+static int gsl_kmod_major;
+static struct class *gsl_kmod_class;
+DEFINE_MUTEX(gsl_mutex);
+
+static const struct file_operations gsl_kmod_fops =
+{
+    .owner = THIS_MODULE,
+    .read = gsl_kmod_read,
+    .write = gsl_kmod_write,
+    .ioctl = gsl_kmod_ioctl,
+    .mmap = gsl_kmod_mmap,
+    .open = gsl_kmod_open,
+    .release = gsl_kmod_release
+};
+
+static struct vm_operations_struct gsl_kmod_vmops =
+{
+	.fault = gsl_kmod_fault,
+};
+
+static ssize_t gsl_kmod_read(struct file *fd, char __user *buf, size_t len, loff_t *ptr)
+{
+    return 0;
+}
+
+static ssize_t gsl_kmod_write(struct file *fd, const char __user *buf, size_t len, loff_t *ptr)
+{
+    return 0;
+}
+
+static int gsl_kmod_ioctl(struct inode *inode, struct file *fd, unsigned int cmd, unsigned long arg)
+{
+    int kgslStatus = GSL_FAILURE;
+
+    switch (cmd) {
+    case IOCTL_KGSL_DEVICE_START:
+        {
+            kgsl_device_start_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_start_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_start(param.device_id, param.flags);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_STOP:
+        {
+            kgsl_device_stop_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_stop_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_stop(param.device_id);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_IDLE:
+        {
+            kgsl_device_idle_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_idle_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_idle(param.device_id, param.timeout);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_GETPROPERTY:
+        {
+            kgsl_device_getproperty_t param;
+            void *tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_getproperty_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            tmp = kmalloc(param.sizebytes, GFP_KERNEL);
+            if (!tmp)
+            {
+                printk(KERN_ERR "%s:kmalloc error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_getproperty(param.device_id, param.type, tmp, param.sizebytes);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.value, tmp, param.sizebytes))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    kfree(tmp);
+                    break;
+                }
+            }
+            else
+            {
+                printk(KERN_ERR "%s: kgsl_device_getproperty error\n", __func__);
+            }
+            kfree(tmp);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_SETPROPERTY:
+        {
+            kgsl_device_setproperty_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_setproperty_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_setproperty(param.device_id, param.type, param.value, param.sizebytes);
+            if (kgslStatus != GSL_SUCCESS)
+            {
+                printk(KERN_ERR "%s: kgsl_device_setproperty error\n", __func__);
+            }
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_REGREAD:
+        {
+            kgsl_device_regread_t param;
+            unsigned int tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_regread_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_regread(param.device_id, param.offsetwords, &tmp);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.value, &tmp, sizeof(unsigned int)))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_REGWRITE:
+        {
+            kgsl_device_regwrite_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_regwrite_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_regwrite(param.device_id, param.offsetwords, param.value);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_WAITIRQ:
+        {
+            kgsl_device_waitirq_t param;
+            unsigned int count;
+
+            printk(KERN_ERR "IOCTL_KGSL_DEVICE_WAITIRQ obsoleted!\n");
+//          kgslStatus = -ENOTTY; break;
+
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_waitirq_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_waitirq(param.device_id, param.intr_id, &count, param.timeout);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.count, &count, sizeof(unsigned int)))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_CMDSTREAM_ISSUEIBCMDS:
+        {
+            kgsl_cmdstream_issueibcmds_t param;
+            gsl_timestamp_t tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdstream_issueibcmds_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_cmdstream_issueibcmds(param.device_id, param.drawctxt_index, param.ibaddr, param.sizedwords, &tmp, param.flags);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t)))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_CMDSTREAM_READTIMESTAMP:
+        {
+            kgsl_cmdstream_readtimestamp_t param;
+            gsl_timestamp_t tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdstream_readtimestamp_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            tmp = kgsl_cmdstream_readtimestamp(param.device_id, param.type);
+            if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t)))
+            {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+            }
+            kgslStatus = GSL_SUCCESS;
+            break;
+        }
+    case IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP:
+        {
+            int err;
+            kgsl_cmdstream_freememontimestamp_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdstream_freememontimestamp_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            err = del_memblock_from_allocated_list(fd, param.memdesc);
+            if(err)
+            {
+                /* tried to remove a block of memory that is not allocated! 
+                 * NOTE that -EINVAL is Linux kernel's error codes! 
+                 * the drivers error codes COULD mix up with kernel's. */
+                kgslStatus = -EINVAL;
+            }
+            else
+            {
+                kgslStatus = kgsl_cmdstream_freememontimestamp(param.device_id,
+                                                               param.memdesc,
+                                                               param.timestamp,
+                                                               param.type);
+            }
+            break;
+        }
+    case IOCTL_KGSL_CMDSTREAM_WAITTIMESTAMP:
+        {
+            kgsl_cmdstream_waittimestamp_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdstream_waittimestamp_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_cmdstream_waittimestamp(param.device_id, param.timestamp, param.timeout);
+            break;
+        }
+    case IOCTL_KGSL_CMDWINDOW_WRITE:
+        {
+            kgsl_cmdwindow_write_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdwindow_write_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_cmdwindow_write(param.device_id, param.target, param.addr, param.data);
+            break;
+        }
+    case IOCTL_KGSL_CONTEXT_CREATE:
+        {
+            kgsl_context_create_t param;
+            unsigned int tmp;
+            int tmpStatus;
+
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_context_create_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_context_create(param.device_id, param.type, &tmp, param.flags);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.drawctxt_id, &tmp, sizeof(unsigned int)))
+                {
+                    tmpStatus = kgsl_context_destroy(param.device_id, tmp);
+                    /* is asserting ok? Basicly we should return the error from copy_to_user
+                     * but will the user space interpret it correctly? Will the user space 
+                     * always check against GSL_SUCCESS  or GSL_FAILURE as they are not the only
+                     * return values.
+                     */
+                    KOS_ASSERT(tmpStatus == GSL_SUCCESS);
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+                else
+                {
+                    add_device_context_to_array(fd, param.device_id, tmp);
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_CONTEXT_DESTROY:
+        {
+            kgsl_context_destroy_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_context_destroy_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_context_destroy(param.device_id, param.drawctxt_id);
+            del_device_context_from_array(fd, param.device_id, param.drawctxt_id);
+            break;
+        }
+    case IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW:
+        {
+            kgsl_drawctxt_bind_gmem_shadow_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_drawctxt_bind_gmem_shadow_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_drawctxt_bind_gmem_shadow(param.device_id, param.drawctxt_id, param.gmem_rect, param.shadow_x, param.shadow_y, param.shadow_buffer, param.buffer_id);
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_ALLOC:
+        {
+            kgsl_sharedmem_alloc_t param;
+            gsl_memdesc_t tmp;
+            int tmpStatus;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_alloc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_alloc(param.device_id, param.flags, param.sizebytes, &tmp);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.memdesc, &tmp, sizeof(gsl_memdesc_t)))
+                {
+                    tmpStatus = kgsl_sharedmem_free(&tmp);
+                    KOS_ASSERT(tmpStatus == GSL_SUCCESS);
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+                else
+                {
+                    add_memblock_to_allocated_list(fd, &tmp);
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_FREE:
+        {
+            kgsl_sharedmem_free_t param;
+            gsl_memdesc_t tmp;
+            int err;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_free_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&tmp, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            err = del_memblock_from_allocated_list(fd, &tmp);
+            if(err)
+            {
+                printk(KERN_ERR "%s: tried to free memdesc that was not allocated!\n", __func__);
+                kgslStatus = err;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_free(&tmp);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.memdesc, &tmp, sizeof(gsl_memdesc_t)))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_READ:
+        {
+            kgsl_sharedmem_read_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_read_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_read(&memdesc, param.dst, param.offsetbytes, param.sizebytes, true);
+            if (kgslStatus != GSL_SUCCESS)
+            {
+                printk(KERN_ERR "%s: kgsl_sharedmem_read failed\n", __func__);
+            }
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_WRITE:
+        {
+            kgsl_sharedmem_write_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_write_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_write(&memdesc, param.offsetbytes, param.src, param.sizebytes, true);
+            if (kgslStatus != GSL_SUCCESS)
+            {
+                printk(KERN_ERR "%s: kgsl_sharedmem_write failed\n", __func__);
+            }
+            
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_SET:
+        {
+            kgsl_sharedmem_set_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_set_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_set(&memdesc, param.offsetbytes, param.value, param.sizebytes);
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_LARGESTFREEBLOCK:
+        {
+            kgsl_sharedmem_largestfreeblock_t param;
+            unsigned int largestfreeblock;
+
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_largestfreeblock_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            largestfreeblock = kgsl_sharedmem_largestfreeblock(param.device_id, param.flags);
+            if (copy_to_user(param.largestfreeblock, &largestfreeblock, sizeof(unsigned int)))
+            {
+                printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = GSL_SUCCESS;
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_CACHEOPERATION:
+        {
+            kgsl_sharedmem_cacheoperation_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_cacheoperation_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_cacheoperation(&memdesc, param.offsetbytes, param.sizebytes, param.operation);
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_FROMHOSTPOINTER:
+        {
+            kgsl_sharedmem_fromhostpointer_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_fromhostpointer_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_fromhostpointer(param.device_id, &memdesc, param.hostptr);
+            break;
+        }
+    case IOCTL_KGSL_ADD_TIMESTAMP:
+        {
+            kgsl_add_timestamp_t param;
+            gsl_timestamp_t tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_add_timestamp_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            tmp = kgsl_add_timestamp(param.device_id, &tmp);
+            if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t)))
+            {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+            }
+            kgslStatus = GSL_SUCCESS;
+            break;
+        }
+    
+    case IOCTL_KGSL_DEVICE_CLOCK:
+        {
+            kgsl_device_clock_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_clock_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_clock(param.device, param.enable);
+            break;
+        }
+    default:
+        kgslStatus = -ENOTTY;
+        break;
+    }
+
+    return kgslStatus;
+}
+
+static int gsl_kmod_mmap(struct file *fd, struct vm_area_struct *vma)
+{
+    int status = 0;
+    unsigned long start = vma->vm_start;
+    unsigned long pfn = vma->vm_pgoff;
+    unsigned long size = vma->vm_end - vma->vm_start;
+    unsigned long prot = pgprot_writecombine(vma->vm_page_prot);
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+	unsigned long addr = vma->vm_pgoff << PAGE_SHIFT;
+	void *va;
+#endif
+
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+	if (addr < GSL_LINUX_MAP_RANGE_END && addr >= GSL_LINUX_MAP_RANGE_START)
+	{
+		va = gsl_linux_map_find(addr);
+		while (size > 0)
+		{
+			if (remap_pfn_range(vma, start, vmalloc_to_pfn(va), PAGE_SIZE, prot))
+			{
+				return -EAGAIN;
+			}
+			start += PAGE_SIZE;
+			va += PAGE_SIZE;
+			size -= PAGE_SIZE;
+		}
+	}
+	else
+#endif
+	{
+		if (remap_pfn_range(vma, start, pfn, size, prot))
+		{
+			status = -EAGAIN;
+		}
+	}
+
+    vma->vm_ops = &gsl_kmod_vmops;
+
+    return status;
+}
+
+static int gsl_kmod_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
+{
+    return VM_FAULT_SIGBUS;
+}
+
+static int gsl_kmod_open(struct inode *inode, struct file *fd)
+{
+    gsl_flags_t flags = 0;
+    struct gsl_kmod_per_fd_data *datp;
+    int err = 0;
+
+    if(mutex_lock_interruptible(&gsl_mutex))
+    {
+        return -EINTR;
+    }
+
+    if (kgsl_driver_entry(flags) != GSL_SUCCESS)
+    {
+        printk(KERN_INFO "%s: kgsl_driver_entry error\n", __func__);
+        err = -EIO;  // TODO: not sure why did it fail?
+    }
+    else
+    {
+        /* allocate per file descriptor data structure */
+        datp = (struct gsl_kmod_per_fd_data *)kzalloc(
+                                             sizeof(struct gsl_kmod_per_fd_data),
+                                             GFP_KERNEL);
+        if(datp)
+        {
+            init_created_contexts_array(datp->created_contexts_array[0]);
+            INIT_LIST_HEAD(&datp->allocated_blocks_head);
+
+            fd->private_data = (void *)datp;
+        }
+        else
+        {
+            err = -ENOMEM;
+        }
+    }
+
+    mutex_unlock(&gsl_mutex);
+
+    return err;
+}
+
+static int gsl_kmod_release(struct inode *inode, struct file *fd)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    int err = 0;
+
+    if(mutex_lock_interruptible(&gsl_mutex))
+    {
+        return -EINTR;
+    }
+
+    /* make sure contexts are destroyed */
+    del_all_devices_contexts(fd);
+
+    if (kgsl_driver_exit() != GSL_SUCCESS)
+    {
+        printk(KERN_INFO "%s: kgsl_driver_exit error\n", __func__);
+        err = -EIO; // TODO: find better error code
+    }
+    else
+    {
+        /* release per file descriptor data structure */
+        datp = (struct gsl_kmod_per_fd_data *)fd->private_data;
+        del_all_memblocks_from_allocated_list(fd);
+        kfree(datp);
+        fd->private_data = 0;
+    }
+
+    mutex_unlock(&gsl_mutex);
+
+    return err;
+}
+
+static struct class *gsl_kmod_class;
+
+static irqreturn_t z160_irq_handler(int irq, void *dev_id)
+{
+    kgsl_intr_isr();
+    return IRQ_HANDLED;
+}
+
+#if defined(MX51)
+static irqreturn_t z430_irq_handler(int irq, void *dev_id)
+{
+    kgsl_intr_isr();
+    return IRQ_HANDLED;
+}
+#endif
+
+static int gpu_probe(struct platform_device *pdev)
+{
+    int i;
+    struct resource *res;
+    struct device *dev;
+
+    for(i = 0; i < 2; i++){
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+        if (!res) {
+            if (i == 0) {
+                printk(KERN_ERR "gpu: unable to get gpu irq\n");
+                return -ENODEV;
+            } else {
+                break;
+            }
+        }
+        if(strcmp(res->name, "gpu_2d_irq") == 0){
+            gpu_2d_irq = res->start;
+        }else if(strcmp(res->name, "gpu_3d_irq") == 0){
+            gpu_3d_irq = res->start;
+        }
+    }
+
+    for(i = 0; i < 4; i++){
+        res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+        if (!res) {
+            gpu_2d_regbase = 0;
+            gpu_2d_regsize = 0;
+            gpu_3d_regbase = 0;
+            gpu_2d_regsize = 0;
+            gmem_size = 0;
+            gpu_reserved_mem = 0;
+            gpu_reserved_mem_size = 0;
+            break;
+        }else{
+            if(strcmp(res->name, "gpu_2d_registers") == 0){
+                gpu_2d_regbase = res->start;
+                gpu_2d_regsize = res->end - res->start + 1;
+            }else if(strcmp(res->name, "gpu_3d_registers") == 0){
+                gpu_3d_regbase = res->start;
+                gpu_3d_regsize = res->end - res->start + 1;
+            }else if(strcmp(res->name, "gpu_graphics_mem") == 0){
+                gmem_size = res->end - res->start + 1;
+             }else if(strcmp(res->name, "gpu_reserved_mem") == 0){
+                gpu_reserved_mem = res->start;
+                gpu_reserved_mem_size = res->end - res->start + 1;
+            }
+        }
+    }
+
+    if (kgsl_driver_init() != GSL_SUCCESS)
+    {
+        printk(KERN_ERR "%s: kgsl_driver_init error\n", __func__);
+        goto kgsl_driver_init_error;
+    }
+
+#if defined(MX51)
+    if (request_irq(gpu_3d_irq, z430_irq_handler, 0, "ydx", NULL) < 0)
+    {
+        printk(KERN_ERR "%s: request_irq error\n", __func__);
+        goto request_irq_error;
+    }
+#endif
+
+    if (request_irq(gpu_2d_irq, z160_irq_handler, 0, "g12", NULL) < 0)
+    {
+        printk(KERN_ERR "2D Acceleration Enabled, OpenVG Disabled!\n");
+        gpu_2d_irq = 0;
+    }
+
+    gsl_kmod_major = register_chrdev(0, "gsl_kmod", &gsl_kmod_fops);
+    gsl_kmod_vmops.fault = gsl_kmod_fault;
+
+    if (gsl_kmod_major <= 0)
+    {
+        pr_err("%s: register_chrdev error\n", __func__);
+        goto register_chrdev_error;
+    }
+
+    gsl_kmod_class = class_create(THIS_MODULE, "gsl_kmod");
+
+    if (IS_ERR(gsl_kmod_class))
+    {
+        pr_err("%s: class_create error\n", __func__);
+        goto class_create_error;
+    }
+
+    #if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28))
+        dev = device_create(gsl_kmod_class, NULL, MKDEV(gsl_kmod_major, 0), "gsl_kmod");
+    #else
+        dev = device_create(gsl_kmod_class, NULL, MKDEV(gsl_kmod_major, 0), NULL,"gsl_kmod");
+    #endif
+
+    if (!IS_ERR(dev))
+    {
+    //    gsl_kmod_data.device = dev;
+        return 0;
+    }
+
+    pr_err("%s: device_create error\n", __func__);
+
+class_create_error:
+    class_destroy(gsl_kmod_class);
+
+register_chrdev_error:
+    unregister_chrdev(gsl_kmod_major, "gsl_kmod");
+
+request_irq_error:
+kgsl_driver_init_error:
+    kgsl_driver_close();
+    return 0;   // TODO: return proper error code
+}
+
+static int gpu_remove(struct platform_device *pdev)
+{
+    device_destroy(gsl_kmod_class, MKDEV(gsl_kmod_major, 0));
+    class_destroy(gsl_kmod_class);
+    unregister_chrdev(gsl_kmod_major, "gsl_kmod");
+#if defined(MX51)
+    if (gpu_3d_irq)
+    {
+        free_irq(gpu_3d_irq, NULL);
+    }
+
+    if (gpu_2d_irq)
+    {
+        free_irq(gpu_2d_irq, NULL);
+    }
+#elif defined(MX35)
+    if (gpu_2d_irq)
+    {
+        free_irq(gpu_2d_irq, NULL);
+    }
+#endif	
+    kgsl_driver_close();
+    return 0;
+}
+
+#ifdef CONFIG_PM
+static int gpu_suspend(struct platform_device *pdev, pm_message_t state)
+{
+    int              i;
+    gsl_powerprop_t  power;
+
+    power.flags = GSL_PWRFLAGS_POWER_OFF;
+    for (i = 0; i < GSL_DEVICE_MAX; i++)
+    {
+        kgsl_device_setproperty(
+                        (gsl_deviceid_t) (i+1),
+                        GSL_PROP_DEVICE_POWER,
+                        &power,
+                        sizeof(gsl_powerprop_t));
+    }   
+
+    return 0;
+}
+
+static int gpu_resume(struct platform_device *pdev)
+{
+    int              i;
+    gsl_powerprop_t  power;
+
+    power.flags = GSL_PWRFLAGS_POWER_ON;
+    for (i = 0; i < GSL_DEVICE_MAX; i++)
+    {
+        kgsl_device_setproperty(
+                        (gsl_deviceid_t) (i+1),
+                        GSL_PROP_DEVICE_POWER,
+                        &power,
+                        sizeof(gsl_powerprop_t));
+    }   
+
+    return 0;
+}
+#else
+#define	gpu_suspend	NULL
+#define	gpu_resume	NULL
+#endif /* !CONFIG_PM */
+
+/*! Driver definition
+ */
+static struct platform_driver gpu_driver = {
+    .driver = {
+        .name = "mxc_gpu",
+        },
+    .probe = gpu_probe,
+    .remove = gpu_remove,
+    .suspend = gpu_suspend,
+    .resume = gpu_resume,
+};
+
+static int __init gsl_kmod_init(void)
+{
+     return platform_driver_register(&gpu_driver);
+}
+
+static void __exit gsl_kmod_exit(void)
+{
+     platform_driver_unregister(&gpu_driver);
+}
+
+module_init(gsl_kmod_init);
+module_exit(gsl_kmod_exit);
+MODULE_AUTHOR("Advanced Micro Devices");
+#if defined(MX51)
+MODULE_DESCRIPTION("AMD 2D/3D graphics core driver for i.MX51");
+#elif defined(MX35)
+MODULE_DESCRIPTION("AMD 2D graphics core driver for i.MX35");
+#endif
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c
new file mode 100644
index 000000000000..3685a5756baf
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c
@@ -0,0 +1,269 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl.h"
+#include "gsl_kmod_cleanup.h"
+
+#include <linux/kernel.h>
+#include <linux/fs.h>
+
+/*
+ * Local helper functions to check and convert device/context id's (1 based)
+ * to index (0 based).
+ */
+static u32 device_id_to_device_index(gsl_deviceid_t device_id)
+{
+    KOS_ASSERT((GSL_DEVICE_ANY < device_id) && 
+               (device_id <= GSL_DEVICE_MAX));
+    return (u32)(device_id - 1);
+}
+
+/* 
+ * Local helper function to check and get pointer to per file descriptor data 
+ */
+static struct gsl_kmod_per_fd_data *get_fd_private_data(struct file *fd)
+{
+    struct gsl_kmod_per_fd_data *datp; 
+
+    KOS_ASSERT(fd);
+    datp = (struct gsl_kmod_per_fd_data *)fd->private_data;
+    KOS_ASSERT(datp);
+    return datp;
+}
+
+static s8 *find_first_entry_with(s8 *subarray, s8 context_id)
+{
+    s8 *entry = NULL;
+    int i;
+
+//printk(KERN_DEBUG "At %s, ctx_id = %d\n", __func__, context_id);
+
+    KOS_ASSERT(context_id >= EMPTY_ENTRY);    
+    KOS_ASSERT(context_id <= GSL_CONTEXT_MAX);  // TODO: check the bound.
+
+    for(i = 0; i < GSL_CONTEXT_MAX; i++)        // TODO: check the bound.
+    {
+        if(subarray[i] == (s8)context_id)
+        {
+            entry = &subarray[i];
+            break;
+        }
+    }
+
+    return entry;
+}
+
+
+/*
+ * Add a memdesc into a list of allocated memory blocks for this file 
+ * descriptor. The list is build in such a way that it implements FIFO (i.e.
+ * list). Traces of tiger, tiger_ri and VG11 CTs should be analysed to make
+ * informed choice.
+ *
+ * NOTE! gsl_memdesc_ts are COPIED so user space should NOT change them.
+ */
+int add_memblock_to_allocated_list(struct file *fd,
+                                   gsl_memdesc_t *allocated_block)
+{
+    int err = 0;
+    struct gsl_kmod_per_fd_data *datp;
+    struct gsl_kmod_alloc_list *lisp;
+    struct list_head *head;
+
+    KOS_ASSERT(allocated_block);
+
+    datp = get_fd_private_data(fd);
+
+    head = &datp->allocated_blocks_head;
+    KOS_ASSERT(head);
+
+    /* allocate and put new entry in the list of allocated memory descriptors */
+    lisp = (struct gsl_kmod_alloc_list *)kzalloc(sizeof(struct gsl_kmod_alloc_list), GFP_KERNEL);
+    if(lisp)
+    {
+        INIT_LIST_HEAD(&lisp->node);
+
+        /* builds FIFO (list_add() would build LIFO) */
+        list_add_tail(&lisp->node, head);
+        memcpy(&lisp->allocated_block, allocated_block, sizeof(gsl_memdesc_t));
+        lisp->allocation_number = datp->maximum_number_of_blocks;
+//        printk(KERN_DEBUG "List entry #%u allocated\n", lisp->allocation_number);
+
+        datp->maximum_number_of_blocks++;
+        datp->number_of_allocated_blocks++;
+
+        err = 0;
+    }
+    else
+    {
+        printk(KERN_ERR "%s: Could not allocate new list element\n", __func__);
+        err = -ENOMEM;
+    }
+
+    return err;
+}
+
+/* Delete a previously allocated memdesc from a list of allocated memory blocks */
+int del_memblock_from_allocated_list(struct file *fd,
+                                     gsl_memdesc_t *freed_block)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    struct gsl_kmod_alloc_list *cursor, *next;
+    struct list_head *head;
+//    int is_different;
+
+    KOS_ASSERT(freed_block);
+
+    datp = get_fd_private_data(fd);
+
+    head = &datp->allocated_blocks_head;
+    KOS_ASSERT(head);
+
+    KOS_ASSERT(datp->number_of_allocated_blocks > 0);
+
+    if(!list_empty(head))
+    {
+        list_for_each_entry_safe(cursor, next, head, node)
+        {
+            if(cursor->allocated_block.gpuaddr == freed_block->gpuaddr)
+            {
+//                is_different = memcmp(&cursor->allocated_block, freed_block, sizeof(gsl_memdesc_t));
+//                KOS_ASSERT(!is_different);
+
+                list_del(&cursor->node);
+//                printk(KERN_DEBUG "List entry #%u freed\n", cursor->allocation_number);
+                kfree(cursor);
+                datp->number_of_allocated_blocks--;
+                return 0;
+            }
+        }
+    }
+    return -EINVAL; // tried to free entry not existing or from empty list.
+}
+
+/* Delete all previously allocated memdescs from a list */
+int del_all_memblocks_from_allocated_list(struct file *fd)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    struct gsl_kmod_alloc_list *cursor, *next;
+    struct list_head *head;
+
+    datp = get_fd_private_data(fd);
+
+    head = &datp->allocated_blocks_head;
+    KOS_ASSERT(head);
+
+    if(!list_empty(head))
+    {
+        printk(KERN_INFO "Not all allocated memory blocks were freed. Doing it now.\n");
+        list_for_each_entry_safe(cursor, next, head, node)
+        {
+            printk(KERN_INFO "Freeing list entry #%u, gpuaddr=%x\n", (u32)cursor->allocation_number, cursor->allocated_block.gpuaddr);
+            kgsl_sharedmem_free(&cursor->allocated_block);
+            list_del(&cursor->node);
+            kfree(cursor);
+        }
+    }
+
+    KOS_ASSERT(list_empty(head));
+    datp->number_of_allocated_blocks = 0;
+
+    return 0;
+}
+
+void init_created_contexts_array(s8 *array)
+{
+    memset((void*)array, EMPTY_ENTRY, GSL_DEVICE_MAX * GSL_CONTEXT_MAX);
+}
+
+
+void add_device_context_to_array(struct file *fd,
+                                 gsl_deviceid_t device_id,
+                                 unsigned int context_id)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    s8 *entry;
+    s8 *subarray;
+    u32 device_index = device_id_to_device_index(device_id);
+
+    datp = get_fd_private_data(fd);
+
+    subarray = datp->created_contexts_array[device_index];
+    entry = find_first_entry_with(subarray, EMPTY_ENTRY);
+
+    KOS_ASSERT(entry);
+    KOS_ASSERT((datp->created_contexts_array[device_index] <= entry) &&
+               (entry < datp->created_contexts_array[device_index] + GSL_CONTEXT_MAX));
+    KOS_ASSERT(context_id < 127);
+    *entry = (s8)context_id;
+}
+
+void del_device_context_from_array(struct file *fd, 
+                                   gsl_deviceid_t device_id,
+                                   unsigned int context_id)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    u32 device_index = device_id_to_device_index(device_id);
+    s8 *entry;
+    s8 *subarray;
+
+    datp = get_fd_private_data(fd);
+
+    KOS_ASSERT(context_id < 127);
+    subarray = &(datp->created_contexts_array[device_index][0]);
+    entry = find_first_entry_with(subarray, context_id);
+    KOS_ASSERT(entry);
+    KOS_ASSERT((datp->created_contexts_array[device_index] <= entry) &&
+               (entry < datp->created_contexts_array[device_index] + GSL_CONTEXT_MAX));
+    *entry = EMPTY_ENTRY;
+}
+
+void del_all_devices_contexts(struct file *fd)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    gsl_deviceid_t id;
+    u32 device_index;
+    u32 ctx_array_index;
+    s8 ctx;
+    int err;
+    
+    datp = get_fd_private_data(fd);
+
+    /* device_id is 1 based */
+    for(id = GSL_DEVICE_ANY + 1; id <= GSL_DEVICE_MAX; id++)
+    {
+        device_index = device_id_to_device_index(id);
+        for(ctx_array_index = 0; ctx_array_index < GSL_CONTEXT_MAX; ctx_array_index++)
+        {
+            ctx = datp->created_contexts_array[device_index][ctx_array_index];
+            if(ctx != EMPTY_ENTRY)
+            {
+                err = kgsl_context_destroy(id, ctx);
+                if(err != GSL_SUCCESS)
+                {
+                    printk(KERN_ERR "%s: could not destroy context %d on device id = %u\n", __func__, ctx, id);
+                }
+                else
+                {
+                    printk(KERN_DEBUG "%s: Destroyed context %d on device id = %u\n", __func__, ctx, id);
+                }
+            }
+        }
+    }
+}
+
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h
new file mode 100644
index 000000000000..475ee3be2e50
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h
@@ -0,0 +1,90 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_KMOD_CLEANUP_H
+#define __GSL_KMOD_CLEANUP_H
+#include "gsl_types.h"
+
+#include <linux/gfp.h>
+#include <linux/slab.h>
+#include <linux/fs.h>
+#include <linux/list.h>
+
+#if (GSL_CONTEXT_MAX > 127)
+    #error created_contexts_array supports context numbers only 127 or less.
+#endif
+
+static const s8 EMPTY_ENTRY = -1;
+
+/* A structure to make list of allocated memory blocks. List per fd. */
+/* should probably be allocated from slab cache to minimise fragmentation */
+struct gsl_kmod_alloc_list
+{
+    struct list_head node;
+    gsl_memdesc_t allocated_block;
+    u32 allocation_number;
+};
+
+/* A structure to hold abovementioned list of blocks. Contain per fd data. */
+struct gsl_kmod_per_fd_data
+{
+    struct list_head allocated_blocks_head; // list head
+    u32 maximum_number_of_blocks;
+    u32 number_of_allocated_blocks;
+    s8 created_contexts_array[GSL_DEVICE_MAX][GSL_CONTEXT_MAX];
+};
+
+
+/* 
+ * prototypes 
+ */
+
+/* allocated memory block tracking */
+int add_memblock_to_allocated_list(struct file *fd,
+                                   gsl_memdesc_t *allocated_block);
+
+int del_memblock_from_allocated_list(struct file *fd,
+                                     gsl_memdesc_t *freed_block);
+
+int del_all_memblocks_from_allocated_list(struct file *fd);
+
+/* created contexts tracking */
+void init_created_contexts_array(s8 *array);
+
+void add_device_context_to_array(struct file *fd,
+                                 gsl_deviceid_t device_id,
+                                 unsigned int context_id);
+
+void del_device_context_from_array(struct file *fd, 
+                                   gsl_deviceid_t device_id,
+                                   unsigned int context_id);
+
+void del_all_devices_contexts(struct file *fd);
+
+#endif  // __GSL_KMOD_CLEANUP_H
+
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c
new file mode 100644
index 000000000000..7fee7b814411
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c
@@ -0,0 +1,221 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/vmalloc.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <asm/uaccess.h>
+
+#include "gsl_linux_map.h"
+
+struct gsl_linux_map
+{
+	struct list_head list;
+	unsigned int gpu_addr;
+	void *kernel_virtual_addr;
+	unsigned int size;
+};
+
+static LIST_HEAD(gsl_linux_map_list);
+static DEFINE_MUTEX(gsl_linux_map_mutex);
+
+int gsl_linux_map_init()
+{
+	mutex_lock(&gsl_linux_map_mutex);
+	INIT_LIST_HEAD(&gsl_linux_map_list);
+	mutex_unlock(&gsl_linux_map_mutex);
+
+	return 0;
+}
+
+void *gsl_linux_map_alloc(unsigned int gpu_addr, unsigned int size)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+	void *va;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr == gpu_addr){
+			mutex_unlock(&gsl_linux_map_mutex);
+			return map->kernel_virtual_addr;
+		}
+	}
+
+	va = __vmalloc(size, GFP_KERNEL, pgprot_noncached(pgprot_kernel));
+	if(va == NULL){
+		mutex_unlock(&gsl_linux_map_mutex);
+		return NULL;
+	}
+
+	map = (struct gsl_linux_map *)kmalloc(sizeof(*map), GFP_KERNEL);
+	map->gpu_addr = gpu_addr;
+	map->kernel_virtual_addr = va;
+	map->size = size;
+
+	INIT_LIST_HEAD(&map->list);
+	list_add_tail(&map->list, &gsl_linux_map_list);
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return va;
+}
+
+void gsl_linux_map_free(unsigned int gpu_addr)
+{
+	int found = 0;
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr == gpu_addr){
+			found = 1;
+			break;
+		}
+	}
+
+	if(found){
+		vfree(map->kernel_virtual_addr);
+		list_del(&map->list);
+		kfree(map);
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+}
+
+void *gsl_linux_map_find(unsigned int gpu_addr)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr == gpu_addr){
+			mutex_unlock(&gsl_linux_map_mutex);
+			return map->kernel_virtual_addr;
+		}
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return NULL;
+}
+
+void *gsl_linux_map_read(void *dst, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr <= gpuoffset && 
+			(map->gpu_addr +  map->size) > gpuoffset){
+			void *src = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr);
+			mutex_unlock(&gsl_linux_map_mutex);
+                        if (touserspace)
+                        {
+                            return (void *)copy_to_user(dst, map->kernel_virtual_addr + gpuoffset - map->gpu_addr, sizebytes);
+                        }
+                        else
+                        {
+	                    return memcpy(dst, src, sizebytes);
+                        }
+		}
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return NULL;
+}
+
+void *gsl_linux_map_write(void *src, unsigned int gpuoffset, unsigned int sizebytes, unsigned int fromuserspace)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr <= gpuoffset && 
+			(map->gpu_addr +  map->size) > gpuoffset){
+			void *dst = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr);
+			mutex_unlock(&gsl_linux_map_mutex);
+                        if (fromuserspace)
+                        {
+                            return (void *)copy_from_user(map->kernel_virtual_addr + gpuoffset - map->gpu_addr, src, sizebytes);
+                        }
+                        else
+                        {
+                            return memcpy(dst, src, sizebytes);
+                        }
+		}
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return NULL;
+}
+
+void *gsl_linux_map_set(unsigned int gpuoffset, unsigned int value, unsigned int sizebytes)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr <= gpuoffset && 
+			(map->gpu_addr +  map->size) > gpuoffset){
+			void *ptr = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr);
+			mutex_unlock(&gsl_linux_map_mutex);
+			return memset(ptr, value, sizebytes);
+		}
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return NULL;
+}
+
+int gsl_linux_map_destroy()
+{
+	struct gsl_linux_map * map;
+	struct list_head *p, *tmp;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each_safe(p, tmp, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		vfree(map->kernel_virtual_addr);
+		list_del(&map->list);
+		kfree(map);
+	}
+
+	INIT_LIST_HEAD(&gsl_linux_map_list);
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return 0;
+}
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h
new file mode 100644
index 000000000000..0469d2b912be
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h
@@ -0,0 +1,46 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_LINUX_MAP_H__
+#define __GSL_LINUX_MAP_H__
+
+#include "gsl_halconfig.h"
+
+#define GSL_LINUX_MAP_RANGE_START (1024*1024)
+#define GSL_LINUX_MAP_RANGE_END (GSL_LINUX_MAP_RANGE_START+GSL_HAL_SHMEM_SIZE_EMEM1)
+
+int gsl_linux_map_init(void);
+void *gsl_linux_map_alloc(unsigned int gpu_addr, unsigned int size);
+void gsl_linux_map_free(unsigned int gpu_addr);
+void *gsl_linux_map_find(unsigned int gpu_addr);
+void *gsl_linux_map_read(void *dst, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace);
+void *gsl_linux_map_write(void *src, unsigned int gpuoffset, unsigned int sizebytes, unsigned int fromuserspace);
+void *gsl_linux_map_set(unsigned int gpuoffset, unsigned int value, unsigned int sizebytes);
+int gsl_linux_map_destroy(void);
+
+#endif
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/misc.c b/drivers/mxc/amd-gpu/platform/hal/linux/misc.c
new file mode 100644
index 000000000000..a356f334b187
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/misc.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <gsl.h>
+
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+typedef struct _gsl_autogate_t {
+    struct timer_list timer;	
+    spinlock_t lock;
+    int active;
+    int timeout;
+    gsl_device_t *dev;
+} gsl_autogate_t;
+
+
+#define KGSL_DEVICE_IDLE_TIMEOUT 5000	/* unit ms */
+
+int kgsl_device_active(gsl_device_t *dev)
+{
+	unsigned long flags;
+	gsl_autogate_t *autogate = dev->autogate;
+	if (!autogate) {
+		printk(KERN_ERR "%s: autogate has exited!\n", __func__);
+		return 0;
+	}
+//	printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, dev->id, autogate->active);
+
+	spin_lock_irqsave(&autogate->lock, flags);
+	if (!autogate->active)
+		kgsl_clock(autogate->dev->id, 1);
+	autogate->active = 1;
+	mod_timer(&autogate->timer, jiffies + msecs_to_jiffies(autogate->timeout));
+	spin_unlock_irqrestore(&autogate->lock, flags);
+	return 0;
+}
+
+static void kgsl_device_inactive(unsigned long data)
+{
+	gsl_autogate_t *autogate = (gsl_autogate_t *)data;
+	unsigned long flags;
+
+//	printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, autogate->dev->id, autogate->active);
+	del_timer(&autogate->timer);
+	spin_lock_irqsave(&autogate->lock, flags);
+	WARN(!autogate->active, "GPU Device %d is already inactive\n", autogate->dev->id);
+	autogate->active = 0;
+	/* idle check may sleep, so don't use it */
+//	if (autogate->dev->ftbl.device_idle) 
+//		autogate->dev->ftbl.device_idle(autogate->dev, GSL_TIMEOUT_DEFAULT);
+	kgsl_clock(autogate->dev->id, 0);
+	spin_unlock_irqrestore(&autogate->lock, flags);
+}
+
+int kgsl_device_clock(gsl_deviceid_t id, int enable)
+{
+	int ret = GSL_SUCCESS;
+	gsl_device_t *device;
+
+	device = &gsl_driver.device[id-1];       // device_id is 1 based
+	if (device->flags & GSL_FLAGS_INITIALIZED) {
+		if (enable)
+			kgsl_device_active(device);
+		else
+			kgsl_device_inactive((unsigned long)device);
+	} else {
+		printk(KERN_ERR "%s: Dev %d clock is already off!\n", __func__, id);
+		ret = GSL_FAILURE;
+	}
+	
+	return ret;
+}
+
+int kgsl_device_autogate_init(gsl_device_t *dev)
+{
+	gsl_autogate_t *autogate;
+
+//	printk(KERN_ERR "%s:%d id %d\n", __func__, __LINE__, dev->id);
+	autogate = kmalloc(sizeof(gsl_autogate_t), GFP_KERNEL);
+	if (!autogate) {
+		printk(KERN_ERR "%s: out of memory!\n", __func__);
+		return -ENOMEM;
+	}
+	autogate->dev = dev;
+	autogate->active = 1;
+	spin_lock_init(&autogate->lock);
+	autogate->timeout = KGSL_DEVICE_IDLE_TIMEOUT;
+	init_timer(&autogate->timer);
+	autogate->timer.expires = jiffies + msecs_to_jiffies(autogate->timeout);
+	autogate->timer.function = kgsl_device_inactive;
+	autogate->timer.data = (unsigned long)autogate;
+	add_timer(&autogate->timer);
+	dev->autogate = autogate;
+	return 0;
+}
+
+void kgsl_device_autogate_exit(gsl_device_t *dev)
+{
+	gsl_autogate_t *autogate = dev->autogate;
+
+//	printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, dev->id,  autogate->active);
+	if (autogate->active)
+		del_timer(&autogate->timer);
+	else
+		kgsl_clock(autogate->dev->id, 1);
+
+	kfree(autogate);
+	dev->autogate = NULL;
+
+}
diff --git a/drivers/mxc/ipu/ipu_common.c b/drivers/mxc/ipu/ipu_common.c
index 43ba100b5c5d..a1dc566e7f8f 100644
--- a/drivers/mxc/ipu/ipu_common.c
+++ b/drivers/mxc/ipu/ipu_common.c
@@ -707,6 +707,38 @@ int32_t ipu_select_buffer(ipu_channel_t channel, ipu_buffer_t type,
 }
 
 /*!
+ * This function check buffer ready for a logical channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to clear.
+ *
+ * @param       bufNum          Input parameter for which buffer number clear
+ * 				ready state.
+ *
+ */
+int32_t ipu_check_buffer_busy(ipu_channel_t channel, ipu_buffer_t type,
+		uint32_t bufNum)
+{
+	uint32_t dma_chan = channel_2_dma(channel, type);
+	uint32_t reg;
+
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	if (bufNum == 0)
+		reg = __raw_readl(IPU_CHA_BUF0_RDY);
+	else
+		reg = __raw_readl(IPU_CHA_BUF1_RDY);
+
+	if (reg & (1UL << dma_chan))
+		return 1;
+	else
+		return 0;
+}
+EXPORT_SYMBOL(ipu_check_buffer_busy);
+
+/*!
  * This function links 2 channels together for automatic frame
  * synchronization. The output of the source channel is linked to the input of
  * the destination channel.
diff --git a/drivers/mxc/ipu/ipu_csi.c b/drivers/mxc/ipu/ipu_csi.c
index 10708cf3ba54..58d58c10af51 100644
--- a/drivers/mxc/ipu/ipu_csi.c
+++ b/drivers/mxc/ipu/ipu_csi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -90,10 +90,13 @@ ipu_csi_init_interface(uint16_t width, uint16_t height, uint32_t pixel_fmt,
 	__raw_writel(height << 16 | 0x22, CSI_FLASH_STROBE_2);
 
 	/* Set CCIR registers */
-	if ((sig.clk_mode == IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE) ||
-	    (sig.clk_mode == IPU_CSI_CLK_MODE_CCIR656_INTERLACED)) {
+	if (sig.clk_mode == IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE) {
 		__raw_writel(0x40030, CSI_CCIR_CODE_1);
 		__raw_writel(0xFF0000, CSI_CCIR_CODE_3);
+	} else if (sig.clk_mode == IPU_CSI_CLK_MODE_CCIR656_INTERLACED) {
+		__raw_writel(0xD07DF, CSI_CCIR_CODE_1);
+		__raw_writel(0x40596, CSI_CCIR_CODE_2);
+		__raw_writel(0xFF0000, CSI_CCIR_CODE_3);
 	}
 
 	dev_dbg(g_ipu_dev, "CSI_SENS_CONF = 0x%08X\n",
diff --git a/drivers/mxc/ipu/ipu_device.c b/drivers/mxc/ipu/ipu_device.c
index 5fd1c51ec9b1..713ba2005ae9 100644
--- a/drivers/mxc/ipu/ipu_device.c
+++ b/drivers/mxc/ipu/ipu_device.c
@@ -169,6 +169,7 @@ static int mxc_ipu_ioctl(struct inode *inode, struct file *file,
 			     sizeof(ipu_channel_buf_parm))) {
 				return -EFAULT;
 			}
+
 			ret =
 			    ipu_init_channel_buffer(parm.channel, parm.type,
 						    parm.pixel_fmt,
diff --git a/drivers/mxc/ipu/ipu_ic.c b/drivers/mxc/ipu/ipu_ic.c
index cdf823a2760b..9fe087590368 100644
--- a/drivers/mxc/ipu/ipu_ic.c
+++ b/drivers/mxc/ipu/ipu_ic.c
@@ -71,8 +71,7 @@ void _ipu_ic_enable_task(ipu_channel_t channel)
 	case MEM_ROT_PP_MEM:
 		ic_conf |= IC_CONF_PP_ROT_EN;
 		break;
-	case CSI_MEM:
-		// ???
+	case CSI_MEM1:
 		ic_conf |= IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
 		break;
 	default:
@@ -110,8 +109,7 @@ void _ipu_ic_disable_task(ipu_channel_t channel)
 	case MEM_ROT_PP_MEM:
 		ic_conf &= ~IC_CONF_PP_ROT_EN;
 		break;
-	case CSI_MEM:
-		// ???
+	case CSI_MEM1:
 		ic_conf &= ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN);
 		break;
 	default:
diff --git a/drivers/mxc/ipu/pf/mxc_pf.c b/drivers/mxc/ipu/pf/mxc_pf.c
index 744152415e3a..8abffb4d8d44 100644
--- a/drivers/mxc/ipu/pf/mxc_pf.c
+++ b/drivers/mxc/ipu/pf/mxc_pf.c
@@ -108,6 +108,7 @@ static int mxc_pf_init(pf_init_params * pf_init)
 
 	memset(&params, 0, sizeof(params));
 	params.mem_pf_mem.operation = pf_data.mode;
+
 	err = ipu_init_channel(MEM_PF_Y_MEM, &params);
 	if (err < 0) {
 		printk(KERN_ERR "mxc_pf: error initializing channel\n");
diff --git a/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c b/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c
index 6a29c90fe095..5d5e0b9155a0 100644
--- a/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c
+++ b/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c
@@ -260,7 +260,7 @@ int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
 				input_frame_width >> 1;
 			left->output_width = right->output_width = right->output_column =
 				output_frame_width >> 1;
-			left->input_column = right->input_column = 0;
+			left->input_column = 0;
 			div = _do_div(((((u64)irr_steps) << 32) *
 				       (right->input_width - 1)), (right->output_width - 1));
 			left->irr = right->irr = truncate(0, div, 1);
diff --git a/drivers/mxc/ipu3/ipu_capture.c b/drivers/mxc/ipu3/ipu_capture.c
index 5d084ab37b0b..e801705f8fe9 100644
--- a/drivers/mxc/ipu3/ipu_capture.c
+++ b/drivers/mxc/ipu3/ipu_capture.c
@@ -101,11 +101,18 @@ ipu_csi_init_interface(uint16_t width, uint16_t height, uint32_t pixel_fmt,
 	__raw_writel((width - 1) | (height - 1) << 16, CSI_SENS_FRM_SIZE(csi));
 
 	/* Set CCIR registers */
-	if ((cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE) ||
-	    (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_INTERLACED)) {
-		_ipu_csi_ccir_err_detection_enable(csi);
+	if (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE) {
 		__raw_writel(0x40030, CSI_CCIR_CODE_1(csi));
 		__raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi));
+	} else if (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_INTERLACED) {
+		_ipu_csi_ccir_err_detection_enable(csi);
+		/* Field0BlankEnd = 0x7, Field0BlankStart = 0x3,
+		   Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1 */
+		__raw_writel(0xD07DF, CSI_CCIR_CODE_1(csi));
+		/* Field1BlankEnd = 0x6, Field1BlankStart = 0x2,
+		   Field1ActiveEnd = 0x4, Field1ActiveStart = 0 */
+		__raw_writel(0x40596, CSI_CCIR_CODE_2(csi));
+		__raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi));
 	} else if ((cfg_param.clk_mode ==
 			IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR) ||
 		(cfg_param.clk_mode ==
@@ -184,7 +191,8 @@ int ipu_csi_enable_mclk(int csi, bool flag, bool wait)
 				return -EINVAL;
 			}
 		} else
-			clk_enable(g_csi_clk[csi]);
+			// CCWMX51 - Both CSIs from master clock 0
+			clk_enable(g_csi_clk[0]);
 		if (wait == true)
 			msleep(10);
 	} else {
@@ -198,7 +206,8 @@ int ipu_csi_enable_mclk(int csi, bool flag, bool wait)
 				return -EINVAL;
 			}
 		} else
-			clk_disable(g_csi_clk[csi]);
+			// CCWMX51 - Both CSIs from master clock 0
+			clk_disable(g_csi_clk[0]);
 	}
 
 	return 0;
@@ -585,7 +594,6 @@ void _ipu_smfc_init(ipu_channel_t channel, uint32_t mipi_id, uint32_t csi)
 	default:
 		return;
 	}
-
 	__raw_writel(temp, SMFC_MAP);
 }
 
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
index 68be542e8370..eae3b549d765 100644
--- a/drivers/mxc/ipu3/ipu_common.c
+++ b/drivers/mxc/ipu3/ipu_common.c
@@ -52,8 +52,8 @@ unsigned char g_dc_di_assignment[10];
 ipu_channel_t g_ipu_csi_channel[2];
 int g_ipu_irq[2];
 int g_ipu_hw_rev;
-bool g_sec_chan_en[22];
-bool g_thrd_chan_en[21];
+bool g_sec_chan_en[24];
+bool g_thrd_chan_en[24];
 uint32_t g_channel_init_mask;
 uint32_t g_channel_enable_mask;
 DEFINE_SPINLOCK(ipu_lock);
@@ -372,7 +372,7 @@ static int ipu_probe(struct platform_device *pdev)
 	_ipu_dmfc_init(DMFC_NORMAL, 1);
 
 	/* Set sync refresh channels and CSI->mem channel as high priority */
-	__raw_writel(0x18800001L, IDMAC_CHA_PRI(0));
+	__raw_writel(0x18800003L, IDMAC_CHA_PRI(0));
 
 	/* Set MCU_T to divide MCU access window into 2 */
 	__raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
@@ -415,7 +415,10 @@ int ipu_remove(struct platform_device *pdev)
 
 void ipu_dump_registers(void)
 {
+	printk(KERN_DEBUG "--------------------------------------------\n");
 	printk(KERN_DEBUG "IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF));
+	printk(KERN_DEBUG "SMFC_MAP = \t0x%08X\n", __raw_readl(SMFC_MAP));
+	printk(KERN_DEBUG "SMFC_WMC = \t0x%08X\n", __raw_readl(SMFC_WMC));
 	printk(KERN_DEBUG "IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF));
 	printk(KERN_DEBUG "IDMAC_CHA_EN1 = \t0x%08X\n",
 	       __raw_readl(IDMAC_CHA_EN(0)));
@@ -451,6 +454,25 @@ void ipu_dump_registers(void)
 	       __raw_readl(IPU_FS_PROC_FLOW3));
 	printk(KERN_DEBUG "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
 	       __raw_readl(IPU_FS_DISP_FLOW1));
+
+	printk(KERN_DEBUG "IPU_INT_CTRL_1 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL (1)));
+	printk(KERN_DEBUG "IPU_INT_STAT_1 = \t0x%08X\n", __raw_readl(IPU_INT_STAT (1)));
+	printk(KERN_DEBUG "IPU_INT_STAT_2 = \t0x%08X\n", __raw_readl(IPU_INT_STAT (2)));
+	printk(KERN_DEBUG "IPU_INT_STAT_3 = \t0x%08X\n", __raw_readl(IPU_INT_STAT (3)));
+	printk(KERN_DEBUG "IPU_INT_STAT_4 = \t0x%08X\n", __raw_readl(IPU_INT_STAT (4)));
+	printk(KERN_DEBUG "IPU_INT_STAT_5 = \t0x%08X\n", __raw_readl(IPU_INT_STAT (5)));
+	printk(KERN_DEBUG "IPU_INT_STAT_6 = \t0x%08X\n", __raw_readl(IPU_INT_STAT (6)));
+
+	printk(KERN_DEBUG "CSI0_SENS_CONF = \t0x%08X\n", __raw_readl(CSI_SENS_CONF (0)));
+	printk(KERN_DEBUG "CSI0_SENS_FRM_SIZE = \t0x%08X\n", __raw_readl(CSI_SENS_FRM_SIZE(0)));
+	printk(KERN_DEBUG "CSI0_ACT_FRM_SIZE = \t0x%08X\n", __raw_readl(CSI_ACT_FRM_SIZE(0)));
+	printk(KERN_DEBUG "CSI0_SKIP = \t0x%08X\n", __raw_readl(CSI_SKIP(0)));
+
+	printk(KERN_DEBUG "CSI1_SENS_CONF = \t0x%08X\n", __raw_readl(CSI_SENS_CONF (1)));
+	printk(KERN_DEBUG "CSI1_SENS_FRM_SIZE = \t0x%08X\n", __raw_readl(CSI_SENS_FRM_SIZE(1)));
+	printk(KERN_DEBUG "CSI1_ACT_FRM_SIZE = \t0x%08X\n", __raw_readl(CSI_ACT_FRM_SIZE(1)));
+	printk(KERN_DEBUG "CSI1_SKIP = \t0x%08X\n", __raw_readl(CSI_SKIP(1)));
+	printk(KERN_DEBUG "--------------------------------------------\n");
 }
 
 /*!
@@ -660,7 +682,8 @@ int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
 
 		g_dc_di_assignment[1] = params->mem_dc_sync.di;
 		_ipu_dc_init(1, params->mem_dc_sync.di,
-			     params->mem_dc_sync.interlaced);
+			     params->mem_dc_sync.interlaced,
+			     params->mem_dc_sync.out_pixel_fmt);
 		ipu_di_use_count[params->mem_dc_sync.di]++;
 		ipu_dc_use_count++;
 		ipu_dmfc_use_count++;
@@ -678,7 +701,8 @@ int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
 		_ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
 			     params->mem_dp_bg_sync.out_pixel_fmt);
 		_ipu_dc_init(5, params->mem_dp_bg_sync.di,
-			     params->mem_dp_bg_sync.interlaced);
+			     params->mem_dp_bg_sync.interlaced,
+			     params->mem_dp_bg_sync.out_pixel_fmt);
 		ipu_di_use_count[params->mem_dp_bg_sync.di]++;
 		ipu_dc_use_count++;
 		ipu_dp_use_count++;
@@ -702,7 +726,7 @@ int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
 		}
 
 		g_dc_di_assignment[8] = params->direct_async.di;
-		_ipu_dc_init(8, params->direct_async.di, false);
+		_ipu_dc_init(8, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
 		ipu_di_use_count[params->direct_async.di]++;
 		ipu_dc_use_count++;
 		break;
@@ -713,7 +737,7 @@ int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
 		}
 
 		g_dc_di_assignment[9] = params->direct_async.di;
-		_ipu_dc_init(9, params->direct_async.di, false);
+		_ipu_dc_init(9, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
 		ipu_di_use_count[params->direct_async.di]++;
 		ipu_dc_use_count++;
 		break;
@@ -724,31 +748,8 @@ int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
 
 	/* Enable IPU sub module */
 	g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
-	if (ipu_ic_use_count == 1)
-		ipu_conf |= IPU_CONF_IC_EN;
-	if (ipu_vdi_use_count == 1) {
-		ipu_conf |= IPU_CONF_VDI_EN;
-		ipu_conf |= IPU_CONF_IC_INPUT;
-	}
-	if (ipu_rot_use_count == 1)
-		ipu_conf |= IPU_CONF_ROT_EN;
-	if (ipu_dc_use_count == 1)
-		ipu_conf |= IPU_CONF_DC_EN;
-	if (ipu_dp_use_count == 1)
-		ipu_conf |= IPU_CONF_DP_EN;
-	if (ipu_dmfc_use_count == 1)
-		ipu_conf |= IPU_CONF_DMFC_EN;
-	if (ipu_di_use_count[0] == 1) {
-		ipu_conf |= IPU_CONF_DI0_EN;
-	}
-	if (ipu_di_use_count[1] == 1) {
-		ipu_conf |= IPU_CONF_DI1_EN;
-	}
-	if (ipu_smfc_use_count == 1)
-		ipu_conf |= IPU_CONF_SMFC_EN;
 
 	__raw_writel(ipu_conf, IPU_CONF);
-
 err:
 	spin_unlock_irqrestore(&ipu_lock, lock_flags);
 	return ret;
@@ -775,8 +776,8 @@ void ipu_uninit_channel(ipu_channel_t channel)
 
 	/* Make sure channel is disabled */
 	/* Get input and output dma channels */
-	in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
-	out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+	in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+	out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
 
 	if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
 	    idma_is_set(IDMAC_CHA_EN, out_dma)) {
@@ -796,8 +797,10 @@ void ipu_uninit_channel(ipu_channel_t channel)
 	reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
 	__raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
 
-	g_sec_chan_en[IPU_CHAN_ID(channel)] = false;
-	g_thrd_chan_en[IPU_CHAN_ID(channel)] = false;
+	if (_ipu_is_ic_chan(in_dma) || _ipu_is_dp_graphic_chan(in_dma)) {
+		g_sec_chan_en[IPU_CHAN_ID(channel)] = false;
+		g_thrd_chan_en[IPU_CHAN_ID(channel)] = false;
+	}
 
 	switch (channel) {
 	case CSI_MEM0:
@@ -849,6 +852,9 @@ void ipu_uninit_channel(ipu_channel_t channel)
 		reg = __raw_readl(IPU_FS_PROC_FLOW1);
 		__raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
 		break;
+	case MEM_VDI_PRP_VF_MEM_P:
+	case MEM_VDI_PRP_VF_MEM_N:
+		break;
 	case MEM_ROT_VF_MEM:
 		ipu_rot_use_count--;
 		ipu_ic_use_count--;
@@ -913,6 +919,7 @@ void ipu_uninit_channel(ipu_channel_t channel)
 	if (ipu_ic_use_count == 0)
 		ipu_conf &= ~IPU_CONF_IC_EN;
 	if (ipu_vdi_use_count == 0) {
+		ipu_conf &= ~IPU_CONF_ISP_EN;
 		ipu_conf &= ~IPU_CONF_VDI_EN;
 		ipu_conf &= ~IPU_CONF_IC_INPUT;
 	}
@@ -1239,8 +1246,6 @@ int32_t ipu_select_buffer(ipu_channel_t channel, ipu_buffer_t type,
 		__raw_writel(idma_mask(dma_chan) | reg,
 			     IPU_CHA_BUF1_RDY(dma_chan));
 	}
-	if (channel == MEM_VDI_PRP_VF_MEM)
-		_ipu_vdi_toggle_top_field_man();
 	return 0;
 }
 EXPORT_SYMBOL(ipu_select_buffer);
@@ -1269,10 +1274,9 @@ int32_t ipu_select_multi_vdi_buffer(uint32_t bufNum)
 		__raw_writel(mask_bit | reg, IPU_CHA_BUF0_RDY(dma_chan));
 	} else {
 		/*Mark buffer 1 as ready. */
-		reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan));
+		reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan));
 		__raw_writel(mask_bit | reg, IPU_CHA_BUF1_RDY(dma_chan));
 	}
-	_ipu_vdi_toggle_top_field_man();
 	return 0;
 }
 EXPORT_SYMBOL(ipu_select_multi_vdi_buffer);
@@ -1282,7 +1286,7 @@ static int proc_dest_sel[] =
   { 0, 1, 1, 3, 5, 5, 4, 7, 8, 9, 10, 11, 12, 14, 15, 16,
     0, 1, 1, 5, 5, 5, 5, 5, 7, 8, 9, 10, 11, 12, 14, 31 };
 static int proc_src_sel[] = { 0, 6, 7, 6, 7, 8, 5, NA, NA, NA,
-  NA, NA, NA, NA, NA,  1,  2,  3,  4,  7,  8, NA, NA, NA };
+  NA, NA, NA, NA, NA,  1,  2,  3,  4,  7,  8, NA, 8, NA };
 static int disp_src_sel[] = { 0, 6, 7, 8, 3, 4, 5, NA, NA, NA,
   NA, NA, NA, NA, NA,  1, NA,  2, NA,  3,  4,  4,  4,  4 };
 
@@ -1659,6 +1663,7 @@ int32_t ipu_enable_channel(ipu_channel_t channel)
 {
 	uint32_t reg;
 	unsigned long lock_flags;
+	uint32_t ipu_conf;
 	uint32_t in_dma;
 	uint32_t out_dma;
 	uint32_t sec_dma;
@@ -1675,6 +1680,32 @@ int32_t ipu_enable_channel(ipu_channel_t channel)
 
 	spin_lock_irqsave(&ipu_lock, lock_flags);
 
+	ipu_conf = __raw_readl(IPU_CONF);
+	if (ipu_di_use_count[0] > 0) {
+		ipu_conf |= IPU_CONF_DI0_EN;
+	}
+	if (ipu_di_use_count[1] > 0) {
+		ipu_conf |= IPU_CONF_DI1_EN;
+	}
+	if (ipu_dp_use_count > 0)
+		ipu_conf |= IPU_CONF_DP_EN;
+	if (ipu_dc_use_count > 0)
+		ipu_conf |= IPU_CONF_DC_EN;
+	if (ipu_dmfc_use_count > 0)
+		ipu_conf |= IPU_CONF_DMFC_EN;
+	if (ipu_ic_use_count > 0)
+		ipu_conf |= IPU_CONF_IC_EN;
+	if (ipu_vdi_use_count > 0) {
+		ipu_conf |= IPU_CONF_ISP_EN;
+		ipu_conf |= IPU_CONF_VDI_EN;
+		ipu_conf |= IPU_CONF_IC_INPUT;
+	}
+	if (ipu_rot_use_count > 0)
+		ipu_conf |= IPU_CONF_ROT_EN;
+	if (ipu_smfc_use_count > 0)
+		ipu_conf |= IPU_CONF_SMFC_EN;
+	__raw_writel(ipu_conf, IPU_CONF);
+
 	if (idma_is_valid(in_dma)) {
 		reg = __raw_readl(IDMAC_CHA_EN(in_dma));
 		__raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
@@ -1710,8 +1741,11 @@ int32_t ipu_enable_channel(ipu_channel_t channel)
 	}
 
 	if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
-	    (channel == MEM_FG_SYNC))
+	    (channel == MEM_FG_SYNC)) {
+		reg = __raw_readl(IDMAC_WM_EN(in_dma));
+		__raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
 		_ipu_dp_dc_enable(channel);
+	}
 
 	if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
 		_ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma))
@@ -1726,6 +1760,38 @@ int32_t ipu_enable_channel(ipu_channel_t channel)
 EXPORT_SYMBOL(ipu_enable_channel);
 
 /*!
+ * This function check buffer ready for a logical channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to clear.
+ *
+ * @param       bufNum          Input parameter for which buffer number clear
+ * 				ready state.
+ *
+ */
+int32_t ipu_check_buffer_busy(ipu_channel_t channel, ipu_buffer_t type,
+		uint32_t bufNum)
+{
+	uint32_t dma_chan = channel_2_dma(channel, type);
+	uint32_t reg;
+
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	if (bufNum == 0)
+		reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan));
+	else
+		reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan));
+
+	if (reg & idma_mask(dma_chan))
+		return 1;
+	else
+		return 0;
+}
+EXPORT_SYMBOL(ipu_check_buffer_busy);
+
+/*!
  * This function clear buffer ready for a logical channel.
  *
  * @param       channel         Input parameter for the logical channel ID.
@@ -1817,7 +1883,30 @@ int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop)
 
 	if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
 	    (channel == MEM_DC_SYNC)) {
+		int timeout = 50;
+		int irq;
+
 		_ipu_dp_dc_disable(channel, false);
+
+		/*
+		 * wait for display channel EOF then disable IDMAC,
+		 * it avoid NFB4EOF error.
+		 */
+		if (channel == MEM_BG_SYNC)
+			irq = IPU_IRQ_BG_SYNC_EOF;
+		if (channel == MEM_FG_SYNC)
+			irq = IPU_IRQ_FG_SYNC_EOF;
+		else
+			irq = IPU_IRQ_DC_SYNC_EOF;
+		__raw_writel(IPUIRQ_2_MASK(irq),
+			     IPUIRQ_2_STATREG(irq));
+		while ((__raw_readl(IPUIRQ_2_STATREG(irq)) &
+			IPUIRQ_2_MASK(irq)) == 0) {
+			msleep(10);
+			timeout -= 10;
+			if (timeout <= 0)
+				break;
+		}
 	} else if (wait_for_stop) {
 		while (idma_is_set(IDMAC_CHA_BUSY, in_dma) ||
 		       idma_is_set(IDMAC_CHA_BUSY, out_dma) ||
@@ -1861,6 +1950,12 @@ int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop)
 
 	spin_lock_irqsave(&ipu_lock, lock_flags);
 
+	if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
+	    (channel == MEM_DC_SYNC)) {
+		reg = __raw_readl(IDMAC_WM_EN(in_dma));
+		__raw_writel(reg & ~idma_mask(in_dma), IDMAC_WM_EN(in_dma));
+	}
+
 	/* Disable IC task */
 	if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
 		_ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma))
@@ -1897,8 +1992,6 @@ int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop)
 
 	g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
 
-	spin_unlock_irqrestore(&ipu_lock, lock_flags);
-
 	/* Set channel buffers NOT to be ready */
 	if (idma_is_valid(in_dma)) {
 		ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
@@ -1917,6 +2010,8 @@ int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop)
 		ipu_clear_buffer_ready(channel, IPU_ALPHA_IN_BUFFER, 1);
 	}
 
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
 	return 0;
 }
 EXPORT_SYMBOL(ipu_disable_channel);
@@ -2029,7 +2124,6 @@ static irqreturn_t ipu_irq_handler(int irq, void *desc)
 						       dev_id);
 		}
 	}
-
 	return result;
 }
 
diff --git a/drivers/mxc/ipu3/ipu_device.c b/drivers/mxc/ipu3/ipu_device.c
index 27455fe26ab6..bf71ea833f58 100644
--- a/drivers/mxc/ipu3/ipu_device.c
+++ b/drivers/mxc/ipu3/ipu_device.c
@@ -124,7 +124,6 @@ static int mxc_ipu_ioctl(struct inode *inode, struct file *file,
 				(&parm, (ipu_channel_buf_parm *) arg,
 				sizeof(ipu_channel_buf_parm)))
 				return -EFAULT;
-
 			ret =
 				ipu_init_channel_buffer(
 						parm.channel, parm.type,
@@ -183,6 +182,17 @@ static int mxc_ipu_ioctl(struct inode *inode, struct file *file,
 
 		}
 		break;
+	case IPU_SELECT_MULTI_VDI_BUFFER:
+		{
+			uint32_t parm;
+			if (copy_from_user
+				(&parm, (uint32_t *) arg,
+				sizeof(uint32_t)))
+				return -EFAULT;
+
+			ret = ipu_select_multi_vdi_buffer(parm);
+		}
+		break;
 	case IPU_LINK_CHANNELS:
 		{
 			ipu_channel_link link;
@@ -225,7 +235,6 @@ static int mxc_ipu_ioctl(struct inode *inode, struct file *file,
 				(&info, (ipu_channel_info *) arg,
 				 sizeof(ipu_channel_info)))
 				return -EFAULT;
-
 			ret = ipu_disable_channel(info.channel,
 				info.stop);
 		}
@@ -435,7 +444,7 @@ static int mxc_ipu_ioctl(struct inode *inode, struct file *file,
 
 static int mxc_ipu_mmap(struct file *file, struct vm_area_struct *vma)
 {
-//	vma->vm_page_prot = pgprot_writethru(vma->vm_page_prot);
+	vma->vm_page_prot = pgprot_writethru(vma->vm_page_prot);
 
 	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 				vma->vm_end - vma->vm_start,
@@ -452,12 +461,20 @@ static int mxc_ipu_release(struct inode *inode, struct file *file)
 	return 0;
 }
 
+int mxc_ipu_fsync(struct file *filp, struct dentry *dentry, int datasync)
+{
+	flush_cache_all();
+	outer_flush_all();
+	return 0;
+}
+
 static struct file_operations mxc_ipu_fops = {
 	.owner = THIS_MODULE,
 	.open = mxc_ipu_open,
 	.mmap = mxc_ipu_mmap,
 	.release = mxc_ipu_release,
-	.ioctl = mxc_ipu_ioctl
+	.ioctl = mxc_ipu_ioctl,
+	.fsync = mxc_ipu_fsync
 };
 
 int register_ipu_device()
diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c
index 00c5008d149f..7ce04d8bca9e 100644
--- a/drivers/mxc/ipu3/ipu_disp.c
+++ b/drivers/mxc/ipu3/ipu_disp.c
@@ -147,6 +147,37 @@ static int __init dmfc_setup(char *options)
 }
 __setup("dmfc=", dmfc_setup);
 
+static bool _ipu_update_dmfc_used_size(int dma_chan, int width, int dmfc_size)
+{
+	u32 fifo_size_5f = 1;
+	u32 dmfc_dp_chan = __raw_readl(DMFC_DP_CHAN);
+
+	if ((width > 352) && (dmfc_size == (256 * 4)))
+		fifo_size_5f = 1;
+	else if (width > 176)
+		fifo_size_5f = 2;
+	else if (width > 88)
+		fifo_size_5f = 3;
+	else if (width > 44)
+		fifo_size_5f = 4;
+	else if (width > 22)
+		fifo_size_5f = 5;
+	else if (width > 11)
+		fifo_size_5f = 6;
+	else if (width > 6)
+		fifo_size_5f = 7;
+	else
+		return false;
+
+	if (dma_chan == 27) {
+		dmfc_dp_chan &= ~DMFC_FIFO_SIZE_5F;
+		dmfc_dp_chan |= fifo_size_5f << 11;
+		__raw_writel(dmfc_dp_chan, DMFC_DP_CHAN);
+	}
+
+	return true;
+}
+
 void _ipu_dmfc_set_wait4eot(int dma_chan, int width)
 {
 	u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1);
@@ -169,7 +200,7 @@ void _ipu_dmfc_set_wait4eot(int dma_chan, int width)
 		else
 			dmfc_gen1 &= ~(1UL << 22);
 	} else if (dma_chan == 27) { /*5F*/
-		if (dmfc_size_27/width > 2)
+		if (!_ipu_update_dmfc_used_size(dma_chan, width, dmfc_size_27))
 			dmfc_gen1 |= 1UL << 21;
 		else
 			dmfc_gen1 &= ~(1UL << 21);
@@ -245,6 +276,24 @@ static void _ipu_di_sync_config(int di, int wave_gen,
 	__raw_writel(reg, DI_STP_REP(di, wave_gen));
 }
 
+static void _ipu_dc_map_link(int current_map,
+			     int base_map_0, int buf_num_0,
+			     int base_map_1, int buf_num_1,
+			     int base_map_2, int buf_num_2)
+{
+	int ptr_0 = base_map_0 * 3 + buf_num_0;
+	int ptr_1 = base_map_1 * 3 + buf_num_1;
+	int ptr_2 = base_map_2 * 3 + buf_num_2;
+	int ptr;
+	u32 reg;
+	ptr = (ptr_2 << 10) +  (ptr_1 << 5) + ptr_0;
+
+	reg = __raw_readl(DC_MAP_CONF_PTR(current_map));
+	reg &= ~(0x1F << ((16 * (current_map & 0x1))));
+	reg |= ptr << ((16 * (current_map & 0x1)));
+	__raw_writel(reg, DC_MAP_CONF_PTR(current_map));
+}
+
 static void _ipu_dc_map_config(int map, int byte_num, int offset, int mask)
 {
 	int ptr = map * 3 + byte_num;
@@ -290,11 +339,30 @@ static void _ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map,
 static void _ipu_dc_link_event(int chan, int event, int addr, int priority)
 {
 	u32 reg;
-
-	reg = __raw_readl(DC_RL_CH(chan, event));
-	reg &= ~(0xFFFF << (16 * (event & 0x1)));
-	reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
-	__raw_writel(reg, DC_RL_CH(chan, event));
+	u32 address_shift;
+	if (event < DC_EVEN_UGDE0) {
+		reg = __raw_readl(DC_RL_CH(chan, event));
+		reg &= ~(0xFFFF << (16 * (event & 0x1)));
+		reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
+		__raw_writel(reg, DC_RL_CH(chan, event));
+	} else {
+		reg = __raw_readl(DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
+		if ((event - DC_EVEN_UGDE0) & 0x1) {
+			reg &= ~(0x2FF << 16);
+			reg |= (addr << 16);
+			reg |= priority ? (2 << 24) : 0x0;
+		} else {
+			reg &= ~0xFC00FFFF;
+			if (priority)
+				chan = (chan >> 1) +
+					((((chan & 0x1) + ((chan & 0x2) >> 1))) | (chan >> 3));
+			else
+				chan = 0x7;
+			address_shift = ((event - DC_EVEN_UGDE0) >> 1) ? 7 : 8;
+			reg |= (addr << address_shift) | (priority << 3) | chan;
+		}
+		__raw_writel(reg, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
+	}
 }
 
 /*     Y = R *  1.200 + G *  2.343 + B *  .453 + 0.250;
@@ -503,7 +571,7 @@ void _ipu_dp_uninit(ipu_channel_t channel)
 	__ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], false);
 }
 
-void _ipu_dc_init(int dc_chan, int di, bool interlaced)
+void _ipu_dc_init(int dc_chan, int di, bool interlaced, uint32_t pixel_fmt)
 {
 	u32 reg = 0;
 
@@ -517,10 +585,24 @@ void _ipu_dc_init(int dc_chan, int di, bool interlaced)
 				_ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3);
 				_ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2);
 				_ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 4, 1);
+				if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+				(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+				(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+				(pixel_fmt == IPU_PIX_FMT_VYUY)) {
+					_ipu_dc_link_event(dc_chan, DC_ODD_UGDE1, 9, 5);
+					_ipu_dc_link_event(dc_chan, DC_EVEN_UGDE1, 8, 5);
+				}
 			} else {
 				_ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3);
 				_ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2);
 				_ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 7, 1);
+				if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+				(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+				(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+				(pixel_fmt == IPU_PIX_FMT_VYUY)) {
+					_ipu_dc_link_event(dc_chan, DC_ODD_UGDE0, 10, 5);
+					_ipu_dc_link_event(dc_chan, DC_EVEN_UGDE0, 11, 5);
+				}
 			}
 		}
 		_ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
@@ -562,6 +644,10 @@ void _ipu_dc_uninit(int dc_chan)
 		_ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
 		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
 		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_ODD_UGDE0, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVEN_UGDE0, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_ODD_UGDE1, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVEN_UGDE1, 0, 0);
 	} else if ((dc_chan == 8) || (dc_chan == 9)) {
 		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
 		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
@@ -689,29 +775,6 @@ void _ipu_dp_dc_disable(ipu_channel_t channel, bool swap)
 			if (timeout <= 0)
 				break;
 		}
-
-		timeout = 50;
-
-		/*
-		 * Wait for DC triple buffer to empty,
-		 * this check is useful for tv overlay.
-		 */
-		if (g_dc_di_assignment[dc_chan] == 0)
-			while ((__raw_readl(DC_STAT) & 0x00000002)
-			       != 0x00000002) {
-				msleep(2);
-				timeout -= 2;
-				if (timeout <= 0)
-					break;
-			}
-		else if (g_dc_di_assignment[dc_chan] == 1)
-			while ((__raw_readl(DC_STAT) & 0x00000020)
-			       != 0x00000020) {
-				msleep(2);
-				timeout -= 2;
-				if (timeout <= 0)
-					break;
-			}
 		return;
 	} else {
 		return;
@@ -743,26 +806,6 @@ void _ipu_dp_dc_disable(ipu_channel_t channel, bool swap)
 		__raw_writel(reg, DC_WR_CH_CONF(dc_chan));
 		spin_unlock_irqrestore(&ipu_lock, lock_flags);
 	} else {
-		timeout = 50;
-
-		/* Wait for DC triple buffer to empty */
-		if (g_dc_di_assignment[dc_chan] == 0)
-			while ((__raw_readl(DC_STAT) & 0x00000002)
-				!= 0x00000002) {
-				msleep(2);
-				timeout -= 2;
-				if (timeout <= 0)
-					break;
-			}
-		else if (g_dc_di_assignment[dc_chan] == 1)
-			while ((__raw_readl(DC_STAT) & 0x00000020)
-				!= 0x00000020) {
-				msleep(2);
-				timeout -= 2;
-				if (timeout <= 0)
-					break;
-			}
-
 		spin_lock_irqsave(&ipu_lock, lock_flags);
 		reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
 		reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
@@ -821,6 +864,34 @@ void _ipu_init_dc_mappings(void)
 	_ipu_dc_map_config(4, 0, 5, 0xFC);
 	_ipu_dc_map_config(4, 1, 13, 0xFC);
 	_ipu_dc_map_config(4, 2, 21, 0xFC);
+
+	/* IPU_PIX_FMT_VYUY 16bit width */
+	_ipu_dc_map_clear(5);
+	_ipu_dc_map_config(5, 0, 7, 0xFF);
+	_ipu_dc_map_config(5, 1, 0, 0x0);
+	_ipu_dc_map_config(5, 2, 15, 0xFF);
+	_ipu_dc_map_clear(6);
+	_ipu_dc_map_config(6, 0, 0, 0x0);
+	_ipu_dc_map_config(6, 1, 7, 0xFF);
+	_ipu_dc_map_config(6, 2, 15, 0xFF);
+
+	/* IPU_PIX_FMT_UYUV 16bit width */
+	_ipu_dc_map_clear(7);
+	_ipu_dc_map_link(7, 6, 0, 6, 1, 6, 2);
+	_ipu_dc_map_clear(8);
+	_ipu_dc_map_link(8, 5, 0, 5, 1, 5, 2);
+
+	/* IPU_PIX_FMT_YUYV 16bit width */
+	_ipu_dc_map_clear(9);
+	_ipu_dc_map_link(9, 5, 2, 5, 1, 5, 0);
+	_ipu_dc_map_clear(10);
+	_ipu_dc_map_link(10, 5, 1, 5, 2, 5, 0);
+
+	/* IPU_PIX_FMT_YVYU 16bit width */
+	_ipu_dc_map_clear(11);
+	_ipu_dc_map_link(11, 5, 1, 5, 2, 5, 0);
+	_ipu_dc_map_clear(12);
+	_ipu_dc_map_link(12, 5, 2, 5, 1, 5, 0);
 }
 
 int _ipu_pixfmt_to_map(uint32_t fmt)
@@ -837,6 +908,14 @@ int _ipu_pixfmt_to_map(uint32_t fmt)
 		return 3;
 	case IPU_PIX_FMT_LVDS666:
 		return 4;
+	case IPU_PIX_FMT_VYUY:
+		return 6;
+	case IPU_PIX_FMT_UYVY:
+		return 8;
+	case IPU_PIX_FMT_YUYV:
+		return 10;
+	case IPU_PIX_FMT_YVYU:
+		return 12;
 	}
 
 	return -1;
@@ -968,18 +1047,14 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
 		if ((clk_get_usecount(g_pixel_clk[0]) == 0) &&
 				(clk_get_usecount(g_pixel_clk[1]) == 0)) {
 			di_parent = clk_get_parent(g_di_clk[disp]);
-			if (strcmp(di_parent->name, "tve_clk") != 0) {
-				rounded_pixel_clk =
-					clk_round_rate(g_pixel_clk[disp], pixel_clk);
-				div  = clk_get_rate(di_parent) / rounded_pixel_clk;
-				if (div % 2)
-					div++;
-
-				if (clk_get_rate(di_parent) != div * rounded_pixel_clk)
-					clk_set_rate(di_parent, div * rounded_pixel_clk);
-				msleep(10);
-				clk_set_rate(g_di_clk[disp], 2 * rounded_pixel_clk);
-				msleep(10);
+			if (strcmp(di_parent->name, "tve_clk") != 0 &&
+			    strcmp(di_parent->name, "ldb_di0_clk") != 0 &&
+			    strcmp(di_parent->name, "ldb_di1_clk") != 0)  {
+				rounded_pixel_clk = pixel_clk * 2;
+				while (rounded_pixel_clk < 150000000)
+					rounded_pixel_clk += pixel_clk * 2;
+				clk_set_rate(di_parent, rounded_pixel_clk);
+				clk_set_rate(g_di_clk[disp], pixel_clk);
 			}
 		}
 		clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]);
@@ -1322,10 +1397,28 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
 
 		/* Init template microcode */
 		if (disp) {
+			if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+				(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+				(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+				(pixel_fmt == IPU_PIX_FMT_VYUY)) {
+				_ipu_dc_write_tmpl(8, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5);
+				_ipu_dc_write_tmpl(9, WROD(0), 0, map, SYNC_WAVE, 0, 5);
+				/* configure user events according to DISP NUM */
+				__raw_writel((width - 1), DC_UGDE_3(disp));
+			}
 		   _ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
 		   _ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
 		   _ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
 		} else {
+			if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+				(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+				(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+				(pixel_fmt == IPU_PIX_FMT_VYUY)) {
+				_ipu_dc_write_tmpl(10, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5);
+				_ipu_dc_write_tmpl(11, WROD(0), 0, map, SYNC_WAVE, 0, 5);
+				/* configure user events according to DISP NUM */
+				__raw_writel(width - 1, DC_UGDE_3(disp));
+			}
 		   _ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
 		   _ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
 		   _ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
@@ -1340,6 +1433,19 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
 			/* Set the clock to stop at counter 6. */
 			di_gen |= 0x6000000;
 	}
+	/* changinc DISP_CLK polarity: it can be wrong for some applications */
+	if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+		(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+		(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+		(pixel_fmt == IPU_PIX_FMT_VYUY))
+			di_gen |= 0x00020000;
+	else {
+		/* Configure accordingly to the received configuration */
+		if (sig.clk_pol)
+			di_gen |= 0x00020000;
+		else
+			di_gen &= ~0x00020000;
+	}
 
 	__raw_writel(di_gen, DI_GENERAL(disp));
 
diff --git a/drivers/mxc/ipu3/ipu_ic.c b/drivers/mxc/ipu3/ipu_ic.c
index 564fab0b699a..78c3a9228941 100644
--- a/drivers/mxc/ipu3/ipu_ic.c
+++ b/drivers/mxc/ipu3/ipu_ic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -157,7 +157,6 @@ void _ipu_vdi_init(ipu_channel_t channel, ipu_channel_params_t *params)
 {
 	uint32_t reg;
 	uint32_t pixel_fmt;
-	bool top_field_0;
 
 	reg = ((params->mem_prp_vf_mem.in_height-1) << 16) |
 	  (params->mem_prp_vf_mem.in_width-1);
@@ -186,19 +185,7 @@ void _ipu_vdi_init(ipu_channel_t channel, ipu_channel_params_t *params)
 	}
 	__raw_writel(reg, VDI_C);
 
-	/* MED_MOTION and LOW_MOTION algorithm that are using 3 fields
-	 * should start presenting using the 2nd field.
-	 */
-	if (((params->mem_prp_vf_mem.field_fmt == V4L2_FIELD_INTERLACED_TB) &&
-	     (params->mem_prp_vf_mem.motion_sel != HIGH_MOTION)) ||
-	    ((params->mem_prp_vf_mem.field_fmt == V4L2_FIELD_INTERLACED_BT) &&
-	     (params->mem_prp_vf_mem.motion_sel == HIGH_MOTION)))
-		top_field_0 = false;
-	else
-		top_field_0 = true;
-
-	/* Buffer selection toggle the value therefore init val is inverted. */
-	_ipu_vdi_set_top_field_man(!top_field_0);
+	_ipu_vdi_set_top_field_man(false);
 
 	_ipu_vdi_set_motion(params->mem_prp_vf_mem.motion_sel);
 
@@ -227,13 +214,13 @@ void _ipu_ic_init_prpvf(ipu_channel_params_t *params, bool src_is_csi)
 
 	/* Setup horizontal resizing */
 	/* Upadeted for IC split case */
-	if (!(params->mem_prp_vf_mem.out_resize_ratio)) {
+	if (!(params->mem_prp_vf_mem.outh_resize_ratio)) {
 		_calc_resize_coeffs(params->mem_prp_vf_mem.in_width,
 				params->mem_prp_vf_mem.out_width,
 				&resizeCoeff, &downsizeCoeff);
 		reg |= (downsizeCoeff << 14) | resizeCoeff;
 	} else
-		reg |= params->mem_prp_vf_mem.out_resize_ratio;
+		reg |= params->mem_prp_vf_mem.outh_resize_ratio;
 
 	__raw_writel(reg, IC_PRP_VF_RSC);
 
@@ -349,13 +336,13 @@ void _ipu_ic_init_prpenc(ipu_channel_params_t *params, bool src_is_csi)
 
 	/* Setup horizontal resizing */
 	/* Upadeted for IC split case */
-	if (!(params->mem_prp_enc_mem.out_resize_ratio)) {
+	if (!(params->mem_prp_enc_mem.outh_resize_ratio)) {
 		_calc_resize_coeffs(params->mem_prp_enc_mem.in_width,
 				params->mem_prp_enc_mem.out_width,
 				&resizeCoeff, &downsizeCoeff);
 		reg |= (downsizeCoeff << 14) | resizeCoeff;
 	} else
-		reg |= params->mem_prp_enc_mem.out_resize_ratio;
+		reg |= params->mem_prp_enc_mem.outh_resize_ratio;
 
 	__raw_writel(reg, IC_PRP_ENC_RSC);
 
@@ -387,6 +374,8 @@ void _ipu_ic_init_prpenc(ipu_channel_params_t *params, bool src_is_csi)
 		ic_conf |= IC_CONF_RWS_EN;
 
 	__raw_writel(ic_conf, IC_CONF);
+
+//	ic_dump_register();
 }
 
 void _ipu_ic_uninit_prpenc(void)
@@ -418,20 +407,24 @@ void _ipu_ic_init_pp(ipu_channel_params_t *params)
 	ipu_color_space_t in_fmt, out_fmt;
 
 	/* Setup vertical resizing */
-	_calc_resize_coeffs(params->mem_pp_mem.in_height,
+	if (!(params->mem_pp_mem.outv_resize_ratio)) {
+		_calc_resize_coeffs(params->mem_pp_mem.in_height,
 			    params->mem_pp_mem.out_height,
 			    &resizeCoeff, &downsizeCoeff);
-	reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
+		reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
+	} else {
+		reg = (params->mem_pp_mem.outv_resize_ratio) << 16;
+	}
 
 	/* Setup horizontal resizing */
 	/* Upadeted for IC split case */
-	if (!(params->mem_pp_mem.out_resize_ratio)) {
+	if (!(params->mem_pp_mem.outh_resize_ratio)) {
 		_calc_resize_coeffs(params->mem_pp_mem.in_width,
 							params->mem_pp_mem.out_width,
 							&resizeCoeff, &downsizeCoeff);
 		reg |= (downsizeCoeff << 14) | resizeCoeff;
 	} else {
-		reg |= params->mem_pp_mem.out_resize_ratio;
+		reg |= params->mem_pp_mem.outh_resize_ratio;
 	}
 
 	__raw_writel(reg, IC_PP_RSC);
diff --git a/drivers/mxc/ipu3/ipu_param_mem.h b/drivers/mxc/ipu3/ipu_param_mem.h
index dab3b617db1c..30e6dc1005ba 100644
--- a/drivers/mxc/ipu3/ipu_param_mem.h
+++ b/drivers/mxc/ipu3/ipu_param_mem.h
@@ -155,8 +155,15 @@ static inline void _ipu_ch_param_init(int ch,
 		ipu_ch_param_set_field(&params, 1, 102, 14, stride - 1);
 	}
 
+	/* EBA is 8-byte aligned */
 	ipu_ch_param_set_field(&params, 1, 0, 29, addr0 >> 3);
 	ipu_ch_param_set_field(&params, 1, 29, 29, addr1 >> 3);
+	if (addr0%8)
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's EBA0 is not 8-byte aligned\n", ch);
+	if (addr1%8)
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's EBA1 is not 8-byte aligned\n", ch);
 
 	switch (pixel_fmt) {
 	case IPU_PIX_FMT_GENERIC:
@@ -210,13 +217,14 @@ static inline void _ipu_ch_param_init(int ch,
 	case IPU_PIX_FMT_ABGR32:
 		ipu_ch_param_set_field(&params, 0, 107, 3, 0);	/* bits/pixel */
 		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 15);	/* burst size */
 
 		_ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
 		break;
 	case IPU_PIX_FMT_UYVY:
 		ipu_ch_param_set_field(&params, 0, 107, 3, 3);	/* bits/pixel */
 		ipu_ch_param_set_field(&params, 1, 85, 4, 0xA);	/* pix format */
-		ipu_ch_param_set_field(&params, 1, 78, 7, 15);	/* burst size */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
 		break;
 	case IPU_PIX_FMT_YUYV:
 		ipu_ch_param_set_field(&params, 0, 107, 3, 3);	/* bits/pixel */
@@ -289,13 +297,19 @@ static inline void _ipu_ch_param_init(int ch,
 		v_offset = v;
 	}
 
-	/* UBO and VBO are 22-bit */
+	/* UBO and VBO are 22-bit and 8-byte aligned */
 	if (u_offset/8 > 0x3fffff)
-		dev_err(g_ipu_dev,
-			"The value of U offset exceeds IPU limitation\n");
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's U offset exceeds IPU limitation\n", ch);
 	if (v_offset/8 > 0x3fffff)
-		dev_err(g_ipu_dev,
-			"The value of V offset exceeds IPU limitation\n");
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's V offset exceeds IPU limitation\n", ch);
+	if (u_offset%8)
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's U offset is not 8-byte aligned\n", ch);
+	if (v_offset%8)
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's V offset is not 8-byte aligned\n", ch);
 
 	ipu_ch_param_set_field(&params, 0, 46, 22, u_offset / 8);
 	ipu_ch_param_set_field(&params, 0, 68, 22, v_offset / 8);
@@ -386,6 +400,13 @@ static inline void _ipu_ch_param_set_interlaced_scan(uint32_t ch)
 	u32 stride;
 	ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 113, 1, 1);
 	stride = ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14) + 1;
+	/* ILO is 20-bit and 8-byte aligned */
+	if (stride/8 > 0xfffff)
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's ILO exceeds IPU limitation\n", ch);
+	if (stride%8)
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's ILO is not 8-byte aligned\n", ch);
 	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 58, 20, stride / 8);
 	stride *= 2;
 	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 102, 14, stride - 1);
@@ -442,7 +463,7 @@ static inline void _ipu_ch_offset_update(int ch,
 					(uv_stride * vertical_offset / 2) +
 					horizontal_offset / 2;
 		v_offset = u_offset + (uv_stride * height / 2);
-		u_fix = u ? (u + (uv_stride * vertical_offset) +
+		u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
 					(horizontal_offset / 2) -
 					(stride * vertical_offset) - (horizontal_offset)) :
 					u_offset;
@@ -493,9 +514,9 @@ static inline void _ipu_ch_offset_update(int ch,
 		uv_stride = stride;
 		u_offset = stride * (height - vertical_offset - 1) +
 					(stride - horizontal_offset) +
-					(uv_stride * vertical_offset) +
+					(uv_stride * vertical_offset / 2) +
 					horizontal_offset;
-		u_fix = u ? (u + (uv_stride * vertical_offset) +
+		u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
 					horizontal_offset -
 					(stride * vertical_offset) - (horizontal_offset)) :
 					u_offset;
@@ -514,13 +535,19 @@ static inline void _ipu_ch_offset_update(int ch,
 	if (v_fix > v_offset)
 		v_offset = v_fix;
 
-	/* UBO and VBO are 22-bit */
+	/* UBO and VBO are 22-bit and 8-byte aligned */
 	if (u_offset/8 > 0x3fffff)
-		dev_err(g_ipu_dev,
-			"The value of U offset exceeds IPU limitation\n");
+		dev_warn(g_ipu_dev,
+			"IDMAC%d's U offset exceeds IPU limitation\n", ch);
 	if (v_offset/8 > 0x3fffff)
-		dev_err(g_ipu_dev,
-			"The value of V offset exceeds IPU limitation\n");
+		dev_warn(g_ipu_dev,
+			"IDMAC%d's V offset exceeds IPU limitation\n", ch);
+	if (u_offset%8)
+		dev_warn(g_ipu_dev,
+			"IDMAC%d's U offset is not 8-byte aligned\n", ch);
+	if (v_offset%8)
+		dev_warn(g_ipu_dev,
+			"IDMAC%d's V offset is not 8-byte aligned\n", ch);
 
 	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 0, 46, 22, u_offset / 8);
 	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 0, 68, 22, v_offset / 8);
diff --git a/drivers/mxc/ipu3/ipu_prv.h b/drivers/mxc/ipu3/ipu_prv.h
index 213ded04c87d..4e62b256889f 100644
--- a/drivers/mxc/ipu3/ipu_prv.h
+++ b/drivers/mxc/ipu3/ipu_prv.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -60,7 +60,7 @@ void _ipu_init_dc_mappings(void);
 int _ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
 		 uint32_t out_pixel_fmt);
 void _ipu_dp_uninit(ipu_channel_t channel);
-void _ipu_dc_init(int dc_chan, int di, bool interlaced);
+void _ipu_dc_init(int dc_chan, int di, bool interlaced, uint32_t pixel_fmt);
 void _ipu_dc_uninit(int dc_chan);
 void _ipu_dp_dc_enable(ipu_channel_t channel);
 void _ipu_dp_dc_disable(ipu_channel_t channel, bool swap);
diff --git a/drivers/mxc/ipu3/ipu_regs.h b/drivers/mxc/ipu3/ipu_regs.h
index 2438df60a0ce..19fde8846aa7 100644
--- a/drivers/mxc/ipu3/ipu_regs.h
+++ b/drivers/mxc/ipu3/ipu_regs.h
@@ -261,6 +261,14 @@ extern u32 *ipu_vdi_reg;
 #define DC_EVT_NEW_CHAN_R_1	9
 #define DC_EVT_NEW_DATA_R_0	10
 #define DC_EVT_NEW_DATA_R_1	11
+#define DC_EVEN_UGDE0 		12
+#define DC_ODD_UGDE0 		13
+#define DC_EVEN_UGDE1 		14
+#define DC_ODD_UGDE1 		15
+#define DC_EVEN_UGDE2 		16
+#define DC_ODD_UGDE2 		17
+#define DC_EVEN_UGDE3 		18
+#define DC_ODD_UGDE3 		19
 
 #define dc_ch_offset(ch) \
 ({ \
@@ -627,6 +635,8 @@ enum {
 	VDI_C_VWM3_CLR_2 = 0x02000000,
 	VDI_C_TOP_FIELD_MAN_1 = 0x40000000,
 	VDI_C_TOP_FIELD_AUTO_1 = 0x80000000,
+
+	DMFC_FIFO_SIZE_5F = 0x00003800,
 };
 
 enum di_pins {
diff --git a/drivers/mxc/mlb/Kconfig b/drivers/mxc/mlb/Kconfig
index 294c9776fb4d..7e3b16c2ddae 100644
--- a/drivers/mxc/mlb/Kconfig
+++ b/drivers/mxc/mlb/Kconfig
@@ -6,7 +6,7 @@ menu "MXC Media Local Bus Driver"
 
 config MXC_MLB
 	tristate "MLB support"
-	depends on ARCH_MX35
+	depends on ARCH_MX35 || ARCH_MX53
 	---help---
          Say Y to get the MLB support.
 
diff --git a/drivers/mxc/pmic/core/mc13892.c b/drivers/mxc/pmic/core/mc13892.c
index 9f232a4f5718..1175ab633fc6 100644
--- a/drivers/mxc/pmic/core/mc13892.c
+++ b/drivers/mxc/pmic/core/mc13892.c
@@ -262,6 +262,7 @@ int pmic_event_unmask(type_event event)
 
 	return ret;
 }
+EXPORT_SYMBOL(pmic_event_unmask);
 
 int pmic_event_mask(type_event event)
 {
@@ -294,7 +295,7 @@ int pmic_event_mask(type_event event)
 
 	return ret;
 }
-
+EXPORT_SYMBOL(pmic_event_mask);
 /*!
  * This function returns the PMIC version in system.
  *
diff --git a/drivers/mxc/pmic/core/pmic.h b/drivers/mxc/pmic/core/pmic.h
index 964c44a06bc1..da61b19a3f31 100644
--- a/drivers/mxc/pmic/core/pmic.h
+++ b/drivers/mxc/pmic/core/pmic.h
@@ -58,8 +58,6 @@ static inline int spi_rw(struct spi_device *spi, u8 * buf, size_t len)
 		.cs_change = 0,
 		.delay_usecs = 0,
 	};
-	mxc_spi_poll_transfer(spi, &t);
-	return 0;
 #if 0
 	struct spi_message m;
 
@@ -68,6 +66,9 @@ static inline int spi_rw(struct spi_device *spi, u8 * buf, size_t len)
 	if (spi_sync(spi, &m) != 0 || m.status != 0)
 		return PMIC_ERROR;
 	return (len - m.actual_length);
+#else
+	mxc_spi_poll_transfer(spi, &t);
+	return 0;
 #endif
 }
 
diff --git a/drivers/mxc/pmic/mc13892/pmic_adc.c b/drivers/mxc/pmic/mc13892/pmic_adc.c
index 68588a40d7e4..60ce35e86a06 100644
--- a/drivers/mxc/pmic/mc13892/pmic_adc.c
+++ b/drivers/mxc/pmic/mc13892/pmic_adc.c
@@ -17,6 +17,7 @@
 #include <linux/delay.h>
 #include <linux/wait.h>
 #include <linux/device.h>
+#include <linux/cdev.h>
 
 #include <linux/pmic_adc.h>
 #include <linux/pmic_status.h>
@@ -33,6 +34,9 @@
 #define MC13892_ADC0_TS_M_LSH	14
 #define MC13892_ADC0_TS_M_WID	3
 
+static int pmic_adc_major;
+static struct class *pmic_adc_class;
+
 /*
  * Maximun allowed variation in the three X/Y co-ordinates acquired from
  * touch-screen
@@ -924,17 +928,322 @@ static ssize_t adc_ctl(struct device *dev, struct device_attribute *attr,
 
 #endif
 
+/*!
+ * This function triggers a conversion and returns sampling results of each
+ * specified channel.
+ *
+ * @param        channels  This input parameter is bitmap to specify channels
+ *                         to be sampled.
+ * @param        result    The pointer to array to store sampling results.
+ *                         The memory should be allocated by the caller of this
+ *                         function.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_adc_convert_multichnnel(t_channel channels,
+					 unsigned short *result)
+{
+	t_adc_param adc_param;
+	int i;
+	PMIC_STATUS ret;
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	mc13892_adc_init_param(&adc_param);
+	pr_debug("pmic_adc_convert_multichnnel\n");
+
+	channels = channel_num[channels];
+
+	if (channels == -1) {
+		pr_debug("Wrong channel ID\n");
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	adc_param.read_ts = false;
+	adc_param.single_channel = false;
+	if ((channels >= 0) && (channels <= 7)) {
+		adc_param.channel_0 = channels;
+		adc_param.channel_1 = ((channels + 4) % 4) + 4;
+	} else {
+		return PMIC_PARAMETER_ERROR;
+	}
+	adc_param.read_mode = 0x00003f;
+	adc_param.read_ts = false;
+	ret = mc13892_adc_convert(&adc_param);
+
+	for (i = 0; i <= 7; i++) {
+		result[i] = adc_param.value[i];
+	}
+	return ret;
+}
+
+/*!
+ * This function starts a Battery Current mode conversion.
+ *
+ * @param        mode      Conversion mode.
+ * @param        result    Battery Current measurement result.
+ *                         if \a mode = ADC_8CHAN_1X, the result is \n
+ *                             result[0] = (BATTP - BATT_I) \n
+ *                         if \a mode = ADC_1CHAN_8X, the result is \n
+ *                             result[0] = BATTP \n
+ *                             result[1] = BATT_I \n
+ *                             result[2] = BATTP \n
+ *                             result[3] = BATT_I \n
+ *                             result[4] = BATTP \n
+ *                             result[5] = BATT_I \n
+ *                             result[6] = BATTP \n
+ *                             result[7] = BATT_I
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_adc_get_battery_current(t_conversion_mode mode,
+					 unsigned short *result)
+{
+	PMIC_STATUS ret;
+	t_channel channel;
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	channel = BATTERY_CURRENT;
+	if (mode == ADC_8CHAN_1X) {
+		ret = pmic_adc_convert(channel, result);
+	} else {
+		ret = pmic_adc_convert_8x(channel, result);
+	}
+	return ret;
+}
+
+/*!
+ * This function implements the open method on a MC13892 ADC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @return       This function returns 0.
+ */
+static int pmic_adc_open(struct inode *inode, struct file *file)
+{
+	while (suspend_flag == 1) {
+		swait++;
+		/* Block if the device is suspended */
+		if (wait_event_interruptible(suspendq, (suspend_flag == 0))) {
+			return -ERESTARTSYS;
+		}
+	}
+	pr_debug("mc13892_adc : mc13892_adc_open()\n");
+	return 0;
+}
+
+/*!
+ * This function implements the release method on a MC13892 ADC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @return       This function returns 0.
+ */
+static int pmic_adc_free(struct inode *inode, struct file *file)
+{
+	pr_debug("mc13892_adc : mc13892_adc_free()\n");
+	return 0;
+}
+
+/*!
+ * This function implements IOCTL controls on a MC13892 ADC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @param        cmd         the command
+ * @param        arg         the parameter
+ * @return       This function returns 0 if successful.
+ */
+static int pmic_adc_ioctl(struct inode *inode, struct file *file,
+			  unsigned int cmd, unsigned long arg)
+{
+	t_adc_convert_param *convert_param;
+	t_touch_mode touch_mode;
+	t_touch_screen touch_sample;
+	unsigned short b_current;
+
+	if ((_IOC_TYPE(cmd) != 'p') && (_IOC_TYPE(cmd) != 'D'))
+		return -ENOTTY;
+
+	while (suspend_flag == 1) {
+		swait++;
+		/* Block if the device is suspended */
+		if (wait_event_interruptible(suspendq, (suspend_flag == 0))) {
+			return -ERESTARTSYS;
+		}
+	}
+
+	switch (cmd) {
+	case PMIC_ADC_INIT:
+		CHECK_ERROR(pmic_adc_init());
+		break;
+
+	case PMIC_ADC_DEINIT:
+		CHECK_ERROR(pmic_adc_deinit());
+		break;
+
+	case PMIC_ADC_CONVERT:
+		if ((convert_param = kmalloc(sizeof(t_adc_convert_param),
+					     GFP_KERNEL)) == NULL) {
+			return -ENOMEM;
+		}
+		if (copy_from_user(convert_param, (t_adc_convert_param *) arg,
+				   sizeof(t_adc_convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+		CHECK_ERROR_KFREE(pmic_adc_convert(convert_param->channel,
+						   convert_param->result),
+				  (kfree(convert_param)));
+
+		if (copy_to_user((t_adc_convert_param *) arg, convert_param,
+				 sizeof(t_adc_convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+		kfree(convert_param);
+		break;
+
+	case PMIC_ADC_CONVERT_8X:
+		if ((convert_param = kmalloc(sizeof(t_adc_convert_param),
+					     GFP_KERNEL)) == NULL) {
+			return -ENOMEM;
+		}
+		if (copy_from_user(convert_param, (t_adc_convert_param *) arg,
+				   sizeof(t_adc_convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+		CHECK_ERROR_KFREE(pmic_adc_convert_8x(convert_param->channel,
+						      convert_param->result),
+				  (kfree(convert_param)));
+
+		if (copy_to_user((t_adc_convert_param *) arg, convert_param,
+				 sizeof(t_adc_convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+		kfree(convert_param);
+		break;
+
+	case PMIC_ADC_CONVERT_MULTICHANNEL:
+		if ((convert_param = kmalloc(sizeof(t_adc_convert_param),
+					     GFP_KERNEL)) == NULL) {
+			return -ENOMEM;
+		}
+		if (copy_from_user(convert_param, (t_adc_convert_param *) arg,
+				   sizeof(t_adc_convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+
+		CHECK_ERROR_KFREE(pmic_adc_convert_multichnnel
+				  (convert_param->channel,
+				   convert_param->result),
+				  (kfree(convert_param)));
+
+		if (copy_to_user((t_adc_convert_param *) arg, convert_param,
+				 sizeof(t_adc_convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+		kfree(convert_param);
+		break;
+
+	case PMIC_ADC_SET_TOUCH_MODE:
+		CHECK_ERROR(pmic_adc_set_touch_mode((t_touch_mode) arg));
+		break;
+
+	case PMIC_ADC_GET_TOUCH_MODE:
+		CHECK_ERROR(pmic_adc_get_touch_mode(&touch_mode));
+		if (copy_to_user((t_touch_mode *) arg, &touch_mode,
+				 sizeof(t_touch_mode))) {
+			return -EFAULT;
+		}
+		break;
+
+	case PMIC_ADC_GET_TOUCH_SAMPLE:
+		CHECK_ERROR(pmic_adc_get_touch_sample(&touch_sample, 1));
+		if (copy_to_user((t_touch_screen *) arg, &touch_sample,
+				 sizeof(t_touch_screen))) {
+			return -EFAULT;
+		}
+		break;
+
+	case PMIC_ADC_GET_BATTERY_CURRENT:
+		CHECK_ERROR(pmic_adc_get_battery_current(ADC_8CHAN_1X,
+							 &b_current));
+		if (copy_to_user((unsigned short *)arg, &b_current,
+				 sizeof(unsigned short))) {
+
+			return -EFAULT;
+		}
+		break;
+
+	default:
+		pr_debug("pmic_adc_ioctl: unsupported ioctl command 0x%x\n",
+			 cmd);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static struct file_operations mc13892_adc_fops = {
+	.owner = THIS_MODULE,
+	.ioctl = pmic_adc_ioctl,
+	.open = pmic_adc_open,
+	.release = pmic_adc_free,
+};
+
+static struct cdev pmic_adc_cdev;
 static DEVICE_ATTR(adc, 0644, adc_info, adc_ctl);
 
 static int pmic_adc_module_probe(struct platform_device *pdev)
 {
 	int ret = 0;
+	struct device * sdev;
+	dev_t devid;
 
 	pr_debug("PMIC ADC start probe\n");
+
+	if( (ret = alloc_chrdev_region(&devid, 0, 8, "pmic_adc")) < 0 ) {
+		pr_debug(KERN_ERR "Unable to allocate device range for pmic_adc\n");
+		return ret;
+	}
+	pmic_adc_major = MAJOR(devid);
+	if (pmic_adc_major < 0) {
+		pr_debug(KERN_ERR "Unable to get a major for pmic_adc\n");
+		ret = pmic_adc_major;
+		goto unreg_char;
+	}
+
+	cdev_init(&pmic_adc_cdev, &mc13892_adc_fops);
+	ret  =cdev_add(&pmic_adc_cdev, devid, 8);
+	if (ret < 0) {
+		pr_err("pmic_adc: cannot add character device\n");
+		goto unreg_char;
+	}
+
+	pmic_adc_class = class_create(THIS_MODULE, "pmic_adc");
+	if (IS_ERR(pmic_adc_class)) {
+		pr_debug(KERN_ERR "Error creating pmic_adc class.\n");
+		ret = PTR_ERR(pmic_adc_class);
+		goto unreg_char;
+	}
+
+	sdev = device_create(pmic_adc_class, NULL, devid, NULL, "pmic_adc");
+	if (IS_ERR(sdev) ) {
+		pr_debug(KERN_ERR "Error creating pmic_adc class device.\n");
+		ret = PTR_ERR(sdev);
+		goto cl_destroy;
+	}
+
 	ret = device_create_file(&(pdev->dev), &dev_attr_adc);
 	if (ret) {
 		pr_debug("Can't create device file!\n");
-		return -ENODEV;
+		ret = -ENODEV;
+		goto dev_destroy;
 	}
 
 	init_waitqueue_head(&suspendq);
@@ -946,11 +1255,17 @@ static int pmic_adc_module_probe(struct platform_device *pdev)
 	}
 
 	pmic_adc_ready = 1;
-	pr_debug("PMIC ADC successfully probed\n");
+	printk(KERN_DEBUG"PMIC ADC successfully probed\n");
 	return 0;
 
-      rm_dev_file:
+rm_dev_file:
 	device_remove_file(&(pdev->dev), &dev_attr_adc);
+dev_destroy:
+	device_destroy(pmic_adc_class, MKDEV(pmic_adc_major, 0));
+cl_destroy:
+	class_destroy(pmic_adc_class);
+unreg_char:
+	unregister_chrdev(pmic_adc_major, "pmic_adc");
 	return ret;
 }
 
diff --git a/drivers/mxc/pmic/mc13892/pmic_battery.c b/drivers/mxc/pmic/mc13892/pmic_battery.c
index 8535eb0a34e4..c355e0c4338f 100644
--- a/drivers/mxc/pmic/mc13892/pmic_battery.c
+++ b/drivers/mxc/pmic/mc13892/pmic_battery.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -104,6 +104,19 @@ enum chg_setting {
        VI_PROGRAM_EN
 };
 
+
+static unsigned int max_voltage_design = 3800000;
+module_param(max_voltage_design, uint, S_IRUGO|S_IWUSR);
+MODULE_PARM_DESC(max_voltage_design, "Maximum battery voltage by design.");
+
+static unsigned int min_voltage_design = 3300000;
+module_param(min_voltage_design, uint, S_IRUGO|S_IWUSR);
+MODULE_PARM_DESC(min_voltage_design, "Minimum battery voltage by design.");
+
+static unsigned int main_charger_current  = 0x8; /* 720 mA */
+module_param(main_charger_current, uint, S_IRUGO|S_IWUSR);
+MODULE_PARM_DESC(main_charger_current, "Main charge path regulator current limit.");
+
 static int pmic_set_chg_current(unsigned short curr)
 {
 	unsigned int mask;
@@ -180,15 +193,35 @@ static int pmic_set_chg_misc(enum chg_setting type, unsigned short flag)
 	return 0;
 }
 
+static void pmic_stop_charging(void)
+{
+	pmic_set_chg_misc(AUTO_CHG_DIS, 0);
+	pmic_set_chg_current(0);
+}
+
+static int pmic_restart_charging(void)
+{
+	pmic_set_chg_misc(BAT_TH_CHECK_DIS, 1);
+	pmic_set_chg_misc(AUTO_CHG_DIS, 0);
+	pmic_set_chg_misc(VI_PROGRAM_EN, 1);
+	pmic_set_chg_current(main_charger_current);
+	pmic_set_chg_misc(RESTART_CHG_STAT, 1);
+	return 0;
+}
+
 static int pmic_get_batt_voltage(unsigned short *voltage)
 {
 	t_channel channel;
 	unsigned short result[8];
 
+	pmic_stop_charging();
+
 	channel = BATTERY_VOLTAGE;
 	CHECK_ERROR(pmic_adc_convert(channel, result));
 	*voltage = result[0];
 
+	pmic_restart_charging();
+
 	return 0;
 }
 
@@ -197,10 +230,14 @@ static int pmic_get_batt_current(unsigned short *curr)
 	t_channel channel;
 	unsigned short result[8];
 
+	pmic_stop_charging();
+
 	channel = BATTERY_CURRENT;
 	CHECK_ERROR(pmic_adc_convert(channel, result));
 	*curr = result[0];
 
+	pmic_restart_charging();
+
 	return 0;
 }
 
@@ -284,16 +321,6 @@ static int pmic_get_charger_coulomb(int *coulomb)
 	return 0;
 }
 
-static int pmic_restart_charging(void)
-{
-	pmic_set_chg_misc(BAT_TH_CHECK_DIS, 1);
-	pmic_set_chg_misc(AUTO_CHG_DIS, 0);
-	pmic_set_chg_misc(VI_PROGRAM_EN, 1);
-	pmic_set_chg_current(0x8);
-	pmic_set_chg_misc(RESTART_CHG_STAT, 1);
-	return 0;
-}
-
 struct mc13892_dev_info {
 	struct device *dev;
 
@@ -353,8 +380,8 @@ static int mc13892_charger_update_status(struct mc13892_dev_info *di)
 				pmic_restart_charging();
 			} else
 				pmic_stop_coulomb_counter();
+			}
 		}
-	}
 
 	return ret;
 }
@@ -422,7 +449,7 @@ static void mc13892_battery_update_status(struct mc13892_dev_info *di)
 			else
 				di->battery_status =
 					POWER_SUPPLY_STATUS_NOT_CHARGING;
-		}
+			}
 
 		if (di->battery_status == POWER_SUPPLY_STATUS_NOT_CHARGING)
 			di->full_counter++;
@@ -491,10 +518,10 @@ static int mc13892_battery_get_property(struct power_supply *psy,
 		val->intval = di->accum_current_uAh;
 		break;
 	case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
-		val->intval = 3800000;
+		val->intval = max_voltage_design;
 		break;
 	case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
-		val->intval = 3300000;
+		val->intval = min_voltage_design;
 		break;
 	default:
 		return -EINVAL;
@@ -536,7 +563,7 @@ static int pmic_battery_probe(struct platform_device *pdev)
 		pr_debug("Battery driver is only applied for MC13892 V2.0\n");
 		return -1;
 	}
-	if (machine_is_mx51_babbage()) {
+	if (machine_is_mx51_babbage() || machine_is_mx50_arm2()) {
 		pr_debug("mc13892 charger is not used for this platform\n");
 		return -1;
 	}
diff --git a/drivers/mxc/security/Kconfig b/drivers/mxc/security/Kconfig
index 875848b2c69c..3e36a29ace64 100644
--- a/drivers/mxc/security/Kconfig
+++ b/drivers/mxc/security/Kconfig
@@ -27,6 +27,7 @@ config MXC_SECURITY_RNG
 	depends on ARCH_MXC
 	depends on !ARCH_MXC91321
 	depends on !ARCH_MX27
+	depends on !ARCH_MX51
 	default n
 	select MXC_SECURITY_CORE
 	---help---
diff --git a/drivers/mxc/security/sahara2/fsl_shw_auth.c b/drivers/mxc/security/sahara2/fsl_shw_auth.c
index d3100f01380a..b3f8788b553a 100644
--- a/drivers/mxc/security/sahara2/fsl_shw_auth.c
+++ b/drivers/mxc/security/sahara2/fsl_shw_auth.c
@@ -326,7 +326,7 @@ static inline fsl_shw_return_t add_assoc_preamble(sah_Head_Desc ** desc_chain,
 	return status;
 }				/* add_assoc_preamble() */
 
-#if SUPPORT_SSL
+#ifdef SUPPORT_SSL
 /*!
  * Generate an SSL value
  *
@@ -473,7 +473,7 @@ fsl_shw_return_t fsl_shw_gen_encrypt(fsl_shw_uco_t * user_ctx,
 	SAH_SF_USER_CHECK();
 
 	if (auth_ctx->mode == FSL_ACC_MODE_SSL) {
-#if SUPPORT_SSL
+#ifdef SUPPORT_SSL
 		ret = do_ssl_gen(user_ctx, auth_ctx, cipher_key_info,
 				 auth_key_info, auth_data_length, auth_data,
 				 payload_length, payload, ct, auth_value);
diff --git a/drivers/mxc/security/scc2_driver.c b/drivers/mxc/security/scc2_driver.c
index 3249405c86a1..5c0d8b4dc26d 100644
--- a/drivers/mxc/security/scc2_driver.c
+++ b/drivers/mxc/security/scc2_driver.c
@@ -415,6 +415,7 @@ extern scc_partition_status_t scc_partition_status(void *part_base)
 		break;
 	}
 }
+EXPORT_SYMBOL(scc_partition_status);
 
 /**
  * Calculate the physical address from the kernel virtual address.
@@ -427,6 +428,7 @@ uint32_t scc_virt_to_phys(void *address)
 	return (uint32_t) address - (uint32_t) scm_ram_base
 	    + (uint32_t) scm_ram_phys_base;
 }
+EXPORT_SYMBOL(scc_virt_to_phys);
 
 /**
  * Engage partition of secure memory
diff --git a/drivers/mxc/vpu/mxc_vpu.c b/drivers/mxc/vpu/mxc_vpu.c
index b9ae23928c5d..f62e3d46a67c 100644
--- a/drivers/mxc/vpu/mxc_vpu.c
+++ b/drivers/mxc/vpu/mxc_vpu.c
@@ -690,20 +690,22 @@ static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
 	for (i = 0; i < vpu_clk_usercount; i++)
 		clk_disable(vpu_clk);
 
-	clk_enable(vpu_clk);
-	if (bitwork_mem.cpu_addr != 0) {
-		SAVE_WORK_REGS;
-		SAVE_CTRL_REGS;
-		SAVE_RDWR_PTR_REGS;
-		SAVE_DIS_FLAG_REGS;
-
-		WRITE_REG(0x1, BIT_BUSY_FLAG);
-		WRITE_REG(VPU_SLEEP_REG_VALUE, BIT_RUN_COMMAND);
-		while (READ_REG(BIT_BUSY_FLAG)) ;
+	if (!cpu_is_mx53()) {
+		clk_enable(vpu_clk);
+		if (bitwork_mem.cpu_addr != 0) {
+			SAVE_WORK_REGS;
+			SAVE_CTRL_REGS;
+			SAVE_RDWR_PTR_REGS;
+			SAVE_DIS_FLAG_REGS;
+
+			WRITE_REG(0x1, BIT_BUSY_FLAG);
+			WRITE_REG(VPU_SLEEP_REG_VALUE, BIT_RUN_COMMAND);
+			while (READ_REG(BIT_BUSY_FLAG))
+				;
+		}
+		clk_disable(vpu_clk);
 	}
 
-	clk_disable(vpu_clk);
-
 	if (cpu_is_mx37() || cpu_is_mx51())
 		mxc_pg_enable(pdev);
 
@@ -722,8 +724,10 @@ static int vpu_resume(struct platform_device *pdev)
 	if (cpu_is_mx37() || cpu_is_mx51())
 		mxc_pg_disable(pdev);
 
-	clk_enable(vpu_clk);
+	if (cpu_is_mx53())
+		goto recover_clk;
 
+	clk_enable(vpu_clk);
 	if (bitwork_mem.cpu_addr != 0) {
 		u32 *p = (u32 *) bitwork_mem.cpu_addr;
 		u32 data;
@@ -786,9 +790,9 @@ static int vpu_resume(struct platform_device *pdev)
 		WRITE_REG(VPU_WAKE_REG_VALUE, BIT_RUN_COMMAND);
 		while (READ_REG(BIT_BUSY_FLAG)) ;
 	}
-
 	clk_disable(vpu_clk);
 
+recover_clk:
 	/* Recover vpu clock */
 	for (i = 0; i < vpu_clk_usercount; i++)
 		clk_enable(vpu_clk);
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index bd5d0e026b02..28318f4236b1 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1885,6 +1885,13 @@ config FEC_1588
 	bool "Enable FEC 1588 timestamping"
 	depends on FEC
 
+config FEC_L2SWITCH
+	bool "L2 Switch Ethernet Controller (of ColdFire CPUs)"
+	depends on ARCH_MX28 && !FEC
+	help
+	  Say Y here if you want to use the built-in 10/100 Ethernet Switch
+	  Controller on some Motorola ColdFire processors.
+
 config FEC2
 	bool "Second FEC ethernet controller (on some ColdFire CPUs)"
 	depends on FEC
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index f3c89fb1b799..11bb1b5623bf 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -115,6 +115,7 @@ obj-$(CONFIG_HP100) += hp100.o
 obj-$(CONFIG_SMC9194) += smc9194.o
 obj-$(CONFIG_FEC) += fec.o
 obj-$(CONFIG_FEC_1588) += fec_1588.o
+obj-$(CONFIG_FEC_L2SWITCH) += fec_switch.o
 obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx.o
 ifeq ($(CONFIG_FEC_MPC52xx_MDIO),y)
 	obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx_phy.o
diff --git a/drivers/net/acenic.c b/drivers/net/acenic.c
index 08419ee10290..12bfc447a896 100644
--- a/drivers/net/acenic.c
+++ b/drivers/net/acenic.c
@@ -1209,7 +1209,8 @@ static int __devinit ace_init(struct net_device *dev)
 	memset(ap->info, 0, sizeof(struct ace_info));
 	memset(ap->skb, 0, sizeof(struct ace_skb));
 
-	if (ace_load_firmware(dev))
+	ecode = ace_load_firmware(dev);
+	if (ecode)
 		goto init_error;
 
 	ap->fw_running = 0;
diff --git a/drivers/net/appletalk/ipddp.c b/drivers/net/appletalk/ipddp.c
index 78cea5e80b1d..bf9ab65d27a4 100644
--- a/drivers/net/appletalk/ipddp.c
+++ b/drivers/net/appletalk/ipddp.c
@@ -176,8 +176,7 @@ static int ipddp_xmit(struct sk_buff *skb, struct net_device *dev)
 	dev->stats.tx_packets++;
 	dev->stats.tx_bytes += skb->len;
 
-        if(aarp_send_ddp(rt->dev, skb, &rt->at, NULL) < 0)
-                dev_kfree_skb(skb);
+	aarp_send_ddp(rt->dev, skb, &rt->at, NULL);
 
 	spin_unlock(&ipddp_route_lock);
 
diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c
index d3c734f4d679..2f6ae784a36f 100644
--- a/drivers/net/au1000_eth.c
+++ b/drivers/net/au1000_eth.c
@@ -1089,7 +1089,14 @@ static struct net_device * au1000_probe(int port_num)
 		return NULL;
 	}
 
-	if ((err = register_netdev(dev)) != 0) {
+	dev->base_addr = base;
+	dev->irq = irq;
+	dev->netdev_ops = &au1000_netdev_ops;
+	SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
+	dev->watchdog_timeo = ETH_TX_TIMEOUT;
+
+	err = register_netdev(dev);
+	if (err != 0) {
 		printk(KERN_ERR "%s: Cannot register net device, error %d\n",
 				DRV_NAME, err);
 		free_netdev(dev);
@@ -1207,12 +1214,6 @@ static struct net_device * au1000_probe(int port_num)
 		aup->tx_db_inuse[i] = pDB;
 	}
 
-	dev->base_addr = base;
-	dev->irq = irq;
-	dev->netdev_ops = &au1000_netdev_ops;
-	SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
-	dev->watchdog_timeo = ETH_TX_TIMEOUT;
-
 	/*
 	 * The boot code uses the ethernet controller, so reset it to start
 	 * fresh.  au1000_init() expects that the device is in reset state.
diff --git a/drivers/net/b44.c b/drivers/net/b44.c
index bafca672ea7d..351a258dccd6 100644
--- a/drivers/net/b44.c
+++ b/drivers/net/b44.c
@@ -913,9 +913,6 @@ static irqreturn_t b44_interrupt(int irq, void *dev_id)
 			bp->istat = istat;
 			__b44_disable_ints(bp);
 			__napi_schedule(&bp->napi);
-		} else {
-			printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
-			       dev->name);
 		}
 
 irq_ack:
@@ -1505,8 +1502,7 @@ static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
 		for (k = 0; k< ethaddr_bytes; k++) {
 			ppattern[offset + magicsync +
 				(j * ETH_ALEN) + k] = macaddr[k];
-			len++;
-			set_bit(len, (unsigned long *) pmask);
+			set_bit(len++, (unsigned long *) pmask);
 		}
 	}
 	return len - 1;
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index aa1be1feceed..bcd8df92dec7 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -691,7 +691,7 @@ static int bond_check_dev_link(struct bonding *bond,
 			       struct net_device *slave_dev, int reporting)
 {
 	const struct net_device_ops *slave_ops = slave_dev->netdev_ops;
-	static int (*ioctl)(struct net_device *, struct ifreq *, int);
+	int (*ioctl)(struct net_device *, struct ifreq *, int);
 	struct ifreq ifr;
 	struct mii_ioctl_data *mii;
 
@@ -3707,10 +3707,10 @@ static int bond_xmit_hash_policy_l23(struct sk_buff *skb,
 
 	if (skb->protocol == htons(ETH_P_IP)) {
 		return ((ntohl(iph->saddr ^ iph->daddr) & 0xffff) ^
-			(data->h_dest[5] ^ bond_dev->dev_addr[5])) % count;
+			(data->h_dest[5] ^ data->h_source[5])) % count;
 	}
 
-	return (data->h_dest[5] ^ bond_dev->dev_addr[5]) % count;
+	return (data->h_dest[5] ^ data->h_source[5]) % count;
 }
 
 /*
@@ -3737,7 +3737,7 @@ static int bond_xmit_hash_policy_l34(struct sk_buff *skb,
 
 	}
 
-	return (data->h_dest[5] ^ bond_dev->dev_addr[5]) % count;
+	return (data->h_dest[5] ^ data->h_source[5]) % count;
 }
 
 /*
@@ -3748,7 +3748,7 @@ static int bond_xmit_hash_policy_l2(struct sk_buff *skb,
 {
 	struct ethhdr *data = (struct ethhdr *)skb->data;
 
-	return (data->h_dest[5] ^ bond_dev->dev_addr[5]) % count;
+	return (data->h_dest[5] ^ data->h_source[5]) % count;
 }
 
 /*-------------------------- Device entry points ----------------------------*/
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index a6bf9a7fddd9..481990fd3f2b 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -86,8 +86,8 @@ config CAN_DEBUG_DEVICES
 
 config CAN_FLEXCAN
         tristate "Freescale FlexCAN"
-        depends on CAN && (ARCH_MX25 || ARCH_MX35 || ARCH_MX28)
-        default m
+        depends on CAN && (ARCH_MX25 || ARCH_MX35 || ARCH_MX28 || ARCH_MX53)
+        default y
         ---help---
           This select the support of Freescale CAN(FlexCAN).
           This driver can also be built as a module.
diff --git a/drivers/net/can/flexcan/dev.c b/drivers/net/can/flexcan/dev.c
index 389f85d75709..404877c33eab 100644
--- a/drivers/net/can/flexcan/dev.c
+++ b/drivers/net/can/flexcan/dev.c
@@ -35,6 +35,74 @@
 #endif
 #include "flexcan.h"
 
+#define DEFAULT_BITRATE	    500000
+#define TIME_SEGMENT_MIN    8
+#define TIME_SEGMENT_MAX    25
+#define TIME_SEGMENT_MID    ((TIME_SEGMENT_MIN + TIME_SEGMENT_MAX)/2)
+
+struct time_segment {
+	char propseg;
+	char pseg1;
+	char pseg2;
+};
+
+struct time_segment time_segments[] = {
+    { /* total 8 timequanta */
+	1, 2, 1
+    },
+    { /* total 9 timequanta */
+	1, 2, 2
+    },
+    { /* total 10 timequanta */
+	2, 2, 2
+    },
+    { /* total 11 timequanta */
+	2, 2, 3
+    },
+    { /* total 12 timequanta */
+	2, 3, 3
+    },
+    { /* total 13 timequanta */
+	3, 3, 3
+    },
+    { /* total 14 timequanta */
+	3, 3, 4
+    },
+    { /* total 15 timequanta */
+	3, 4, 4
+    },
+    { /* total 16 timequanta */
+	4, 4, 4
+    },
+    { /* total 17 timequanta */
+	4, 4, 5
+    },
+    { /* total 18 timequanta */
+	4, 5, 5
+    },
+    { /* total 19 timequanta */
+	5, 5, 5
+    },
+    { /* total 20 timequanta */
+	5, 5, 6
+    },
+    { /* total 21 timequanta */
+	5, 6, 6
+    },
+    { /* total 22 timequanta */
+	6, 6, 6
+    },
+    { /* total 23 timequanta */
+	6, 6, 7
+    },
+    { /* total 24 timequanta */
+	6, 7, 7
+    },
+    { /* total 25 timequanta */
+	7, 7, 7
+    },
+};
+
 enum {
 	FLEXCAN_ATTR_STATE = 0,
 	FLEXCAN_ATTR_BITRATE,
@@ -138,6 +206,45 @@ static void flexcan_set_bitrate(struct flexcan_device *flexcan, int bitrate)
 	 * based on the bitrate to get the timing of
 	 * presdiv, pseg1, pseg2, propseg
 	 */
+	int i, rate, div;
+	bool found = false;
+	struct time_segment *segment;
+	rate = clk_get_rate(flexcan->clk);
+
+	if (!bitrate)
+		bitrate = DEFAULT_BITRATE;
+
+	if (rate % bitrate == 0) {
+		div = rate / bitrate;
+		for (i = TIME_SEGMENT_MID; i <= TIME_SEGMENT_MAX; i++) {
+			if (div % i == 0) {
+				found = true;
+				break;
+			}
+		}
+		if (!found) {
+			for (i = TIME_SEGMENT_MID - 1;
+					    i >= TIME_SEGMENT_MIN; i--) {
+				if (div % i == 0) {
+					found = true;
+					break;
+				}
+			}
+
+		}
+	}
+
+	if (found) {
+		segment = &time_segments[i - TIME_SEGMENT_MIN];
+		flexcan->br_presdiv = div/i - 1;
+		flexcan->br_propseg = segment->propseg;
+		flexcan->br_pseg1 = segment->pseg1;
+		flexcan->br_pseg2 = segment->pseg2;
+		flexcan->bitrate = bitrate;
+	} else {
+		pr_info("The bitrate %d can't supported with clock \
+				    rate of %d \n", bitrate, rate);
+	}
 }
 
 static void flexcan_update_bitrate(struct flexcan_device *flexcan)
@@ -201,7 +308,7 @@ static int flexcan_dump_xmit_mb(struct flexcan_device *flexcan, char *buf)
 		ret +=
 		    sprintf(buf + ret,
 			    "mb[%d]::CS:0x%x ID:0x%x DATA[1~2]:0x%02x,0x%02x\n",
-			    i, flexcan->hwmb[i].mb_cs.data,
+			    i, flexcan->hwmb[i].mb_cs,
 			    flexcan->hwmb[i].mb_id, flexcan->hwmb[i].mb_data[1],
 			    flexcan->hwmb[i].mb_data[2]);
 	return ret;
@@ -214,7 +321,7 @@ static int flexcan_dump_rx_mb(struct flexcan_device *flexcan, char *buf)
 		ret +=
 		    sprintf(buf + ret,
 			    "mb[%d]::CS:0x%x ID:0x%x DATA[1~2]:0x%02x,0x%02x\n",
-			    i, flexcan->hwmb[i].mb_cs.data,
+			    i, flexcan->hwmb[i].mb_cs,
 			    flexcan->hwmb[i].mb_id, flexcan->hwmb[i].mb_data[1],
 			    flexcan->hwmb[i].mb_data[2]);
 	return ret;
@@ -575,6 +682,7 @@ struct net_device *flexcan_device_alloc(struct platform_device *pdev,
 		return NULL;
 	}
 	flexcan_device_default(flexcan);
+	flexcan_set_bitrate(flexcan, flexcan->bitrate);
 	flexcan_update_bitrate(flexcan);
 
 	num = ARRAY_SIZE(flexcan_dev_attr);
diff --git a/drivers/net/can/flexcan/flexcan.h b/drivers/net/can/flexcan/flexcan.h
index d19cc1ee0620..51a800bd8e55 100644
--- a/drivers/net/can/flexcan/flexcan.h
+++ b/drivers/net/can/flexcan/flexcan.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -32,17 +32,6 @@
 
 #define FLEXCAN_DEVICE_NAME	"FlexCAN"
 
-struct can_mb_cs {
-	unsigned int time_stamp:16;
-	unsigned int length:4;
-	unsigned int rtr:1;
-	unsigned int ide:1;
-	unsigned int srr:1;
-	unsigned int nouse1:1;
-	unsigned int code:4;
-	unsigned int nouse2:4;
-};
-
 #define CAN_MB_RX_INACTIVE	0x0
 #define CAN_MB_RX_EMPTY		0x4
 #define CAN_MB_RX_FULL		0x2
@@ -55,14 +44,24 @@ struct can_mb_cs {
 #define CAN_MB_TX_REMOTE	0xA
 
 struct can_hw_mb {
-	union {
-		struct can_mb_cs cs;
-		unsigned int data;
-	} mb_cs;
+	unsigned int mb_cs;
 	unsigned int mb_id;
 	unsigned char mb_data[8];
 };
 
+#define MB_CS_CODE_OFFSET	24
+#define MB_CS_CODE_MASK		(0xF << MB_CS_CODE_OFFSET)
+#define MB_CS_SRR_OFFSET	22
+#define MB_CS_SRR_MASK		(0x1 << MB_CS_SRR_OFFSET)
+#define MB_CS_IDE_OFFSET	21
+#define MB_CS_IDE_MASK		(0x1 << MB_CS_IDE_OFFSET)
+#define MB_CS_RTR_OFFSET	20
+#define MB_CS_RTR_MASK		(0x1 << MB_CS_RTR_OFFSET)
+#define MB_CS_LENGTH_OFFSET	16
+#define MB_CS_LENGTH_MASK	(0xF << MB_CS_LENGTH_OFFSET)
+#define MB_CS_TIMESTAMP_OFFSET	0
+#define MB_CS_TIMESTAMP_MASK	(0xFF << MB_CS_TIMESTAMP_OFFSET)
+
 #define CAN_HW_REG_MCR		0x00
 #define CAN_HW_REG_CTRL		0x04
 #define CAN_HW_REG_TIMER	0x08
diff --git a/drivers/net/can/flexcan/mbm.c b/drivers/net/can/flexcan/mbm.c
index b0341ba9128e..42266e719ce3 100644
--- a/drivers/net/can/flexcan/mbm.c
+++ b/drivers/net/can/flexcan/mbm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -55,10 +55,13 @@ static void flexcan_mb_bottom(struct net_device *dev, int index)
 
 	hwmb = flexcan->hwmb + index;
 	if (flexcan->fifo || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) {
-		if (hwmb->mb_cs.cs.code == CAN_MB_TX_ABORT)
-			hwmb->mb_cs.cs.code = CAN_MB_TX_INACTIVE;
+		if ((hwmb->mb_cs & MB_CS_CODE_MASK) >> MB_CS_CODE_OFFSET ==
+							CAN_MB_TX_ABORT) {
+			hwmb->mb_cs &= ~MB_CS_CODE_MASK;
+			hwmb->mb_cs |= CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET;
+		}
 
-		if (hwmb->mb_cs.cs.code & CAN_MB_TX_INACTIVE) {
+		if (hwmb->mb_cs & (CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET)) {
 			if (netif_queue_stopped(dev))
 				netif_start_queue(dev);
 			return;
@@ -68,16 +71,17 @@ static void flexcan_mb_bottom(struct net_device *dev, int index)
 	if (skb) {
 		frame = (struct can_frame *)skb_put(skb, sizeof(*frame));
 		memset(frame, 0, sizeof(*frame));
-		if (hwmb->mb_cs.cs.ide)
+		if (hwmb->mb_cs & MB_CS_IDE_MASK)
 			frame->can_id =
 			    (hwmb->mb_id & CAN_EFF_MASK) | CAN_EFF_FLAG;
 		else
 			frame->can_id = (hwmb->mb_id >> 18) & CAN_SFF_MASK;
 
-		if (hwmb->mb_cs.cs.rtr)
+		if (hwmb->mb_cs & MB_CS_RTR_MASK)
 			frame->can_id |= CAN_RTR_FLAG;
 
-		frame->can_dlc = hwmb->mb_cs.cs.length;
+		frame->can_dlc =
+		(hwmb->mb_cs & MB_CS_LENGTH_MASK) >> MB_CS_LENGTH_OFFSET;
 
 		if (frame->can_dlc && frame->can_dlc)
 			flexcan_memcpy(frame->data, hwmb->mb_data,
@@ -85,7 +89,8 @@ static void flexcan_mb_bottom(struct net_device *dev, int index)
 
 		if (flexcan->fifo
 		    || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) {
-			hwmb->mb_cs.cs.code = CAN_MB_TX_INACTIVE;
+			hwmb->mb_cs &= ~MB_CS_CODE_MASK;
+			hwmb->mb_cs |= CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET;
 			if (netif_queue_stopped(dev))
 				netif_start_queue(dev);
 		}
@@ -101,13 +106,13 @@ static void flexcan_mb_bottom(struct net_device *dev, int index)
 		skb->ip_summed = CHECKSUM_UNNECESSARY;
 		netif_rx(skb);
 	} else {
-		tmp = hwmb->mb_cs.data;
+		tmp = hwmb->mb_cs;
 		tmp = hwmb->mb_id;
 		tmp = hwmb->mb_data[0];
 		if (flexcan->fifo
 		    || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) {
-
-			hwmb->mb_cs.cs.code = CAN_MB_TX_INACTIVE;
+			hwmb->mb_cs &= ~MB_CS_CODE_MASK;
+			hwmb->mb_cs |= CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET;
 			if (netif_queue_stopped(dev))
 				netif_start_queue(dev);
 		}
@@ -131,17 +136,19 @@ static void flexcan_fifo_isr(struct net_device *dev, unsigned int iflag1)
 			frame =
 			    (struct can_frame *)skb_put(skb, sizeof(*frame));
 			memset(frame, 0, sizeof(*frame));
-			if (hwmb->mb_cs.cs.ide)
+			if (hwmb->mb_cs & MB_CS_IDE_MASK)
 				frame->can_id =
 				    (hwmb->mb_id & CAN_EFF_MASK) | CAN_EFF_FLAG;
 			else
 				frame->can_id =
 				    (hwmb->mb_id >> 18) & CAN_SFF_MASK;
 
-			if (hwmb->mb_cs.cs.rtr)
+			if (hwmb->mb_cs & MB_CS_RTR_MASK)
 				frame->can_id |= CAN_RTR_FLAG;
 
-			frame->can_dlc = hwmb->mb_cs.cs.length;
+			frame->can_dlc =
+				(hwmb->mb_cs & MB_CS_LENGTH_MASK) >>
+						MB_CS_LENGTH_OFFSET;
 
 			if (frame->can_dlc && (frame->can_dlc <= 8))
 				flexcan_memcpy(frame->data, hwmb->mb_data,
@@ -158,7 +165,7 @@ static void flexcan_fifo_isr(struct net_device *dev, unsigned int iflag1)
 			skb->ip_summed = CHECKSUM_UNNECESSARY;
 			netif_rx(skb);
 		} else {
-			tmp = hwmb->mb_cs.data;
+			tmp = hwmb->mb_cs;
 			tmp = hwmb->mb_id;
 			tmp = hwmb->mb_data[0];
 			tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER);
@@ -252,7 +259,8 @@ int flexcan_mbm_xmit(struct flexcan_device *flexcan, struct can_frame *frame)
 	struct can_hw_mb *hwmb = flexcan->hwmb;
 
 	do {
-		if (hwmb[i].mb_cs.cs.code == CAN_MB_TX_INACTIVE)
+		if ((hwmb[i].mb_cs & MB_CS_CODE_MASK) >> MB_CS_CODE_OFFSET ==
+							    CAN_MB_TX_INACTIVE)
 			break;
 		if ((++i) > flexcan->maxmb) {
 			if (flexcan->fifo)
@@ -273,22 +281,24 @@ int flexcan_mbm_xmit(struct flexcan_device *flexcan, struct can_frame *frame)
 	}
 
 	if (frame->can_id & CAN_RTR_FLAG)
-		hwmb[i].mb_cs.cs.rtr = 1;
+		hwmb[i].mb_cs |= 1 << MB_CS_RTR_OFFSET;
 	else
-		hwmb[i].mb_cs.cs.rtr = 0;
+		hwmb[i].mb_cs &= ~MB_CS_RTR_MASK;
 
 	if (frame->can_id & CAN_EFF_FLAG) {
-		hwmb[i].mb_cs.cs.ide = 1;
-		hwmb[i].mb_cs.cs.srr = 1;
+		hwmb[i].mb_cs |= 1 << MB_CS_IDE_OFFSET;
+		hwmb[i].mb_cs |= 1 << MB_CS_SRR_OFFSET;
 		hwmb[i].mb_id = frame->can_id & CAN_EFF_MASK;
 	} else {
-		hwmb[i].mb_cs.cs.ide = 0;
+		hwmb[i].mb_cs &= ~MB_CS_IDE_MASK;
 		hwmb[i].mb_id = (frame->can_id & CAN_SFF_MASK) << 18;
 	}
 
-	hwmb[i].mb_cs.cs.length = frame->can_dlc;
+	hwmb[i].mb_cs &= MB_CS_LENGTH_MASK;
+	hwmb[i].mb_cs |= frame->can_dlc << MB_CS_LENGTH_OFFSET;
 	flexcan_memcpy(hwmb[i].mb_data, frame->data, frame->can_dlc);
-	hwmb[i].mb_cs.cs.code = CAN_MB_TX_ONCE;
+	hwmb[i].mb_cs &= ~MB_CS_CODE_MASK;
+	hwmb[i].mb_cs |= CAN_MB_TX_ONCE << MB_CS_CODE_OFFSET;
 	return 0;
 }
 
@@ -325,23 +335,27 @@ void flexcan_mbm_init(struct flexcan_device *flexcan)
 			id_table[i] = 0;
 	} else {
 		for (i = 0; i < rx_mb; i++) {
-			hwmb[i].mb_cs.cs.code = CAN_MB_RX_EMPTY;
+			hwmb[i].mb_cs &= ~MB_CS_CODE_MASK;
+			hwmb[i].mb_cs |= CAN_MB_RX_EMPTY << MB_CS_CODE_OFFSET;
 			/*
 			 * IDE bit can not control by mask registers
 			 * So set message buffer to receive extend
 			 * or standard message.
 			 */
-			if (flexcan->ext_msg && flexcan->std_msg)
-				hwmb[i].mb_cs.cs.ide = i & 1;
-			else {
+			if (flexcan->ext_msg && flexcan->std_msg) {
+				hwmb[i].mb_cs &= ~MB_CS_IDE_MASK;
+				hwmb[i].mb_cs |= (i & 1) << MB_CS_IDE_OFFSET;
+			} else {
 				if (flexcan->ext_msg)
-					hwmb[i].mb_cs.cs.ide = 1;
+					hwmb[i].mb_cs |= 1 << MB_CS_IDE_OFFSET;
 			}
 		}
 	}
 
-	for (; i <= flexcan->maxmb; i++)
-		hwmb[i].mb_cs.cs.code = CAN_MB_TX_INACTIVE;
+	for (; i <= flexcan->maxmb; i++) {
+		hwmb[i].mb_cs &= ~MB_CS_CODE_MASK;
+		hwmb[i].mb_cs |= CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET;
+	}
 
 	flexcan->xmit_mb = rx_mb;
 }
diff --git a/drivers/net/can/vcan.c b/drivers/net/can/vcan.c
index a10c1d7b3b0a..460bb886fbdf 100644
--- a/drivers/net/can/vcan.c
+++ b/drivers/net/can/vcan.c
@@ -80,7 +80,7 @@ static void vcan_rx(struct sk_buff *skb, struct net_device *dev)
 	skb->dev       = dev;
 	skb->ip_summed = CHECKSUM_UNNECESSARY;
 
-	netif_rx(skb);
+	netif_rx_ni(skb);
 }
 
 static int vcan_tx(struct sk_buff *skb, struct net_device *dev)
diff --git a/drivers/net/e100.c b/drivers/net/e100.c
index 3a6735dc9f6a..c786e6a96eae 100644
--- a/drivers/net/e100.c
+++ b/drivers/net/e100.c
@@ -156,6 +156,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/mii.h>
@@ -601,6 +602,7 @@ struct nic {
 	struct mem *mem;
 	dma_addr_t dma_addr;
 
+	struct pci_pool *cbs_pool;
 	dma_addr_t cbs_dma_addr;
 	u8 adaptive_ifs;
 	u8 tx_threshold;
@@ -1779,9 +1781,7 @@ static void e100_clean_cbs(struct nic *nic)
 			nic->cb_to_clean = nic->cb_to_clean->next;
 			nic->cbs_avail++;
 		}
-		pci_free_consistent(nic->pdev,
-			sizeof(struct cb) * nic->params.cbs.count,
-			nic->cbs, nic->cbs_dma_addr);
+		pci_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
 		nic->cbs = NULL;
 		nic->cbs_avail = 0;
 	}
@@ -1799,10 +1799,11 @@ static int e100_alloc_cbs(struct nic *nic)
 	nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
 	nic->cbs_avail = 0;
 
-	nic->cbs = pci_alloc_consistent(nic->pdev,
-		sizeof(struct cb) * count, &nic->cbs_dma_addr);
+	nic->cbs = pci_pool_alloc(nic->cbs_pool, GFP_KERNEL,
+				  &nic->cbs_dma_addr);
 	if (!nic->cbs)
 		return -ENOMEM;
+	memset(nic->cbs, 0, count * sizeof(struct cb));
 
 	for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
 		cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
@@ -1811,7 +1812,6 @@ static int e100_alloc_cbs(struct nic *nic)
 		cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
 		cb->link = cpu_to_le32(nic->cbs_dma_addr +
 			((i+1) % count) * sizeof(struct cb));
-		cb->skb = NULL;
 	}
 
 	nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
@@ -2827,7 +2827,11 @@ static int __devinit e100_probe(struct pci_dev *pdev,
 		DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
 		goto err_out_free;
 	}
-
+	nic->cbs_pool = pci_pool_create(netdev->name,
+			   nic->pdev,
+			   nic->params.cbs.count * sizeof(struct cb),
+			   sizeof(u32),
+			   0);
 	DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, MAC addr %pM\n",
 		(unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
 		pdev->irq, netdev->dev_addr);
@@ -2857,6 +2861,7 @@ static void __devexit e100_remove(struct pci_dev *pdev)
 		unregister_netdev(netdev);
 		e100_free(nic);
 		pci_iounmap(pdev, nic->csr);
+		pci_pool_destroy(nic->cbs_pool);
 		free_netdev(netdev);
 		pci_release_regions(pdev);
 		pci_disable_device(pdev);
diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c
index b53b40ba88a8..d1e0563a67df 100644
--- a/drivers/net/e1000e/82571.c
+++ b/drivers/net/e1000e/82571.c
@@ -1803,7 +1803,7 @@ struct e1000_info e1000_82574_info = {
 				  | FLAG_HAS_AMT
 				  | FLAG_HAS_CTRLEXT_ON_LOAD,
 	.pba			= 20,
-	.max_hw_frame_size	= ETH_FRAME_LEN + ETH_FCS_LEN,
+	.max_hw_frame_size	= DEFAULT_JUMBO,
 	.get_variants		= e1000_get_variants_82571,
 	.mac_ops		= &e82571_mac_ops,
 	.phy_ops		= &e82_phy_ops_bm,
@@ -1820,7 +1820,7 @@ struct e1000_info e1000_82583_info = {
 				  | FLAG_HAS_AMT
 				  | FLAG_HAS_CTRLEXT_ON_LOAD,
 	.pba			= 20,
-	.max_hw_frame_size	= DEFAULT_JUMBO,
+	.max_hw_frame_size	= ETH_FRAME_LEN + ETH_FCS_LEN,
 	.get_variants		= e1000_get_variants_82571,
 	.mac_ops		= &e82571_mac_ops,
 	.phy_ops		= &e82_phy_ops_bm,
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
index 582eb37390ed..8a34f4679fa5 100644
--- a/drivers/net/enc28j60.c
+++ b/drivers/net/enc28j60.c
@@ -30,8 +30,6 @@
 #include <linux/delay.h>
 #include <linux/spi/spi.h>
 
-#include <mach/platform.h>
-
 #include "enc28j60_hw.h"
 
 #define DRV_NAME	"enc28j60"
@@ -53,9 +51,17 @@
 #define MAX_TX_RETRYCOUNT	16
 
 #ifdef CONFIG_ARCH_STMP3XXX
+#include <mach/platform.h>
 #include <mach/stmp3xxx.h>
 #include <mach/regs-ocotp.h>
 #endif
+#ifdef CONFIG_ARCH_MXS
+#include <mach/system.h>
+#include <mach/hardware.h>
+#include <mach/regs-ocotp.h>
+#define REGS_OCOTP_BASE	IO_ADDRESS(OCOTP_PHYS_ADDR)
+#endif
+
 enum {
 	RXFILTER_NORMAL,
 	RXFILTER_MULTI,
@@ -104,12 +110,14 @@ static int enc28j60_get_mac(unsigned char *dev_addr, int idx)
 		return false;
 
 	if (!mac[idx]) {
-#ifdef CONFIG_ARCH_STMP3XXX
+#if defined(CONFIG_ARCH_STMP3XXX) || defined(CONFIG_ARCH_MXS)
 		if (get_evk_board_version() >= 1) {
 			int mac1 , mac2 , retry = 0;
 
-			stmp3xxx_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, REGS_OCOTP_BASE + HW_OCOTP_CTRL);
-			while (__raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL) & BM_OCOTP_CTRL_BUSY) {
+			__raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN,
+					REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET);
+			while (__raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL) &
+					BM_OCOTP_CTRL_BUSY) {
 				msleep(10);
 				retry++;
 				if (retry > 10)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 46799e092bc1..d8817aad351f 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1131,17 +1131,18 @@ fec_set_mac_address(struct net_device *dev, void *p)
 {
 	struct fec_enet_private *fep = netdev_priv(dev);
 	struct sockaddr *addr = p;
+	u32 temp_mac[2];
 
 	if (!is_valid_ether_addr(addr->sa_data))
 		return -EADDRNOTAVAIL;
 
 	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
 
-	writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
-		(dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
-		fep->hwp + FEC_ADDR_LOW);
-	writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24),
-		fep + FEC_ADDR_HIGH);
+	memcpy(&temp_mac, dev->dev_addr, ETH_ALEN);
+
+	writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
+	writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
+
 	return 0;
 }
 
@@ -1277,6 +1278,7 @@ fec_restart(struct net_device *dev, int duplex)
 	/* Clear any outstanding interrupt. */
 	writel(0xffc00000, fep->hwp + FEC_IEVENT);
 
+#if !defined(CONFIG_MACH_CCMX51JS) && !defined(CONFIG_MACH_CCWMX51JS)
 	/* Reset all multicast.	*/
 	writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
 	writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
@@ -1284,6 +1286,7 @@ fec_restart(struct net_device *dev, int duplex)
 	writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
 	writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
 #endif
+#endif /* !defined(CONFIG_MACH_CCMX51JS) && !defined(CONFIG_MACH_CCWMX51JS) */
 
 #ifndef CONFIG_ARCH_MXS
 	if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
@@ -1499,10 +1502,10 @@ fec_probe(struct platform_device *pdev)
 		fep->mii_bus = fec_mii_bus;
 	}
 
-	fep->ptp_priv = kmalloc(sizeof(struct fec_ptp_private), GFP_KERNEL);
+	fep->ptp_priv = kzalloc(sizeof(struct fec_ptp_private), GFP_KERNEL);
 	if (fep->ptp_priv) {
 		fep->ptp_priv->hwp = fep->hwp;
-		ret = fec_ptp_init(fep->ptp_priv);
+		ret = fec_ptp_init(fep->ptp_priv, pdev->id);
 		if (ret)
 			printk(KERN_WARNING
 					"IEEE1588: ptp-timer is unavailable\n");
diff --git a/drivers/net/fec_1588.c b/drivers/net/fec_1588.c
index 5babcc29de78..37b1b01778fd 100644
--- a/drivers/net/fec_1588.c
+++ b/drivers/net/fec_1588.c
@@ -35,7 +35,7 @@
 static DECLARE_WAIT_QUEUE_HEAD(ptp_rx_ts_wait);
 #define PTP_GET_RX_TIMEOUT      (HZ/10)
 
-static struct fec_ptp_private *ptp_private;
+static struct fec_ptp_private *ptp_private[2];
 
 /* Alloc the ring resource */
 static int fec_ptp_init_circ(struct circ_buf *ptp_buf)
@@ -88,14 +88,15 @@ static int fec_ptp_is_full(struct circ_buf *buf)
 }
 
 static int fec_ptp_insert(struct circ_buf *ptp_buf,
-				struct fec_ptp_data_t *data)
+			  struct fec_ptp_data_t *data,
+			  struct fec_ptp_private *priv)
 {
 	struct fec_ptp_data_t *tmp;
 
 	if (fec_ptp_is_full(ptp_buf))
 		return 1;
 
-	spin_lock(&ptp_private->ptp_lock);
+	spin_lock(&priv->ptp_lock);
 	tmp = (struct fec_ptp_data_t *)(ptp_buf->buf) + ptp_buf->tail;
 
 	tmp->key = data->key;
@@ -104,13 +105,15 @@ static int fec_ptp_insert(struct circ_buf *ptp_buf,
 
 	ptp_buf->tail = fec_ptp_calc_index(DEFAULT_PTP_RX_BUF_SZ,
 					ptp_buf->tail, 1);
-	spin_unlock(&ptp_private->ptp_lock);
+	spin_unlock(&priv->ptp_lock);
 
 	return 0;
 }
 
 static int fec_ptp_find_and_remove(struct circ_buf *ptp_buf,
-			int key, struct fec_ptp_data_t *data)
+				   int key,
+				   struct fec_ptp_data_t *data,
+				   struct fec_ptp_private *priv)
 {
 	int i;
 	int size = DEFAULT_PTP_RX_BUF_SZ;
@@ -129,10 +132,10 @@ static int fec_ptp_find_and_remove(struct circ_buf *ptp_buf,
 		i = fec_ptp_calc_index(size, i, 1);
 	}
 
-	spin_lock_irqsave(&ptp_private->ptp_lock, flags);
+	spin_lock_irqsave(&priv->ptp_lock, flags);
 	if (i == end) {
 		ptp_buf->head = end;
-		spin_unlock_irqrestore(&ptp_private->ptp_lock, flags);
+		spin_unlock_irqrestore(&priv->ptp_lock, flags);
 		return 1;
 	}
 
@@ -140,7 +143,7 @@ static int fec_ptp_find_and_remove(struct circ_buf *ptp_buf,
 	data->ts_time.nsec = tmp->ts_time.nsec;
 
 	ptp_buf->head = fec_ptp_calc_index(size, i, 1);
-	spin_unlock_irqrestore(&ptp_private->ptp_lock, flags);
+	spin_unlock_irqrestore(&priv->ptp_lock, flags);
 
 	return 0;
 }
@@ -154,9 +157,9 @@ int fec_ptp_start(struct fec_ptp_private *priv)
 	writel(FEC_T_CTRL_RESTART, fpp->hwp + FEC_ATIME_CTRL);
 	writel(FEC_T_INC_40MHZ << FEC_T_INC_OFFSET, fpp->hwp + FEC_ATIME_INC);
 	writel(FEC_T_PERIOD_ONE_SEC, fpp->hwp + FEC_ATIME_EVT_PERIOD);
-	writel(FEC_T_CTRL_PERIOD_RST, fpp->hwp + FEC_ATIME_CTRL);
 	/* start counter */
-	writel(FEC_T_CTRL_ENABLE, fpp->hwp + FEC_ATIME_CTRL);
+	writel(FEC_T_CTRL_PERIOD_RST | FEC_T_CTRL_ENABLE,
+			fpp->hwp + FEC_ATIME_CTRL);
 
 	return 0;
 }
@@ -190,12 +193,12 @@ static void fec_set_1588cnt(struct fec_ptp_private *priv,
 	u32 tempval;
 	unsigned long flags;
 
-	spin_lock_irqsave(&ptp_private->cnt_lock, flags);
+	spin_lock_irqsave(&priv->cnt_lock, flags);
 	priv->prtc = fec_time->rtc_time.sec;
 
 	tempval = fec_time->rtc_time.nsec;
 	writel(tempval, priv->hwp + FEC_ATIME);
-	spin_unlock_irqrestore(&ptp_private->cnt_lock, flags);
+	spin_unlock_irqrestore(&priv->cnt_lock, flags);
 }
 
 /* Set the BD to ptp */
@@ -207,11 +210,11 @@ int fec_ptp_do_txstamp(struct sk_buff *skb)
 	if (skb->len > 44) {
 		/* Check if port is 319 for PTP Event, and check for UDP */
 		iph = ip_hdr(skb);
-		if (iph->protocol != FEC_PACKET_TYPE_UDP)
+		if (iph == NULL || iph->protocol != FEC_PACKET_TYPE_UDP)
 			return 0;
 
 		udph = udp_hdr(skb);
-		if (udph->source == 319)
+		if (udph != NULL && udph->source == 319)
 			return 1;
 	}
 
@@ -257,11 +260,11 @@ void fec_ptp_store_rxstamp(struct fec_ptp_private *priv,
 	switch (control) {
 
 	case PTP_MSG_SYNC:
-		fec_ptp_insert(&(priv->rx_time_sync), &tmp_rx_time);
+		fec_ptp_insert(&(priv->rx_time_sync), &tmp_rx_time, priv);
 		break;
 
 	case PTP_MSG_DEL_REQ:
-		fec_ptp_insert(&(priv->rx_time_del_req), &tmp_rx_time);
+		fec_ptp_insert(&(priv->rx_time_del_req), &tmp_rx_time, priv);
 		break;
 
 	/* clear transportSpecific field*/
@@ -271,11 +274,11 @@ void fec_ptp_store_rxstamp(struct fec_ptp_private *priv,
 		switch (msg_type) {
 		case PTP_MSG_P_DEL_REQ:
 			fec_ptp_insert(&(priv->rx_time_pdel_req),
-						&tmp_rx_time);
+						&tmp_rx_time, priv);
 			break;
 		case PTP_MSG_P_DEL_RESP:
 			fec_ptp_insert(&(priv->rx_time_pdel_resp),
-					&tmp_rx_time);
+					&tmp_rx_time, priv);
 			break;
 		default:
 			break;
@@ -308,20 +311,20 @@ static uint8_t fec_get_rx_time(struct fec_ptp_private *priv,
 	switch (mode) {
 	case PTP_MSG_SYNC:
 		flag = fec_ptp_find_and_remove(&(priv->rx_time_sync),
-						key, &tmp);
+						key, &tmp, priv);
 		break;
 	case PTP_MSG_DEL_REQ:
 		flag = fec_ptp_find_and_remove(&(priv->rx_time_del_req),
-						key, &tmp);
+						key, &tmp, priv);
 		break;
 
 	case PTP_MSG_P_DEL_REQ:
 		flag = fec_ptp_find_and_remove(&(priv->rx_time_pdel_req),
-						key, &tmp);
+						key, &tmp, priv);
 		break;
 	case PTP_MSG_P_DEL_RESP:
 		flag = fec_ptp_find_and_remove(&(priv->rx_time_pdel_resp),
-						key, &tmp);
+						key, &tmp, priv);
 		break;
 
 	default:
@@ -341,19 +344,19 @@ static uint8_t fec_get_rx_time(struct fec_ptp_private *priv,
 		switch (mode) {
 		case PTP_MSG_SYNC:
 			flag = fec_ptp_find_and_remove(&(priv->rx_time_sync),
-				key, &tmp);
+				key, &tmp, priv);
 			break;
 		case PTP_MSG_DEL_REQ:
 			flag = fec_ptp_find_and_remove(
-				&(priv->rx_time_del_req), key, &tmp);
+				&(priv->rx_time_del_req), key, &tmp, priv);
 			break;
 		case PTP_MSG_P_DEL_REQ:
 			flag = fec_ptp_find_and_remove(
-				&(priv->rx_time_pdel_req), key, &tmp);
+				&(priv->rx_time_pdel_req), key, &tmp, priv);
 			break;
 		case PTP_MSG_P_DEL_RESP:
 			flag = fec_ptp_find_and_remove(
-				&(priv->rx_time_pdel_resp), key, &tmp);
+				&(priv->rx_time_pdel_resp), key, &tmp, priv);
 			break;
 		}
 
@@ -388,9 +391,10 @@ static int ptp_ioctl(
 	struct ptp_time rx_time, tx_time;
 	struct ptp_ts_data *p_ts;
 	struct fec_ptp_private *priv;
+	unsigned int minor = MINOR(inode->i_rdev);
 	int retval = 0;
 
-	priv = (struct fec_ptp_private *) ptp_private;
+	priv = (struct fec_ptp_private *) ptp_private[minor];
 	switch (cmd) {
 	case PTP_GET_RX_TIMESTAMP:
 		p_ts = (struct ptp_ts_data *)arg;
@@ -466,7 +470,7 @@ static void ptp_free(void)
 /*
  * Resource required for accessing 1588 Timer Registers.
  */
-int fec_ptp_init(struct fec_ptp_private *priv)
+int fec_ptp_init(struct fec_ptp_private *priv, int id)
 {
 	fec_ptp_init_circ(&(priv->rx_time_sync));
 	fec_ptp_init_circ(&(priv->rx_time_del_req));
@@ -475,8 +479,9 @@ int fec_ptp_init(struct fec_ptp_private *priv)
 
 	spin_lock_init(&priv->ptp_lock);
 	spin_lock_init(&priv->cnt_lock);
-	ptp_private = priv;
-	init_ptp();
+	ptp_private[id] = priv;
+	if (id == 0)
+		init_ptp();
 	return 0;
 }
 EXPORT_SYMBOL(fec_ptp_init);
diff --git a/drivers/net/fec_1588.h b/drivers/net/fec_1588.h
index 55b1a8c995bd..a503527eadbb 100644
--- a/drivers/net/fec_1588.h
+++ b/drivers/net/fec_1588.h
@@ -33,7 +33,7 @@
 #define FEC_T_INC_MASK			0x0000007f
 #define FEC_T_INC_OFFSET		0
 
-#define FEC_T_INC_40MHZ			20
+#define FEC_T_INC_40MHZ			25
 
 #define FEC_T_PERIOD_ONE_SEC		0x3B9ACA00
 
@@ -124,7 +124,7 @@ struct fec_ptp_private {
 };
 
 #ifdef CONFIG_FEC_1588
-extern int fec_ptp_init(struct fec_ptp_private *priv);
+extern int fec_ptp_init(struct fec_ptp_private *priv, int id);
 extern void fec_ptp_cleanup(struct fec_ptp_private *priv);
 extern int fec_ptp_start(struct fec_ptp_private *priv);
 extern void fec_ptp_stop(struct fec_ptp_private *priv);
@@ -134,7 +134,7 @@ extern void fec_ptp_store_rxstamp(struct fec_ptp_private *priv,
 				  struct sk_buff *skb,
 				  struct bufdesc *bdp);
 #else
-static inline int fec_ptp_init(struct fec_ptp_private *priv)
+static inline int fec_ptp_init(struct fec_ptp_private *priv, int id)
 {
 	return 1;
 }
diff --git a/drivers/net/fec_switch.c b/drivers/net/fec_switch.c
new file mode 100644
index 000000000000..f2c78e439278
--- /dev/null
+++ b/drivers/net/fec_switch.c
@@ -0,0 +1,4238 @@
+/*
+ *  L2 switch Controller (Etheren switch) driver for Mx28.
+ *
+ *  Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    Shrek Wu (B16972@freescale.com)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/ptrace.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/fec.h>
+#include <linux/phy.h>
+
+#include <asm/irq.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <asm/pgtable.h>
+#include <asm/cacheflush.h>
+
+#include "fec_switch.h"
+
+#define	SWITCH_MAX_PORTS	1
+
+#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS)
+#include <mach/hardware.h>
+#define FEC_ALIGNMENT   0xf
+#else
+#define FEC_ALIGNMENT   0x3
+#endif
+
+/* The number of Tx and Rx buffers.  These are allocated from the page
+ * pool.  The code may assume these are power of two, so it it best
+ * to keep them that size.
+ * We don't need to allocate pages for the transmitter.  We just use
+ * the skbuffer directly.
+ */
+#define FEC_ENET_RX_PAGES       8
+#define FEC_ENET_RX_FRSIZE      2048
+#define FEC_ENET_RX_FRPPG       (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
+#define FEC_ENET_TX_FRSIZE      2048
+#define FEC_ENET_TX_FRPPG       (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
+#define TX_RING_SIZE            16      /* Must be power of two */
+#define TX_RING_MOD_MASK        15      /*   for this to work */
+
+#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
+#error "FEC: descriptor ring size constants too large"
+#endif
+
+/* Interrupt events/masks */
+#define FEC_ENET_HBERR	((uint)0x80000000)	/* Heartbeat error */
+#define FEC_ENET_BABR	((uint)0x40000000)	/* Babbling receiver */
+#define FEC_ENET_BABT	((uint)0x20000000)	/* Babbling transmitter */
+#define FEC_ENET_GRA	((uint)0x10000000)	/* Graceful stop complete */
+#define FEC_ENET_TXF	((uint)0x08000000)	/* Full frame transmitted */
+#define FEC_ENET_TXB	((uint)0x04000000)	/* A buffer was transmitted */
+#define FEC_ENET_RXF	((uint)0x02000000)	/* Full frame received */
+#define FEC_ENET_RXB	((uint)0x01000000)	/* A buffer was received */
+#define FEC_ENET_MII	((uint)0x00800000)	/* MII interrupt */
+#define FEC_ENET_EBERR	((uint)0x00400000)	/* SDMA bus error */
+
+/* FEC MII MMFR bits definition */
+#define FEC_MMFR_ST             (1 << 30)
+#define FEC_MMFR_OP_READ        (2 << 28)
+#define FEC_MMFR_OP_WRITE       (1 << 28)
+#define FEC_MMFR_PA(v)          ((v & 0x1f) << 23)
+#define FEC_MMFR_RA(v)          ((v & 0x1f) << 18)
+#define FEC_MMFR_TA             (2 << 16)
+#define FEC_MMFR_DATA(v)        (v & 0xffff)
+
+#ifdef FEC_PHY
+static struct phy_device *g_phy_dev;
+static struct mii_bus *fec_mii_bus;
+#endif
+
+static int switch_enet_open(struct net_device *dev);
+static int switch_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
+static irqreturn_t switch_enet_interrupt(int irq, void *dev_id);
+static void switch_enet_tx(struct net_device *dev);
+static void switch_enet_rx(struct net_device *dev);
+static int switch_enet_close(struct net_device *dev);
+static void set_multicast_list(struct net_device *dev);
+static void switch_restart(struct net_device *dev, int duplex);
+static void switch_stop(struct net_device *dev);
+
+#define		NMII	20
+
+/* Make MII read/write commands for the FEC */
+#define mk_mii_read(REG)	(0x60020000 | ((REG & 0x1f) << 18))
+#define mk_mii_write(REG, VAL)	(0x50020000 | ((REG & 0x1f) << 18) | \
+						(VAL & 0xffff))
+
+/* Transmitter timeout */
+#define TX_TIMEOUT (2*HZ)
+#define FEC_MII_TIMEOUT	10
+
+#ifdef CONFIG_ARCH_MXS
+static void *swap_buffer(void *bufaddr, int len)
+{
+	int i;
+	unsigned int *buf = bufaddr;
+
+	for (i = 0; i < (len + 3) / 4; i++, buf++)
+		*buf = __swab32(*buf);
+
+	return bufaddr;
+}
+#endif
+
+/*last read entry from learning interface*/
+struct eswPortInfo g_info;
+
+static unsigned char    switch_mac_default[] = {
+	0x00, 0x08, 0x02, 0x6B, 0xA3, 0x1A,
+};
+
+static void switch_request_intrs(struct net_device *dev,
+	irqreturn_t switch_net_irq_handler(int irq, void *private),
+	void *irq_privatedata)
+{
+	struct switch_enet_private *fep;
+
+	fep = netdev_priv(dev);
+
+	/* Setup interrupt handlers */
+	if (request_irq(dev->irq,
+		switch_net_irq_handler, IRQF_DISABLED,
+		"mxs-l2switch", irq_privatedata) != 0)
+		printk(KERN_ERR "FEC: Could not alloc %s IRQ(%d)!\n",
+			dev->name, dev->irq);
+}
+
+static void switch_set_mii(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	struct switch_t *fecp;
+
+	fecp = (struct switch_t *)fep->hwp;
+
+	writel(MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE |
+			MCF_FEC_RCR_MAX_FL(1522),
+			fep->enet_addr + MCF_FEC_RCR0);
+	writel(MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE |
+			MCF_FEC_RCR_MAX_FL(1522),
+			fep->enet_addr + MCF_FEC_RCR1);
+	/* TCR */
+	writel(MCF_FEC_TCR_FDEN, fep->enet_addr + MCF_FEC_TCR0);
+	writel(MCF_FEC_TCR_FDEN, fep->enet_addr + MCF_FEC_TCR1);
+
+	/* ECR */
+#ifdef L2SWITCH_ENHANCED_BUFFER
+	writel(MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588,
+			fep->enet_addr + MCF_FEC_ECR0);
+	writel(MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588,
+			fep->enet_addr + MCF_FEC_ECR1);
+#else /*legac buffer*/
+	writel(MCF_FEC_ECR_ETHER_EN, fep->enet_addr + MCF_FEC_ECR0);
+	writel(MCF_FEC_ECR_ETHER_EN, fep->enet_addr + MCF_FEC_ECR1);
+#endif
+	writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->enet_addr + MCF_FEC_EIMR0);
+	writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->enet_addr + MCF_FEC_EIMR1);
+
+	/*
+	* Set MII speed to 2.5 MHz
+	*/
+	writel(DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1,
+			fep->enet_addr + MCF_FEC_MSCR0);
+	writel(DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1,
+			fep->enet_addr + MCF_FEC_MSCR1);
+
+#ifdef CONFIG_ARCH_MXS
+	/* Can't get phy(8720) ID when set to 2.5M on MX28, lower it*/
+	fep->phy_speed = readl(fep->enet_addr + MCF_FEC_MSCR0) << 2;
+	writel(fep->phy_speed, fep->enet_addr + MCF_FEC_MSCR0);
+	writel(fep->phy_speed, fep->enet_addr + MCF_FEC_MSCR1);
+#endif
+
+}
+
+static void switch_get_mac(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	unsigned char *iap, tmpaddr[ETH_ALEN];
+	static int index;
+#ifdef CONFIG_M5272
+	if (FEC_FLASHMAC) {
+		/*
+		 * Get MAC address from FLASH.
+		 * If it is all 1's or 0's, use the default.
+		 */
+		iap = (unsigned char *)FEC_FLASHMAC;
+		if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
+		    (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
+			iap = switch_mac_default;
+		if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
+		    (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
+			iap = switch_mac_default;
+	}
+#else
+	if (is_valid_ether_addr(switch_mac_default))
+		iap = switch_mac_default;
+#endif
+	else {
+		*((unsigned long *) &tmpaddr[0]) =
+			be32_to_cpu(readl(fep->enet_addr
+			+ FEC_ADDR_LOW / sizeof(unsigned long)));
+		*((unsigned short *) &tmpaddr[4]) =
+			be16_to_cpu(readl(fep->enet_addr
+			+ FEC_ADDR_HIGH / sizeof(unsigned long)) >> 16);
+		iap = &tmpaddr[0];
+	}
+
+	memcpy(dev->dev_addr, iap, ETH_ALEN);
+
+	/* Adjust MAC if using default MAC address */
+	if (iap == switch_mac_default) {
+		dev->dev_addr[ETH_ALEN-1] =
+			switch_mac_default[ETH_ALEN-1] + index;
+		index++;
+	}
+}
+
+static void switch_enable_phy_intr(void)
+{
+}
+
+static void switch_disable_phy_intr(void)
+{
+}
+
+static void switch_phy_ack_intr(void)
+{
+}
+
+static void switch_localhw_setup(void)
+{
+}
+
+static void switch_uncache(unsigned long addr)
+{
+}
+
+static void switch_platform_flush_cache(void)
+{
+}
+
+/*
+ * Calculate Galois Field Arithmetic CRC for Polynom x^8+x^2+x+1.
+ * It omits the final shift in of 8 zeroes a "normal" CRC would do
+ * (getting the remainder).
+ *
+ *  Examples (hexadecimal values):<br>
+ *   10-11-12-13-14-15  => CRC=0xc2
+ *   10-11-cc-dd-ee-00  => CRC=0xe6
+ *
+ *   param: pmacaddress
+ *          A 6-byte array with the MAC address.
+ *          The first byte is the first byte transmitted
+ *   return The 8-bit CRC in bits 7:0
+ */
+static int crc8_calc(unsigned char *pmacaddress)
+{
+	/* byte index */
+	int byt;
+	/* bit index */
+	int bit;
+	int inval;
+	int crc;
+	/* preset */
+	crc   = 0x12;
+	for (byt = 0; byt < 6; byt++) {
+		inval = (((int)pmacaddress[byt]) & 0xff);
+		/*
+		 * shift bit 0 to bit 8 so all our bits
+		 * travel through bit 8
+		 * (simplifies below calc)
+		 */
+		inval <<= 8;
+
+		for (bit = 0; bit < 8; bit++) {
+			/* next input bit comes into d7 after shift */
+			crc |= inval & 0x100;
+			if (crc & 0x01)
+				/* before shift  */
+				crc ^= 0x1c0;
+
+			crc >>= 1;
+			inval >>= 1;
+		}
+
+	}
+	/* upper bits are clean as we shifted in zeroes! */
+	return crc;
+}
+
+static void read_atable(struct switch_enet_private *fep,
+	int index,
+	unsigned long *read_lo, unsigned long *read_hi)
+{
+	unsigned long atable_base = (unsigned long)fep->hwentry;
+
+	*read_lo = readl(atable_base + (index<<3));
+	*read_hi = readl(atable_base + (index<<3) + 4);
+}
+
+static void write_atable(struct switch_enet_private *fep,
+	int index,
+	unsigned long write_lo, unsigned long write_hi)
+{
+	unsigned long atable_base = (unsigned long)fep->hwentry;
+
+	writel(write_lo, atable_base + (index<<3));
+	writel(write_hi, atable_base + (index<<3) + 4);
+}
+
+/* Read one element from the HW receive FIFO (Queue)
+ * if available and return it.
+ * return ms_HwPortInfo or null if no data is available
+ */
+static struct eswPortInfo *esw_portinfofifo_read(
+	struct switch_enet_private *fep)
+{
+	struct switch_t  *fecp;
+	unsigned long tmp;
+
+	fecp = fep->hwp;
+	if (fecp->ESW_LSR == 0) {
+		printk(KERN_ERR "%s: ESW_LSR = %lx\n",
+			__func__, fecp->ESW_LSR);
+		return NULL;
+	}
+	/* read word from FIFO */
+	g_info.maclo = fecp->ESW_LREC0;
+	/* but verify that we actually did so
+	 * (0=no data available)
+	 */
+	if (g_info.maclo == 0) {
+		printk(KERN_ERR "%s: mac lo %x\n",
+			__func__, g_info.maclo);
+		return NULL;
+	}
+	/* read 2nd word from FIFO */
+	tmp = fecp->ESW_LREC1;
+	g_info.machi = tmp & 0xffff;
+	g_info.hash  = (tmp >> 16) & 0xff;
+	g_info.port  = (tmp >> 24) & 0xf;
+
+	return &g_info;
+}
+
+
+/*
+ * Clear complete MAC Look Up Table
+ */
+static void esw_clear_atable(struct switch_enet_private *fep)
+{
+	int index;
+	for (index = 0; index < 2048; index++)
+		write_atable(fep, index, 0, 0);
+}
+
+/*
+ * pdates MAC address lookup table with a static entry
+ * Searches if the MAC address is already there in the block and replaces
+ * the older entry with new one. If MAC address is not there then puts a
+ * new entry in the first empty slot available in the block
+ *
+ * mac_addr Pointer to the array containing MAC address to
+ *          be put as static entry
+ * port     Port bitmask numbers to be added in static entry,
+ *          valid values are 1-7
+ * priority Priority for the static entry in table
+ *
+ * return 0 for a successful update else -1  when no slot available
+ */
+static int esw_update_atable_static(unsigned char *mac_addr,
+	unsigned int port, unsigned int priority,
+	struct switch_enet_private *fep)
+{
+	unsigned long block_index, entry, index_end;
+
+	unsigned long read_lo, read_hi;
+	unsigned long write_lo, write_hi;
+
+	write_lo = (unsigned long)((mac_addr[3] << 24) |
+			(mac_addr[2] << 16) |
+			(mac_addr[1] << 8) |
+			mac_addr[0]);
+	write_hi = (unsigned long)(0 |
+			(port << AT_SENTRY_PORTMASK_shift) |
+			(priority << AT_SENTRY_PRIO_shift) |
+			(AT_ENTRY_TYPE_STATIC << AT_ENTRY_TYPE_shift) |
+			(AT_ENTRY_RECORD_VALID << AT_ENTRY_VALID_shift) |
+			(mac_addr[5] << 8) | (mac_addr[4]));
+
+	block_index = GET_BLOCK_PTR(crc8_calc(mac_addr));
+	index_end = block_index + ATABLE_ENTRY_PER_SLOT;
+	/* Now search all the entries in the selected block */
+	for (entry = block_index; entry < index_end; entry++) {
+		read_atable(fep, entry, &read_lo, &read_hi);
+		/*
+		 * MAC address matched, so update the
+		 * existing entry
+		 * even if its a dynamic one
+		 */
+		if ((read_lo == write_lo) &&
+			((read_hi & 0x0000ffff) ==
+			 (write_hi & 0x0000ffff))) {
+			write_atable(fep, entry, write_lo, write_hi);
+			return 0;
+		} else if (!(read_hi & (1 << 16))) {
+			/*
+			 * Fill this empty slot (valid bit zero),
+			 * assuming no holes in the block
+			 */
+			write_atable(fep, entry, write_lo, write_hi);
+			fep->atCurrEntries++;
+			return 0;
+		}
+	}
+
+	/* No space available for this static entry */
+	return -1;
+}
+
+static int esw_update_atable_dynamic1(unsigned long write_lo,
+	unsigned long write_hi, int block_index,
+	unsigned int port, unsigned int currTime,
+	struct switch_enet_private *fep)
+{
+	unsigned long entry, index_end;
+	unsigned long read_lo, read_hi;
+	unsigned long tmp;
+	int time, timeold, indexold;
+
+	/* prepare update port and timestamp */
+	tmp = AT_ENTRY_RECORD_VALID << AT_ENTRY_VALID_shift;
+	tmp |= AT_ENTRY_TYPE_DYNAMIC << AT_ENTRY_TYPE_shift;
+	tmp |= currTime << AT_DENTRY_TIME_shift;
+	tmp |= port << AT_DENTRY_PORT_shift;
+	tmp |= write_hi;
+
+	/*
+	* linear search through all slot
+	* entries and update if found
+	*/
+	index_end = block_index + ATABLE_ENTRY_PER_SLOT;
+	/* Now search all the entries in the selected block */
+	for (entry = block_index; entry < index_end; entry++) {
+		read_atable(fep, entry, &read_lo, &read_hi);
+		if ((read_lo == write_lo) &&
+			((read_hi & 0x0000ffff) ==
+			(write_hi & 0x0000ffff))) {
+			/* found correct address,
+			 * update timestamp.
+			 */
+			write_atable(fep, entry, write_lo, tmp);
+			return 0;
+		} else if (!(read_hi & (1 << 16))) {
+			/* slot is empty, then use it
+			 * for new entry
+			 * Note: There are no holes,
+			 * therefore cannot be any
+			 * more that need to be compared.
+			 */
+			write_atable(fep, entry, write_lo, tmp);
+			/* statistics (we do it between writing
+			 *  .hi an .lo due to
+			 * hardware limitation...
+			 */
+			fep->atCurrEntries++;
+			/* newly inserted */
+			return 1;
+		}
+	}
+
+	/*
+	 * no more entry available in block ...
+	 * overwrite oldest
+	 */
+	timeold = 0;
+	indexold = 0;
+	for (entry = block_index; entry < index_end; entry++) {
+		read_atable(fep, entry, &read_lo, &read_hi);
+		time = AT_EXTRACT_TIMESTAMP(read_hi);
+		printk(KERN_ERR "%s : time %x currtime %x\n",
+			__func__, time, currTime);
+		time = TIMEDELTA(currTime, time);
+		if (time > timeold) {
+			/* is it older ? */
+			timeold = time;
+			indexold = entry;
+		}
+	}
+
+	write_atable(fep, indexold, write_lo, tmp);
+	/*
+	 * Statistics (do it inbetween
+	 *writing to .lo and .hi
+	 */
+	fep->atBlockOverflows++;
+	printk(KERN_ERR "%s update time, atBlockOverflows %x\n",
+		__func__, fep->atBlockOverflows);
+	/* newly inserted */
+	return 1;
+}
+
+/* dynamicms MAC address table learn and migration */
+static int esw_atable_dynamicms_learn_migration(
+	struct switch_enet_private *fep,
+	int currTime)
+{
+	struct eswPortInfo *pESWPortInfo;
+	int index;
+	int inserted = 0;
+
+	pESWPortInfo = esw_portinfofifo_read(fep);
+	/* Anything to learn */
+	if (pESWPortInfo != 0) {
+		/* get block index from lookup table */
+		index = GET_BLOCK_PTR(pESWPortInfo->hash);
+		inserted = esw_update_atable_dynamic1(
+			pESWPortInfo->maclo,
+			pESWPortInfo->machi, index,
+			pESWPortInfo->port, currTime, fep);
+	} else {
+		printk(KERN_ERR "%s:hav invalidate learned data \n", __func__);
+		return -1;
+	}
+
+	return 0;
+
+}
+
+/*
+ * esw_forced_forward
+ * The frame is forwared to the forced destination ports.
+ * It only replace the MAC lookup function,
+ * all other filtering(eg.VLAN verification) act as normal
+ */
+static int esw_forced_forward(struct switch_enet_private *fep,
+	int port1, int port2, int enable)
+{
+	unsigned long tmp = 0;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	/* Enable Forced forwarding for port num */
+	if ((port1 == 1) && (port2 == 1))
+		tmp |= MCF_ESW_P0FFEN_FD(3);
+	else if (port1 == 1)
+		/* Enable Forced forwarding for port 1 only */
+		tmp |= MCF_ESW_P0FFEN_FD(1);
+	else if (port2 == 1)
+		/* Enable Forced forwarding for port 2 only */
+		tmp |= MCF_ESW_P0FFEN_FD(2);
+	else {
+		printk(KERN_ERR "%s:do not support "
+			"the forced forward mode"
+			"port1 %x port2 %x\n",
+			__func__, port1, port2);
+		return -1;
+	}
+
+	if (enable == 1)
+		tmp |= MCF_ESW_P0FFEN_FEN;
+	else if (enable == 0)
+		tmp &= ~MCF_ESW_P0FFEN_FEN;
+	else {
+		printk(KERN_ERR "%s: the enable %x is error\n",
+			__func__, enable);
+		return -2;
+	}
+
+	fecp->ESW_P0FFEN = tmp;
+	return 0;
+}
+
+static int esw_get_forced_forward(
+	struct switch_enet_private *fep,
+	unsigned long *ulForceForward)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulForceForward = fecp->ESW_P0FFEN;
+#ifdef DEBUG_FORCED_FORWARD
+	printk(KERN_INFO "%s  ESW_P0FFEN %#lx\n",
+		__func__, fecp->ESW_P0FFEN);
+#endif
+	return 0;
+}
+
+static void esw_get_port_enable(
+	struct switch_enet_private *fep,
+	unsigned long *ulPortEnable)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulPortEnable = fecp->ESW_PER;
+#ifdef DEBUG_PORT_ENABLE
+	printk(KERN_INFO "%s  fecp->ESW_PER %#lx\n",
+		__func__, fecp->ESW_PER);
+#endif
+}
+/*
+ * enable or disable port n tx or rx
+ * tx_en 0 disable port n tx
+ * tx_en 1 enable  port n tx
+ * rx_en 0 disbale port n rx
+ * rx_en 1 enable  port n rx
+ */
+static int esw_port_enable_config(struct switch_enet_private *fep,
+	int port, int tx_en, int rx_en)
+{
+	unsigned long tmp = 0;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	tmp = fecp->ESW_PER;
+	if (tx_en == 1) {
+		if (port == 0)
+			tmp |= MCF_ESW_PER_TE0;
+		else if (port == 1)
+			tmp |= MCF_ESW_PER_TE1;
+		else if (port == 2)
+			tmp |= MCF_ESW_PER_TE2;
+		else {
+			printk(KERN_ERR "%s:do not support the"
+				" port %x tx enable %d\n",
+				__func__, port, tx_en);
+			return -1;
+		}
+	} else if (tx_en == 0) {
+		if (port == 0)
+			tmp &= (~MCF_ESW_PER_TE0);
+		else if (port == 1)
+			tmp &= (~MCF_ESW_PER_TE1);
+		else if (port == 2)
+			tmp &= (~MCF_ESW_PER_TE2);
+		else {
+			printk(KERN_ERR "%s:do not support "
+				"the port %x tx disable %d\n",
+				__func__, port, tx_en);
+			return -2;
+		}
+	} else {
+		printk(KERN_ERR "%s:do not support the port %x"
+			" tx op value %x\n",
+			__func__, port, tx_en);
+		return -3;
+	}
+
+	if (rx_en == 1) {
+		if (port == 0)
+			tmp |= MCF_ESW_PER_RE0;
+		else if (port == 1)
+			tmp |= MCF_ESW_PER_RE1;
+		else if (port == 2)
+			tmp |= MCF_ESW_PER_RE2;
+		else {
+			printk(KERN_ERR "%s:do not support the "
+				"port %x rx enable %d\n",
+				__func__, port, tx_en);
+			return -4;
+		}
+	} else if (rx_en == 0) {
+		if (port == 0)
+			tmp &= (~MCF_ESW_PER_RE0);
+		else if (port == 1)
+			tmp &= (~MCF_ESW_PER_RE1);
+		else if (port == 2)
+			tmp &= (~MCF_ESW_PER_RE2);
+		else {
+			printk(KERN_ERR "%s:do not support the "
+				"port %x rx disable %d\n",
+				__func__, port, rx_en);
+			return -5;
+		}
+	} else {
+		printk(KERN_ERR "%s:do not support the port %x"
+			" rx op value %x\n",
+			__func__, port, tx_en);
+		return -6;
+	}
+
+	fecp->ESW_PER = tmp;
+	return 0;
+}
+
+
+static void esw_get_port_broadcast(
+	struct switch_enet_private *fep,
+	unsigned long *ulPortBroadcast)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulPortBroadcast = fecp->ESW_DBCR;
+#ifdef DEBUG_PORT_BROADCAST
+	printk(KERN_INFO "%s  fecp->ESW_DBCR %#lx\n",
+		__func__, fecp->ESW_DBCR);
+#endif
+}
+
+static int esw_port_broadcast_config(
+	struct switch_enet_private *fep,
+	int port, int enable)
+{
+	unsigned long tmp = 0;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if ((port > 2) || (port < 0)) {
+		printk(KERN_ERR "%s:do not support the port %x"
+			" default broadcast\n",
+			__func__, port);
+		return -1;
+	}
+
+	tmp = fecp->ESW_DBCR;
+	if (enable == 1) {
+		if (port == 0)
+			tmp |= MCF_ESW_DBCR_P0;
+		else if (port == 1)
+			tmp |= MCF_ESW_DBCR_P1;
+		else if (port == 2)
+			tmp |= MCF_ESW_DBCR_P2;
+	} else if (enable == 0) {
+		if (port == 0)
+			tmp &= ~MCF_ESW_DBCR_P0;
+		else if (port == 1)
+			tmp &= ~MCF_ESW_DBCR_P1;
+		else if (port == 2)
+			tmp &= ~MCF_ESW_DBCR_P2;
+	}
+
+	fecp->ESW_DBCR = tmp;
+	return 0;
+}
+
+
+static void esw_get_port_multicast(
+	struct switch_enet_private *fep,
+	unsigned long *ulPortMulticast)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulPortMulticast = fecp->ESW_DMCR;
+#ifdef DEBUG_PORT_MULTICAST
+	printk(KERN_INFO "%s  fecp->ESW_DMCR %#lx\n",
+		__func__, fecp->ESW_DMCR);
+#endif
+}
+
+static int esw_port_multicast_config(
+	struct switch_enet_private *fep,
+	int port, int enable)
+{
+	unsigned long tmp = 0;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if ((port > 2) || (port < 0)) {
+		printk(KERN_ERR "%s:do not support the port %x"
+			" default broadcast\n",
+			__func__, port);
+		return -1;
+	}
+
+	tmp = fecp->ESW_DMCR;
+	if (enable == 1) {
+		if (port == 0)
+			tmp |= MCF_ESW_DMCR_P0;
+		else if (port == 1)
+			tmp |= MCF_ESW_DMCR_P1;
+		else if (port == 2)
+			tmp |= MCF_ESW_DMCR_P2;
+	} else if (enable == 0) {
+		if (port == 0)
+			tmp &= ~MCF_ESW_DMCR_P0;
+		else if (port == 1)
+			tmp &= ~MCF_ESW_DMCR_P1;
+		else if (port == 2)
+			tmp &= ~MCF_ESW_DMCR_P2;
+	}
+
+	fecp->ESW_DMCR = tmp;
+	return 0;
+}
+
+
+static void esw_get_port_blocking(
+	struct switch_enet_private *fep,
+	unsigned long *ulPortBlocking)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulPortBlocking = (fecp->ESW_BKLR & 0x00ff);
+#ifdef DEBUG_PORT_BLOCKING
+	printk(KERN_INFO "%s  fecp->ESW_BKLR %#lx\n",
+		__func__, fecp->ESW_BKLR);
+#endif
+}
+
+static int esw_port_blocking_config(
+	struct switch_enet_private *fep,
+	int port, int enable)
+{
+	unsigned long tmp = 0;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if ((port > 2) || (port < 0)) {
+		printk(KERN_ERR "%s:do not support the port %x"
+			" default broadcast\n",
+			__func__, port);
+		return -1;
+	}
+
+	tmp = fecp->ESW_BKLR;
+	if (enable == 1) {
+		if (port == 0)
+			tmp |= MCF_ESW_BKLR_BE0;
+		else if (port == 1)
+			tmp |= MCF_ESW_BKLR_BE1;
+		else if (port == 2)
+			tmp |= MCF_ESW_BKLR_BE2;
+	} else if (enable == 0) {
+		if (port == 0)
+			tmp &= ~MCF_ESW_BKLR_BE0;
+		else if (port == 1)
+			tmp &= ~MCF_ESW_BKLR_BE1;
+		else if (port == 2)
+			tmp &= ~MCF_ESW_BKLR_BE2;
+	}
+
+	fecp->ESW_BKLR = tmp;
+	return 0;
+}
+
+
+static void esw_get_port_learning(
+	struct switch_enet_private *fep,
+	unsigned long *ulPortLearning)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulPortLearning = (fecp->ESW_BKLR & 0xff00) >> 16;
+#ifdef DEBUG_PORT_LEARNING
+	printk(KERN_INFO "%s  fecp->ESW_BKLR %#lx\n",
+		__func__, fecp->ESW_BKLR);
+#endif
+}
+
+static int esw_port_learning_config(
+	struct switch_enet_private *fep,
+	int port, int disable)
+{
+	unsigned long tmp = 0;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if ((port > 2) || (port < 0)) {
+		printk(KERN_ERR "%s:do not support the port %x"
+			" default broadcast\n",
+			__func__, port);
+		return -1;
+	}
+
+	tmp = fecp->ESW_BKLR;
+	if (disable == 1) {
+		fep->learning_irqhandle_enable = 0;
+		if (port == 0)
+			tmp |= MCF_ESW_BKLR_LD0;
+		else if (port == 1)
+			tmp |= MCF_ESW_BKLR_LD1;
+		else if (port == 2)
+			tmp |= MCF_ESW_BKLR_LD2;
+	} else if (disable == 0) {
+		fep->learning_irqhandle_enable = 1;
+		fecp->switch_imask |= MCF_ESW_IMR_LRN;
+		if (port == 0)
+			tmp &= ~MCF_ESW_BKLR_LD0;
+		else if (port == 1)
+			tmp &= ~MCF_ESW_BKLR_LD1;
+		else if (port == 2)
+			tmp &= ~MCF_ESW_BKLR_LD2;
+	}
+
+	fecp->ESW_BKLR = tmp;
+#ifdef DEBUG_PORT_LEARNING
+	printk(KERN_INFO "%s  ESW_BKLR %#lx, switch_imask %#lx\n",
+		__func__, fecp->ESW_BKLR, fecp->switch_imask);
+#endif
+	return 0;
+}
+
+/*
+ * Checks IP Snoop options of handling the snooped frame.
+ * mode 0 : The snooped frame is forward only to management port
+ * mode 1 : The snooped frame is copy to management port and
+ *              normal forwarding is checked.
+ * mode 2 : The snooped frame is discarded.
+ * mode 3 : Disable the ip snoop function
+ * ip_header_protocol : the IP header protocol field
+ */
+static int esw_ip_snoop_config(struct switch_enet_private *fep,
+	int num, int mode, unsigned long ip_header_protocol)
+{
+	struct switch_t  *fecp;
+	unsigned long tmp = 0, protocol_type = 0;
+
+	fecp = fep->hwp;
+	/* Config IP Snooping */
+	if (mode == 0) {
+		/* Enable IP Snooping */
+		tmp = MCF_ESW_IPSNP_EN;
+		tmp |= MCF_ESW_IPSNP_MODE(0);/*For Forward*/
+	} else if (mode == 1) {
+		/* Enable IP Snooping */
+		tmp = MCF_ESW_IPSNP_EN;
+		/*For Forward and copy_to_mangmnt_port*/
+		tmp |= MCF_ESW_IPSNP_MODE(1);
+	} else if (mode == 2) {
+		/* Enable IP Snooping */
+		tmp = MCF_ESW_IPSNP_EN;
+		tmp |= MCF_ESW_IPSNP_MODE(2);/*discard*/
+	} else if (mode == 3) {
+		/* disable IP Snooping */
+		tmp = MCF_ESW_IPSNP_EN;
+		tmp &= ~MCF_ESW_IPSNP_EN;
+	} else {
+		printk(KERN_ERR "%s: the mode %x "
+			"we do not support\n", __func__, mode);
+		return -1;
+	}
+
+	protocol_type = ip_header_protocol;
+	fecp->ESW_IPSNP[num] =
+		tmp | MCF_ESW_IPSNP_PROTOCOL(protocol_type);
+	printk(KERN_INFO "%s : ESW_IPSNP[%d] %#lx\n",
+		__func__, num, fecp->ESW_IPSNP[num]);
+	return 0;
+}
+
+static void esw_get_ip_snoop_config(
+	struct switch_enet_private *fep,
+	unsigned long *ulpESW_IPSNP)
+{
+	int i;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	for (i = 0; i < 8; i++)
+		*(ulpESW_IPSNP + i) = fecp->ESW_IPSNP[i];
+#ifdef DEBUG_IP_SNOOP
+	printk(KERN_INFO "%s  ", __func__);
+	for (i = 0; i < 8; i++)
+		printk(KERN_INFO " reg(%d) %#lx", fecp->ESW_IPSNP[i]);
+	printk(KERN_INFO "\n");
+#endif
+
+}
+/*
+ * Checks TCP/UDP Port Snoop options of handling the snooped frame.
+ * mode 0 : The snooped frame is forward only to management port
+ * mode 1 : The snooped frame is copy to management port and
+ *              normal forwarding is checked.
+ * mode 2 : The snooped frame is discarded.
+ * compare_port : port number in the TCP/UDP header
+ * compare_num 1: TCP/UDP source port number is compared
+ * compare_num 2: TCP/UDP destination port number is compared
+ * compare_num 3: TCP/UDP source and destination port number is compared
+ */
+static int esw_tcpudp_port_snoop_config(struct switch_enet_private *fep,
+	int num, int mode, int compare_port, int compare_num)
+{
+	struct switch_t  *fecp;
+	unsigned long tmp = 0;
+
+	fecp = fep->hwp;
+
+	/* Enable TCP/UDP port Snooping */
+	tmp = MCF_ESW_PSNP_EN;
+	if (mode == 0)
+		tmp |= MCF_ESW_PSNP_MODE(0);/* For Forward */
+	else if (mode == 1)/*For Forward and copy_to_mangmnt_port*/
+		tmp |= MCF_ESW_PSNP_MODE(1);
+	else if (mode == 2)
+		tmp |= MCF_ESW_PSNP_MODE(2);/* discard */
+	else if (mode == 3) /* disable the port function */
+		tmp &= (~MCF_ESW_PSNP_EN);
+	else {
+		printk(KERN_ERR "%s: the mode %x we do not support\n",
+			__func__, mode);
+		return -1;
+	}
+
+	if (compare_num == 1)
+		tmp |= MCF_ESW_PSNP_CS;
+	else if (compare_num == 2)
+		tmp |= MCF_ESW_PSNP_CD;
+	else if (compare_num == 3)
+		tmp |= MCF_ESW_PSNP_CD | MCF_ESW_PSNP_CS;
+	else {
+		printk(KERN_ERR "%s: the compare port address %x"
+			" we do not support\n",
+			__func__, compare_num);
+		return -1;
+	}
+
+	fecp->ESW_PSNP[num] = tmp |
+		MCF_ESW_PSNP_PORT_COMPARE(compare_port);
+	printk(KERN_INFO "ESW_PSNP[%d] %#lx\n",
+			num, fecp->ESW_PSNP[num]);
+	return 0;
+}
+
+static void esw_get_tcpudp_port_snoop_config(
+	struct switch_enet_private *fep,
+	unsigned long *ulpESW_PSNP)
+{
+	int i;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	for (i = 0; i < 8; i++)
+		*(ulpESW_PSNP + i) = fecp->ESW_PSNP[i];
+#ifdef DEBUG_TCPUDP_PORT_SNOOP
+	 printk(KERN_INFO "%s  ", __func__);
+	 for (i = 0; i < 8; i++)
+		printk(KERN_INFO " reg(%d) %#lx", fecp->ESW_PSNP[i]);
+	 printk(KERN_INFO "\n");
+#endif
+
+}
+
+static void esw_get_port_mirroring(
+	struct switch_enet_private *fep,
+	struct eswIoctlPortMirrorStatus *pPortMirrorStatus)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	pPortMirrorStatus->ESW_MCR    = fecp->ESW_MCR;
+	pPortMirrorStatus->ESW_EGMAP  = fecp->ESW_EGMAP;
+	pPortMirrorStatus->ESW_INGMAP = fecp->ESW_INGMAP;
+	pPortMirrorStatus->ESW_INGSAL = fecp->ESW_INGSAL;
+	pPortMirrorStatus->ESW_INGSAH = fecp->ESW_INGSAH;
+	pPortMirrorStatus->ESW_INGDAL = fecp->ESW_INGDAL;
+	pPortMirrorStatus->ESW_INGDAH = fecp->ESW_INGDAH;
+	pPortMirrorStatus->ESW_ENGSAL = fecp->ESW_ENGSAL;
+	pPortMirrorStatus->ESW_ENGSAH = fecp->ESW_ENGSAH;
+	pPortMirrorStatus->ESW_ENGDAL = fecp->ESW_ENGDAL;
+	pPortMirrorStatus->ESW_ENGDAH = fecp->ESW_ENGDAH;
+	pPortMirrorStatus->ESW_MCVAL  = fecp->ESW_MCVAL;
+#ifdef DEBUG_PORT_MIRROR
+	printk(KERN_INFO "%s : ESW_MCR %#lx, ESW_EGMAP %#lx\n"
+		"ESW_INGMAP %#lx, ESW_INGSAL %#lx, "
+		"ESW_INGSAH %#lx ESW_INGDAL %#lx, ESW_INGDAH %#lx\n"
+		"ESW_ENGSAL %#lx, ESW_ENGSAH%#lx, ESW_ENGDAL %#lx,"
+		"ESW_ENGDAH %#lx, ESW_MCVAL %#lx\n",
+		__func__, fecp->ESW_MCR, fecp->ESW_EGMAP, fecp->ESW_INGMAP,
+		fecp->ESW_INGSAL, fecp->ESW_INGSAH, fecp->ESW_INGDAL,
+		fecp->ESW_INGDAH, fecp->ESW_ENGSAL, fecp->ESW_ENGSAH,
+		fecp->ESW_ENGDAL, fecp->ESW_ENGDAH, fecp->ESW_MCVAL);
+#endif
+}
+
+static int esw_port_mirroring_config(struct switch_enet_private *fep,
+	int mirror_port, int port, int mirror_enable,
+	unsigned char *src_mac, unsigned char *des_mac,
+	int egress_en, int ingress_en,
+	int egress_mac_src_en, int egress_mac_des_en,
+	int ingress_mac_src_en, int ingress_mac_des_en)
+{
+	struct switch_t  *fecp;
+	unsigned long tmp = 0;
+
+	fecp = fep->hwp;
+
+	/*mirroring config*/
+	tmp = 0;
+	if (egress_en == 1) {
+		tmp |= MCF_ESW_MCR_EGMAP;
+		if (port == 0)
+			fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG0;
+		else if (port == 1)
+			fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG1;
+		else if (port == 2)
+			fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG2;
+		else {
+			printk(KERN_ERR "%s: the port %x we do not support\n",
+					__func__, port);
+			return -1;
+		}
+	} else if (egress_en == 0) {
+		tmp &= (~MCF_ESW_MCR_EGMAP);
+	} else {
+		printk(KERN_ERR "%s: egress_en %x we do not support\n",
+			__func__, egress_en);
+		return -1;
+	}
+
+	if (ingress_en == 1) {
+		tmp |= MCF_ESW_MCR_INGMAP;
+		if (port == 0)
+			fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING0;
+		else if (port == 1)
+			fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING1;
+		else if (port == 2)
+			fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING2;
+		else {
+			printk(KERN_ERR "%s: the port %x we do not support\n",
+				__func__, port);
+			return -1;
+		}
+	} else if (ingress_en == 0) {
+		tmp &= ~MCF_ESW_MCR_INGMAP;
+	} else{
+		printk(KERN_ERR "%s: ingress_en %x we do not support\n",
+				__func__, ingress_en);
+		return -1;
+	}
+
+	if (egress_mac_src_en == 1) {
+		tmp |= MCF_ESW_MCR_EGSA;
+		fecp->ESW_ENGSAH = (src_mac[5] << 8) | (src_mac[4]);
+		fecp->ESW_ENGSAL = (unsigned long)((src_mac[3] << 24) |
+					(src_mac[2] << 16) |
+					(src_mac[1] << 8) |
+					src_mac[0]);
+	} else if (egress_mac_src_en == 0) {
+		tmp &= ~MCF_ESW_MCR_EGSA;
+	} else {
+		printk(KERN_ERR "%s: egress_mac_src_en  %x we do not support\n",
+			__func__, egress_mac_src_en);
+		return -1;
+	}
+
+	if (egress_mac_des_en == 1) {
+		tmp |= MCF_ESW_MCR_EGDA;
+		fecp->ESW_ENGDAH = (des_mac[5] << 8) | (des_mac[4]);
+		fecp->ESW_ENGDAL = (unsigned long)((des_mac[3] << 24) |
+					(des_mac[2] << 16) |
+					(des_mac[1] << 8) |
+					des_mac[0]);
+	} else if (egress_mac_des_en == 0) {
+		tmp &= ~MCF_ESW_MCR_EGDA;
+	} else {
+		printk(KERN_ERR "%s: egress_mac_des_en  %x we do not support\n",
+			__func__, egress_mac_des_en);
+		return -1;
+	}
+
+	if (ingress_mac_src_en == 1) {
+		tmp |= MCF_ESW_MCR_INGSA;
+		fecp->ESW_INGSAH = (src_mac[5] << 8) | (src_mac[4]);
+		fecp->ESW_INGSAL = (unsigned long)((src_mac[3] << 24) |
+					(src_mac[2] << 16) |
+					(src_mac[1] << 8) |
+					src_mac[0]);
+	} else if (ingress_mac_src_en == 0) {
+		tmp &= ~MCF_ESW_MCR_INGSA;
+	} else {
+		printk(KERN_ERR "%s: ingress_mac_src_en  %x we do not support\n",
+			__func__, ingress_mac_src_en);
+		return -1;
+	}
+
+	if (ingress_mac_des_en == 1) {
+		tmp |= MCF_ESW_MCR_INGDA;
+		fecp->ESW_INGDAH = (des_mac[5] << 8) | (des_mac[4]);
+		fecp->ESW_INGDAL = (unsigned long)((des_mac[3] << 24) |
+					(des_mac[2] << 16) |
+					(des_mac[1] << 8) |
+					des_mac[0]);
+	} else if (ingress_mac_des_en == 0) {
+		tmp &= ~MCF_ESW_MCR_INGDA;
+	} else {
+		printk(KERN_ERR "%s: ingress_mac_des_en  %x we do not support\n",
+			__func__, ingress_mac_des_en);
+		return -1;
+	}
+
+	/*------------------------------------------------------------------*/
+	if (mirror_enable == 1)
+		tmp |= MCF_ESW_MCR_MEN | MCF_ESW_MCR_PORT(mirror_port);
+	else if (mirror_enable == 0)
+		tmp &= ~MCF_ESW_MCR_MEN;
+	else
+		printk(KERN_ERR "%s: the mirror enable %x is error\n",
+			__func__, mirror_enable);
+
+
+	fecp->ESW_MCR = tmp;
+	printk(KERN_INFO "%s : MCR %#lx, EGMAP %#lx, INGMAP %#lx;\n"
+		"ENGSAH %#lx, ENGSAL %#lx ;ENGDAH %#lx, ENGDAL %#lx;\n"
+		"INGSAH %#lx, INGSAL %#lx\n;INGDAH %#lx, INGDAL %#lx;\n",
+		__func__, fecp->ESW_MCR, fecp->ESW_EGMAP, fecp->ESW_INGMAP,
+		fecp->ESW_ENGSAH, fecp->ESW_ENGSAL,
+		fecp->ESW_ENGDAH, fecp->ESW_ENGDAL,
+		fecp->ESW_INGSAH, fecp->ESW_INGSAL,
+		fecp->ESW_INGDAH, fecp->ESW_INGDAL);
+	return 0;
+}
+
+static void esw_get_vlan_verification(
+	struct switch_enet_private *fep,
+	unsigned long *ulValue)
+{
+	struct switch_t  *fecp;
+	fecp = fep->hwp;
+	*ulValue = fecp->ESW_VLANV;
+
+#ifdef DEBUG_VLAN_VERIFICATION_CONFIG
+	printk(KERN_INFO "%s: ESW_VLANV %#lx\n",
+		__func__, fecp->ESW_VLANV);
+#endif
+}
+
+static int esw_set_vlan_verification(
+	struct switch_enet_private *fep, int port,
+	int vlan_domain_verify_en,
+	int vlan_discard_unknown_en)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	if ((port < 0) || (port > 2)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -1;
+	}
+
+	if (vlan_domain_verify_en == 1) {
+		if (port == 0)
+			fecp->ESW_VLANV |= MCF_ESW_VLANV_VV0;
+		else if (port == 1)
+			fecp->ESW_VLANV |= MCF_ESW_VLANV_VV1;
+		else if (port == 2)
+			fecp->ESW_VLANV |= MCF_ESW_VLANV_VV2;
+	} else if (vlan_domain_verify_en == 0) {
+		if (port == 0)
+			fecp->ESW_VLANV &= ~MCF_ESW_VLANV_VV0;
+		else if (port == 1)
+			fecp->ESW_VLANV &= ~MCF_ESW_VLANV_VV1;
+		else if (port == 2)
+			fecp->ESW_VLANV &= ~MCF_ESW_VLANV_VV2;
+	} else {
+		printk(KERN_INFO "%s: donot support "
+			"vlan_domain_verify %x\n",
+			__func__, vlan_domain_verify_en);
+		return -2;
+	}
+
+	if (vlan_discard_unknown_en == 1) {
+		if (port == 0)
+			fecp->ESW_VLANV |= MCF_ESW_VLANV_DU0;
+		else if (port == 1)
+			fecp->ESW_VLANV |= MCF_ESW_VLANV_DU1;
+		else if (port == 2)
+			fecp->ESW_VLANV |= MCF_ESW_VLANV_DU2;
+	} else if (vlan_discard_unknown_en == 0) {
+		if (port == 0)
+			fecp->ESW_VLANV &= ~MCF_ESW_VLANV_DU0;
+		else if (port == 1)
+			fecp->ESW_VLANV &= ~MCF_ESW_VLANV_DU1;
+		else if (port == 2)
+			fecp->ESW_VLANV &= ~MCF_ESW_VLANV_DU2;
+	} else {
+		printk(KERN_INFO "%s: donot support "
+			"vlan_discard_unknown %x\n",
+			__func__, vlan_discard_unknown_en);
+		return -3;
+	}
+
+#ifdef DEBUG_VLAN_VERIFICATION_CONFIG
+	printk(KERN_INFO "%s: ESW_VLANV %#lx\n",
+		__func__, fecp->ESW_VLANV);
+#endif
+	return 0;
+}
+
+static void esw_get_vlan_resolution_table(
+	struct switch_enet_private *fep,
+	int vlan_domain_num,
+	unsigned long *ulValue)
+{
+	struct switch_t  *fecp;
+	fecp = fep->hwp;
+
+	*ulValue = fecp->ESW_VRES[vlan_domain_num];
+
+#ifdef DEBUG_VLAN_DOMAIN_TABLE
+	printk(KERN_INFO "%s: ESW_VRES[%d] = %#lx\n",
+		__func__, vlan_domain_num,
+		fecp->ESW_VRES[vlan_domain_num]);
+#endif
+}
+
+int esw_set_vlan_resolution_table(
+	struct switch_enet_private *fep,
+	unsigned short port_vlanid,
+	int vlan_domain_num,
+	int vlan_domain_port)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	if ((vlan_domain_num < 0)
+		|| (vlan_domain_num > 31)) {
+		printk(KERN_ERR "%s: do not support the "
+			"vlan_domain_num %d\n",
+		__func__, vlan_domain_num);
+		return -1;
+	}
+
+	if ((vlan_domain_port < 0)
+		|| (vlan_domain_port > 7)) {
+		printk(KERN_ERR "%s: do not support the "
+			"vlan_domain_port %d\n",
+			__func__, vlan_domain_port);
+		return -2;
+	}
+
+	fecp->ESW_VRES[vlan_domain_num] =
+		MCF_ESW_VRES_VLANID(port_vlanid)
+		| vlan_domain_port;
+
+#ifdef DEBUG_VLAN_DOMAIN_TABLE
+	printk(KERN_INFO "%s: ESW_VRES[%d] = %#lx\n",
+		__func__, vlan_domain_num,
+		fecp->ESW_VRES[vlan_domain_num]);
+#endif
+	return 0;
+}
+
+static void esw_get_vlan_input_config(
+	struct switch_enet_private *fep,
+	struct eswIoctlVlanInputStatus *pVlanInputConfig)
+{
+	struct switch_t  *fecp;
+	int i;
+
+	fecp = fep->hwp;
+	for (i = 0; i < 3; i++)
+		pVlanInputConfig->ESW_PID[i] = fecp->ESW_PID[i];
+
+	pVlanInputConfig->ESW_VLANV  = fecp->ESW_VLANV;
+	pVlanInputConfig->ESW_VIMSEL = fecp->ESW_VIMSEL;
+	pVlanInputConfig->ESW_VIMEN  = fecp->ESW_VIMEN;
+
+	for (i = 0; i < 32; i++)
+		pVlanInputConfig->ESW_VRES[i] = fecp->ESW_VRES[i];
+#ifdef DEBUG_VLAN_INTPUT_CONFIG
+	printk(KERN_INFO "%s: ESW_VLANV %#lx, ESW_VIMSEL %#lx, "
+		"ESW_VIMEN %#lx, ESW_PID[0], ESW_PID[1] %#lx, "
+		"ESW_PID[2] %#lx", __func__,
+		fecp->ESW_VLANV, fecp->ESW_VIMSEL, fecp->ESW_VIMEN,
+		fecp->ESW_PID[0], fecp->ESW_PID[1], fecp->ESW_PID[2]);
+#endif
+}
+
+
+static int esw_vlan_input_process(struct switch_enet_private *fep,
+	int port, int mode, unsigned short port_vlanid,
+	int vlan_verify_en, int vlan_domain_num,
+	int vlan_domain_port)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	/*we only support mode1 mode2 mode3 mode4*/
+	if ((mode < 0) || (mode > 3)) {
+		printk(KERN_ERR "%s: do not support the"
+			" VLAN input processing mode %d\n",
+			__func__, mode);
+		return -1;
+	}
+
+	if ((port < 0) || (port > 3)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, mode);
+		return -2;
+	}
+
+	if ((vlan_verify_en == 1) && ((vlan_domain_num < 0)
+		|| (vlan_domain_num > 32))) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, mode);
+		return -3;
+	}
+
+	fecp->ESW_PID[port] = MCF_ESW_PID_VLANID(port_vlanid);
+	if (port == 0) {
+		if (vlan_verify_en == 1)
+			fecp->ESW_VRES[vlan_domain_num] =
+				MCF_ESW_VRES_VLANID(port_vlanid)
+				| MCF_ESW_VRES_P0;
+
+		fecp->ESW_VIMEN |= MCF_ESW_VIMEN_EN0;
+		fecp->ESW_VIMSEL |= MCF_ESW_VIMSEL_IM0(mode);
+	} else if (port == 1) {
+		if (vlan_verify_en == 1)
+			fecp->ESW_VRES[vlan_domain_num] =
+				MCF_ESW_VRES_VLANID(port_vlanid)
+				| MCF_ESW_VRES_P1;
+
+		fecp->ESW_VIMEN |= MCF_ESW_VIMEN_EN1;
+		fecp->ESW_VIMSEL |= MCF_ESW_VIMSEL_IM1(mode);
+	} else if (port == 2) {
+		if (vlan_verify_en == 1)
+			fecp->ESW_VRES[vlan_domain_num] =
+				MCF_ESW_VRES_VLANID(port_vlanid)
+				| MCF_ESW_VRES_P2;
+
+		fecp->ESW_VIMEN |= MCF_ESW_VIMEN_EN2;
+		fecp->ESW_VIMSEL |= MCF_ESW_VIMSEL_IM2(mode);
+	} else {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -2;
+	}
+
+	return 0;
+}
+
+static void esw_get_vlan_output_config(struct switch_enet_private *fep,
+	unsigned long *ulVlanOutputConfig)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	*ulVlanOutputConfig = fecp->ESW_VOMSEL;
+#ifdef DEBUG_VLAN_OUTPUT_CONFIG
+	printk(KERN_INFO "%s: ESW_VOMSEL %#lx", __func__,
+			fecp->ESW_VOMSEL);
+#endif
+}
+
+static int esw_vlan_output_process(struct switch_enet_private *fep,
+	int port, int mode)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if ((port < 0) || (port > 2)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, mode);
+		return -1;
+	}
+
+	if (port == 0) {
+		fecp->ESW_VOMSEL |= MCF_ESW_VOMSEL_OM0(mode);
+	} else if (port == 1) {
+		fecp->ESW_VOMSEL |= MCF_ESW_VOMSEL_OM1(mode);
+	} else if (port == 2) {
+		fecp->ESW_VOMSEL |= MCF_ESW_VOMSEL_OM2(mode);
+	} else {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -1;
+	}
+	return 0;
+}
+
+/* frame calssify and priority resolution */
+/* vlan priority lookup */
+static int esw_framecalssify_vlan_priority_lookup(
+	struct switch_enet_private *fep,
+	int port, int func_enable,
+	int vlan_pri_table_num,
+	int vlan_pri_table_value)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if ((port < 0) || (port > 3)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -1;
+	}
+
+	if (func_enable == 0) {
+		fecp->ESW_PRES[port] &= ~MCF_ESW_PRES_VLAN;
+		printk(KERN_ERR "%s: disable port %d VLAN priority "
+			"lookup function\n", __func__, port);
+		return 0;
+	}
+
+	if ((vlan_pri_table_num < 0) || (vlan_pri_table_num > 7)) {
+		printk(KERN_ERR "%s: do not support the priority %d\n",
+			__func__, vlan_pri_table_num);
+		return -1;
+	}
+
+	fecp->ESW_PVRES[port] |= ((vlan_pri_table_value & 0x3)
+		<< (vlan_pri_table_num*3));
+	/* enable port  VLAN priority lookup function */
+	fecp->ESW_PRES[port] |= MCF_ESW_PRES_VLAN;
+
+	return 0;
+}
+
+static int esw_framecalssify_ip_priority_lookup(
+	struct switch_enet_private *fep,
+	int port, int func_enable, int ipv4_en,
+	int ip_priority_num,
+	int ip_priority_value)
+{
+	struct switch_t  *fecp;
+	unsigned long tmp = 0, tmp_prio = 0;
+
+	fecp = fep->hwp;
+
+	if ((port < 0) || (port > 3)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -1;
+	}
+
+	if (func_enable == 0) {
+		fecp->ESW_PRES[port] &= ~MCF_ESW_PRES_IP;
+		printk(KERN_ERR "%s: disable port %d ip priority "
+			"lookup function\n", __func__, port);
+		return 0;
+	}
+
+	/* IPV4 priority 64 entry table lookup */
+	/* IPv4 head 6 bit TOS field */
+	if (ipv4_en == 1) {
+		if ((ip_priority_num < 0) || (ip_priority_num > 63)) {
+			printk(KERN_ERR "%s: do not support the table entry %d\n",
+				__func__, ip_priority_num);
+			return -2;
+		}
+	} else { /* IPV6 priority 256 entry table lookup */
+		/* IPv6 head 8 bit COS field */
+		if ((ip_priority_num < 0) || (ip_priority_num > 255)) {
+			printk(KERN_ERR "%s: do not support the table entry %d\n",
+				__func__, ip_priority_num);
+			return -3;
+		}
+	}
+
+	/* IP priority  table lookup : address */
+	tmp = MCF_ESW_IPRES_ADDRESS(ip_priority_num);
+	/* IP priority  table lookup : ipv4sel */
+	if (ipv4_en == 1)
+		tmp = tmp | MCF_ESW_IPRES_IPV4SEL;
+	/* IP priority  table lookup : priority */
+	if (port == 0)
+		tmp |= MCF_ESW_IPRES_PRI0(ip_priority_value);
+	else if (port == 1)
+		tmp |= MCF_ESW_IPRES_PRI1(ip_priority_value);
+	else if (port == 2)
+		tmp |= MCF_ESW_IPRES_PRI2(ip_priority_value);
+
+	/* configure */
+	fecp->ESW_IPRES = MCF_ESW_IPRES_READ |
+		MCF_ESW_IPRES_ADDRESS(ip_priority_num);
+	tmp_prio = fecp->ESW_IPRES;
+
+	fecp->ESW_IPRES = tmp | tmp_prio;
+
+	fecp->ESW_IPRES = MCF_ESW_IPRES_READ |
+		MCF_ESW_IPRES_ADDRESS(ip_priority_num);
+	tmp_prio = fecp->ESW_IPRES;
+
+	/* enable port  IP priority lookup function */
+	fecp->ESW_PRES[port] |= MCF_ESW_PRES_IP;
+
+	return 0;
+}
+
+static int esw_framecalssify_mac_priority_lookup(
+	struct switch_enet_private *fep,
+	int port)
+{
+	struct switch_t  *fecp;
+
+	if ((port < 0) || (port > 3)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -1;
+	}
+
+	fecp = fep->hwp;
+	fecp->ESW_PRES[port] |= MCF_ESW_PRES_MAC;
+
+	return 0;
+}
+
+static int esw_frame_calssify_priority_init(
+	struct switch_enet_private *fep,
+	int port, unsigned char priority_value)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if ((port < 0) || (port > 3)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -1;
+	}
+	/* disable all priority lookup function */
+	fecp->ESW_PRES[port] = 0;
+	fecp->ESW_PRES[port] = MCF_ESW_PRES_DFLT_PRI(priority_value & 0x7);
+
+	return 0;
+}
+
+static int esw_get_statistics_status(
+	struct switch_enet_private *fep,
+	struct esw_statistics_status *pStatistics)
+{
+	struct switch_t  *fecp;
+	fecp = fep->hwp;
+
+	pStatistics->ESW_DISCN   = fecp->ESW_DISCN;
+	pStatistics->ESW_DISCB   = fecp->ESW_DISCB;
+	pStatistics->ESW_NDISCN  = fecp->ESW_NDISCN;
+	pStatistics->ESW_NDISCB  = fecp->ESW_NDISCB;
+#ifdef DEBUG_STATISTICS
+	printk(KERN_ERR "%s:ESW_DISCN %#lx, ESW_DISCB %#lx,"
+		"ESW_NDISCN %#lx, ESW_NDISCB %#lx\n",
+		__func__, fecp->ESW_DISCN, fecp->ESW_DISCB,
+		fecp->ESW_NDISCN, fecp->ESW_NDISCB);
+#endif
+	return 0;
+}
+
+static int esw_get_port_statistics_status(
+	struct switch_enet_private *fep,
+	int port,
+	struct esw_port_statistics_status *pPortStatistics)
+{
+	struct switch_t  *fecp;
+
+	if ((port < 0) || (port > 3)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -1;
+	}
+
+	fecp = fep->hwp;
+
+	pPortStatistics->MCF_ESW_POQC   =
+		fecp->port_statistics_status[port].MCF_ESW_POQC;
+	pPortStatistics->MCF_ESW_PMVID  =
+		fecp->port_statistics_status[port].MCF_ESW_PMVID;
+	pPortStatistics->MCF_ESW_PMVTAG =
+		fecp->port_statistics_status[port].MCF_ESW_PMVTAG;
+	pPortStatistics->MCF_ESW_PBL    =
+		fecp->port_statistics_status[port].MCF_ESW_PBL;
+#ifdef DEBUG_PORT_STATISTICS
+	printk(KERN_ERR "%s : port[%d].MCF_ESW_POQC %#lx, MCF_ESW_PMVID %#lx,"
+		" MCF_ESW_PMVTAG %#lx, MCF_ESW_PBL %#lx\n",
+		__func__, port,
+		fecp->port_statistics_status[port].MCF_ESW_POQC,
+		fecp->port_statistics_status[port].MCF_ESW_PMVID,
+		fecp->port_statistics_status[port].MCF_ESW_PMVTAG,
+		fecp->port_statistics_status[port].MCF_ESW_PBL);
+#endif
+	return 0;
+}
+
+static int esw_get_output_queue_status(
+	struct switch_enet_private *fep,
+	struct esw_output_queue_status *pOutputQueue)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	pOutputQueue->ESW_MMSR  = fecp->ESW_MMSR;
+	pOutputQueue->ESW_LMT   = fecp->ESW_LMT;
+	pOutputQueue->ESW_LFC   = fecp->ESW_LFC;
+	pOutputQueue->ESW_IOSR  = fecp->ESW_IOSR;
+	pOutputQueue->ESW_PCSR  = fecp->ESW_PCSR;
+	pOutputQueue->ESW_QWT   = fecp->ESW_QWT;
+	pOutputQueue->ESW_P0BCT = fecp->ESW_P0BCT;
+#ifdef DEBUG_OUTPUT_QUEUE
+	printk(KERN_ERR "%s:ESW_MMSR %#lx, ESW_LMT %#lx, ESW_LFC %#lx, "
+		"ESW_IOSR %#lx, ESW_PCSR %#lx, ESW_QWT %#lx, ESW_P0BCT %#lx\n",
+		__func__, fecp->ESW_MMSR,
+		fecp->ESW_LMT, fecp->ESW_LFC,
+		fecp->ESW_IOSR,  fecp->ESW_PCSR,
+		fecp->ESW_QWT, fecp->ESW_P0BCT);
+#endif
+	return 0;
+}
+
+/* set output queue memory status and configure*/
+static int esw_set_output_queue_memory(
+	struct switch_enet_private *fep,
+	int fun_num,
+	struct esw_output_queue_status *pOutputQueue)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if (fun_num == 1) {
+		/* memory manager status*/
+		fecp->ESW_MMSR = pOutputQueue->ESW_MMSR;
+	} else if (fun_num == 2) {
+		/*low memory threshold*/
+		fecp->ESW_LMT = pOutputQueue->ESW_LMT;
+	} else if (fun_num == 3) {
+		/*lowest number of free cells*/
+		fecp->ESW_LFC = pOutputQueue->ESW_LFC;
+	} else if (fun_num == 4) {
+		/*queue weights*/
+		fecp->ESW_QWT = pOutputQueue->ESW_QWT;
+	} else if (fun_num == 5) {
+		/*port 0 backpressure congenstion thresled*/
+		fecp->ESW_P0BCT = pOutputQueue->ESW_P0BCT;
+	} else {
+		printk(KERN_INFO "%s: do not support the cmd %x\n",
+			__func__, fun_num);
+		return -1;
+	}
+#ifdef DEBUG_OUTPUT_QUEUE
+	printk(KERN_ERR "%s:ESW_MMSR %#lx, ESW_LMT %#lx, ESW_LFC %#lx, "
+		"ESW_IOSR %#lx, ESW_PCSR %#lx, ESW_QWT %#lx, ESW_P0BCT %#lx\n",
+		__func__, fecp->ESW_MMSR,
+		fecp->ESW_LMT, fecp->ESW_LFC,
+		fecp->ESW_IOSR,  fecp->ESW_PCSR,
+		fecp->ESW_QWT, fecp->ESW_P0BCT);
+#endif
+	return 0;
+}
+
+int esw_set_irq_mask(
+	struct switch_enet_private *fep,
+	unsigned long mask, int enable)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+#ifdef DEBUG_IRQ
+	printk(KERN_INFO "%s: irq event %#lx, irq mask %#lx "
+		" mask %x, enable %x\n",
+		__func__, fecp->switch_ievent,
+		fecp->switch_imask, mask, enable);
+#endif
+	if (enable == 1)
+		fecp->switch_imask |= mask;
+	else if (enable == 1)
+		fecp->switch_imask &= (~mask);
+	else {
+		printk(KERN_INFO "%s: enable %x is error value\n",
+			__func__, enable);
+		return -1;
+	}
+#ifdef DEBUG_IRQ
+	printk(KERN_INFO "%s: irq event %#lx, irq mask %#lx, "
+		"rx_des_start %#lx, tx_des_start %#lx, "
+		"rx_buff_size %#lx, rx_des_active %#lx, "
+		"tx_des_active %#lx\n",
+		__func__, fecp->switch_ievent, fecp->switch_imask,
+		fecp->fec_r_des_start, fecp->fec_x_des_start,
+		fecp->fec_r_buff_size, fecp->fec_r_des_active,
+		fecp->fec_x_des_active);
+#endif
+	return 0;
+}
+
+static void esw_get_switch_mode(
+	struct switch_enet_private *fep,
+	unsigned long *ulModeConfig)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulModeConfig = fecp->ESW_MODE;
+#ifdef DEBUG_SWITCH_MODE
+	printk(KERN_INFO "%s: mode %#lx \n",
+		__func__, fecp->ESW_MODE);
+#endif
+}
+
+static void esw_switch_mode_configure(
+	struct switch_enet_private *fep,
+	unsigned long configure)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	fecp->ESW_MODE |= configure;
+#ifdef DEBUG_SWITCH_MODE
+	printk(KERN_INFO "%s: mode %#lx \n",
+		__func__, fecp->ESW_MODE);
+#endif
+}
+
+
+static void esw_get_bridge_port(
+	struct switch_enet_private *fep,
+	unsigned long *ulBMPConfig)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulBMPConfig = fecp->ESW_BMPC;
+#ifdef DEBUG_BRIDGE_PORT
+	printk(KERN_INFO "%s: bridge management port %#lx \n",
+		__func__, fecp->ESW_BMPC);
+#endif
+}
+
+static void  esw_bridge_port_configure(
+	struct switch_enet_private *fep,
+	unsigned long configure)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	fecp->ESW_BMPC |= configure;
+#ifdef DEBUG_BRIDGE_PORT
+	printk(KERN_INFO "%s: bridge management port %#lx \n",
+		__func__, fecp->ESW_BMPC);
+#endif
+}
+
+/* The timer should create an interrupt every 4 seconds*/
+static void l2switch_aging_timer(unsigned long data)
+{
+	struct switch_enet_private *fep;
+
+	fep = (struct switch_enet_private *)data;
+
+	if (fep) {
+		TIMEINCREMENT(fep->currTime);
+		fep->timeChanged++;
+	}
+
+	mod_timer(&fep->timer_aging, jiffies + LEARNING_AGING_TIMER);
+}
+
+void esw_check_rxb_txb_interrupt(struct switch_enet_private *fep)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	/*Enable Forced forwarding for port 1*/
+	fecp->ESW_P0FFEN = MCF_ESW_P0FFEN_FEN |
+		MCF_ESW_P0FFEN_FD(1);
+	/*Disable learning for all ports*/
+
+	fecp->switch_imask = MCF_ESW_IMR_TXB | MCF_ESW_IMR_TXF |
+		MCF_ESW_IMR_LRN | MCF_ESW_IMR_RXB | MCF_ESW_IMR_RXF;
+	printk(KERN_ERR "%s: fecp->ESW_DBCR %#lx, fecp->ESW_P0FFEN %#lx"
+		" fecp->ESW_BKLR %#lx\n", __func__, fecp->ESW_DBCR,
+		fecp->ESW_P0FFEN, fecp->ESW_BKLR);
+}
+
+static int esw_mac_addr_static(struct switch_enet_private *fep)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	fecp->ESW_DBCR = MCF_ESW_DBCR_P1;
+
+	if (is_valid_ether_addr(fep->netdev->dev_addr))
+		esw_update_atable_static(fep->netdev->dev_addr, 7, 7, fep);
+	else{
+		printk(KERN_ERR "Can not add available mac address"
+				" for switch!!\n");
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+static void esw_main(struct switch_enet_private *fep)
+{
+	struct switch_t  *fecp;
+	fecp = fep->hwp;
+
+	esw_mac_addr_static(fep);
+	fecp->ESW_BKLR = 0;
+	fecp->switch_imask = MCF_ESW_IMR_TXB | MCF_ESW_IMR_TXF |
+		MCF_ESW_IMR_LRN | MCF_ESW_IMR_RXB | MCF_ESW_IMR_RXF;
+	fecp->ESW_PER = 0x70007;
+	fecp->ESW_DBCR = MCF_ESW_DBCR_P1 | MCF_ESW_DBCR_P2;
+}
+
+static int switch_enet_ioctl(
+	struct net_device *dev,
+	struct ifreq *ifr, int cmd)
+{
+	struct switch_enet_private *fep;
+	struct switch_t       *fecp;
+	int ret = 0;
+
+	printk(KERN_INFO "%s cmd %x\n", __func__, cmd);
+	fep = netdev_priv(dev);
+	fecp = (struct switch_t *)dev->base_addr;
+
+	switch (cmd) {
+	case ESW_SET_PORTENABLE_CONF:
+	{
+		struct eswIoctlPortEnableConfig configData;
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlPortEnableConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_port_enable_config(fep,
+			configData.port,
+			configData.tx_enable,
+			configData.rx_enable);
+	}
+		break;
+	case ESW_SET_BROADCAST_CONF:
+	{
+		struct eswIoctlPortConfig configData;
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlPortConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_port_broadcast_config(fep,
+			configData.port, configData.enable);
+	}
+		break;
+
+	case ESW_SET_MULTICAST_CONF:
+	{
+		struct eswIoctlPortConfig configData;
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlPortConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_port_multicast_config(fep,
+			configData.port, configData.enable);
+	}
+		break;
+
+	case ESW_SET_BLOCKING_CONF:
+	{
+		struct eswIoctlPortConfig configData;
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlPortConfig));
+
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_port_blocking_config(fep,
+			configData.port, configData.enable);
+	}
+		break;
+
+	case ESW_SET_LEARNING_CONF:
+	{
+		struct eswIoctlPortConfig configData;
+		printk(KERN_INFO "ESW_SET_LEARNING_CONF\n");
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlPortConfig));
+		if (ret)
+			return -EFAULT;
+		printk(KERN_INFO "ESW_SET_LEARNING_CONF: %x %x\n",
+				configData.port, configData.enable);
+		ret = esw_port_learning_config(fep,
+			configData.port, configData.enable);
+	}
+		break;
+
+	case ESW_SET_IP_SNOOP_CONF:
+	{
+		struct eswIoctlIpsnoopConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlIpsnoopConfig));
+		if (ret)
+			return -EFAULT;
+		printk(KERN_INFO "ESW_SET_IP_SNOOP_CONF:: %x %x %x\n",
+				configData.num, configData.mode,
+				configData.ip_header_protocol);
+		ret = esw_ip_snoop_config(fep,
+			configData.num, configData.mode,
+			configData.ip_header_protocol);
+	}
+		break;
+
+	case ESW_SET_PORT_SNOOP_CONF:
+	{
+		struct eswIoctlPortsnoopConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlPortsnoopConfig));
+		if (ret)
+			return -EFAULT;
+		printk(KERN_INFO "ESW_SET_PORT_SNOOP_CONF:: %x %x %x %x\n",
+			configData.num, configData.mode,
+			configData.compare_port, configData.compare_num);
+		ret = esw_tcpudp_port_snoop_config(fep,
+			configData.num, configData.mode,
+			configData.compare_port,
+			configData.compare_num);
+	}
+		break;
+
+	case ESW_SET_PORT_MIRROR_CONF:
+	{
+		struct eswIoctlPortMirrorConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlPortMirrorConfig));
+		if (ret)
+			return -EFAULT;
+		printk(KERN_INFO "ESW_SET_PORT_MIRROR_CONF:: %x %x %x "
+			"%s %s\n %x %x %x %x %x %x\n",
+			configData.mirror_port, configData.port,
+			configData.mirror_enable,
+			configData.src_mac, configData.des_mac,
+			configData.egress_en, configData.ingress_en,
+			configData.egress_mac_src_en,
+			configData.egress_mac_des_en,
+			configData.ingress_mac_src_en,
+			configData.ingress_mac_des_en);
+		ret = esw_port_mirroring_config(fep,
+			configData.mirror_port, configData.port,
+			configData.mirror_enable,
+			configData.src_mac, configData.des_mac,
+			configData.egress_en, configData.ingress_en,
+			configData.egress_mac_src_en,
+			configData.egress_mac_des_en,
+			configData.ingress_mac_src_en,
+			configData.ingress_mac_des_en);
+	}
+		break;
+
+	case ESW_SET_PIRORITY_VLAN:
+	{
+		struct eswIoctlPriorityVlanConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlPriorityVlanConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_framecalssify_vlan_priority_lookup(fep,
+			configData.port, configData.func_enable,
+			configData.vlan_pri_table_num,
+			configData.vlan_pri_table_value);
+	}
+		break;
+
+	case ESW_SET_PIRORITY_IP:
+	{
+		struct eswIoctlPriorityIPConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlPriorityIPConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_framecalssify_ip_priority_lookup(fep,
+			configData.port, configData.func_enable,
+			configData.ipv4_en, configData.ip_priority_num,
+			configData.ip_priority_value);
+	}
+		break;
+
+	case ESW_SET_PIRORITY_MAC:
+	{
+		struct eswIoctlPriorityMacConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlPriorityMacConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_framecalssify_mac_priority_lookup(fep,
+			configData.port);
+	}
+		break;
+
+	case ESW_SET_PIRORITY_DEFAULT:
+	{
+		struct eswIoctlPriorityDefaultConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlPriorityDefaultConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_frame_calssify_priority_init(fep,
+			configData.port, configData.priority_value);
+	}
+		break;
+
+	case ESW_SET_P0_FORCED_FORWARD:
+	{
+		struct eswIoctlP0ForcedForwardConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlP0ForcedForwardConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_forced_forward(fep, configData.port1,
+			configData.port2, configData.enable);
+	}
+		break;
+
+	case ESW_SET_BRIDGE_CONFIG:
+	{
+		unsigned long configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+
+		esw_bridge_port_configure(fep, configData);
+	}
+		break;
+
+	case ESW_SET_SWITCH_MODE:
+	{
+		unsigned long configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+
+		esw_switch_mode_configure(fep, configData);
+	}
+		break;
+
+	case ESW_SET_OUTPUT_QUEUE_MEMORY:
+	{
+		struct eswIoctlOutputQueue configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlOutputQueue));
+		if (ret)
+			return -EFAULT;
+
+		printk(KERN_INFO "ESW_SET_OUTPUT_QUEUE_MEMORY:: %#x \n"
+			"%#lx %#lx %#lx %#lx\n"
+			"%#lx %#lx %#lx\n",
+			configData.fun_num,
+			configData.sOutputQueue.ESW_MMSR,
+			configData.sOutputQueue.ESW_LMT,
+			configData.sOutputQueue.ESW_LFC,
+			configData.sOutputQueue.ESW_PCSR,
+			configData.sOutputQueue.ESW_IOSR,
+			configData.sOutputQueue.ESW_QWT,
+			configData.sOutputQueue.ESW_P0BCT);
+		ret = esw_set_output_queue_memory(fep,
+			configData.fun_num, &configData.sOutputQueue);
+	}
+		break;
+
+	case ESW_SET_VLAN_OUTPUT_PROCESS:
+	{
+		struct eswIoctlVlanOutputConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlVlanOutputConfig));
+		if (ret)
+			return -EFAULT;
+
+		printk(KERN_INFO "ESW_SET_VLAN_OUTPUT_PROCESS: %x %x\n",
+			configData.port, configData.mode);
+		ret = esw_vlan_output_process(fep,
+			configData.port, configData.mode);
+	}
+		break;
+
+	case ESW_SET_VLAN_INPUT_PROCESS:
+	{
+		struct eswIoctlVlanInputConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlVlanInputConfig));
+		if (ret)
+			return -EFAULT;
+
+		printk(KERN_INFO "ESW_SET_VLAN_INPUT_PROCESS: %x %x"
+				"%x %x %x %x\n",
+			configData.port, configData.mode,
+			configData.port_vlanid,
+			configData.vlan_verify_en,
+			configData.vlan_domain_num,
+			configData.vlan_domain_port);
+		ret = esw_vlan_input_process(fep, configData.port,
+				configData.mode, configData.port_vlanid,
+				configData.vlan_verify_en,
+				configData.vlan_domain_num,
+				configData.vlan_domain_port);
+	}
+		break;
+
+	case ESW_SET_VLAN_DOMAIN_VERIFICATION:
+	{
+		struct eswIoctlVlanVerificationConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlVlanVerificationConfig));
+		if (ret)
+			return -EFAULT;
+
+		printk("ESW_SET_VLAN_DOMAIN_VERIFICATION: "
+			"%x %x %x\n",
+			configData.port,
+			configData.vlan_domain_verify_en,
+			configData.vlan_discard_unknown_en);
+		ret = esw_set_vlan_verification(
+			fep, configData.port,
+			configData.vlan_domain_verify_en,
+			configData.vlan_discard_unknown_en);
+	}
+		break;
+
+	case ESW_SET_VLAN_RESOLUTION_TABLE:
+	{
+		struct eswIoctlVlanResoultionTable configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlVlanResoultionTable));
+		if (ret)
+			return -EFAULT;
+
+		printk(KERN_INFO "ESW_SET_VLAN_RESOLUTION_TABLE: "
+			"%x %x %x\n",
+			configData.port_vlanid,
+			configData.vlan_domain_num,
+			configData.vlan_domain_port);
+
+		ret = esw_set_vlan_resolution_table(
+			fep, configData.port_vlanid,
+			configData.vlan_domain_num,
+			configData.vlan_domain_port);
+
+	}
+		break;
+	case ESW_UPDATE_STATIC_MACTABLE:
+	{
+		struct eswIoctlUpdateStaticMACtable configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlUpdateStaticMACtable));
+		if (ret)
+			return -EFAULT;
+
+		printk(KERN_INFO "%s: ESW_UPDATE_STATIC_MACTABLE: mac %s, "
+			"port %x, priority %x\n", __func__,
+			configData.mac_addr,
+			configData.port,
+			configData.priority);
+		ret = esw_update_atable_static(configData.mac_addr,
+				configData.port, configData.priority, fep);
+	}
+		break;
+
+	case ESW_CLEAR_ALL_MACTABLE:
+	{
+		esw_clear_atable(fep);
+	}
+		break;
+
+	case ESW_GET_STATISTICS_STATUS:
+	{
+		struct esw_statistics_status Statistics;
+		ret = esw_get_statistics_status(fep, &Statistics);
+		if (ret != 0) {
+			printk(KERN_ERR "%s: cmd %x fail\n",
+				__func__, cmd);
+			return -1;
+		}
+
+		ret = copy_to_user(ifr->ifr_data, &Statistics,
+			sizeof(struct esw_statistics_status));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_PORT0_STATISTICS_STATUS:
+	{
+		struct esw_port_statistics_status PortStatistics;
+
+		ret = esw_get_port_statistics_status(fep,
+			0, &PortStatistics);
+		if (ret != 0) {
+			printk(KERN_ERR "%s: cmd %x fail\n",
+				__func__, cmd);
+			return -1;
+		}
+
+		ret = copy_to_user(ifr->ifr_data, &PortStatistics,
+			sizeof(struct esw_port_statistics_status));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_PORT1_STATISTICS_STATUS:
+	{
+		struct esw_port_statistics_status PortStatistics;
+
+		ret = esw_get_port_statistics_status(fep,
+			1, &PortStatistics);
+		if (ret != 0) {
+			printk(KERN_ERR "%s: cmd %x fail\n",
+				__func__, cmd);
+			return -1;
+		}
+
+		ret = copy_to_user(ifr->ifr_data, &PortStatistics,
+			sizeof(struct esw_port_statistics_status));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_PORT2_STATISTICS_STATUS:
+	{
+		struct esw_port_statistics_status PortStatistics;
+
+		ret = esw_get_port_statistics_status(fep,
+			2, &PortStatistics);
+		if (ret != 0) {
+			printk(KERN_ERR "%s: cmd %x fail\n",
+				__func__, cmd);
+			return -1;
+		}
+
+		ret = copy_to_user(ifr->ifr_data, &PortStatistics,
+			sizeof(struct esw_port_statistics_status));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_LEARNING_CONF:
+	{
+		unsigned long PortLearning;
+
+		esw_get_port_learning(fep, &PortLearning);
+		ret = copy_to_user(ifr->ifr_data, &PortLearning,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_BLOCKING_CONF:
+	{
+		unsigned long PortBlocking;
+
+		esw_get_port_blocking(fep, &PortBlocking);
+		ret = copy_to_user(ifr->ifr_data, &PortBlocking,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_MULTICAST_CONF:
+	{
+		unsigned long PortMulticast;
+
+		esw_get_port_multicast(fep, &PortMulticast);
+		ret = copy_to_user(ifr->ifr_data, &PortMulticast,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_BROADCAST_CONF:
+	{
+		unsigned long PortBroadcast;
+
+		esw_get_port_broadcast(fep, &PortBroadcast);
+		ret = copy_to_user(ifr->ifr_data, &PortBroadcast,
+		sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_PORTENABLE_CONF:
+	{
+		unsigned long PortEnable;
+
+		esw_get_port_enable(fep, &PortEnable);
+		ret = copy_to_user(ifr->ifr_data, &PortEnable,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_IP_SNOOP_CONF:
+	{
+		unsigned long ESW_IPSNP[8];
+
+		esw_get_ip_snoop_config(fep, (unsigned long *)ESW_IPSNP);
+		ret = copy_to_user(ifr->ifr_data, ESW_IPSNP,
+			(8 * sizeof(unsigned long)));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_PORT_SNOOP_CONF:
+	{
+		unsigned long ESW_PSNP[8];
+
+		esw_get_tcpudp_port_snoop_config(fep,
+				(unsigned long *)ESW_PSNP);
+		ret = copy_to_user(ifr->ifr_data, ESW_PSNP,
+			(8 * sizeof(unsigned long)));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_PORT_MIRROR_CONF:
+	{
+		struct eswIoctlPortMirrorStatus PortMirrorStatus;
+
+		esw_get_port_mirroring(fep, &PortMirrorStatus);
+		ret = copy_to_user(ifr->ifr_data, &PortMirrorStatus,
+			sizeof(struct eswIoctlPortMirrorStatus));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_P0_FORCED_FORWARD:
+	{
+		unsigned long ForceForward;
+
+		esw_get_forced_forward(fep, &ForceForward);
+		ret = copy_to_user(ifr->ifr_data, &ForceForward,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_SWITCH_MODE:
+	{
+		unsigned long Config;
+
+		esw_get_switch_mode(fep, &Config);
+		ret = copy_to_user(ifr->ifr_data, &Config,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_BRIDGE_CONFIG:
+	{
+		unsigned long Config;
+
+		esw_get_bridge_port(fep, &Config);
+		ret = copy_to_user(ifr->ifr_data, &Config,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+	case ESW_GET_OUTPUT_QUEUE_STATUS:
+	{
+		struct esw_output_queue_status Config;
+		esw_get_output_queue_status(fep,
+			&Config);
+		ret = copy_to_user(ifr->ifr_data, &Config,
+			sizeof(struct esw_output_queue_status));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_VLAN_OUTPUT_PROCESS:
+	{
+		unsigned long Config;
+
+		esw_get_vlan_output_config(fep, &Config);
+		ret = copy_to_user(ifr->ifr_data, &Config,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_VLAN_INPUT_PROCESS:
+	{
+		struct eswIoctlVlanInputStatus Config;
+
+		esw_get_vlan_input_config(fep, &Config);
+		ret = copy_to_user(ifr->ifr_data, &Config,
+			sizeof(struct eswIoctlVlanInputStatus));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_VLAN_RESOLUTION_TABLE:
+	{
+		unsigned long Config;
+		unsigned char ConfigData;
+		ret = copy_from_user(&ConfigData,
+			ifr->ifr_data,
+			sizeof(unsigned char));
+		if (ret)
+			return -EFAULT;
+
+		printk(KERN_INFO "ESW_GET_VLAN_RESOLUTION_TABLE: %x \n",
+			ConfigData);
+
+		esw_get_vlan_resolution_table(fep, ConfigData, &Config);
+
+		ret = copy_to_user(ifr->ifr_data, &Config,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_VLAN_DOMAIN_VERIFICATION:
+	{
+		unsigned long Config;
+
+		esw_get_vlan_verification(fep, &Config);
+		ret = copy_to_user(ifr->ifr_data, &Config,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+	/*------------------------------------------------------------------*/
+	default:
+		return -EOPNOTSUPP;
+	}
+
+
+	return ret;
+}
+
+static int
+switch_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct switch_enet_private *fep;
+	struct switch_t	*fecp;
+	struct cbd_t	*bdp;
+	void *bufaddr;
+	unsigned short	status;
+	unsigned long flags;
+
+	fep = netdev_priv(dev);
+	fecp = (struct switch_t *)fep->hwp;
+
+	spin_lock_irqsave(&fep->hw_lock, flags);
+	/* Fill in a Tx ring entry */
+	bdp = fep->cur_tx;
+
+	status = bdp->cbd_sc;
+
+	if (status & BD_ENET_TX_READY) {
+		/*
+		 * Ooops.  All transmit buffers are full.  Bail out.
+		 * This should not happen, since dev->tbusy should be set.
+		 */
+		printk(KERN_ERR "%s: tx queue full!.\n", dev->name);
+		spin_unlock_irqrestore(&fep->hw_lock, flags);
+		return NETDEV_TX_BUSY;
+	}
+
+	/* Clear all of the status flags */
+	status &= ~BD_ENET_TX_STATS;
+
+	/* Set buffer length and buffer pointer	*/
+	bufaddr = skb->data;
+	bdp->cbd_datlen = skb->len;
+
+	/*
+	 * On some FEC implementations data must be aligned on
+	 * 4-byte boundaries. Use bounce buffers to copy data
+	 * and get it aligned. Ugh.
+	 */
+	if ((unsigned long) bufaddr & FEC_ALIGNMENT) {
+		unsigned int index;
+		index = bdp - fep->tx_bd_base;
+		memcpy(fep->tx_bounce[index],
+		       (void *)skb->data, skb->len);
+		bufaddr = fep->tx_bounce[index];
+	}
+
+#ifdef CONFIG_ARCH_MXS
+	swap_buffer(bufaddr, skb->len);
+#endif
+
+	/* Save skb pointer. */
+	fep->tx_skbuff[fep->skb_cur] = skb;
+
+	dev->stats.tx_bytes += skb->len;
+	fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
+
+	/*
+	 * Push the data cache so the CPM does not get stale memory
+	 * data.
+	 */
+	bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr,
+		FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
+
+	/*
+	 * Send it on its way.  Tell FEC it's ready, interrupt when done,
+	 * it's the last BD of the frame, and to put the CRC on the end.
+	 */
+
+	status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
+			| BD_ENET_TX_LAST | BD_ENET_TX_TC);
+	bdp->cbd_sc = status;
+#ifdef L2SWITCH_ENHANCED_BUFFER
+	bdp->bdu = 0x00000000;
+	bdp->ebd_status = TX_BD_INT | TX_BD_TS;
+#endif
+	dev->trans_start = jiffies;
+
+	/* Trigger transmission start */
+	fecp->fec_x_des_active = MCF_ESW_TDAR_X_DES_ACTIVE;
+
+	/* If this was the last BD in the ring,
+	 * start at the beginning again.
+	 */
+	if (status & BD_ENET_TX_WRAP)
+		bdp = fep->tx_bd_base;
+	else
+		bdp++;
+
+	if (bdp == fep->dirty_tx) {
+		fep->tx_full = 1;
+		netif_stop_queue(dev);
+		printk(KERN_ERR "%s:  net stop\n", __func__);
+	}
+
+	fep->cur_tx = bdp;
+
+	spin_unlock_irqrestore(&fep->hw_lock, flags);
+
+	return 0;
+}
+
+static void
+switch_timeout(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+
+	printk(KERN_INFO "%s: transmit timed out.\n", dev->name);
+	dev->stats.tx_errors++;
+	{
+	int	i;
+	struct cbd_t	*bdp;
+
+	printk(KERN_INFO "Ring data dump: cur_tx %lx%s,"
+		"dirty_tx %lx cur_rx: %lx\n",
+		(unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
+		(unsigned long)fep->dirty_tx,
+		(unsigned long)fep->cur_rx);
+
+	bdp = fep->tx_bd_base;
+	printk(KERN_INFO " tx: %u buffers\n",  TX_RING_SIZE);
+	for (i = 0 ; i < TX_RING_SIZE; i++) {
+		printk(KERN_INFO "  %08x: %04x %04x %08x\n",
+		       (uint) bdp,
+		       bdp->cbd_sc,
+		       bdp->cbd_datlen,
+		       (int) bdp->cbd_bufaddr);
+		bdp++;
+	}
+
+	bdp = fep->rx_bd_base;
+	printk(KERN_INFO " rx: %lu buffers\n",
+			(unsigned long) RX_RING_SIZE);
+	for (i = 0 ; i < RX_RING_SIZE; i++) {
+		printk(KERN_INFO "  %08x: %04x %04x %08x\n",
+		       (uint) bdp,
+		       bdp->cbd_sc,
+		       bdp->cbd_datlen,
+		       (int) bdp->cbd_bufaddr);
+		bdp++;
+	}
+	}
+	switch_restart(dev, fep->full_duplex);
+	netif_wake_queue(dev);
+}
+
+/*
+ * The interrupt handler.
+ * This is called from the MPC core interrupt.
+ */
+static irqreturn_t
+switch_enet_interrupt(int irq, void *dev_id)
+{
+	struct	net_device *dev = dev_id;
+	struct switch_enet_private *fep = netdev_priv(dev);
+	struct switch_t *fecp;
+	uint	int_events;
+	irqreturn_t ret = IRQ_NONE;
+
+	fecp = (struct switch_t *)dev->base_addr;
+
+	/* Get the interrupt events that caused us to be here */
+	do {
+		int_events = fecp->switch_ievent;
+		fecp->switch_ievent = int_events;
+		/* Handle receive event in its own function. */
+
+		/* Transmit OK, or non-fatal error. Update the buffer
+		 * descriptors. FEC handles all errors, we just discover
+		 *  them as part of the transmit process.
+		 */
+		if (int_events & MCF_ESW_ISR_LRN) {
+			if (fep->learning_irqhandle_enable)
+				esw_atable_dynamicms_learn_migration(
+					fep, fep->currTime);
+			ret = IRQ_HANDLED;
+		}
+
+		if (int_events & MCF_ESW_ISR_OD0)
+			ret = IRQ_HANDLED;
+
+		if (int_events & MCF_ESW_ISR_OD1)
+			ret = IRQ_HANDLED;
+
+		if (int_events & MCF_ESW_ISR_OD2)
+			ret = IRQ_HANDLED;
+
+		if (int_events & MCF_ESW_ISR_RXB)
+			ret = IRQ_HANDLED;
+
+		if (int_events & MCF_ESW_ISR_RXF) {
+			ret = IRQ_HANDLED;
+			switch_enet_rx(dev);
+		}
+
+		if (int_events & MCF_ESW_ISR_TXB)
+			ret = IRQ_HANDLED;
+
+		if (int_events & MCF_ESW_ISR_TXF) {
+			ret = IRQ_HANDLED;
+			switch_enet_tx(dev);
+		}
+
+	} while (int_events);
+
+	return ret;
+}
+
+
+static void
+switch_enet_tx(struct net_device *dev)
+{
+	struct	switch_enet_private *fep;
+	struct cbd_t	*bdp;
+	unsigned short status;
+	struct	sk_buff	*skb;
+
+	fep = netdev_priv(dev);
+	spin_lock(&fep->hw_lock);
+	bdp = fep->dirty_tx;
+
+	while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
+		if (bdp == fep->cur_tx && fep->tx_full == 0)
+			break;
+
+		dma_unmap_single(&dev->dev, bdp->cbd_bufaddr,
+				FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
+		bdp->cbd_bufaddr = 0;
+		skb = fep->tx_skbuff[fep->skb_dirty];
+		/* Check for errors */
+		if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
+				   BD_ENET_TX_RL | BD_ENET_TX_UN |
+				   BD_ENET_TX_CSL)) {
+			dev->stats.tx_errors++;
+			if (status & BD_ENET_TX_HB)  /* No heartbeat */
+				dev->stats.tx_heartbeat_errors++;
+			if (status & BD_ENET_TX_LC)  /* Late collision */
+				dev->stats.tx_window_errors++;
+			if (status & BD_ENET_TX_RL)  /* Retrans limit */
+				dev->stats.tx_aborted_errors++;
+			if (status & BD_ENET_TX_UN)  /* Underrun */
+				dev->stats.tx_fifo_errors++;
+			if (status & BD_ENET_TX_CSL) /* Carrier lost */
+				dev->stats.tx_carrier_errors++;
+		} else {
+			dev->stats.tx_packets++;
+		}
+
+		if (status & BD_ENET_TX_READY)
+			printk(KERN_ERR "HEY! "
+				"Enet xmit interrupt and TX_READY.\n");
+		/*
+		 * Deferred means some collisions occurred during transmit,
+		 * but we eventually sent the packet OK.
+		 */
+		if (status & BD_ENET_TX_DEF)
+			dev->stats.collisions++;
+
+		/* Free the sk buffer associated with this last transmit */
+		dev_kfree_skb_any(skb);
+		fep->tx_skbuff[fep->skb_dirty] = NULL;
+		fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
+
+		/* Update pointer to next buffer descriptor to be transmitted */
+		if (status & BD_ENET_TX_WRAP)
+			bdp = fep->tx_bd_base;
+		else
+			bdp++;
+
+		/*
+		 * Since we have freed up a buffer, the ring is no longer
+		 * full.
+		 */
+		if (fep->tx_full) {
+			fep->tx_full = 0;
+			printk(KERN_ERR "%s: tx full is zero\n", __func__);
+			if (netif_queue_stopped(dev))
+				netif_wake_queue(dev);
+		}
+	}
+	fep->dirty_tx = bdp;
+	spin_unlock(&fep->hw_lock);
+}
+
+
+/*
+ * During a receive, the cur_rx points to the current incoming buffer.
+ * When we update through the ring, if the next incoming buffer has
+ * not been given to the system, we just set the empty indicator,
+ * effectively tossing the packet.
+ */
+static void
+switch_enet_rx(struct net_device *dev)
+{
+	struct	switch_enet_private *fep;
+	struct switch_t *fecp;
+	struct cbd_t *bdp;
+	unsigned short status;
+	struct	sk_buff	*skb;
+	ushort	pkt_len;
+	__u8 *data;
+
+#ifdef CONFIG_M532x
+	flush_cache_all();
+#endif
+
+	fep = netdev_priv(dev);
+	fecp = (struct switch_t *)fep->hwp;
+
+	spin_lock(&fep->hw_lock);
+	/*
+	 * First, grab all of the stats for the incoming packet.
+	 * These get messed up if we get called due to a busy condition.
+	 */
+	bdp = fep->cur_rx;
+#ifdef L2SWITCH_ENHANCED_BUFFER
+	printk(KERN_INFO "%s: cbd_sc %x cbd_datlen %x cbd_bufaddr %x "
+		"ebd_status %x bdu %x length_proto_type %x "
+		"payload_checksum %x\n",
+		__func__, bdp->cbd_sc, bdp->cbd_datlen,
+		bdp->cbd_bufaddr, bdp->ebd_status, bdp->bdu,
+		bdp->length_proto_type, bdp->payload_checksum);
+#endif
+
+while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
+	/*
+	 * Since we have allocated space to hold a complete frame,
+	 * the last indicator should be set.
+	 */
+	if ((status & BD_ENET_RX_LAST) == 0)
+		printk(KERN_INFO "SWITCH ENET: rcv is not +last\n");
+
+	if (!fep->opened)
+		goto rx_processing_done;
+
+	/* Check for errors. */
+	if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
+			   BD_ENET_RX_CR | BD_ENET_RX_OV)) {
+		dev->stats.rx_errors++;
+		if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
+			/* Frame too long or too short. */
+			dev->stats.rx_length_errors++;
+		}
+		if (status & BD_ENET_RX_NO)	/* Frame alignment */
+			dev->stats.rx_frame_errors++;
+		if (status & BD_ENET_RX_CR)	/* CRC Error */
+			dev->stats.rx_crc_errors++;
+		if (status & BD_ENET_RX_OV)	/* FIFO overrun */
+			dev->stats.rx_fifo_errors++;
+	}
+
+	/*
+	 * Report late collisions as a frame error.
+	 * On this error, the BD is closed, but we don't know what we
+	 * have in the buffer.  So, just drop this frame on the floor.
+	 */
+	if (status & BD_ENET_RX_CL) {
+		dev->stats.rx_errors++;
+		dev->stats.rx_frame_errors++;
+		goto rx_processing_done;
+	}
+
+	/* Process the incoming frame */
+	dev->stats.rx_packets++;
+	pkt_len = bdp->cbd_datlen;
+	dev->stats.rx_bytes += pkt_len;
+	data = (__u8 *)__va(bdp->cbd_bufaddr);
+
+	dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
+			DMA_FROM_DEVICE);
+#ifdef CONFIG_ARCH_MXS
+	swap_buffer(data, pkt_len);
+#endif
+	/*
+	 * This does 16 byte alignment, exactly what we need.
+	 * The packet length includes FCS, but we don't want to
+	 * include that when passing upstream as it messes up
+	 * bridging applications.
+	 */
+	skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
+	if (unlikely(!skb)) {
+		printk("%s: Memory squeeze, dropping packet.\n",
+			dev->name);
+		dev->stats.rx_dropped++;
+	} else {
+		skb_reserve(skb, NET_IP_ALIGN);
+		skb_put(skb, pkt_len - 4);      /* Make room */
+		skb_copy_to_linear_data(skb, data, pkt_len - 4);
+		skb->protocol = eth_type_trans(skb, dev);
+		netif_rx(skb);
+	}
+
+	bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen,
+		DMA_FROM_DEVICE);
+
+rx_processing_done:
+
+	/* Clear the status flags for this buffer */
+	status &= ~BD_ENET_RX_STATS;
+
+	/* Mark the buffer empty */
+	status |= BD_ENET_RX_EMPTY;
+	bdp->cbd_sc = status;
+
+	/* Update BD pointer to next entry */
+	if (status & BD_ENET_RX_WRAP)
+		bdp = fep->rx_bd_base;
+	else
+		bdp++;
+
+	/*
+	 * Doing this here will keep the FEC running while we process
+	 * incoming frames.  On a heavily loaded network, we should be
+	 * able to keep up at the expense of system resources.
+	 */
+	fecp->fec_r_des_active = MCF_ESW_RDAR_R_DES_ACTIVE;
+   } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
+	fep->cur_rx = bdp;
+
+	spin_unlock(&fep->hw_lock);
+}
+
+#ifdef FEC_PHY
+static int fec_mdio_transfer(struct mii_bus *bus, int phy_id,
+	int reg, int regval)
+{
+	struct net_device *dev = bus->priv;
+	unsigned long   flags;
+	struct switch_enet_private *fep;
+	int tries = 100;
+	int retval = 0;
+
+	fep = netdev_priv(dev);
+	spin_lock_irqsave(&fep->mii_lock, flags);
+
+	regval |= phy_id << 23;
+	writel(regval, fep->enet_addr + MCF_FEC_MMFR0);
+
+	/* wait for it to finish, this takes about 23 us on lite5200b */
+	while (!(readl(fep->enet_addr + MCF_FEC_EIR0) & FEC_ENET_MII)
+			&& --tries)
+		udelay(5);
+
+	if (!tries) {
+		printk(KERN_ERR "%s timeout\n", __func__);
+		return -ETIMEDOUT;
+	}
+
+	writel(FEC_ENET_MII, fep->enet_addr + MCF_FEC_EIR0);
+	retval = readl(fep->enet_addr + MCF_FEC_MMFR0);
+	spin_unlock_irqrestore(&fep->mii_lock, flags);
+
+	return retval;
+}
+
+/*
+ * Phy section
+ */
+static void switch_adjust_link(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	struct phy_device *phy_dev = fep->phy_dev;
+	unsigned long flags;
+	int status_change = 0;
+
+	phy_dev = g_phy_dev;
+	spin_lock_irqsave(&fep->hw_lock, flags);
+
+	/* Prevent a state halted on mii error */
+	if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
+		phy_dev->state = PHY_RESUMING;
+		goto spin_unlock;
+	}
+
+	/* Duplex link change */
+	if (phy_dev->link) {
+		if (fep->full_duplex != phy_dev->duplex) {
+			switch_restart(dev, phy_dev->duplex);
+			status_change = 1;
+		}
+	}
+
+	/* Link on or off change */
+	if (phy_dev->link != fep->link) {
+		fep->link = phy_dev->link;
+		if (phy_dev->link)
+			switch_restart(dev, phy_dev->duplex);
+		else
+			switch_stop(dev);
+		status_change = 1;
+	}
+
+spin_unlock:
+	spin_unlock_irqrestore(&fep->hw_lock, flags);
+
+	if (status_change)
+		phy_print_status(phy_dev);
+}
+
+/*
+ * NOTE: a MII transaction is during around 25 us, so polling it...
+ */
+static int fec_enet_mdio_poll(struct switch_enet_private *fep)
+ {
+	int timeout = FEC_MII_TIMEOUT;
+	unsigned int reg = 0;
+
+	fep->mii_timeout = 0;
+
+	/* wait for end of transfer */
+	reg = readl(fep->hwp + FEC_IEVENT);
+	while (!(reg & FEC_ENET_MII)) {
+		msleep(1);
+		if (timeout-- < 0) {
+			fep->mii_timeout = 1;
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+	struct switch_enet_private *fep = netdev_priv(bus->priv);
+
+
+	/* clear MII end of transfer bit */
+	writel(FEC_ENET_MII, fep->enet_addr + FEC_IEVENT
+			/ sizeof(unsigned long));
+
+	/* start a read op */
+	writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
+		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
+		FEC_MMFR_TA, fep->enet_addr + FEC_MII_DATA
+		/ sizeof(unsigned long));
+
+	fec_enet_mdio_poll(fep);
+
+	/* return value */
+	return FEC_MMFR_DATA(readl(fep->enet_addr + FEC_MII_DATA
+				/ sizeof(unsigned long)));
+}
+
+static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
+			   u16 value)
+{
+	struct switch_enet_private *fep = netdev_priv(bus->priv);
+
+	/* clear MII end of transfer bit */
+	writel(FEC_ENET_MII, fep->enet_addr + FEC_IEVENT
+			/ sizeof(unsigned long));
+
+	/* start a read op */
+	writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
+		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
+		FEC_MMFR_TA | FEC_MMFR_DATA(value),
+		fep->enet_addr + FEC_MII_DATA / sizeof(unsigned long));
+
+	fec_enet_mdio_poll(fep);
+
+	return 0;
+}
+
+static int fec_enet_mdio_reset(struct mii_bus *bus)
+{
+	return 0;
+}
+
+static struct mii_bus *fec_enet_mii_init(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	int err = -ENXIO, i;
+
+	fep->mii_timeout = 0;
+	/*
+	 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
+	 */
+	fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
+#ifdef CONFIG_ARCH_MXS
+	/* Can't get phy(8720) ID when set to 2.5M on MX28, lower it */
+	fep->phy_speed <<= 2;
+#endif
+	writel(fep->phy_speed, fep->enet_addr + FEC_MII_SPEED
+			/ sizeof(unsigned long));
+
+	fep->mii_bus = mdiobus_alloc();
+	if (fep->mii_bus == NULL) {
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	fep->mii_bus->name = "fec_enet_mii_bus";
+	fep->mii_bus->read = fec_enet_mdio_read;
+	fep->mii_bus->write = fec_enet_mdio_write;
+	fep->mii_bus->reset = fec_enet_mdio_reset;
+	snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", fep->pdev->id);
+	fep->mii_bus->priv = dev;
+
+	fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+	if (!fep->mii_bus->irq) {
+		err = -ENOMEM;
+		goto err_out_free_mdiobus;
+	}
+
+	for (i = 0; i < PHY_MAX_ADDR; i++)
+		fep->mii_bus->irq[i] = PHY_POLL;
+
+	if (mdiobus_register(fep->mii_bus)) {
+		goto err_out_free_mdio_irq;
+	}
+
+	return fep->mii_bus;
+
+err_out_free_mdio_irq:
+	kfree(fep->mii_bus->irq);
+err_out_free_mdiobus:
+	mdiobus_free(fep->mii_bus);
+err_out:
+	return ERR_PTR(err);
+}
+#endif
+
+static int fec_enet_get_settings(struct net_device *dev,
+				  struct ethtool_cmd *cmd)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	struct phy_device *phydev = fep->phy_dev;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_ethtool_gset(phydev, cmd);
+}
+
+static int fec_enet_set_settings(struct net_device *dev,
+				 struct ethtool_cmd *cmd)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	struct phy_device *phydev = fep->phy_dev;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_ethtool_sset(phydev, cmd);
+}
+
+static void fec_enet_get_drvinfo(struct net_device *dev,
+				 struct ethtool_drvinfo *info)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+
+	strcpy(info->driver, fep->pdev->dev.driver->name);
+	strcpy(info->version, "Revision: 1.0");
+	strcpy(info->bus_info, dev_name(&dev->dev));
+}
+
+#ifdef FEC_PHY
+static int fec_switch_init_phy(struct net_device *dev)
+{
+	struct switch_enet_private *priv = netdev_priv(dev);
+	struct phy_device *phydev = NULL;
+	int i;
+
+	/* search for connect PHY device */
+	for (i = 0; i < PHY_MAX_ADDR; i++) {
+		struct phy_device *const tmp_phydev =
+			priv->mdio_bus->phy_map[i];
+
+		if (!tmp_phydev) {
+#ifdef FEC_DEBUG
+			printk(KERN_INFO "%s no PHY here at"
+				"mii_bus->phy_map[%d]\n",
+				__func__, i);
+#endif
+			continue; /* no PHY here... */
+		}
+
+#ifdef CONFIG_FEC_SHARED_PHY
+		if (priv->index == 0)
+			phydev = tmp_phydev;
+		else if (priv->index == 1) {
+			if (startnode == 1) {
+				phydev = tmp_phydev;
+				startnode = 0;
+			} else {
+				startnode++;
+				continue;
+			}
+		} else
+			printk(KERN_INFO "%s now we do not"
+				"support (%d) more than"
+				"2 phys shared "
+				"one mdio bus\n",
+				__func__, startnode);
+#else
+		phydev = tmp_phydev;
+#endif
+#ifdef FEC_DEBUG
+		printk(KERN_INFO "%s find PHY here at"
+			"mii_bus->phy_map[%d]\n",
+			__func__, i);
+#endif
+		break; /* found it */
+	}
+
+	/* now we are supposed to have a proper phydev, to attach to... */
+	if (!phydev) {
+		printk(KERN_INFO "%s: Don't found any phy device at all\n",
+			dev->name);
+		return -ENODEV;
+	}
+
+	priv->link = PHY_DOWN;
+	priv->old_link = PHY_DOWN;
+	priv->speed = 0;
+	priv->duplex = -1;
+
+	phydev = phy_connect(dev, dev_name(&phydev->dev),
+		&switch_adjust_link, 0, PHY_INTERFACE_MODE_MII);
+	if (IS_ERR(phydev)) {
+		printk(KERN_ERR " %s phy_connect failed\n", __func__);
+		return PTR_ERR(phydev);
+	}
+
+	printk(KERN_INFO "attached phy %i to driver %s\n",
+		phydev->addr, phydev->drv->name);
+
+	priv->phydev	= phydev;
+	g_phy_dev	= phydev;
+
+	return 0;
+}
+#endif
+
+static void fec_enet_free_buffers(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	int i;
+	struct sk_buff *skb;
+	struct cbd_t	*bdp;
+
+	bdp = fep->rx_bd_base;
+	for (i = 0; i < RX_RING_SIZE; i++) {
+		skb = fep->rx_skbuff[i];
+
+		if (bdp->cbd_bufaddr)
+			dma_unmap_single(&dev->dev, bdp->cbd_bufaddr,
+					FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
+		if (skb)
+			dev_kfree_skb(skb);
+		bdp++;
+	}
+
+	bdp = fep->tx_bd_base;
+	for (i = 0; i < TX_RING_SIZE; i++)
+		kfree(fep->tx_bounce[i]);
+}
+
+static int fec_enet_alloc_buffers(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	int i;
+	struct sk_buff *skb;
+	struct cbd_t	*bdp;
+
+	bdp = fep->rx_bd_base;
+	for (i = 0; i < RX_RING_SIZE; i++) {
+		skb = dev_alloc_skb(SWITCH_ENET_RX_FRSIZE);
+		if (!skb) {
+			fec_enet_free_buffers(dev);
+			return -ENOMEM;
+		}
+		fep->rx_skbuff[i] = skb;
+
+		bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data,
+				SWITCH_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
+		bdp->cbd_sc = BD_ENET_RX_EMPTY;
+#ifdef L2SWITCH_ENHANCED_BUFFER
+	bdp->bdu = 0x00000000;
+	bdp->ebd_status = RX_BD_INT;
+#endif
+#ifdef CONFIG_FEC_1588
+		bdp->cbd_esc = BD_ENET_RX_INT;
+#endif
+		bdp++;
+	}
+
+	/* Set the last buffer to wrap. */
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+
+	bdp = fep->tx_bd_base;
+	for (i = 0; i < TX_RING_SIZE; i++) {
+		fep->tx_bounce[i] = kmalloc(SWITCH_ENET_TX_FRSIZE, GFP_KERNEL);
+
+		bdp->cbd_sc = 0;
+		bdp->cbd_bufaddr = 0;
+#ifdef CONFIG_FEC_1588
+		bdp->cbd_esc = BD_ENET_TX_INT;
+#endif
+		bdp++;
+	}
+
+	/* Set the last buffer to wrap. */
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+
+	return 0;
+}
+
+static int
+switch_enet_open(struct net_device *dev)
+{
+	int ret;
+	struct switch_enet_private *fep = netdev_priv(dev);
+	/* I should reset the ring buffers here, but I don't yet know
+	 * a simple way to do that.
+	 */
+	clk_enable(fep->clk);
+	ret = fec_enet_alloc_buffers(dev);
+	if (ret)
+		return ret;
+
+	fep->link = 0;
+#ifdef FEC_PHY
+	clk_enable(fep->clk);
+	fec_switch_init_phy(dev);
+	phy_start(fep->phydev);
+#endif
+	fep->old_link = 0;
+	if (fep->phydev) {
+		/*
+		 * Set the initial link state to true. A lot of hardware
+		 * based on this device does not implement a PHY interrupt,
+		 * so we are never notified of link change.
+		 */
+		fep->link = 1;
+	} else {
+		fep->link = 1;
+		/* no phy,  go full duplex,  it's most likely a hub chip */
+		switch_restart(dev, 1);
+	}
+
+	/*
+	 * if the fec is the fist open, we need to do nothing
+	 * if the fec is not the fist open, we need to restart the FEC
+	 */
+	if (fep->sequence_done == 0)
+		switch_restart(dev, 1);
+	else
+		fep->sequence_done = 0;
+
+	fep->currTime = 0;
+	fep->learning_irqhandle_enable = 0;
+
+	esw_main(fep);
+
+	netif_start_queue(dev);
+	fep->opened = 1;
+
+	return 0;		/* Success */
+}
+
+static int
+switch_enet_close(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+
+	fep->opened = 0;
+	netif_stop_queue(dev);
+	switch_stop(dev);
+#ifdef FEC_PHY
+	phy_disconnect(fep->phydev);
+	phy_stop(fep->phydev);
+	phy_write(fep->phydev, MII_BMCR, BMCR_PDOWN);
+#endif
+	fec_enet_free_buffers(dev);
+	clk_disable(fep->clk);
+
+	return 0;
+}
+
+/*
+ * Set or clear the multicast filter for this adaptor.
+ * Skeleton taken from sunlance driver.
+ * The CPM Ethernet implementation allows Multicast as well as individual
+ * MAC address filtering.  Some of the drivers check to make sure it is
+ * a group multicast address, and discard those that are not.  I guess I
+ * will do the same for now, but just remove the test if you want
+ * individual filtering as well (do the upper net layers want or support
+ * this kind of feature?).
+ */
+
+/* bits in hash */
+#define HASH_BITS	6
+#define CRC32_POLY	0xEDB88320
+
+static void set_multicast_list(struct net_device *dev)
+{
+	struct switch_enet_private *fep;
+	struct switch_t *ep;
+	struct dev_mc_list *dmi;
+	unsigned int i, j, bit, data, crc;
+
+	fep = netdev_priv(dev);
+	ep = fep->hwp;
+
+	if (dev->flags & IFF_PROMISC) {
+		/* ep->fec_r_cntrl |= 0x0008; */
+		printk(KERN_INFO "%s IFF_PROMISC\n", __func__);
+	} else {
+
+		/* ep->fec_r_cntrl &= ~0x0008; */
+
+		if (dev->flags & IFF_ALLMULTI) {
+			/*
+			 * Catch all multicast addresses, so set the
+			 * filter to all 1's.
+			 */
+			printk(KERN_INFO "%s IFF_ALLMULTI\n", __func__);
+		} else {
+			/*
+			 * Clear filter and add the addresses
+			 * in hash register
+			 */
+			/*
+			 * ep->fec_grp_hash_table_high = 0;
+			 * ep->fec_grp_hash_table_low = 0;
+			 */
+
+			dmi = dev->mc_list;
+
+			for (j = 0; j < dev->mc_count;
+				j++, dmi = dmi->next) {
+				/* Only support group multicast for now */
+				if (!(dmi->dmi_addr[0] & 1))
+					continue;
+
+				/* calculate crc32 value of mac address	*/
+				crc = 0xffffffff;
+
+				for (i = 0; i < dmi->dmi_addrlen; i++) {
+					data = dmi->dmi_addr[i];
+					for (bit = 0; bit < 8; bit++,
+						data >>= 1) {
+						crc = (crc >> 1) ^
+						(((crc ^ data) & 1) ?
+						CRC32_POLY : 0);
+					}
+				}
+
+			}
+		}
+	}
+}
+
+/* Set a MAC change in hardware */
+static int
+switch_set_mac_address(struct net_device *dev, void *p)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	struct sockaddr *addr = p;
+	struct switch_t  *fecp;
+
+	if (!is_valid_ether_addr(addr->sa_data))
+		return -EADDRNOTAVAIL;
+
+	fecp = fep->hwp;
+	fecp->ESW_DBCR = MCF_ESW_DBCR_P1;
+
+	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+
+	writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
+		(dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
+		fep->enet_addr + MCF_FEC_PAUR0);
+	writel((dev->dev_addr[5] << 16)
+		| ((dev->dev_addr[4]+(unsigned char)(0)) << 24),
+		fep->enet_addr + MCF_FEC_PAUR0);
+
+	writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
+		(dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
+		fep->enet_addr + MCF_FEC_PAUR1);
+	writel((dev->dev_addr[5] << 16)
+		| ((dev->dev_addr[4]+(unsigned char)(1)) << 24),
+		fep->enet_addr + MCF_FEC_PAUR1);
+
+	esw_update_atable_static(dev->dev_addr, 7, 7, fep);
+	fecp->ESW_DBCR = MCF_ESW_DBCR_P1 | MCF_ESW_DBCR_P2;
+
+	return 0;
+}
+
+static struct ethtool_ops fec_enet_ethtool_ops = {
+	.get_settings           = fec_enet_get_settings,
+	.set_settings           = fec_enet_set_settings,
+	.get_drvinfo            = fec_enet_get_drvinfo,
+	.get_link               = ethtool_op_get_link,
+ };
+static const struct net_device_ops fec_netdev_ops = {
+       .ndo_open		= switch_enet_open,
+       .ndo_stop		= switch_enet_close,
+       .ndo_do_ioctl		= switch_enet_ioctl,
+       .ndo_start_xmit		= switch_enet_start_xmit,
+       .ndo_set_multicast_list	= set_multicast_list,
+       .ndo_tx_timeout		= switch_timeout,
+       .ndo_set_mac_address	= switch_set_mac_address,
+};
+
+static int switch_mac_addr_setup(char *mac_addr)
+{
+	char *ptr, *p = mac_addr;
+	unsigned long tmp;
+	int i = 0, ret = 0;
+
+	while (p && (*p) && i < 6) {
+		ptr = strchr(p, ':');
+		if (ptr)
+			*ptr++ = '\0';
+		if (strlen(p)) {
+			ret = strict_strtoul(p, 16, &tmp);
+			if (ret < 0 || tmp > 0xff)
+				break;
+			switch_mac_default[i++] = tmp;
+		}
+		p = ptr;
+	}
+
+	return 0;
+}
+
+__setup("fec_mac=", switch_mac_addr_setup);
+
+/* Initialize the FEC Ethernet */
+static int __init switch_enet_init(struct net_device *dev,
+	int slot, struct platform_device *pdev)
+{
+	struct switch_enet_private	*fep = netdev_priv(dev);
+	struct resource 	*r;
+	struct cbd_t		*bdp;
+	struct cbd_t		*cbd_base;
+	struct switch_t	*fecp;
+	int	i;
+	struct switch_platform_data *plat = pdev->dev.platform_data;
+
+	/* Only allow us to be probed once. */
+	if (slot >= SWITCH_MAX_PORTS)
+		return -ENXIO;
+
+	/* Allocate memory for buffer descriptors */
+	cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
+			 GFP_KERNEL);
+	if (!cbd_base) {
+		printk(KERN_ERR "FEC: allocate descriptor memory failed?\n");
+		return -ENOMEM;
+	}
+
+	spin_lock_init(&fep->hw_lock);
+	spin_lock_init(&fep->mii_lock);
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!r)
+		return -ENXIO;
+
+	r = request_mem_region(r->start, resource_size(r), pdev->name);
+	if (!r)
+		return -EBUSY;
+
+	fep->enet_addr = ioremap(r->start, resource_size(r));
+
+	dev->irq = platform_get_irq(pdev, 0);
+
+	/*
+	 * Create an Ethernet device instance.
+	 * The switch lookup address memory start 0x800FC000
+	 */
+	fecp = (struct switch_t *)(fep->enet_addr + ENET_SWI_PHYS_ADDR_OFFSET
+		/ sizeof(unsigned long));
+	plat->switch_hw[1] = (unsigned long)fecp + MCF_ESW_LOOKUP_MEM_OFFSET;
+
+	fep->index = slot;
+	fep->hwp = fecp;
+	fep->hwentry = (struct eswAddrTable_t *)plat->switch_hw[1];
+	fep->netdev = dev;
+#ifdef CONFIG_FEC_SHARED_PHY
+	fep->phy_hwp = (struct switch_t *) plat->switch_hw[slot & ~1];
+#else
+	fep->phy_hwp = fecp;
+#endif
+
+	fep->clk = clk_get(&pdev->dev, "fec_clk");
+	if (IS_ERR(fep->clk))
+		return PTR_ERR(fep->clk);
+	clk_enable(fep->clk);
+
+
+	/* PHY reset should be done during clock on */
+	if (plat) {
+		fep->phy_interface = plat->fec_enet->phy;
+		if (plat->fec_enet->init && plat->fec_enet->init())
+			return -EIO;
+	} else
+		fep->phy_interface = PHY_INTERFACE_MODE_MII;
+
+	/*
+	 * SWITCH CONFIGURATION
+	 */
+	fecp->ESW_MODE = MCF_ESW_MODE_SW_RST;
+	udelay(10);
+
+	/* enable switch*/
+	fecp->ESW_MODE = MCF_ESW_MODE_STATRST;
+	fecp->ESW_MODE = MCF_ESW_MODE_SW_EN;
+
+	/* Enable transmit/receive on all ports */
+	fecp->ESW_PER = 0xffffffff;
+	/* Management port configuration,
+	 * make port 0 as management port
+	 */
+	fecp->ESW_BMPC = 0;
+
+	/* clear all switch irq */
+	fecp->switch_ievent = 0xffffffff;
+	fecp->switch_imask  = 0;
+	udelay(10);
+
+	plat->request_intrs = switch_request_intrs;
+	plat->set_mii = switch_set_mii;
+	plat->get_mac = switch_get_mac;
+	plat->enable_phy_intr = switch_enable_phy_intr;
+	plat->disable_phy_intr = switch_disable_phy_intr;
+	plat->phy_ack_intr = switch_phy_ack_intr;
+	plat->localhw_setup = switch_localhw_setup;
+	plat->uncache = switch_uncache;
+	plat->platform_flush_cache = switch_platform_flush_cache;
+
+	/*
+	 * Set the Ethernet address.  If using multiple Enets on the 8xx,
+	 * this needs some work to get unique addresses.
+	 *
+	 * This is our default MAC address unless the user changes
+	 * it via eth_mac_addr (our dev->set_mac_addr handler).
+	 */
+	if (plat && plat->get_mac)
+		plat->get_mac(dev);
+
+	/* Set receive and transmit descriptor base */
+	fep->rx_bd_base = cbd_base;
+	fep->tx_bd_base = cbd_base + RX_RING_SIZE;
+
+	/* Initialize the receive buffer descriptors */
+	bdp = fep->rx_bd_base;
+	for (i = 0; i < RX_RING_SIZE; i++) {
+		bdp->cbd_sc = 0;
+
+#ifdef L2SWITCH_ENHANCED_BUFFER
+		bdp->bdu = 0x00000000;
+		bdp->ebd_status = RX_BD_INT;
+#endif
+		bdp++;
+	}
+
+	/* Set the last buffer to wrap */
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+
+	/* ...and the same for transmmit */
+	bdp = fep->tx_bd_base;
+	for (i = 0; i < TX_RING_SIZE; i++) {
+		/* Initialize the BD for every fragment in the page */
+		bdp->cbd_sc = 0;
+		bdp->cbd_bufaddr = 0;
+		bdp++;
+	}
+
+	/* Set the last buffer to wrap */
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+
+	/*
+	 * Install our interrupt handlers. This varies depending on
+	 * the architecture.
+	 */
+	if (plat && plat->request_intrs)
+		plat->request_intrs(dev, switch_enet_interrupt, dev);
+
+	dev->base_addr = (unsigned long)fecp;
+
+	/* The FEC Ethernet specific entries in the device structure. */
+	dev->netdev_ops = &fec_netdev_ops;
+	dev->ethtool_ops = &fec_enet_ethtool_ops;
+
+	/* setup MII interface */
+	if (plat && plat->set_mii)
+		plat->set_mii(dev);
+
+
+#ifndef CONFIG_FEC_SHARED_PHY
+	fep->phy_addr = 0;
+#else
+	fep->phy_addr = fep->index;
+#endif
+
+	fep->sequence_done = 1;
+	return 0;
+}
+
+static void enet_reset(struct net_device *dev, int duplex)
+{
+	struct switch_enet_private	*fep = netdev_priv(dev);
+
+	/* ECR */
+#ifdef L2SWITCH_ENHANCED_BUFFER
+	writel(MCF_FEC_ECR_ENA_1588
+			| MCF_FEC_ECR_MAGIC_ENA,
+			fep->enet_addr + MCF_FEC_ECR0);
+	writel(MCF_FEC_ECR_ENA_1588,
+			| MCF_FEC_ECR_MAGIC_ENA,
+			fep->enet_addr + MCF_FEC_ECR1);
+#else /*legac buffer*/
+	writel(MCF_FEC_ECR_MAGIC_ENA,
+			fep->enet_addr + MCF_FEC_ECR0);
+	writel(MCF_FEC_ECR_MAGIC_ENA,
+			fep->enet_addr + MCF_FEC_ECR1);
+#endif
+	/* EMRBR */
+	writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR0);
+	writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR1);
+
+	/*
+	 * set the receive and transmit BDs ring base to
+	 * hardware registers(ERDSR & ETDSR)
+	 */
+	writel(fep->bd_dma, fep->enet_addr + MCF_FEC_ERDSR0);
+	writel(fep->bd_dma, fep->enet_addr + MCF_FEC_ERDSR1);
+	writel((unsigned long)fep->bd_dma + sizeof(struct cbd_t) * RX_RING_SIZE,
+			fep->enet_addr + MCF_FEC_ETDSR0);
+	writel((unsigned long)fep->bd_dma + sizeof(struct cbd_t) * RX_RING_SIZE,
+			fep->enet_addr + MCF_FEC_ETDSR1);
+#ifdef CONFIG_ARCH_MXS
+	/* Can't get phy(8720) ID when set to 2.5M on MX28, lower it */
+	writel(fep->phy_speed,
+			fep->enet_addr + MCF_FEC_MSCR0);
+	writel(fep->phy_speed,
+			fep->enet_addr + MCF_FEC_MSCR1);
+#endif
+	fep->full_duplex = duplex;
+
+	/* EIR */
+	writel(0, fep->enet_addr + MCF_FEC_EIR0);
+	writel(0, fep->enet_addr + MCF_FEC_EIR1);
+
+	/* IAUR */
+	writel(0, fep->enet_addr + MCF_FEC_IAUR0);
+	writel(0, fep->enet_addr + MCF_FEC_IAUR1);
+
+	/* IALR */
+	writel(0, fep->enet_addr + MCF_FEC_IALR0);
+	writel(0, fep->enet_addr + MCF_FEC_IALR1);
+
+	/* GAUR */
+	writel(0, fep->enet_addr + MCF_FEC_GAUR0);
+	writel(0, fep->enet_addr + MCF_FEC_GAUR1);
+
+	/* GALR */
+	writel(0, fep->enet_addr + MCF_FEC_GALR0);
+	writel(0, fep->enet_addr + MCF_FEC_GALR1);
+
+	/* EMRBR */
+	writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR0);
+	writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR1);
+	msleep(10);
+
+	/* EIMR */
+	writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->enet_addr + MCF_FEC_EIMR0);
+	writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->enet_addr + MCF_FEC_EIMR1);
+
+	/* PALR PAUR */
+	/* Set the station address for the ENET Adapter */
+	writel(dev->dev_addr[3] |
+		dev->dev_addr[2]<<8 |
+		dev->dev_addr[1]<<16 |
+		dev->dev_addr[0]<<24, fep->enet_addr + MCF_FEC_PALR0);
+	writel(dev->dev_addr[5]<<16 |
+		(dev->dev_addr[4]+(unsigned char)(0))<<24,
+		fep->enet_addr + MCF_FEC_PAUR0);
+	writel(dev->dev_addr[3] |
+		dev->dev_addr[2]<<8 |
+		dev->dev_addr[1]<<16 |
+		dev->dev_addr[0]<<24, fep->enet_addr + MCF_FEC_PALR1);
+	writel(dev->dev_addr[5]<<16 |
+		(dev->dev_addr[4]+(unsigned char)(1))<<24,
+		fep->enet_addr + MCF_FEC_PAUR1);
+
+	/* RCR */
+	writel(readl(fep->enet_addr + MCF_FEC_RCR0)
+		| MCF_FEC_RCR_FCE | MCF_FEC_RCR_PROM,
+		fep->enet_addr + MCF_FEC_RCR0);
+	writel(readl(fep->enet_addr + MCF_FEC_RCR1)
+		| MCF_FEC_RCR_FCE | MCF_FEC_RCR_PROM,
+		fep->enet_addr + MCF_FEC_RCR1);
+
+	/* TCR */
+	writel(0x1c, fep->enet_addr + MCF_FEC_TCR0);
+	writel(0x1c, fep->enet_addr + MCF_FEC_TCR1);
+
+	/* ECR */
+	writel(readl(fep->enet_addr + MCF_FEC_ECR0) | MCF_FEC_ECR_ETHER_EN,
+			fep->enet_addr + MCF_FEC_ECR0);
+	writel(readl(fep->enet_addr + MCF_FEC_ECR1) | MCF_FEC_ECR_ETHER_EN,
+			fep->enet_addr + MCF_FEC_ECR1);
+}
+
+/*
+ * This function is called to start or restart the FEC during a link
+ * change.  This only happens when switching between half and full
+ * duplex.
+ */
+static void
+switch_restart(struct net_device *dev, int duplex)
+{
+	struct switch_enet_private *fep;
+	struct switch_t *fecp;
+	int i;
+	struct switch_platform_data *plat;
+
+	fep = netdev_priv(dev);
+	fecp = fep->hwp;
+	plat = fep->pdev->dev.platform_data;
+	/*
+	 * Whack a reset.  We should wait for this.
+	 */
+	/* fecp->fec_ecntrl = 1; */
+	fecp->ESW_MODE = MCF_ESW_MODE_SW_RST;
+	udelay(10);
+	fecp->ESW_MODE = MCF_ESW_MODE_STATRST;
+	fecp->ESW_MODE = MCF_ESW_MODE_SW_EN;
+
+	/* Enable transmit/receive on all ports */
+	fecp->ESW_PER = 0xffffffff;
+	/*
+	 * Management port configuration,
+	 * make port 0 as management port
+	 */
+	fecp->ESW_BMPC = 0;
+
+	/* Clear any outstanding interrupt */
+	fecp->switch_ievent = 0xffffffff;
+	/*if (plat && plat->enable_phy_intr)
+	 *	plat->enable_phy_intr();
+	 */
+
+	/* Reset all multicast */
+	/*
+	 * fecp->fec_grp_hash_table_high = 0;
+	 * fecp->fec_grp_hash_table_low = 0;
+	 */
+
+	/* Set maximum receive buffer size */
+	fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
+
+	if (plat && plat->localhw_setup)
+		plat->localhw_setup();
+
+	/* Set receive and transmit descriptor base */
+	fecp->fec_r_des_start = fep->bd_dma;
+	fecp->fec_x_des_start = (unsigned long)fep->bd_dma
+		+ sizeof(struct cbd_t) * RX_RING_SIZE;
+
+	fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
+	fep->cur_rx = fep->rx_bd_base;
+
+	/* Reset SKB transmit buffers */
+	fep->skb_cur = fep->skb_dirty = 0;
+	for (i = 0; i <= TX_RING_MOD_MASK; i++) {
+		if (fep->tx_skbuff[i] != NULL) {
+			dev_kfree_skb_any(fep->tx_skbuff[i]);
+			fep->tx_skbuff[i] = NULL;
+		}
+	}
+
+	enet_reset(dev, duplex);
+	esw_clear_atable(fep);
+
+	/* And last, enable the transmit and receive processing */
+	fecp->fec_r_des_active = MCF_ESW_RDAR_R_DES_ACTIVE;
+
+	/* Enable interrupts we wish to service */
+	fecp->switch_ievent = 0xffffffff;
+	fecp->switch_imask  = MCF_ESW_IMR_RXF | MCF_ESW_IMR_TXF |
+		MCF_ESW_IMR_RXB | MCF_ESW_IMR_TXB;
+
+#ifdef SWITCH_DEBUG
+	printk(KERN_INFO "%s: switch hw init over."
+		"isr %x mask %x rx_addr %x %x tx_addr %x %x."
+		"fec_r_buff_size %x\n", __func__,
+		fecp->switch_ievent, fecp->switch_imask, fecp->fec_r_des_start,
+		&fecp->fec_r_des_start, fecp->fec_x_des_start,
+		&fecp->fec_x_des_start, fecp->fec_r_buff_size);
+	printk(KERN_INFO "%s: fecp->ESW_DBCR %x, fecp->ESW_P0FFEN %x fecp->ESW_BKLR %x\n",
+		__func__, fecp->ESW_DBCR, fecp->ESW_P0FFEN, fecp->ESW_BKLR);
+
+	printk(KERN_INFO "fecp->portstats[0].MCF_ESW_POQC %x,"
+		"fecp->portstats[0].MCF_ESW_PMVID %x,"
+		"fecp->portstats[0].MCF_ESW_PMVTAG %x,"
+		"fecp->portstats[0].MCF_ESW_PBL %x\n",
+		fecp->port_statistics_status[0].MCF_ESW_POQC,
+		fecp->port_statistics_status[0].MCF_ESW_PMVID,
+		fecp->port_statistics_status[0].MCF_ESW_PMVTAG,
+		fecp->port_statistics_status[0].MCF_ESW_PBL);
+
+	printk(KERN_INFO "fecp->portstats[1].MCF_ESW_POQC %x,"
+		"fecp->portstats[1].MCF_ESW_PMVID %x,"
+		"fecp->portstats[1].MCF_ESW_PMVTAG %x,"
+		"fecp->portstats[1].MCF_ESW_PBL %x\n",
+		fecp->port_statistics_status[1].MCF_ESW_POQC,
+		fecp->port_statistics_status[1].MCF_ESW_PMVID,
+		fecp->port_statistics_status[1].MCF_ESW_PMVTAG,
+		fecp->port_statistics_status[1].MCF_ESW_PBL);
+
+	printk(KERN_INFO "fecp->portstats[2].MCF_ESW_POQC %x,"
+		"fecp->portstats[2].MCF_ESW_PMVID %x,"
+		"fecp->portstats[2].MCF_ESW_PMVTAG %x,"
+		"fecp->portstats[2].MCF_ESW_PBL %x\n",
+		fecp->port_statistics_status[2].MCF_ESW_POQC,
+		fecp->port_statistics_status[2].MCF_ESW_PMVID,
+		fecp->port_statistics_status[2].MCF_ESW_PMVTAG,
+		fecp->port_statistics_status[2].MCF_ESW_PBL);
+#endif
+}
+
+static void
+switch_stop(struct net_device *dev)
+{
+	struct switch_t *fecp;
+	struct switch_enet_private *fep;
+	struct switch_platform_data *plat;
+
+#ifdef SWITCH_DEBUG
+	printk(KERN_ERR "%s\n", __func__);
+#endif
+	fep = netdev_priv(dev);
+	fecp = fep->hwp;
+	plat = fep->pdev->dev.platform_data;
+	/* We cannot expect a graceful transmit stop without link !!! */
+	if (fep->link)
+		udelay(10);
+
+	/* Whack a reset.  We should wait for this */
+	udelay(10);
+}
+
+#ifdef FEC_PHY
+static int fec_mdio_register(struct net_device *dev,
+	int slot)
+{
+	int err = 0;
+	struct switch_enet_private *fep = netdev_priv(dev);
+
+	fep->mdio_bus = mdiobus_alloc();
+	if (!fep->mdio_bus) {
+		printk(KERN_ERR "ethernet switch mdiobus_alloc fail\n");
+		return -ENOMEM;
+	}
+
+	if (slot == 0) {
+		fep->mdio_bus->name = "FEC switch MII 0 Bus";
+		strcpy(fep->mdio_bus->id, "0");
+	} else if (slot == 1) {
+		fep->mdio_bus->name = "FEC switch MII 1 Bus";
+		strcpy(fep->mdio_bus->id, "1");
+	} else {
+		printk(KERN_ERR "Now Fec switch can not"
+			"support more than 2 mii bus\n");
+	}
+
+	fep->mdio_bus->read = &fec_enet_mdio_read;
+	fep->mdio_bus->write = &fec_enet_mdio_write;
+	fep->mdio_bus->priv = dev;
+	err = mdiobus_register(fep->mdio_bus);
+	if (err) {
+		mdiobus_free(fep->mdio_bus);
+		printk(KERN_ERR "%s: ethernet mdiobus_register fail\n",
+			dev->name);
+		return -EIO;
+	}
+
+	printk(KERN_INFO "mdiobus_register %s ok\n",
+		fep->mdio_bus->name);
+	return err;
+}
+#endif
+
+static int __init eth_switch_probe(struct platform_device *pdev)
+{
+	struct net_device *dev;
+	int i, err;
+	struct switch_enet_private *fep;
+	struct switch_platform_private *chip;
+
+	printk(KERN_INFO "Ethernet Switch Version 1.0\n");
+	chip = kzalloc(sizeof(struct switch_platform_private) +
+		sizeof(struct switch_enet_private *) * SWITCH_MAX_PORTS,
+		GFP_KERNEL);
+	if (!chip) {
+		err = -ENOMEM;
+		printk(KERN_ERR "%s: kzalloc fail %x\n", __func__,
+			(unsigned int)chip);
+		return err;
+	}
+
+	chip->pdev = pdev;
+	chip->num_slots = SWITCH_MAX_PORTS;
+	platform_set_drvdata(pdev, chip);
+
+	for (i = 0; (i < chip->num_slots); i++) {
+		dev = alloc_etherdev(sizeof(struct switch_enet_private));
+		if (!dev) {
+			printk(KERN_ERR "%s: ethernet switch\
+				 alloc_etherdev fail\n",
+				dev->name);
+			return -ENOMEM;
+		}
+
+		fep = netdev_priv(dev);
+		fep->pdev = pdev;
+		printk(KERN_ERR "%s: ethernet switch port %d init\n",
+			__func__, i);
+		err = switch_enet_init(dev, i, pdev);
+		if (err) {
+			free_netdev(dev);
+			platform_set_drvdata(pdev, NULL);
+			kfree(chip);
+			continue;
+		}
+
+		chip->fep_host[i] = fep;
+		/* disable mdio */
+#ifdef FEC_PHY
+#ifdef CONFIG_FEC_SHARED_PHY
+		if (i == 0)
+			err = fec_mdio_register(dev, 0);
+		else {
+			fep->mdio_bus = chip->fep_host[0]->mdio_bus;
+			printk(KERN_INFO "FEC%d SHARED the %s ok\n",
+				i, fep->mdio_bus->name);
+		}
+#else
+		err = fec_mdio_register(dev, i);
+#endif
+		if (err) {
+			printk(KERN_ERR "%s: ethernet switch fec_mdio_register\n",
+				dev->name);
+			free_netdev(dev);
+			platform_set_drvdata(pdev, NULL);
+			kfree(chip);
+			return -ENOMEM;
+		}
+#endif
+		/* setup timer for Learning  Aging function */
+		/*
+		 * setup_timer(&fep->timer_aging,
+		 *	l2switch_aging_timer, (unsigned long)fep);
+		 */
+		init_timer(&fep->timer_aging);
+		fep->timer_aging.function = l2switch_aging_timer;
+		fep->timer_aging.data = (unsigned long) fep;
+		fep->timer_aging.expires = jiffies + LEARNING_AGING_TIMER;
+
+		/* register network device */
+		if (register_netdev(dev) != 0) {
+			free_netdev(dev);
+			platform_set_drvdata(pdev, NULL);
+			kfree(chip);
+			printk(KERN_ERR "%s: ethernet switch register_netdev fail\n",
+				dev->name);
+			return -EIO;
+		}
+		printk(KERN_INFO "%s: ethernet switch %pM\n",
+				dev->name, dev->dev_addr);
+	}
+
+	return 0;
+}
+
+static int eth_switch_remove(struct platform_device *pdev)
+{
+	int i;
+	struct net_device *dev;
+	struct switch_enet_private *fep;
+	struct switch_platform_private *chip;
+
+	chip = platform_get_drvdata(pdev);
+	if (chip) {
+		for (i = 0; i < chip->num_slots; i++) {
+			fep = chip->fep_host[i];
+			dev = fep->netdev;
+			fep->sequence_done = 1;
+			unregister_netdev(dev);
+			free_netdev(dev);
+
+			del_timer_sync(&fep->timer_aging);
+		}
+
+		platform_set_drvdata(pdev, NULL);
+		kfree(chip);
+
+	} else
+		printk(KERN_ERR "%s: can not get the "
+			"switch_platform_private %x\n", __func__,
+			(unsigned int)chip);
+
+	return 0;
+}
+
+static struct platform_driver eth_switch_driver = {
+	.probe          = eth_switch_probe,
+	.remove         = eth_switch_remove,
+	.driver         = {
+		.name   = "mxs-l2switch",
+		.owner  = THIS_MODULE,
+	},
+};
+
+static int __init fec_l2switch_init(void)
+{
+	return platform_driver_register(&eth_switch_driver);;
+}
+
+static void __exit fec_l2_switch_exit(void)
+{
+	platform_driver_unregister(&eth_switch_driver);
+}
+
+module_init(fec_l2switch_init);
+module_exit(fec_l2_switch_exit);
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/fec_switch.h b/drivers/net/fec_switch.h
new file mode 100644
index 000000000000..7b9f6a180f6a
--- /dev/null
+++ b/drivers/net/fec_switch.h
@@ -0,0 +1,1121 @@
+/****************************************************************************/
+
+/*
+ *	mcfswitch -- L2 Switch Controller for Modelo ColdFire SoC
+ *		   processors.
+ *
+ *      Copyright (C) 2010 Freescale Semiconductor,Inc.All rights reserved.
+ *
+ *     This program is free software; you can redistribute it and/or modify
+ *     it under the terms of the GNU General Public License as published by
+ *     the Free Software Foundation; either version 2 of the License, or (at
+ *     your option) any later version.
+ *
+ */
+
+/****************************************************************************/
+#ifndef SWITCH_H
+#define	SWITCH_H
+/****************************************************************************/
+/* The Switch stores dest/src/type, data, and checksum for receive packets.
+ */
+#define PKT_MAXBUF_SIZE         1518
+#define PKT_MINBUF_SIZE         64
+#define PKT_MAXBLR_SIZE         1520
+
+/*
+ * The 5441x RX control register also contains maximum frame
+ * size bits.
+ */
+#define OPT_FRAME_SIZE  (PKT_MAXBUF_SIZE << 16)
+
+/*
+ * Some hardware gets it MAC address out of local flash memory.
+ * if this is non-zero then assume it is the address to get MAC from.
+ */
+#define FEC_FLASHMAC    0
+
+/* The number of Tx and Rx buffers.  These are allocated from the page
+ * pool.  The code may assume these are power of two, so it it best
+ * to keep them that size.
+ * We don't need to allocate pages for the transmitter.  We just use
+ * the skbuffer directly.
+ */
+#ifdef CONFIG_SWITCH_DMA_USE_SRAM
+#define SWITCH_ENET_RX_PAGES       6
+#else
+#define SWITCH_ENET_RX_PAGES       8
+#endif
+
+#define SWITCH_ENET_RX_FRSIZE      2048
+#define SWITCH_ENET_RX_FRPPG       (PAGE_SIZE / SWITCH_ENET_RX_FRSIZE)
+#define RX_RING_SIZE            (SWITCH_ENET_RX_FRPPG * SWITCH_ENET_RX_PAGES)
+#define SWITCH_ENET_TX_FRSIZE      2048
+#define SWITCH_ENET_TX_FRPPG       (PAGE_SIZE / SWITCH_ENET_TX_FRSIZE)
+
+#ifdef CONFIG_SWITCH_DMA_USE_SRAM
+#define TX_RING_SIZE            8      /* Must be power of two */
+#define TX_RING_MOD_MASK        7      /*   for this to work */
+#else
+#define TX_RING_SIZE            16      /* Must be power of two */
+#define TX_RING_MOD_MASK        15      /*   for this to work */
+#endif
+
+#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
+#error "L2SWITCH: descriptor ring size constants too large"
+#endif
+/*-----------------------------------------------------------------------*/
+struct esw_output_queue_status {
+	unsigned long ESW_MMSR;
+	unsigned long ESW_LMT;
+	unsigned long ESW_LFC;
+	unsigned long ESW_PCSR;
+	unsigned long ESW_IOSR;
+	unsigned long ESW_QWT;
+	unsigned long esw_reserved;
+	unsigned long ESW_P0BCT;
+};
+struct esw_statistics_status {
+	/*
+	 * Total number of incoming frames processed
+	 * but discarded in switch
+	 */
+	unsigned long ESW_DISCN;
+	/*Sum of bytes of frames counted in ESW_DISCN*/
+	unsigned long ESW_DISCB;
+	/*
+	 * Total number of incoming frames processed
+	 * but not discarded in switch
+	 */
+	unsigned long ESW_NDISCN;
+	/*Sum of bytes of frames counted in ESW_NDISCN*/
+	unsigned long ESW_NDISCB;
+};
+
+struct esw_port_statistics_status {
+	/*outgoing frames discarded due to transmit queue congestion*/
+	unsigned long MCF_ESW_POQC;
+	/*incoming frames discarded due to VLAN domain mismatch*/
+	unsigned long MCF_ESW_PMVID;
+	/*incoming frames discarded due to untagged discard*/
+	unsigned long MCF_ESW_PMVTAG;
+	/*incoming frames discarded due port is in blocking state*/
+	unsigned long MCF_ESW_PBL;
+};
+
+struct switch_t {
+	unsigned long ESW_REVISION;
+	unsigned long ESW_SCRATCH;
+	unsigned long ESW_PER;
+	unsigned long reserved0[1];
+	unsigned long ESW_VLANV;
+	unsigned long ESW_DBCR;
+	unsigned long ESW_DMCR;
+	unsigned long ESW_BKLR;
+	unsigned long ESW_BMPC;
+	unsigned long ESW_MODE;
+	unsigned long ESW_VIMSEL;
+	unsigned long ESW_VOMSEL;
+	unsigned long ESW_VIMEN;
+	unsigned long ESW_VID;/*0x34*/
+	/*from 0x38 0x3C*/
+	unsigned long esw_reserved0[2];
+	unsigned long ESW_MCR;/*0x40*/
+	unsigned long ESW_EGMAP;
+	unsigned long ESW_INGMAP;
+	unsigned long ESW_INGSAL;
+	unsigned long ESW_INGSAH;
+	unsigned long ESW_INGDAL;
+	unsigned long ESW_INGDAH;
+	unsigned long ESW_ENGSAL;
+	unsigned long ESW_ENGSAH;
+	unsigned long ESW_ENGDAL;
+	unsigned long ESW_ENGDAH;
+	unsigned long ESW_MCVAL;/*0x6C*/
+	/*from 0x70--0x7C*/
+	unsigned long esw_reserved1[4];
+	unsigned long ESW_MMSR;/*0x80*/
+	unsigned long ESW_LMT;
+	unsigned long ESW_LFC;
+	unsigned long ESW_PCSR;
+	unsigned long ESW_IOSR;
+	unsigned long ESW_QWT;/*0x94*/
+	unsigned long esw_reserved2[1];/*0x98*/
+	unsigned long ESW_P0BCT;/*0x9C*/
+	/*from 0xA0-0xB8*/
+	unsigned long esw_reserved3[7];
+	unsigned long ESW_P0FFEN;/*0xBC*/
+	unsigned long ESW_PSNP[8];
+	unsigned long ESW_IPSNP[8];
+	unsigned long ESW_PVRES[3];
+	/*from 0x10C-0x13C*/
+	unsigned long esw_reserved4[13];
+	unsigned long ESW_IPRES;/*0x140*/
+	/*from 0x144-0x17C*/
+	unsigned long esw_reserved5[15];
+	unsigned long ESW_PRES[3];
+	/*from 0x18C-0x1FC*/
+	unsigned long esw_reserved6[29];
+	unsigned long ESW_PID[3];
+	/*from 0x20C-0x27C*/
+	unsigned long esw_reserved7[29];
+	unsigned long ESW_VRES[32];
+	unsigned long ESW_DISCN;/*0x300*/
+	unsigned long ESW_DISCB;
+	unsigned long ESW_NDISCN;
+	unsigned long ESW_NDISCB;/*0xFC0DC30C*/
+	struct esw_port_statistics_status port_statistics_status[3];
+	/*from 0x340-0x400*/
+	unsigned long esw_reserved8[48];
+
+	/*0xFC0DC400---0xFC0DC418*/
+	/*unsigned long MCF_ESW_ISR;*/
+	unsigned long   switch_ievent;             /* Interrupt event reg */
+	/*unsigned long MCF_ESW_IMR;*/
+	unsigned long   switch_imask;              /* Interrupt mask reg */
+	/*unsigned long MCF_ESW_RDSR;*/
+	unsigned long   fec_r_des_start;        /* Receive descriptor ring */
+	/*unsigned long MCF_ESW_TDSR;*/
+	unsigned long   fec_x_des_start;        /* Transmit descriptor ring */
+	/*unsigned long MCF_ESW_MRBR;*/
+	unsigned long   fec_r_buff_size;        /* Maximum receive buff size */
+	/*unsigned long MCF_ESW_RDAR;*/
+	unsigned long   fec_r_des_active;       /* Receive descriptor reg */
+	/*unsigned long MCF_ESW_TDAR;*/
+	unsigned long   fec_x_des_active;       /* Transmit descriptor reg */
+	/*from 0x420-0x4FC*/
+	unsigned long esw_reserved9[57];
+
+	/*0xFC0DC500---0xFC0DC508*/
+	unsigned long ESW_LREC0;
+	unsigned long ESW_LREC1;
+	unsigned long ESW_LSR;
+};
+
+struct  AddrTable64bEntry {
+	unsigned int lo;  /* lower 32 bits */
+	unsigned int hi;  /* upper 32 bits */
+};
+
+struct  eswAddrTable_t {
+	struct AddrTable64bEntry  eswTable64bEntry[2048];
+};
+
+#define MCF_ESW_LOOKUP_MEM_OFFSET      0x4000
+#define ENET_SWI_PHYS_ADDR_OFFSET	0x8000
+#define MCF_ESW_PER	(0x08 / sizeof(unsigned long))
+#define MCF_ESW_DBCR	(0x14 / sizeof(unsigned long))
+#define MCF_ESW_IMR	(0x404 / sizeof(unsigned long))
+
+#define MCF_FEC_BASE_ADDR	(fep->enet_addr)
+#define MCF_FEC_EIR0		(0x04 / sizeof(unsigned long))
+#define MCF_FEC_EIR1		(0x4004 / sizeof(unsigned long))
+#define MCF_FEC_EIMR0		(0x08 / sizeof(unsigned long))
+#define MCF_FEC_EIMR1		(0x4008 / sizeof(unsigned long))
+#define MCF_FEC_MMFR0		(0x40 / sizeof(unsigned long))
+#define MCF_FEC_MMFR1		(0x4040 / sizeof(unsigned long))
+#define MCF_FEC_MSCR0		(0x44 / sizeof(unsigned long))
+#define MCF_FEC_MSCR1		(0x4044 / sizeof(unsigned long))
+
+#define MCF_FEC_RCR0		(0x84 / sizeof(unsigned long))
+#define MCF_FEC_RCR1		(0x4084 / sizeof(unsigned long))
+#define MCF_FEC_TCR0		(0xC4 / sizeof(unsigned long))
+#define MCF_FEC_TCR1		(0x40C4 / sizeof(unsigned long))
+#define MCF_FEC_ECR0		(0x24 / sizeof(unsigned long))
+#define MCF_FEC_ECR1		(0x4024 / sizeof(unsigned long))
+
+#define MCF_FEC_PALR0          (0xE4 / sizeof(unsigned long))
+#define MCF_FEC_PALR1          (0x40E4 / sizeof(unsigned long))
+#define MCF_FEC_PAUR0          (0xE8 / sizeof(unsigned long))
+#define MCF_FEC_PAUR1          (0x40E8 / sizeof(unsigned long))
+
+#define MCF_FEC_ERDSR0         (0x180 / sizeof(unsigned long))
+#define MCF_FEC_ERDSR1         (0x4180 / sizeof(unsigned long))
+#define MCF_FEC_ETDSR0         (0x184 / sizeof(unsigned long))
+#define MCF_FEC_ETDSR1         (0x4184 / sizeof(unsigned long))
+
+#define MCF_FEC_IAUR0          (0x118 / sizeof(unsigned long))
+#define MCF_FEC_IAUR1          (0x4118 / sizeof(unsigned long))
+#define MCF_FEC_IALR0          (0x11C / sizeof(unsigned long))
+#define MCF_FEC_IALR1          (0x411C / sizeof(unsigned long))
+
+#define MCF_FEC_GAUR0          (0x120 / sizeof(unsigned long))
+#define MCF_FEC_GAUR1          (0x4120 / sizeof(unsigned long))
+#define MCF_FEC_GALR0          (0x124 / sizeof(unsigned long))
+#define MCF_FEC_GALR1          (0x4124 / sizeof(unsigned long))
+
+#define MCF_FEC_EMRBR0         (0x188 / sizeof(unsigned long))
+#define MCF_FEC_EMRBR1         (0x4188 / sizeof(unsigned long))
+
+#define MCF_FEC_RCR_DRT	(0x00000002)
+#define MCF_FEC_RCR_PROM       (0x00000008)
+#define MCF_FEC_RCR_FCE	(0x00000020)
+#define MCF_FEC_RCR_RMII_MODE  (0x00000100)
+#define MCF_FEC_RCR_MAX_FL(x)  (((x)&0x00003FFF)<<16)
+#define MCF_FEC_RCR_CRC_FWD    (0x00004000)
+#define MCF_FEC_RCR_NO_LGTH_CHECK (0x40000000)
+#define MCF_FEC_TCR_FDEN       (0x00000004)
+
+#define MCF_FEC_ECR_RESET      (0x00000001)
+#define MCF_FEC_ECR_ETHER_EN   (0x00000002)
+#define MCF_FEC_ECR_MAGIC_ENA  (0x00000004)
+#define MCF_FEC_ECR_ENA_1588   (0x00000010)
+
+#define MCF_FEC_ERDSR(x)       ((x) << 2)
+
+/*-------------ioctl command ---------------------------------------*/
+#define ESW_SET_LEARNING_CONF               0x9101
+#define ESW_GET_LEARNING_CONF               0x9201
+#define ESW_SET_BLOCKING_CONF               0x9102
+#define ESW_GET_BLOCKING_CONF               0x9202
+#define ESW_SET_MULTICAST_CONF              0x9103
+#define ESW_GET_MULTICAST_CONF              0x9203
+#define ESW_SET_BROADCAST_CONF              0x9104
+#define ESW_GET_BROADCAST_CONF              0x9204
+#define ESW_SET_PORTENABLE_CONF             0x9105
+#define ESW_GET_PORTENABLE_CONF             0x9205
+#define ESW_SET_IP_SNOOP_CONF               0x9106
+#define ESW_GET_IP_SNOOP_CONF               0x9206
+#define ESW_SET_PORT_SNOOP_CONF             0x9107
+#define ESW_GET_PORT_SNOOP_CONF             0x9207
+#define ESW_SET_PORT_MIRROR_CONF            0x9108
+#define ESW_GET_PORT_MIRROR_CONF            0x9208
+#define ESW_SET_PIRORITY_VLAN               0x9109
+#define ESW_GET_PIRORITY_VLAN               0x9209
+#define ESW_SET_PIRORITY_IP                 0x910A
+#define ESW_GET_PIRORITY_IP                 0x920A
+#define ESW_SET_PIRORITY_MAC                0x910B
+#define ESW_GET_PIRORITY_MAC                0x920B
+#define ESW_SET_PIRORITY_DEFAULT            0x910C
+#define ESW_GET_PIRORITY_DEFAULT            0x920C
+#define ESW_SET_P0_FORCED_FORWARD           0x910D
+#define ESW_GET_P0_FORCED_FORWARD           0x920D
+#define ESW_SET_SWITCH_MODE                 0x910E
+#define ESW_GET_SWITCH_MODE                 0x920E
+#define ESW_SET_BRIDGE_CONFIG               0x910F
+#define ESW_GET_BRIDGE_CONFIG               0x920F
+#define ESW_SET_VLAN_OUTPUT_PROCESS         0x9110
+#define ESW_GET_VLAN_OUTPUT_PROCESS         0x9210
+#define ESW_SET_VLAN_INPUT_PROCESS          0x9111
+#define ESW_GET_VLAN_INPUT_PROCESS          0x9211
+#define ESW_SET_VLAN_DOMAIN_VERIFICATION    0x9112
+#define ESW_GET_VLAN_DOMAIN_VERIFICATION    0x9212
+#define ESW_SET_VLAN_RESOLUTION_TABLE       0x9113
+#define ESW_GET_VLAN_RESOLUTION_TABLE       0x9213
+
+
+#define ESW_GET_STATISTICS_STATUS           0x9221
+#define ESW_GET_PORT0_STATISTICS_STATUS     0x9222
+#define ESW_GET_PORT1_STATISTICS_STATUS     0x9223
+#define ESW_GET_PORT2_STATISTICS_STATUS     0x9224
+#define ESW_SET_OUTPUT_QUEUE_MEMORY         0x9125
+#define ESW_GET_OUTPUT_QUEUE_STATUS         0x9225
+#define ESW_UPDATE_STATIC_MACTABLE          0x9226
+#define ESW_CLEAR_ALL_MACTABLE              0x9227
+
+struct eswIoctlPortConfig {
+	int port;
+	int enable;
+};
+
+struct  eswIoctlPortEnableConfig {
+	int port;
+	int tx_enable;
+	int rx_enable;
+};
+
+struct  eswIoctlIpsnoopConfig {
+	int num;
+	int mode;
+	unsigned char ip_header_protocol;
+};
+
+struct eswIoctlP0ForcedForwardConfig {
+	int port1;
+	int port2;
+	int enable;
+};
+
+struct eswIoctlPortsnoopConfig {
+     int num;
+     int mode;
+     unsigned short compare_port;
+     int compare_num;
+};
+
+struct  eswIoctlPortMirrorConfig {
+	int mirror_port;
+	int port;
+	int egress_en;
+	int ingress_en;
+	int egress_mac_src_en;
+	int egress_mac_des_en;
+	int ingress_mac_src_en;
+	int ingress_mac_des_en;
+	unsigned char *src_mac;
+	unsigned char *des_mac;
+	int mirror_enable;
+};
+
+struct  eswIoctlPriorityVlanConfig {
+	int port;
+	int func_enable;
+	int vlan_pri_table_num;
+	int vlan_pri_table_value;
+};
+
+struct eswIoctlPriorityIPConfig {
+	int port;
+	int func_enable;
+	int ipv4_en;
+	int ip_priority_num;
+	int ip_priority_value;
+};
+
+struct  eswIoctlPriorityMacConfig {
+	int port;
+};
+
+struct  eswIoctlPriorityDefaultConfig{
+	int port;
+	unsigned char priority_value;
+};
+
+struct eswIoctlIrqStatus {
+	unsigned long isr;
+	unsigned long imr;
+	unsigned long rx_buf_pointer;
+	unsigned long tx_buf_pointer;
+	unsigned long rx_max_size;
+	unsigned long rx_buf_active;
+	unsigned long tx_buf_active;
+};
+
+struct eswIoctlPortMirrorStatus {
+	unsigned long ESW_MCR;
+	unsigned long ESW_EGMAP;
+	unsigned long ESW_INGMAP;
+	unsigned long ESW_INGSAL;
+	unsigned long ESW_INGSAH;
+	unsigned long ESW_INGDAL;
+	unsigned long ESW_INGDAH;
+	unsigned long ESW_ENGSAL;
+	unsigned long ESW_ENGSAH;
+	unsigned long ESW_ENGDAL;
+	unsigned long ESW_ENGDAH;
+	unsigned long ESW_MCVAL;
+};
+
+struct eswIoctlVlanOutputConfig {
+	int port;
+	int mode;
+};
+
+struct eswIoctlVlanInputConfig {
+	int port;
+	int mode;
+	unsigned short port_vlanid;
+	int vlan_verify_en;
+	int vlan_domain_num;
+	int vlan_domain_port;
+};
+
+struct eswIoctlVlanVerificationConfig {
+	int port;
+	int vlan_domain_verify_en;
+	int vlan_discard_unknown_en;
+};
+
+struct eswIoctlVlanResoultionTable {
+	unsigned short port_vlanid;
+	int vlan_domain_num;
+	int vlan_domain_port;
+};
+
+struct eswIoctlVlanInputStatus {
+	unsigned long ESW_VLANV;
+	unsigned long ESW_PID[3];
+	unsigned long ESW_VIMSEL;
+	unsigned long ESW_VIMEN;
+	unsigned long ESW_VRES[32];
+};
+
+struct eswIoctlUpdateStaticMACtable {
+	unsigned char *mac_addr;
+	int port;
+	int priority;
+};
+
+struct eswIoctlOutputQueue {
+	int fun_num;
+	struct esw_output_queue_status  sOutputQueue;
+};
+
+/*=============================================================*/
+#define LEARNING_AGING_TIMER (10 * HZ)
+/*
+ * Info received from Hardware Learning FIFO,
+ * holding MAC address and corresponding Hash Value and
+ * port number where the frame was received (disassembled).
+ */
+struct eswPortInfo {
+	/* MAC lower 32 bits (first byte is 7:0). */
+	unsigned int   maclo;
+	/* MAC upper 16 bits (47:32). */
+	unsigned int   machi;
+	/* the hash value for this MAC address. */
+	unsigned int   hash;
+	/* the port number this MAC address is associated with. */
+	unsigned int   port;
+};
+
+/*
+ * Hardware Look up Address Table 64-bit element.
+ */
+struct eswTable64bitEntry {
+	unsigned int lo;  /* lower 32 bits */
+	unsigned int hi;  /* upper 32 bits */
+};
+
+/*
+ * Disassembled element stored in Address Table.
+ */
+struct eswAddrTableDynamicEntry {
+	/* MAC lower 32 bits (first byte is 7:0). */
+	unsigned int maclo;
+	/* MAC upper 16 bits (47:32). */
+	unsigned int machi;
+	/* timestamp of this entry */
+	unsigned int timestamp;
+	/* the port number this MAC address is associated with */
+	unsigned int port;
+};
+
+struct eswAddrTableStaticEntry {
+	/* MAC lower 32 bits (first byte is 7:0). */
+	unsigned int maclo;
+	/* MAC upper 16 bits (47:32). */
+	unsigned int machi;
+	/* priority of this entry */
+	unsigned int priority;
+	/* the port bitmask this MAC address is associated with */
+	unsigned int portbitmask;
+};
+/*
+ *	Define the buffer descriptor structure.
+ */
+struct cbd_t {
+#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS)
+	unsigned short	cbd_datlen;		/* Data length */
+	unsigned short	cbd_sc;			/* Control and status info */
+#else
+	unsigned short	cbd_sc;			/* Control and status info */
+	unsigned short	cbd_datlen;		/* Data length */
+#endif
+	unsigned long	cbd_bufaddr;		/* Buffer address */
+#ifdef L2SWITCH_ENHANCED_BUFFER
+	unsigned long   ebd_status;
+	unsigned short  length_proto_type;
+	unsigned short  payload_checksum;
+	unsigned long   bdu;
+	unsigned long   timestamp;
+	unsigned long   reserverd_word1;
+	unsigned long   reserverd_word2;
+#endif
+};
+
+/* Forward declarations of some structures to support different PHYs
+ */
+struct phy_cmd_t {
+	uint mii_data;
+	void (*funct)(uint mii_reg, struct net_device *dev);
+};
+
+struct  phy_info_t {
+	uint id;
+	char *name;
+
+	const struct phy_cmd_t *config;
+	const struct phy_cmd_t *startup;
+	const struct phy_cmd_t *ack_int;
+	const struct phy_cmd_t *shutdown;
+};
+
+/* The switch buffer descriptors track the ring buffers.  The rx_bd_base and
+ * tx_bd_base always point to the base of the buffer descriptors.  The
+ * cur_rx and cur_tx point to the currently available buffer.
+ * The dirty_tx tracks the current buffer that is being sent by the
+ * controller.  The cur_tx and dirty_tx are equal under both completely
+ * empty and completely full conditions.  The empty/ready indicator in
+ * the buffer descriptor determines the actual condition.
+ */
+struct switch_enet_private {
+	/* Hardware registers of the switch device */
+	struct switch_t  *hwp;
+	struct eswAddrTable_t  *hwentry;
+	unsigned long *enet_addr;
+
+	struct net_device *netdev;
+	struct platform_device *pdev;
+	struct clk *clk;
+	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
+	unsigned char *tx_bounce[TX_RING_SIZE];
+	struct  sk_buff *tx_skbuff[TX_RING_SIZE];
+	struct  sk_buff *rx_skbuff[RX_RING_SIZE];
+	ushort  skb_cur;
+	ushort  skb_dirty;
+
+	/* CPM dual port RAM relative addresses */
+	dma_addr_t      bd_dma;
+	struct cbd_t   *rx_bd_base;	/* Address of Rx and Tx buffers. */
+	struct cbd_t   *tx_bd_base;
+	struct cbd_t   *cur_rx, *cur_tx;	/* The next free ring entry */
+	struct cbd_t   *dirty_tx;      /* The ring entries to be free()ed. */
+	uint    tx_full;
+	/* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
+	spinlock_t hw_lock;
+
+	/* hold while accessing the mii_list_t() elements */
+	spinlock_t mii_lock;
+	struct mii_bus *mdio_bus;
+	struct phy_device *phydev;
+	phy_interface_t phy_interface;
+
+	uint    phy_id;
+	uint    phy_id_done;
+	uint    phy_status;
+	struct	phy_info_t const        *phy;
+	struct work_struct phy_task;
+	struct switch_t  *phy_hwp;
+
+	uint    sequence_done;
+	uint    mii_phy_task_queued;
+
+	uint    phy_addr;
+
+	int     opened;
+	int     old_link;
+	int     duplex;
+	int     speed;
+	int     msg_enable;
+
+	/* --------------Statistics--------------------------- */
+	/* when a new element deleted a element with in
+	 * a block due to lack of space */
+	int atBlockOverflows;
+	/* Peak number of valid entries in the address table */
+	int atMaxEntries;
+	/* current number of valid entries in the address table */
+	int atCurrEntries;
+	/* maximum entries within a block found
+	 * (updated within ageing)*/
+	int atMaxEntriesPerBlock;
+
+	/* -------------------ageing function------------------ */
+	/* maximum age allowed for an entry */
+	int ageMax;
+	/* last LUT entry to block that was
+	 * inspected by the Ageing task*/
+	int ageLutIdx;
+	/* last element within block inspected by the Ageing task */
+	int ageBlockElemIdx;
+	/* complete table has been processed by ageing process */
+	int ageCompleted;
+	/* delay setting */
+	int ageDelay;
+	/* current delay Counter */
+	int  ageDelayCnt;
+
+	/* ----------------timer related---------------------------- */
+	/* current time (for timestamping) */
+	int currTime;
+	/* flag set by timer when currTime changed
+	 * and cleared by serving function*/
+	int timeChanged;
+
+	/**/
+	/* Timer for Aging */
+	struct timer_list       timer_aging;
+	int learning_irqhandle_enable;
+	/* Phylib and MDIO interface */
+	struct  mii_bus *mii_bus;
+	struct  phy_device *phy_dev;
+	int     mii_timeout;
+	uint    phy_speed;
+	int     index;
+	int     link;
+	int     full_duplex;
+};
+
+struct switch_platform_private {
+	struct platform_device  *pdev;
+
+	unsigned long           quirks;
+	int                     num_slots;      /* Slots on controller */
+	struct switch_enet_private *fep_host[0];      /* Pointers to hosts */
+};
+
+/******************************************************************************/
+#define FEC_IEVENT		0x004 /* Interrupt event reg */
+#define FEC_IMASK		0x008 /* Interrupt mask reg */
+#define FEC_R_DES_ACTIVE	0x010 /* Receive descriptor reg */
+#define FEC_X_DES_ACTIVE	0x014 /* Transmit descriptor reg */
+#define FEC_ECNTRL		0x024 /* Ethernet control reg */
+#define FEC_MII_DATA		0x040 /* MII manage frame reg */
+#define FEC_MII_SPEED		0x044 /* MII speed control reg */
+#define FEC_MIB_CTRLSTAT	0x064 /* MIB control/status reg */
+#define FEC_R_CNTRL		0x084 /* Receive control reg */
+#define FEC_X_CNTRL		0x0c4 /* Transmit Control reg */
+#define FEC_ADDR_LOW		0x0e4 /* Low 32bits MAC address */
+#define FEC_ADDR_HIGH		0x0e8 /* High 16bits MAC address */
+#define FEC_OPD			0x0ec /* Opcode + Pause duration */
+#define FEC_HASH_TABLE_HIGH	0x118 /* High 32bits hash table */
+#define FEC_HASH_TABLE_LOW	0x11c /* Low 32bits hash table */
+#define FEC_GRP_HASH_TABLE_HIGH	0x120 /* High 32bits hash table */
+#define FEC_GRP_HASH_TABLE_LOW	0x124 /* Low 32bits hash table */
+#define FEC_X_WMRK		0x144 /* FIFO transmit water mark */
+#define FEC_R_BOUND		0x14c /* FIFO receive bound reg */
+#define FEC_R_FSTART		0x150 /* FIFO receive start reg */
+#define FEC_R_DES_START		0x180 /* Receive descriptor ring */
+#define FEC_X_DES_START		0x184 /* Transmit descriptor ring */
+#define FEC_R_BUFF_SIZE		0x188 /* Maximum receive buff size */
+#define FEC_MIIGSK_CFGR		0x300 /* MIIGSK config register */
+#define FEC_MIIGSK_ENR		0x308 /* MIIGSK enable register */
+
+/* Recieve is empty */
+#define BD_SC_EMPTY     ((unsigned short)0x8000)
+/* Transmit is ready */
+#define BD_SC_READY     ((unsigned short)0x8000)
+/* Last buffer descriptor */
+#define BD_SC_WRAP      ((unsigned short)0x2000)
+/* Interrupt on change */
+#define BD_SC_INTRPT    ((unsigned short)0x1000)
+/* Continous mode */
+#define BD_SC_CM        ((unsigned short)0x0200)
+/* Rec'd too many idles */
+#define BD_SC_ID        ((unsigned short)0x0100)
+/* xmt preamble */
+#define BD_SC_P         ((unsigned short)0x0100)
+/* Break received */
+#define BD_SC_BR        ((unsigned short)0x0020)
+/* Framing error */
+#define BD_SC_FR        ((unsigned short)0x0010)
+/* Parity error */
+#define BD_SC_PR        ((unsigned short)0x0008)
+/* Overrun */
+#define BD_SC_OV        ((unsigned short)0x0002)
+#define BD_SC_CD        ((unsigned short)0x0001)
+
+/* Buffer descriptor control/status used by Ethernet receive.
+*/
+#define BD_ENET_RX_EMPTY        ((unsigned short)0x8000)
+#define BD_ENET_RX_WRAP         ((unsigned short)0x2000)
+#define BD_ENET_RX_INTR         ((unsigned short)0x1000)
+#define BD_ENET_RX_LAST         ((unsigned short)0x0800)
+#define BD_ENET_RX_FIRST        ((unsigned short)0x0400)
+#define BD_ENET_RX_MISS         ((unsigned short)0x0100)
+#define BD_ENET_RX_LG           ((unsigned short)0x0020)
+#define BD_ENET_RX_NO           ((unsigned short)0x0010)
+#define BD_ENET_RX_SH           ((unsigned short)0x0008)
+#define BD_ENET_RX_CR           ((unsigned short)0x0004)
+#define BD_ENET_RX_OV           ((unsigned short)0x0002)
+#define BD_ENET_RX_CL           ((unsigned short)0x0001)
+/* All status bits */
+#define BD_ENET_RX_STATS        ((unsigned short)0x013f)
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+*/
+#define BD_ENET_TX_READY        ((unsigned short)0x8000)
+#define BD_ENET_TX_PAD          ((unsigned short)0x4000)
+#define BD_ENET_TX_WRAP         ((unsigned short)0x2000)
+#define BD_ENET_TX_INTR         ((unsigned short)0x1000)
+#define BD_ENET_TX_LAST         ((unsigned short)0x0800)
+#define BD_ENET_TX_TC           ((unsigned short)0x0400)
+#define BD_ENET_TX_DEF          ((unsigned short)0x0200)
+#define BD_ENET_TX_HB           ((unsigned short)0x0100)
+#define BD_ENET_TX_LC           ((unsigned short)0x0080)
+#define BD_ENET_TX_RL           ((unsigned short)0x0040)
+#define BD_ENET_TX_RCMASK       ((unsigned short)0x003c)
+#define BD_ENET_TX_UN           ((unsigned short)0x0002)
+#define BD_ENET_TX_CSL          ((unsigned short)0x0001)
+/* All status bits */
+#define BD_ENET_TX_STATS        ((unsigned short)0x03ff)
+
+/*Copy from validation code */
+#define RX_BUFFER_SIZE 256
+#define TX_BUFFER_SIZE 256
+#define NUM_RXBDS 20
+#define NUM_TXBDS 20
+
+#define TX_BD_R                 0x8000
+#define TX_BD_TO1               0x4000
+#define TX_BD_W                 0x2000
+#define TX_BD_TO2               0x1000
+#define TX_BD_L                 0x0800
+#define TX_BD_TC                0x0400
+
+#define TX_BD_INT       0x40000000
+#define TX_BD_TS        0x20000000
+#define TX_BD_PINS      0x10000000
+#define TX_BD_IINS      0x08000000
+#define TX_BD_TXE       0x00008000
+#define TX_BD_UE        0x00002000
+#define TX_BD_EE        0x00001000
+#define TX_BD_FE        0x00000800
+#define TX_BD_LCE       0x00000400
+#define TX_BD_OE        0x00000200
+#define TX_BD_TSE       0x00000100
+#define TX_BD_BDU       0x80000000
+
+#define RX_BD_E                 0x8000
+#define RX_BD_R01               0x4000
+#define RX_BD_W                 0x2000
+#define RX_BD_R02               0x1000
+#define RX_BD_L                 0x0800
+#define RX_BD_M                 0x0100
+#define RX_BD_BC                0x0080
+#define RX_BD_MC                0x0040
+#define RX_BD_LG                0x0020
+#define RX_BD_NO                0x0010
+#define RX_BD_CR                0x0004
+#define RX_BD_OV                0x0002
+#define RX_BD_TR                0x0001
+
+#define RX_BD_ME               0x80000000
+#define RX_BD_PE               0x04000000
+#define RX_BD_CE               0x02000000
+#define RX_BD_UC               0x01000000
+#define RX_BD_INT              0x00800000
+#define RX_BD_ICE              0x00000020
+#define RX_BD_PCR              0x00000010
+#define RX_BD_VLAN             0x00000004
+#define RX_BD_IPV6             0x00000002
+#define RX_BD_FRAG             0x00000001
+#define RX_BD_BDU              0x80000000
+/****************************************************************************/
+
+/* Address Table size in bytes(2048 64bit entry ) */
+#define ESW_ATABLE_MEM_SIZE         (2048*8)
+/* How many 64-bit elements fit in the address table */
+#define ESW_ATABLE_MEM_NUM_ENTRIES  (2048)
+/* Address Table Maximum number of entries in each Slot */
+#define ATABLE_ENTRY_PER_SLOT 8
+/* log2(ATABLE_ENTRY_PER_SLOT)*/
+#define ATABLE_ENTRY_PER_SLOT_bits 3
+/* entry size in byte */
+#define ATABLE_ENTRY_SIZE     8
+/*  slot size in byte */
+#define ATABLE_SLOT_SIZE    (ATABLE_ENTRY_PER_SLOT * ATABLE_ENTRY_SIZE)
+/* width of timestamp variable (bits) within address table entry */
+#define AT_DENTRY_TIMESTAMP_WIDTH    10
+/* number of bits for port number storage */
+#define AT_DENTRY_PORT_WIDTH     4
+/* number of bits for port bitmask number storage */
+#define AT_SENTRY_PORT_WIDTH     11
+/* address table static entry port bitmask start address bit */
+#define AT_SENTRY_PORTMASK_shift     21
+/* address table static entry priority start address bit */
+#define AT_SENTRY_PRIO_shift     18
+/* address table dynamic entry port start address bit */
+#define AT_DENTRY_PORT_shift     28
+/* address table dynamic entry timestamp start address bit */
+#define AT_DENTRY_TIME_shift     18
+/* address table entry record type start address bit */
+#define AT_ENTRY_TYPE_shift     17
+/* address table entry record type bit: 1 static, 0 dynamic */
+#define AT_ENTRY_TYPE_STATIC      1
+#define AT_ENTRY_TYPE_DYNAMIC     0
+/* address table entry record valid start address bit */
+#define AT_ENTRY_VALID_shift     16
+#define AT_ENTRY_RECORD_VALID     1
+
+
+/* return block corresponding to the 8 bit hash value calculated */
+#define GET_BLOCK_PTR(hash)  (hash << 3)
+#define AT_EXTRACT_TIMESTAMP(x) \
+	((x >> AT_DENTRY_TIME_shift) & ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1))
+#define AT_EXTRACT_PORT(x)   \
+	((x >> AT_DENTRY_PORT_shift) & ((1 << AT_DENTRY_PORT_WIDTH)-1))
+#define TIMEDELTA(newtime, oldtime) \
+	 ((newtime - oldtime) & \
+	  ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1))
+/* increment time value respecting modulo. */
+#define TIMEINCREMENT(time) \
+	((time) = ((time)+1) & ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1))
+/* ------------------------------------------------------------------------- */
+/* Bit definitions and macros for MCF_ESW_REVISION */
+#define MCF_ESW_REVISION_CORE_REVISION(x)      (((x)&0x0000FFFF)<<0)
+#define MCF_ESW_REVISION_CUSTOMER_REVISION(x)  (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for MCF_ESW_PER */
+#define MCF_ESW_PER_TE0                        (0x00000001)
+#define MCF_ESW_PER_TE1                        (0x00000002)
+#define MCF_ESW_PER_TE2                        (0x00000004)
+#define MCF_ESW_PER_RE0                        (0x00010000)
+#define MCF_ESW_PER_RE1                        (0x00020000)
+#define MCF_ESW_PER_RE2                        (0x00040000)
+
+/* Bit definitions and macros for MCF_ESW_VLANV */
+#define MCF_ESW_VLANV_VV0                      (0x00000001)
+#define MCF_ESW_VLANV_VV1                      (0x00000002)
+#define MCF_ESW_VLANV_VV2                      (0x00000004)
+#define MCF_ESW_VLANV_DU0                      (0x00010000)
+#define MCF_ESW_VLANV_DU1                      (0x00020000)
+#define MCF_ESW_VLANV_DU2                      (0x00040000)
+
+/* Bit definitions and macros for MCF_ESW_DBCR */
+#define MCF_ESW_DBCR_P0                        (0x00000001)
+#define MCF_ESW_DBCR_P1                        (0x00000002)
+#define MCF_ESW_DBCR_P2                        (0x00000004)
+
+/* Bit definitions and macros for MCF_ESW_DMCR */
+#define MCF_ESW_DMCR_P0                        (0x00000001)
+#define MCF_ESW_DMCR_P1                        (0x00000002)
+#define MCF_ESW_DMCR_P2                        (0x00000004)
+
+/* Bit definitions and macros for MCF_ESW_BKLR */
+#define MCF_ESW_BKLR_BE0                       (0x00000001)
+#define MCF_ESW_BKLR_BE1                       (0x00000002)
+#define MCF_ESW_BKLR_BE2                       (0x00000004)
+#define MCF_ESW_BKLR_LD0                       (0x00010000)
+#define MCF_ESW_BKLR_LD1                       (0x00020000)
+#define MCF_ESW_BKLR_LD2                       (0x00040000)
+
+/* Bit definitions and macros for MCF_ESW_BMPC */
+#define MCF_ESW_BMPC_PORT(x)                   (((x)&0x0000000F)<<0)
+#define MCF_ESW_BMPC_MSG_TX                    (0x00000020)
+#define MCF_ESW_BMPC_EN                        (0x00000040)
+#define MCF_ESW_BMPC_DIS                       (0x00000080)
+#define MCF_ESW_BMPC_PRIORITY(x)               (((x)&0x00000007)<<13)
+#define MCF_ESW_BMPC_PORTMASK(x)               (((x)&0x00000007)<<16)
+
+/* Bit definitions and macros for MCF_ESW_MODE */
+#define MCF_ESW_MODE_SW_RST                    (0x00000001)
+#define MCF_ESW_MODE_SW_EN                     (0x00000002)
+#define MCF_ESW_MODE_STOP                      (0x00000080)
+#define MCF_ESW_MODE_CRC_TRAN                  (0x00000100)
+#define MCF_ESW_MODE_P0CT                      (0x00000200)
+#define MCF_ESW_MODE_STATRST                   (0x80000000)
+
+/* Bit definitions and macros for MCF_ESW_VIMSEL */
+#define MCF_ESW_VIMSEL_IM0(x)                  (((x)&0x00000003)<<0)
+#define MCF_ESW_VIMSEL_IM1(x)                  (((x)&0x00000003)<<2)
+#define MCF_ESW_VIMSEL_IM2(x)                  (((x)&0x00000003)<<4)
+
+/* Bit definitions and macros for MCF_ESW_VOMSEL */
+#define MCF_ESW_VOMSEL_OM0(x)                  (((x)&0x00000003)<<0)
+#define MCF_ESW_VOMSEL_OM1(x)                  (((x)&0x00000003)<<2)
+#define MCF_ESW_VOMSEL_OM2(x)                  (((x)&0x00000003)<<4)
+
+/* Bit definitions and macros for MCF_ESW_VIMEN */
+#define MCF_ESW_VIMEN_EN0                      (0x00000001)
+#define MCF_ESW_VIMEN_EN1                      (0x00000002)
+#define MCF_ESW_VIMEN_EN2                      (0x00000004)
+
+/* Bit definitions and macros for MCF_ESW_VID */
+#define MCF_ESW_VID_TAG(x)                     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_MCR */
+#define MCF_ESW_MCR_PORT(x)                    (((x)&0x0000000F)<<0)
+#define MCF_ESW_MCR_MEN                        (0x00000010)
+#define MCF_ESW_MCR_INGMAP                     (0x00000020)
+#define MCF_ESW_MCR_EGMAP                      (0x00000040)
+#define MCF_ESW_MCR_INGSA                      (0x00000080)
+#define MCF_ESW_MCR_INGDA                      (0x00000100)
+#define MCF_ESW_MCR_EGSA                       (0x00000200)
+#define MCF_ESW_MCR_EGDA                       (0x00000400)
+
+/* Bit definitions and macros for MCF_ESW_EGMAP */
+#define MCF_ESW_EGMAP_EG0                      (0x00000001)
+#define MCF_ESW_EGMAP_EG1                      (0x00000002)
+#define MCF_ESW_EGMAP_EG2                      (0x00000004)
+
+/* Bit definitions and macros for MCF_ESW_INGMAP */
+#define MCF_ESW_INGMAP_ING0                    (0x00000001)
+#define MCF_ESW_INGMAP_ING1                    (0x00000002)
+#define MCF_ESW_INGMAP_ING2                    (0x00000004)
+
+/* Bit definitions and macros for MCF_ESW_INGSAL */
+#define MCF_ESW_INGSAL_ADDLOW(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_INGSAH */
+#define MCF_ESW_INGSAH_ADDHIGH(x)              (((x)&0x0000FFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_INGDAL */
+#define MCF_ESW_INGDAL_ADDLOW(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_INGDAH */
+#define MCF_ESW_INGDAH_ADDHIGH(x)              (((x)&0x0000FFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_ENGSAL */
+#define MCF_ESW_ENGSAL_ADDLOW(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_ENGSAH */
+#define MCF_ESW_ENGSAH_ADDHIGH(x)              (((x)&0x0000FFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_ENGDAL */
+#define MCF_ESW_ENGDAL_ADDLOW(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_ENGDAH */
+#define MCF_ESW_ENGDAH_ADDHIGH(x)              (((x)&0x0000FFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_MCVAL */
+#define MCF_ESW_MCVAL_COUNT(x)                 (((x)&0x000000FF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_MMSR */
+#define MCF_ESW_MMSR_BUSY                      (0x00000001)
+#define MCF_ESW_MMSR_NOCELL                    (0x00000002)
+#define MCF_ESW_MMSR_MEMFULL                   (0x00000004)
+#define MCF_ESW_MMSR_MFLATCH                   (0x00000008)
+#define MCF_ESW_MMSR_DQ_GRNT                   (0x00000040)
+#define MCF_ESW_MMSR_CELLS_AVAIL(x)            (((x)&0x000000FF)<<16)
+
+/* Bit definitions and macros for MCF_ESW_LMT */
+#define MCF_ESW_LMT_THRESH(x)                  (((x)&0x000000FF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_LFC */
+#define MCF_ESW_LFC_COUNT(x)                   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_PCSR */
+#define MCF_ESW_PCSR_PC0                       (0x00000001)
+#define MCF_ESW_PCSR_PC1                       (0x00000002)
+#define MCF_ESW_PCSR_PC2                       (0x00000004)
+
+/* Bit definitions and macros for MCF_ESW_IOSR */
+#define MCF_ESW_IOSR_OR0                       (0x00000001)
+#define MCF_ESW_IOSR_OR1                       (0x00000002)
+#define MCF_ESW_IOSR_OR2                       (0x00000004)
+
+/* Bit definitions and macros for MCF_ESW_QWT */
+#define MCF_ESW_QWT_Q0WT(x)                    (((x)&0x0000001F)<<0)
+#define MCF_ESW_QWT_Q1WT(x)                    (((x)&0x0000001F)<<8)
+#define MCF_ESW_QWT_Q2WT(x)                    (((x)&0x0000001F)<<16)
+#define MCF_ESW_QWT_Q3WT(x)                    (((x)&0x0000001F)<<24)
+
+/* Bit definitions and macros for MCF_ESW_P0BCT */
+#define MCF_ESW_P0BCT_THRESH(x)                (((x)&0x000000FF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_P0FFEN */
+#define MCF_ESW_P0FFEN_FEN                     (0x00000001)
+#define MCF_ESW_P0FFEN_FD(x)                   (((x)&0x00000003)<<2)
+
+/* Bit definitions and macros for MCF_ESW_PSNP */
+#define MCF_ESW_PSNP_EN                        (0x00000001)
+#define MCF_ESW_PSNP_MODE(x)                   (((x)&0x00000003)<<1)
+#define MCF_ESW_PSNP_CD                        (0x00000008)
+#define MCF_ESW_PSNP_CS                        (0x00000010)
+#define MCF_ESW_PSNP_PORT_COMPARE(x)           (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for MCF_ESW_IPSNP */
+#define MCF_ESW_IPSNP_EN                       (0x00000001)
+#define MCF_ESW_IPSNP_MODE(x)                  (((x)&0x00000003)<<1)
+#define MCF_ESW_IPSNP_PROTOCOL(x)              (((x)&0x000000FF)<<8)
+
+/* Bit definitions and macros for MCF_ESW_PVRES */
+#define MCF_ESW_PVRES_PRI0(x)                  (((x)&0x00000007)<<0)
+#define MCF_ESW_PVRES_PRI1(x)                  (((x)&0x00000007)<<3)
+#define MCF_ESW_PVRES_PRI2(x)                  (((x)&0x00000007)<<6)
+#define MCF_ESW_PVRES_PRI3(x)                  (((x)&0x00000007)<<9)
+#define MCF_ESW_PVRES_PRI4(x)                  (((x)&0x00000007)<<12)
+#define MCF_ESW_PVRES_PRI5(x)                  (((x)&0x00000007)<<15)
+#define MCF_ESW_PVRES_PRI6(x)                  (((x)&0x00000007)<<18)
+#define MCF_ESW_PVRES_PRI7(x)                  (((x)&0x00000007)<<21)
+
+/* Bit definitions and macros for MCF_ESW_IPRES */
+#define MCF_ESW_IPRES_ADDRESS(x)               (((x)&0x000000FF)<<0)
+#define MCF_ESW_IPRES_IPV4SEL                  (0x00000100)
+#define MCF_ESW_IPRES_PRI0(x)                  (((x)&0x00000003)<<9)
+#define MCF_ESW_IPRES_PRI1(x)                  (((x)&0x00000003)<<11)
+#define MCF_ESW_IPRES_PRI2(x)                   (((x)&0x00000003)<<13)
+#define MCF_ESW_IPRES_READ                     (0x80000000)
+
+/* Bit definitions and macros for MCF_ESW_PRES */
+#define MCF_ESW_PRES_VLAN                      (0x00000001)
+#define MCF_ESW_PRES_IP                        (0x00000002)
+#define MCF_ESW_PRES_MAC                       (0x00000004)
+#define MCF_ESW_PRES_DFLT_PRI(x)               (((x)&0x00000007)<<4)
+
+/* Bit definitions and macros for MCF_ESW_PID */
+#define MCF_ESW_PID_VLANID(x)                  (((x)&0x0000FFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_VRES */
+#define MCF_ESW_VRES_P0                        (0x00000001)
+#define MCF_ESW_VRES_P1                        (0x00000002)
+#define MCF_ESW_VRES_P2                        (0x00000004)
+#define MCF_ESW_VRES_VLANID(x)                 (((x)&0x00000FFF)<<3)
+
+/* Bit definitions and macros for MCF_ESW_DISCN */
+#define MCF_ESW_DISCN_COUNT(x)                 (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_DISCB */
+#define MCF_ESW_DISCB_COUNT(x)                 (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_NDISCN */
+#define MCF_ESW_NDISCN_COUNT(x)                (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_NDISCB */
+#define MCF_ESW_NDISCB_COUNT(x)                (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_POQC */
+#define MCF_ESW_POQC_COUNT(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_PMVID */
+#define MCF_ESW_PMVID_COUNT(x)                 (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_PMVTAG */
+#define MCF_ESW_PMVTAG_COUNT(x)                (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_PBL */
+#define MCF_ESW_PBL_COUNT(x)                   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_ISR */
+#define MCF_ESW_ISR_EBERR                      (0x00000001)
+#define MCF_ESW_ISR_RXB                        (0x00000002)
+#define MCF_ESW_ISR_RXF                        (0x00000004)
+#define MCF_ESW_ISR_TXB                        (0x00000008)
+#define MCF_ESW_ISR_TXF                        (0x00000010)
+#define MCF_ESW_ISR_QM                         (0x00000020)
+#define MCF_ESW_ISR_OD0                        (0x00000040)
+#define MCF_ESW_ISR_OD1                        (0x00000080)
+#define MCF_ESW_ISR_OD2                        (0x00000100)
+#define MCF_ESW_ISR_LRN                        (0x00000200)
+
+/* Bit definitions and macros for MCF_ESW_IMR */
+#define MCF_ESW_IMR_EBERR                      (0x00000001)
+#define MCF_ESW_IMR_RXB                        (0x00000002)
+#define MCF_ESW_IMR_RXF                        (0x00000004)
+#define MCF_ESW_IMR_TXB                        (0x00000008)
+#define MCF_ESW_IMR_TXF                        (0x00000010)
+#define MCF_ESW_IMR_QM                         (0x00000020)
+#define MCF_ESW_IMR_OD0                        (0x00000040)
+#define MCF_ESW_IMR_OD1                        (0x00000080)
+#define MCF_ESW_IMR_OD2                        (0x00000100)
+#define MCF_ESW_IMR_LRN                        (0x00000200)
+
+/* Bit definitions and macros for MCF_ESW_RDSR */
+#define MCF_ESW_RDSR_ADDRESS(x)                (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for MCF_ESW_TDSR */
+#define MCF_ESW_TDSR_ADDRESS(x)                (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for MCF_ESW_MRBR */
+#define MCF_ESW_MRBR_SIZE(x)                   (((x)&0x000003FF)<<4)
+
+/* Bit definitions and macros for MCF_ESW_RDAR */
+#define MCF_ESW_RDAR_R_DES_ACTIVE              (0x01000000)
+
+/* Bit definitions and macros for MCF_ESW_TDAR */
+#define MCF_ESW_TDAR_X_DES_ACTIVE              (0x01000000)
+
+/* Bit definitions and macros for MCF_ESW_LREC0 */
+#define MCF_ESW_LREC0_MACADDR0(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_LREC1 */
+#define MCF_ESW_LREC1_MACADDR1(x)              (((x)&0x0000FFFF)<<0)
+#define MCF_ESW_LREC1_HASH(x)                  (((x)&0x000000FF)<<16)
+#define MCF_ESW_LREC1_SWPORT(x)                (((x)&0x00000003)<<24)
+
+/* Bit definitions and macros for MCF_ESW_LSR */
+#define MCF_ESW_LSR_DA                         (0x00000001)
+
+#endif /* SWITCH_H */
diff --git a/drivers/net/iseries_veth.c b/drivers/net/iseries_veth.c
index e44215cb1882..9048718aff1b 100644
--- a/drivers/net/iseries_veth.c
+++ b/drivers/net/iseries_veth.c
@@ -495,7 +495,7 @@ static void veth_take_cap_ack(struct veth_lpar_connection *cnx,
 			   cnx->remote_lp);
 	} else {
 		memcpy(&cnx->cap_ack_event, event,
-		       sizeof(&cnx->cap_ack_event));
+		       sizeof(cnx->cap_ack_event));
 		cnx->state |= VETH_STATE_GOTCAPACK;
 		veth_kick_statemachine(cnx);
 	}
diff --git a/drivers/net/mlx4/eq.c b/drivers/net/mlx4/eq.c
index b9ceddde46c0..4ff665c0f144 100644
--- a/drivers/net/mlx4/eq.c
+++ b/drivers/net/mlx4/eq.c
@@ -526,48 +526,6 @@ static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
 	iounmap(priv->clr_base);
 }
 
-int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt)
-{
-	struct mlx4_priv *priv = mlx4_priv(dev);
-	int ret;
-
-	/*
-	 * We assume that mapping one page is enough for the whole EQ
-	 * context table.  This is fine with all current HCAs, because
-	 * we only use 32 EQs and each EQ uses 64 bytes of context
-	 * memory, or 1 KB total.
-	 */
-	priv->eq_table.icm_virt = icm_virt;
-	priv->eq_table.icm_page = alloc_page(GFP_HIGHUSER);
-	if (!priv->eq_table.icm_page)
-		return -ENOMEM;
-	priv->eq_table.icm_dma  = pci_map_page(dev->pdev, priv->eq_table.icm_page, 0,
-					       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
-	if (pci_dma_mapping_error(dev->pdev, priv->eq_table.icm_dma)) {
-		__free_page(priv->eq_table.icm_page);
-		return -ENOMEM;
-	}
-
-	ret = mlx4_MAP_ICM_page(dev, priv->eq_table.icm_dma, icm_virt);
-	if (ret) {
-		pci_unmap_page(dev->pdev, priv->eq_table.icm_dma, PAGE_SIZE,
-			       PCI_DMA_BIDIRECTIONAL);
-		__free_page(priv->eq_table.icm_page);
-	}
-
-	return ret;
-}
-
-void mlx4_unmap_eq_icm(struct mlx4_dev *dev)
-{
-	struct mlx4_priv *priv = mlx4_priv(dev);
-
-	mlx4_UNMAP_ICM(dev, priv->eq_table.icm_virt, 1);
-	pci_unmap_page(dev->pdev, priv->eq_table.icm_dma, PAGE_SIZE,
-		       PCI_DMA_BIDIRECTIONAL);
-	__free_page(priv->eq_table.icm_page);
-}
-
 int mlx4_alloc_eq_table(struct mlx4_dev *dev)
 {
 	struct mlx4_priv *priv = mlx4_priv(dev);
diff --git a/drivers/net/mlx4/main.c b/drivers/net/mlx4/main.c
index dac621b1e9fc..8e8b79fed508 100644
--- a/drivers/net/mlx4/main.c
+++ b/drivers/net/mlx4/main.c
@@ -525,7 +525,10 @@ static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
 		goto err_unmap_aux;
 	}
 
-	err = mlx4_map_eq_icm(dev, init_hca->eqc_base);
+	err = mlx4_init_icm_table(dev, &priv->eq_table.table,
+				  init_hca->eqc_base, dev_cap->eqc_entry_sz,
+				  dev->caps.num_eqs, dev->caps.num_eqs,
+				  0, 0);
 	if (err) {
 		mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
 		goto err_unmap_cmpt;
@@ -668,7 +671,7 @@ err_unmap_mtt:
 	mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
 
 err_unmap_eq:
-	mlx4_unmap_eq_icm(dev);
+	mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
 
 err_unmap_cmpt:
 	mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
@@ -698,11 +701,11 @@ static void mlx4_free_icms(struct mlx4_dev *dev)
 	mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
 	mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
 	mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
+	mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
 	mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
 	mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
 	mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
 	mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
-	mlx4_unmap_eq_icm(dev);
 
 	mlx4_UNMAP_ICM_AUX(dev);
 	mlx4_free_icm(dev, priv->fw.aux_icm, 0);
diff --git a/drivers/net/mlx4/mlx4.h b/drivers/net/mlx4/mlx4.h
index 5bd79c2b184f..bc72d6e4919b 100644
--- a/drivers/net/mlx4/mlx4.h
+++ b/drivers/net/mlx4/mlx4.h
@@ -205,9 +205,7 @@ struct mlx4_eq_table {
 	void __iomem	      **uar_map;
 	u32			clr_mask;
 	struct mlx4_eq	       *eq;
-	u64			icm_virt;
-	struct page	       *icm_page;
-	dma_addr_t		icm_dma;
+	struct mlx4_icm_table	table;
 	struct mlx4_icm_table	cmpt_table;
 	int			have_irq;
 	u8			inta_pin;
@@ -373,9 +371,6 @@ u64 mlx4_make_profile(struct mlx4_dev *dev,
 		      struct mlx4_dev_cap *dev_cap,
 		      struct mlx4_init_hca_param *init_hca);
 
-int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt);
-void mlx4_unmap_eq_icm(struct mlx4_dev *dev);
-
 int mlx4_cmd_init(struct mlx4_dev *dev);
 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
index bd4e8d72dc08..e17b70291bbc 100644
--- a/drivers/net/phy/mdio_bus.c
+++ b/drivers/net/phy/mdio_bus.c
@@ -264,6 +264,8 @@ static int mdio_bus_match(struct device *dev, struct device_driver *drv)
 		(phydev->phy_id & phydrv->phy_id_mask));
 }
 
+#ifdef CONFIG_PM
+
 static bool mdio_bus_phy_may_suspend(struct phy_device *phydev)
 {
 	struct device_driver *drv = phydev->dev.driver;
@@ -295,34 +297,88 @@ static bool mdio_bus_phy_may_suspend(struct phy_device *phydev)
 	return true;
 }
 
-/* Suspend and resume.  Copied from platform_suspend and
- * platform_resume
- */
-static int mdio_bus_suspend(struct device * dev, pm_message_t state)
+static int mdio_bus_suspend(struct device *dev)
 {
 	struct phy_driver *phydrv = to_phy_driver(dev->driver);
 	struct phy_device *phydev = to_phy_device(dev);
 
+	/*
+	 * We must stop the state machine manually, otherwise it stops out of
+	 * control, possibly with the phydev->lock held. Upon resume, netdev
+	 * may call phy routines that try to grab the same lock, and that may
+	 * lead to a deadlock.
+	 */
+	if (phydev->attached_dev)
+		phy_stop_machine(phydev);
+
 	if (!mdio_bus_phy_may_suspend(phydev))
 		return 0;
+
 	return phydrv->suspend(phydev);
 }
 
-static int mdio_bus_resume(struct device * dev)
+static int mdio_bus_resume(struct device *dev)
 {
 	struct phy_driver *phydrv = to_phy_driver(dev->driver);
 	struct phy_device *phydev = to_phy_device(dev);
+	int ret;
 
 	if (!mdio_bus_phy_may_suspend(phydev))
+		goto no_resume;
+
+	ret = phydrv->resume(phydev);
+	if (ret < 0)
+		return ret;
+
+no_resume:
+	if (phydev->attached_dev)
+		phy_start_machine(phydev, NULL);
+
+	return 0;
+}
+
+static int mdio_bus_restore(struct device *dev)
+{
+	struct phy_device *phydev = to_phy_device(dev);
+	struct net_device *netdev = phydev->attached_dev;
+	int ret;
+
+	if (!netdev)
 		return 0;
-	return phydrv->resume(phydev);
+
+	ret = phy_init_hw(phydev);
+	if (ret < 0)
+		return ret;
+
+	/* The PHY needs to renegotiate. */
+	phydev->link = 0;
+	phydev->state = PHY_UP;
+
+	phy_start_machine(phydev, NULL);
+
+	return 0;
 }
 
+static struct dev_pm_ops mdio_bus_pm_ops = {
+	.suspend = mdio_bus_suspend,
+	.resume = mdio_bus_resume,
+	.freeze = mdio_bus_suspend,
+	.thaw = mdio_bus_resume,
+	.restore = mdio_bus_restore,
+};
+
+#define MDIO_BUS_PM_OPS (&mdio_bus_pm_ops)
+
+#else
+
+#define MDIO_BUS_PM_OPS NULL
+
+#endif /* CONFIG_PM */
+
 struct bus_type mdio_bus_type = {
 	.name		= "mdio_bus",
 	.match		= mdio_bus_match,
-	.suspend	= mdio_bus_suspend,
-	.resume		= mdio_bus_resume,
+	.pm		= MDIO_BUS_PM_OPS,
 };
 EXPORT_SYMBOL(mdio_bus_type);
 
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index eda94fcd4065..d2df6382e123 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -413,7 +413,6 @@ EXPORT_SYMBOL(phy_start_aneg);
 
 
 static void phy_change(struct work_struct *work);
-static void phy_state_machine(struct work_struct *work);
 
 /**
  * phy_start_machine - start PHY state machine tracking
@@ -433,7 +432,6 @@ void phy_start_machine(struct phy_device *phydev,
 {
 	phydev->adjust_state = handler;
 
-	INIT_DELAYED_WORK(&phydev->state_queue, phy_state_machine);
 	schedule_delayed_work(&phydev->state_queue, HZ);
 }
 
@@ -764,7 +762,7 @@ EXPORT_SYMBOL(phy_start);
  * phy_state_machine - Handle the state machine
  * @work: work_struct that describes the work to be done
  */
-static void phy_state_machine(struct work_struct *work)
+void phy_state_machine(struct work_struct *work)
 {
 	struct delayed_work *dwork = to_delayed_work(work);
 	struct phy_device *phydev =
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index b10fedd82143..adbc0fded130 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -177,6 +177,7 @@ struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id)
 	dev->state = PHY_DOWN;
 
 	mutex_init(&dev->lock);
+	INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine);
 
 	return dev;
 }
@@ -378,6 +379,20 @@ void phy_disconnect(struct phy_device *phydev)
 }
 EXPORT_SYMBOL(phy_disconnect);
 
+int phy_init_hw(struct phy_device *phydev)
+{
+	int ret;
+
+	if (!phydev->drv || !phydev->drv->config_init)
+		return 0;
+
+	ret = phy_scan_fixups(phydev);
+	if (ret < 0)
+		return ret;
+
+	return phydev->drv->config_init(phydev);
+}
+
 /**
  * phy_attach_direct - attach a network device to a given PHY device pointer
  * @dev: network device to attach
@@ -425,21 +440,7 @@ int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
 	/* Do initial configuration here, now that
 	 * we have certain key parameters
 	 * (dev_flags and interface) */
-	if (phydev->drv->config_init) {
-		int err;
-
-		err = phy_scan_fixups(phydev);
-
-		if (err < 0)
-			return err;
-
-		err = phydev->drv->config_init(phydev);
-
-		if (err < 0)
-			return err;
-	}
-
-	return 0;
+	return phy_init_hw(phydev);
 }
 EXPORT_SYMBOL(phy_attach_direct);
 
diff --git a/drivers/net/sfc/rx.c b/drivers/net/sfc/rx.c
index 01f9432c31ef..98bff5ada09a 100644
--- a/drivers/net/sfc/rx.c
+++ b/drivers/net/sfc/rx.c
@@ -444,7 +444,8 @@ static void efx_rx_packet__check_len(struct efx_rx_queue *rx_queue,
  * the appropriate LRO method
  */
 static void efx_rx_packet_lro(struct efx_channel *channel,
-			      struct efx_rx_buffer *rx_buf)
+			      struct efx_rx_buffer *rx_buf,
+			      bool checksummed)
 {
 	struct napi_struct *napi = &channel->napi_str;
 
@@ -466,7 +467,8 @@ static void efx_rx_packet_lro(struct efx_channel *channel,
 		skb->len = rx_buf->len;
 		skb->data_len = rx_buf->len;
 		skb->truesize += rx_buf->len;
-		skb->ip_summed = CHECKSUM_UNNECESSARY;
+		skb->ip_summed =
+			checksummed ? CHECKSUM_UNNECESSARY : CHECKSUM_NONE;
 
 		napi_gro_frags(napi);
 
@@ -475,6 +477,7 @@ out:
 		rx_buf->page = NULL;
 	} else {
 		EFX_BUG_ON_PARANOID(!rx_buf->skb);
+		EFX_BUG_ON_PARANOID(!checksummed);
 
 		napi_gro_receive(napi, rx_buf->skb);
 		rx_buf->skb = NULL;
@@ -570,7 +573,7 @@ void __efx_rx_packet(struct efx_channel *channel,
 	}
 
 	if (likely(checksummed || rx_buf->page)) {
-		efx_rx_packet_lro(channel, rx_buf);
+		efx_rx_packet_lro(channel, rx_buf, checksummed);
 		goto done;
 	}
 
diff --git a/drivers/net/sfc/tx.c b/drivers/net/sfc/tx.c
index 14a14788566c..d36a2894f005 100644
--- a/drivers/net/sfc/tx.c
+++ b/drivers/net/sfc/tx.c
@@ -823,8 +823,6 @@ static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
 					   tx_queue->efx->type->txd_ring_mask];
 		efx_tsoh_free(tx_queue, buffer);
 		EFX_BUG_ON_PARANOID(buffer->skb);
-		buffer->len = 0;
-		buffer->continuation = true;
 		if (buffer->unmap_len) {
 			unmap_addr = (buffer->dma_addr + buffer->len -
 				      buffer->unmap_len);
@@ -838,6 +836,8 @@ static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
 					       PCI_DMA_TODEVICE);
 			buffer->unmap_len = 0;
 		}
+		buffer->len = 0;
+		buffer->continuation = true;
 	}
 }
 
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 0a551d8f5d95..329f447f5bf7 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -1455,7 +1455,6 @@ static int sky2_up(struct net_device *dev)
 	if (ramsize > 0) {
 		u32 rxspace;
 
-		hw->flags |= SKY2_HW_RAM_BUFFER;
 		pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
 		if (ramsize < 16)
 			rxspace = ramsize / 2;
@@ -2942,6 +2941,9 @@ static int __devinit sky2_init(struct sky2_hw *hw)
 			++hw->ports;
 	}
 
+	if (sky2_read8(hw, B2_E_0))
+		hw->flags |= SKY2_HW_RAM_BUFFER;
+
 	return 0;
 }
 
@@ -4526,6 +4528,8 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
 		goto err_out_free_netdev;
 	}
 
+	netif_carrier_off(dev);
+
 	netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
 
 	err = request_irq(pdev->irq, sky2_intr,
diff --git a/drivers/net/smc91x.c b/drivers/net/smc91x.c
index 7567f510eff5..d8ed1b63da78 100644
--- a/drivers/net/smc91x.c
+++ b/drivers/net/smc91x.c
@@ -2283,7 +2283,7 @@ static int __devinit smc_drv_probe(struct platform_device *pdev)
 
 	ndev->irq = ires->start;
 
-	if (ires->flags & IRQF_TRIGGER_MASK)
+	if (irq_flags == -1 || ires->flags & IRQF_TRIGGER_MASK)
 		irq_flags = ires->flags & IRQF_TRIGGER_MASK;
 
 	ret = smc_request_attrib(pdev, ndev);
diff --git a/drivers/net/smsc911x.c b/drivers/net/smsc911x.c
index d4c82f5fa555..a13d107a412b 100644
--- a/drivers/net/smsc911x.c
+++ b/drivers/net/smsc911x.c
@@ -789,6 +789,7 @@ static void smsc911x_phy_adjust_link(struct net_device *dev)
 		}
 		pdata->last_carrier = carrier;
 	}
+	udelay(10);
 }
 
 static int smsc911x_mii_probe(struct net_device *dev)
@@ -1011,7 +1012,7 @@ static int smsc911x_poll(struct napi_struct *napi, int budget)
 	struct net_device *dev = pdata->dev;
 	int npackets = 0;
 
-	while (likely(netif_running(dev)) && (npackets < budget)) {
+	while (npackets < budget) {
 		unsigned int pktlength;
 		unsigned int pktwords;
 		struct sk_buff *skb;
@@ -1584,7 +1585,7 @@ static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
 	if (unlikely(intsts & inten & INT_STS_PHY_INT_)) {
 		smsc911x_reg_write( pdata, INT_STS , INT_STS_PHY_INT_);
 		temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, MII_INTSTS);
-		SMSC_TRACE("PHY interrupt, sts 0x%04X", (u16)temp);
+		SMSC_TRACE(DRV,"PHY interrupt, sts 0x%04X", (u16)temp);
 		smsc911x_phy_adjust_link(dev);
 		serviced = IRQ_HANDLED;
 	}
diff --git a/drivers/net/smsc9420.c b/drivers/net/smsc9420.c
index 60abdb1081ad..97ababd189c6 100644
--- a/drivers/net/smsc9420.c
+++ b/drivers/net/smsc9420.c
@@ -252,6 +252,9 @@ static int smsc9420_ethtool_get_settings(struct net_device *dev,
 {
 	struct smsc9420_pdata *pd = netdev_priv(dev);
 
+	if (!pd->phy_dev)
+		return -ENODEV;
+
 	cmd->maxtxpkt = 1;
 	cmd->maxrxpkt = 1;
 	return phy_ethtool_gset(pd->phy_dev, cmd);
@@ -262,6 +265,9 @@ static int smsc9420_ethtool_set_settings(struct net_device *dev,
 {
 	struct smsc9420_pdata *pd = netdev_priv(dev);
 
+	if (!pd->phy_dev)
+		return -ENODEV;
+
 	return phy_ethtool_sset(pd->phy_dev, cmd);
 }
 
@@ -290,6 +296,10 @@ static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
 static int smsc9420_ethtool_nway_reset(struct net_device *netdev)
 {
 	struct smsc9420_pdata *pd = netdev_priv(netdev);
+
+	if (!pd->phy_dev)
+		return -ENODEV;
+
 	return phy_start_aneg(pd->phy_dev);
 }
 
@@ -312,6 +322,10 @@ smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
 	for (i = 0; i < 0x100; i += (sizeof(u32)))
 		data[j++] = smsc9420_reg_read(pd, i);
 
+	// cannot read phy registers if the net device is down
+	if (!phy_dev)
+		return;
+
 	for (i = 0; i <= 31; i++)
 		data[j++] = smsc9420_mii_read(phy_dev->bus, phy_dev->addr, i);
 }
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index 42b6c6319bc2..156f59b25191 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -943,8 +943,6 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr)
 		char *name;
 		unsigned long flags = 0;
 
-		err = -EINVAL;
-
 		if (!capable(CAP_NET_ADMIN))
 			return -EPERM;
 
@@ -958,7 +956,7 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr)
 			flags |= TUN_TAP_DEV;
 			name = "tap%d";
 		} else
-			goto failed;
+			return -EINVAL;
 
 		if (*ifr->ifr_name)
 			name = ifr->ifr_name;
diff --git a/drivers/net/usb/hso.c b/drivers/net/usb/hso.c
index f8c6d7ea7264..9e1fc2968cf1 100644
--- a/drivers/net/usb/hso.c
+++ b/drivers/net/usb/hso.c
@@ -1362,7 +1362,7 @@ static void hso_serial_close(struct tty_struct *tty, struct file *filp)
 	/* reset the rts and dtr */
 	/* do the actual close */
 	serial->open_count--;
-	kref_put(&serial->parent->ref, hso_serial_ref_free);
+
 	if (serial->open_count <= 0) {
 		serial->open_count = 0;
 		spin_lock_irq(&serial->serial_lock);
@@ -1382,6 +1382,8 @@ static void hso_serial_close(struct tty_struct *tty, struct file *filp)
 		usb_autopm_put_interface(serial->parent->interface);
 
 	mutex_unlock(&serial->parent->mutex);
+
+	kref_put(&serial->parent->ref, hso_serial_ref_free);
 }
 
 /* close the requested serial port */
diff --git a/drivers/net/usb/kaweth.c b/drivers/net/usb/kaweth.c
index 1f9ec29fce50..65a43c8e76b5 100644
--- a/drivers/net/usb/kaweth.c
+++ b/drivers/net/usb/kaweth.c
@@ -263,6 +263,7 @@ static int kaweth_control(struct kaweth_device *kaweth,
 			  int timeout)
 {
 	struct usb_ctrlrequest *dr;
+	int retval;
 
 	dbg("kaweth_control()");
 
@@ -278,18 +279,21 @@ static int kaweth_control(struct kaweth_device *kaweth,
 		return -ENOMEM;
 	}
 
-	dr->bRequestType= requesttype;
+	dr->bRequestType = requesttype;
 	dr->bRequest = request;
 	dr->wValue = cpu_to_le16(value);
 	dr->wIndex = cpu_to_le16(index);
 	dr->wLength = cpu_to_le16(size);
 
-	return kaweth_internal_control_msg(kaweth->dev,
-					pipe,
-					dr,
-					data,
-					size,
-					timeout);
+	retval = kaweth_internal_control_msg(kaweth->dev,
+					     pipe,
+					     dr,
+					     data,
+					     size,
+					     timeout);
+
+	kfree(dr);
+	return retval;
 }
 
 /****************************************************************
diff --git a/drivers/net/usb/rtl8150.c b/drivers/net/usb/rtl8150.c
index fcc6fa0905d1..18686839cd12 100644
--- a/drivers/net/usb/rtl8150.c
+++ b/drivers/net/usb/rtl8150.c
@@ -324,7 +324,7 @@ static int rtl8150_set_mac_address(struct net_device *netdev, void *p)
 		dbg("%02X:", netdev->dev_addr[i]);
 	dbg("%02X\n", netdev->dev_addr[i]);
 	/* Set the IDR registers. */
-	set_registers(dev, IDR, sizeof(netdev->dev_addr), netdev->dev_addr);
+	set_registers(dev, IDR, netdev->addr_len, netdev->dev_addr);
 #ifdef EEPROM_WRITE
 	{
 	u8 cr;
diff --git a/drivers/net/usb/smsc95xx.c b/drivers/net/usb/smsc95xx.c
index fe045896406b..df49d0daaa16 100644
--- a/drivers/net/usb/smsc95xx.c
+++ b/drivers/net/usb/smsc95xx.c
@@ -1232,7 +1232,7 @@ static const struct driver_info smsc95xx_info = {
 	.rx_fixup	= smsc95xx_rx_fixup,
 	.tx_fixup	= smsc95xx_tx_fixup,
 	.status		= smsc95xx_status,
-	.flags		= FLAG_ETHER,
+	.flags		= FLAG_ETHER | FLAG_SEND_ZLP,
 };
 
 static const struct usb_device_id products[] = {
diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c
index edfd9e10ceba..d49df7352017 100644
--- a/drivers/net/usb/usbnet.c
+++ b/drivers/net/usb/usbnet.c
@@ -988,7 +988,7 @@ int usbnet_start_xmit (struct sk_buff *skb, struct net_device *net)
 	 * NOTE:  strictly conforming cdc-ether devices should expect
 	 * the ZLP here, but ignore the one-byte packet.
 	 */
-	if ((length % dev->maxpacket) == 0) {
+	if (!(info->flags & FLAG_SEND_ZLP) && (length % dev->maxpacket) == 0) {
 		urb->transfer_buffer_length++;
 		if (skb_tailroom(skb)) {
 			skb->data[skb->len] = 0;
diff --git a/drivers/net/wireless/airo.c b/drivers/net/wireless/airo.c
index 8ce5e4cee168..374f74702156 100644
--- a/drivers/net/wireless/airo.c
+++ b/drivers/net/wireless/airo.c
@@ -5249,11 +5249,7 @@ static int set_wep_key(struct airo_info *ai, u16 index, const char *key,
 	WepKeyRid wkr;
 	int rc;
 
-	if (keylen == 0) {
-		airo_print_err(ai->dev->name, "%s: key length to set was zero",
-			       __func__);
-		return -1;
-	}
+	WARN_ON(keylen == 0);
 
 	memset(&wkr, 0, sizeof(wkr));
 	wkr.len = cpu_to_le16(sizeof(wkr));
@@ -6399,11 +6395,7 @@ static int airo_set_encode(struct net_device *dev,
 		if (dwrq->length > MIN_KEY_SIZE)
 			key.len = MAX_KEY_SIZE;
 		else
-			if (dwrq->length > 0)
-				key.len = MIN_KEY_SIZE;
-			else
-				/* Disable the key */
-				key.len = 0;
+			key.len = MIN_KEY_SIZE;
 		/* Check if the key is not marked as invalid */
 		if(!(dwrq->flags & IW_ENCODE_NOKEY)) {
 			/* Cleanup */
@@ -6584,12 +6576,22 @@ static int airo_set_encodeext(struct net_device *dev,
 		default:
 			return -EINVAL;
 		}
-		/* Send the key to the card */
-		rc = set_wep_key(local, idx, key.key, key.len, perm, 1);
-		if (rc < 0) {
-			airo_print_err(local->dev->name, "failed to set WEP key"
-			               " at index %d: %d.", idx, rc);
-			return rc;
+		if (key.len == 0) {
+			rc = set_wep_tx_idx(local, idx, perm, 1);
+			if (rc < 0) {
+				airo_print_err(local->dev->name,
+					       "failed to set WEP transmit index to %d: %d.",
+					       idx, rc);
+				return rc;
+			}
+		} else {
+			rc = set_wep_key(local, idx, key.key, key.len, perm, 1);
+			if (rc < 0) {
+				airo_print_err(local->dev->name,
+					       "failed to set WEP key at index %d: %d.",
+					       idx, rc);
+				return rc;
+			}
 		}
 	}
 
diff --git a/drivers/net/wireless/ath/ar9170/usb.c b/drivers/net/wireless/ath/ar9170/usb.c
index 007eb85fc67e..1084ca69835f 100644
--- a/drivers/net/wireless/ath/ar9170/usb.c
+++ b/drivers/net/wireless/ath/ar9170/usb.c
@@ -64,6 +64,8 @@ static struct usb_device_id ar9170_usb_ids[] = {
 	{ USB_DEVICE(0x0cf3, 0x9170) },
 	/* Atheros TG121N */
 	{ USB_DEVICE(0x0cf3, 0x1001) },
+	/* TP-Link TL-WN821N v2 */
+	{ USB_DEVICE(0x0cf3, 0x1002) },
 	/* Cace Airpcap NX */
 	{ USB_DEVICE(0xcace, 0x0300) },
 	/* D-Link DWA 160A */
diff --git a/drivers/net/wireless/ath/ath5k/ath5k.h b/drivers/net/wireless/ath/ath5k/ath5k.h
index 6358233bac99..778baf7de231 100644
--- a/drivers/net/wireless/ath/ath5k/ath5k.h
+++ b/drivers/net/wireless/ath/ath5k/ath5k.h
@@ -1164,6 +1164,7 @@ extern void ath5k_unregister_leds(struct ath5k_softc *sc);
 
 /* Reset Functions */
 extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
+extern int ath5k_hw_on_hold(struct ath5k_hw *ah);
 extern int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, struct ieee80211_channel *channel, bool change_channel);
 /* Power management functions */
 extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
diff --git a/drivers/net/wireless/ath/ath5k/attach.c b/drivers/net/wireless/ath/ath5k/attach.c
index c41ef58393e7..605b8f67dbe0 100644
--- a/drivers/net/wireless/ath/ath5k/attach.c
+++ b/drivers/net/wireless/ath/ath5k/attach.c
@@ -145,7 +145,7 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
 		goto err_free;
 
 	/* Bring device out of sleep and reset it's units */
-	ret = ath5k_hw_nic_wakeup(ah, CHANNEL_B, true);
+	ret = ath5k_hw_nic_wakeup(ah, 0, true);
 	if (ret)
 		goto err_free;
 
diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index 029c1bc7468f..753f50e8d84f 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -666,7 +666,6 @@ ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 
 	ath5k_led_off(sc);
 
-	free_irq(pdev->irq, sc);
 	pci_save_state(pdev);
 	pci_disable_device(pdev);
 	pci_set_power_state(pdev, PCI_D3hot);
@@ -694,18 +693,8 @@ ath5k_pci_resume(struct pci_dev *pdev)
 	 */
 	pci_write_config_byte(pdev, 0x41, 0);
 
-	err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
-	if (err) {
-		ATH5K_ERR(sc, "request_irq failed\n");
-		goto err_no_irq;
-	}
-
 	ath5k_led_enable(sc);
 	return 0;
-
-err_no_irq:
-	pci_disable_device(pdev);
-	return err;
 }
 #endif /* CONFIG_PM */
 
@@ -2445,27 +2434,29 @@ ath5k_stop_hw(struct ath5k_softc *sc)
 	ret = ath5k_stop_locked(sc);
 	if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
 		/*
-		 * Set the chip in full sleep mode.  Note that we are
-		 * careful to do this only when bringing the interface
-		 * completely to a stop.  When the chip is in this state
-		 * it must be carefully woken up or references to
-		 * registers in the PCI clock domain may freeze the bus
-		 * (and system).  This varies by chip and is mostly an
-		 * issue with newer parts that go to sleep more quickly.
-		 */
-		if (sc->ah->ah_mac_srev >= 0x78) {
-			/*
-			 * XXX
-			 * don't put newer MAC revisions > 7.8 to sleep because
-			 * of the above mentioned problems
-			 */
-			ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
-				"not putting device to sleep\n");
-		} else {
-			ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
-				"putting device to full sleep\n");
-			ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
-		}
+		 * Don't set the card in full sleep mode!
+		 *
+		 * a) When the device is in this state it must be carefully
+		 * woken up or references to registers in the PCI clock
+		 * domain may freeze the bus (and system).  This varies
+		 * by chip and is mostly an issue with newer parts
+		 * (madwifi sources mentioned srev >= 0x78) that go to
+		 * sleep more quickly.
+		 *
+		 * b) On older chips full sleep results a weird behaviour
+		 * during wakeup. I tested various cards with srev < 0x78
+		 * and they don't wake up after module reload, a second
+		 * module reload is needed to bring the card up again.
+		 *
+		 * Until we figure out what's going on don't enable
+		 * full chip reset on any chip (this is what Legacy HAL
+		 * and Sam's HAL do anyway). Instead Perform a full reset
+		 * on the device (same as initial state after attach) and
+		 * leave it idle (keep MAC/BB on warm reset) */
+		ret = ath5k_hw_on_hold(sc->ah);
+
+		ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
+				"putting device to sleep\n");
 	}
 	ath5k_txbuf_free(sc, sc->bbuf);
 
@@ -2676,7 +2667,7 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
 		sc->curchan = chan;
 		sc->curband = &sc->sbands[chan->band];
 	}
-	ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
+	ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
 	if (ret) {
 		ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
 		goto err;
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.c b/drivers/net/wireless/ath/ath5k/eeprom.c
index c56b494d417a..5eded5a0d452 100644
--- a/drivers/net/wireless/ath/ath5k/eeprom.c
+++ b/drivers/net/wireless/ath/ath5k/eeprom.c
@@ -97,6 +97,7 @@ ath5k_eeprom_init_header(struct ath5k_hw *ah)
 	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 	int ret;
 	u16 val;
+	u32 cksum, offset, eep_max = AR5K_EEPROM_INFO_MAX;
 
 	/*
 	 * Read values from EEPROM and store them in the capability structure
@@ -111,20 +112,44 @@ ath5k_eeprom_init_header(struct ath5k_hw *ah)
 	if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
 		return 0;
 
-#ifdef notyet
 	/*
 	 * Validate the checksum of the EEPROM date. There are some
 	 * devices with invalid EEPROMs.
 	 */
-	for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
+	AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val);
+	if (val) {
+		eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) <<
+			   AR5K_EEPROM_SIZE_ENDLOC_SHIFT;
+		AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_LOWER, val);
+		eep_max = (eep_max | val) - AR5K_EEPROM_INFO_BASE;
+
+		/*
+		 * Fail safe check to prevent stupid loops due
+		 * to busted EEPROMs. XXX: This value is likely too
+		 * big still, waiting on a better value.
+		 */
+		if (eep_max > (3 * AR5K_EEPROM_INFO_MAX)) {
+			ATH5K_ERR(ah->ah_sc, "Invalid max custom EEPROM size: "
+				  "%d (0x%04x) max expected: %d (0x%04x)\n",
+				  eep_max, eep_max,
+				  3 * AR5K_EEPROM_INFO_MAX,
+				  3 * AR5K_EEPROM_INFO_MAX);
+			return -EIO;
+		}
+	}
+
+	for (cksum = 0, offset = 0; offset < eep_max; offset++) {
 		AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
 		cksum ^= val;
 	}
 	if (cksum != AR5K_EEPROM_INFO_CKSUM) {
-		ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum);
+		ATH5K_ERR(ah->ah_sc, "Invalid EEPROM "
+			  "checksum: 0x%04x eep_max: 0x%04x (%s)\n",
+			  cksum, eep_max,
+			  eep_max == AR5K_EEPROM_INFO_MAX ?
+				"default size" : "custom size");
 		return -EIO;
 	}
-#endif
 
 	AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
 	    ee_ant_gain);
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.h b/drivers/net/wireless/ath/ath5k/eeprom.h
index 64be73a5edae..020bc4c75ef0 100644
--- a/drivers/net/wireless/ath/ath5k/eeprom.h
+++ b/drivers/net/wireless/ath/ath5k/eeprom.h
@@ -34,6 +34,14 @@
 #define AR5K_EEPROM_RFKILL_POLARITY_S	1
 
 #define AR5K_EEPROM_REG_DOMAIN		0x00bf	/* EEPROM regdom */
+
+/* FLASH(EEPROM) Defines for AR531X chips */
+#define AR5K_EEPROM_SIZE_LOWER		0x1b /* size info -- lower */
+#define AR5K_EEPROM_SIZE_UPPER		0x1c /* size info -- upper */
+#define AR5K_EEPROM_SIZE_UPPER_MASK	0xfff0
+#define AR5K_EEPROM_SIZE_UPPER_SHIFT	4
+#define AR5K_EEPROM_SIZE_ENDLOC_SHIFT	12
+
 #define AR5K_EEPROM_CHECKSUM		0x00c0	/* EEPROM checksum */
 #define AR5K_EEPROM_INFO_BASE		0x00c0	/* EEPROM header */
 #define AR5K_EEPROM_INFO_MAX		(0x400 - AR5K_EEPROM_INFO_BASE)
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c
index a876ca8d69ef..5c0e31b197a0 100644
--- a/drivers/net/wireless/ath/ath5k/phy.c
+++ b/drivers/net/wireless/ath/ath5k/phy.c
@@ -740,13 +740,22 @@ int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
 						AR5K_RF_XPD_GAIN, true);
 
 		} else {
-			/* TODO: Set high and low gain bits */
-			ath5k_hw_rfb_op(ah, rf_regs,
-						ee->ee_x_gain[ee_mode],
+			u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
+			if (ee->ee_pd_gains[ee_mode] > 1) {
+				ath5k_hw_rfb_op(ah, rf_regs,
+						pdg_curve_to_idx[0],
 						AR5K_RF_PD_GAIN_LO, true);
-			ath5k_hw_rfb_op(ah, rf_regs,
-						ee->ee_x_gain[ee_mode],
+				ath5k_hw_rfb_op(ah, rf_regs,
+						pdg_curve_to_idx[1],
 						AR5K_RF_PD_GAIN_HI, true);
+			} else {
+				ath5k_hw_rfb_op(ah, rf_regs,
+						pdg_curve_to_idx[0],
+						AR5K_RF_PD_GAIN_LO, true);
+				ath5k_hw_rfb_op(ah, rf_regs,
+						pdg_curve_to_idx[0],
+						AR5K_RF_PD_GAIN_HI, true);
+			}
 
 			/* Lower synth voltage on Rev 2 */
 			ath5k_hw_rfb_op(ah, rf_regs, 2,
@@ -1897,8 +1906,9 @@ ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
 	s16 min_pwrL, min_pwrR;
 	s16 pwr_i;
 
-	if (WARN_ON(stepL[0] == stepL[1] || stepR[0] == stepR[1]))
-		return 0;
+	/* Some vendors write the same pcdac value twice !!! */
+	if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
+		return max(pwrL[0], pwrR[0]);
 
 	if (pwrL[0] == pwrL[1])
 		min_pwrL = pwrL[0];
@@ -2921,8 +2931,6 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
 		ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
 		return -EINVAL;
 	}
-	if (txpower == 0)
-		txpower = AR5K_TUNE_DEFAULT_TXPOWER;
 
 	/* Reset TX power values */
 	memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c
index bd0a97a38d34..4980621b0239 100644
--- a/drivers/net/wireless/ath/ath5k/reset.c
+++ b/drivers/net/wireless/ath/ath5k/reset.c
@@ -258,29 +258,35 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
 		if (!set_chip)
 			goto commit;
 
-		/* Preserve sleep duration */
 		data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
+
+		/* If card is down we 'll get 0xffff... so we
+		 * need to clean this up before we write the register
+		 */
 		if (data & 0xffc00000)
 			data = 0;
 		else
-			data = data & 0xfffcffff;
+			/* Preserve sleep duration etc */
+			data = data & ~AR5K_SLEEP_CTL_SLE;
 
-		ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL);
+		ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
+							AR5K_SLEEP_CTL);
 		udelay(15);
 
-		for (i = 50; i > 0; i--) {
+		for (i = 200; i > 0; i--) {
 			/* Check if the chip did wake up */
 			if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
 					AR5K_PCICFG_SPWR_DN) == 0)
 				break;
 
 			/* Wait a bit and retry */
-			udelay(200);
-			ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL);
+			udelay(50);
+			ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
+							AR5K_SLEEP_CTL);
 		}
 
 		/* Fail if the chip didn't wake up */
-		if (i <= 0)
+		if (i == 0)
 			return -EIO;
 
 		break;
@@ -297,6 +303,64 @@ commit:
 }
 
 /*
+ * Put device on hold
+ *
+ * Put MAC and Baseband on warm reset and
+ * keep that state (don't clean sleep control
+ * register). After this MAC and Baseband are
+ * disabled and a full reset is needed to come
+ * back. This way we save as much power as possible
+ * without puting the card on full sleep.
+ */
+int ath5k_hw_on_hold(struct ath5k_hw *ah)
+{
+	struct pci_dev *pdev = ah->ah_sc->pdev;
+	u32 bus_flags;
+	int ret;
+
+	/* Make sure device is awake */
+	ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
+	if (ret) {
+		ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
+		return ret;
+	}
+
+	/*
+	 * Put chipset on warm reset...
+	 *
+	 * Note: puting PCI core on warm reset on PCI-E cards
+	 * results card to hang and always return 0xffff... so
+	 * we ingore that flag for PCI-E cards. On PCI cards
+	 * this flag gets cleared after 64 PCI clocks.
+	 */
+	bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
+
+	if (ah->ah_version == AR5K_AR5210) {
+		ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
+			AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
+			AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
+			mdelay(2);
+	} else {
+		ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
+			AR5K_RESET_CTL_BASEBAND | bus_flags);
+	}
+
+	if (ret) {
+		ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n");
+		return -EIO;
+	}
+
+	/* ...wakeup again!*/
+	ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
+	if (ret) {
+		ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+/*
  * Bring up MAC + PHY Chips and program PLL
  * TODO: Half/Quarter rate support
  */
@@ -319,6 +383,50 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
 		return ret;
 	}
 
+	/*
+	 * Put chipset on warm reset...
+	 *
+	 * Note: puting PCI core on warm reset on PCI-E cards
+	 * results card to hang and always return 0xffff... so
+	 * we ingore that flag for PCI-E cards. On PCI cards
+	 * this flag gets cleared after 64 PCI clocks.
+	 */
+	bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
+
+	if (ah->ah_version == AR5K_AR5210) {
+		ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
+			AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
+			AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
+			mdelay(2);
+	} else {
+		ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
+			AR5K_RESET_CTL_BASEBAND | bus_flags);
+	}
+
+	if (ret) {
+		ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
+		return -EIO;
+	}
+
+	/* ...wakeup again!...*/
+	ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
+	if (ret) {
+		ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
+		return ret;
+	}
+
+	/* ...clear reset control register and pull device out of
+	 * warm reset */
+	if (ath5k_hw_nic_reset(ah, 0)) {
+		ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
+		return -EIO;
+	}
+
+	/* On initialization skip PLL programming since we don't have
+	 * a channel / mode set yet */
+	if (initial)
+		return 0;
+
 	if (ah->ah_version != AR5K_AR5210) {
 		/*
 		 * Get channel mode flags
@@ -384,39 +492,6 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
 					AR5K_PHY_TURBO);
 	}
 
-	/* reseting PCI on PCI-E cards results card to hang
-	 * and always return 0xffff... so we ingore that flag
-	 * for PCI-E cards */
-	bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
-
-	/* Reset chipset */
-	if (ah->ah_version == AR5K_AR5210) {
-		ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
-			AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
-			AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
-			mdelay(2);
-	} else {
-		ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
-			AR5K_RESET_CTL_BASEBAND | bus_flags);
-	}
-	if (ret) {
-		ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
-		return -EIO;
-	}
-
-	/* ...wakeup again!*/
-	ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
-	if (ret) {
-		ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
-		return ret;
-	}
-
-	/* ...final warm reset */
-	if (ath5k_hw_nic_reset(ah, 0)) {
-		ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
-		return -EIO;
-	}
-
 	if (ah->ah_version != AR5K_AR5210) {
 
 		/* ...update PLL if needed */
diff --git a/drivers/net/wireless/ath6kl/os/linux/ar6000_android.c b/drivers/net/wireless/ath6kl/os/linux/ar6000_android.c
index 1ca77e513493..9d0c3773d4d7 100644
--- a/drivers/net/wireless/ath6kl/os/linux/ar6000_android.c
+++ b/drivers/net/wireless/ath6kl/os/linux/ar6000_android.c
@@ -56,7 +56,7 @@ ATH_DEBUG_INSTANTIATE_MODULE_VAR(android,
 #endif
 
 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
-char fwpath[256] = "/system/wifi";
+char fwpath[256] = "/lib/firmware/ath6k/AR6102";
 #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */
 int buspm = WLAN_PWR_CTRL_CUT_PWR;
 int wow2mode = WLAN_PWR_CTRL_CUT_PWR;
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h
index 40448067e4cc..7797166a0cdb 100644
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
@@ -117,6 +117,7 @@
 #define B43_MMIO_TSF_2			0x636	/* core rev < 3 only */
 #define B43_MMIO_TSF_3			0x638	/* core rev < 3 only */
 #define B43_MMIO_RNG			0x65A
+#define B43_MMIO_IFSSLOT		0x684	/* Interframe slot time */
 #define B43_MMIO_IFSCTL			0x688 /* Interframe space control */
 #define  B43_MMIO_IFSCTL_USE_EDCF	0x0004
 #define B43_MMIO_POWERUP_DELAY		0x6A8
diff --git a/drivers/net/wireless/b43/dma.c b/drivers/net/wireless/b43/dma.c
index 7964cc32b258..32e9513bbc0b 100644
--- a/drivers/net/wireless/b43/dma.c
+++ b/drivers/net/wireless/b43/dma.c
@@ -1158,8 +1158,9 @@ struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
 }
 
 static int dma_tx_fragment(struct b43_dmaring *ring,
-			   struct sk_buff *skb)
+			   struct sk_buff **in_skb)
 {
+	struct sk_buff *skb = *in_skb;
 	const struct b43_dma_ops *ops = ring->ops;
 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 	u8 *header;
@@ -1225,8 +1226,14 @@ static int dma_tx_fragment(struct b43_dmaring *ring,
 		}
 
 		memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
+		memcpy(bounce_skb->cb, skb->cb, sizeof(skb->cb));
+		bounce_skb->dev = skb->dev;
+		skb_set_queue_mapping(bounce_skb, skb_get_queue_mapping(skb));
+		info = IEEE80211_SKB_CB(bounce_skb);
+
 		dev_kfree_skb_any(skb);
 		skb = bounce_skb;
+		*in_skb = bounce_skb;
 		meta->skb = skb;
 		meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
 		if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
@@ -1334,13 +1341,22 @@ int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
 	spin_lock_irqsave(&ring->lock, flags);
 
 	B43_WARN_ON(!ring->tx);
-	/* Check if the queue was stopped in mac80211,
-	 * but we got called nevertheless.
-	 * That would be a mac80211 bug. */
-	B43_WARN_ON(ring->stopped);
 
-	if (unlikely(free_slots(ring) < TX_SLOTS_PER_FRAME)) {
-		b43warn(dev->wl, "DMA queue overflow\n");
+	if (unlikely(ring->stopped)) {
+		/* We get here only because of a bug in mac80211.
+		 * Because of a race, one packet may be queued after
+		 * the queue is stopped, thus we got called when we shouldn't.
+		 * For now, just refuse the transmit. */
+		if (b43_debug(dev, B43_DBG_DMAVERBOSE))
+			b43err(dev->wl, "Packet after queue stopped\n");
+		err = -ENOSPC;
+		goto out_unlock;
+	}
+
+	if (unlikely(WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME))) {
+		/* If we get here, we have a real error with the queue
+		 * full, but queues not stopped. */
+		b43err(dev->wl, "DMA queue overflow\n");
 		err = -ENOSPC;
 		goto out_unlock;
 	}
@@ -1350,7 +1366,11 @@ int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
 	 * static, so we don't need to store it per frame. */
 	ring->queue_prio = skb_get_queue_mapping(skb);
 
-	err = dma_tx_fragment(ring, skb);
+	/* dma_tx_fragment might reallocate the skb, so invalidate pointers pointing
+	 * into the skb data or cb now. */
+	hdr = NULL;
+	info = NULL;
+	err = dma_tx_fragment(ring, &skb);
 	if (unlikely(err == -ENOKEY)) {
 		/* Drop this packet, as we don't have the encryption key
 		 * anymore and must not transmit it unencrypted. */
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index e71c8d9cd706..82fb9d48fa55 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -664,10 +664,17 @@ static void b43_upload_card_macaddress(struct b43_wldev *dev)
 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
 {
 	/* slot_time is in usec. */
-	if (dev->phy.type != B43_PHYTYPE_G)
+	/* This test used to exit for all but a G PHY. */
+	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
 		return;
-	b43_write16(dev, 0x684, 510 + slot_time);
-	b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
+	b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
+	/* Shared memory location 0x0010 is the slot time and should be
+	 * set to slot_time; however, this register is initially 0 and changing
+	 * the value adversely affects the transmit rate for BCM4311
+	 * devices. Until this behavior is unterstood, delete this step
+	 *
+	 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
+	 */
 }
 
 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
diff --git a/drivers/net/wireless/b43/rfkill.c b/drivers/net/wireless/b43/rfkill.c
index 31e55999893f..dcde92d682ce 100644
--- a/drivers/net/wireless/b43/rfkill.c
+++ b/drivers/net/wireless/b43/rfkill.c
@@ -33,7 +33,8 @@ bool b43_is_hw_radio_enabled(struct b43_wldev *dev)
 		      & B43_MMIO_RADIO_HWENABLED_HI_MASK))
 			return 1;
 	} else {
-		if (b43_read16(dev, B43_MMIO_RADIO_HWENABLED_LO)
+		if (b43_status(dev) >= B43_STAT_STARTED &&
+		    b43_read16(dev, B43_MMIO_RADIO_HWENABLED_LO)
 		    & B43_MMIO_RADIO_HWENABLED_LO_MASK)
 			return 1;
 	}
diff --git a/drivers/net/wireless/b43legacy/rfkill.c b/drivers/net/wireless/b43legacy/rfkill.c
index 8783022db11e..d579df72b783 100644
--- a/drivers/net/wireless/b43legacy/rfkill.c
+++ b/drivers/net/wireless/b43legacy/rfkill.c
@@ -34,6 +34,13 @@ bool b43legacy_is_hw_radio_enabled(struct b43legacy_wldev *dev)
 		      & B43legacy_MMIO_RADIO_HWENABLED_HI_MASK))
 			return 1;
 	} else {
+		/* To prevent CPU fault on PPC, do not read a register
+		 * unless the interface is started; however, on resume
+		 * for hibernation, this routine is entered early. When
+		 * that happens, unconditionally return TRUE.
+		 */
+		if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
+			return 1;
 		if (b43legacy_read16(dev, B43legacy_MMIO_RADIO_HWENABLED_LO)
 		    & B43legacy_MMIO_RADIO_HWENABLED_LO_MASK)
 			return 1;
diff --git a/drivers/net/wireless/hostap/hostap_main.c b/drivers/net/wireless/hostap/hostap_main.c
index 6fe122f18c0d..eb57d1ea361f 100644
--- a/drivers/net/wireless/hostap/hostap_main.c
+++ b/drivers/net/wireless/hostap/hostap_main.c
@@ -875,15 +875,16 @@ void hostap_setup_dev(struct net_device *dev, local_info_t *local,
 
 	switch(type) {
 	case HOSTAP_INTERFACE_AP:
+		dev->tx_queue_len = 0;	/* use main radio device queue */
 		dev->netdev_ops = &hostap_mgmt_netdev_ops;
 		dev->type = ARPHRD_IEEE80211;
 		dev->header_ops = &hostap_80211_ops;
 		break;
 	case HOSTAP_INTERFACE_MASTER:
-		dev->tx_queue_len = 0;	/* use main radio device queue */
 		dev->netdev_ops = &hostap_master_ops;
 		break;
 	default:
+		dev->tx_queue_len = 0;	/* use main radio device queue */
 		dev->netdev_ops = &hostap_netdev_ops;
 	}
 
diff --git a/drivers/net/wireless/ipw2x00/ipw2100.c b/drivers/net/wireless/ipw2x00/ipw2100.c
index 742432388ca3..d04350b14790 100644
--- a/drivers/net/wireless/ipw2x00/ipw2100.c
+++ b/drivers/net/wireless/ipw2x00/ipw2100.c
@@ -6487,6 +6487,16 @@ static int ipw2100_resume(struct pci_dev *pci_dev)
 }
 #endif
 
+static void ipw2100_shutdown(struct pci_dev *pci_dev)
+{
+	struct ipw2100_priv *priv = pci_get_drvdata(pci_dev);
+
+	/* Take down the device; powers it off, etc. */
+	ipw2100_down(priv);
+
+	pci_disable_device(pci_dev);
+}
+
 #define IPW2100_DEV_ID(x) { PCI_VENDOR_ID_INTEL, 0x1043, 0x8086, x }
 
 static struct pci_device_id ipw2100_pci_id_table[] __devinitdata = {
@@ -6550,6 +6560,7 @@ static struct pci_driver ipw2100_pci_driver = {
 	.suspend = ipw2100_suspend,
 	.resume = ipw2100_resume,
 #endif
+	.shutdown = ipw2100_shutdown,
 };
 
 /**
diff --git a/drivers/net/wireless/iwlwifi/iwl-1000.c b/drivers/net/wireless/iwlwifi/iwl-1000.c
index 7da52f1cc1d6..44baa60c9fd3 100644
--- a/drivers/net/wireless/iwlwifi/iwl-1000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-1000.c
@@ -46,7 +46,7 @@
 #include "iwl-5000-hw.h"
 
 /* Highest firmware API version supported */
-#define IWL1000_UCODE_API_MAX 2
+#define IWL1000_UCODE_API_MAX 3
 
 /* Lowest firmware API version supported */
 #define IWL1000_UCODE_API_MIN 1
@@ -62,12 +62,15 @@ struct iwl_cfg iwl1000_bgn_cfg = {
 	.ucode_api_min = IWL1000_UCODE_API_MIN,
 	.sku = IWL_SKU_G|IWL_SKU_N,
 	.ops = &iwl5000_ops,
-	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
+	.eeprom_size = OTP_LOW_IMAGE_SIZE,
 	.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
 	.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
 	.mod_params = &iwl50_mod_params,
 	.valid_tx_ant = ANT_A,
 	.valid_rx_ant = ANT_AB,
 	.need_pll_cfg = true,
+	.max_ll_items = OTP_MAX_LL_ITEMS_1000,
+	.shadow_ram_support = false,
+	.use_rts_for_ht = true, /* use rts/cts protection */
 };
 
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
index 46288e724889..b73ab6c278f3 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.c
@@ -2784,11 +2784,50 @@ static int iwl3945_load_bsm(struct iwl_priv *priv)
 	return 0;
 }
 
+#define IWL3945_UCODE_GET(item)						\
+static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
+				    u32 api_ver)			\
+{									\
+	return le32_to_cpu(ucode->u.v1.item);				\
+}
+
+static u32 iwl3945_ucode_get_header_size(u32 api_ver)
+{
+	return UCODE_HEADER_SIZE(1);
+}
+static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
+				   u32 api_ver)
+{
+	return 0;
+}
+static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
+				  u32 api_ver)
+{
+	return (u8 *) ucode->u.v1.data;
+}
+
+IWL3945_UCODE_GET(inst_size);
+IWL3945_UCODE_GET(data_size);
+IWL3945_UCODE_GET(init_size);
+IWL3945_UCODE_GET(init_data_size);
+IWL3945_UCODE_GET(boot_size);
+
 static struct iwl_hcmd_ops iwl3945_hcmd = {
 	.rxon_assoc = iwl3945_send_rxon_assoc,
 	.commit_rxon = iwl3945_commit_rxon,
 };
 
+static struct iwl_ucode_ops iwl3945_ucode = {
+	.get_header_size = iwl3945_ucode_get_header_size,
+	.get_build = iwl3945_ucode_get_build,
+	.get_inst_size = iwl3945_ucode_get_inst_size,
+	.get_data_size = iwl3945_ucode_get_data_size,
+	.get_init_size = iwl3945_ucode_get_init_size,
+	.get_init_data_size = iwl3945_ucode_get_init_data_size,
+	.get_boot_size = iwl3945_ucode_get_boot_size,
+	.get_data = iwl3945_ucode_get_data,
+};
+
 static struct iwl_lib_ops iwl3945_lib = {
 	.txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
 	.txq_free_tfd = iwl3945_hw_txq_free_tfd,
@@ -2829,6 +2868,7 @@ static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
 };
 
 static struct iwl_ops iwl3945_ops = {
+	.ucode = &iwl3945_ucode,
 	.lib = &iwl3945_lib,
 	.hcmd = &iwl3945_hcmd,
 	.utils = &iwl3945_hcmd_utils,
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index 8f3d4bc6a03f..157ee1506b3c 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -2221,12 +2221,50 @@ static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
 	cancel_work_sync(&priv->txpower_work);
 }
 
+#define IWL4965_UCODE_GET(item)						\
+static u32 iwl4965_ucode_get_##item(const struct iwl_ucode_header *ucode,\
+				    u32 api_ver)			\
+{									\
+	return le32_to_cpu(ucode->u.v1.item);				\
+}
+
+static u32 iwl4965_ucode_get_header_size(u32 api_ver)
+{
+	return UCODE_HEADER_SIZE(1);
+}
+static u32 iwl4965_ucode_get_build(const struct iwl_ucode_header *ucode,
+				   u32 api_ver)
+{
+	return 0;
+}
+static u8 *iwl4965_ucode_get_data(const struct iwl_ucode_header *ucode,
+				  u32 api_ver)
+{
+	return (u8 *) ucode->u.v1.data;
+}
+
+IWL4965_UCODE_GET(inst_size);
+IWL4965_UCODE_GET(data_size);
+IWL4965_UCODE_GET(init_size);
+IWL4965_UCODE_GET(init_data_size);
+IWL4965_UCODE_GET(boot_size);
+
 static struct iwl_hcmd_ops iwl4965_hcmd = {
 	.rxon_assoc = iwl4965_send_rxon_assoc,
 	.commit_rxon = iwl_commit_rxon,
 	.set_rxon_chain = iwl_set_rxon_chain,
 };
 
+static struct iwl_ucode_ops iwl4965_ucode = {
+	.get_header_size = iwl4965_ucode_get_header_size,
+	.get_build = iwl4965_ucode_get_build,
+	.get_inst_size = iwl4965_ucode_get_inst_size,
+	.get_data_size = iwl4965_ucode_get_data_size,
+	.get_init_size = iwl4965_ucode_get_init_size,
+	.get_init_data_size = iwl4965_ucode_get_init_data_size,
+	.get_boot_size = iwl4965_ucode_get_boot_size,
+	.get_data = iwl4965_ucode_get_data,
+};
 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
 	.get_hcmd_size = iwl4965_get_hcmd_size,
 	.build_addsta_hcmd = iwl4965_build_addsta_hcmd,
@@ -2287,6 +2325,7 @@ static struct iwl_lib_ops iwl4965_lib = {
 };
 
 static struct iwl_ops iwl4965_ops = {
+	.ucode = &iwl4965_ucode,
 	.lib = &iwl4965_lib,
 	.hcmd = &iwl4965_hcmd,
 	.utils = &iwl4965_hcmd_utils,
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c
index b3c648ce8c7b..a9ea3b5d49d5 100644
--- a/drivers/net/wireless/iwlwifi/iwl-5000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-5000.c
@@ -239,6 +239,13 @@ static void iwl5000_nic_config(struct iwl_priv *priv)
 				APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 				~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 
+	if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_1000) {
+		/* Setting digital SVR for 1000 card to 1.32V */
+		iwl_set_bits_mask_prph(priv, APMG_DIGITAL_SVR_REG,
+					APMG_SVR_DIGITAL_VOLTAGE_1_32,
+					~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK);
+	}
+
 	spin_unlock_irqrestore(&priv->lock, flags);
 }
 
@@ -1426,6 +1433,44 @@ int iwl5000_calc_rssi(struct iwl_priv *priv,
 	return max_rssi - agc - IWL49_RSSI_OFFSET;
 }
 
+#define IWL5000_UCODE_GET(item)						\
+static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
+				    u32 api_ver)			\
+{									\
+	if (api_ver <= 2)						\
+		return le32_to_cpu(ucode->u.v1.item);			\
+	return le32_to_cpu(ucode->u.v2.item);				\
+}
+
+static u32 iwl5000_ucode_get_header_size(u32 api_ver)
+{
+	if (api_ver <= 2)
+		return UCODE_HEADER_SIZE(1);
+	return UCODE_HEADER_SIZE(2);
+}
+
+static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
+				   u32 api_ver)
+{
+	if (api_ver <= 2)
+		return 0;
+	return le32_to_cpu(ucode->u.v2.build);
+}
+
+static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
+				  u32 api_ver)
+{
+	if (api_ver <= 2)
+		return (u8 *) ucode->u.v1.data;
+	return (u8 *) ucode->u.v2.data;
+}
+
+IWL5000_UCODE_GET(inst_size);
+IWL5000_UCODE_GET(data_size);
+IWL5000_UCODE_GET(init_size);
+IWL5000_UCODE_GET(init_data_size);
+IWL5000_UCODE_GET(boot_size);
+
 struct iwl_hcmd_ops iwl5000_hcmd = {
 	.rxon_assoc = iwl5000_send_rxon_assoc,
 	.commit_rxon = iwl_commit_rxon,
@@ -1441,6 +1486,17 @@ struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
 	.calc_rssi = iwl5000_calc_rssi,
 };
 
+struct iwl_ucode_ops iwl5000_ucode = {
+	.get_header_size = iwl5000_ucode_get_header_size,
+	.get_build = iwl5000_ucode_get_build,
+	.get_inst_size = iwl5000_ucode_get_inst_size,
+	.get_data_size = iwl5000_ucode_get_data_size,
+	.get_init_size = iwl5000_ucode_get_init_size,
+	.get_init_data_size = iwl5000_ucode_get_init_data_size,
+	.get_boot_size = iwl5000_ucode_get_boot_size,
+	.get_data = iwl5000_ucode_get_data,
+};
+
 struct iwl_lib_ops iwl5000_lib = {
 	.set_hw_params = iwl5000_hw_set_hw_params,
 	.txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
@@ -1542,12 +1598,14 @@ static struct iwl_lib_ops iwl5150_lib = {
 };
 
 struct iwl_ops iwl5000_ops = {
+	.ucode = &iwl5000_ucode,
 	.lib = &iwl5000_lib,
 	.hcmd = &iwl5000_hcmd,
 	.utils = &iwl5000_hcmd_utils,
 };
 
 static struct iwl_ops iwl5150_ops = {
+	.ucode = &iwl5000_ucode,
 	.lib = &iwl5150_lib,
 	.hcmd = &iwl5000_hcmd,
 	.utils = &iwl5000_hcmd_utils,
diff --git a/drivers/net/wireless/iwlwifi/iwl-6000.c b/drivers/net/wireless/iwlwifi/iwl-6000.c
index bd438d8acf55..ee7b48ed3e8b 100644
--- a/drivers/net/wireless/iwlwifi/iwl-6000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-6000.c
@@ -46,8 +46,8 @@
 #include "iwl-5000-hw.h"
 
 /* Highest firmware API version supported */
-#define IWL6000_UCODE_API_MAX 2
-#define IWL6050_UCODE_API_MAX 2
+#define IWL6000_UCODE_API_MAX 3
+#define IWL6050_UCODE_API_MAX 3
 
 /* Lowest firmware API version supported */
 #define IWL6000_UCODE_API_MIN 1
@@ -69,6 +69,7 @@ static struct iwl_hcmd_utils_ops iwl6000_hcmd_utils = {
 };
 
 static struct iwl_ops iwl6000_ops = {
+	.ucode = &iwl5000_ucode,
 	.lib = &iwl5000_lib,
 	.hcmd = &iwl5000_hcmd,
 	.utils = &iwl6000_hcmd_utils,
@@ -81,13 +82,15 @@ struct iwl_cfg iwl6000_2ag_cfg = {
 	.ucode_api_min = IWL6000_UCODE_API_MIN,
 	.sku = IWL_SKU_A|IWL_SKU_G,
 	.ops = &iwl6000_ops,
-	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
+	.eeprom_size = OTP_LOW_IMAGE_SIZE,
 	.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
 	.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
 	.mod_params = &iwl50_mod_params,
 	.valid_tx_ant = ANT_BC,
 	.valid_rx_ant = ANT_BC,
 	.need_pll_cfg = false,
+	.max_ll_items = OTP_MAX_LL_ITEMS_6x00,
+	.shadow_ram_support = true,
 };
 
 struct iwl_cfg iwl6000_2agn_cfg = {
@@ -97,13 +100,16 @@ struct iwl_cfg iwl6000_2agn_cfg = {
 	.ucode_api_min = IWL6000_UCODE_API_MIN,
 	.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
 	.ops = &iwl6000_ops,
-	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
+	.eeprom_size = OTP_LOW_IMAGE_SIZE,
 	.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
 	.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
 	.mod_params = &iwl50_mod_params,
 	.valid_tx_ant = ANT_AB,
 	.valid_rx_ant = ANT_AB,
 	.need_pll_cfg = false,
+	.max_ll_items = OTP_MAX_LL_ITEMS_6x00,
+	.shadow_ram_support = true,
+	.use_rts_for_ht = true, /* use rts/cts protection */
 };
 
 struct iwl_cfg iwl6050_2agn_cfg = {
@@ -113,13 +119,16 @@ struct iwl_cfg iwl6050_2agn_cfg = {
 	.ucode_api_min = IWL6050_UCODE_API_MIN,
 	.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
 	.ops = &iwl6000_ops,
-	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
+	.eeprom_size = OTP_LOW_IMAGE_SIZE,
 	.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
 	.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
 	.mod_params = &iwl50_mod_params,
 	.valid_tx_ant = ANT_AB,
 	.valid_rx_ant = ANT_AB,
 	.need_pll_cfg = false,
+	.max_ll_items = OTP_MAX_LL_ITEMS_6x00,
+	.shadow_ram_support = true,
+	.use_rts_for_ht = true, /* use rts/cts protection */
 };
 
 struct iwl_cfg iwl6000_3agn_cfg = {
@@ -129,13 +138,16 @@ struct iwl_cfg iwl6000_3agn_cfg = {
 	.ucode_api_min = IWL6000_UCODE_API_MIN,
 	.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
 	.ops = &iwl6000_ops,
-	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
+	.eeprom_size = OTP_LOW_IMAGE_SIZE,
 	.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
 	.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
 	.mod_params = &iwl50_mod_params,
 	.valid_tx_ant = ANT_ABC,
 	.valid_rx_ant = ANT_ABC,
 	.need_pll_cfg = false,
+	.max_ll_items = OTP_MAX_LL_ITEMS_6x00,
+	.shadow_ram_support = true,
+	.use_rts_for_ht = true, /* use rts/cts protection */
 };
 
 struct iwl_cfg iwl6050_3agn_cfg = {
@@ -145,13 +157,16 @@ struct iwl_cfg iwl6050_3agn_cfg = {
 	.ucode_api_min = IWL6050_UCODE_API_MIN,
 	.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
 	.ops = &iwl6000_ops,
-	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
+	.eeprom_size = OTP_LOW_IMAGE_SIZE,
 	.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
 	.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
 	.mod_params = &iwl50_mod_params,
 	.valid_tx_ant = ANT_ABC,
 	.valid_rx_ant = ANT_ABC,
 	.need_pll_cfg = false,
+	.max_ll_items = OTP_MAX_LL_ITEMS_6x00,
+	.shadow_ram_support = true,
+	.use_rts_for_ht = true, /* use rts/cts protection */
 };
 
 MODULE_FIRMWARE(IWL6000_MODULE_FIRMWARE(IWL6000_UCODE_API_MAX));
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-rs.c b/drivers/net/wireless/iwlwifi/iwl-agn-rs.c
index ff20e5048a55..f5c108be541c 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-rs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-rs.c
@@ -415,6 +415,15 @@ static void rs_tl_turn_on_agg(struct iwl_priv *priv, u8 tid,
 	else if (tid == IWL_AGG_ALL_TID)
 		for (tid = 0; tid < TID_MAX_LOAD_COUNT; tid++)
 			rs_tl_turn_on_agg_for_tid(priv, lq_data, tid, sta);
+	if (priv->cfg->use_rts_for_ht) {
+		/*
+		 * switch to RTS/CTS if it is the prefer protection method
+		 * for HT traffic
+		 */
+		IWL_DEBUG_HT(priv, "use RTS/CTS protection for HT\n");
+		priv->staging_rxon.flags &= ~RXON_FLG_SELF_CTS_EN;
+		iwlcore_commit_rxon(priv);
+	}
 }
 
 static inline int get_num_of_ant_from_rate(u32 rate_n_flags)
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c
index 355f50ea7fef..fc33b29c58ae 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c
@@ -115,9 +115,6 @@ int iwl_commit_rxon(struct iwl_priv *priv)
 
 	/* always get timestamp with Rx frame */
 	priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
-	/* allow CTS-to-self if possible. this is relevant only for
-	 * 5000, but will not damage 4965 */
-	priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
 
 	ret = iwl_check_rxon_cmd(priv);
 	if (ret) {
@@ -217,6 +214,13 @@ int iwl_commit_rxon(struct iwl_priv *priv)
 					"Could not send WEP static key.\n");
 		}
 
+		/*
+		 * allow CTS-to-self if possible for new association.
+		 * this is relevant only for 5000 series and up,
+		 * but will not damage 4965
+		 */
+		priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
+
 		/* Apply the new configuration
 		 * RXON assoc doesn't clear the station table in uCode,
 		 */
@@ -1348,7 +1352,7 @@ static void iwl_nic_start(struct iwl_priv *priv)
  */
 static int iwl_read_ucode(struct iwl_priv *priv)
 {
-	struct iwl_ucode *ucode;
+	struct iwl_ucode_header *ucode;
 	int ret = -EINVAL, index;
 	const struct firmware *ucode_raw;
 	const char *name_pre = priv->cfg->fw_name_pre;
@@ -1357,7 +1361,8 @@ static int iwl_read_ucode(struct iwl_priv *priv)
 	char buf[25];
 	u8 *src;
 	size_t len;
-	u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
+	u32 api_ver, build;
+	u32 inst_size, data_size, init_size, init_data_size, boot_size;
 
 	/* Ask kernel firmware_class module to get the boot firmware off disk.
 	 * request_firmware() is synchronous, file is in memory on return. */
@@ -1387,23 +1392,26 @@ static int iwl_read_ucode(struct iwl_priv *priv)
 	if (ret < 0)
 		goto error;
 
-	/* Make sure that we got at least our header! */
-	if (ucode_raw->size < sizeof(*ucode)) {
+	/* Make sure that we got at least the v1 header! */
+	if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
 		IWL_ERR(priv, "File size way too small!\n");
 		ret = -EINVAL;
 		goto err_release;
 	}
 
 	/* Data from ucode file:  header followed by uCode images */
-	ucode = (void *)ucode_raw->data;
+	ucode = (struct iwl_ucode_header *)ucode_raw->data;
 
 	priv->ucode_ver = le32_to_cpu(ucode->ver);
 	api_ver = IWL_UCODE_API(priv->ucode_ver);
-	inst_size = le32_to_cpu(ucode->inst_size);
-	data_size = le32_to_cpu(ucode->data_size);
-	init_size = le32_to_cpu(ucode->init_size);
-	init_data_size = le32_to_cpu(ucode->init_data_size);
-	boot_size = le32_to_cpu(ucode->boot_size);
+	build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
+	inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
+	data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
+	init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
+	init_data_size =
+		priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
+	boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
+	src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
 
 	/* api_ver should match the api version forming part of the
 	 * firmware filename ... but we don't check for that and only rely
@@ -1429,6 +1437,9 @@ static int iwl_read_ucode(struct iwl_priv *priv)
 	       IWL_UCODE_API(priv->ucode_ver),
 	       IWL_UCODE_SERIAL(priv->ucode_ver));
 
+	if (build)
+		IWL_DEBUG_INFO(priv, "Build %u\n", build);
+
 	IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
 		       priv->ucode_ver);
 	IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
@@ -1443,12 +1454,14 @@ static int iwl_read_ucode(struct iwl_priv *priv)
 		       boot_size);
 
 	/* Verify size of file vs. image size info in file's header */
-	if (ucode_raw->size < sizeof(*ucode) +
+	if (ucode_raw->size !=
+		priv->cfg->ops->ucode->get_header_size(api_ver) +
 		inst_size + data_size + init_size +
 		init_data_size + boot_size) {
 
-		IWL_DEBUG_INFO(priv, "uCode file size %d too small\n",
-			       (int)ucode_raw->size);
+		IWL_DEBUG_INFO(priv,
+			"uCode file size %d does not match expected size\n",
+			(int)ucode_raw->size);
 		ret = -EINVAL;
 		goto err_release;
 	}
@@ -1528,42 +1541,42 @@ static int iwl_read_ucode(struct iwl_priv *priv)
 	/* Copy images into buffers for card's bus-master reads ... */
 
 	/* Runtime instructions (first block of data in file) */
-	src = &ucode->data[0];
-	len = priv->ucode_code.len;
+	len = inst_size;
 	IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
 	memcpy(priv->ucode_code.v_addr, src, len);
+	src += len;
+
 	IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
 		priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
 
 	/* Runtime data (2nd block)
 	 * NOTE:  Copy into backup buffer will be done in iwl_up()  */
-	src = &ucode->data[inst_size];
-	len = priv->ucode_data.len;
+	len = data_size;
 	IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
 	memcpy(priv->ucode_data.v_addr, src, len);
 	memcpy(priv->ucode_data_backup.v_addr, src, len);
+	src += len;
 
 	/* Initialization instructions (3rd block) */
 	if (init_size) {
-		src = &ucode->data[inst_size + data_size];
-		len = priv->ucode_init.len;
+		len = init_size;
 		IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
 				len);
 		memcpy(priv->ucode_init.v_addr, src, len);
+		src += len;
 	}
 
 	/* Initialization data (4th block) */
 	if (init_data_size) {
-		src = &ucode->data[inst_size + data_size + init_size];
-		len = priv->ucode_init_data.len;
+		len = init_data_size;
 		IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
 			       len);
 		memcpy(priv->ucode_init_data.v_addr, src, len);
+		src += len;
 	}
 
 	/* Bootstrap instructions (5th block) */
-	src = &ucode->data[inst_size + data_size + init_size + init_data_size];
-	len = priv->ucode_boot.len;
+	len = boot_size;
 	IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
 	memcpy(priv->ucode_boot.v_addr, src, len);
 
@@ -2206,7 +2219,7 @@ static void iwl_mac_stop(struct ieee80211_hw *hw)
 
 	priv->is_open = 0;
 
-	if (iwl_is_ready_rf(priv)) {
+	if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
 		/* stop mac, cancel any scan request and clear
 		 * RXON_FILTER_ASSOC_MSK BIT
 		 */
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.h b/drivers/net/wireless/iwlwifi/iwl-core.h
index dabf663e36e5..4e616eccebfb 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.h
+++ b/drivers/net/wireless/iwlwifi/iwl-core.h
@@ -116,6 +116,17 @@ struct iwl_temp_ops {
 	void (*set_ct_kill)(struct iwl_priv *priv);
 };
 
+struct iwl_ucode_ops {
+	u32 (*get_header_size)(u32);
+	u32 (*get_build)(const struct iwl_ucode_header *, u32);
+	u32 (*get_inst_size)(const struct iwl_ucode_header *, u32);
+	u32 (*get_data_size)(const struct iwl_ucode_header *, u32);
+	u32 (*get_init_size)(const struct iwl_ucode_header *, u32);
+	u32 (*get_init_data_size)(const struct iwl_ucode_header *, u32);
+	u32 (*get_boot_size)(const struct iwl_ucode_header *, u32);
+	u8 * (*get_data)(const struct iwl_ucode_header *, u32);
+};
+
 struct iwl_lib_ops {
 	/* set hw dependent parameters */
 	int (*set_hw_params)(struct iwl_priv *priv);
@@ -171,6 +182,7 @@ struct iwl_lib_ops {
 };
 
 struct iwl_ops {
+	const struct iwl_ucode_ops *ucode;
 	const struct iwl_lib_ops *lib;
 	const struct iwl_hcmd_ops *hcmd;
 	const struct iwl_hcmd_utils_ops *utils;
@@ -195,6 +207,9 @@ struct iwl_mod_params {
  * 	filename is constructed as fw_name_pre<api>.ucode.
  * @ucode_api_max: Highest version of uCode API supported by driver.
  * @ucode_api_min: Lowest version of uCode API supported by driver.
+ * @max_ll_items: max number of OTP blocks
+ * @shadow_ram_support: shadow support for OTP memory
+ * @use_rts_for_ht: use rts/cts protection for HT traffic
  *
  * We enable the driver to be backward compatible wrt API version. The
  * driver specifies which APIs it supports (with @ucode_api_max being the
@@ -231,6 +246,9 @@ struct iwl_cfg {
 	u8   valid_rx_ant;
 	bool need_pll_cfg;
 	bool use_isr_legacy;
+	const u16 max_ll_items;
+	const bool shadow_ram_support;
+	bool use_rts_for_ht;
 };
 
 /***************************
diff --git a/drivers/net/wireless/iwlwifi/iwl-dev.h b/drivers/net/wireless/iwlwifi/iwl-dev.h
index 650e20af20fa..e8c86079334a 100644
--- a/drivers/net/wireless/iwlwifi/iwl-dev.h
+++ b/drivers/net/wireless/iwlwifi/iwl-dev.h
@@ -66,6 +66,7 @@ extern struct iwl_cfg iwl1000_bgn_cfg;
 /* shared structures from iwl-5000.c */
 extern struct iwl_mod_params iwl50_mod_params;
 extern struct iwl_ops iwl5000_ops;
+extern struct iwl_ucode_ops iwl5000_ucode;
 extern struct iwl_lib_ops iwl5000_lib;
 extern struct iwl_hcmd_ops iwl5000_hcmd;
 extern struct iwl_hcmd_utils_ops iwl5000_hcmd_utils;
@@ -525,15 +526,29 @@ struct fw_desc {
 };
 
 /* uCode file layout */
-struct iwl_ucode {
-	__le32 ver;		/* major/minor/API/serial */
-	__le32 inst_size;	/* bytes of runtime instructions */
-	__le32 data_size;	/* bytes of runtime data */
-	__le32 init_size;	/* bytes of initialization instructions */
-	__le32 init_data_size;	/* bytes of initialization data */
-	__le32 boot_size;	/* bytes of bootstrap instructions */
-	u8 data[0];		/* data in same order as "size" elements */
+struct iwl_ucode_header {
+	__le32 ver;	/* major/minor/API/serial */
+	union {
+		struct {
+			__le32 inst_size;	/* bytes of runtime code */
+			__le32 data_size;	/* bytes of runtime data */
+			__le32 init_size;	/* bytes of init code */
+			__le32 init_data_size;	/* bytes of init data */
+			__le32 boot_size;	/* bytes of bootstrap code */
+			u8 data[0];		/* in same order as sizes */
+		} v1;
+		struct {
+			__le32 build;		/* build number */
+			__le32 inst_size;	/* bytes of runtime code */
+			__le32 data_size;	/* bytes of runtime data */
+			__le32 init_size;	/* bytes of init code */
+			__le32 init_data_size;	/* bytes of init data */
+			__le32 boot_size;	/* bytes of bootstrap code */
+			u8 data[0];		/* in same order as sizes */
+		} v2;
+	} u;
 };
+#define UCODE_HEADER_SIZE(ver) ((ver) == 1 ? 24 : 28)
 
 struct iwl4965_ibss_seq {
 	u8 mac[ETH_ALEN];
@@ -820,6 +835,18 @@ enum iwl_nvm_type {
 	NVM_DEVICE_TYPE_OTP,
 };
 
+/*
+ * Two types of OTP memory access modes
+ *   IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
+ * 			        based on physical memory addressing
+ *   IWL_OTP_ACCESS_RELATIVE - relative address mode,
+ * 			       based on logical memory addressing
+ */
+enum iwl_access_mode {
+	IWL_OTP_ACCESS_ABSOLUTE,
+	IWL_OTP_ACCESS_RELATIVE,
+};
+
 /* interrupt statistics */
 struct isr_statistics {
 	u32 hw;
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
index 7d7554a2f341..eabe48a7ebfe 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
@@ -152,6 +152,19 @@ int iwlcore_eeprom_verify_signature(struct iwl_priv *priv)
 }
 EXPORT_SYMBOL(iwlcore_eeprom_verify_signature);
 
+static void iwl_set_otp_access(struct iwl_priv *priv, enum iwl_access_mode mode)
+{
+	u32 otpgp;
+
+	otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
+	if (mode == IWL_OTP_ACCESS_ABSOLUTE)
+		iwl_clear_bit(priv, CSR_OTP_GP_REG,
+				CSR_OTP_GP_REG_OTP_ACCESS_MODE);
+	else
+		iwl_set_bit(priv, CSR_OTP_GP_REG,
+				CSR_OTP_GP_REG_OTP_ACCESS_MODE);
+}
+
 static int iwlcore_get_nvm_type(struct iwl_priv *priv)
 {
 	u32 otpgp;
@@ -249,6 +262,123 @@ static int iwl_init_otp_access(struct iwl_priv *priv)
 	return ret;
 }
 
+static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, u16 *eeprom_data)
+{
+	int ret = 0;
+	u32 r;
+	u32 otpgp;
+
+	_iwl_write32(priv, CSR_EEPROM_REG,
+		     CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
+	ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
+				  CSR_EEPROM_REG_READ_VALID_MSK,
+				  IWL_EEPROM_ACCESS_TIMEOUT);
+	if (ret < 0) {
+		IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
+		return ret;
+	}
+	r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
+	/* check for ECC errors: */
+	otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
+	if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
+		/* stop in this case */
+		/* set the uncorrectable OTP ECC bit for acknowledgement */
+		iwl_set_bit(priv, CSR_OTP_GP_REG,
+			CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
+		IWL_ERR(priv, "Uncorrectable OTP ECC error, abort OTP read\n");
+		return -EINVAL;
+	}
+	if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
+		/* continue in this case */
+		/* set the correctable OTP ECC bit for acknowledgement */
+		iwl_set_bit(priv, CSR_OTP_GP_REG,
+				CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
+		IWL_ERR(priv, "Correctable OTP ECC error, continue read\n");
+	}
+	*eeprom_data = le16_to_cpu((__force __le16)(r >> 16));
+	return 0;
+}
+
+/*
+ * iwl_is_otp_empty: check for empty OTP
+ */
+static bool iwl_is_otp_empty(struct iwl_priv *priv)
+{
+	u16 next_link_addr = 0, link_value;
+	bool is_empty = false;
+
+	/* locate the beginning of OTP link list */
+	if (!iwl_read_otp_word(priv, next_link_addr, &link_value)) {
+		if (!link_value) {
+			IWL_ERR(priv, "OTP is empty\n");
+			is_empty = true;
+		}
+	} else {
+		IWL_ERR(priv, "Unable to read first block of OTP list.\n");
+		is_empty = true;
+	}
+
+	return is_empty;
+}
+
+
+/*
+ * iwl_find_otp_image: find EEPROM image in OTP
+ *   finding the OTP block that contains the EEPROM image.
+ *   the last valid block on the link list (the block _before_ the last block)
+ *   is the block we should read and used to configure the device.
+ *   If all the available OTP blocks are full, the last block will be the block
+ *   we should read and used to configure the device.
+ *   only perform this operation if shadow RAM is disabled
+ */
+static int iwl_find_otp_image(struct iwl_priv *priv,
+					u16 *validblockaddr)
+{
+	u16 next_link_addr = 0, link_value = 0, valid_addr;
+	int usedblocks = 0;
+
+	/* set addressing mode to absolute to traverse the link list */
+	iwl_set_otp_access(priv, IWL_OTP_ACCESS_ABSOLUTE);
+
+	/* checking for empty OTP or error */
+	if (iwl_is_otp_empty(priv))
+		return -EINVAL;
+
+	/*
+	 * start traverse link list
+	 * until reach the max number of OTP blocks
+	 * different devices have different number of OTP blocks
+	 */
+	do {
+		/* save current valid block address
+		 * check for more block on the link list
+		 */
+		valid_addr = next_link_addr;
+		next_link_addr = link_value * sizeof(u16);
+		IWL_DEBUG_INFO(priv, "OTP blocks %d addr 0x%x\n",
+			       usedblocks, next_link_addr);
+		if (iwl_read_otp_word(priv, next_link_addr, &link_value))
+			return -EINVAL;
+		if (!link_value) {
+			/*
+			 * reach the end of link list, return success and
+			 * set address point to the starting address
+			 * of the image
+			 */
+			*validblockaddr = valid_addr;
+			/* skip first 2 bytes (link list pointer) */
+			*validblockaddr += 2;
+			return 0;
+		}
+		/* more in the link list, continue */
+		usedblocks++;
+	} while (usedblocks <= priv->cfg->max_ll_items);
+
+	/* OTP has no valid blocks */
+	IWL_DEBUG_INFO(priv, "OTP has no valid blocks\n");
+	return -EINVAL;
+}
+
 /**
  * iwl_eeprom_init - read EEPROM contents
  *
@@ -263,14 +393,13 @@ int iwl_eeprom_init(struct iwl_priv *priv)
 	int sz;
 	int ret;
 	u16 addr;
-	u32 otpgp;
+	u16 validblockaddr = 0;
+	u16 cache_addr = 0;
 
 	priv->nvm_device_type = iwlcore_get_nvm_type(priv);
 
 	/* allocate eeprom */
-	if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
-		priv->cfg->eeprom_size =
-			OTP_BLOCK_SIZE * OTP_LOWER_BLOCKS_TOTAL;
+	IWL_DEBUG_INFO(priv, "NVM size = %d\n", priv->cfg->eeprom_size);
 	sz = priv->cfg->eeprom_size;
 	priv->eeprom = kzalloc(sz, GFP_KERNEL);
 	if (!priv->eeprom) {
@@ -298,46 +427,31 @@ int iwl_eeprom_init(struct iwl_priv *priv)
 		if (ret) {
 			IWL_ERR(priv, "Failed to initialize OTP access.\n");
 			ret = -ENOENT;
-			goto err;
+			goto done;
 		}
 		_iwl_write32(priv, CSR_EEPROM_GP,
 			     iwl_read32(priv, CSR_EEPROM_GP) &
 			     ~CSR_EEPROM_GP_IF_OWNER_MSK);
-		/* clear */
-		_iwl_write32(priv, CSR_OTP_GP_REG,
-			     iwl_read32(priv, CSR_OTP_GP_REG) |
+
+		iwl_set_bit(priv, CSR_OTP_GP_REG,
 			     CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
 			     CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
-
-		for (addr = 0; addr < sz; addr += sizeof(u16)) {
-			u32 r;
-
-			_iwl_write32(priv, CSR_EEPROM_REG,
-				     CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
-
-			ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
-						  CSR_EEPROM_REG_READ_VALID_MSK,
-						  IWL_EEPROM_ACCESS_TIMEOUT);
-			if (ret < 0) {
-				IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
+		/* traversing the linked list if no shadow ram supported */
+		if (!priv->cfg->shadow_ram_support) {
+			if (iwl_find_otp_image(priv, &validblockaddr)) {
+				ret = -ENOENT;
 				goto done;
 			}
-			r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
-			/* check for ECC errors: */
-			otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
-			if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
-				/* stop in this case */
-				IWL_ERR(priv, "Uncorrectable OTP ECC error, Abort OTP read\n");
+		}
+		for (addr = validblockaddr; addr < validblockaddr + sz;
+		     addr += sizeof(u16)) {
+			u16 eeprom_data;
+
+			ret = iwl_read_otp_word(priv, addr, &eeprom_data);
+			if (ret)
 				goto done;
-			}
-			if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
-				/* continue in this case */
-				_iwl_write32(priv, CSR_OTP_GP_REG,
-					     iwl_read32(priv, CSR_OTP_GP_REG) |
-					     CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
-				IWL_ERR(priv, "Correctable OTP ECC error, continue read\n");
-			}
-			e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
+			e[cache_addr / 2] = eeprom_data;
+			cache_addr += sizeof(u16);
 		}
 	} else {
 		/* eeprom is an array of 16bit values */
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.h b/drivers/net/wireless/iwlwifi/iwl-eeprom.h
index 195b4ef12c27..78998854dd99 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.h
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.h
@@ -180,8 +180,14 @@ struct iwl_eeprom_channel {
 #define EEPROM_5050_EEPROM_VERSION	(0x21E)
 
 /* OTP */
-#define OTP_LOWER_BLOCKS_TOTAL		(3)
-#define OTP_BLOCK_SIZE			(0x400)
+/* lower blocks contain EEPROM image and calibration data */
+#define OTP_LOW_IMAGE_SIZE		(2 * 512 * sizeof(u16)) /* 2 KB */
+/* high blocks contain PAPD data */
+#define OTP_HIGH_IMAGE_SIZE_6x00        (6 * 512 * sizeof(u16)) /* 6 KB */
+#define OTP_HIGH_IMAGE_SIZE_1000        (0x200 * sizeof(u16)) /* 1024 bytes */
+#define OTP_MAX_LL_ITEMS_1000		(3)	/* OTP blocks for 1000 */
+#define OTP_MAX_LL_ITEMS_6x00		(4)	/* OTP blocks for 6x00 */
+#define OTP_MAX_LL_ITEMS_6x50		(7)	/* OTP blocks for 6x50 */
 
 /* 2.4 GHz */
 extern const u8 iwl_eeprom_band_1[14];
diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h
index 3b9cac3fd216..d393e8f02102 100644
--- a/drivers/net/wireless/iwlwifi/iwl-prph.h
+++ b/drivers/net/wireless/iwlwifi/iwl-prph.h
@@ -80,6 +80,8 @@
 #define APMG_RFKILL_REG			(APMG_BASE + 0x0014)
 #define APMG_RTC_INT_STT_REG		(APMG_BASE + 0x001c)
 #define APMG_RTC_INT_MSK_REG		(APMG_BASE + 0x0020)
+#define APMG_DIGITAL_SVR_REG		(APMG_BASE + 0x0058)
+#define APMG_ANALOG_SVR_REG		(APMG_BASE + 0x006C)
 
 #define APMG_CLK_VAL_DMA_CLK_RQT	(0x00000200)
 #define APMG_CLK_VAL_BSM_CLK_RQT	(0x00000800)
@@ -91,7 +93,8 @@
 #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN		(0x00000000)
 #define APMG_PS_CTRL_VAL_PWR_SRC_MAX		(0x01000000) /* 3945 only */
 #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX		(0x02000000)
-
+#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK	(0x000001E0) /* bit 8:5 */
+#define APMG_SVR_DIGITAL_VOLTAGE_1_32		(0x00000060)
 
 #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS		(0x00000800)
 
diff --git a/drivers/net/wireless/iwlwifi/iwl-rx.c b/drivers/net/wireless/iwlwifi/iwl-rx.c
index 2b8d40b37a1c..a13f678fe44c 100644
--- a/drivers/net/wireless/iwlwifi/iwl-rx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-rx.c
@@ -239,33 +239,51 @@ void iwl_rx_allocate(struct iwl_priv *priv, gfp_t priority)
 	struct iwl_rx_queue *rxq = &priv->rxq;
 	struct list_head *element;
 	struct iwl_rx_mem_buffer *rxb;
+	struct sk_buff *skb;
 	unsigned long flags;
 
 	while (1) {
 		spin_lock_irqsave(&rxq->lock, flags);
-
 		if (list_empty(&rxq->rx_used)) {
 			spin_unlock_irqrestore(&rxq->lock, flags);
 			return;
 		}
-		element = rxq->rx_used.next;
-		rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
-		list_del(element);
-
 		spin_unlock_irqrestore(&rxq->lock, flags);
 
+		if (rxq->free_count > RX_LOW_WATERMARK)
+			priority |= __GFP_NOWARN;
 		/* Alloc a new receive buffer */
-		rxb->skb = alloc_skb(priv->hw_params.rx_buf_size + 256,
+		skb = alloc_skb(priv->hw_params.rx_buf_size + 256,
 						priority);
 
-		if (!rxb->skb) {
-			IWL_CRIT(priv, "Can not allocate SKB buffers\n");
+		if (!skb) {
+			if (net_ratelimit())
+				IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
+			if ((rxq->free_count <= RX_LOW_WATERMARK) &&
+			    net_ratelimit())
+				IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
+					 priority == GFP_ATOMIC ?  "GFP_ATOMIC" : "GFP_KERNEL",
+					 rxq->free_count);
 			/* We don't reschedule replenish work here -- we will
 			 * call the restock method and if it still needs
 			 * more buffers it will schedule replenish */
 			break;
 		}
 
+		spin_lock_irqsave(&rxq->lock, flags);
+
+		if (list_empty(&rxq->rx_used)) {
+			spin_unlock_irqrestore(&rxq->lock, flags);
+			dev_kfree_skb_any(skb);
+			return;
+		}
+		element = rxq->rx_used.next;
+		rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
+		list_del(element);
+
+		spin_unlock_irqrestore(&rxq->lock, flags);
+
+		rxb->skb = skb;
 		/* Get physical address of RB/SKB */
 		rxb->real_dma_addr = pci_map_single(
 					priv->pci_dev,
diff --git a/drivers/net/wireless/iwlwifi/iwl-scan.c b/drivers/net/wireless/iwlwifi/iwl-scan.c
index e26875dbe859..474fd4982471 100644
--- a/drivers/net/wireless/iwlwifi/iwl-scan.c
+++ b/drivers/net/wireless/iwlwifi/iwl-scan.c
@@ -799,7 +799,8 @@ void iwl_bg_abort_scan(struct work_struct *work)
 {
 	struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan);
 
-	if (!iwl_is_ready(priv))
+	if (!test_bit(STATUS_READY, &priv->status) ||
+	    !test_bit(STATUS_GEO_CONFIGURED, &priv->status))
 		return;
 
 	mutex_lock(&priv->mutex);
diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-tx.c
index 2e89040e63be..c17b8f93ad15 100644
--- a/drivers/net/wireless/iwlwifi/iwl-tx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-tx.c
@@ -1233,8 +1233,16 @@ int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
 		return -ENXIO;
 	}
 
+	if (priv->stations[sta_id].tid[tid].agg.state ==
+				IWL_EMPTYING_HW_QUEUE_ADDBA) {
+		IWL_DEBUG_HT(priv, "AGG stop before setup done\n");
+		ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
+		priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
+		return 0;
+	}
+
 	if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
-		IWL_WARN(priv, "Stopping AGG while state not IWL_AGG_ON\n");
+		IWL_WARN(priv, "Stopping AGG while state not ON or starting\n");
 
 	tid_data = &priv->stations[sta_id].tid[tid];
 	ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c
index 523843369ca2..4fac58260001 100644
--- a/drivers/net/wireless/iwlwifi/iwl3945-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c
@@ -1196,6 +1196,7 @@ static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
 	struct iwl_rx_queue *rxq = &priv->rxq;
 	struct list_head *element;
 	struct iwl_rx_mem_buffer *rxb;
+	struct sk_buff *skb;
 	unsigned long flags;
 
 	while (1) {
@@ -1205,25 +1206,39 @@ static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
 			spin_unlock_irqrestore(&rxq->lock, flags);
 			return;
 		}
-
-		element = rxq->rx_used.next;
-		rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
-		list_del(element);
 		spin_unlock_irqrestore(&rxq->lock, flags);
 
+		if (rxq->free_count > RX_LOW_WATERMARK)
+			priority |= __GFP_NOWARN;
 		/* Alloc a new receive buffer */
-		rxb->skb =
-		    alloc_skb(priv->hw_params.rx_buf_size,
-				priority);
-		if (!rxb->skb) {
+		skb = alloc_skb(priv->hw_params.rx_buf_size, priority);
+		if (!skb) {
 			if (net_ratelimit())
-				IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
+				IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
+			if ((rxq->free_count <= RX_LOW_WATERMARK) &&
+			    net_ratelimit())
+				IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
+					 priority == GFP_ATOMIC ?  "GFP_ATOMIC" : "GFP_KERNEL",
+					 rxq->free_count);
 			/* We don't reschedule replenish work here -- we will
 			 * call the restock method and if it still needs
 			 * more buffers it will schedule replenish */
 			break;
 		}
 
+		spin_lock_irqsave(&rxq->lock, flags);
+		if (list_empty(&rxq->rx_used)) {
+			spin_unlock_irqrestore(&rxq->lock, flags);
+			dev_kfree_skb_any(skb);
+			return;
+		}
+		element = rxq->rx_used.next;
+		rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
+		list_del(element);
+		spin_unlock_irqrestore(&rxq->lock, flags);
+
+		rxb->skb = skb;
+
 		/* If radiotap head is required, reserve some headroom here.
 		 * The physical head count is a variable rx_stats->phy_count.
 		 * We reserve 4 bytes here. Plus these extra bytes, the
@@ -2111,7 +2126,7 @@ static void iwl3945_nic_start(struct iwl_priv *priv)
  */
 static int iwl3945_read_ucode(struct iwl_priv *priv)
 {
-	struct iwl_ucode *ucode;
+	const struct iwl_ucode_header *ucode;
 	int ret = -EINVAL, index;
 	const struct firmware *ucode_raw;
 	/* firmware file name contains uCode/driver compatibility version */
@@ -2152,22 +2167,24 @@ static int iwl3945_read_ucode(struct iwl_priv *priv)
 		goto error;
 
 	/* Make sure that we got at least our header! */
-	if (ucode_raw->size < sizeof(*ucode)) {
+	if (ucode_raw->size <  priv->cfg->ops->ucode->get_header_size(1)) {
 		IWL_ERR(priv, "File size way too small!\n");
 		ret = -EINVAL;
 		goto err_release;
 	}
 
 	/* Data from ucode file:  header followed by uCode images */
-	ucode = (void *)ucode_raw->data;
+	ucode = (struct iwl_ucode_header *)ucode_raw->data;
 
 	priv->ucode_ver = le32_to_cpu(ucode->ver);
 	api_ver = IWL_UCODE_API(priv->ucode_ver);
-	inst_size = le32_to_cpu(ucode->inst_size);
-	data_size = le32_to_cpu(ucode->data_size);
-	init_size = le32_to_cpu(ucode->init_size);
-	init_data_size = le32_to_cpu(ucode->init_data_size);
-	boot_size = le32_to_cpu(ucode->boot_size);
+	inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
+	data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
+	init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
+	init_data_size =
+		priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
+	boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
+	src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
 
 	/* api_ver should match the api version forming part of the
 	 * firmware filename ... but we don't check for that and only rely
@@ -2208,12 +2225,13 @@ static int iwl3945_read_ucode(struct iwl_priv *priv)
 
 
 	/* Verify size of file vs. image size info in file's header */
-	if (ucode_raw->size < sizeof(*ucode) +
+	if (ucode_raw->size != priv->cfg->ops->ucode->get_header_size(api_ver) +
 		inst_size + data_size + init_size +
 		init_data_size + boot_size) {
 
-		IWL_DEBUG_INFO(priv, "uCode file size %zd too small\n",
-			       ucode_raw->size);
+		IWL_DEBUG_INFO(priv,
+			"uCode file size %zd does not match expected size\n",
+			ucode_raw->size);
 		ret = -EINVAL;
 		goto err_release;
 	}
@@ -2296,44 +2314,44 @@ static int iwl3945_read_ucode(struct iwl_priv *priv)
 	/* Copy images into buffers for card's bus-master reads ... */
 
 	/* Runtime instructions (first block of data in file) */
-	src = &ucode->data[0];
-	len = priv->ucode_code.len;
+	len = inst_size;
 	IWL_DEBUG_INFO(priv,
 		"Copying (but not loading) uCode instr len %zd\n", len);
 	memcpy(priv->ucode_code.v_addr, src, len);
+	src += len;
+
 	IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
 		priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
 
 	/* Runtime data (2nd block)
 	 * NOTE:  Copy into backup buffer will be done in iwl3945_up()  */
-	src = &ucode->data[inst_size];
-	len = priv->ucode_data.len;
+	len = data_size;
 	IWL_DEBUG_INFO(priv,
 		"Copying (but not loading) uCode data len %zd\n", len);
 	memcpy(priv->ucode_data.v_addr, src, len);
 	memcpy(priv->ucode_data_backup.v_addr, src, len);
+	src += len;
 
 	/* Initialization instructions (3rd block) */
 	if (init_size) {
-		src = &ucode->data[inst_size + data_size];
-		len = priv->ucode_init.len;
+		len = init_size;
 		IWL_DEBUG_INFO(priv,
 			"Copying (but not loading) init instr len %zd\n", len);
 		memcpy(priv->ucode_init.v_addr, src, len);
+		src += len;
 	}
 
 	/* Initialization data (4th block) */
 	if (init_data_size) {
-		src = &ucode->data[inst_size + data_size + init_size];
-		len = priv->ucode_init_data.len;
+		len = init_data_size;
 		IWL_DEBUG_INFO(priv,
 			"Copying (but not loading) init data len %zd\n", len);
 		memcpy(priv->ucode_init_data.v_addr, src, len);
+		src += len;
 	}
 
 	/* Bootstrap instructions (5th block) */
-	src = &ucode->data[inst_size + data_size + init_size + init_data_size];
-	len = priv->ucode_boot.len;
+	len = boot_size;
 	IWL_DEBUG_INFO(priv,
 		"Copying (but not loading) boot instr len %zd\n", len);
 	memcpy(priv->ucode_boot.v_addr, src, len);
diff --git a/drivers/net/wireless/libertas/if_usb.c b/drivers/net/wireless/libertas/if_usb.c
index 1844c5adf6e9..3a9a8c13b8a9 100644
--- a/drivers/net/wireless/libertas/if_usb.c
+++ b/drivers/net/wireless/libertas/if_usb.c
@@ -507,7 +507,7 @@ static int __if_usb_submit_rx_urb(struct if_usb_card *cardp,
 	/* Fill the receive configuration URB and initialise the Rx call back */
 	usb_fill_bulk_urb(cardp->rx_urb, cardp->udev,
 			  usb_rcvbulkpipe(cardp->udev, cardp->ep_in),
-			  (void *) (skb->tail + (size_t) IPFIELD_ALIGN_OFFSET),
+			  skb->data + IPFIELD_ALIGN_OFFSET,
 			  MRVDRV_ETH_RX_PACKET_BUFFER_SIZE, callbackfn,
 			  cardp);
 
diff --git a/drivers/net/wireless/libertas/wext.c b/drivers/net/wireless/libertas/wext.c
index 8bc1907458b1..f9c366c6ce4c 100644
--- a/drivers/net/wireless/libertas/wext.c
+++ b/drivers/net/wireless/libertas/wext.c
@@ -1951,10 +1951,8 @@ static int lbs_get_essid(struct net_device *dev, struct iw_request_info *info,
 	if (priv->connect_status == LBS_CONNECTED) {
 		memcpy(extra, priv->curbssparams.ssid,
 		       priv->curbssparams.ssid_len);
-		extra[priv->curbssparams.ssid_len] = '\0';
 	} else {
 		memset(extra, 0, 32);
-		extra[priv->curbssparams.ssid_len] = '\0';
 	}
 	/*
 	 * If none, we may want to get the one that was set
diff --git a/drivers/net/wireless/p54/p54usb.c b/drivers/net/wireless/p54/p54usb.c
index 0e877a104a89..b17ec7f24b82 100644
--- a/drivers/net/wireless/p54/p54usb.c
+++ b/drivers/net/wireless/p54/p54usb.c
@@ -66,6 +66,7 @@ static struct usb_device_id p54u_table[] __devinitdata = {
 	{USB_DEVICE(0x0bf8, 0x1009)},   /* FUJITSU E-5400 USB D1700*/
 	{USB_DEVICE(0x0cde, 0x0006)},   /* Medion MD40900 */
 	{USB_DEVICE(0x0cde, 0x0008)},	/* Sagem XG703A */
+	{USB_DEVICE(0x0cde, 0x0015)},	/* Zcomax XG-705A */
 	{USB_DEVICE(0x0d8e, 0x3762)},	/* DLink DWL-G120 Cohiba */
 	{USB_DEVICE(0x124a, 0x4025)},	/* IOGear GWU513 (GW3887IK chip) */
 	{USB_DEVICE(0x1260, 0xee22)},	/* SMC 2862W-G version 2 */
@@ -426,12 +427,16 @@ static const char p54u_romboot_3887[] = "~~~~";
 static int p54u_firmware_reset_3887(struct ieee80211_hw *dev)
 {
 	struct p54u_priv *priv = dev->priv;
-	u8 buf[4];
+	u8 *buf;
 	int ret;
 
-	memcpy(&buf, p54u_romboot_3887, sizeof(buf));
+	buf = kmalloc(4, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+	memcpy(buf, p54u_romboot_3887, 4);
 	ret = p54u_bulk_msg(priv, P54U_PIPE_DATA,
-			    buf, sizeof(buf));
+			    buf, 4);
+	kfree(buf);
 	if (ret)
 		dev_err(&priv->udev->dev, "(p54usb) unable to jump to "
 			"boot ROM (%d)!\n", ret);
diff --git a/drivers/net/wireless/ray_cs.c b/drivers/net/wireless/ray_cs.c
index 698b11b1cadb..8c67a488f83b 100644
--- a/drivers/net/wireless/ray_cs.c
+++ b/drivers/net/wireless/ray_cs.c
@@ -2878,7 +2878,7 @@ static int write_essid(struct file *file, const char __user *buffer,
 		       unsigned long count, void *data)
 {
 	static char proc_essid[33];
-	int len = count;
+	unsigned int len = count;
 
 	if (len > 32)
 		len = 32;
diff --git a/drivers/net/wireless/rtl818x/rtl8187_leds.c b/drivers/net/wireless/rtl818x/rtl8187_leds.c
index cf9f899fe0e6..75648dd17595 100644
--- a/drivers/net/wireless/rtl818x/rtl8187_leds.c
+++ b/drivers/net/wireless/rtl818x/rtl8187_leds.c
@@ -210,10 +210,10 @@ void rtl8187_leds_exit(struct ieee80211_hw *dev)
 
 	/* turn the LED off before exiting */
 	queue_delayed_work(dev->workqueue, &priv->led_off, 0);
-	cancel_delayed_work_sync(&priv->led_off);
-	cancel_delayed_work_sync(&priv->led_on);
 	rtl8187_unregister_led(&priv->led_rx);
 	rtl8187_unregister_led(&priv->led_tx);
+	cancel_delayed_work_sync(&priv->led_off);
+	cancel_delayed_work_sync(&priv->led_on);
 }
 #endif /* def CONFIG_RTL8187_LED */
 
diff --git a/drivers/parisc/ccio-dma.c b/drivers/parisc/ccio-dma.c
index a45b0c0d574e..a6b4a5a53d40 100644
--- a/drivers/parisc/ccio-dma.c
+++ b/drivers/parisc/ccio-dma.c
@@ -1266,7 +1266,7 @@ ccio_ioc_init(struct ioc *ioc)
 	** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
 	*/
 
-	iova_space_size = (u32) (num_physpages / count_parisc_driver(&ccio_driver));
+	iova_space_size = (u32) (totalram_pages / count_parisc_driver(&ccio_driver));
 
 	/* limit IOVA space size to 1MB-1GB */
 
@@ -1305,7 +1305,7 @@ ccio_ioc_init(struct ioc *ioc)
 
 	DBG_INIT("%s() hpa 0x%p mem %luMB IOV %dMB (%d bits)\n",
 			__func__, ioc->ioc_regs,
-			(unsigned long) num_physpages >> (20 - PAGE_SHIFT),
+			(unsigned long) totalram_pages >> (20 - PAGE_SHIFT),
 			iova_space_size>>20,
 			iov_order + PAGE_SHIFT);
 
diff --git a/drivers/parisc/sba_iommu.c b/drivers/parisc/sba_iommu.c
index 123d8fe3427d..57a6d19eba4c 100644
--- a/drivers/parisc/sba_iommu.c
+++ b/drivers/parisc/sba_iommu.c
@@ -1390,7 +1390,7 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
 	** for DMA hints - ergo only 30 bits max.
 	*/
 
-	iova_space_size = (u32) (num_physpages/global_ioc_cnt);
+	iova_space_size = (u32) (totalram_pages/global_ioc_cnt);
 
 	/* limit IOVA space size to 1MB-1GB */
 	if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
@@ -1415,7 +1415,7 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
 	DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
 			__func__,
 			ioc->ioc_hpa,
-			(unsigned long) num_physpages >> (20 - PAGE_SHIFT),
+			(unsigned long) totalram_pages >> (20 - PAGE_SHIFT),
 			iova_space_size>>20,
 			iov_order + PAGE_SHIFT);
 
diff --git a/drivers/pci/dmar.c b/drivers/pci/dmar.c
index 7b287cb38b7a..380b60e677e0 100644
--- a/drivers/pci/dmar.c
+++ b/drivers/pci/dmar.c
@@ -632,20 +632,31 @@ int alloc_iommu(struct dmar_drhd_unit *drhd)
 	iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
 	iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
 
+	if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {
+		/* Promote an attitude of violence to a BIOS engineer today */
+		WARN(1, "Your BIOS is broken; DMAR reported at address %llx returns all ones!\n"
+		     "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
+		     drhd->reg_base_addr,
+		     dmi_get_system_info(DMI_BIOS_VENDOR),
+		     dmi_get_system_info(DMI_BIOS_VERSION),
+		     dmi_get_system_info(DMI_PRODUCT_VERSION));
+		goto err_unmap;
+	}
+
 #ifdef CONFIG_DMAR
 	agaw = iommu_calculate_agaw(iommu);
 	if (agaw < 0) {
 		printk(KERN_ERR
 		       "Cannot get a valid agaw for iommu (seq_id = %d)\n",
 		       iommu->seq_id);
-		goto error;
+		goto err_unmap;
 	}
 	msagaw = iommu_calculate_max_sagaw(iommu);
 	if (msagaw < 0) {
 		printk(KERN_ERR
 			"Cannot get a valid max agaw for iommu (seq_id = %d)\n",
 			iommu->seq_id);
-		goto error;
+		goto err_unmap;
 	}
 #endif
 	iommu->agaw = agaw;
@@ -665,7 +676,7 @@ int alloc_iommu(struct dmar_drhd_unit *drhd)
 	}
 
 	ver = readl(iommu->reg + DMAR_VER_REG);
-	pr_debug("IOMMU %llx: ver %d:%d cap %llx ecap %llx\n",
+	pr_info("IOMMU %llx: ver %d:%d cap %llx ecap %llx\n",
 		(unsigned long long)drhd->reg_base_addr,
 		DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
 		(unsigned long long)iommu->cap,
@@ -675,7 +686,10 @@ int alloc_iommu(struct dmar_drhd_unit *drhd)
 
 	drhd->iommu = iommu;
 	return 0;
-error:
+
+ err_unmap:
+	iounmap(iommu->reg);
+ error:
 	kfree(iommu);
 	return -1;
 }
diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c
index 4770f13b3ca1..e2504be1fa8d 100644
--- a/drivers/pci/pcie/aer/aerdrv.c
+++ b/drivers/pci/pcie/aer/aerdrv.c
@@ -52,7 +52,7 @@ static struct pci_error_handlers aer_error_handlers = {
 
 static struct pcie_port_service_driver aerdriver = {
 	.name		= "aer",
-	.port_type	= PCIE_ANY_PORT,
+	.port_type	= PCIE_RC_PORT,
 	.service	= PCIE_PORT_SERVICE_AER,
 
 	.probe		= aer_probe,
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 06b965623962..10731373d00e 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1201,6 +1201,7 @@ static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
 			switch(dev->subsystem_device) {
 			case 0x00b8: /* Compaq Evo D510 CMT */
 			case 0x00b9: /* Compaq Evo D510 SFF */
+			case 0x00ba: /* Compaq Evo D510 USDT */
 				/* Motherboard doesn't have Host bridge
 				 * subvendor/subdevice IDs and on-board VGA
 				 * controller is disabled if an AGP card is
@@ -2382,8 +2383,10 @@ static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
 }
 
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
 
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
 
 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
 {
@@ -2492,6 +2495,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov);
 
 #endif	/* CONFIG_PCI_IOV */
 
diff --git a/drivers/pcmcia/at91_cf.c b/drivers/pcmcia/at91_cf.c
index 9e1140f085fd..e1dccedc5960 100644
--- a/drivers/pcmcia/at91_cf.c
+++ b/drivers/pcmcia/at91_cf.c
@@ -363,7 +363,7 @@ static int at91_cf_suspend(struct platform_device *pdev, pm_message_t mesg)
 	struct at91_cf_socket	*cf = platform_get_drvdata(pdev);
 	struct at91_cf_data	*board = cf->board;
 
-	pcmcia_socket_dev_suspend(&pdev->dev, mesg);
+	pcmcia_socket_dev_suspend(&pdev->dev);
 	if (device_may_wakeup(&pdev->dev)) {
 		enable_irq_wake(board->det_pin);
 		if (board->irq_pin)
diff --git a/drivers/pcmcia/au1000_generic.c b/drivers/pcmcia/au1000_generic.c
index 90013341cd5f..02088704ac2c 100644
--- a/drivers/pcmcia/au1000_generic.c
+++ b/drivers/pcmcia/au1000_generic.c
@@ -515,7 +515,7 @@ static int au1x00_drv_pcmcia_probe(struct platform_device *dev)
 static int au1x00_drv_pcmcia_suspend(struct platform_device *dev,
 				     pm_message_t state)
 {
-	return pcmcia_socket_dev_suspend(&dev->dev, state);
+	return pcmcia_socket_dev_suspend(&dev->dev);
 }
 
 static int au1x00_drv_pcmcia_resume(struct platform_device *dev)
diff --git a/drivers/pcmcia/bfin_cf_pcmcia.c b/drivers/pcmcia/bfin_cf_pcmcia.c
index b59d4115d20f..300b368605c9 100644
--- a/drivers/pcmcia/bfin_cf_pcmcia.c
+++ b/drivers/pcmcia/bfin_cf_pcmcia.c
@@ -302,7 +302,7 @@ static int __devexit bfin_cf_remove(struct platform_device *pdev)
 
 static int bfin_cf_suspend(struct platform_device *pdev, pm_message_t mesg)
 {
-	return pcmcia_socket_dev_suspend(&pdev->dev, mesg);
+	return pcmcia_socket_dev_suspend(&pdev->dev);
 }
 
 static int bfin_cf_resume(struct platform_device *pdev)
diff --git a/drivers/pcmcia/cs.c b/drivers/pcmcia/cs.c
index 0660ad182589..698d75cda084 100644
--- a/drivers/pcmcia/cs.c
+++ b/drivers/pcmcia/cs.c
@@ -98,10 +98,13 @@ EXPORT_SYMBOL(pcmcia_socket_list_rwsem);
  * These functions check for the appropriate struct pcmcia_soket arrays,
  * and pass them to the low-level functions pcmcia_{suspend,resume}_socket
  */
+static int socket_early_resume(struct pcmcia_socket *skt);
+static int socket_late_resume(struct pcmcia_socket *skt);
 static int socket_resume(struct pcmcia_socket *skt);
 static int socket_suspend(struct pcmcia_socket *skt);
 
-int pcmcia_socket_dev_suspend(struct device *dev, pm_message_t state)
+static void pcmcia_socket_dev_run(struct device *dev,
+				  int (*cb)(struct pcmcia_socket *))
 {
 	struct pcmcia_socket *socket;
 
@@ -110,29 +113,34 @@ int pcmcia_socket_dev_suspend(struct device *dev, pm_message_t state)
 		if (socket->dev.parent != dev)
 			continue;
 		mutex_lock(&socket->skt_mutex);
-		socket_suspend(socket);
+		cb(socket);
 		mutex_unlock(&socket->skt_mutex);
 	}
 	up_read(&pcmcia_socket_list_rwsem);
+}
 
+int pcmcia_socket_dev_suspend(struct device *dev)
+{
+	pcmcia_socket_dev_run(dev, socket_suspend);
 	return 0;
 }
 EXPORT_SYMBOL(pcmcia_socket_dev_suspend);
 
-int pcmcia_socket_dev_resume(struct device *dev)
+void pcmcia_socket_dev_early_resume(struct device *dev)
 {
-	struct pcmcia_socket *socket;
+	pcmcia_socket_dev_run(dev, socket_early_resume);
+}
+EXPORT_SYMBOL(pcmcia_socket_dev_early_resume);
 
-	down_read(&pcmcia_socket_list_rwsem);
-	list_for_each_entry(socket, &pcmcia_socket_list, socket_list) {
-		if (socket->dev.parent != dev)
-			continue;
-		mutex_lock(&socket->skt_mutex);
-		socket_resume(socket);
-		mutex_unlock(&socket->skt_mutex);
-	}
-	up_read(&pcmcia_socket_list_rwsem);
+void pcmcia_socket_dev_late_resume(struct device *dev)
+{
+	pcmcia_socket_dev_run(dev, socket_late_resume);
+}
+EXPORT_SYMBOL(pcmcia_socket_dev_late_resume);
 
+int pcmcia_socket_dev_resume(struct device *dev)
+{
+	pcmcia_socket_dev_run(dev, socket_resume);
 	return 0;
 }
 EXPORT_SYMBOL(pcmcia_socket_dev_resume);
@@ -546,29 +554,24 @@ static int socket_suspend(struct pcmcia_socket *skt)
 	return 0;
 }
 
-/*
- * Resume a socket.  If a card is present, verify its CIS against
- * our cached copy.  If they are different, the card has been
- * replaced, and we need to tell the drivers.
- */
-static int socket_resume(struct pcmcia_socket *skt)
+static int socket_early_resume(struct pcmcia_socket *skt)
 {
-	int ret;
-
-	if (!(skt->state & SOCKET_SUSPEND))
-		return -EBUSY;
-
 	skt->socket = dead_socket;
 	skt->ops->init(skt);
 	skt->ops->set_socket(skt, &skt->socket);
+	if (skt->state & SOCKET_PRESENT)
+		skt->resume_status = socket_setup(skt, resume_delay);
+	return 0;
+}
 
+static int socket_late_resume(struct pcmcia_socket *skt)
+{
 	if (!(skt->state & SOCKET_PRESENT)) {
 		skt->state &= ~SOCKET_SUSPEND;
 		return socket_insert(skt);
 	}
 
-	ret = socket_setup(skt, resume_delay);
-	if (ret == 0) {
+	if (skt->resume_status == 0) {
 		/*
 		 * FIXME: need a better check here for cardbus cards.
 		 */
@@ -596,6 +599,20 @@ static int socket_resume(struct pcmcia_socket *skt)
 	return 0;
 }
 
+/*
+ * Resume a socket.  If a card is present, verify its CIS against
+ * our cached copy.  If they are different, the card has been
+ * replaced, and we need to tell the drivers.
+ */
+static int socket_resume(struct pcmcia_socket *skt)
+{
+	if (!(skt->state & SOCKET_SUSPEND))
+		return -EBUSY;
+
+	socket_early_resume(skt);
+	return socket_late_resume(skt);
+}
+
 static void socket_remove(struct pcmcia_socket *skt)
 {
 	dev_printk(KERN_NOTICE, &skt->dev,
diff --git a/drivers/pcmcia/i82092.c b/drivers/pcmcia/i82092.c
index 46561face128..a04f21c8170f 100644
--- a/drivers/pcmcia/i82092.c
+++ b/drivers/pcmcia/i82092.c
@@ -42,7 +42,7 @@ MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids);
 #ifdef CONFIG_PM
 static int i82092aa_socket_suspend (struct pci_dev *dev, pm_message_t state)
 {
-	return pcmcia_socket_dev_suspend(&dev->dev, state);
+	return pcmcia_socket_dev_suspend(&dev->dev);
 }
 
 static int i82092aa_socket_resume (struct pci_dev *dev)
diff --git a/drivers/pcmcia/i82365.c b/drivers/pcmcia/i82365.c
index 40d4953e4b12..b906abe26ad0 100644
--- a/drivers/pcmcia/i82365.c
+++ b/drivers/pcmcia/i82365.c
@@ -1241,7 +1241,7 @@ static int pcic_init(struct pcmcia_socket *s)
 static int i82365_drv_pcmcia_suspend(struct platform_device *dev,
 				     pm_message_t state)
 {
-	return pcmcia_socket_dev_suspend(&dev->dev, state);
+	return pcmcia_socket_dev_suspend(&dev->dev);
 }
 
 static int i82365_drv_pcmcia_resume(struct platform_device *dev)
diff --git a/drivers/pcmcia/m32r_cfc.c b/drivers/pcmcia/m32r_cfc.c
index 62b4ecc97c46..d1d89c4491ad 100644
--- a/drivers/pcmcia/m32r_cfc.c
+++ b/drivers/pcmcia/m32r_cfc.c
@@ -699,7 +699,7 @@ static struct pccard_operations pcc_operations = {
 static int cfc_drv_pcmcia_suspend(struct platform_device *dev,
 				     pm_message_t state)
 {
-	return pcmcia_socket_dev_suspend(&dev->dev, state);
+	return pcmcia_socket_dev_suspend(&dev->dev);
 }
 
 static int cfc_drv_pcmcia_resume(struct platform_device *dev)
diff --git a/drivers/pcmcia/m32r_pcc.c b/drivers/pcmcia/m32r_pcc.c
index 12034b41d196..a0655839c8d3 100644
--- a/drivers/pcmcia/m32r_pcc.c
+++ b/drivers/pcmcia/m32r_pcc.c
@@ -675,7 +675,7 @@ static struct pccard_operations pcc_operations = {
 static int pcc_drv_pcmcia_suspend(struct platform_device *dev,
 				     pm_message_t state)
 {
-	return pcmcia_socket_dev_suspend(&dev->dev, state);
+	return pcmcia_socket_dev_suspend(&dev->dev);
 }
 
 static int pcc_drv_pcmcia_resume(struct platform_device *dev)
diff --git a/drivers/pcmcia/m8xx_pcmcia.c b/drivers/pcmcia/m8xx_pcmcia.c
index d1ad0966392d..c69f2c4fe520 100644
--- a/drivers/pcmcia/m8xx_pcmcia.c
+++ b/drivers/pcmcia/m8xx_pcmcia.c
@@ -1296,7 +1296,7 @@ static int m8xx_remove(struct of_device *ofdev)
 #ifdef CONFIG_PM
 static int m8xx_suspend(struct platform_device *pdev, pm_message_t state)
 {
-	return pcmcia_socket_dev_suspend(&pdev->dev, state);
+	return pcmcia_socket_dev_suspend(&pdev->dev);
 }
 
 static int m8xx_resume(struct platform_device *pdev)
diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c
index f3736398900e..68570bc3ac86 100644
--- a/drivers/pcmcia/omap_cf.c
+++ b/drivers/pcmcia/omap_cf.c
@@ -334,7 +334,7 @@ static int __exit omap_cf_remove(struct platform_device *pdev)
 
 static int omap_cf_suspend(struct platform_device *pdev, pm_message_t mesg)
 {
-	return pcmcia_socket_dev_suspend(&pdev->dev, mesg);
+	return pcmcia_socket_dev_suspend(&pdev->dev);
 }
 
 static int omap_cf_resume(struct platform_device *pdev)
diff --git a/drivers/pcmcia/pd6729.c b/drivers/pcmcia/pd6729.c
index 8bed1dab9039..1c39d3438f20 100644
--- a/drivers/pcmcia/pd6729.c
+++ b/drivers/pcmcia/pd6729.c
@@ -758,7 +758,7 @@ static void __devexit pd6729_pci_remove(struct pci_dev *dev)
 #ifdef CONFIG_PM
 static int pd6729_socket_suspend(struct pci_dev *dev, pm_message_t state)
 {
-	return pcmcia_socket_dev_suspend(&dev->dev, state);
+	return pcmcia_socket_dev_suspend(&dev->dev);
 }
 
 static int pd6729_socket_resume(struct pci_dev *dev)
diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c
index c49a7269f6d1..86ad87604241 100644
--- a/drivers/pcmcia/pxa2xx_base.c
+++ b/drivers/pcmcia/pxa2xx_base.c
@@ -302,7 +302,7 @@ static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
 
 static int pxa2xx_drv_pcmcia_suspend(struct platform_device *dev, pm_message_t state)
 {
-	return pcmcia_socket_dev_suspend(&dev->dev, state);
+	return pcmcia_socket_dev_suspend(&dev->dev);
 }
 
 static int pxa2xx_drv_pcmcia_resume(struct platform_device *dev)
diff --git a/drivers/pcmcia/sa1100_generic.c b/drivers/pcmcia/sa1100_generic.c
index d8da5ac844e9..2d0e99751530 100644
--- a/drivers/pcmcia/sa1100_generic.c
+++ b/drivers/pcmcia/sa1100_generic.c
@@ -89,7 +89,7 @@ static int sa11x0_drv_pcmcia_remove(struct platform_device *dev)
 static int sa11x0_drv_pcmcia_suspend(struct platform_device *dev,
 				     pm_message_t state)
 {
-	return pcmcia_socket_dev_suspend(&dev->dev, state);
+	return pcmcia_socket_dev_suspend(&dev->dev);
 }
 
 static int sa11x0_drv_pcmcia_resume(struct platform_device *dev)
diff --git a/drivers/pcmcia/sa1111_generic.c b/drivers/pcmcia/sa1111_generic.c
index 401052a21ce8..4be4e172ffa1 100644
--- a/drivers/pcmcia/sa1111_generic.c
+++ b/drivers/pcmcia/sa1111_generic.c
@@ -159,7 +159,7 @@ static int __devexit pcmcia_remove(struct sa1111_dev *dev)
 
 static int pcmcia_suspend(struct sa1111_dev *dev, pm_message_t state)
 {
-	return pcmcia_socket_dev_suspend(&dev->dev, state);
+	return pcmcia_socket_dev_suspend(&dev->dev);
 }
 
 static int pcmcia_resume(struct sa1111_dev *dev)
diff --git a/drivers/pcmcia/tcic.c b/drivers/pcmcia/tcic.c
index 8eb04230fec7..582413fcb62f 100644
--- a/drivers/pcmcia/tcic.c
+++ b/drivers/pcmcia/tcic.c
@@ -366,7 +366,7 @@ static int __init get_tcic_id(void)
 static int tcic_drv_pcmcia_suspend(struct platform_device *dev,
 				     pm_message_t state)
 {
-	return pcmcia_socket_dev_suspend(&dev->dev, state);
+	return pcmcia_socket_dev_suspend(&dev->dev);
 }
 
 static int tcic_drv_pcmcia_resume(struct platform_device *dev)
diff --git a/drivers/pcmcia/vrc4171_card.c b/drivers/pcmcia/vrc4171_card.c
index d4ad50d737b0..c9fcbdc164ea 100644
--- a/drivers/pcmcia/vrc4171_card.c
+++ b/drivers/pcmcia/vrc4171_card.c
@@ -707,7 +707,7 @@ __setup("vrc4171_card=", vrc4171_card_setup);
 static int vrc4171_card_suspend(struct platform_device *dev,
 				     pm_message_t state)
 {
-	return pcmcia_socket_dev_suspend(&dev->dev, state);
+	return pcmcia_socket_dev_suspend(&dev->dev);
 }
 
 static int vrc4171_card_resume(struct platform_device *dev)
diff --git a/drivers/pcmcia/yenta_socket.c b/drivers/pcmcia/yenta_socket.c
index 3ecd7c99d8eb..bcebffb54b25 100644
--- a/drivers/pcmcia/yenta_socket.c
+++ b/drivers/pcmcia/yenta_socket.c
@@ -1225,60 +1225,81 @@ static int __devinit yenta_probe (struct pci_dev *dev, const struct pci_device_i
 }
 
 #ifdef CONFIG_PM
-static int yenta_dev_suspend (struct pci_dev *dev, pm_message_t state)
+static int yenta_dev_suspend_noirq(struct device *dev)
 {
-	struct yenta_socket *socket = pci_get_drvdata(dev);
+	struct pci_dev *pdev = to_pci_dev(dev);
+	struct yenta_socket *socket = pci_get_drvdata(pdev);
 	int ret;
 
-	ret = pcmcia_socket_dev_suspend(&dev->dev, state);
+	ret = pcmcia_socket_dev_suspend(dev);
 
-	if (socket) {
-		if (socket->type && socket->type->save_state)
-			socket->type->save_state(socket);
+	if (!socket)
+		return ret;
 
-		/* FIXME: pci_save_state needs to have a better interface */
-		pci_save_state(dev);
-		pci_read_config_dword(dev, 16*4, &socket->saved_state[0]);
-		pci_read_config_dword(dev, 17*4, &socket->saved_state[1]);
-		pci_disable_device(dev);
+	if (socket->type && socket->type->save_state)
+		socket->type->save_state(socket);
 
-		/*
-		 * Some laptops (IBM T22) do not like us putting the Cardbus
-		 * bridge into D3.  At a guess, some other laptop will
-		 * probably require this, so leave it commented out for now.
-		 */
-		/* pci_set_power_state(dev, 3); */
-	}
+	pci_save_state(pdev);
+	pci_read_config_dword(pdev, 16*4, &socket->saved_state[0]);
+	pci_read_config_dword(pdev, 17*4, &socket->saved_state[1]);
+	pci_disable_device(pdev);
+
+	/*
+	 * Some laptops (IBM T22) do not like us putting the Cardbus
+	 * bridge into D3.  At a guess, some other laptop will
+	 * probably require this, so leave it commented out for now.
+	 */
+	/* pci_set_power_state(dev, 3); */
 
 	return ret;
 }
 
-
-static int yenta_dev_resume (struct pci_dev *dev)
+static int yenta_dev_resume_noirq(struct device *dev)
 {
-	struct yenta_socket *socket = pci_get_drvdata(dev);
+	struct pci_dev *pdev = to_pci_dev(dev);
+	struct yenta_socket *socket = pci_get_drvdata(pdev);
+	int ret;
 
-	if (socket) {
-		int rc;
+	if (!socket)
+		return 0;
 
-		pci_set_power_state(dev, 0);
-		/* FIXME: pci_restore_state needs to have a better interface */
-		pci_restore_state(dev);
-		pci_write_config_dword(dev, 16*4, socket->saved_state[0]);
-		pci_write_config_dword(dev, 17*4, socket->saved_state[1]);
+	pci_write_config_dword(pdev, 16*4, socket->saved_state[0]);
+	pci_write_config_dword(pdev, 17*4, socket->saved_state[1]);
 
-		rc = pci_enable_device(dev);
-		if (rc)
-			return rc;
+	ret = pci_enable_device(pdev);
+	if (ret)
+		return ret;
 
-		pci_set_master(dev);
+	pci_set_master(pdev);
 
-		if (socket->type && socket->type->restore_state)
-			socket->type->restore_state(socket);
-	}
+	if (socket->type && socket->type->restore_state)
+		socket->type->restore_state(socket);
+
+	pcmcia_socket_dev_early_resume(dev);
+	return 0;
+}
 
-	return pcmcia_socket_dev_resume(&dev->dev);
+static int yenta_dev_resume(struct device *dev)
+{
+	pcmcia_socket_dev_late_resume(dev);
+	return 0;
 }
+
+static struct dev_pm_ops yenta_pm_ops = {
+	.suspend_noirq = yenta_dev_suspend_noirq,
+	.resume_noirq = yenta_dev_resume_noirq,
+	.resume = yenta_dev_resume,
+	.freeze_noirq = yenta_dev_suspend_noirq,
+	.thaw_noirq = yenta_dev_resume_noirq,
+	.thaw = yenta_dev_resume,
+	.poweroff_noirq = yenta_dev_suspend_noirq,
+	.restore_noirq = yenta_dev_resume_noirq,
+	.restore = yenta_dev_resume,
+};
+
+#define YENTA_PM_OPS	(&yenta_pm_ops)
+#else
+#define YENTA_PM_OPS	NULL
 #endif
 
 #define CB_ID(vend,dev,type)				\
@@ -1376,10 +1397,7 @@ static struct pci_driver yenta_cardbus_driver = {
 	.id_table	= yenta_table,
 	.probe		= yenta_probe,
 	.remove		= __devexit_p(yenta_close),
-#ifdef CONFIG_PM
-	.suspend	= yenta_dev_suspend,
-	.resume		= yenta_dev_resume,
-#endif
+	.driver.pm	= YENTA_PM_OPS,
 };
 
 
diff --git a/drivers/platform/x86/acerhdf.c b/drivers/platform/x86/acerhdf.c
index bdfee177eefb..034ca6d9081d 100644
--- a/drivers/platform/x86/acerhdf.c
+++ b/drivers/platform/x86/acerhdf.c
@@ -52,7 +52,7 @@
  */
 #undef START_IN_KERNEL_MODE
 
-#define DRV_VER "0.5.13"
+#define DRV_VER "0.5.16"
 
 /*
  * According to the Atom N270 datasheet,
@@ -61,7 +61,7 @@
  * measured by the on-die thermal monitor are within 0 <= Tj <= 90. So,
  * assume 89°C is critical temperature.
  */
-#define ACERHDF_TEMP_CRIT 89
+#define ACERHDF_TEMP_CRIT 89000
 #define ACERHDF_FAN_OFF 0
 #define ACERHDF_FAN_AUTO 1
 
@@ -69,7 +69,7 @@
  * No matter what value the user puts into the fanon variable, turn on the fan
  * at 80 degree Celsius to prevent hardware damage
  */
-#define ACERHDF_MAX_FANON 80
+#define ACERHDF_MAX_FANON 80000
 
 /*
  * Maximum interval between two temperature checks is 15 seconds, as the die
@@ -85,11 +85,12 @@ static int kernelmode;
 #endif
 
 static unsigned int interval = 10;
-static unsigned int fanon = 63;
-static unsigned int fanoff = 58;
+static unsigned int fanon = 63000;
+static unsigned int fanoff = 58000;
 static unsigned int verbose;
 static unsigned int fanstate = ACERHDF_FAN_AUTO;
 static char force_bios[16];
+static char force_product[16];
 static unsigned int prev_interval;
 struct thermal_zone_device *thz_dev;
 struct thermal_cooling_device *cl_dev;
@@ -107,34 +108,62 @@ module_param(verbose, uint, 0600);
 MODULE_PARM_DESC(verbose, "Enable verbose dmesg output");
 module_param_string(force_bios, force_bios, 16, 0);
 MODULE_PARM_DESC(force_bios, "Force BIOS version and omit BIOS check");
+module_param_string(force_product, force_product, 16, 0);
+MODULE_PARM_DESC(force_product, "Force BIOS product and omit BIOS check");
+
+/*
+ * cmd_off: to switch the fan completely off / to check if the fan is off
+ *	cmd_auto: to set the BIOS in control of the fan. The BIOS regulates then
+ *		the fan speed depending on the temperature
+ */
+struct fancmd {
+	u8 cmd_off;
+	u8 cmd_auto;
+};
 
 /* BIOS settings */
 struct bios_settings_t {
 	const char *vendor;
+	const char *product;
 	const char *version;
 	unsigned char fanreg;
 	unsigned char tempreg;
-	unsigned char fancmd[2]; /* fan off and auto commands */
+	struct fancmd cmd;
 };
 
 /* Register addresses and values for different BIOS versions */
 static const struct bios_settings_t bios_tbl[] = {
-	{"Acer", "v0.3109", 0x55, 0x58, {0x1f, 0x00} },
-	{"Acer", "v0.3114", 0x55, 0x58, {0x1f, 0x00} },
-	{"Acer", "v0.3301", 0x55, 0x58, {0xaf, 0x00} },
-	{"Acer", "v0.3304", 0x55, 0x58, {0xaf, 0x00} },
-	{"Acer", "v0.3305", 0x55, 0x58, {0xaf, 0x00} },
-	{"Acer", "v0.3308", 0x55, 0x58, {0x21, 0x00} },
-	{"Acer", "v0.3309", 0x55, 0x58, {0x21, 0x00} },
-	{"Acer", "v0.3310", 0x55, 0x58, {0x21, 0x00} },
-	{"Gateway", "v0.3103", 0x55, 0x58, {0x21, 0x00} },
-	{"Packard Bell", "v0.3105", 0x55, 0x58, {0x21, 0x00} },
-	{"", "", 0, 0, {0, 0} }
+	/* AOA110 */
+	{"Acer", "AOA110", "v0.3109", 0x55, 0x58, {0x1f, 0x00} },
+	{"Acer", "AOA110", "v0.3114", 0x55, 0x58, {0x1f, 0x00} },
+	{"Acer", "AOA110", "v0.3301", 0x55, 0x58, {0xaf, 0x00} },
+	{"Acer", "AOA110", "v0.3304", 0x55, 0x58, {0xaf, 0x00} },
+	{"Acer", "AOA110", "v0.3305", 0x55, 0x58, {0xaf, 0x00} },
+	{"Acer", "AOA110", "v0.3307", 0x55, 0x58, {0xaf, 0x00} },
+	{"Acer", "AOA110", "v0.3308", 0x55, 0x58, {0x21, 0x00} },
+	{"Acer", "AOA110", "v0.3309", 0x55, 0x58, {0x21, 0x00} },
+	{"Acer", "AOA110", "v0.3310", 0x55, 0x58, {0x21, 0x00} },
+	/* AOA150 */
+	{"Acer", "AOA150", "v0.3114", 0x55, 0x58, {0x20, 0x00} },
+	{"Acer", "AOA150", "v0.3301", 0x55, 0x58, {0x20, 0x00} },
+	{"Acer", "AOA150", "v0.3304", 0x55, 0x58, {0x20, 0x00} },
+	{"Acer", "AOA150", "v0.3305", 0x55, 0x58, {0x20, 0x00} },
+	{"Acer", "AOA150", "v0.3307", 0x55, 0x58, {0x20, 0x00} },
+	{"Acer", "AOA150", "v0.3308", 0x55, 0x58, {0x20, 0x00} },
+	{"Acer", "AOA150", "v0.3309", 0x55, 0x58, {0x20, 0x00} },
+	{"Acer", "AOA150", "v0.3310", 0x55, 0x58, {0x20, 0x00} },
+	/* special BIOS / other */
+	{"Gateway", "AOA110", "v0.3103", 0x55, 0x58, {0x21, 0x00} },
+	{"Gateway", "AOA150", "v0.3103", 0x55, 0x58, {0x20, 0x00} },
+	{"Packard Bell", "DOA150", "v0.3104", 0x55, 0x58, {0x21, 0x00} },
+	{"Packard Bell", "AOA110", "v0.3105", 0x55, 0x58, {0x21, 0x00} },
+	{"Packard Bell", "AOA150", "v0.3105", 0x55, 0x58, {0x20, 0x00} },
+	/* pewpew-terminator */
+	{"", "", "", 0, 0, {0, 0} }
 };
 
 static const struct bios_settings_t *bios_cfg __read_mostly;
 
-
 static int acerhdf_get_temp(int *temp)
 {
 	u8 read_temp;
@@ -142,7 +171,7 @@ static int acerhdf_get_temp(int *temp)
 	if (ec_read(bios_cfg->tempreg, &read_temp))
 		return -EINVAL;
 
-	*temp = read_temp;
+	*temp = read_temp * 1000;
 
 	return 0;
 }
@@ -150,13 +179,14 @@ static int acerhdf_get_temp(int *temp)
 static int acerhdf_get_fanstate(int *state)
 {
 	u8 fan;
-	bool tmp;
 
 	if (ec_read(bios_cfg->fanreg, &fan))
 		return -EINVAL;
 
-	tmp = (fan == bios_cfg->fancmd[ACERHDF_FAN_OFF]);
-	*state = tmp ? ACERHDF_FAN_OFF : ACERHDF_FAN_AUTO;
+	if (fan != bios_cfg->cmd.cmd_off)
+		*state = ACERHDF_FAN_AUTO;
+	else
+		*state = ACERHDF_FAN_OFF;
 
 	return 0;
 }
@@ -175,7 +205,8 @@ static void acerhdf_change_fanstate(int state)
 		state = ACERHDF_FAN_AUTO;
 	}
 
-	cmd = bios_cfg->fancmd[state];
+	cmd = (state == ACERHDF_FAN_OFF) ? bios_cfg->cmd.cmd_off
+					 : bios_cfg->cmd.cmd_auto;
 	fanstate = state;
 
 	ec_write(bios_cfg->fanreg, cmd);
@@ -437,7 +468,7 @@ static int acerhdf_remove(struct platform_device *device)
 	return 0;
 }
 
-struct platform_driver acerhdf_drv = {
+static struct platform_driver acerhdf_driver = {
 	.driver = {
 		.name = "acerhdf",
 		.owner = THIS_MODULE,
@@ -454,32 +485,40 @@ static int acerhdf_check_hardware(void)
 {
 	char const *vendor, *version, *product;
 	int i;
+	unsigned long prod_len = 0;
 
 	/* get BIOS data */
 	vendor  = dmi_get_system_info(DMI_SYS_VENDOR);
 	version = dmi_get_system_info(DMI_BIOS_VERSION);
 	product = dmi_get_system_info(DMI_PRODUCT_NAME);
 
+
 	pr_info("Acer Aspire One Fan driver, v.%s\n", DRV_VER);
 
-	if (!force_bios[0]) {
-		if (strncmp(product, "AO", 2)) {
-			pr_err("no Aspire One hardware found\n");
-			return -EINVAL;
-		}
-	} else {
-		pr_info("forcing BIOS version: %s\n", version);
+	if (force_bios[0]) {
 		version = force_bios;
+		pr_info("forcing BIOS version: %s\n", version);
 		kernelmode = 0;
 	}
 
+	if (force_product[0]) {
+		product = force_product;
+		pr_info("forcing BIOS product: %s\n", product);
+		kernelmode = 0;
+	}
+
+	prod_len = strlen(product);
+
 	if (verbose)
 		pr_info("BIOS info: %s %s, product: %s\n",
 			vendor, version, product);
 
 	/* search BIOS version and vendor in BIOS settings table */
 	for (i = 0; bios_tbl[i].version[0]; i++) {
-		if (!strcmp(bios_tbl[i].vendor, vendor) &&
+		if (strlen(bios_tbl[i].product) >= prod_len &&
+		    !strncmp(bios_tbl[i].product, product,
+			   strlen(bios_tbl[i].product)) &&
+		    !strcmp(bios_tbl[i].vendor, vendor) &&
 		    !strcmp(bios_tbl[i].version, version)) {
 			bios_cfg = &bios_tbl[i];
 			break;
@@ -487,8 +526,8 @@ static int acerhdf_check_hardware(void)
 	}
 
 	if (!bios_cfg) {
-		pr_err("unknown (unsupported) BIOS version %s/%s, "
-			"please report, aborting!\n", vendor, version);
+		pr_err("unknown (unsupported) BIOS version %s/%s/%s, "
+			"please report, aborting!\n", vendor, product, version);
 		return -EINVAL;
 	}
 
@@ -509,7 +548,7 @@ static int acerhdf_register_platform(void)
 {
 	int err = 0;
 
-	err = platform_driver_register(&acerhdf_drv);
+	err = platform_driver_register(&acerhdf_driver);
 	if (err)
 		return err;
 
@@ -525,7 +564,7 @@ static void acerhdf_unregister_platform(void)
 		return;
 
 	platform_device_del(acerhdf_dev);
-	platform_driver_unregister(&acerhdf_drv);
+	platform_driver_unregister(&acerhdf_driver);
 }
 
 static int acerhdf_register_thermal(void)
@@ -594,9 +633,10 @@ static void __exit acerhdf_exit(void)
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Peter Feuerer");
 MODULE_DESCRIPTION("Aspire One temperature and fan driver");
-MODULE_ALIAS("dmi:*:*Acer*:*:");
-MODULE_ALIAS("dmi:*:*Gateway*:*:");
-MODULE_ALIAS("dmi:*:*Packard Bell*:*:");
+MODULE_ALIAS("dmi:*:*Acer*:pnAOA*:");
+MODULE_ALIAS("dmi:*:*Gateway*:pnAOA*:");
+MODULE_ALIAS("dmi:*:*Packard Bell*:pnAOA*:");
+MODULE_ALIAS("dmi:*:*Packard Bell*:pnDOA*:");
 
 module_init(acerhdf_init);
 module_exit(acerhdf_exit);
diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c
index db657bbeec90..fae1951cb753 100644
--- a/drivers/platform/x86/asus-laptop.c
+++ b/drivers/platform/x86/asus-laptop.c
@@ -1172,8 +1172,8 @@ static int asus_hotk_add(struct acpi_device *device)
 	hotk->ledd_status = 0xFFF;
 
 	/* Set initial values of light sensor and level */
-	hotk->light_switch = 1;	/* Default to light sensor disabled */
-	hotk->light_level = 0;	/* level 5 for sensor sensitivity */
+	hotk->light_switch = 0;	/* Default to light sensor disabled */
+	hotk->light_level = 5;	/* level 5 for sensor sensitivity */
 
 	if (ls_switch_handle)
 		set_light_sens_switch(hotk->light_switch);
diff --git a/drivers/platform/x86/sony-laptop.c b/drivers/platform/x86/sony-laptop.c
index dafaa4a92df5..a234a9db15d9 100644
--- a/drivers/platform/x86/sony-laptop.c
+++ b/drivers/platform/x86/sony-laptop.c
@@ -1081,6 +1081,8 @@ static int sony_nc_setup_rfkill(struct acpi_device *device,
 	struct rfkill *rfk;
 	enum rfkill_type type;
 	const char *name;
+	int result;
+	bool hwblock;
 
 	switch (nc_type) {
 	case SONY_WIFI:
@@ -1108,6 +1110,10 @@ static int sony_nc_setup_rfkill(struct acpi_device *device,
 	if (!rfk)
 		return -ENOMEM;
 
+	sony_call_snc_handle(0x124, 0x200, &result);
+	hwblock = !(result & 0x1);
+	rfkill_set_hw_state(rfk, hwblock);
+
 	err = rfkill_register(rfk);
 	if (err) {
 		rfkill_destroy(rfk);
diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c
index e85600852502..05e5d56f9c82 100644
--- a/drivers/platform/x86/thinkpad_acpi.c
+++ b/drivers/platform/x86/thinkpad_acpi.c
@@ -3406,15 +3406,6 @@ enum {
 
 #define TPACPI_RFK_BLUETOOTH_SW_NAME	"tpacpi_bluetooth_sw"
 
-static void bluetooth_suspend(pm_message_t state)
-{
-	/* Try to make sure radio will resume powered off */
-	if (!acpi_evalf(NULL, NULL, "\\BLTH", "vd",
-		   TP_ACPI_BLTH_PWR_OFF_ON_RESUME))
-		vdbg_printk(TPACPI_DBG_RFKILL,
-			"bluetooth power down on resume request failed\n");
-}
-
 static int bluetooth_get_status(void)
 {
 	int status;
@@ -3448,10 +3439,9 @@ static int bluetooth_set_status(enum tpacpi_rfkill_state state)
 #endif
 
 	/* We make sure to keep TP_ACPI_BLUETOOTH_RESUMECTRL off */
+	status = TP_ACPI_BLUETOOTH_RESUMECTRL;
 	if (state == TPACPI_RFK_RADIO_ON)
-		status = TP_ACPI_BLUETOOTH_RADIOSSW;
-	else
-		status = 0;
+		status |= TP_ACPI_BLUETOOTH_RADIOSSW;
 
 	if (!acpi_evalf(hkey_handle, NULL, "SBDC", "vd", status))
 		return -EIO;
@@ -3590,7 +3580,6 @@ static struct ibm_struct bluetooth_driver_data = {
 	.read = bluetooth_read,
 	.write = bluetooth_write,
 	.exit = bluetooth_exit,
-	.suspend = bluetooth_suspend,
 	.shutdown = bluetooth_shutdown,
 };
 
@@ -3608,15 +3597,6 @@ enum {
 
 #define TPACPI_RFK_WWAN_SW_NAME		"tpacpi_wwan_sw"
 
-static void wan_suspend(pm_message_t state)
-{
-	/* Try to make sure radio will resume powered off */
-	if (!acpi_evalf(NULL, NULL, "\\WGSV", "qvd",
-		   TP_ACPI_WGSV_PWR_OFF_ON_RESUME))
-		vdbg_printk(TPACPI_DBG_RFKILL,
-			"WWAN power down on resume request failed\n");
-}
-
 static int wan_get_status(void)
 {
 	int status;
@@ -3649,11 +3629,10 @@ static int wan_set_status(enum tpacpi_rfkill_state state)
 	}
 #endif
 
-	/* We make sure to keep TP_ACPI_WANCARD_RESUMECTRL off */
+	/* We make sure to set TP_ACPI_WANCARD_RESUMECTRL */
+	status = TP_ACPI_WANCARD_RESUMECTRL;
 	if (state == TPACPI_RFK_RADIO_ON)
-		status = TP_ACPI_WANCARD_RADIOSSW;
-	else
-		status = 0;
+		status |= TP_ACPI_WANCARD_RADIOSSW;
 
 	if (!acpi_evalf(hkey_handle, NULL, "SWAN", "vd", status))
 		return -EIO;
@@ -3791,7 +3770,6 @@ static struct ibm_struct wan_driver_data = {
 	.read = wan_read,
 	.write = wan_write,
 	.exit = wan_exit,
-	.suspend = wan_suspend,
 	.shutdown = wan_shutdown,
 };
 
@@ -5655,16 +5633,16 @@ static const struct tpacpi_quirk brightness_quirk_table[] __initconst = {
 	/* Models with ATI GPUs known to require ECNVRAM mode */
 	TPACPI_Q_IBM('1', 'Y', TPACPI_BRGHT_Q_EC),	/* T43/p ATI */
 
-	/* Models with ATI GPUs (waiting confirmation) */
-	TPACPI_Q_IBM('1', 'R', TPACPI_BRGHT_Q_ASK|TPACPI_BRGHT_Q_EC),
+	/* Models with ATI GPUs that can use ECNVRAM */
+	TPACPI_Q_IBM('1', 'R', TPACPI_BRGHT_Q_EC),
 	TPACPI_Q_IBM('1', 'Q', TPACPI_BRGHT_Q_ASK|TPACPI_BRGHT_Q_EC),
 	TPACPI_Q_IBM('7', '6', TPACPI_BRGHT_Q_ASK|TPACPI_BRGHT_Q_EC),
 	TPACPI_Q_IBM('7', '8', TPACPI_BRGHT_Q_ASK|TPACPI_BRGHT_Q_EC),
 
-	/* Models with Intel Extreme Graphics 2 (waiting confirmation) */
-	TPACPI_Q_IBM('1', 'V', TPACPI_BRGHT_Q_ASK|TPACPI_BRGHT_Q_NOEC),
-	TPACPI_Q_IBM('1', 'W', TPACPI_BRGHT_Q_ASK|TPACPI_BRGHT_Q_NOEC),
-	TPACPI_Q_IBM('1', 'U', TPACPI_BRGHT_Q_ASK|TPACPI_BRGHT_Q_NOEC),
+	/* Models with Intel Extreme Graphics 2 */
+	TPACPI_Q_IBM('1', 'U', TPACPI_BRGHT_Q_NOEC),
+	TPACPI_Q_IBM('1', 'V', TPACPI_BRGHT_Q_ASK|TPACPI_BRGHT_Q_EC),
+	TPACPI_Q_IBM('1', 'W', TPACPI_BRGHT_Q_ASK|TPACPI_BRGHT_Q_EC),
 
 	/* Models with Intel GMA900 */
 	TPACPI_Q_IBM('7', '0', TPACPI_BRGHT_Q_NOEC),	/* T43, R52 */
@@ -5863,7 +5841,7 @@ static int brightness_write(char *buf)
 	 * Doing it this way makes the syscall restartable in case of EINTR
 	 */
 	rc = brightness_set(level);
-	return (rc == -EINTR)? ERESTARTSYS : rc;
+	return (rc == -EINTR)? -ERESTARTSYS : rc;
 }
 
 static struct ibm_struct brightness_driver_data = {
diff --git a/drivers/power/mxs/Makefile b/drivers/power/mxs/Makefile
index 6662defd9c70..c7675a9ec52b 100644
--- a/drivers/power/mxs/Makefile
+++ b/drivers/power/mxs/Makefile
@@ -5,5 +5,5 @@
 obj-$(CONFIG_BATTERY_MXS) += mxs-battery.o
 
 mxs-battery-objs := ddi_bc_api.o ddi_bc_hw.o ddi_bc_init.o \
-		         ddi_bc_ramp.o ddi_bc_sm.o ddi_power_battery.o linux.o
+		         ddi_bc_ramp.o ddi_bc_sm.o ddi_power_battery.o linux.o fiq.o
 
diff --git a/drivers/power/mxs/ddi_bc_internal.h b/drivers/power/mxs/ddi_bc_internal.h
index a8510d08935c..b5bceeffae98 100644
--- a/drivers/power/mxs/ddi_bc_internal.h
+++ b/drivers/power/mxs/ddi_bc_internal.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
  */
 
 /*
@@ -41,6 +41,7 @@
 
 /* Externs */
 
+#include <linux/kernel.h>
 
 extern bool g_ddi_bc_Configured;
 extern ddi_bc_Cfg_t g_ddi_bc_Configuration;
diff --git a/drivers/power/mxs/ddi_power_battery.c b/drivers/power/mxs/ddi_power_battery.c
index 6e2119af1676..762f29bd784e 100644
--- a/drivers/power/mxs/ddi_power_battery.c
+++ b/drivers/power/mxs/ddi_power_battery.c
@@ -1805,9 +1805,11 @@ void ddi_power_enable_vddio_interrupt(bool enable)
 
 }
 
+
 void ddi_power_handle_vddio_brnout(void)
 {
-	if (ddi_power_GetPmu5vStatus() == new_5v_connection) {
+	if (ddi_power_GetPmu5vStatus() == new_5v_connection ||
+		(ddi_power_GetPmu5vStatus() == new_5v_disconnection)) {
 		ddi_power_enable_vddio_interrupt(false);
 	} else {
 #ifdef DEBUG_IRQS
diff --git a/drivers/power/mxs/fiq.S b/drivers/power/mxs/fiq.S
index ee71730c85c9..1ad380d07efd 100644
--- a/drivers/power/mxs/fiq.S
+++ b/drivers/power/mxs/fiq.S
@@ -19,11 +19,10 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <mach/platform.h>
 #include <mach/hardware.h>
 #include <asm/pgtable-hwdef.h>
 #include <mach/regs-power.h>
-#include <mach/regs-clkctrl.h>
+#include <mach/../../regs-clkctrl.h>
 #include <mach/regs-timrot.h>
 
 	.align 5
@@ -33,7 +32,6 @@
 	.globl lock_vector_tlb
 
 power_fiq_start:
-
 	ldr 	r8,power_reg
 	ldr	r9,[r8,#HW_POWER_CTRL ]
 	ldr	r10,power_off
@@ -101,7 +99,7 @@ check_dcdc4p2:
 	subs    pc,lr, #4
 
 power_reg:
-	.long REGS_POWER_BASE
+	.long IO_ADDRESS(POWER_PHYS_ADDR)
 power_off:
 	.long 0x3e770001
 power_bo:
diff --git a/drivers/power/mxs/linux.c b/drivers/power/mxs/linux.c
index 6a3172415145..1c2dfc10f7ca 100644
--- a/drivers/power/mxs/linux.c
+++ b/drivers/power/mxs/linux.c
@@ -102,7 +102,7 @@ struct mxs_info {
 #define IRQ_DCDC4P2_BRNOUT IRQ_DCDC4P2_BO
 #endif
 
-/* #define  POWER_FIQ */
+#define  POWER_FIQ
 
 /* #define DEBUG_IRQS */
 
@@ -129,9 +129,7 @@ void init_protection(struct mxs_info *info)
 	battery_voltage = ddi_power_GetBattery();
 
 	/* InitializeFiqSystem(); */
-#ifdef CONFIG_ARCH_MX23
 	ddi_power_InitOutputBrownouts();
-#endif
 
 
 	/* if we start the kernel with 4p2 already started
@@ -238,12 +236,12 @@ static void check_and_handle_5v_connection(struct mxs_info *info)
 		*/
 		if ((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL)
 			& BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) ==
-			(0x8 << BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT)) {
+			(0x20 << BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT)) {
 			dev_info(info->dev, "waiting USB enum done...\r\n");
 		}
 		while ((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL)
 			& BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT)
-			== (0x8 << BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT)) {
+			== (0x20 << BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT)) {
 			msleep(50);
 		}
 	#endif
@@ -299,7 +297,7 @@ static void check_and_handle_5v_connection(struct mxs_info *info)
 				__raw_writel(__raw_readl(REGS_POWER_BASE +
 				HW_POWER_5VCTRL) &
 				(~BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT)
-				| (0x8 << BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT),
+				| (0x20 << BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT),
 				REGS_POWER_BASE + HW_POWER_5VCTRL);
 
 			}
@@ -659,6 +657,8 @@ static irqreturn_t mxs_irq_batt_brnout(int irq, void *cookie)
 #endif
 	return IRQ_HANDLED;
 }
+
+
 static irqreturn_t mxs_irq_vddd_brnout(int irq, void *cookie)
 {
 #ifdef DEBUG_IRQS
@@ -1144,13 +1144,13 @@ static int __init mxs_bat_init(void)
 
 #ifdef CONFIG_MXS_VBUS_CURRENT_DRAW
 	if (((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) &
-		BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) == 0x8000)
+		BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) == 0x20000)
 		&& ((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) &
 		BM_POWER_5VCTRL_PWD_CHARGE_4P2) == 0)) {
 #ifdef CONFIG_USB_GADGET
 		printk(KERN_INFO "USB GADGET exist,wait USB enum done...\r\n");
 		while (((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL)
-			& BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) == 0x8000) &&
+			& BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) == 0x20000) &&
 			((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) &
 			BM_POWER_5VCTRL_PWD_CHARGE_4P2) == 0))
 			;
@@ -1161,8 +1161,7 @@ static int __init mxs_bat_init(void)
 	}
 	cpu = clk_get(NULL, "cpu");
 	pll0 = clk_get(NULL, "ref_cpu");
-	if (cpu->set_parent)
-		cpu->set_parent(cpu, pll0);
+	clk_set_parent(cpu, pll0);
 #endif
 	return platform_driver_register(&mxs_batdrv);
 }
diff --git a/drivers/pps/kapi.c b/drivers/pps/kapi.c
index 35a0b192d768..2d414e23d390 100644
--- a/drivers/pps/kapi.c
+++ b/drivers/pps/kapi.c
@@ -271,6 +271,7 @@ void pps_event(int source, struct pps_ktime *ts, int event, void *data)
 {
 	struct pps_device *pps;
 	unsigned long flags;
+	int captured = 0;
 
 	if ((event & (PPS_CAPTUREASSERT | PPS_CAPTURECLEAR)) == 0) {
 		printk(KERN_ERR "pps: unknown event (%x) for source %d\n",
@@ -293,7 +294,8 @@ void pps_event(int source, struct pps_ktime *ts, int event, void *data)
 
 	/* Check the event */
 	pps->current_mode = pps->params.mode;
-	if (event & PPS_CAPTUREASSERT) {
+	if ((event & PPS_CAPTUREASSERT) &
+			(pps->params.mode & PPS_CAPTUREASSERT)) {
 		/* We have to add an offset? */
 		if (pps->params.mode & PPS_OFFSETASSERT)
 			pps_add_offset(ts, &pps->params.assert_off_tu);
@@ -303,8 +305,11 @@ void pps_event(int source, struct pps_ktime *ts, int event, void *data)
 		pps->assert_sequence++;
 		pr_debug("capture assert seq #%u for source %d\n",
 			pps->assert_sequence, source);
+
+		captured = ~0;
 	}
-	if (event & PPS_CAPTURECLEAR) {
+	if ((event & PPS_CAPTURECLEAR) &
+			(pps->params.mode & PPS_CAPTURECLEAR)) {
 		/* We have to add an offset? */
 		if (pps->params.mode & PPS_OFFSETCLEAR)
 			pps_add_offset(ts, &pps->params.clear_off_tu);
@@ -314,12 +319,17 @@ void pps_event(int source, struct pps_ktime *ts, int event, void *data)
 		pps->clear_sequence++;
 		pr_debug("capture clear seq #%u for source %d\n",
 			pps->clear_sequence, source);
+
+		captured = ~0;
 	}
 
-	pps->go = ~0;
-	wake_up_interruptible(&pps->queue);
+	/* Wake up iif captured somthing */
+	if (captured) {
+		pps->go = ~0;
+		wake_up_interruptible(&pps->queue);
 
-	kill_fasync(&pps->async_queue, SIGIO, POLL_IN);
+		kill_fasync(&pps->async_queue, SIGIO, POLL_IN);
+	}
 
 	spin_unlock_irqrestore(&pps->lock, flags);
 
diff --git a/drivers/pps/pps.c b/drivers/pps/pps.c
index fea17e7805e9..ca5183bdad85 100644
--- a/drivers/pps/pps.c
+++ b/drivers/pps/pps.c
@@ -71,9 +71,14 @@ static long pps_cdev_ioctl(struct file *file,
 	case PPS_GETPARAMS:
 		pr_debug("PPS_GETPARAMS: source %d\n", pps->id);
 
-		/* Return current parameters */
-		err = copy_to_user(uarg, &pps->params,
-						sizeof(struct pps_kparams));
+		spin_lock_irq(&pps->lock);
+
+		/* Get the current parameters */
+		params = pps->params;
+
+		spin_unlock_irq(&pps->lock);
+
+		err = copy_to_user(uarg, &params, sizeof(struct pps_kparams));
 		if (err)
 			return -EFAULT;
 
diff --git a/drivers/ps3/ps3stor_lib.c b/drivers/ps3/ps3stor_lib.c
index 18066d555397..af0afa1db4a8 100644
--- a/drivers/ps3/ps3stor_lib.c
+++ b/drivers/ps3/ps3stor_lib.c
@@ -23,6 +23,65 @@
 #include <asm/lv1call.h>
 #include <asm/ps3stor.h>
 
+/*
+ * A workaround for flash memory I/O errors when the internal hard disk
+ * has not been formatted for OtherOS use.  Delay disk close until flash
+ * memory is closed.
+ */
+
+static struct ps3_flash_workaround {
+	int flash_open;
+	int disk_open;
+	struct ps3_system_bus_device *disk_sbd;
+} ps3_flash_workaround;
+
+static int ps3stor_open_hv_device(struct ps3_system_bus_device *sbd)
+{
+	int error = ps3_open_hv_device(sbd);
+
+	if (error)
+		return error;
+
+	if (sbd->match_id == PS3_MATCH_ID_STOR_FLASH)
+		ps3_flash_workaround.flash_open = 1;
+
+	if (sbd->match_id == PS3_MATCH_ID_STOR_DISK)
+		ps3_flash_workaround.disk_open = 1;
+
+	return 0;
+}
+
+static int ps3stor_close_hv_device(struct ps3_system_bus_device *sbd)
+{
+	int error;
+
+	if (sbd->match_id == PS3_MATCH_ID_STOR_DISK
+		&& ps3_flash_workaround.disk_open
+		&& ps3_flash_workaround.flash_open) {
+		ps3_flash_workaround.disk_sbd = sbd;
+		return 0;
+	}
+
+	error = ps3_close_hv_device(sbd);
+
+	if (error)
+		return error;
+
+	if (sbd->match_id == PS3_MATCH_ID_STOR_DISK)
+		ps3_flash_workaround.disk_open = 0;
+
+	if (sbd->match_id == PS3_MATCH_ID_STOR_FLASH) {
+		ps3_flash_workaround.flash_open = 0;
+
+		if (ps3_flash_workaround.disk_sbd) {
+			ps3_close_hv_device(ps3_flash_workaround.disk_sbd);
+			ps3_flash_workaround.disk_open = 0;
+			ps3_flash_workaround.disk_sbd = NULL;
+		}
+	}
+
+	return 0;
+}
 
 static int ps3stor_probe_access(struct ps3_storage_device *dev)
 {
@@ -90,7 +149,7 @@ int ps3stor_setup(struct ps3_storage_device *dev, irq_handler_t handler)
 	int error, res, alignment;
 	enum ps3_dma_page_size page_size;
 
-	error = ps3_open_hv_device(&dev->sbd);
+	error = ps3stor_open_hv_device(&dev->sbd);
 	if (error) {
 		dev_err(&dev->sbd.core,
 			"%s:%u: ps3_open_hv_device failed %d\n", __func__,
@@ -166,7 +225,7 @@ fail_free_irq:
 fail_sb_event_receive_port_destroy:
 	ps3_sb_event_receive_port_destroy(&dev->sbd, dev->irq);
 fail_close_device:
-	ps3_close_hv_device(&dev->sbd);
+	ps3stor_close_hv_device(&dev->sbd);
 fail:
 	return error;
 }
@@ -193,7 +252,7 @@ void ps3stor_teardown(struct ps3_storage_device *dev)
 			"%s:%u: destroy event receive port failed %d\n",
 			__func__, __LINE__, error);
 
-	error = ps3_close_hv_device(&dev->sbd);
+	error = ps3stor_close_hv_device(&dev->sbd);
 	if (error)
 		dev_err(&dev->sbd.core,
 			"%s:%u: ps3_close_hv_device failed %d\n", __func__,
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index fd3183e30a1c..804c32cabb50 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -153,4 +153,9 @@ config REGULATOR_MC9S08DZ60
 	depends on MXC_PMIC_MC9S08DZ60
 	default y
 
+config REGULATOR_MAX17135
+	tristate "Maxim MAX17135 Regulator Support"
+	depends on REGULATOR
+	default n
+
 endif
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index a10178d99acc..d88116ba8139 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
 obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
 obj-$(CONFIG_REGULATOR_DA903X)	+= da903x.o
 obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o
+obj-$(CONFIG_REGULATOR_MAX17135) += max17135-regulator.o
 
 obj-$(CONFIG_REGULATOR_MC13892) += reg-mc13892.o
 obj-$(CONFIG_REGULATOR_MC13783) += reg-mc13783.o
diff --git a/drivers/regulator/max17135-regulator.c b/drivers/regulator/max17135-regulator.c
new file mode 100644
index 000000000000..3fdec795fbeb
--- /dev/null
+++ b/drivers/regulator/max17135-regulator.c
@@ -0,0 +1,736 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/max17135.h>
+#include <linux/gpio.h>
+
+/*
+ * Define this as 1 when using a Rev 1 MAX17135 part.  These parts have
+ * some limitations, including an inability to turn on the PMIC via I2C.
+ */
+#define MAX17135_REV 1
+
+/*
+ * PMIC Register Addresses
+ */
+enum {
+    REG_MAX17135_EXT_TEMP = 0x0,
+    REG_MAX17135_CONFIG,
+    REG_MAX17135_INT_TEMP = 0x4,
+    REG_MAX17135_STATUS,
+    REG_MAX17135_PRODUCT_REV,
+    REG_MAX17135_PRODUCT_ID,
+    REG_MAX17135_DVR,
+    REG_MAX17135_ENABLE,
+    REG_MAX17135_FAULT,  /*0x0A*/
+    REG_MAX17135_HVINP,
+    REG_MAX17135_PRGM_CTRL,
+    REG_MAX17135_TIMING1 = 0x10,    /* Timing regs base address is 0x10 */
+    REG_MAX17135_TIMING2,
+    REG_MAX17135_TIMING3,
+    REG_MAX17135_TIMING4,
+    REG_MAX17135_TIMING5,
+    REG_MAX17135_TIMING6,
+    REG_MAX17135_TIMING7,
+    REG_MAX17135_TIMING8,
+};
+#define MAX17135_REG_NUM        21
+#define MAX17135_MAX_REGISTER   0xFF
+
+/*
+ * Bitfield macros that use rely on bitfield width/shift information.
+ */
+#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH))
+#define BITFVAL(field, val) ((val) << (field ## _LSH))
+#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH))
+
+/*
+ * Shift and width values for each register bitfield
+ */
+#define EXT_TEMP_LSH    7
+#define EXT_TEMP_WID    9
+
+#define THERMAL_SHUTDOWN_LSH    0
+#define THERMAL_SHUTDOWN_WID    1
+
+#define INT_TEMP_LSH    7
+#define INT_TEMP_WID    9
+
+#define STAT_BUSY_LSH   0
+#define STAT_BUSY_WID   1
+#define STAT_OPEN_LSH   1
+#define STAT_OPEN_WID   1
+#define STAT_SHRT_LSH   2
+#define STAT_SHRT_WID   1
+
+#define PROD_REV_LSH    0
+#define PROD_REV_WID    8
+
+#define PROD_ID_LSH     0
+#define PROD_ID_WID     8
+
+#define DVR_LSH         0
+#define DVR_WID         8
+
+#define ENABLE_LSH      0
+#define ENABLE_WID      1
+#define VCOM_ENABLE_LSH 1
+#define VCOM_ENABLE_WID 1
+
+#define FAULT_FBPG_LSH      0
+#define FAULT_FBPG_WID      1
+#define FAULT_HVINP_LSH     1
+#define FAULT_HVINP_WID     1
+#define FAULT_HVINN_LSH     2
+#define FAULT_HVINN_WID     1
+#define FAULT_FBNG_LSH      3
+#define FAULT_FBNG_WID      1
+#define FAULT_HVINPSC_LSH   4
+#define FAULT_HVINPSC_WID   1
+#define FAULT_HVINNSC_LSH   5
+#define FAULT_HVINNSC_WID   1
+#define FAULT_OT_LSH        6
+#define FAULT_OT_WID        1
+#define FAULT_POK_LSH       7
+#define FAULT_POK_WID       1
+
+#define HVINP_LSH           0
+#define HVINP_WID           4
+
+#define CTRL_DVR_LSH        0
+#define CTRL_DVR_WID        1
+#define CTRL_TIMING_LSH     1
+#define CTRL_TIMING_WID     1
+
+#define TIMING1_LSH         0
+#define TIMING1_WID         8
+#define TIMING2_LSH         0
+#define TIMING2_WID         8
+#define TIMING3_LSH         0
+#define TIMING3_WID         8
+#define TIMING4_LSH         0
+#define TIMING4_WID         8
+#define TIMING5_LSH         0
+#define TIMING5_WID         8
+#define TIMING6_LSH         0
+#define TIMING6_WID         8
+#define TIMING7_LSH         0
+#define TIMING7_WID         8
+#define TIMING8_LSH         0
+#define TIMING8_WID         8
+
+/*
+ * Regulator definitions
+ *   *_MIN_uV  - minimum microvolt for regulator
+ *   *_MAX_uV  - maximum microvolt for regulator
+ *   *_STEP_uV - microvolts between regulator output levels
+ *   *_MIN_VAL - minimum register field value for regulator
+ *   *_MAX_VAL - maximum register field value for regulator
+ */
+#define MAX17135_HVINP_MIN_uV    5000000
+#define MAX17135_HVINP_MAX_uV   20000000
+#define MAX17135_HVINP_STEP_uV   1000000
+#define MAX17135_HVINP_MIN_VAL         0
+#define MAX17135_HVINP_MAX_VAL         1
+
+#define MAX17135_HVINN_MIN_uV    5000000
+#define MAX17135_HVINN_MAX_uV   20000000
+#define MAX17135_HVINN_STEP_uV   1000000
+#define MAX17135_HVINN_MIN_VAL         0
+#define MAX17135_HVINN_MAX_VAL         1
+
+#define MAX17135_GVDD_MIN_uV    5000000
+#define MAX17135_GVDD_MAX_uV   20000000
+#define MAX17135_GVDD_STEP_uV   1000000
+#define MAX17135_GVDD_MIN_VAL         0
+#define MAX17135_GVDD_MAX_VAL         1
+
+#define MAX17135_GVEE_MIN_uV    5000000
+#define MAX17135_GVEE_MAX_uV   20000000
+#define MAX17135_GVEE_STEP_uV   1000000
+#define MAX17135_GVEE_MIN_VAL         0
+#define MAX17135_GVEE_MAX_VAL         1
+
+#if (MAX17135_REV == 1)
+#define MAX17135_VCOM_MIN_uV   -4325000
+#define MAX17135_VCOM_MAX_uV    -500000
+#define MAX17135_VCOM_STEP_uV     15000
+#define MAX17135_VCOM_MIN_VAL         0
+#define MAX17135_VCOM_MAX_VAL       255
+/* Required due to discrepancy between
+ * observed VCOM programming and
+ * what is suggested in the spec.
+ */
+#define MAX17135_VCOM_FUDGE_FACTOR 330000
+#else
+#define MAX17135_VCOM_MIN_uV   -3050000
+#define MAX17135_VCOM_MAX_uV    -500000
+#define MAX17135_VCOM_STEP_uV     10000
+#define MAX17135_VCOM_MIN_VAL         0
+#define MAX17135_VCOM_MAX_VAL       255
+#define MAX17135_VCOM_FUDGE_FACTOR 330000
+#endif
+
+#define MAX17135_VCOM_VOLTAGE_DEFAULT -1250000
+
+#define MAX17135_VNEG_MIN_uV    5000000
+#define MAX17135_VNEG_MAX_uV   20000000
+#define MAX17135_VNEG_STEP_uV   1000000
+#define MAX17135_VNEG_MIN_VAL         0
+#define MAX17135_VNEG_MAX_VAL         1
+
+#define MAX17135_VPOS_MIN_uV    5000000
+#define MAX17135_VPOS_MAX_uV   20000000
+#define MAX17135_VPOS_STEP_uV   1000000
+#define MAX17135_VPOS_MIN_VAL         0
+#define MAX17135_VPOS_MAX_VAL         1
+
+struct max17135 {
+	/* chip revision */
+	int rev;
+
+	struct device *dev;
+
+	/* Platform connection */
+	struct i2c_client *i2c_client;
+
+	/* Client devices */
+	struct platform_device *pdev[MAX17135_REG_NUM];
+
+	/* GPIOs */
+	int gpio_pmic_pwrgood;
+	int gpio_pmic_vcom_ctrl;
+	int gpio_pmic_wakeup;
+	int gpio_pmic_intr;
+
+	bool vcom_setup;
+
+	int max_wait;
+};
+
+/*
+ * Regulator operations
+ */
+static int max17135_hvinp_set_voltage(struct regulator_dev *reg,
+					int minuV, int uV)
+{
+	unsigned int reg_val;
+	unsigned int fld_val;
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+	struct i2c_client *client = max17135->i2c_client;
+
+	if ((uV >= MAX17135_HVINP_MIN_uV) &&
+	    (uV <= MAX17135_HVINP_MAX_uV))
+		fld_val = (uV - MAX17135_HVINP_MIN_uV) /
+			MAX17135_HVINP_STEP_uV;
+	else
+		return -EINVAL;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_HVINP);
+
+	reg_val &= ~BITFMASK(HVINP);
+	reg_val |= BITFVAL(HVINP, fld_val); /* shift to correct bit */
+
+	return i2c_smbus_write_byte_data(client, REG_MAX17135_HVINP, reg_val);
+}
+
+static int max17135_hvinp_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int reg_val;
+	unsigned int fld_val;
+	int volt;
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+	struct i2c_client *client = max17135->i2c_client;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_HVINP);
+
+	fld_val = (reg_val & BITFMASK(HVINP)) >> HVINP_LSH;
+
+	if ((fld_val >= MAX17135_HVINP_MIN_VAL) &&
+		(fld_val <= MAX17135_HVINP_MAX_VAL)) {
+		volt = (fld_val * MAX17135_HVINP_STEP_uV) +
+			MAX17135_HVINP_MIN_uV;
+	} else {
+		printk(KERN_ERR "MAX17135: HVINP voltage is out of range\n");
+		volt = 0;
+	}
+	return volt;
+}
+
+static int max17135_hvinp_enable(struct regulator_dev *reg)
+{
+	return 0;
+}
+
+static int max17135_hvinp_disable(struct regulator_dev *reg)
+{
+	return 0;
+}
+
+/* Convert uV to the VCOM register bitfield setting */
+static inline int vcom_uV_to_rs(int uV)
+{
+	return (MAX17135_VCOM_MAX_uV - uV) / MAX17135_VCOM_STEP_uV;
+}
+
+/* Convert the VCOM register bitfield setting to uV */
+static inline int vcom_rs_to_uV(int rs)
+{
+	return MAX17135_VCOM_MAX_uV - (MAX17135_VCOM_STEP_uV * rs);
+}
+
+static int max17135_vcom_set_voltage(struct regulator_dev *reg,
+					int minuV, int uV)
+{
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+	struct i2c_client *client = max17135->i2c_client;
+	unsigned int reg_val;
+	int vcom_read;
+
+	if ((uV < MAX17135_VCOM_MIN_uV) || (uV > MAX17135_VCOM_MAX_uV))
+		return -EINVAL;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_DVR);
+
+	/*
+	 * Only program VCOM if it is not set to the desired value.
+	 * Programming VCOM excessively degrades ability to keep
+	 * DVR register value persistent.
+	 */
+	vcom_read = vcom_rs_to_uV(reg_val) - MAX17135_VCOM_FUDGE_FACTOR;
+	if (vcom_read != MAX17135_VCOM_VOLTAGE_DEFAULT) {
+		reg_val &= ~BITFMASK(DVR);
+		reg_val |= BITFVAL(DVR,
+			vcom_uV_to_rs(uV + MAX17135_VCOM_FUDGE_FACTOR));
+		i2c_smbus_write_byte_data(client, REG_MAX17135_DVR, reg_val);
+
+		reg_val = BITFVAL(CTRL_DVR, true); /* shift to correct bit */
+		return i2c_smbus_write_byte_data(client,
+			REG_MAX17135_PRGM_CTRL, reg_val);
+	}
+}
+
+static int max17135_vcom_get_voltage(struct regulator_dev *reg)
+{
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+	struct i2c_client *client = max17135->i2c_client;
+	unsigned int reg_val;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_DVR);
+	return vcom_rs_to_uV(BITFEXT(reg_val, DVR));
+}
+
+static int max17135_vcom_enable(struct regulator_dev *reg)
+{
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+
+	/*
+	 * Check to see if we need to set the VCOM voltage.
+	 * Should only be done one time. And, we can
+	 * only change vcom voltage if we have been enabled.
+	 */
+	if (!max17135->vcom_setup
+		&& gpio_get_value(max17135->gpio_pmic_pwrgood)) {
+		max17135_vcom_set_voltage(reg,
+			MAX17135_VCOM_VOLTAGE_DEFAULT,
+			MAX17135_VCOM_VOLTAGE_DEFAULT);
+		max17135->vcom_setup = true;
+	}
+
+	/* enable VCOM regulator output */
+#if (MAX17135_REV == 1)
+	gpio_set_value(max17135->gpio_pmic_vcom_ctrl, 1);
+#else
+	struct i2c_client *client = max17135->i2c_client;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_ENABLE);
+	reg_val &= ~BITFMASK(VCOM_ENABLE);
+	reg_val |= BITFVAL(VCOM_ENABLE, 1); /* shift to correct bit */
+	i2c_smbus_write_byte_data(client, REG_MAX17135_ENABLE, reg_val);
+#endif
+	return 0;
+}
+
+static int max17135_vcom_disable(struct regulator_dev *reg)
+{
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+#if (MAX17135_REV == 1)
+	gpio_set_value(max17135->gpio_pmic_vcom_ctrl, 0);
+#else
+	struct i2c_client *client = max17135->i2c_client;
+	unsigned int reg_val;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_ENABLE);
+	reg_val &= ~BITFMASK(VCOM_ENABLE);
+	i2c_smbus_write_byte_data(client, REG_MAX17135_ENABLE, reg_val);
+#endif
+	return 0;
+}
+
+static int max17135_wait_power_good(struct max17135 *max17135)
+{
+	int i;
+
+	for (i = 0; i < max17135->max_wait * 3; i++) {
+		if (gpio_get_value(max17135->gpio_pmic_pwrgood))
+			return 0;
+
+		msleep(1);
+	}
+	return -ETIMEDOUT;
+}
+
+static int max17135_display_enable(struct regulator_dev *reg)
+{
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+#if (MAX17135_REV == 1)
+	gpio_set_value(max17135->gpio_pmic_wakeup, 1);
+#else
+	struct i2c_client *client = max17135->i2c_client;
+	unsigned int reg_val;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_ENABLE);
+	reg_val &= ~BITFMASK(ENABLE);
+	reg_val |= BITFVAL(ENABLE, 1);
+	i2c_smbus_write_byte_data(client, REG_MAX17135_ENABLE, reg_val);
+#endif
+
+	return max17135_wait_power_good(max17135);
+}
+
+static int max17135_display_disable(struct regulator_dev *reg)
+{
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+#if (MAX17135_REV == 1)
+	gpio_set_value(max17135->gpio_pmic_wakeup, 0);
+#else
+	struct i2c_client *client = max17135->i2c_client;
+	unsigned int reg_val;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_ENABLE);
+	reg_val &= ~BITFMASK(ENABLE);
+	i2c_smbus_write_byte_data(client, REG_MAX17135_ENABLE, reg_val);
+	msleep(PMIC_DISABLE__V3P3_DESERT/1000);
+#endif
+	return 0;
+}
+
+static int max17135_display_is_enabled(struct regulator_dev *reg)
+{
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+	int gpio = gpio_get_value(max17135->gpio_pmic_wakeup);
+
+	if (gpio == 0)
+		return 0;
+	else
+		return 1;
+}
+
+/*
+ * Regulator operations
+ */
+
+static struct regulator_ops max17135_display_ops = {
+	.enable = max17135_display_enable,
+	.disable = max17135_display_disable,
+	.is_enabled = max17135_display_is_enabled,
+};
+
+static struct regulator_ops max17135_gvdd_ops = {
+};
+
+static struct regulator_ops max17135_gvee_ops = {
+};
+
+static struct regulator_ops max17135_hvinn_ops = {
+};
+
+static struct regulator_ops max17135_hvinp_ops = {
+	.enable = max17135_hvinp_enable,
+	.disable = max17135_hvinp_disable,
+	.get_voltage = max17135_hvinp_get_voltage,
+	.set_voltage = max17135_hvinp_set_voltage,
+};
+
+static struct regulator_ops max17135_vcom_ops = {
+	.enable = max17135_vcom_enable,
+	.disable = max17135_vcom_disable,
+	.get_voltage = max17135_vcom_get_voltage,
+	.set_voltage = max17135_vcom_set_voltage,
+};
+
+static struct regulator_ops max17135_vneg_ops = {
+};
+
+static struct regulator_ops max17135_vpos_ops = {
+};
+
+/*
+ * Regulator descriptors
+ */
+static struct regulator_desc max17135_reg[MAX17135_NUM_REGULATORS] = {
+{
+	.name = "DISPLAY",
+	.id = MAX17135_DISPLAY,
+	.ops = &max17135_display_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+{
+	.name = "GVDD",
+	.id = MAX17135_GVDD,
+	.ops = &max17135_gvdd_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+{
+	.name = "GVEE",
+	.id = MAX17135_GVEE,
+	.ops = &max17135_gvee_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+{
+	.name = "HVINN",
+	.id = MAX17135_HVINN,
+	.ops = &max17135_hvinn_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+{
+	.name = "HVINP",
+	.id = MAX17135_HVINP,
+	.ops = &max17135_hvinp_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+{
+	.name = "VCOM",
+	.id = MAX17135_VCOM,
+	.ops = &max17135_vcom_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+{
+	.name = "VNEG",
+	.id = MAX17135_VNEG,
+	.ops = &max17135_vneg_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+{
+	.name = "VPOS",
+	.id = MAX17135_VPOS,
+	.ops = &max17135_vpos_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+};
+
+/*
+ * Regulator init/probing/exit functions
+ */
+static int max17135_regulator_probe(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev;
+
+	rdev = regulator_register(&max17135_reg[pdev->id], &pdev->dev,
+				  pdev->dev.platform_data,
+				  dev_get_drvdata(&pdev->dev));
+
+	if (IS_ERR(rdev)) {
+		dev_err(&pdev->dev, "failed to register %s\n",
+			max17135_reg[pdev->id].name);
+		return PTR_ERR(rdev);
+	}
+
+	return 0;
+}
+
+static int max17135_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+	regulator_unregister(rdev);
+	return 0;
+}
+
+static struct platform_driver max17135_regulator_driver = {
+	.probe = max17135_regulator_probe,
+	.remove = max17135_regulator_remove,
+	.driver = {
+		.name = "max17135-reg",
+	},
+};
+
+static int max17135_register_regulator(struct max17135 *max17135, int reg,
+				     struct regulator_init_data *initdata)
+{
+	struct platform_device *pdev;
+	int ret;
+
+	struct i2c_client *client = max17135->i2c_client;
+	/* If we can't find PMIC via I2C, we should not register regulators */
+	if (i2c_smbus_read_byte_data(client,
+		REG_MAX17135_PRODUCT_REV >= 0)) {
+		dev_err(max17135->dev,
+			"Max17135 PMIC not found!\n");
+		return -ENXIO;
+	}
+
+	if (max17135->pdev[reg])
+		return -EBUSY;
+
+	pdev = platform_device_alloc("max17135-reg", reg);
+	if (!pdev)
+		return -ENOMEM;
+
+	max17135->pdev[reg] = pdev;
+
+	initdata->driver_data = max17135;
+
+	pdev->dev.platform_data = initdata;
+	pdev->dev.parent = max17135->dev;
+	platform_set_drvdata(pdev, max17135);
+
+	ret = platform_device_add(pdev);
+
+	if (ret != 0) {
+		dev_err(max17135->dev,
+		       "Failed to register regulator %d: %d\n",
+			reg, ret);
+		platform_device_del(pdev);
+		max17135->pdev[reg] = NULL;
+	}
+
+	return ret;
+}
+
+static int max17135_i2c_probe(struct i2c_client *client,
+			    const struct i2c_device_id *id)
+{
+	int i;
+	struct max17135 *max17135;
+	struct max17135_platform_data *pdata = client->dev.platform_data;
+	int ret = 0;
+
+	if (!pdata || !pdata->regulator_init)
+		return -ENODEV;
+
+	/* Create the PMIC data structure */
+	max17135 = kzalloc(sizeof(struct max17135), GFP_KERNEL);
+	if (max17135 == NULL) {
+		kfree(client);
+		return -ENOMEM;
+	}
+
+	/* Initialize the PMIC data structure */
+	i2c_set_clientdata(client, max17135);
+	max17135->dev = &client->dev;
+	max17135->i2c_client = client;
+
+	max17135->gpio_pmic_pwrgood = pdata->gpio_pmic_pwrgood;
+	max17135->gpio_pmic_vcom_ctrl = pdata->gpio_pmic_vcom_ctrl;
+	max17135->gpio_pmic_wakeup = pdata->gpio_pmic_wakeup;
+	max17135->gpio_pmic_intr = pdata->gpio_pmic_intr;
+
+	max17135->vcom_setup = false;
+
+	ret = platform_driver_register(&max17135_regulator_driver);
+	if (ret < 0)
+		goto err;
+
+	for (i = 0; i <= MAX17135_VPOS; i++) {
+		ret = max17135_register_regulator(max17135, i, &pdata->regulator_init[i]);
+		if (ret != 0) {
+			dev_err(max17135->dev, "Platform init() failed: %d\n",
+			ret);
+		goto err;
+		}
+	}
+
+	max17135->max_wait = pdata->vpos_pwrup + pdata->vneg_pwrup +
+		pdata->gvdd_pwrup + pdata->gvee_pwrup;
+
+	/* Initialize the PMIC device */
+	dev_info(&client->dev, "PMIC MAX17135 for eInk display\n");
+
+	return ret;
+err:
+	kfree(max17135);
+
+	return ret;
+}
+
+
+static int max17135_i2c_remove(struct i2c_client *i2c)
+{
+	struct max17135 *max17135 = i2c_get_clientdata(i2c);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(max17135->pdev); i++)
+		platform_device_unregister(max17135->pdev[i]);
+
+	platform_driver_unregister(&max17135_regulator_driver);
+
+	kfree(max17135);
+
+	return 0;
+}
+
+static const struct i2c_device_id max17135_i2c_id[] = {
+       { "max17135", 0 },
+       { }
+};
+MODULE_DEVICE_TABLE(i2c, max17135_i2c_id);
+
+
+static struct i2c_driver max17135_i2c_driver = {
+	.driver = {
+		   .name = "max17135",
+		   .owner = THIS_MODULE,
+	},
+	.probe = max17135_i2c_probe,
+	.remove = max17135_i2c_remove,
+	.id_table = max17135_i2c_id,
+};
+
+static int __init max17135_init(void)
+{
+	return i2c_add_driver(&max17135_i2c_driver);
+}
+module_init(max17135_init);
+
+static void __exit max17135_exit(void)
+{
+	i2c_del_driver(&max17135_i2c_driver);
+}
+module_exit(max17135_exit);
+
+/* Module information */
+MODULE_DESCRIPTION("MAX17135 regulator driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-fm3130.c b/drivers/rtc/rtc-fm3130.c
index 3a7be11cc6b9..812c66755083 100644
--- a/drivers/rtc/rtc-fm3130.c
+++ b/drivers/rtc/rtc-fm3130.c
@@ -376,20 +376,22 @@ static int __devinit fm3130_probe(struct i2c_client *client,
 	}
 
 	/* Disabling calibration mode */
-	if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_CAL)
+	if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_CAL) {
 		i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
 			fm3130->regs[FM3130_RTC_CONTROL] &
 				~(FM3130_RTC_CONTROL_BIT_CAL));
 		dev_warn(&client->dev, "Disabling calibration mode!\n");
+	}
 
 	/* Disabling read and write modes */
 	if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_WRITE ||
-	    fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_READ)
+	    fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_READ) {
 		i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
 			fm3130->regs[FM3130_RTC_CONTROL] &
 				~(FM3130_RTC_CONTROL_BIT_READ |
 					FM3130_RTC_CONTROL_BIT_WRITE));
 		dev_warn(&client->dev, "Disabling READ or WRITE mode!\n");
+	}
 
 	/* oscillator off?  turn it on, so clock can tick. */
 	if (fm3130->regs[FM3130_CAL_CONTROL] & FM3130_CAL_CONTROL_BIT_nOSCEN)
diff --git a/drivers/rtc/rtc-mxc_v2.c b/drivers/rtc/rtc-mxc_v2.c
index 5d410fd9d5d2..beb31415a4da 100644
--- a/drivers/rtc/rtc-mxc_v2.c
+++ b/drivers/rtc/rtc-mxc_v2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -37,6 +37,10 @@
 #include <linux/uaccess.h>
 #include <mach/hardware.h>
 #include <asm/io.h>
+#include <linux/mxc_srtc.h>
+
+
+#define SRTC_LPSCLR_LLPSC_LSH	17	 /* start bit for LSB time value */
 
 #define SRTC_LPPDR_INIT       0x41736166	/* init for glitch detect */
 
@@ -147,6 +151,12 @@ struct rtc_drv_data {
 	bool irq_enable;
 };
 
+
+/* completion event for implementing RTC_WAIT_FOR_TIME_SET ioctl */
+DECLARE_COMPLETION(srtc_completion);
+/* global to save difference of 47-bit counter value */
+static int64_t time_diff;
+
 /*!
  * @defgroup RTC Real Time Clock (RTC) Driver
  */
@@ -313,6 +323,8 @@ static int mxc_rtc_ioctl(struct device *dev, unsigned int cmd,
 	void __iomem *ioaddr = pdata->ioaddr;
 	unsigned long lock_flags = 0;
 	u32 lp_cr;
+	u64 time_47bit;
+	int retVal;
 
 	switch (cmd) {
 	case RTC_AIE_OFF:
@@ -339,6 +351,36 @@ static int mxc_rtc_ioctl(struct device *dev, unsigned int cmd,
 		__raw_writel(lp_cr, ioaddr + SRTC_LPCR);
 		spin_unlock_irqrestore(&rtc_lock, lock_flags);
 		return 0;
+
+	case RTC_READ_TIME_47BIT:
+		time_47bit = (((u64) __raw_readl(ioaddr + SRTC_LPSCMR)) << 32 |
+			((u64) __raw_readl(ioaddr + SRTC_LPSCLR)));
+		time_47bit >>= SRTC_LPSCLR_LLPSC_LSH;
+
+		if (arg && copy_to_user((u64 *) arg, &time_47bit, sizeof(u64)))
+			return -EFAULT;
+
+		return 0;
+
+	case RTC_WAIT_TIME_SET:
+
+		/* don't block without releasing mutex first */
+		mutex_unlock(&pdata->rtc->ops_lock);
+
+		/* sleep until awakened by SRTC driver when LPSCMR is changed */
+		wait_for_completion(&srtc_completion);
+
+		/* relock mutex because rtc_dev_ioctl will unlock again */
+		retVal = mutex_lock_interruptible(&pdata->rtc->ops_lock);
+
+		/* copy the new time difference = new time - previous time
+		  * to the user param. The difference is a signed value */
+		if (arg && copy_to_user((int64_t *) arg, &time_diff,
+			sizeof(int64_t)))
+			return -EFAULT;
+
+		return retVal;
+
 	}
 
 	return -ENOIOCTLCMD;
@@ -372,14 +414,31 @@ static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
 	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
 	void __iomem *ioaddr = pdata->ioaddr;
 	unsigned long time;
+	u64 old_time_47bit, new_time_47bit;
 	int ret;
 	ret = rtc_tm_to_time(tm, &time);
 	if (ret != 0)
 		return ret;
 
+	old_time_47bit = (((u64) __raw_readl(ioaddr + SRTC_LPSCMR)) << 32 |
+			((u64) __raw_readl(ioaddr + SRTC_LPSCLR)));
+	old_time_47bit >>= SRTC_LPSCLR_LLPSC_LSH;
+
 	__raw_writel(time, ioaddr + SRTC_LPSCMR);
 	rtc_write_sync_lp(ioaddr);
 
+	new_time_47bit = (((u64) __raw_readl(ioaddr + SRTC_LPSCMR)) << 32 |
+			((u64) __raw_readl(ioaddr + SRTC_LPSCLR)));
+	new_time_47bit >>= SRTC_LPSCLR_LLPSC_LSH;
+
+	/* update the difference between previous time and new time */
+	time_diff = new_time_47bit - old_time_47bit;
+
+	/* signal all waiting threads that time changed */
+	complete_all(&srtc_completion);
+	/* reinitialize completion variable */
+	INIT_COMPLETION(srtc_completion);
+
 	return 0;
 }
 
@@ -549,41 +608,30 @@ static int mxc_rtc_probe(struct platform_device *pdev)
 
 	/* clear lp interrupt status */
 	__raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
-	udelay(100);;
+	udelay(100);
 
 	plat_data = (struct mxc_srtc_platform_data *)pdev->dev.platform_data;
-	clk = clk_get(NULL, "iim_clk");
-	clk_enable(clk);
-	srtc_secmode_addr = ioremap(plat_data->srtc_sec_mode_addr, 1);
-
-	/* Check SRTC security mode */
-	if (((__raw_readl(srtc_secmode_addr) & SRTC_SECMODE_MASK) ==
-	    SRTC_SECMODE_LOW) && (cpu_is_mx51_rev(CHIP_REV_1_0) == 1)) {
-		/* Workaround for MX51 TO1 due to inaccurate CKIL clock */
-		__raw_writel(SRTC_LPCR_EN_LP, ioaddr + SRTC_LPCR);
-		udelay(100);
-	} else {
-		/* move out of init state */
-		__raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NSA),
-			     ioaddr + SRTC_LPCR);
 
-		udelay(100);
+	/* move out of init state */
+	__raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NSA),
+		     ioaddr + SRTC_LPCR);
 
-		while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_IES) == 0);
+	udelay(100);
 
-		/* move out of non-valid state */
-		__raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
-			      SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
+	while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_IES) == 0)
+		;
 
-		udelay(100);
+	/* move out of non-valid state */
+	__raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
+		      SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
 
-		while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_NVES) == 0);
+	udelay(100);
 
-		__raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
-		udelay(100);
-	}
-	clk_disable(clk);
-	clk_put(clk);
+	while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_NVES) == 0)
+		;
+
+	__raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
+	udelay(100);
 
 	rtc = rtc_device_register(pdev->name, &pdev->dev,
 				  &mxc_rtc_ops, THIS_MODULE);
diff --git a/drivers/rtc/rtc-v3020.c b/drivers/rtc/rtc-v3020.c
index ad164056feb6..423cd5a30b10 100644
--- a/drivers/rtc/rtc-v3020.c
+++ b/drivers/rtc/rtc-v3020.c
@@ -96,7 +96,7 @@ static void v3020_mmio_write_bit(struct v3020 *chip, unsigned char bit)
 
 static unsigned char v3020_mmio_read_bit(struct v3020 *chip)
 {
-	return readl(chip->ioaddress) & (1 << chip->leftshift);
+	return !!(readl(chip->ioaddress) & (1 << chip->leftshift));
 }
 
 static struct v3020_chip_ops v3020_mmio_ops = {
diff --git a/drivers/s390/block/dasd_diag.c b/drivers/s390/block/dasd_diag.c
index 644086ba2ede..b76dee9f2861 100644
--- a/drivers/s390/block/dasd_diag.c
+++ b/drivers/s390/block/dasd_diag.c
@@ -145,6 +145,15 @@ dasd_diag_erp(struct dasd_device *device)
 
 	mdsk_term_io(device);
 	rc = mdsk_init_io(device, device->block->bp_block, 0, NULL);
+	if (rc == 4) {
+		if (!(device->features & DASD_FEATURE_READONLY)) {
+			dev_warn(&device->cdev->dev,
+				 "The access mode of a DIAG device changed"
+				 " to read-only");
+			device->features |= DASD_FEATURE_READONLY;
+		}
+		rc = 0;
+	}
 	if (rc)
 		dev_warn(&device->cdev->dev, "DIAG ERP failed with "
 			    "rc=%d\n", rc);
@@ -433,16 +442,20 @@ dasd_diag_check_device(struct dasd_device *device)
 	for (sb = 512; sb < bsize; sb = sb << 1)
 		block->s2b_shift++;
 	rc = mdsk_init_io(device, block->bp_block, 0, NULL);
-	if (rc) {
+	if (rc && (rc != 4)) {
 		dev_warn(&device->cdev->dev, "DIAG initialization "
 			"failed with rc=%d\n", rc);
 		rc = -EIO;
 	} else {
+		if (rc == 4)
+			device->features |= DASD_FEATURE_READONLY;
 		dev_info(&device->cdev->dev,
-			 "New DASD with %ld byte/block, total size %ld KB\n",
+			 "New DASD with %ld byte/block, total size %ld KB%s\n",
 			 (unsigned long) block->bp_block,
 			 (unsigned long) (block->blocks <<
-					  block->s2b_shift) >> 1);
+					  block->s2b_shift) >> 1,
+			 (rc == 4) ? ", read-only device" : "");
+		rc = 0;
 	}
 out_label:
 	free_page((long) label);
diff --git a/drivers/scsi/dpt_i2o.c b/drivers/scsi/dpt_i2o.c
index b6af63ca980b..496764349c41 100644
--- a/drivers/scsi/dpt_i2o.c
+++ b/drivers/scsi/dpt_i2o.c
@@ -1918,6 +1918,10 @@ static int adpt_i2o_passthru(adpt_hba* pHba, u32 __user *arg)
 		}
 		size = size>>16;
 		size *= 4;
+		if (size > MAX_MESSAGE_SIZE) {
+			rcode = -EINVAL;
+			goto cleanup;
+		}
 		/* Copy in the user's I2O command */
 		if (copy_from_user (msg, user_msg, size)) {
 			rcode = -EFAULT;
diff --git a/drivers/scsi/gdth.c b/drivers/scsi/gdth.c
index 185e6bc4dd40..9e8fce0f0c1b 100644
--- a/drivers/scsi/gdth.c
+++ b/drivers/scsi/gdth.c
@@ -2900,7 +2900,7 @@ static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
         eindex = handle;
     estr->event_source = 0;
 
-    if (eindex >= MAX_EVENTS) {
+    if (eindex < 0 || eindex >= MAX_EVENTS) {
         spin_unlock_irqrestore(&ha->smp_lock, flags);
         return eindex;
     }
diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c
index 5fd2da494d08..28a753d796f3 100644
--- a/drivers/scsi/hosts.c
+++ b/drivers/scsi/hosts.c
@@ -180,14 +180,20 @@ void scsi_remove_host(struct Scsi_Host *shost)
 EXPORT_SYMBOL(scsi_remove_host);
 
 /**
- * scsi_add_host - add a scsi host
+ * scsi_add_host_with_dma - add a scsi host with dma device
  * @shost:	scsi host pointer to add
  * @dev:	a struct device of type scsi class
+ * @dma_dev:	dma device for the host
+ *
+ * Note: You rarely need to worry about this unless you're in a
+ * virtualised host environments, so use the simpler scsi_add_host()
+ * function instead.
  *
  * Return value: 
  * 	0 on success / != 0 for error
  **/
-int scsi_add_host(struct Scsi_Host *shost, struct device *dev)
+int scsi_add_host_with_dma(struct Scsi_Host *shost, struct device *dev,
+			   struct device *dma_dev)
 {
 	struct scsi_host_template *sht = shost->hostt;
 	int error = -EINVAL;
@@ -207,6 +213,7 @@ int scsi_add_host(struct Scsi_Host *shost, struct device *dev)
 
 	if (!shost->shost_gendev.parent)
 		shost->shost_gendev.parent = dev ? dev : &platform_bus;
+	shost->dma_dev = dma_dev;
 
 	error = device_add(&shost->shost_gendev);
 	if (error)
@@ -262,7 +269,7 @@ int scsi_add_host(struct Scsi_Host *shost, struct device *dev)
  fail:
 	return error;
 }
-EXPORT_SYMBOL(scsi_add_host);
+EXPORT_SYMBOL(scsi_add_host_with_dma);
 
 static void scsi_host_dev_release(struct device *dev)
 {
diff --git a/drivers/scsi/libsrp.c b/drivers/scsi/libsrp.c
index 2742ae8a3d09..9ad38e81e343 100644
--- a/drivers/scsi/libsrp.c
+++ b/drivers/scsi/libsrp.c
@@ -124,6 +124,7 @@ static void srp_ring_free(struct device *dev, struct srp_buf **ring, size_t max,
 		dma_free_coherent(dev, size, ring[i]->buf, ring[i]->dma);
 		kfree(ring[i]);
 	}
+	kfree(ring);
 }
 
 int srp_target_alloc(struct srp_target *target, struct device *dev,
diff --git a/drivers/scsi/lpfc/lpfc_init.c b/drivers/scsi/lpfc/lpfc_init.c
index fc67cc65c63b..cf13ff2e9f01 100644
--- a/drivers/scsi/lpfc/lpfc_init.c
+++ b/drivers/scsi/lpfc/lpfc_init.c
@@ -2384,7 +2384,7 @@ lpfc_create_port(struct lpfc_hba *phba, int instance, struct device *dev)
 	vport->els_tmofunc.function = lpfc_els_timeout;
 	vport->els_tmofunc.data = (unsigned long)vport;
 
-	error = scsi_add_host(shost, dev);
+	error = scsi_add_host_with_dma(shost, dev, &phba->pcidev->dev);
 	if (error)
 		goto out_put_shost;
 
diff --git a/drivers/scsi/megaraid/megaraid_sas.c b/drivers/scsi/megaraid/megaraid_sas.c
index 7dc3d1894b1a..4352e30cd1f6 100644
--- a/drivers/scsi/megaraid/megaraid_sas.c
+++ b/drivers/scsi/megaraid/megaraid_sas.c
@@ -3032,7 +3032,7 @@ megasas_mgmt_fw_ioctl(struct megasas_instance *instance,
 	int error = 0, i;
 	void *sense = NULL;
 	dma_addr_t sense_handle;
-	u32 *sense_ptr;
+	unsigned long *sense_ptr;
 
 	memset(kbuff_arr, 0, sizeof(kbuff_arr));
 
@@ -3109,7 +3109,7 @@ megasas_mgmt_fw_ioctl(struct megasas_instance *instance,
 		}
 
 		sense_ptr =
-		    (u32 *) ((unsigned long)cmd->frame + ioc->sense_off);
+		(unsigned long *) ((unsigned long)cmd->frame + ioc->sense_off);
 		*sense_ptr = sense_handle;
 	}
 
@@ -3140,8 +3140,8 @@ megasas_mgmt_fw_ioctl(struct megasas_instance *instance,
 		 * sense_ptr points to the location that has the user
 		 * sense buffer address
 		 */
-		sense_ptr = (u32 *) ((unsigned long)ioc->frame.raw +
-				     ioc->sense_off);
+		sense_ptr = (unsigned long *) ((unsigned long)ioc->frame.raw +
+				ioc->sense_off);
 
 		if (copy_to_user((void __user *)((unsigned long)(*sense_ptr)),
 				 sense, ioc->sense_len)) {
@@ -3451,7 +3451,7 @@ out:
 	return retval;
 }
 
-static DRIVER_ATTR(poll_mode_io, S_IRUGO|S_IWUGO,
+static DRIVER_ATTR(poll_mode_io, S_IRUGO|S_IWUSR,
 		megasas_sysfs_show_poll_mode_io,
 		megasas_sysfs_set_poll_mode_io);
 
diff --git a/drivers/scsi/mpt2sas/mpt2sas_base.c b/drivers/scsi/mpt2sas/mpt2sas_base.c
index 35a13867495e..2e4bc3d2b435 100644
--- a/drivers/scsi/mpt2sas/mpt2sas_base.c
+++ b/drivers/scsi/mpt2sas/mpt2sas_base.c
@@ -94,7 +94,7 @@ _base_fault_reset_work(struct work_struct *work)
 	int rc;
 
 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
-	if (ioc->ioc_reset_in_progress)
+	if (ioc->shost_recovery)
 		goto rearm_timer;
 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 
@@ -1542,6 +1542,8 @@ _base_display_ioc_capabilities(struct MPT2SAS_ADAPTER *ioc)
 	   (ioc->bios_pg3.BiosVersion & 0x0000FF00) >> 8,
 	    ioc->bios_pg3.BiosVersion & 0x000000FF);
 
+	_base_display_dell_branding(ioc);
+
 	printk(MPT2SAS_INFO_FMT "Protocol=(", ioc->name);
 
 	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
@@ -1554,8 +1556,6 @@ _base_display_ioc_capabilities(struct MPT2SAS_ADAPTER *ioc)
 		i++;
 	}
 
-	_base_display_dell_branding(ioc);
-
 	i = 0;
 	printk("), ");
 	printk("Capabilities=(");
@@ -1627,6 +1627,9 @@ _base_static_config_pages(struct MPT2SAS_ADAPTER *ioc)
 	u32 iounit_pg1_flags;
 
 	mpt2sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
+	if (ioc->ir_firmware)
+		mpt2sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
+		    &ioc->manu_pg10);
 	mpt2sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
 	mpt2sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
 	mpt2sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
@@ -3501,20 +3504,13 @@ mpt2sas_base_hard_reset_handler(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
 	    __func__));
 
 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
-	if (ioc->ioc_reset_in_progress) {
+	if (ioc->shost_recovery) {
 		spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 		printk(MPT2SAS_ERR_FMT "%s: busy\n",
 		    ioc->name, __func__);
 		return -EBUSY;
 	}
-	ioc->ioc_reset_in_progress = 1;
 	ioc->shost_recovery = 1;
-	if (ioc->shost->shost_state == SHOST_RUNNING) {
-		/* set back to SHOST_RUNNING in mpt2sas_scsih.c */
-		scsi_host_set_state(ioc->shost, SHOST_RECOVERY);
-		printk(MPT2SAS_INFO_FMT "putting controller into "
-		    "SHOST_RECOVERY\n", ioc->name);
-	}
 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 
 	_base_reset_handler(ioc, MPT2_IOC_PRE_RESET);
@@ -3534,7 +3530,10 @@ mpt2sas_base_hard_reset_handler(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
 	    ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
 
 	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
-	ioc->ioc_reset_in_progress = 0;
+	ioc->shost_recovery = 0;
 	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
+
+	if (!r)
+		_base_reset_handler(ioc, MPT2_IOC_RUNNING);
 	return r;
 }
diff --git a/drivers/scsi/mpt2sas/mpt2sas_base.h b/drivers/scsi/mpt2sas/mpt2sas_base.h
index acdcff150a35..22f84d3a3f2e 100644
--- a/drivers/scsi/mpt2sas/mpt2sas_base.h
+++ b/drivers/scsi/mpt2sas/mpt2sas_base.h
@@ -119,6 +119,7 @@
 #define MPT2_IOC_PRE_RESET		1 /* prior to host reset */
 #define MPT2_IOC_AFTER_RESET		2 /* just after host reset */
 #define MPT2_IOC_DONE_RESET		3 /* links re-initialized */
+#define MPT2_IOC_RUNNING		4 /* shost running */
 
 /*
  * logging format
@@ -196,6 +197,38 @@ struct MPT2SAS_TARGET {
  * @block: device is in SDEV_BLOCK state
  * @tlr_snoop_check: flag used in determining whether to disable TLR
  */
+
+/* OEM Identifiers */
+#define MFG10_OEM_ID_INVALID                   (0x00000000)
+#define MFG10_OEM_ID_DELL                      (0x00000001)
+#define MFG10_OEM_ID_FSC                       (0x00000002)
+#define MFG10_OEM_ID_SUN                       (0x00000003)
+#define MFG10_OEM_ID_IBM                       (0x00000004)
+
+/* GENERIC Flags 0*/
+#define MFG10_GF0_OCE_DISABLED                 (0x00000001)
+#define MFG10_GF0_R1E_DRIVE_COUNT              (0x00000002)
+#define MFG10_GF0_R10_DISPLAY                  (0x00000004)
+#define MFG10_GF0_SSD_DATA_SCRUB_DISABLE       (0x00000008)
+#define MFG10_GF0_SINGLE_DRIVE_R0              (0x00000010)
+
+/* OEM Specific Flags will come from OEM specific header files */
+typedef struct _MPI2_CONFIG_PAGE_MAN_10 {
+    MPI2_CONFIG_PAGE_HEADER Header;                                 /* 00h */
+    U8                      OEMIdentifier;                          /* 04h */
+    U8                      Reserved1;                              /* 05h */
+    U16                     Reserved2;                              /* 08h */
+    U32                     Reserved3;                              /* 0Ch */
+    U32                     GenericFlags0;                          /* 10h */
+    U32                     GenericFlags1;                          /* 14h */
+    U32                     Reserved4;                              /* 18h */
+    U32                     OEMSpecificFlags0;                      /* 1Ch */
+    U32                     OEMSpecificFlags1;                      /* 20h */
+    U32                     Reserved5[18];                          /* 24h-60h*/
+} MPI2_CONFIG_PAGE_MAN_10,
+  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_10,
+  Mpi2ManufacturingPage10_t, MPI2_POINTER pMpi2ManufacturingPage10_t;
+
 struct MPT2SAS_DEVICE {
 	struct MPT2SAS_TARGET *sas_target;
 	unsigned int	lun;
@@ -431,7 +464,7 @@ typedef void (*MPT_ADD_SGE)(void *paddr, u32 flags_length, dma_addr_t dma_addr);
  * @fw_event_list: list of fw events
  * @aen_event_read_flag: event log was read
  * @broadcast_aen_busy: broadcast aen waiting to be serviced
- * @ioc_reset_in_progress: host reset in progress
+ * @shost_recovery: host reset in progress
  * @ioc_reset_in_progress_lock:
  * @ioc_link_reset_in_progress: phy/hard reset in progress
  * @ignore_loginfos: ignore loginfos during task managment
@@ -460,6 +493,7 @@ typedef void (*MPT_ADD_SGE)(void *paddr, u32 flags_length, dma_addr_t dma_addr);
  * @facts: static facts data
  * @pfacts: static port facts data
  * @manu_pg0: static manufacturing page 0
+ * @manu_pg10: static manufacturing page 10
  * @bios_pg2: static bios page 2
  * @bios_pg3: static bios page 3
  * @ioc_pg8: static ioc page 8
@@ -544,7 +578,6 @@ struct MPT2SAS_ADAPTER {
 	 /* misc flags */
 	int		aen_event_read_flag;
 	u8		broadcast_aen_busy;
-	u8		ioc_reset_in_progress;
 	u8		shost_recovery;
 	spinlock_t 	ioc_reset_in_progress_lock;
 	u8		ioc_link_reset_in_progress;
@@ -663,6 +696,7 @@ struct MPT2SAS_ADAPTER {
 	dma_addr_t	diag_buffer_dma[MPI2_DIAG_BUF_TYPE_COUNT];
 	u8		diag_buffer_status[MPI2_DIAG_BUF_TYPE_COUNT];
 	u32		unique_id[MPI2_DIAG_BUF_TYPE_COUNT];
+	Mpi2ManufacturingPage10_t manu_pg10;
 	u32		product_specific[MPI2_DIAG_BUF_TYPE_COUNT][23];
 	u32		diagnostic_flags[MPI2_DIAG_BUF_TYPE_COUNT];
 };
@@ -734,6 +768,8 @@ void mpt2sas_config_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 VF_ID, u32 re
 int mpt2sas_config_get_number_hba_phys(struct MPT2SAS_ADAPTER *ioc, u8 *num_phys);
 int mpt2sas_config_get_manufacturing_pg0(struct MPT2SAS_ADAPTER *ioc,
     Mpi2ConfigReply_t *mpi_reply, Mpi2ManufacturingPage0_t *config_page);
+int mpt2sas_config_get_manufacturing_pg10(struct MPT2SAS_ADAPTER *ioc,
+    Mpi2ConfigReply_t *mpi_reply, Mpi2ManufacturingPage10_t *config_page);
 int mpt2sas_config_get_bios_pg2(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t
     *mpi_reply, Mpi2BiosPage2_t *config_page);
 int mpt2sas_config_get_bios_pg3(struct MPT2SAS_ADAPTER *ioc, Mpi2ConfigReply_t
@@ -776,7 +812,6 @@ int mpt2sas_config_get_volume_handle(struct MPT2SAS_ADAPTER *ioc, u16 pd_handle,
     u16 *volume_handle);
 int mpt2sas_config_get_volume_wwid(struct MPT2SAS_ADAPTER *ioc, u16 volume_handle,
     u64 *wwid);
-
 /* ctl shared API */
 extern struct device_attribute *mpt2sas_host_attrs[];
 extern struct device_attribute *mpt2sas_dev_attrs[];
@@ -802,5 +837,7 @@ void mpt2sas_transport_update_phy_link_change(struct MPT2SAS_ADAPTER *ioc, u16 h
    u16 attached_handle, u8 phy_number, u8 link_rate);
 extern struct sas_function_template mpt2sas_transport_functions;
 extern struct scsi_transport_template *mpt2sas_transport_template;
+extern int scsi_internal_device_block(struct scsi_device *sdev);
+extern int scsi_internal_device_unblock(struct scsi_device *sdev);
 
 #endif /* MPT2SAS_BASE_H_INCLUDED */
diff --git a/drivers/scsi/mpt2sas/mpt2sas_config.c b/drivers/scsi/mpt2sas/mpt2sas_config.c
index 6ddee161beb3..b9f4d0f97e50 100644
--- a/drivers/scsi/mpt2sas/mpt2sas_config.c
+++ b/drivers/scsi/mpt2sas/mpt2sas_config.c
@@ -426,6 +426,67 @@ mpt2sas_config_get_manufacturing_pg0(struct MPT2SAS_ADAPTER *ioc,
 }
 
 /**
+ * mpt2sas_config_get_manufacturing_pg10 - obtain manufacturing page 10
+ * @ioc: per adapter object
+ * @mpi_reply: reply mf payload returned from firmware
+ * @config_page: contents of the config page
+ * Context: sleep.
+ *
+ * Returns 0 for success, non-zero for failure.
+ */
+int
+mpt2sas_config_get_manufacturing_pg10(struct MPT2SAS_ADAPTER *ioc,
+    Mpi2ConfigReply_t *mpi_reply, Mpi2ManufacturingPage10_t *config_page)
+{
+	Mpi2ConfigRequest_t mpi_request;
+	int r;
+	struct config_request mem;
+
+	memset(config_page, 0, sizeof(Mpi2ManufacturingPage10_t));
+	memset(&mpi_request, 0, sizeof(Mpi2ConfigRequest_t));
+	mpi_request.Function = MPI2_FUNCTION_CONFIG;
+	mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_HEADER;
+	mpi_request.Header.PageType = MPI2_CONFIG_PAGETYPE_MANUFACTURING;
+	mpi_request.Header.PageNumber = 10;
+	mpi_request.Header.PageVersion = MPI2_MANUFACTURING0_PAGEVERSION;
+	mpt2sas_base_build_zero_len_sge(ioc, &mpi_request.PageBufferSGE);
+	r = _config_request(ioc, &mpi_request, mpi_reply,
+	    MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT);
+	if (r)
+		goto out;
+
+	mpi_request.Action = MPI2_CONFIG_ACTION_PAGE_READ_CURRENT;
+	mpi_request.Header.PageVersion = mpi_reply->Header.PageVersion;
+	mpi_request.Header.PageNumber = mpi_reply->Header.PageNumber;
+	mpi_request.Header.PageType = mpi_reply->Header.PageType;
+	mpi_request.Header.PageLength = mpi_reply->Header.PageLength;
+	mem.config_page_sz = le16_to_cpu(mpi_reply->Header.PageLength) * 4;
+	if (mem.config_page_sz > ioc->config_page_sz) {
+		r = _config_alloc_config_dma_memory(ioc, &mem);
+		if (r)
+			goto out;
+	} else {
+		mem.config_page_dma = ioc->config_page_dma;
+		mem.config_page = ioc->config_page;
+	}
+	ioc->base_add_sg_single(&mpi_request.PageBufferSGE,
+	    MPT2_CONFIG_COMMON_SGLFLAGS | mem.config_page_sz,
+	    mem.config_page_dma);
+	r = _config_request(ioc, &mpi_request, mpi_reply,
+	    MPT2_CONFIG_PAGE_DEFAULT_TIMEOUT);
+	if (!r)
+		memcpy(config_page, mem.config_page,
+		    min_t(u16, mem.config_page_sz,
+		    sizeof(Mpi2ManufacturingPage10_t)));
+
+	if (mem.config_page_sz > ioc->config_page_sz)
+		_config_free_config_dma_memory(ioc, &mem);
+
+ out:
+	return r;
+}
+
+/**
  * mpt2sas_config_get_bios_pg2 - obtain bios page 2
  * @ioc: per adapter object
  * @mpi_reply: reply mf payload returned from firmware
diff --git a/drivers/scsi/mpt2sas/mpt2sas_ctl.c b/drivers/scsi/mpt2sas/mpt2sas_ctl.c
index 14e473d1fa7b..c2a51018910f 100644
--- a/drivers/scsi/mpt2sas/mpt2sas_ctl.c
+++ b/drivers/scsi/mpt2sas/mpt2sas_ctl.c
@@ -1963,7 +1963,6 @@ _ctl_ioctl_main(struct file *file, unsigned int cmd, void __user *arg)
 {
 	enum block_state state;
 	long ret = -EINVAL;
-	unsigned long flags;
 
 	state = (file->f_flags & O_NONBLOCK) ? NON_BLOCKING :
 	    BLOCKING;
@@ -1989,13 +1988,8 @@ _ctl_ioctl_main(struct file *file, unsigned int cmd, void __user *arg)
 		    !ioc)
 			return -ENODEV;
 
-		spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
-		if (ioc->shost_recovery) {
-			spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock,
-			    flags);
+		if (ioc->shost_recovery)
 			return -EAGAIN;
-		}
-		spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 
 		if (_IOC_SIZE(cmd) == sizeof(struct mpt2_ioctl_command)) {
 			uarg = arg;
@@ -2098,7 +2092,6 @@ _ctl_compat_mpt_command(struct file *file, unsigned cmd, unsigned long arg)
 	struct mpt2_ioctl_command karg;
 	struct MPT2SAS_ADAPTER *ioc;
 	enum block_state state;
-	unsigned long flags;
 
 	if (_IOC_SIZE(cmd) != sizeof(struct mpt2_ioctl_command32))
 		return -EINVAL;
@@ -2113,13 +2106,8 @@ _ctl_compat_mpt_command(struct file *file, unsigned cmd, unsigned long arg)
 	if (_ctl_verify_adapter(karg32.hdr.ioc_number, &ioc) == -1 || !ioc)
 		return -ENODEV;
 
-	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
-	if (ioc->shost_recovery) {
-		spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock,
-		    flags);
+	if (ioc->shost_recovery)
 		return -EAGAIN;
-	}
-	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 
 	memset(&karg, 0, sizeof(struct mpt2_ioctl_command));
 	karg.hdr.ioc_number = karg32.hdr.ioc_number;
diff --git a/drivers/scsi/mpt2sas/mpt2sas_scsih.c b/drivers/scsi/mpt2sas/mpt2sas_scsih.c
index 2e9a4445596f..bb65cce0491d 100644
--- a/drivers/scsi/mpt2sas/mpt2sas_scsih.c
+++ b/drivers/scsi/mpt2sas/mpt2sas_scsih.c
@@ -103,7 +103,6 @@ struct sense_info {
 };
 
 
-#define MPT2SAS_RESCAN_AFTER_HOST_RESET (0xFFFF)
 /**
  * struct fw_event_work - firmware event struct
  * @list: link list framework
@@ -1502,7 +1501,13 @@ _scsih_slave_configure(struct scsi_device *sdev)
 			break;
 		case MPI2_RAID_VOL_TYPE_RAID1E:
 			qdepth = MPT2SAS_RAID_QUEUE_DEPTH;
-			r_level = "RAID1E";
+			if (ioc->manu_pg10.OEMIdentifier &&
+			    (ioc->manu_pg10.GenericFlags0 &
+			    MFG10_GF0_R10_DISPLAY) &&
+			    !(raid_device->num_pds % 2))
+				r_level = "RAID10";
+			else
+				r_level = "RAID1E";
 			break;
 		case MPI2_RAID_VOL_TYPE_RAID1:
 			qdepth = MPT2SAS_RAID_QUEUE_DEPTH;
@@ -1786,17 +1791,18 @@ mpt2sas_scsih_issue_tm(struct MPT2SAS_ADAPTER *ioc, u16 handle, uint lun,
 	u32 ioc_state;
 	unsigned long timeleft;
 	u8 VF_ID = 0;
-	unsigned long flags;
 
-	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
-	if (ioc->tm_cmds.status != MPT2_CMD_NOT_USED ||
-	    ioc->shost_recovery) {
-		spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
+	if (ioc->tm_cmds.status != MPT2_CMD_NOT_USED) {
+		printk(MPT2SAS_INFO_FMT "%s: tm_cmd busy!!!\n",
+		    __func__, ioc->name);
+		return;
+	}
+
+	if (ioc->shost_recovery) {
 		printk(MPT2SAS_INFO_FMT "%s: host reset in progress!\n",
 		    __func__, ioc->name);
 		return;
 	}
-	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 
 	ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
 	if (ioc_state & MPI2_DOORBELL_USED) {
@@ -2222,7 +2228,7 @@ _scsih_ublock_io_device(struct MPT2SAS_ADAPTER *ioc, u16 handle)
 			    MPT2SAS_INFO_FMT "SDEV_RUNNING: "
 			    "handle(0x%04x)\n", ioc->name, handle));
 			sas_device_priv_data->block = 0;
-			scsi_device_set_state(sdev, SDEV_RUNNING);
+			scsi_internal_device_unblock(sdev);
 		}
 	}
 }
@@ -2251,7 +2257,7 @@ _scsih_block_io_device(struct MPT2SAS_ADAPTER *ioc, u16 handle)
 			    MPT2SAS_INFO_FMT "SDEV_BLOCK: "
 			    "handle(0x%04x)\n", ioc->name, handle));
 			sas_device_priv_data->block = 1;
-			scsi_device_set_state(sdev, SDEV_BLOCK);
+			scsi_internal_device_block(sdev);
 		}
 	}
 }
@@ -2327,6 +2333,7 @@ _scsih_block_io_to_children_attached_directly(struct MPT2SAS_ADAPTER *ioc,
 	u16 handle;
 	u16 reason_code;
 	u8 phy_number;
+	u8 link_rate;
 
 	for (i = 0; i < event_data->NumEntries; i++) {
 		handle = le16_to_cpu(event_data->PHY[i].AttachedDevHandle);
@@ -2337,6 +2344,11 @@ _scsih_block_io_to_children_attached_directly(struct MPT2SAS_ADAPTER *ioc,
 		    MPI2_EVENT_SAS_TOPO_RC_MASK;
 		if (reason_code == MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING)
 			_scsih_block_io_device(ioc, handle);
+		if (reason_code == MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED) {
+			link_rate = event_data->PHY[i].LinkRate >> 4;
+			if (link_rate >= MPI2_SAS_NEG_LINK_RATE_1_5)
+				_scsih_ublock_io_device(ioc, handle);
+		}
 	}
 }
 
@@ -2405,27 +2417,6 @@ _scsih_check_topo_delete_events(struct MPT2SAS_ADAPTER *ioc,
 }
 
 /**
- * _scsih_queue_rescan - queue a topology rescan from user context
- * @ioc: per adapter object
- *
- * Return nothing.
- */
-static void
-_scsih_queue_rescan(struct MPT2SAS_ADAPTER *ioc)
-{
-	struct fw_event_work *fw_event;
-
-	if (ioc->wait_for_port_enable_to_complete)
-		return;
-	fw_event = kzalloc(sizeof(struct fw_event_work), GFP_ATOMIC);
-	if (!fw_event)
-		return;
-	fw_event->event = MPT2SAS_RESCAN_AFTER_HOST_RESET;
-	fw_event->ioc = ioc;
-	_scsih_fw_event_add(ioc, fw_event);
-}
-
-/**
  * _scsih_flush_running_cmds - completing outstanding commands.
  * @ioc: per adapter object
  *
@@ -2456,46 +2447,6 @@ _scsih_flush_running_cmds(struct MPT2SAS_ADAPTER *ioc)
 }
 
 /**
- * mpt2sas_scsih_reset_handler - reset callback handler (for scsih)
- * @ioc: per adapter object
- * @reset_phase: phase
- *
- * The handler for doing any required cleanup or initialization.
- *
- * The reset phase can be MPT2_IOC_PRE_RESET, MPT2_IOC_AFTER_RESET,
- * MPT2_IOC_DONE_RESET
- *
- * Return nothing.
- */
-void
-mpt2sas_scsih_reset_handler(struct MPT2SAS_ADAPTER *ioc, int reset_phase)
-{
-	switch (reset_phase) {
-	case MPT2_IOC_PRE_RESET:
-		dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
-		    "MPT2_IOC_PRE_RESET\n", ioc->name, __func__));
-		_scsih_fw_event_off(ioc);
-		break;
-	case MPT2_IOC_AFTER_RESET:
-		dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
-		    "MPT2_IOC_AFTER_RESET\n", ioc->name, __func__));
-		if (ioc->tm_cmds.status & MPT2_CMD_PENDING) {
-			ioc->tm_cmds.status |= MPT2_CMD_RESET;
-			mpt2sas_base_free_smid(ioc, ioc->tm_cmds.smid);
-			complete(&ioc->tm_cmds.done);
-		}
-		_scsih_fw_event_on(ioc);
-		_scsih_flush_running_cmds(ioc);
-		break;
-	case MPT2_IOC_DONE_RESET:
-		dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
-		    "MPT2_IOC_DONE_RESET\n", ioc->name, __func__));
-		_scsih_queue_rescan(ioc);
-		break;
-	}
-}
-
-/**
  * _scsih_setup_eedp - setup MPI request for EEDP transfer
  * @scmd: pointer to scsi command object
  * @mpi_request: pointer to the SCSI_IO reqest message frame
@@ -2615,7 +2566,6 @@ _scsih_qcmd(struct scsi_cmnd *scmd, void (*done)(struct scsi_cmnd *))
 	Mpi2SCSIIORequest_t *mpi_request;
 	u32 mpi_control;
 	u16 smid;
-	unsigned long flags;
 
 	scmd->scsi_done = done;
 	sas_device_priv_data = scmd->device->hostdata;
@@ -2634,13 +2584,10 @@ _scsih_qcmd(struct scsi_cmnd *scmd, void (*done)(struct scsi_cmnd *))
 	}
 
 	/* see if we are busy with task managment stuff */
-	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
-	if (sas_target_priv_data->tm_busy ||
-	    ioc->shost_recovery || ioc->ioc_link_reset_in_progress) {
-		spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
+	if (sas_target_priv_data->tm_busy)
+		return SCSI_MLQUEUE_DEVICE_BUSY;
+	else if (ioc->shost_recovery || ioc->ioc_link_reset_in_progress)
 		return SCSI_MLQUEUE_HOST_BUSY;
-	}
-	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 
 	if (scmd->sc_data_direction == DMA_FROM_DEVICE)
 		mpi_control = MPI2_SCSIIO_CONTROL_READ;
@@ -3436,6 +3383,9 @@ _scsih_expander_add(struct MPT2SAS_ADAPTER *ioc, u16 handle)
 	if (!handle)
 		return -1;
 
+	if (ioc->shost_recovery)
+		return -1;
+
 	if ((mpt2sas_config_get_expander_pg0(ioc, &mpi_reply, &expander_pg0,
 	    MPI2_SAS_EXPAND_PGAD_FORM_HNDL, handle))) {
 		printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n",
@@ -3572,6 +3522,9 @@ _scsih_expander_remove(struct MPT2SAS_ADAPTER *ioc, u16 handle)
 	struct _sas_node *sas_expander;
 	unsigned long flags;
 
+	if (ioc->shost_recovery)
+		return;
+
 	spin_lock_irqsave(&ioc->sas_node_lock, flags);
 	sas_expander = mpt2sas_scsih_expander_find_by_handle(ioc, handle);
 	spin_unlock_irqrestore(&ioc->sas_node_lock, flags);
@@ -3743,6 +3696,8 @@ _scsih_remove_device(struct MPT2SAS_ADAPTER *ioc, u16 handle)
 		mutex_unlock(&ioc->tm_cmds.mutex);
 		dewtprintk(ioc, printk(MPT2SAS_INFO_FMT "issue target reset "
 		    "done: handle(0x%04x)\n", ioc->name, device_handle));
+		if (ioc->shost_recovery)
+			goto out;
 	}
 
 	/* SAS_IO_UNIT_CNTR - send REMOVE_DEVICE */
@@ -3765,6 +3720,9 @@ _scsih_remove_device(struct MPT2SAS_ADAPTER *ioc, u16 handle)
 	    le32_to_cpu(mpi_reply.IOCLogInfo)));
 
  out:
+
+	_scsih_ublock_io_device(ioc, handle);
+
 	mpt2sas_transport_port_remove(ioc, sas_device->sas_address,
 	    sas_device->parent_handle);
 
@@ -3908,6 +3866,8 @@ _scsih_sas_topology_change_event(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID,
 			    "expander event\n", ioc->name));
 			return;
 		}
+		if (ioc->shost_recovery)
+			return;
 		if (event_data->PHY[i].PhyStatus &
 		    MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT)
 			continue;
@@ -3942,10 +3902,6 @@ _scsih_sas_topology_change_event(struct MPT2SAS_ADAPTER *ioc, u8 VF_ID,
 						   link_rate_);
 				}
 			}
-			if (reason_code == MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED) {
-				if (link_rate_ >= MPI2_SAS_NEG_LINK_RATE_1_5)
-					_scsih_ublock_io_device(ioc, handle);
-			}
 			if (reason_code == MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED) {
 				if (link_rate_ < MPI2_SAS_NEG_LINK_RATE_1_5)
 					break;
@@ -5156,22 +5112,9 @@ static void
 _scsih_remove_unresponding_devices(struct MPT2SAS_ADAPTER *ioc)
 {
 	struct _sas_device *sas_device, *sas_device_next;
-	struct _sas_node *sas_expander, *sas_expander_next;
+	struct _sas_node *sas_expander;
 	struct _raid_device *raid_device, *raid_device_next;
-	unsigned long flags;
-
-	_scsih_search_responding_sas_devices(ioc);
-	_scsih_search_responding_raid_devices(ioc);
-	_scsih_search_responding_expanders(ioc);
 
-	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
-	ioc->shost_recovery = 0;
-	if (ioc->shost->shost_state == SHOST_RECOVERY) {
-		printk(MPT2SAS_INFO_FMT "putting controller into "
-		    "SHOST_RUNNING\n", ioc->name);
-		scsi_host_set_state(ioc->shost, SHOST_RUNNING);
-	}
-	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 
 	list_for_each_entry_safe(sas_device, sas_device_next,
 	    &ioc->sas_device_list, list) {
@@ -5207,16 +5150,63 @@ _scsih_remove_unresponding_devices(struct MPT2SAS_ADAPTER *ioc)
 		_scsih_raid_device_remove(ioc, raid_device);
 	}
 
-	list_for_each_entry_safe(sas_expander, sas_expander_next,
-	    &ioc->sas_expander_list, list) {
+ retry_expander_search:
+	sas_expander = NULL;
+	list_for_each_entry(sas_expander, &ioc->sas_expander_list, list) {
 		if (sas_expander->responding) {
 			sas_expander->responding = 0;
 			continue;
 		}
-		printk("\tremoving expander: handle(0x%04x), "
-		    " sas_addr(0x%016llx)\n", sas_expander->handle,
-		    (unsigned long long)sas_expander->sas_address);
 		_scsih_expander_remove(ioc, sas_expander->handle);
+		goto retry_expander_search;
+	}
+}
+
+/**
+ * mpt2sas_scsih_reset_handler - reset callback handler (for scsih)
+ * @ioc: per adapter object
+ * @reset_phase: phase
+ *
+ * The handler for doing any required cleanup or initialization.
+ *
+ * The reset phase can be MPT2_IOC_PRE_RESET, MPT2_IOC_AFTER_RESET,
+ * MPT2_IOC_DONE_RESET
+ *
+ * Return nothing.
+ */
+void
+mpt2sas_scsih_reset_handler(struct MPT2SAS_ADAPTER *ioc, int reset_phase)
+{
+	switch (reset_phase) {
+	case MPT2_IOC_PRE_RESET:
+		dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
+		    "MPT2_IOC_PRE_RESET\n", ioc->name, __func__));
+		_scsih_fw_event_off(ioc);
+		break;
+	case MPT2_IOC_AFTER_RESET:
+		dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
+		    "MPT2_IOC_AFTER_RESET\n", ioc->name, __func__));
+		if (ioc->tm_cmds.status & MPT2_CMD_PENDING) {
+			ioc->tm_cmds.status |= MPT2_CMD_RESET;
+			mpt2sas_base_free_smid(ioc, ioc->tm_cmds.smid);
+			complete(&ioc->tm_cmds.done);
+		}
+		_scsih_fw_event_on(ioc);
+		_scsih_flush_running_cmds(ioc);
+		break;
+	case MPT2_IOC_DONE_RESET:
+		dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
+		    "MPT2_IOC_DONE_RESET\n", ioc->name, __func__));
+		_scsih_sas_host_refresh(ioc, 0);
+		_scsih_search_responding_sas_devices(ioc);
+		_scsih_search_responding_raid_devices(ioc);
+		_scsih_search_responding_expanders(ioc);
+		break;
+	case MPT2_IOC_RUNNING:
+		dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
+		    "MPT2_IOC_RUNNING\n", ioc->name, __func__));
+		_scsih_remove_unresponding_devices(ioc);
+		break;
 	}
 }
 
@@ -5236,14 +5226,6 @@ _firmware_event_work(struct work_struct *work)
 	unsigned long flags;
 	struct MPT2SAS_ADAPTER *ioc = fw_event->ioc;
 
-	/* This is invoked by calling _scsih_queue_rescan(). */
-	if (fw_event->event == MPT2SAS_RESCAN_AFTER_HOST_RESET) {
-		_scsih_fw_event_free(ioc, fw_event);
-		_scsih_sas_host_refresh(ioc, 1);
-		_scsih_remove_unresponding_devices(ioc);
-		return;
-	}
-
 	/* the queue is being flushed so ignore this event */
 	spin_lock_irqsave(&ioc->fw_event_lock, flags);
 	if (ioc->fw_events_off || ioc->remove_host) {
@@ -5253,13 +5235,10 @@ _firmware_event_work(struct work_struct *work)
 	}
 	spin_unlock_irqrestore(&ioc->fw_event_lock, flags);
 
-	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 	if (ioc->shost_recovery) {
-		spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 		_scsih_fw_event_requeue(ioc, fw_event, 1000);
 		return;
 	}
-	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 
 	switch (fw_event->event) {
 	case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
@@ -5461,6 +5440,8 @@ _scsih_expander_node_remove(struct MPT2SAS_ADAPTER *ioc,
 			if (!sas_device)
 				continue;
 			_scsih_remove_device(ioc, sas_device->handle);
+			if (ioc->shost_recovery)
+				return;
 			goto retry_device_search;
 		}
 	}
@@ -5482,6 +5463,8 @@ _scsih_expander_node_remove(struct MPT2SAS_ADAPTER *ioc,
 			if (!expander_sibling)
 				continue;
 			_scsih_expander_remove(ioc, expander_sibling->handle);
+			if (ioc->shost_recovery)
+				return;
 			goto retry_expander_search;
 		}
 	}
@@ -5513,6 +5496,8 @@ _scsih_remove(struct pci_dev *pdev)
 	struct _sas_port *mpt2sas_port;
 	struct _sas_device *sas_device;
 	struct _sas_node *expander_sibling;
+	struct _raid_device *raid_device, *next;
+	struct MPT2SAS_TARGET *sas_target_priv_data;
 	struct workqueue_struct	*wq;
 	unsigned long flags;
 
@@ -5526,6 +5511,21 @@ _scsih_remove(struct pci_dev *pdev)
 	if (wq)
 		destroy_workqueue(wq);
 
+	/* release all the volumes */
+	list_for_each_entry_safe(raid_device, next, &ioc->raid_device_list,
+	    list) {
+		if (raid_device->starget) {
+			sas_target_priv_data =
+			    raid_device->starget->hostdata;
+			sas_target_priv_data->deleted = 1;
+			scsi_remove_target(&raid_device->starget->dev);
+		}
+		printk(MPT2SAS_INFO_FMT "removing handle(0x%04x), wwid"
+		    "(0x%016llx)\n", ioc->name,  raid_device->handle,
+		    (unsigned long long) raid_device->wwid);
+		_scsih_raid_device_remove(ioc, raid_device);
+	}
+
 	/* free ports attached to the sas_host */
  retry_again:
 	list_for_each_entry(mpt2sas_port,
diff --git a/drivers/scsi/mpt2sas/mpt2sas_transport.c b/drivers/scsi/mpt2sas/mpt2sas_transport.c
index 686695b155c7..a53086d0381a 100644
--- a/drivers/scsi/mpt2sas/mpt2sas_transport.c
+++ b/drivers/scsi/mpt2sas/mpt2sas_transport.c
@@ -140,11 +140,18 @@ _transport_set_identify(struct MPT2SAS_ADAPTER *ioc, u16 handle,
 	u32 device_info;
 	u32 ioc_status;
 
+	if (ioc->shost_recovery) {
+		printk(MPT2SAS_INFO_FMT "%s: host reset in progress!\n",
+		    __func__, ioc->name);
+		return -EFAULT;
+	}
+
 	if ((mpt2sas_config_get_sas_device_pg0(ioc, &mpi_reply, &sas_device_pg0,
 	    MPI2_SAS_DEVICE_PGAD_FORM_HANDLE, handle))) {
 		printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n",
+
 		    ioc->name, __FILE__, __LINE__, __func__);
-		return -1;
+		return -ENXIO;
 	}
 
 	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
@@ -153,7 +160,7 @@ _transport_set_identify(struct MPT2SAS_ADAPTER *ioc, u16 handle,
 		printk(MPT2SAS_ERR_FMT "handle(0x%04x), ioc_status(0x%04x)"
 		    "\nfailure at %s:%d/%s()!\n", ioc->name, handle, ioc_status,
 		     __FILE__, __LINE__, __func__);
-		return -1;
+		return -EIO;
 	}
 
 	memset(identify, 0, sizeof(identify));
@@ -288,21 +295,17 @@ _transport_expander_report_manufacture(struct MPT2SAS_ADAPTER *ioc,
 	void *psge;
 	u32 sgl_flags;
 	u8 issue_reset = 0;
-	unsigned long flags;
 	void *data_out = NULL;
 	dma_addr_t data_out_dma;
 	u32 sz;
 	u64 *sas_address_le;
 	u16 wait_state_count;
 
-	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
-	if (ioc->ioc_reset_in_progress) {
-		spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
+	if (ioc->shost_recovery) {
 		printk(MPT2SAS_INFO_FMT "%s: host reset in progress!\n",
 		    __func__, ioc->name);
 		return -EFAULT;
 	}
-	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 
 	mutex_lock(&ioc->transport_cmds.mutex);
 
@@ -806,6 +809,12 @@ mpt2sas_transport_update_phy_link_change(struct MPT2SAS_ADAPTER *ioc,
 	struct _sas_node *sas_node;
 	struct _sas_phy *mpt2sas_phy;
 
+	if (ioc->shost_recovery) {
+		printk(MPT2SAS_INFO_FMT "%s: host reset in progress!\n",
+			__func__, ioc->name);
+		return;
+	}
+
 	spin_lock_irqsave(&ioc->sas_node_lock, flags);
 	sas_node = _transport_sas_node_find_by_handle(ioc, handle);
 	spin_unlock_irqrestore(&ioc->sas_node_lock, flags);
@@ -1025,7 +1034,6 @@ _transport_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy,
 	void *psge;
 	u32 sgl_flags;
 	u8 issue_reset = 0;
-	unsigned long flags;
 	dma_addr_t dma_addr_in = 0;
 	dma_addr_t dma_addr_out = 0;
 	u16 wait_state_count;
@@ -1045,14 +1053,11 @@ _transport_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy,
 		return -EINVAL;
 	}
 
-	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
-	if (ioc->ioc_reset_in_progress) {
-		spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
+	if (ioc->shost_recovery) {
 		printk(MPT2SAS_INFO_FMT "%s: host reset in progress!\n",
 		    __func__, ioc->name);
 		return -EFAULT;
 	}
-	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 
 	rc = mutex_lock_interruptible(&ioc->transport_cmds.mutex);
 	if (rc)
diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c
index 0f8796201504..67e016d29f96 100644
--- a/drivers/scsi/qla2xxx/qla_attr.c
+++ b/drivers/scsi/qla2xxx/qla_attr.c
@@ -1654,7 +1654,8 @@ qla24xx_vport_create(struct fc_vport *fc_vport, bool disable)
 			fc_vport_set_state(fc_vport, FC_VPORT_LINKDOWN);
 	}
 
-	if (scsi_add_host(vha->host, &fc_vport->dev)) {
+	if (scsi_add_host_with_dma(vha->host, &fc_vport->dev,
+				   &ha->pdev->dev)) {
 		DEBUG15(printk("scsi(%ld): scsi_add_host failure for VP[%d].\n",
 			vha->host_no, vha->vp_idx));
 		goto vport_create_failed_2;
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 2de5f3ad640b..69397bb964a4 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -241,10 +241,7 @@ scsi_host_alloc_command(struct Scsi_Host *shost, gfp_t gfp_mask)
  */
 struct scsi_cmnd *__scsi_get_command(struct Scsi_Host *shost, gfp_t gfp_mask)
 {
-	struct scsi_cmnd *cmd;
-	unsigned char *buf;
-
-	cmd = scsi_host_alloc_command(shost, gfp_mask);
+	struct scsi_cmnd *cmd = scsi_host_alloc_command(shost, gfp_mask);
 
 	if (unlikely(!cmd)) {
 		unsigned long flags;
@@ -258,9 +255,15 @@ struct scsi_cmnd *__scsi_get_command(struct Scsi_Host *shost, gfp_t gfp_mask)
 		spin_unlock_irqrestore(&shost->free_list_lock, flags);
 
 		if (cmd) {
+			void *buf, *prot;
+
 			buf = cmd->sense_buffer;
+			prot = cmd->prot_sdb;
+
 			memset(cmd, 0, sizeof(*cmd));
+
 			cmd->sense_buffer = buf;
+			cmd->prot_sdb = prot;
 		}
 	}
 
diff --git a/drivers/scsi/scsi_error.c b/drivers/scsi/scsi_error.c
index a1689353d7fd..c253e9c051b2 100644
--- a/drivers/scsi/scsi_error.c
+++ b/drivers/scsi/scsi_error.c
@@ -721,6 +721,9 @@ static int scsi_send_eh_cmnd(struct scsi_cmnd *scmd, unsigned char *cmnd,
 		case NEEDS_RETRY:
 		case FAILED:
 			break;
+		case ADD_TO_MLQUEUE:
+			rtn = NEEDS_RETRY;
+			break;
 		default:
 			rtn = FAILED;
 			break;
diff --git a/drivers/scsi/scsi_lib_dma.c b/drivers/scsi/scsi_lib_dma.c
index ac6855cd2657..dcd128583b89 100644
--- a/drivers/scsi/scsi_lib_dma.c
+++ b/drivers/scsi/scsi_lib_dma.c
@@ -23,7 +23,7 @@ int scsi_dma_map(struct scsi_cmnd *cmd)
 	int nseg = 0;
 
 	if (scsi_sg_count(cmd)) {
-		struct device *dev = cmd->device->host->shost_gendev.parent;
+		struct device *dev = cmd->device->host->dma_dev;
 
 		nseg = dma_map_sg(dev, scsi_sglist(cmd), scsi_sg_count(cmd),
 				  cmd->sc_data_direction);
@@ -41,7 +41,7 @@ EXPORT_SYMBOL(scsi_dma_map);
 void scsi_dma_unmap(struct scsi_cmnd *cmd)
 {
 	if (scsi_sg_count(cmd)) {
-		struct device *dev = cmd->device->host->shost_gendev.parent;
+		struct device *dev = cmd->device->host->dma_dev;
 
 		dma_unmap_sg(dev, scsi_sglist(cmd), scsi_sg_count(cmd),
 			     cmd->sc_data_direction);
diff --git a/drivers/scsi/scsi_transport_fc.c b/drivers/scsi/scsi_transport_fc.c
index 292c02f810d0..7c3264ed146d 100644
--- a/drivers/scsi/scsi_transport_fc.c
+++ b/drivers/scsi/scsi_transport_fc.c
@@ -648,11 +648,22 @@ static __init int fc_transport_init(void)
 		return error;
 	error = transport_class_register(&fc_vport_class);
 	if (error)
-		return error;
+		goto unreg_host_class;
 	error = transport_class_register(&fc_rport_class);
 	if (error)
-		return error;
-	return transport_class_register(&fc_transport_class);
+		goto unreg_vport_class;
+	error = transport_class_register(&fc_transport_class);
+	if (error)
+		goto unreg_rport_class;
+	return 0;
+
+unreg_rport_class:
+	transport_class_unregister(&fc_rport_class);
+unreg_vport_class:
+	transport_class_unregister(&fc_vport_class);
+unreg_host_class:
+	transport_class_unregister(&fc_host_class);
+	return error;
 }
 
 static void __exit fc_transport_exit(void)
diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c
index b7b9fec67a98..a89c421dab51 100644
--- a/drivers/scsi/sd.c
+++ b/drivers/scsi/sd.c
@@ -2021,6 +2021,7 @@ static void sd_probe_async(void *data, async_cookie_t cookie)
 
 	sd_printk(KERN_NOTICE, sdkp, "Attached SCSI %sdisk\n",
 		  sdp->removable ? "removable " : "");
+	put_device(&sdkp->dev);
 }
 
 /**
@@ -2106,6 +2107,7 @@ static int sd_probe(struct device *dev)
 
 	get_device(&sdp->sdev_gendev);
 
+	get_device(&sdkp->dev);	/* prevent release before async_schedule */
 	async_schedule(sd_probe_async, sdkp);
 
 	return 0;
diff --git a/drivers/scsi/sg.c b/drivers/scsi/sg.c
index 9230402c45af..dc0e3d4eacc2 100644
--- a/drivers/scsi/sg.c
+++ b/drivers/scsi/sg.c
@@ -1708,11 +1708,6 @@ static int sg_finish_rem_req(Sg_request * srp)
 	Sg_scatter_hold *req_schp = &srp->data;
 
 	SCSI_LOG_TIMEOUT(4, printk("sg_finish_rem_req: res_used=%d\n", (int) srp->res_used));
-	if (srp->res_used)
-		sg_unlink_reserve(sfp, srp);
-	else
-		sg_remove_scat(req_schp);
-
 	if (srp->rq) {
 		if (srp->bio)
 			ret = blk_rq_unmap_user(srp->bio);
@@ -1720,6 +1715,11 @@ static int sg_finish_rem_req(Sg_request * srp)
 		blk_put_request(srp->rq);
 	}
 
+	if (srp->res_used)
+		sg_unlink_reserve(sfp, srp);
+	else
+		sg_remove_scat(req_schp);
+
 	sg_remove_request(sfp, srp);
 
 	return ret;
@@ -1811,7 +1811,7 @@ retry:
 	return 0;
 out:
 	for (i = 0; i < k; i++)
-		__free_pages(schp->pages[k], order);
+		__free_pages(schp->pages[i], order);
 
 	if (--order >= 0)
 		goto retry;
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index d5da26f34cee..ecbf0dac375a 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -81,6 +81,9 @@ static int serial_index(struct uart_port *port)
 
 #define PASS_LIMIT	256
 
+#define BOTH_EMPTY 	(UART_LSR_TEMT | UART_LSR_THRE)
+
+
 /*
  * We default to IRQ0 for the "no irq" hack.   Some
  * machine types want others as well - they're free
@@ -1342,14 +1345,12 @@ static void serial8250_start_tx(struct uart_port *port)
 		serial_out(up, UART_IER, up->ier);
 
 		if (up->bugs & UART_BUG_TXEN) {
-			unsigned char lsr, iir;
+			unsigned char lsr;
 			lsr = serial_in(up, UART_LSR);
 			up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
-			iir = serial_in(up, UART_IIR) & 0x0f;
 			if ((up->port.type == PORT_RM9000) ?
-				(lsr & UART_LSR_THRE &&
-				(iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
-				(lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
+				(lsr & UART_LSR_THRE) :
+				(lsr & UART_LSR_TEMT))
 				transmit_chars(up);
 		}
 	}
@@ -1802,7 +1803,7 @@ static unsigned int serial8250_tx_empty(struct uart_port *port)
 	up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
 	spin_unlock_irqrestore(&up->port.lock, flags);
 
-	return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
+	return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
 }
 
 static unsigned int serial8250_get_mctrl(struct uart_port *port)
@@ -1860,8 +1861,6 @@ static void serial8250_break_ctl(struct uart_port *port, int break_state)
 	spin_unlock_irqrestore(&up->port.lock, flags);
 }
 
-#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
-
 /*
  *	Wait for transmitter & holding register to empty
  */
diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
index e7108e75653d..7b5ff096c2db 100644
--- a/drivers/serial/8250_pci.c
+++ b/drivers/serial/8250_pci.c
@@ -1561,6 +1561,7 @@ enum pci_board_num_t {
 	pbn_exar_XR17C152,
 	pbn_exar_XR17C154,
 	pbn_exar_XR17C158,
+	pbn_exar_ibm_saturn,
 	pbn_pasemi_1682M,
 	pbn_ni8430_2,
 	pbn_ni8430_4,
@@ -2146,6 +2147,13 @@ static struct pciserial_board pci_boards[] __devinitdata = {
 		.base_baud	= 921600,
 		.uart_offset	= 0x200,
 	},
+	[pbn_exar_ibm_saturn] = {
+		.flags		= FL_BASE0,
+		.num_ports	= 1,
+		.base_baud	= 921600,
+		.uart_offset	= 0x200,
+	},
+
 	/*
 	 * PA Semi PWRficient PA6T-1682M on-chip UART
 	 */
@@ -2649,6 +2657,9 @@ static struct pci_device_id serial_pci_tbl[] = {
 		PCI_SUBVENDOR_ID_CONNECT_TECH,
 		PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
 		pbn_b0_8_1843200_200 },
+	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
+		PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
+		0, 0, pbn_exar_ibm_saturn },
 
 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
diff --git a/drivers/serial/8250_pnp.c b/drivers/serial/8250_pnp.c
index d71dfe398940..9fb71903c107 100644
--- a/drivers/serial/8250_pnp.c
+++ b/drivers/serial/8250_pnp.c
@@ -328,15 +328,7 @@ static const struct pnp_device_id pnp_dev_table[] = {
 	/* U.S. Robotics 56K Voice INT PnP*/
 	{	"USR9190",		0	},
 	/* Wacom tablets */
-	{	"WACF004",		0	},
-	{	"WACF005",		0	},
-	{       "WACF006",              0       },
-	{       "WACF007",              0       },
-	{       "WACF008",              0       },
-	{       "WACF009",              0       },
-	{       "WACF00A",              0       },
-	{       "WACF00B",              0       },
-	{       "WACF00C",              0       },
+	{	"WACFXXX",		0	},
 	/* Compaq touchscreen */
 	{       "FPI2002",              0 },
 	/* Fujitsu Stylistic touchscreens */
diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c
index b4a7650af696..4fff4e524034 100644
--- a/drivers/serial/bfin_5xx.c
+++ b/drivers/serial/bfin_5xx.c
@@ -42,6 +42,10 @@
 # undef CONFIG_EARLY_PRINTK
 #endif
 
+#ifdef CONFIG_SERIAL_BFIN_MODULE
+# undef CONFIG_EARLY_PRINTK
+#endif
+
 /* UART name and device definitions */
 #define BFIN_SERIAL_NAME	"ttyBF"
 #define BFIN_SERIAL_MAJOR	204
diff --git a/drivers/serial/mxs-auart.c b/drivers/serial/mxs-auart.c
index 0eea46d71979..0791af105f72 100644
--- a/drivers/serial/mxs-auart.c
+++ b/drivers/serial/mxs-auart.c
@@ -514,7 +514,7 @@ static void mxs_auart_settermios(struct uart_port *u,
 
 	/* parity */
 	if (cflag & PARENB) {
-		ctrl |= BM_UARTAPP_LINECTRL_PEN | BM_UARTAPP_LINECTRL_SPS;
+		ctrl |= BM_UARTAPP_LINECTRL_PEN;
 		if ((cflag & PARODD) == 0)
 			ctrl |= BM_UARTAPP_LINECTRL_EPS;
 	}
@@ -565,9 +565,33 @@ static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
 		mxs_auart_tx_chars(s);
 		istat &= ~BM_UARTAPP_INTR_TXIS;
 	}
-	if (istat & 0xFFFF)
+	/* modem status interrupt bits are undefined
+	after reset,and the hardware do not support
+	DSRMIS,DCDMIS and RIMIS bit,so we should ingore
+	them when they are pending. */
+	if (istat & (BM_UARTAPP_INTR_ABDIS
+		| BM_UARTAPP_INTR_OEIS
+		| BM_UARTAPP_INTR_BEIS
+		| BM_UARTAPP_INTR_PEIS
+		| BM_UARTAPP_INTR_FEIS
+		| BM_UARTAPP_INTR_RTIS
+		| BM_UARTAPP_INTR_TXIS
+		| BM_UARTAPP_INTR_RXIS
+		| BM_UARTAPP_INTR_CTSMIS)) {
 		dev_info(s->dev, "Unhandled status %x\n", istat);
-	__raw_writel(istatus & 0xFFFF,
+	}
+	__raw_writel(istatus & (BM_UARTAPP_INTR_ABDIS
+		| BM_UARTAPP_INTR_OEIS
+		| BM_UARTAPP_INTR_BEIS
+		| BM_UARTAPP_INTR_PEIS
+		| BM_UARTAPP_INTR_FEIS
+		| BM_UARTAPP_INTR_RTIS
+		| BM_UARTAPP_INTR_TXIS
+		| BM_UARTAPP_INTR_RXIS
+		| BM_UARTAPP_INTR_DSRMIS
+		| BM_UARTAPP_INTR_DCDMIS
+		| BM_UARTAPP_INTR_CTSMIS
+		| BM_UARTAPP_INTR_RIMIS),
 			s->port.membase + HW_UARTAPP_INTR_CLR);
 
 	return IRQ_HANDLED;
diff --git a/drivers/serial/mxs-duart.c b/drivers/serial/mxs-duart.c
index 5d006f380930..171b8628faee 100644
--- a/drivers/serial/mxs-duart.c
+++ b/drivers/serial/mxs-duart.c
@@ -735,9 +735,40 @@ static int __devexit duart_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_PM
+static int duart_suspend(struct platform_device *pdev,
+		pm_message_t state)
+{
+	int ret = 0;
+	if (!duart_port.suspended) {
+		ret = uart_suspend_port(&duart_drv, &duart_port.port);
+		if (!ret)
+			duart_port.suspended = 1;
+	}
+	return ret;
+}
+
+static int duart_resume(struct platform_device *pdev,
+		pm_message_t state)
+{
+	int ret = 0;
+	if (duart_port.suspended) {
+		ret = uart_resume_port(&duart_drv, &duart_port.port);
+		if (!ret)
+			duart_port.suspended = 0;
+	}
+	return ret;
+}
+#else
+#define	duart_suspend	NULL
+#define	duart_resume	NULL
+#endif
+
 static struct platform_driver duart_driver = {
 	.probe = duart_probe,
 	.remove = __devexit_p(duart_remove),
+	.suspend = duart_suspend,
+	.resume = duart_resume,
 	.driver = {
 		   .name = "mxs-duart",
 		   .owner = THIS_MODULE,
diff --git a/drivers/serial/of_serial.c b/drivers/serial/of_serial.c
index 02406ba6da1c..cdf172eda2e3 100644
--- a/drivers/serial/of_serial.c
+++ b/drivers/serial/of_serial.c
@@ -161,6 +161,7 @@ static int of_platform_serial_remove(struct of_device *ofdev)
 static struct of_device_id __devinitdata of_platform_serial_table[] = {
 	{ .type = "serial", .compatible = "ns8250",   .data = (void *)PORT_8250, },
 	{ .type = "serial", .compatible = "ns16450",  .data = (void *)PORT_16450, },
+	{ .type = "serial", .compatible = "ns16550a", .data = (void *)PORT_16550A, },
 	{ .type = "serial", .compatible = "ns16550",  .data = (void *)PORT_16550, },
 	{ .type = "serial", .compatible = "ns16750",  .data = (void *)PORT_16750, },
 	{ .type = "serial", .compatible = "ns16850",  .data = (void *)PORT_16850, },
diff --git a/drivers/serial/serial_cs.c b/drivers/serial/serial_cs.c
index 79c9c5f5cdba..6ecb51baf56e 100644
--- a/drivers/serial/serial_cs.c
+++ b/drivers/serial/serial_cs.c
@@ -884,6 +884,7 @@ static struct pcmcia_device_id serial_ids[] = {
 	PCMCIA_DEVICE_CIS_MANF_CARD(0x0192, 0xa555, "SW_555_SER.cis"),  /* Sierra Aircard 555 CDMA 1xrtt Modem -- pre update */
 	PCMCIA_DEVICE_CIS_MANF_CARD(0x013f, 0xa555, "SW_555_SER.cis"),  /* Sierra Aircard 555 CDMA 1xrtt Modem -- post update */
 	PCMCIA_DEVICE_CIS_PROD_ID12("MultiTech", "PCMCIA 56K DataFax", 0x842047ee, 0xc2efcf03, "MT5634ZLX.cis"),
+	PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-2", 0x96913a85, 0x27ab5437, "COMpad2.cis"),
 	PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-4", 0x96913a85, 0xcec8f102, "COMpad4.cis"),
 	PCMCIA_DEVICE_CIS_PROD_ID123("ADVANTECH", "COMpad-32/85", "1.0", 0x96913a85, 0x8fbe92ae, 0x0877b627, "COMpad2.cis"),
 	PCMCIA_DEVICE_CIS_PROD_ID2("RS-COM 2P", 0xad20b156, "RS-COM-2P.cis"),
diff --git a/drivers/serial/suncore.c b/drivers/serial/suncore.c
index a2d4a19550ab..ed7d958b0a01 100644
--- a/drivers/serial/suncore.c
+++ b/drivers/serial/suncore.c
@@ -53,20 +53,21 @@ void sunserial_unregister_minors(struct uart_driver *drv, int count)
 EXPORT_SYMBOL(sunserial_unregister_minors);
 
 int sunserial_console_match(struct console *con, struct device_node *dp,
-			    struct uart_driver *drv, int line)
+			    struct uart_driver *drv, int line, bool ignore_line)
 {
-	int off;
-
 	if (!con || of_console_device != dp)
 		return 0;
 
-	off = 0;
-	if (of_console_options &&
-	    *of_console_options == 'b')
-		off = 1;
+	if (!ignore_line) {
+		int off = 0;
 
-	if ((line & 1) != off)
-		return 0;
+		if (of_console_options &&
+		    *of_console_options == 'b')
+			off = 1;
+
+		if ((line & 1) != off)
+			return 0;
+	}
 
 	con->index = line;
 	drv->cons = con;
@@ -76,23 +77,24 @@ int sunserial_console_match(struct console *con, struct device_node *dp,
 }
 EXPORT_SYMBOL(sunserial_console_match);
 
-void
-sunserial_console_termios(struct console *con)
+void sunserial_console_termios(struct console *con, struct device_node *uart_dp)
 {
-	struct device_node *dp;
-	const char *od, *mode, *s;
+	const char *mode, *s;
 	char mode_prop[] = "ttyX-mode";
 	int baud, bits, stop, cflag;
 	char parity;
 
-	dp = of_find_node_by_path("/options");
-	od = of_get_property(dp, "output-device", NULL);
-	if (!strcmp(od, "rsc")) {
-		mode = of_get_property(of_console_device,
+	if (!strcmp(uart_dp->name, "rsc") ||
+	    !strcmp(uart_dp->name, "rsc-console") ||
+	    !strcmp(uart_dp->name, "rsc-control")) {
+		mode = of_get_property(uart_dp,
 				       "ssp-console-modes", NULL);
 		if (!mode)
 			mode = "115200,8,n,1,-";
+	} else if (!strcmp(uart_dp->name, "lom-console")) {
+		mode = "9600,8,n,1,-";
 	} else {
+		struct device_node *dp;
 		char c;
 
 		c = 'a';
@@ -101,6 +103,7 @@ sunserial_console_termios(struct console *con)
 
 		mode_prop[3] = c;
 
+		dp = of_find_node_by_path("/options");
 		mode = of_get_property(dp, mode_prop, NULL);
 		if (!mode)
 			mode = "9600,8,n,1,-";
diff --git a/drivers/serial/suncore.h b/drivers/serial/suncore.h
index 042668aa602e..db2057936c31 100644
--- a/drivers/serial/suncore.h
+++ b/drivers/serial/suncore.h
@@ -26,7 +26,8 @@ extern int sunserial_register_minors(struct uart_driver *, int);
 extern void sunserial_unregister_minors(struct uart_driver *, int);
 
 extern int sunserial_console_match(struct console *, struct device_node *,
-				   struct uart_driver *, int);
-extern void sunserial_console_termios(struct console *);
+				   struct uart_driver *, int, bool);
+extern void sunserial_console_termios(struct console *,
+				      struct device_node *);
 
 #endif /* !(_SERIAL_SUN_H) */
diff --git a/drivers/serial/sunhv.c b/drivers/serial/sunhv.c
index 1df5325faab2..3b6953aa5d03 100644
--- a/drivers/serial/sunhv.c
+++ b/drivers/serial/sunhv.c
@@ -566,7 +566,7 @@ static int __devinit hv_probe(struct of_device *op, const struct of_device_id *m
 		goto out_free_con_read_page;
 
 	sunserial_console_match(&sunhv_console, op->node,
-				&sunhv_reg, port->line);
+				&sunhv_reg, port->line, false);
 
 	err = uart_add_one_port(&sunhv_reg, port);
 	if (err)
diff --git a/drivers/serial/sunsab.c b/drivers/serial/sunsab.c
index 0355efe115d9..9cbf597e0ab8 100644
--- a/drivers/serial/sunsab.c
+++ b/drivers/serial/sunsab.c
@@ -883,7 +883,7 @@ static int sunsab_console_setup(struct console *con, char *options)
 	printk("Console: ttyS%d (SAB82532)\n",
 	       (sunsab_reg.minor - 64) + con->index);
 
-	sunserial_console_termios(con);
+	sunserial_console_termios(con, to_of_device(up->port.dev)->node);
 
 	switch (con->cflag & CBAUD) {
 	case B150: baud = 150; break;
@@ -1027,10 +1027,12 @@ static int __devinit sab_probe(struct of_device *op, const struct of_device_id *
 		goto out1;
 
 	sunserial_console_match(SUNSAB_CONSOLE(), op->node,
-				&sunsab_reg, up[0].port.line);
+				&sunsab_reg, up[0].port.line,
+				false);
 
 	sunserial_console_match(SUNSAB_CONSOLE(), op->node,
-				&sunsab_reg, up[1].port.line);
+				&sunsab_reg, up[1].port.line,
+				false);
 
 	err = uart_add_one_port(&sunsab_reg, &up[0].port);
 	if (err)
@@ -1116,7 +1118,6 @@ static int __init sunsab_init(void)
 		if (!sunsab_ports)
 			return -ENOMEM;
 
-		sunsab_reg.cons = SUNSAB_CONSOLE();
 		err = sunserial_register_minors(&sunsab_reg, num_channels);
 		if (err) {
 			kfree(sunsab_ports);
diff --git a/drivers/serial/sunsu.c b/drivers/serial/sunsu.c
index 47c6837850b1..ab91166b1b16 100644
--- a/drivers/serial/sunsu.c
+++ b/drivers/serial/sunsu.c
@@ -1329,11 +1329,9 @@ static void sunsu_console_write(struct console *co, const char *s,
  */
 static int __init sunsu_console_setup(struct console *co, char *options)
 {
+	static struct ktermios dummy;
+	struct ktermios termios;
 	struct uart_port *port;
-	int baud = 9600;
-	int bits = 8;
-	int parity = 'n';
-	int flow = 'n';
 
 	printk("Console: ttyS%d (SU)\n",
 	       (sunsu_reg.minor - 64) + co->index);
@@ -1352,10 +1350,15 @@ static int __init sunsu_console_setup(struct console *co, char *options)
 	 */
 	spin_lock_init(&port->lock);
 
-	if (options)
-		uart_parse_options(options, &baud, &parity, &bits, &flow);
+	/* Get firmware console settings.  */
+	sunserial_console_termios(co, to_of_device(port->dev)->node);
 
-	return uart_set_options(port, co, baud, parity, bits, flow);
+	memset(&termios, 0, sizeof(struct ktermios));
+	termios.c_cflag = co->cflag;
+	port->mctrl |= TIOCM_DTR;
+	port->ops->set_termios(port, &termios, &dummy);
+
+	return 0;
 }
 
 static struct console sunsu_console = {
@@ -1409,6 +1412,7 @@ static int __devinit su_probe(struct of_device *op, const struct of_device_id *m
 	struct uart_sunsu_port *up;
 	struct resource *rp;
 	enum su_type type;
+	bool ignore_line;
 	int err;
 
 	type = su_get_type(dp);
@@ -1467,8 +1471,14 @@ static int __devinit su_probe(struct of_device *op, const struct of_device_id *m
 
 	up->port.ops = &sunsu_pops;
 
+	ignore_line = false;
+	if (!strcmp(dp->name, "rsc-console") ||
+	    !strcmp(dp->name, "lom-console"))
+		ignore_line = true;
+
 	sunserial_console_match(SUNSU_CONSOLE(), dp,
-				&sunsu_reg, up->port.line);
+				&sunsu_reg, up->port.line,
+				ignore_line);
 	err = uart_add_one_port(&sunsu_reg, &up->port);
 	if (err)
 		goto out_unmap;
@@ -1517,6 +1527,10 @@ static const struct of_device_id su_match[] = {
 		.name = "serial",
 		.compatible = "su",
 	},
+	{
+		.type = "serial",
+		.compatible = "su",
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, su_match);
@@ -1548,6 +1562,12 @@ static int __init sunsu_init(void)
 				num_uart++;
 		}
 	}
+	for_each_node_by_type(dp, "serial") {
+		if (of_device_is_compatible(dp, "su")) {
+			if (su_get_type(dp) == SU_PORT_PORT)
+				num_uart++;
+		}
+	}
 
 	if (num_uart) {
 		err = sunserial_register_minors(&sunsu_reg, num_uart);
diff --git a/drivers/serial/sunzilog.c b/drivers/serial/sunzilog.c
index e09d3cebb4fb..0a2a3335f30f 100644
--- a/drivers/serial/sunzilog.c
+++ b/drivers/serial/sunzilog.c
@@ -1180,7 +1180,7 @@ static int __init sunzilog_console_setup(struct console *con, char *options)
 	       (sunzilog_reg.minor - 64) + con->index, con->index);
 
 	/* Get firmware console settings.  */
-	sunserial_console_termios(con);
+	sunserial_console_termios(con, to_of_device(up->port.dev)->node);
 
 	/* Firmware console speed is limited to 150-->38400 baud so
 	 * this hackish cflag thing is OK.
@@ -1416,7 +1416,8 @@ static int __devinit zs_probe(struct of_device *op, const struct of_device_id *m
 
 	if (!keyboard_mouse) {
 		if (sunserial_console_match(SUNZILOG_CONSOLE(), op->node,
-					    &sunzilog_reg, up[0].port.line))
+					    &sunzilog_reg, up[0].port.line,
+					    false))
 			up->flags |= SUNZILOG_FLAG_IS_CONS;
 		err = uart_add_one_port(&sunzilog_reg, &up[0].port);
 		if (err) {
@@ -1425,7 +1426,8 @@ static int __devinit zs_probe(struct of_device *op, const struct of_device_id *m
 			return err;
 		}
 		if (sunserial_console_match(SUNZILOG_CONSOLE(), op->node,
-					    &sunzilog_reg, up[1].port.line))
+					    &sunzilog_reg, up[1].port.line,
+					    false))
 			up->flags |= SUNZILOG_FLAG_IS_CONS;
 		err = uart_add_one_port(&sunzilog_reg, &up[1].port);
 		if (err) {
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index e16915107c6b..736a12ff9045 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -261,6 +261,11 @@ config SPI_STMP3XXX
 	help
 	  SPI driver for Freescale STMP37xx/378x SoC SSP interface
 
+config SPI_MXS
+	tristate "Freescale MXS SPI/SSP controller"
+	depends on ARCH_MXS && SPI_MASTER
+	help
+	  SPI driver for Freescale MXS SoC SSP interface
 #
 # Add new SPI master controllers in alphabetical order above this line
 #
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index b7cfb6245c0b..b6dbdf064181 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_SPI_MXC)			+= mxc_spi.o
 obj-$(CONFIG_SPI_XILINX)		+= xilinx_spi.o
 obj-$(CONFIG_SPI_SH_SCI)		+= spi_sh_sci.o
 obj-$(CONFIG_SPI_STMP3XXX)		+= spi_stmp.o
+obj-$(CONFIG_SPI_MXS)			+= spi_mxs.o
 # 	... add above this line ...
 
 # SPI protocol drivers (device/link on bus)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index cfe40a4526a7..5f4aa2e90392 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -657,7 +657,7 @@ void mxc_spi_chipselect(struct spi_device *spi, int is_active)
 		if (spi->mode & SPI_CPHA)
 			ctrl_reg |=
 			    spi_ver_def->mode_mask << spi_ver_def->pha_shift;
-		if (!(spi->mode & SPI_CPOL))
+		if (spi->mode & SPI_CPOL)
 			ctrl_reg |=
 			    spi_ver_def->mode_mask << spi_ver_def->
 			    low_pol_shift;
@@ -824,16 +824,23 @@ int mxc_spi_poll_transfer(struct spi_device *spi, struct spi_transfer *t)
 	master_drv_data->transfer.count = t->len;
 	fifo_size = master_drv_data->spi_ver_def->fifo_size;
 
-	count = (t->len > fifo_size) ? fifo_size : t->len;
-	spi_put_tx_data(master_drv_data->base, count, master_drv_data);
+	while (master_drv_data->transfer.count) {
+		count = (master_drv_data->transfer.count > fifo_size) ?
+			fifo_size : master_drv_data->transfer.count;
 
-	while ((((status = __raw_readl(master_drv_data->test_addr)) &
-		 master_drv_data->spi_ver_def->rx_cnt_mask) >> master_drv_data->
-		spi_ver_def->rx_cnt_off) != count);
+		spi_put_tx_data(master_drv_data->base, count, master_drv_data);
 
-	for (i = 0; i < count; i++) {
-		rx_tmp = __raw_readl(master_drv_data->base + MXC_CSPIRXDATA);
-		master_drv_data->transfer.rx_get(master_drv_data, rx_tmp);
+		while ((((status = __raw_readl(master_drv_data->test_addr)) &
+		  	 master_drv_data->spi_ver_def->rx_cnt_mask) >> master_drv_data->
+			spi_ver_def->rx_cnt_off) != count)
+			;
+
+		for (i = 0; i < count; i++) {
+			rx_tmp = __raw_readl(master_drv_data->base + MXC_CSPIRXDATA);
+			master_drv_data->transfer.rx_get(master_drv_data, rx_tmp);
+		}
+
+		master_drv_data->transfer.count -= count;
 	}
 
 	clk_disable(master_drv_data->clk);
@@ -864,8 +871,19 @@ int mxc_spi_transfer(struct spi_device *spi, struct spi_transfer *t)
 	int chipselect_status;
 	u32 fifo_size;
 
+#if defined(CONFIG_MODULE_CCXMX51)
+	/**
+	 * The ConnectCore i.MX51/Wi-i.MX51 use this bus to communicate with
+	 * the pmic, using poll transfers. Because that bus is also used to
+	 * communicate the cpu with other devices, use also poll transfers
+	 * to avoid conflicts.
+	 */
+	if (spi->master->bus_num == 1) {
+		mxc_spi_poll_transfer(spi, t);
+		return t->len;
+	}
+#endif
 	/* Get the master controller driver data from spi device's master */
-
 	master_drv_data = spi_master_get_devdata(spi->master);
 
 	chipselect_status = __raw_readl(MXC_CSPICONFIG +
diff --git a/drivers/spi/spi_mxs.c b/drivers/spi/spi_mxs.c
new file mode 100644
index 000000000000..744be68d9433
--- /dev/null
+++ b/drivers/spi/spi_mxs.c
@@ -0,0 +1,711 @@
+/*
+ * Freescale MXS SPI master driver
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/errno.h>
+#include <asm/dma.h>
+
+#include <mach/regs-ssp.h>
+#include <mach/dmaengine.h>
+#include <mach/device.h>
+#include <mach/system.h>
+#include <mach/hardware.h>
+
+#include "spi_mxs.h"
+
+/* 0 means DMA modei(recommended, default), !0 - PIO mode */
+static int pio /* = 0 */ ;
+static int debug;
+
+/**
+ * mxs_spi_init_hw
+ *
+ * Initialize the SSP port
+ */
+static int mxs_spi_init_hw(struct mxs_spi *ss)
+{
+	int err;
+
+	ss->clk = clk_get(NULL, "ssp.0");
+	if (IS_ERR(ss->clk)) {
+		err = PTR_ERR(ss->clk);
+		goto out;
+	}
+	clk_enable(ss->clk);
+
+	mxs_reset_block((void *)ss->regs, 0);
+	mxs_dma_reset(ss->dma);
+
+	return 0;
+
+out:
+	return err;
+}
+
+static void mxs_spi_release_hw(struct mxs_spi *ss)
+{
+	if (ss->clk && !IS_ERR(ss->clk)) {
+		clk_disable(ss->clk);
+		clk_put(ss->clk);
+	}
+}
+
+static int mxs_spi_setup_transfer(struct spi_device *spi,
+				  struct spi_transfer *t)
+{
+	u8 bits_per_word;
+	u32 hz;
+	struct mxs_spi *ss /* = spi_master_get_devdata(spi->master) */ ;
+	u16 rate;
+
+	ss = spi_master_get_devdata(spi->master);
+
+	bits_per_word = spi->bits_per_word;
+	if (t && t->bits_per_word)
+		bits_per_word = t->bits_per_word;
+
+	/*
+	   Calculate speed:
+	   - by default, use maximum speed from ssp clk
+	   - if device overrides it, use it
+	   - if transfer specifies other speed, use transfer's one
+	 */
+	hz = 1000 * ss->speed_khz / ss->divider;
+	if (spi->max_speed_hz)
+		hz = min(hz, spi->max_speed_hz);
+	if (t && t->speed_hz)
+		hz = min(hz, t->speed_hz);
+
+	if (hz == 0) {
+		dev_err(&spi->dev, "Cannot continue with zero clock\n");
+		return -EINVAL;
+	}
+
+	if (bits_per_word != 8) {
+		dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
+			__func__, bits_per_word);
+		return -EINVAL;
+	}
+
+	dev_dbg(&spi->dev, "Requested clk rate = %uHz, max = %ukHz/%d = %uHz\n",
+		hz, ss->speed_khz, ss->divider,
+		ss->speed_khz * 1000 / ss->divider);
+
+	if (ss->speed_khz * 1000 / ss->divider < hz) {
+		dev_err(&spi->dev, "%s, unsupported clock rate %uHz\n",
+			__func__, hz);
+		return -EINVAL;
+	}
+
+	rate = 1000 * ss->speed_khz / ss->divider / hz;
+
+	__raw_writel(BF_SSP_TIMING_CLOCK_DIVIDE(ss->divider) |
+		     BF_SSP_TIMING_CLOCK_RATE(rate - 1),
+		     ss->regs + HW_SSP_TIMING);
+
+	__raw_writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
+		     BF_SSP_CTRL1_WORD_LENGTH
+		     (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
+		     ((spi->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
+		     ((spi->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0) |
+		     (pio ? 0 : BM_SSP_CTRL1_DMA_ENABLE),
+		     ss->regs + HW_SSP_CTRL1);
+
+	__raw_writel(0x00, ss->regs + HW_SSP_CMD0_SET);
+
+	return 0;
+}
+
+static void mxs_spi_cleanup(struct spi_device *spi)
+{
+	struct mxs_spi_platform_data *pdata = spi->dev.platform_data;
+
+	if (pdata && pdata->hw_pin_release)
+		pdata->hw_pin_release();
+}
+
+/* the spi->mode bits understood by this driver: */
+#define MODEBITS (SPI_CPOL | SPI_CPHA)
+static int mxs_spi_setup(struct spi_device *spi)
+{
+	struct mxs_spi_platform_data *pdata;
+	struct mxs_spi *ss;
+	int err = 0;
+
+	ss = spi_master_get_devdata(spi->master);
+
+	if (!spi->bits_per_word)
+		spi->bits_per_word = 8;
+
+	if (spi->mode & ~MODEBITS) {
+		dev_err(&spi->dev, "%s: unsupported mode bits %x\n",
+			__func__, spi->mode & ~MODEBITS);
+		err = -EINVAL;
+		goto out;
+	}
+
+	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w\n",
+		__func__, spi->mode & MODEBITS, spi->bits_per_word);
+
+	pdata = spi->dev.platform_data;
+
+	if (pdata && pdata->hw_pin_init) {
+		err = pdata->hw_pin_init();
+		if (err)
+			goto out;
+	}
+
+	err = mxs_spi_setup_transfer(spi, NULL);
+	if (err)
+		goto out2;
+	return 0;
+
+out2:
+	if (pdata && pdata->hw_pin_release)
+		pdata->hw_pin_release();
+out:
+	dev_err(&spi->dev, "Failed to setup transfer, error = %d\n", err);
+	return err;
+}
+
+static inline u32 mxs_spi_cs(unsigned cs)
+{
+	return ((cs & 1) ? BM_SSP_CTRL0_WAIT_FOR_CMD : 0) |
+	    ((cs & 2) ? BM_SSP_CTRL0_WAIT_FOR_IRQ : 0);
+}
+
+static int mxs_spi_txrx_dma(struct mxs_spi *ss, int cs,
+			    unsigned char *buf, dma_addr_t dma_buf, int len,
+			    int *first, int *last, int write)
+{
+	u32 c0 = 0;
+	dma_addr_t spi_buf_dma = dma_buf;
+	int count, status = 0;
+	enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+
+	c0 |= (*first ? BM_SSP_CTRL0_LOCK_CS : 0);
+	c0 |= (*last ? BM_SSP_CTRL0_IGNORE_CRC : 0);
+	c0 |= (write ? 0 : BM_SSP_CTRL0_READ);
+	c0 |= BM_SSP_CTRL0_DATA_XFER;
+
+	c0 |= mxs_spi_cs(cs);
+
+	c0 |= BF_SSP_CTRL0_XFER_COUNT(len);
+
+	if (!dma_buf)
+		spi_buf_dma = dma_map_single(ss->master_dev, buf, len, dir);
+
+	ss->pdesc->cmd.cmd.bits.bytes = len;
+	ss->pdesc->cmd.cmd.bits.pio_words = 1;
+	ss->pdesc->cmd.cmd.bits.wait4end = 1;
+	ss->pdesc->cmd.cmd.bits.dec_sem = 1;
+	ss->pdesc->cmd.cmd.bits.irq = 1;
+	ss->pdesc->cmd.cmd.bits.command = write ? DMA_READ : DMA_WRITE;
+	ss->pdesc->cmd.address = spi_buf_dma;
+	ss->pdesc->cmd.pio_words[0] = c0;
+	mxs_dma_desc_append(ss->dma, ss->pdesc);
+
+	mxs_dma_reset(ss->dma);
+	mxs_dma_ack_irq(ss->dma);
+	mxs_dma_enable_irq(ss->dma, 1);
+	init_completion(&ss->done);
+	mxs_dma_enable(ss->dma);
+	wait_for_completion(&ss->done);
+	count = 10000;
+	while ((__raw_readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN)
+	       && count--)
+		continue;
+	if (count <= 0) {
+		printk(KERN_ERR "%c: timeout on line %s:%d\n",
+		       write ? 'W' : 'C', __func__, __LINE__);
+		status = -ETIMEDOUT;
+	}
+
+	if (!dma_buf)
+		dma_unmap_single(ss->master_dev, spi_buf_dma, len, dir);
+
+	return status;
+}
+
+static inline void mxs_spi_enable(struct mxs_spi *ss)
+{
+	__raw_writel(BM_SSP_CTRL0_LOCK_CS, ss->regs + HW_SSP_CTRL0_SET);
+	__raw_writel(BM_SSP_CTRL0_IGNORE_CRC, ss->regs + HW_SSP_CTRL0_CLR);
+}
+
+static inline void mxs_spi_disable(struct mxs_spi *ss)
+{
+	__raw_writel(BM_SSP_CTRL0_LOCK_CS, ss->regs + HW_SSP_CTRL0_CLR);
+	__raw_writel(BM_SSP_CTRL0_IGNORE_CRC, ss->regs + HW_SSP_CTRL0_SET);
+}
+
+static int mxs_spi_txrx_pio(struct mxs_spi *ss, int cs,
+			    unsigned char *buf, int len,
+			    int *first, int *last, int write)
+{
+	int count;
+
+	if (*first) {
+		mxs_spi_enable(ss);
+		*first = 0;
+	}
+
+	__raw_writel(mxs_spi_cs(cs), ss->regs + HW_SSP_CTRL0_SET);
+
+	while (len--) {
+		if (*last && len == 0) {
+			mxs_spi_disable(ss);
+			*last = 0;
+		}
+		__raw_writel(BM_SSP_CTRL0_XFER_COUNT,
+			     ss->regs + HW_SSP_CTRL0_CLR);
+		__raw_writel(1, ss->regs + HW_SSP_CTRL0_SET);	/* byte-by-byte */
+
+		if (write)
+			__raw_writel(BM_SSP_CTRL0_READ,
+				     ss->regs + HW_SSP_CTRL0_CLR);
+		else
+			__raw_writel(BM_SSP_CTRL0_READ,
+				     ss->regs + HW_SSP_CTRL0_SET);
+
+		/* Run! */
+		__raw_writel(BM_SSP_CTRL0_RUN, ss->regs + HW_SSP_CTRL0_SET);
+		count = 10000;
+		while (((__raw_readl(ss->regs + HW_SSP_CTRL0) &
+			 BM_SSP_CTRL0_RUN) == 0) && count--)
+			continue;
+		if (count <= 0) {
+			printk(KERN_ERR "%c: timeout on line %s:%d\n",
+			       write ? 'W' : 'C', __func__, __LINE__);
+			break;
+		}
+
+		if (write)
+			__raw_writel(*buf, ss->regs + HW_SSP_DATA);
+
+		/* Set TRANSFER */
+		__raw_writel(BM_SSP_CTRL0_DATA_XFER,
+			     ss->regs + HW_SSP_CTRL0_SET);
+
+		if (!write) {
+			count = 10000;
+			while (count-- &&
+			       (__raw_readl(ss->regs + HW_SSP_STATUS) &
+				BM_SSP_STATUS_FIFO_EMPTY))
+				continue;
+			if (count <= 0) {
+				printk(KERN_ERR "%c: timeout on line %s:%d\n",
+				       write ? 'W' : 'C', __func__, __LINE__);
+				break;
+			}
+			*buf = (__raw_readl(ss->regs + HW_SSP_DATA) & 0xFF);
+		}
+
+		count = 10000;
+		while ((__raw_readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN)
+		       && count--)
+			continue;
+		if (count <= 0) {
+			printk(KERN_ERR "%c: timeout on line %s:%d\n",
+			       write ? 'W' : 'C', __func__, __LINE__);
+			break;
+		}
+
+		/* advance to the next byte */
+		buf++;
+	}
+	return len < 0 ? 0 : -ETIMEDOUT;
+}
+
+static int mxs_spi_handle_message(struct mxs_spi *ss, struct spi_message *m)
+{
+	int first, last;
+	struct spi_transfer *t, *tmp_t;
+	int status = 0;
+	int cs;
+
+	first = last = 0;
+
+	cs = m->spi->chip_select;
+
+	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
+
+		mxs_spi_setup_transfer(m->spi, t);
+
+		if (&t->transfer_list == m->transfers.next)
+			first = !0;
+		if (&t->transfer_list == m->transfers.prev)
+			last = !0;
+		if (t->rx_buf && t->tx_buf) {
+			pr_debug("%s: cannot send and receive simultaneously\n",
+				 __func__);
+			return -EINVAL;
+		}
+
+		/*
+		   REVISIT:
+		   here driver completely ignores setting of t->cs_change
+		 */
+		if (t->tx_buf) {
+			status = pio ?
+			    mxs_spi_txrx_pio(ss, cs, (void *)t->tx_buf,
+					     t->len, &first, &last, 1) :
+			    mxs_spi_txrx_dma(ss, cs, (void *)t->tx_buf,
+					     t->tx_dma, t->len, &first, &last,
+					     1);
+			if (debug) {
+				if (t->len < 0x10)
+					print_hex_dump_bytes("Tx ",
+							     DUMP_PREFIX_OFFSET,
+							     t->tx_buf, t->len);
+				else
+					pr_debug("Tx: %d bytes\n", t->len);
+			}
+		}
+		if (t->rx_buf) {
+			status = pio ?
+			    mxs_spi_txrx_pio(ss, cs, t->rx_buf,
+					     t->len, &first, &last, 0) :
+			    mxs_spi_txrx_dma(ss, cs, t->rx_buf,
+					     t->rx_dma, t->len, &first, &last,
+					     0);
+			if (debug) {
+				if (t->len < 0x10)
+					print_hex_dump_bytes("Rx ",
+							     DUMP_PREFIX_OFFSET,
+							     t->rx_buf, t->len);
+				else
+					pr_debug("Rx: %d bytes\n", t->len);
+			}
+		}
+
+		if (status)
+			break;
+
+		first = last = 0;
+
+	}
+	return status;
+}
+
+/**
+ * mxs_spi_handle
+ *
+ * The workhorse of the driver - it handles messages from the list
+ *
+ **/
+static void mxs_spi_handle(struct work_struct *w)
+{
+	struct mxs_spi *ss = container_of(w, struct mxs_spi, work);
+	unsigned long flags;
+	struct spi_message *m;
+
+	BUG_ON(w == NULL);
+
+	spin_lock_irqsave(&ss->lock, flags);
+	while (!list_empty(&ss->queue)) {
+		m = list_entry(ss->queue.next, struct spi_message, queue);
+		list_del_init(&m->queue);
+		spin_unlock_irqrestore(&ss->lock, flags);
+
+		m->status = mxs_spi_handle_message(ss, m);
+		if (m->complete)
+			m->complete(m->context);
+
+		spin_lock_irqsave(&ss->lock, flags);
+	}
+	spin_unlock_irqrestore(&ss->lock, flags);
+
+	return;
+}
+
+/**
+ * mxs_spi_transfer
+ *
+ * Called indirectly from spi_async, queues all the messages to
+ * spi_handle_message
+ *
+ * @spi: spi device
+ * @m: message to be queued
+**/
+static int mxs_spi_transfer(struct spi_device *spi, struct spi_message *m)
+{
+	struct mxs_spi *ss = spi_master_get_devdata(spi->master);
+	unsigned long flags;
+
+	m->status = -EINPROGRESS;
+	spin_lock_irqsave(&ss->lock, flags);
+	list_add_tail(&m->queue, &ss->queue);
+	queue_work(ss->workqueue, &ss->work);
+	spin_unlock_irqrestore(&ss->lock, flags);
+	return 0;
+}
+
+static irqreturn_t mxs_spi_irq_dma(int irq, void *dev_id)
+{
+	struct mxs_spi *ss = dev_id;
+
+	mxs_dma_ack_irq(ss->dma);
+	mxs_dma_cooked(ss->dma, NULL);
+	complete(&ss->done);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mxs_spi_irq_err(int irq, void *dev_id)
+{
+	struct mxs_spi *ss = dev_id;
+	u32 c1, st;
+
+	c1 = __raw_readl(ss->regs + HW_SSP_CTRL1);
+	st = __raw_readl(ss->regs + HW_SSP_STATUS);
+	printk(KERN_ERR "IRQ - ERROR!, status = 0x%08X, c1 = 0x%08X\n", st, c1);
+	__raw_writel(c1 & 0xCCCC0000, ss->regs + HW_SSP_CTRL1_CLR);
+
+	return IRQ_HANDLED;
+}
+
+static int __init mxs_spi_probe(struct platform_device *dev)
+{
+	int err = 0;
+	struct spi_master *master;
+	struct mxs_spi *ss;
+	struct resource *r;
+	u32 mem;
+
+	/* Get resources(memory, IRQ) associated with the device */
+	master = spi_alloc_master(&dev->dev, sizeof(struct mxs_spi));
+
+	if (master == NULL) {
+		err = -ENOMEM;
+		goto out0;
+	}
+
+	platform_set_drvdata(dev, master);
+
+	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
+	if (r == NULL) {
+		err = -ENODEV;
+		goto out_put_master;
+	}
+
+	ss = spi_master_get_devdata(master);
+	ss->master_dev = &dev->dev;
+
+	INIT_WORK(&ss->work, mxs_spi_handle);
+	INIT_LIST_HEAD(&ss->queue);
+	spin_lock_init(&ss->lock);
+	ss->workqueue = create_singlethread_workqueue(dev_name(&dev->dev));
+	master->transfer = mxs_spi_transfer;
+	master->setup = mxs_spi_setup;
+	master->cleanup = mxs_spi_cleanup;
+
+	if (!request_mem_region(r->start,
+				resource_size(r), dev_name(&dev->dev))) {
+		err = -ENXIO;
+		goto out_put_master;
+	}
+	mem = r->start;
+
+	ss->regs = IO_ADDRESS(r->start);
+
+	ss->irq_dma = platform_get_irq(dev, 0);
+	if (ss->irq_dma < 0) {
+		err = -ENXIO;
+		goto out_put_master;
+	}
+	ss->irq_err = platform_get_irq(dev, 1);
+	if (ss->irq_err < 0) {
+		err = -ENXIO;
+		goto out_put_master;
+	}
+
+	r = platform_get_resource(dev, IORESOURCE_DMA, 0);
+	if (r == NULL) {
+		err = -ENODEV;
+		goto out_put_master;
+	}
+
+	ss->dma = r->start;
+	err = mxs_dma_request(ss->dma, &dev->dev, (char *)dev_name(&dev->dev));
+	if (err)
+		goto out_put_master;
+
+	ss->pdesc = mxs_dma_alloc_desc();
+	if (ss->pdesc == NULL || IS_ERR(ss->pdesc)) {
+		err = -ENOMEM;
+		goto out_free_dma;
+	}
+
+	master->bus_num = dev->id + 1;
+	master->num_chipselect = 1;
+
+	/* SPI controller initializations */
+	err = mxs_spi_init_hw(ss);
+	if (err) {
+		dev_dbg(&dev->dev, "cannot initialize hardware\n");
+		goto out_free_dma_desc;
+	}
+
+	clk_set_rate(ss->clk, 120 * 1000 * 1000);
+	ss->speed_khz = clk_get_rate(ss->clk) / 1000;
+	ss->divider = 2;
+	dev_info(&dev->dev, "Max possible speed %d = %ld/%d kHz\n",
+		 ss->speed_khz, clk_get_rate(ss->clk), ss->divider);
+
+	/* Register for SPI Interrupt */
+	err = request_irq(ss->irq_dma, mxs_spi_irq_dma, 0,
+			  dev_name(&dev->dev), ss);
+	if (err) {
+		dev_dbg(&dev->dev, "request_irq failed, %d\n", err);
+		goto out_release_hw;
+	}
+	err = request_irq(ss->irq_err, mxs_spi_irq_err, IRQF_SHARED,
+			  dev_name(&dev->dev), ss);
+	if (err) {
+		dev_dbg(&dev->dev, "request_irq(error) failed, %d\n", err);
+		goto out_free_irq;
+	}
+
+	err = spi_register_master(master);
+	if (err) {
+		dev_dbg(&dev->dev, "cannot register spi master, %d\n", err);
+		goto out_free_irq_2;
+	}
+	dev_info(&dev->dev, "at 0x%08X mapped to 0x%08X, irq=%d, bus %d, %s\n",
+		 mem, (u32) ss->regs, ss->irq_dma,
+		 master->bus_num, pio ? "PIO" : "DMA");
+	return 0;
+
+out_free_irq_2:
+	free_irq(ss->irq_err, ss);
+out_free_irq:
+	free_irq(ss->irq_dma, ss);
+out_free_dma_desc:
+	mxs_dma_free_desc(ss->pdesc);
+out_free_dma:
+	mxs_dma_release(ss->dma, &dev->dev);
+out_release_hw:
+	mxs_spi_release_hw(ss);
+out_put_master:
+	spi_master_put(master);
+out0:
+	return err;
+}
+
+static int __devexit mxs_spi_remove(struct platform_device *dev)
+{
+	struct mxs_spi *ss;
+	struct spi_master *master;
+
+	master = platform_get_drvdata(dev);
+	if (master == NULL)
+		goto out0;
+	ss = spi_master_get_devdata(master);
+	if (ss == NULL)
+		goto out1;
+	free_irq(ss->irq_err, ss);
+	free_irq(ss->irq_dma, ss);
+	if (ss->workqueue)
+		destroy_workqueue(ss->workqueue);
+	mxs_dma_free_desc(ss->pdesc);
+	mxs_dma_release(ss->dma, &dev->dev);
+	mxs_spi_release_hw(ss);
+	platform_set_drvdata(dev, 0);
+out1:
+	spi_master_put(master);
+out0:
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxs_spi_suspend(struct platform_device *pdev, pm_message_t pmsg)
+{
+	struct mxs_spi *ss;
+	struct spi_master *master;
+
+	master = platform_get_drvdata(pdev);
+	ss = spi_master_get_devdata(master);
+
+	ss->saved_timings = __raw_readl(ss->regs + HW_SSP_TIMING);
+	clk_disable(ss->clk);
+
+	return 0;
+}
+
+static int mxs_spi_resume(struct platform_device *pdev)
+{
+	struct mxs_spi *ss;
+	struct spi_master *master;
+
+	master = platform_get_drvdata(pdev);
+	ss = spi_master_get_devdata(master);
+
+	clk_enable(ss->clk);
+	__raw_writel(BM_SSP_CTRL0_SFTRST | BM_SSP_CTRL0_CLKGATE,
+		     ss->regs + HW_SSP_CTRL0_CLR);
+	__raw_writel(ss->saved_timings, ss->regs + HW_SSP_TIMING);
+
+	return 0;
+}
+
+#else
+#define mxs_spi_suspend NULL
+#define mxs_spi_resume  NULL
+#endif
+
+static struct platform_driver mxs_spi_driver = {
+	.probe = mxs_spi_probe,
+	.remove = __devexit_p(mxs_spi_remove),
+	.driver = {
+		   .name = "mxs-spi",
+		   .owner = THIS_MODULE,
+		   },
+	.suspend = mxs_spi_suspend,
+	.resume = mxs_spi_resume,
+};
+
+static int __init mxs_spi_init(void)
+{
+	return platform_driver_register(&mxs_spi_driver);
+}
+
+static void __exit mxs_spi_exit(void)
+{
+	platform_driver_unregister(&mxs_spi_driver);
+}
+
+module_init(mxs_spi_init);
+module_exit(mxs_spi_exit);
+module_param(pio, int, S_IRUGO);
+module_param(debug, int, S_IRUGO);
+MODULE_AUTHOR("dmitry pervushin <dimka@embeddedalley.com>");
+MODULE_DESCRIPTION("MXS SPI/SSP");
+MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi_mxs.h b/drivers/spi/spi_mxs.h
new file mode 100644
index 000000000000..ba605bf3b56e
--- /dev/null
+++ b/drivers/spi/spi_mxs.h
@@ -0,0 +1,52 @@
+/*
+ * Freescale MXS SPI master driver
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __SPI_STMP_H
+#define __SPI_STMP_H
+
+#include <mach/dma.h>
+
+struct mxs_spi {
+	void __iomem *regs;	/* vaddr of the control registers */
+
+	u32 irq_dma;
+	u32 irq_err;
+	u32 dma;
+	struct mxs_dma_desc *pdesc;
+
+	u32 speed_khz;
+	u32 saved_timings;
+	u32 divider;
+
+	struct clk *clk;
+	struct device *master_dev;
+
+	struct work_struct work;
+	struct workqueue_struct *workqueue;
+	spinlock_t lock;
+	struct list_head queue;
+
+	struct completion done;
+};
+
+#endif /* __SPI_STMP_H */
diff --git a/drivers/ssb/sprom.c b/drivers/ssb/sprom.c
index 8943015a3eef..eb708431cb96 100644
--- a/drivers/ssb/sprom.c
+++ b/drivers/ssb/sprom.c
@@ -13,6 +13,8 @@
 
 #include "ssb_private.h"
 
+#include <linux/ctype.h>
+
 
 static const struct ssb_sprom *fallback_sprom;
 
@@ -33,17 +35,27 @@ static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
 static int hex2sprom(u16 *sprom, const char *dump, size_t len,
 		     size_t sprom_size_words)
 {
-	char tmp[5] = { 0 };
-	int cnt = 0;
+	char c, tmp[5] = { 0 };
+	int err, cnt = 0;
 	unsigned long parsed;
 
-	if (len < sprom_size_words * 2)
+	/* Strip whitespace at the end. */
+	while (len) {
+		c = dump[len - 1];
+		if (!isspace(c) && c != '\0')
+			break;
+		len--;
+	}
+	/* Length must match exactly. */
+	if (len != sprom_size_words * 4)
 		return -EINVAL;
 
 	while (cnt < sprom_size_words) {
 		memcpy(tmp, dump, 4);
 		dump += 4;
-		parsed = simple_strtoul(tmp, NULL, 16);
+		err = strict_strtoul(tmp, 16, &parsed);
+		if (err)
+			return err;
 		sprom[cnt++] = swab16((u16)parsed);
 	}
 
diff --git a/drivers/staging/android/lowmemorykiller.c b/drivers/staging/android/lowmemorykiller.c
index 803b891dc85e..ae41f79d995d 100644
--- a/drivers/staging/android/lowmemorykiller.c
+++ b/drivers/staging/android/lowmemorykiller.c
@@ -18,6 +18,8 @@
 #include <linux/mm.h>
 #include <linux/oom.h>
 #include <linux/sched.h>
+#include <linux/nodemask.h>
+#include <linux/vmstat.h>
 
 static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask);
 
@@ -67,6 +69,15 @@ static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask)
 	int array_size = ARRAY_SIZE(lowmem_adj);
 	int other_free = global_page_state(NR_FREE_PAGES);
 	int other_file = global_page_state(NR_FILE_PAGES);
+	int node;
+
+	for_each_node_state(node, N_HIGH_MEMORY) {
+		struct zone *z =
+			&NODE_DATA(node)->node_zones[ZONE_DMA];
+
+		other_free -= zone_page_state(z, NR_FREE_PAGES);
+		other_file -= zone_page_state(z, NR_FILE_PAGES);
+	}
 
 	if (lowmem_adj_size < array_size)
 		array_size = lowmem_adj_size;
diff --git a/drivers/staging/dst/dcore.c b/drivers/staging/dst/dcore.c
index fad25b753042..5546898dbdb4 100644
--- a/drivers/staging/dst/dcore.c
+++ b/drivers/staging/dst/dcore.c
@@ -846,15 +846,19 @@ static dst_command_func dst_commands[] = {
 /*
  * Configuration parser.
  */
-static void cn_dst_callback(void *data)
+static void cn_dst_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp)
 {
 	struct dst_ctl *ctl;
-	struct cn_msg *msg = data;
 	int err;
 	struct dst_ctl_ack ack;
 	struct dst_node *n = NULL, *tmp;
 	unsigned int hash;
 
+	if (!cap_raised(nsp->eff_cap, CAP_SYS_ADMIN)) {
+		err = -EPERM;
+		goto out;
+	}
+
 	if (msg->len < sizeof(struct dst_ctl)) {
 		err = -EBADMSG;
 		goto out;
diff --git a/drivers/staging/pohmelfs/config.c b/drivers/staging/pohmelfs/config.c
index a6eaa42fb669..d8ec47a6ee06 100644
--- a/drivers/staging/pohmelfs/config.c
+++ b/drivers/staging/pohmelfs/config.c
@@ -446,11 +446,13 @@ out_unlock:
 	return err;
 }
 
-static void pohmelfs_cn_callback(void *data)
+static void pohmelfs_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp)
 {
-	struct cn_msg *msg = data;
 	int err;
 
+	if (!cap_raised(nsp->eff_cap, CAP_SYS_ADMIN))
+		return;
+
 	switch (msg->flags) {
 		case POHMELFS_FLAGS_ADD:
 		case POHMELFS_FLAGS_DEL:
diff --git a/drivers/staging/rt2860/common/cmm_data_2860.c b/drivers/staging/rt2860/common/cmm_data_2860.c
index fb1735533b74..857ff450b6c9 100644
--- a/drivers/staging/rt2860/common/cmm_data_2860.c
+++ b/drivers/staging/rt2860/common/cmm_data_2860.c
@@ -363,6 +363,8 @@ int RtmpPCIMgmtKickOut(
 	ULONG			SwIdx = pAd->MgmtRing.TxCpuIdx;
 
 	pTxD  = (PTXD_STRUC) pAd->MgmtRing.Cell[SwIdx].AllocVa;
+	if (!pTxD)
+		return 0;
 
 	pAd->MgmtRing.Cell[SwIdx].pNdisPacket = pPacket;
 	pAd->MgmtRing.Cell[SwIdx].pNextNdisPacket = NULL;
diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
index 2bfc41ece0e1..b72fa49eb257 100644
--- a/drivers/usb/class/cdc-acm.c
+++ b/drivers/usb/class/cdc-acm.c
@@ -59,6 +59,7 @@
 #include <linux/init.h>
 #include <linux/slab.h>
 #include <linux/tty.h>
+#include <linux/serial.h>
 #include <linux/tty_driver.h>
 #include <linux/tty_flip.h>
 #include <linux/module.h>
@@ -608,8 +609,9 @@ static int acm_tty_open(struct tty_struct *tty, struct file *filp)
 
 	acm->throttle = 0;
 
-	tasklet_schedule(&acm->urb_task);
+	set_bit(ASYNCB_INITIALIZED, &acm->port.flags);
 	rv = tty_port_block_til_ready(&acm->port, tty, filp);
+	tasklet_schedule(&acm->urb_task);
 done:
 	mutex_unlock(&acm->mutex);
 err_out:
@@ -858,10 +860,7 @@ static void acm_tty_set_termios(struct tty_struct *tty,
 	if (!ACM_READY(acm))
 		return;
 
-	/* FIXME: Needs to support the tty_baud interface */
-	/* FIXME: Broken on sparc */
-	newline.dwDTERate = cpu_to_le32p(acm_tty_speed +
-		(termios->c_cflag & CBAUD & ~CBAUDEX) + (termios->c_cflag & CBAUDEX ? 15 : 0));
+	newline.dwDTERate = cpu_to_le32(tty_get_baud_rate(tty));
 	newline.bCharFormat = termios->c_cflag & CSTOPB ? 2 : 0;
 	newline.bParityType = termios->c_cflag & PARENB ?
 				(termios->c_cflag & PARODD ? 1 : 2) +
diff --git a/drivers/usb/class/cdc-wdm.c b/drivers/usb/class/cdc-wdm.c
index ba589d4ca8bc..a9c33994459b 100644
--- a/drivers/usb/class/cdc-wdm.c
+++ b/drivers/usb/class/cdc-wdm.c
@@ -313,8 +313,13 @@ static ssize_t wdm_write
 	r = usb_autopm_get_interface(desc->intf);
 	if (r < 0)
 		goto outnp;
-	r = wait_event_interruptible(desc->wait, !test_bit(WDM_IN_USE,
-							   &desc->flags));
+
+	if (!file->f_flags && O_NONBLOCK)
+		r = wait_event_interruptible(desc->wait, !test_bit(WDM_IN_USE,
+								&desc->flags));
+	else
+		if (test_bit(WDM_IN_USE, &desc->flags))
+			r = -EAGAIN;
 	if (r < 0)
 		goto out;
 
@@ -377,7 +382,7 @@ outnl:
 static ssize_t wdm_read
 (struct file *file, char __user *buffer, size_t count, loff_t *ppos)
 {
-	int rv, cntr;
+	int rv, cntr = 0;
 	int i = 0;
 	struct wdm_device *desc = file->private_data;
 
@@ -389,10 +394,23 @@ static ssize_t wdm_read
 	if (desc->length == 0) {
 		desc->read = 0;
 retry:
+		if (test_bit(WDM_DISCONNECTING, &desc->flags)) {
+			rv = -ENODEV;
+			goto err;
+		}
 		i++;
-		rv = wait_event_interruptible(desc->wait,
-					      test_bit(WDM_READ, &desc->flags));
+		if (file->f_flags & O_NONBLOCK) {
+			if (!test_bit(WDM_READ, &desc->flags)) {
+				rv = cntr ? cntr : -EAGAIN;
+				goto err;
+			}
+			rv = 0;
+		} else {
+			rv = wait_event_interruptible(desc->wait,
+				test_bit(WDM_READ, &desc->flags));
+		}
 
+		/* may have happened while we slept */
 		if (test_bit(WDM_DISCONNECTING, &desc->flags)) {
 			rv = -ENODEV;
 			goto err;
@@ -448,7 +466,7 @@ retry:
 
 err:
 	mutex_unlock(&desc->rlock);
-	if (rv < 0)
+	if (rv < 0 && rv != -EAGAIN)
 		dev_err(&desc->intf->dev, "wdm_read: exit error\n");
 	return rv;
 }
diff --git a/drivers/usb/class/usbtmc.c b/drivers/usb/class/usbtmc.c
index b09a527f7341..aa145f7b4e25 100644
--- a/drivers/usb/class/usbtmc.c
+++ b/drivers/usb/class/usbtmc.c
@@ -367,13 +367,13 @@ static ssize_t usbtmc_read(struct file *filp, char __user *buf,
 {
 	struct usbtmc_device_data *data;
 	struct device *dev;
-	unsigned long int n_characters;
+	u32 n_characters;
 	u8 *buffer;
 	int actual;
-	int done;
-	int remaining;
+	size_t done;
+	size_t remaining;
 	int retval;
-	int this_part;
+	size_t this_part;
 
 	/* Get pointer to private data structure */
 	data = filp->private_data;
@@ -455,6 +455,18 @@ static ssize_t usbtmc_read(struct file *filp, char __user *buf,
 			       (buffer[6] << 16) +
 			       (buffer[7] << 24);
 
+		/* Ensure the instrument doesn't lie about it */
+		if(n_characters > actual - 12) {
+			dev_err(dev, "Device lies about message size: %zu > %zu\n", n_characters, actual - 12);
+			n_characters = actual - 12;
+		}
+
+		/* Ensure the instrument doesn't send more back than requested */
+		if(n_characters > this_part) {
+			dev_err(dev, "Device returns more than requested: %zu > %zu\n", done + n_characters, done + this_part);
+			n_characters = this_part;
+		}
+
 		/* Copy buffer to user space */
 		if (copy_to_user(buf + done, &buffer[12], n_characters)) {
 			/* There must have been an addressing problem */
@@ -465,6 +477,8 @@ static ssize_t usbtmc_read(struct file *filp, char __user *buf,
 		done += n_characters;
 		if (n_characters < USBTMC_SIZE_IOBUFFER)
 			remaining = 0;
+		else
+			remaining -= n_characters;
 	}
 
 	/* Update file position value */
@@ -531,10 +545,16 @@ static ssize_t usbtmc_write(struct file *filp, const char __user *buf,
 		n_bytes = roundup(12 + this_part, 4);
 		memset(buffer + 12 + this_part, 0, n_bytes - (12 + this_part));
 
-		retval = usb_bulk_msg(data->usb_dev,
-				      usb_sndbulkpipe(data->usb_dev,
-						      data->bulk_out),
-				      buffer, n_bytes, &actual, USBTMC_TIMEOUT);
+		do {
+			retval = usb_bulk_msg(data->usb_dev,
+					      usb_sndbulkpipe(data->usb_dev,
+							      data->bulk_out),
+					      buffer, n_bytes,
+					      &actual, USBTMC_TIMEOUT);
+			if (retval != 0)
+				break;
+			n_bytes -= actual;
+		} while (n_bytes);
 
 		data->bTag_last_write = data->bTag;
 		data->bTag++;
diff --git a/drivers/usb/core/config.c b/drivers/usb/core/config.c
index a16c538d0132..0d3af6a6ee49 100644
--- a/drivers/usb/core/config.c
+++ b/drivers/usb/core/config.c
@@ -105,7 +105,7 @@ static int usb_parse_ss_endpoint_companion(struct device *ddev, int cfgno,
 	ep->ss_ep_comp->extralen = i;
 	buffer += i;
 	size -= i;
-	retval = buffer - buffer_start + i;
+	retval = buffer - buffer_start;
 	if (num_skipped > 0)
 		dev_dbg(ddev, "skipped %d descriptor%s after %s\n",
 				num_skipped, plural(num_skipped),
diff --git a/drivers/usb/core/devices.c b/drivers/usb/core/devices.c
index 96f11715cd26..355dffcc23b0 100644
--- a/drivers/usb/core/devices.c
+++ b/drivers/usb/core/devices.c
@@ -494,7 +494,7 @@ static ssize_t usb_device_dump(char __user **buffer, size_t *nbytes,
 		return 0;
 	/* allocate 2^1 pages = 8K (on i386);
 	 * should be more than enough for one device */
-	pages_start = (char *)__get_free_pages(GFP_KERNEL, 1);
+	pages_start = (char *)__get_free_pages(GFP_NOIO, 1);
 	if (!pages_start)
 		return -ENOMEM;
 
diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c
index 4247eccf858c..5ae4099fb4c1 100644
--- a/drivers/usb/core/devio.c
+++ b/drivers/usb/core/devio.c
@@ -1139,6 +1139,13 @@ static int proc_do_submiturb(struct dev_state *ps, struct usbdevfs_urb *uurb,
 			free_async(as);
 			return -ENOMEM;
 		}
+		/* Isochronous input data may end up being discontiguous
+		 * if some of the packets are short.  Clear the buffer so
+		 * that the gaps don't leak kernel data to userspace.
+		 */
+		if (is_in && uurb->type == USBDEVFS_URB_TYPE_ISO)
+			memset(as->urb->transfer_buffer, 0,
+					uurb->buffer_length);
 	}
 	as->urb->dev = ps->dev;
 	as->urb->pipe = (uurb->type << 30) |
@@ -1240,10 +1247,14 @@ static int processcompl(struct async *as, void __user * __user *arg)
 	void __user *addr = as->userurb;
 	unsigned int i;
 
-	if (as->userbuffer)
-		if (copy_to_user(as->userbuffer, urb->transfer_buffer,
-				 urb->transfer_buffer_length))
+	if (as->userbuffer && urb->actual_length) {
+		if (urb->number_of_packets > 0)		/* Isochronous */
+			i = urb->transfer_buffer_length;
+		else					/* Non-Isoc */
+			i = urb->actual_length;
+		if (copy_to_user(as->userbuffer, urb->transfer_buffer, i))
 			goto err_out;
+	}
 	if (put_user(as->status, &userurb->status))
 		goto err_out;
 	if (put_user(urb->actual_length, &userurb->actual_length))
@@ -1262,14 +1273,11 @@ static int processcompl(struct async *as, void __user * __user *arg)
 		}
 	}
 
-	free_async(as);
-
 	if (put_user(addr, (void __user * __user *)arg))
 		return -EFAULT;
 	return 0;
 
 err_out:
-	free_async(as);
 	return -EFAULT;
 }
 
@@ -1299,8 +1307,11 @@ static struct async *reap_as(struct dev_state *ps)
 static int proc_reapurb(struct dev_state *ps, void __user *arg)
 {
 	struct async *as = reap_as(ps);
-	if (as)
-		return processcompl(as, (void __user * __user *)arg);
+	if (as) {
+		int retval = processcompl(as, (void __user * __user *)arg);
+		free_async(as);
+		return retval;
+	}
 	if (signal_pending(current))
 		return -EINTR;
 	return -EIO;
@@ -1308,11 +1319,16 @@ static int proc_reapurb(struct dev_state *ps, void __user *arg)
 
 static int proc_reapurbnonblock(struct dev_state *ps, void __user *arg)
 {
+	int retval;
 	struct async *as;
 
-	if (!(as = async_getcompleted(ps)))
-		return -EAGAIN;
-	return processcompl(as, (void __user * __user *)arg);
+	as = async_getcompleted(ps);
+	retval = -EAGAIN;
+	if (as) {
+		retval = processcompl(as, (void __user * __user *)arg);
+		free_async(as);
+	}
+	return retval;
 }
 
 #ifdef CONFIG_COMPAT
@@ -1363,9 +1379,9 @@ static int processcompl_compat(struct async *as, void __user * __user *arg)
 	void __user *addr = as->userurb;
 	unsigned int i;
 
-	if (as->userbuffer)
+	if (as->userbuffer && urb->actual_length)
 		if (copy_to_user(as->userbuffer, urb->transfer_buffer,
-				 urb->transfer_buffer_length))
+				 urb->actual_length))
 			return -EFAULT;
 	if (put_user(as->status, &userurb->status))
 		return -EFAULT;
@@ -1385,7 +1401,6 @@ static int processcompl_compat(struct async *as, void __user * __user *arg)
 		}
 	}
 
-	free_async(as);
 	if (put_user(ptr_to_compat(addr), (u32 __user *)arg))
 		return -EFAULT;
 	return 0;
@@ -1394,8 +1409,11 @@ static int processcompl_compat(struct async *as, void __user * __user *arg)
 static int proc_reapurb_compat(struct dev_state *ps, void __user *arg)
 {
 	struct async *as = reap_as(ps);
-	if (as)
-		return processcompl_compat(as, (void __user * __user *)arg);
+	if (as) {
+		int retval = processcompl_compat(as, (void __user * __user *)arg);
+		free_async(as);
+		return retval;
+	}
 	if (signal_pending(current))
 		return -EINTR;
 	return -EIO;
@@ -1403,11 +1421,16 @@ static int proc_reapurb_compat(struct dev_state *ps, void __user *arg)
 
 static int proc_reapurbnonblock_compat(struct dev_state *ps, void __user *arg)
 {
+	int retval;
 	struct async *as;
 
-	if (!(as = async_getcompleted(ps)))
-		return -EAGAIN;
-	return processcompl_compat(as, (void __user * __user *)arg);
+	retval = -EAGAIN;
+	as = async_getcompleted(ps);
+	if (as) {
+		retval = processcompl_compat(as, (void __user * __user *)arg);
+		free_async(as);
+	}
+	return retval;
 }
 
 #endif
diff --git a/drivers/usb/core/driver.c b/drivers/usb/core/driver.c
index 69e5773abfce..c209dbe4f6c6 100644
--- a/drivers/usb/core/driver.c
+++ b/drivers/usb/core/driver.c
@@ -1765,7 +1765,7 @@ int usb_resume(struct device *dev, pm_message_t msg)
 	/* Avoid PM error messages for devices disconnected while suspended
 	 * as we'll display regular disconnect messages just a bit later.
 	 */
-	if (status == -ENODEV)
+	if (status == -ENODEV || status == -ESHUTDOWN)
 		return 0;
 	return status;
 }
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index d47201c75915..3bcd08fbfb71 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -457,7 +457,7 @@ resubmit:
 static inline int
 hub_clear_tt_buffer (struct usb_device *hdev, u16 devinfo, u16 tt)
 {
-	return usb_control_msg(hdev, usb_rcvctrlpipe(hdev, 0),
+	return usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
 			       HUB_CLEAR_TT_BUFFER, USB_RT_PORT, devinfo,
 			       tt, NULL, 0, 1000);
 }
@@ -3286,6 +3286,9 @@ static void hub_events(void)
 					USB_PORT_FEAT_C_SUSPEND);
 				udev = hdev->children[i-1];
 				if (udev) {
+					/* TRSMRCY = 10 msec */
+					msleep(10);
+
 					usb_lock_device(udev);
 					ret = remote_wakeup(hdev->
 							children[i-1]);
diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c
index 9720e699f472..8c929daa71f2 100644
--- a/drivers/usb/core/message.c
+++ b/drivers/usb/core/message.c
@@ -923,11 +923,11 @@ char *usb_cache_string(struct usb_device *udev, int index)
 	if (index <= 0)
 		return NULL;
 
-	buf = kmalloc(MAX_USB_STRING_SIZE, GFP_KERNEL);
+	buf = kmalloc(MAX_USB_STRING_SIZE, GFP_NOIO);
 	if (buf) {
 		len = usb_string(udev, index, buf, MAX_USB_STRING_SIZE);
 		if (len > 0) {
-			smallbuf = kmalloc(++len, GFP_KERNEL);
+			smallbuf = kmalloc(++len, GFP_NOIO);
 			if (!smallbuf)
 				return buf;
 			memcpy(smallbuf, buf, len);
@@ -1694,7 +1694,7 @@ int usb_set_configuration(struct usb_device *dev, int configuration)
 	if (cp) {
 		nintf = cp->desc.bNumInterfaces;
 		new_interfaces = kmalloc(nintf * sizeof(*new_interfaces),
-				GFP_KERNEL);
+				GFP_NOIO);
 		if (!new_interfaces) {
 			dev_err(&dev->dev, "Out of memory\n");
 			return -ENOMEM;
@@ -1703,7 +1703,7 @@ int usb_set_configuration(struct usb_device *dev, int configuration)
 		for (; n < nintf; ++n) {
 			new_interfaces[n] = kzalloc(
 					sizeof(struct usb_interface),
-					GFP_KERNEL);
+					GFP_NOIO);
 			if (!new_interfaces[n]) {
 				dev_err(&dev->dev, "Out of memory\n");
 				ret = -ENOMEM;
diff --git a/drivers/usb/core/sysfs.c b/drivers/usb/core/sysfs.c
index b5c72e458943..7bc1469c8f0e 100644
--- a/drivers/usb/core/sysfs.c
+++ b/drivers/usb/core/sysfs.c
@@ -111,6 +111,12 @@ show_speed(struct device *dev, struct device_attribute *attr, char *buf)
 	case USB_SPEED_HIGH:
 		speed = "480";
 		break;
+	case USB_SPEED_VARIABLE:
+		speed = "480";
+		break;
+	case USB_SPEED_SUPER:
+		speed = "5000";
+		break;
 	default:
 		speed = "unknown";
 	}
diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c
index a26f73880c32..b661dbd93208 100644
--- a/drivers/usb/core/usb.c
+++ b/drivers/usb/core/usb.c
@@ -132,7 +132,7 @@ EXPORT_SYMBOL_GPL(usb_altnum_to_altsetting);
 
 struct find_interface_arg {
 	int minor;
-	struct usb_interface *interface;
+	struct device_driver *drv;
 };
 
 static int __find_interface(struct device *dev, void *data)
@@ -143,12 +143,10 @@ static int __find_interface(struct device *dev, void *data)
 	if (!is_usb_interface(dev))
 		return 0;
 
+	if (dev->driver != arg->drv)
+		return 0;
 	intf = to_usb_interface(dev);
-	if (intf->minor != -1 && intf->minor == arg->minor) {
-		arg->interface = intf;
-		return 1;
-	}
-	return 0;
+	return intf->minor == arg->minor;
 }
 
 /**
@@ -156,21 +154,24 @@ static int __find_interface(struct device *dev, void *data)
  * @drv: the driver whose current configuration is considered
  * @minor: the minor number of the desired device
  *
- * This walks the driver device list and returns a pointer to the interface
- * with the matching minor.  Note, this only works for devices that share the
- * USB major number.
+ * This walks the bus device list and returns a pointer to the interface
+ * with the matching minor and driver.  Note, this only works for devices
+ * that share the USB major number.
  */
 struct usb_interface *usb_find_interface(struct usb_driver *drv, int minor)
 {
 	struct find_interface_arg argb;
-	int retval;
+	struct device *dev;
 
 	argb.minor = minor;
-	argb.interface = NULL;
-	/* eat the error, it will be in argb.interface */
-	retval = driver_for_each_device(&drv->drvwrap.driver, NULL, &argb,
-					__find_interface);
-	return argb.interface;
+	argb.drv = &drv->drvwrap.driver;
+
+	dev = bus_find_device(&usb_bus_type, NULL, &argb, __find_interface);
+
+	/* Drop reference count from bus_find_device */
+	put_device(dev);
+
+	return dev ? to_usb_interface(dev) : NULL;
 }
 EXPORT_SYMBOL_GPL(usb_find_interface);
 
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index ce44379bd172..a19d73730470 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -466,7 +466,6 @@ config USB_GOKU
 config USB_GADGET_ARC
 	boolean "Freescale USB Device Controller"
 	depends on ARCH_MXC || ARCH_STMP3XXX || ARCH_MXS
-	depends on !USB_EHCI_ARC_OTG
 	select USB_GADGET_DUALSPEED
 	select USB_OTG_UTILS
 	select USB_GADGET_DUALSPEED if USB_GADGET_FSL_1504 || USB_GADGET_FSL_UTMI
diff --git a/drivers/usb/gadget/amd5536udc.c b/drivers/usb/gadget/amd5536udc.c
index 77352ccc245e..fb0976643a2f 100644
--- a/drivers/usb/gadget/amd5536udc.c
+++ b/drivers/usb/gadget/amd5536udc.c
@@ -1213,7 +1213,12 @@ udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
 				tmp &= AMD_UNMASK_BIT(ep->num);
 				writel(tmp, &dev->regs->ep_irqmsk);
 			}
-		}
+		} else if (ep->in) {
+				/* enable ep irq */
+				tmp = readl(&dev->regs->ep_irqmsk);
+				tmp &= AMD_UNMASK_BIT(ep->num);
+				writel(tmp, &dev->regs->ep_irqmsk);
+			}
 
 	} else if (ep->dma) {
 
@@ -2005,18 +2010,17 @@ __acquires(dev->lock)
 {
 	int tmp;
 
-	/* empty queues and init hardware */
-	udc_basic_init(dev);
-	for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
-		empty_req_queue(&dev->ep[tmp]);
-	}
-
 	if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
 		spin_unlock(&dev->lock);
 		driver->disconnect(&dev->gadget);
 		spin_lock(&dev->lock);
 	}
-	/* init */
+
+	/* empty queues and init hardware */
+	udc_basic_init(dev);
+	for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
+		empty_req_queue(&dev->ep[tmp]);
+
 	udc_setup_endpoints(dev);
 }
 
@@ -2478,6 +2482,13 @@ static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
 				}
 			}
 
+		} else if (!use_dma && ep->in) {
+			/* disable interrupt */
+			tmp = readl(
+				&dev->regs->ep_irqmsk);
+			tmp |= AMD_BIT(ep->num);
+			writel(tmp,
+				&dev->regs->ep_irqmsk);
 		}
 	}
 	/* clear status bits */
@@ -3285,6 +3296,17 @@ static int udc_pci_probe(
 		goto finished;
 	}
 
+	spin_lock_init(&dev->lock);
+	/* udc csr registers base */
+	dev->csr = dev->virt_addr + UDC_CSR_ADDR;
+	/* dev registers base */
+	dev->regs = dev->virt_addr + UDC_DEVCFG_ADDR;
+	/* ep registers base */
+	dev->ep_regs = dev->virt_addr + UDC_EPREGS_ADDR;
+	/* fifo's base */
+	dev->rxfifo = (u32 __iomem *)(dev->virt_addr + UDC_RXFIFO_ADDR);
+	dev->txfifo = (u32 __iomem *)(dev->virt_addr + UDC_TXFIFO_ADDR);
+
 	if (request_irq(pdev->irq, udc_irq, IRQF_SHARED, name, dev) != 0) {
 		dev_dbg(&dev->pdev->dev, "request_irq(%d) fail\n", pdev->irq);
 		kfree(dev);
@@ -3337,7 +3359,6 @@ static int udc_probe(struct udc *dev)
 	udc_pollstall_timer.data = 0;
 
 	/* device struct setup */
-	spin_lock_init(&dev->lock);
 	dev->gadget.ops = &udc_ops;
 
 	dev_set_name(&dev->gadget.dev, "gadget");
@@ -3346,16 +3367,6 @@ static int udc_probe(struct udc *dev)
 	dev->gadget.name = name;
 	dev->gadget.is_dualspeed = 1;
 
-	/* udc csr registers base */
-	dev->csr = dev->virt_addr + UDC_CSR_ADDR;
-	/* dev registers base */
-	dev->regs = dev->virt_addr + UDC_DEVCFG_ADDR;
-	/* ep registers base */
-	dev->ep_regs = dev->virt_addr + UDC_EPREGS_ADDR;
-	/* fifo's base */
-	dev->rxfifo = (u32 __iomem *)(dev->virt_addr + UDC_RXFIFO_ADDR);
-	dev->txfifo = (u32 __iomem *)(dev->virt_addr + UDC_TXFIFO_ADDR);
-
 	/* init registers, interrupts, ... */
 	startup_registers(dev);
 
diff --git a/drivers/usb/gadget/arcotg_udc.c b/drivers/usb/gadget/arcotg_udc.c
index 1577c93c35bb..abba4d2ae8d4 100644
--- a/drivers/usb/gadget/arcotg_udc.c
+++ b/drivers/usb/gadget/arcotg_udc.c
@@ -177,6 +177,25 @@ static inline void dump_ep_queue(struct fsl_ep *ep)
 }
 #endif
 
+#if (defined CONFIG_ARCH_MX35 || defined CONFIG_ARCH_MX25)
+/*
+ * The Phy at MX35 and MX25 have bugs, it must disable, and re-eable phy
+ * if the phy clock is disabled before
+ */
+static void reset_phy(void)
+{
+	u32 phyctrl;
+	phyctrl = fsl_readl(&dr_regs->phyctrl1);
+	phyctrl &= ~PHY_CTRL0_USBEN;
+	fsl_writel(phyctrl, &dr_regs->phyctrl1);
+
+	phyctrl = fsl_readl(&dr_regs->phyctrl1);
+	phyctrl |= PHY_CTRL0_USBEN;
+	fsl_writel(phyctrl, &dr_regs->phyctrl1);
+}
+#else
+static void reset_phy(void){; }
+#endif
 /*-----------------------------------------------------------------
  * done() - retire a request; caller blocked irqs
  * @status : request status to be set, only works when
@@ -300,6 +319,8 @@ static void dr_phy_low_power_mode(struct fsl_udc *udc, bool enable)
 		if (udc_controller->pdata->usb_clock_for_pm)
 			udc_controller->pdata->usb_clock_for_pm(true);
 
+		/* Due to mx35/mx25's phy's bug */
+		reset_phy();
 		temp = fsl_readl(&dr_regs->portsc1);
 		temp &= ~PORTSCX_PHY_LOW_POWER_SPD;
 		fsl_writel(temp, &dr_regs->portsc1);
@@ -445,12 +466,14 @@ static void dr_controller_run(struct fsl_udc *udc)
 		dr_phy_low_power_mode(udc, true);
 		printk(KERN_INFO "udc enter low power mode \n");
 	} else {
+#ifdef CONFIG_ARCH_MX37
 		/*
 		 add some delay for USB timing issue. USB may be
 		 recognize as FS device
 		 during USB gadget remote wake up function
 		*/
 		mdelay(100);
+#endif
 		/* Clear stopped bit */
 		udc->stopped = 0;
 		/* Set controller to Run */
@@ -680,7 +703,7 @@ static int fsl_ep_enable(struct usb_ep *_ep,
 	case USB_ENDPOINT_XFER_ISOC:
 		/* Calculate transactions needed for high bandwidth iso */
 		mult = (unsigned char)(1 + ((max >> 11) & 0x03));
-		max = max & 0x8ff;	/* bit 0~10 */
+		max = max & 0x7ff;	/* bit 0~10 */
 		/* 3 transactions at most */
 		if (mult > 3)
 			goto en_done;
@@ -2018,29 +2041,12 @@ static void reset_irq(struct fsl_udc *udc)
 	/* Write 1s to the flush register */
 	fsl_writel(0xffffffff, &dr_regs->endptflush);
 
-	if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
-		VDBG("Bus reset");
-		/* Bus is reseting */
-		udc->bus_reset = 1;
-		/* Reset all the queues, include XD, dTD, EP queue
-		 * head and TR Queue */
-		reset_queues(udc);
-		udc->usb_state = USB_STATE_DEFAULT;
-	} else {
-		VDBG("Controller reset");
-		/* initialize usb hw reg except for regs for EP, not
-		 * touch usbintr reg */
-		dr_controller_setup(udc);
-
-		/* Reset all internal used Queues */
-		reset_queues(udc);
-
-		ep0_setup(udc);
-
-		/* Enable DR IRQ reg, Set Run bit, change udc state */
-		dr_controller_run(udc);
-		udc->usb_state = USB_STATE_ATTACHED;
-	}
+	/* Bus is reseting */
+	udc->bus_reset = 1;
+	/* Reset all the queues, include XD, dTD, EP queue
+	 * head and TR Queue */
+	reset_queues(udc);
+	udc->usb_state = USB_STATE_DEFAULT;
 }
 
 /* if wakup udc, return true; else return false*/
@@ -2176,9 +2182,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
 {
 	int retval = -ENODEV;
 	unsigned long flags = 0;
-#ifndef CONFIG_USB_OTG
 	u32 portsc;
-#endif
 
 	if (!udc_controller)
 		return -ENODEV;
@@ -2200,14 +2204,14 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
 	udc_controller->driver = driver;
 	udc_controller->gadget.dev.driver = &driver->driver;
 	spin_unlock_irqrestore(&udc_controller->lock, flags);
-#ifndef CONFIG_USB_OTG
+
 	if (udc_controller->pdata->usb_clock_for_pm)
 		udc_controller->pdata->usb_clock_for_pm(true);
 
 	portsc = fsl_readl(&dr_regs->portsc1);
 	portsc &= ~PORTSCX_PHY_LOW_POWER_SPD;
 	fsl_writel(portsc, &dr_regs->portsc1);
-#endif
+
 	/* bind udc driver to gadget driver */
 	retval = driver->bind(&udc_controller->gadget);
 	if (retval) {
@@ -2705,14 +2709,6 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
 	int ret = -ENODEV;
 	unsigned int i;
 	u32 dccparams;
-#ifndef CONFIG_USB_OTG
-	u32 portsc;
-#endif
-
-	if (strcmp(pdev->name, driver_name)) {
-		VDBG("Wrong device\n");
-		return -ENODEV;
-	}
 
 	udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
 	if (udc_controller == NULL) {
@@ -2768,6 +2764,9 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
 		goto err2a;
 	}
 
+	/* Due to mx35/mx25's phy's bug */
+	reset_phy();
+
 	if (pdata->have_sysif_regs)
 		usb_sys_regs = (struct usb_sys_interface *)
 				((u32)dr_regs + USB_DR_SYS_OFFSET);
@@ -2881,10 +2880,14 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
 	dr_wake_up_enable(udc_controller, false);
 	udc_controller->stopped = 1;
 
+#if !(defined CONFIG_ARCH_MX35 || defined CONFIG_ARCH_MX25)
+{
+	u32 portsc;
 	portsc = fsl_readl(&dr_regs->portsc1);
 	portsc |= PORTSCX_PHY_LOW_POWER_SPD;
 	fsl_writel(portsc, &dr_regs->portsc1);
-
+}
+#endif
 	if (udc_controller->pdata->usb_clock_for_pm)
 		udc_controller->pdata->usb_clock_for_pm(false);
 #endif
diff --git a/drivers/usb/gadget/arcotg_udc.h b/drivers/usb/gadget/arcotg_udc.h
index 480d953dcf58..4574954bf4f4 100644
--- a/drivers/usb/gadget/arcotg_udc.h
+++ b/drivers/usb/gadget/arcotg_udc.h
@@ -365,6 +365,7 @@ struct usb_sys_interface {
 
 /* PHY control0 Register Bit Masks */
 #define	PHY_CTRL0_CONF2			(1 << 26)
+#define PHY_CTRL0_USBEN			(1 << 24) /* USB UTMI PHY Enable */
 
 /* USB UH2 CTRL Register Bits */
 #define USB_UH2_OVBWK_EN		(1 << 6) /* OTG VBUS Wakeup Enable */
diff --git a/drivers/usb/gadget/fsl_updater.c b/drivers/usb/gadget/fsl_updater.c
index 8b4b54f8cca7..50acce441a90 100644
--- a/drivers/usb/gadget/fsl_updater.c
+++ b/drivers/usb/gadget/fsl_updater.c
@@ -29,6 +29,7 @@ static int utp_init(struct fsg_dev *fsg)
 	INIT_LIST_HEAD(&utp_context.write);
 	mutex_init(&utp_context.lock);
 
+	/* the max message is 64KB */
 	utp_context.buffer = vmalloc(0x10000);
 	if (!utp_context.buffer)
 		return -EIO;
@@ -63,6 +64,7 @@ static void utp_user_data_free(struct utp_user_data *uud)
 	kfree(uud);
 }
 
+/* Get the number of element for list */
 static u32 count_list(struct list_head *l)
 {
 	u32 count = 0;
@@ -74,10 +76,11 @@ static u32 count_list(struct list_head *l)
 
 	return count;
 }
-
+/* The routine will not go on if utp_context.queue is empty */
 #define WAIT_ACTIVITY(queue) \
  wait_event_interruptible(utp_context.wq, !list_empty(&utp_context.queue))
 
+/* Called by userspace program (uuc) */
 static ssize_t utp_file_read(struct file *file,
 			     char __user *buf,
 			     size_t size,
@@ -109,12 +112,15 @@ static ssize_t utp_file_read(struct file *file,
 			"need to put %d\n", size, size_to_put);
 	}
 
+	/*
+	 * The user program has already finished data process,
+	 * go on getting data from the host
+	 */
 	wake_up(&utp_context.list_full_wq);
 
 	return size_to_put;
 }
 
-
 static ssize_t utp_file_write(struct file *file, const char __user *buf,
 				size_t size, loff_t *off)
 {
@@ -127,11 +133,13 @@ static ssize_t utp_file_write(struct file *file, const char __user *buf,
 		return -EACCES;
 	mutex_lock(&utp_context.lock);
 	list_add_tail(&uud->link, &utp_context.write);
+	/* Go on EXEC routine process */
 	wake_up(&utp_context.wq);
 	mutex_unlock(&utp_context.lock);
 	return size;
 }
 
+/* Will be called when the host wants to get the sense data */
 static int utp_get_sense(struct fsg_dev *fsg)
 {
 	if (UTP_CTX(fsg)->processed == 0)
@@ -186,6 +194,7 @@ static int utp_do_read(struct fsg_dev *fsg, void *data, size_t size)
 		/* Perform the read */
 		pr_info("Copied to %p, %d bytes started from %d\n",
 				bh->buf, amount, size - amount_left);
+		/* from upt buffer to file_storeage buffer */
 		memcpy(bh->buf, data + size - amount_left, amount);
 		amount_left  -= amount;
 		fsg->residue -= amount;
@@ -196,6 +205,7 @@ static int utp_do_read(struct fsg_dev *fsg, void *data, size_t size)
 		/* Send this buffer and go read some more */
 		bh->inreq->zero = 0;
 
+		/* USB Physical transfer: Data from device to host */
 		start_transfer(fsg, fsg->bulk_in, bh->inreq,
 				&bh->inreq_busy, &bh->state);
 
@@ -326,8 +336,8 @@ static void utp_poll(struct fsg_dev *fsg)
 
 	if (uud) {
 		if (uud->data.flags & UTP_FLAG_STATUS) {
-			pr_debug("%s: exit with status %d\n", __func__,
-				uud->data.status);
+			printk(KERN_WARNING "%s: exit with status %d\n",
+					__func__, uud->data.status);
 			UTP_SS_EXIT(fsg, uud->data.status);
 		} else {
 			pr_debug("%s: pass\n", __func__);
@@ -356,11 +366,16 @@ static int utp_exec(struct fsg_dev *fsg,
 	mutex_lock(&ctx->lock);
 	list_add_tail(&uud2r->link, &ctx->read);
 	mutex_unlock(&ctx->lock);
+	/* wake up the read routine */
 	wake_up(&ctx->wq);
 
 	if (command[0] == '!')	/* there will be no response */
 		return 0;
 
+	/*
+	 * the user program (uuc) will return utp_message
+	 * and add list to write list
+	 */
 	WAIT_ACTIVITY(write);
 
 	mutex_lock(&ctx->lock);
@@ -382,21 +397,19 @@ static int utp_exec(struct fsg_dev *fsg,
 	if (uud->data.flags & UTP_FLAG_DATA) {
 		memcpy(ctx->buffer, uud->data.data, uud->data.bufsize);
 		UTP_SS_SIZE(fsg, uud->data.bufsize);
-		utp_user_data_free(uud);
-		return 0;
-	}
-
-	if (uud->data.flags & UTP_FLAG_REPORT_BUSY) {
-		utp_user_data_free(uud);
+	} else if (uud->data.flags & UTP_FLAG_REPORT_BUSY) {
 		ctx->counter = 0xFFFF;
 		UTP_SS_BUSY(fsg, ctx->counter);
-		return 0;
+	} else if (uud->data.flags & UTP_FLAG_STATUS) {
+		printk(KERN_WARNING "%s: exit with status %d\n", __func__,
+				uud->data.status);
+		UTP_SS_EXIT(fsg, uud->data.status);
+	} else {
+		pr_debug("%s: pass\n", __func__);
+		UTP_SS_PASS(fsg);
 	}
-
 	utp_user_data_free(uud);
-	UTP_SS_PASS(fsg);
-
-	return -1;
+	return 0;
 }
 
 static int utp_send_status(struct fsg_dev *fsg)
@@ -470,16 +483,17 @@ static int utp_handle_message(struct fsg_dev *fsg,
 	case UTP_EXEC:
 		pr_debug("%s: EXEC\n", __func__);
 		data = kzalloc(fsg->data_size, GFP_KERNEL);
+		/* copy data from usb buffer to utp buffer */
 		utp_do_write(fsg, data, fsg->data_size);
 		utp_exec(fsg, data, fsg->data_size, param);
 		kfree(data);
 		break;
-	case UTP_GET:
+	case UTP_GET: /* data from device to host */
 		pr_debug("%s: GET, %d bytes\n", __func__, fsg->data_size);
 		r = utp_do_read(fsg, UTP_CTX(fsg)->buffer, fsg->data_size);
 		UTP_SS_PASS(fsg);
 		break;
-	case UTP_PUT:
+	case UTP_PUT: /* data from host to device */
 		pr_debug("%s: PUT, %d bytes\n", __func__, fsg->data_size);
 		uud2r = utp_user_data_alloc(fsg->data_size);
 		uud2r->data.bufsize = fsg->data_size;
@@ -490,6 +504,37 @@ static int utp_handle_message(struct fsg_dev *fsg,
 		list_add_tail(&uud2r->link, &UTP_CTX(fsg)->read);
 		mutex_unlock(&UTP_CTX(fsg)->lock);
 		wake_up(&UTP_CTX(fsg)->wq);
+		/*
+		 * Return PASS or FAIL according to uuc's status
+		 * Please open it if need to check uuc's status
+		 * and use another version uuc
+		 */
+#if 0
+		struct utp_user_data *uud = NULL;
+		struct utp_context *ctx;
+		WAIT_ACTIVITY(write);
+		ctx = UTP_CTX(fsg);
+		mutex_lock(&ctx->lock);
+
+		if (!list_empty(&ctx->write))
+			uud = list_first_entry(&ctx->write,
+					struct utp_user_data, link);
+
+		mutex_unlock(&ctx->lock);
+		if (uud) {
+			if (uud->data.flags & UTP_FLAG_STATUS) {
+				printk(KERN_WARNING "%s: exit with status %d\n",
+					 __func__, uud->data.status);
+				UTP_SS_EXIT(fsg, uud->data.status);
+			} else {
+				pr_debug("%s: pass\n", __func__);
+				UTP_SS_PASS(fsg);
+			}
+			utp_user_data_free(uud);
+		} else{
+			UTP_SS_PASS(fsg);
+		}
+#endif
 		UTP_SS_PASS(fsg);
 
 		wait_event_interruptible(UTP_CTX(fsg)->list_full_wq,
diff --git a/drivers/usb/gadget/fsl_updater.h b/drivers/usb/gadget/fsl_updater.h
index 44329a9af58a..70e4defa1a9c 100644
--- a/drivers/usb/gadget/fsl_updater.h
+++ b/drivers/usb/gadget/fsl_updater.h
@@ -59,6 +59,7 @@ static int utp_handle_message(struct fsg_dev *fsg,
 #define UTP_SS_BUSY(fsg, r)	utp_set_sense(fsg, UTP_REPLY_BUSY, (u64)r)
 #define UTP_SS_SIZE(fsg, r)	utp_set_sense(fsg, UTP_REPLY_SIZE, (u64)r)
 
+/* the structure of utp message which is mapped to 16-byte SCSI CBW's CDB */
 #pragma pack(1)
 struct utp_msg {
 	u8  f0;
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 1a9266e7e798..f0d6627fb981 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -28,6 +28,7 @@
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/timer.h>
+#include <linux/ktime.h>
 #include <linux/list.h>
 #include <linux/interrupt.h>
 #include <linux/reboot.h>
@@ -660,6 +661,7 @@ static int ehci_run (struct usb_hcd *hcd)
 	ehci_readl(ehci, &ehci->regs->command);	/* unblock posted writes */
 	msleep(5);
 	up_write(&ehci_cf_port_reset_rwsem);
+	ehci->last_periodic_enable = ktime_get_real();
 
 	temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
 	ehci_info (ehci,
@@ -767,9 +769,10 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd)
 
 			/* start 20 msec resume signaling from this port,
 			 * and make khubd collect PORT_STAT_C_SUSPEND to
-			 * stop that signaling.
+			 * stop that signaling.  Use 5 ms extra for safety,
+			 * like usb_port_resume() does.
 			 */
-			ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
+			ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
 			ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
 			mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
 		}
diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c
index de459bbd1eb1..2eac68f54ccd 100644
--- a/drivers/usb/host/ehci-hub.c
+++ b/drivers/usb/host/ehci-hub.c
@@ -119,9 +119,26 @@ static int ehci_bus_suspend (struct usb_hcd *hcd)
 	del_timer_sync(&ehci->watchdog);
 	del_timer_sync(&ehci->iaa_watchdog);
 
-	port = HCS_N_PORTS (ehci->hcs_params);
 	spin_lock_irq (&ehci->lock);
 
+	/* Once the controller is stopped, port resumes that are already
+	 * in progress won't complete.  Hence if remote wakeup is enabled
+	 * for the root hub and any ports are in the middle of a resume or
+	 * remote wakeup, we must fail the suspend.
+	 */
+	if (hcd->self.root_hub->do_remote_wakeup) {
+		port = HCS_N_PORTS(ehci->hcs_params);
+		while (port--) {
+			if (ehci->reset_done[port] != 0) {
+				spin_unlock_irq(&ehci->lock);
+				ehci_dbg(ehci, "suspend failed because "
+						"port %d is resuming\n",
+						port + 1);
+				return -EBUSY;
+			}
+		}
+	}
+
 	/* stop schedules, clean any completed work */
 	if (HC_IS_RUNNING(hcd->state)) {
 		ehci_quiesce (ehci);
@@ -137,6 +154,7 @@ static int ehci_bus_suspend (struct usb_hcd *hcd)
 	 */
 	ehci->bus_suspended = 0;
 	ehci->owned_ports = 0;
+	port = HCS_N_PORTS(ehci->hcs_params);
 	while (port--) {
 		u32 __iomem	*reg = &ehci->regs->port_status [port];
 		u32		t1 = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index c2f1b7df918c..c757a706843c 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -72,6 +72,12 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
 	int			retval;
 
 	switch (pdev->vendor) {
+	case PCI_VENDOR_ID_INTEL:
+		if (pdev->device == 0x27cc) {
+			ehci->broken_periodic = 1;
+			ehci_info(ehci, "using broken periodic workaround\n");
+		}
+		break;
 	case PCI_VENDOR_ID_TOSHIBA_2:
 		/* celleb's companion chip */
 		if (pdev->device == 0x01b5) {
diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c
index 7673554fa64d..1ae9faf1f8c2 100644
--- a/drivers/usb/host/ehci-q.c
+++ b/drivers/usb/host/ehci-q.c
@@ -475,8 +475,20 @@ halt:
 			 * we must clear the TT buffer (11.17.5).
 			 */
 			if (unlikely(last_status != -EINPROGRESS &&
-					last_status != -EREMOTEIO))
-				ehci_clear_tt_buffer(ehci, qh, urb, token);
+					last_status != -EREMOTEIO)) {
+				/* The TT's in some hubs malfunction when they
+				 * receive this request following a STALL (they
+				 * stop sending isochronous packets).  Since a
+				 * STALL can't leave the TT buffer in a busy
+				 * state (if you believe Figures 11-48 - 11-51
+				 * in the USB 2.0 spec), we won't clear the TT
+				 * buffer in this case.  Strictly speaking this
+				 * is a violation of the spec.
+				 */
+				if (last_status != -EPIPE)
+					ehci_clear_tt_buffer(ehci, qh, urb,
+							token);
+			}
 		}
 
 		/* if we're removing something not at the queue head,
@@ -790,9 +802,10 @@ qh_make (
 				 * But interval 1 scheduling is simpler, and
 				 * includes high bandwidth.
 				 */
-				dbg ("intr period %d uframes, NYET!",
-						urb->interval);
-				goto done;
+				urb->interval = 1;
+			} else if (qh->period > ehci->periodic_size) {
+				qh->period = ehci->periodic_size;
+				urb->interval = qh->period << 3;
 			}
 		} else {
 			int		think_time;
@@ -815,6 +828,10 @@ qh_make (
 					usb_calc_bus_time (urb->dev->speed,
 					is_input, 0, max_packet (maxp)));
 			qh->period = urb->interval;
+			if (qh->period > ehci->periodic_size) {
+				qh->period = ehci->periodic_size;
+				urb->interval = qh->period;
+			}
 		}
 	}
 
diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c
index edd61ee90323..c340f1f4b881 100644
--- a/drivers/usb/host/ehci-sched.c
+++ b/drivers/usb/host/ehci-sched.c
@@ -456,6 +456,8 @@ static int enable_periodic (struct ehci_hcd *ehci)
 	/* make sure ehci_work scans these */
 	ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index)
 		% (ehci->periodic_size << 3);
+	if (unlikely(ehci->broken_periodic))
+		ehci->last_periodic_enable = ktime_get_real();
 	return 0;
 }
 
@@ -467,6 +469,16 @@ static int disable_periodic (struct ehci_hcd *ehci)
 	if (--ehci->periodic_sched)
 		return 0;
 
+	if (unlikely(ehci->broken_periodic)) {
+		/* delay experimentally determined */
+		ktime_t safe = ktime_add_us(ehci->last_periodic_enable, 1000);
+		ktime_t now = ktime_get_real();
+		s64 delay = ktime_us_delta(safe, now);
+
+		if (unlikely(delay > 0))
+			udelay(delay);
+	}
+
 	/* did setting PSE not take effect yet?
 	 * takes effect only at frame boundaries...
 	 */
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index 4b81f5e77c8b..7a412652cb5d 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -118,6 +118,7 @@ struct ehci_hcd {			/* one per controller */
 	unsigned		stamp;
 	unsigned		random_frame;
 	unsigned long		next_statechange;
+	ktime_t			last_periodic_enable;
 	u32			command;
 
 	/* SILICON QUIRKS */
@@ -126,6 +127,7 @@ struct ehci_hcd {			/* one per controller */
 	unsigned		big_endian_mmio:1;
 	unsigned		big_endian_desc:1;
 	unsigned		has_amcc_usb23:1;
+	unsigned		broken_periodic:1;
 
 	/* required for usb32 quirk */
 	#define OHCI_CTRL_HCFS          (3 << 6)
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 58151687d351..1ed2a16a61de 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -88,6 +88,7 @@ static int ohci_restart (struct ohci_hcd *ohci);
 #ifdef CONFIG_PCI
 static void quirk_amd_pll(int state);
 static void amd_iso_dev_put(void);
+static void sb800_prefetch(struct ohci_hcd *ohci, int on);
 #else
 static inline void quirk_amd_pll(int state)
 {
@@ -97,6 +98,10 @@ static inline void amd_iso_dev_put(void)
 {
 	return;
 }
+static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
+{
+	return;
+}
 #endif
 
 
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index d2ba04dd785e..b8a1148f248e 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -177,6 +177,13 @@ static int ohci_quirk_amd700(struct usb_hcd *hcd)
 		return 0;
 
 	pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev);
+
+	/* SB800 needs pre-fetch fix */
+	if ((rev >= 0x40) && (rev <= 0x4f)) {
+		ohci->flags |= OHCI_QUIRK_AMD_PREFETCH;
+		ohci_dbg(ohci, "enabled AMD prefetch quirk\n");
+	}
+
 	if ((rev > 0x3b) || (rev < 0x30)) {
 		pci_dev_put(amd_smbus_dev);
 		amd_smbus_dev = NULL;
@@ -262,6 +269,19 @@ static void amd_iso_dev_put(void)
 
 }
 
+static void sb800_prefetch(struct ohci_hcd *ohci, int on)
+{
+	struct pci_dev *pdev;
+	u16 misc;
+
+	pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);
+	pci_read_config_word(pdev, 0x50, &misc);
+	if (on == 0)
+		pci_write_config_word(pdev, 0x50, misc & 0xfcff);
+	else
+		pci_write_config_word(pdev, 0x50, misc | 0x0300);
+}
+
 /* List of quirks for OHCI */
 static const struct pci_device_id ohci_pci_quirks[] = {
 	{
diff --git a/drivers/usb/host/ohci-q.c b/drivers/usb/host/ohci-q.c
index c2d80f80448b..2c7409b09e8b 100644
--- a/drivers/usb/host/ohci-q.c
+++ b/drivers/usb/host/ohci-q.c
@@ -49,9 +49,12 @@ __acquires(ohci->lock)
 	switch (usb_pipetype (urb->pipe)) {
 	case PIPE_ISOCHRONOUS:
 		ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
-		if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
-				&& quirk_amdiso(ohci))
-			quirk_amd_pll(1);
+		if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
+			if (quirk_amdiso(ohci))
+				quirk_amd_pll(1);
+			if (quirk_amdprefetch(ohci))
+				sb800_prefetch(ohci, 0);
+		}
 		break;
 	case PIPE_INTERRUPT:
 		ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
@@ -680,9 +683,12 @@ static void td_submit_urb (
 				data + urb->iso_frame_desc [cnt].offset,
 				urb->iso_frame_desc [cnt].length, urb, cnt);
 		}
-		if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
-				&& quirk_amdiso(ohci))
-			quirk_amd_pll(0);
+		if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
+			if (quirk_amdiso(ohci))
+				quirk_amd_pll(0);
+			if (quirk_amdprefetch(ohci))
+				sb800_prefetch(ohci, 1);
+		}
 		periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
 			&& ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
 		break;
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index 222011f6172c..5bf15fed0d9f 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -402,6 +402,7 @@ struct ohci_hcd {
 #define	OHCI_QUIRK_FRAME_NO	0x80			/* no big endian frame_no shift */
 #define	OHCI_QUIRK_HUB_POWER	0x100			/* distrust firmware power/oc setup */
 #define	OHCI_QUIRK_AMD_ISO	0x200			/* ISO transfers*/
+#define	OHCI_QUIRK_AMD_PREFETCH	0x400			/* pre-fetch for ISO transfer */
 	// there are also chip quirks/bugs in init logic
 
 	struct work_struct	nec_work;	/* Worker for NEC quirk */
@@ -433,6 +434,10 @@ static inline int quirk_amdiso(struct ohci_hcd *ohci)
 {
 	return ohci->flags & OHCI_QUIRK_AMD_ISO;
 }
+static inline int quirk_amdprefetch(struct ohci_hcd *ohci)
+{
+	return ohci->flags & OHCI_QUIRK_AMD_PREFETCH;
+}
 #else
 static inline int quirk_nec(struct ohci_hcd *ohci)
 {
@@ -446,6 +451,10 @@ static inline int quirk_amdiso(struct ohci_hcd *ohci)
 {
 	return 0;
 }
+static inline int quirk_amdprefetch(struct ohci_hcd *ohci)
+{
+	return 0;
+}
 #endif
 
 /* convert between an hcd pointer and the corresponding ohci_hcd */
diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c
index a949259f18b9..5b22a4d1c9e4 100644
--- a/drivers/usb/host/sl811-hcd.c
+++ b/drivers/usb/host/sl811-hcd.c
@@ -719,8 +719,12 @@ retry:
 		/* port status seems weird until after reset, so
 		 * force the reset and make khubd clean up later.
 		 */
-		sl811->port1 |= (1 << USB_PORT_FEAT_C_CONNECTION)
-				| (1 << USB_PORT_FEAT_CONNECTION);
+		if (sl811->stat_insrmv & 1)
+			sl811->port1 |= 1 << USB_PORT_FEAT_CONNECTION;
+		else
+			sl811->port1 &= ~(1 << USB_PORT_FEAT_CONNECTION);
+
+		sl811->port1 |= 1 << USB_PORT_FEAT_C_CONNECTION;
 
 	} else if (irqstat & SL11H_INTMASK_RD) {
 		if (sl811->port1 & (1 << USB_PORT_FEAT_SUSPEND)) {
diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c
index 274751b4409c..eb37d86bafef 100644
--- a/drivers/usb/host/uhci-hcd.c
+++ b/drivers/usb/host/uhci-hcd.c
@@ -749,7 +749,20 @@ static int uhci_rh_suspend(struct usb_hcd *hcd)
 	spin_lock_irq(&uhci->lock);
 	if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))
 		rc = -ESHUTDOWN;
-	else if (!uhci->dead)
+	else if (uhci->dead)
+		;		/* Dead controllers tell no tales */
+
+	/* Once the controller is stopped, port resumes that are already
+	 * in progress won't complete.  Hence if remote wakeup is enabled
+	 * for the root hub and any ports are in the middle of a resume or
+	 * remote wakeup, we must fail the suspend.
+	 */
+	else if (hcd->self.root_hub->do_remote_wakeup &&
+			uhci->resuming_ports) {
+		dev_dbg(uhci_dev(uhci), "suspend failed because a port "
+				"is resuming\n");
+		rc = -EBUSY;
+	} else
 		suspend_rh(uhci, UHCI_RH_SUSPENDED);
 	spin_unlock_irq(&uhci->lock);
 	return rc;
diff --git a/drivers/usb/host/uhci-hub.c b/drivers/usb/host/uhci-hub.c
index 885b585360b9..8270055848ca 100644
--- a/drivers/usb/host/uhci-hub.c
+++ b/drivers/usb/host/uhci-hub.c
@@ -167,7 +167,7 @@ static void uhci_check_ports(struct uhci_hcd *uhci)
 				/* Port received a wakeup request */
 				set_bit(port, &uhci->resuming_ports);
 				uhci->ports_timeout = jiffies +
-						msecs_to_jiffies(20);
+						msecs_to_jiffies(25);
 
 				/* Make sure we see the port again
 				 * after the resuming period is over. */
diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c
index 705e34324156..33128d52f212 100644
--- a/drivers/usb/host/xhci-dbg.c
+++ b/drivers/usb/host/xhci-dbg.c
@@ -413,7 +413,8 @@ void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx)
 	int i;
 
 	struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
-	dma_addr_t dma = ctx->dma + ((unsigned long)slot_ctx - (unsigned long)ctx);
+	dma_addr_t dma = ctx->dma +
+		((unsigned long)slot_ctx - (unsigned long)ctx->bytes);
 	int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
 
 	xhci_dbg(xhci, "Slot Context:\n");
@@ -459,7 +460,7 @@ void xhci_dbg_ep_ctx(struct xhci_hcd *xhci,
 	for (i = 0; i < last_ep_ctx; ++i) {
 		struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, ctx, i);
 		dma_addr_t dma = ctx->dma +
-			((unsigned long)ep_ctx - (unsigned long)ctx);
+			((unsigned long)ep_ctx - (unsigned long)ctx->bytes);
 
 		xhci_dbg(xhci, "Endpoint %02d Context:\n", i);
 		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",
diff --git a/drivers/usb/host/xhci-hcd.c b/drivers/usb/host/xhci-hcd.c
index 816c39caca1c..e478a63488fb 100644
--- a/drivers/usb/host/xhci-hcd.c
+++ b/drivers/usb/host/xhci-hcd.c
@@ -22,12 +22,18 @@
 
 #include <linux/irq.h>
 #include <linux/module.h>
+#include <linux/moduleparam.h>
 
 #include "xhci.h"
 
 #define DRIVER_AUTHOR "Sarah Sharp"
 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
 
+/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
+static int link_quirk;
+module_param(link_quirk, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
+
 /* TODO: copied from ehci-hcd.c - can this be refactored? */
 /*
  * handshake - spin reading hc until handshake completes or fails
@@ -214,6 +220,12 @@ int xhci_init(struct usb_hcd *hcd)
 
 	xhci_dbg(xhci, "xhci_init\n");
 	spin_lock_init(&xhci->lock);
+	if (link_quirk) {
+		xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
+		xhci->quirks |= XHCI_LINK_TRB_QUIRK;
+	} else {
+		xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
+	}
 	retval = xhci_mem_init(xhci, GFP_KERNEL);
 	xhci_dbg(xhci, "Finished xhci_init\n");
 
@@ -555,13 +567,22 @@ unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
 	return 1 << (xhci_get_endpoint_index(desc) + 1);
 }
 
+/* Find the flag for this endpoint (for use in the control context).  Use the
+ * endpoint index to create a bitmask.  The slot context is bit 0, endpoint 0 is
+ * bit 1, etc.
+ */
+unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
+{
+	return 1 << (ep_index + 1);
+}
+
 /* Compute the last valid endpoint context index.  Basically, this is the
  * endpoint index plus one.  For slot contexts with more than valid endpoint,
  * we find the most significant bit set in the added contexts flags.
  * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
  * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
  */
-static inline unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
+unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
 {
 	return fls(added_ctxs) - 1;
 }
@@ -589,6 +610,70 @@ int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
 	return 1;
 }
 
+static int xhci_configure_endpoint(struct xhci_hcd *xhci,
+		struct usb_device *udev, struct xhci_virt_device *virt_dev,
+		bool ctx_change);
+
+/*
+ * Full speed devices may have a max packet size greater than 8 bytes, but the
+ * USB core doesn't know that until it reads the first 8 bytes of the
+ * descriptor.  If the usb_device's max packet size changes after that point,
+ * we need to issue an evaluate context command and wait on it.
+ */
+static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
+		unsigned int ep_index, struct urb *urb)
+{
+	struct xhci_container_ctx *in_ctx;
+	struct xhci_container_ctx *out_ctx;
+	struct xhci_input_control_ctx *ctrl_ctx;
+	struct xhci_ep_ctx *ep_ctx;
+	int max_packet_size;
+	int hw_max_packet_size;
+	int ret = 0;
+
+	out_ctx = xhci->devs[slot_id]->out_ctx;
+	ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
+	hw_max_packet_size = MAX_PACKET_DECODED(ep_ctx->ep_info2);
+	max_packet_size = urb->dev->ep0.desc.wMaxPacketSize;
+	if (hw_max_packet_size != max_packet_size) {
+		xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
+		xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
+				max_packet_size);
+		xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
+				hw_max_packet_size);
+		xhci_dbg(xhci, "Issuing evaluate context command.\n");
+
+		/* Set up the modified control endpoint 0 */
+		xhci_endpoint_copy(xhci, xhci->devs[slot_id], ep_index);
+		in_ctx = xhci->devs[slot_id]->in_ctx;
+		ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
+		ep_ctx->ep_info2 &= ~MAX_PACKET_MASK;
+		ep_ctx->ep_info2 |= MAX_PACKET(max_packet_size);
+
+		/* Set up the input context flags for the command */
+		/* FIXME: This won't work if a non-default control endpoint
+		 * changes max packet sizes.
+		 */
+		ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
+		ctrl_ctx->add_flags = EP0_FLAG;
+		ctrl_ctx->drop_flags = 0;
+
+		xhci_dbg(xhci, "Slot %d input context\n", slot_id);
+		xhci_dbg_ctx(xhci, in_ctx, ep_index);
+		xhci_dbg(xhci, "Slot %d output context\n", slot_id);
+		xhci_dbg_ctx(xhci, out_ctx, ep_index);
+
+		ret = xhci_configure_endpoint(xhci, urb->dev,
+				xhci->devs[slot_id], true);
+
+		/* Clean up the input context for later use by bandwidth
+		 * functions.
+		 */
+		ctrl_ctx->add_flags = SLOT_FLAG;
+	}
+	return ret;
+}
+
 /*
  * non-error returns are a promise to giveback() the urb later
  * we drop ownership so next owner (or urb unlink) can get it
@@ -600,13 +685,13 @@ int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
 	int ret = 0;
 	unsigned int slot_id, ep_index;
 
+
 	if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, true, __func__) <= 0)
 		return -EINVAL;
 
 	slot_id = urb->dev->slot_id;
 	ep_index = xhci_get_endpoint_index(&urb->ep->desc);
 
-	spin_lock_irqsave(&xhci->lock, flags);
 	if (!xhci->devs || !xhci->devs[slot_id]) {
 		if (!in_interrupt())
 			dev_warn(&urb->dev->dev, "WARN: urb submitted for dev with no Slot ID\n");
@@ -619,19 +704,38 @@ int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
 		ret = -ESHUTDOWN;
 		goto exit;
 	}
-	if (usb_endpoint_xfer_control(&urb->ep->desc))
+	if (usb_endpoint_xfer_control(&urb->ep->desc)) {
+		/* Check to see if the max packet size for the default control
+		 * endpoint changed during FS device enumeration
+		 */
+		if (urb->dev->speed == USB_SPEED_FULL) {
+			ret = xhci_check_maxpacket(xhci, slot_id,
+					ep_index, urb);
+			if (ret < 0)
+				return ret;
+		}
+
 		/* We have a spinlock and interrupts disabled, so we must pass
 		 * atomic context to this function, which may allocate memory.
 		 */
+		spin_lock_irqsave(&xhci->lock, flags);
 		ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
 				slot_id, ep_index);
-	else if (usb_endpoint_xfer_bulk(&urb->ep->desc))
+		spin_unlock_irqrestore(&xhci->lock, flags);
+	} else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
+		spin_lock_irqsave(&xhci->lock, flags);
 		ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
 				slot_id, ep_index);
-	else
+		spin_unlock_irqrestore(&xhci->lock, flags);
+	} else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
+		spin_lock_irqsave(&xhci->lock, flags);
+		ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
+				slot_id, ep_index);
+		spin_unlock_irqrestore(&xhci->lock, flags);
+	} else {
 		ret = -EINVAL;
+	}
 exit:
-	spin_unlock_irqrestore(&xhci->lock, flags);
 	return ret;
 }
 
@@ -930,6 +1034,122 @@ static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *vir
 	}
 }
 
+static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
+		struct usb_device *udev, struct xhci_virt_device *virt_dev)
+{
+	int ret;
+
+	switch (virt_dev->cmd_status) {
+	case COMP_ENOMEM:
+		dev_warn(&udev->dev, "Not enough host controller resources "
+				"for new device state.\n");
+		ret = -ENOMEM;
+		/* FIXME: can we allocate more resources for the HC? */
+		break;
+	case COMP_BW_ERR:
+		dev_warn(&udev->dev, "Not enough bandwidth "
+				"for new device state.\n");
+		ret = -ENOSPC;
+		/* FIXME: can we go back to the old state? */
+		break;
+	case COMP_TRB_ERR:
+		/* the HCD set up something wrong */
+		dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
+				"add flag = 1, "
+				"and endpoint is not disabled.\n");
+		ret = -EINVAL;
+		break;
+	case COMP_SUCCESS:
+		dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
+		ret = 0;
+		break;
+	default:
+		xhci_err(xhci, "ERROR: unexpected command completion "
+				"code 0x%x.\n", virt_dev->cmd_status);
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
+		struct usb_device *udev, struct xhci_virt_device *virt_dev)
+{
+	int ret;
+
+	switch (virt_dev->cmd_status) {
+	case COMP_EINVAL:
+		dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
+				"context command.\n");
+		ret = -EINVAL;
+		break;
+	case COMP_EBADSLT:
+		dev_warn(&udev->dev, "WARN: slot not enabled for"
+				"evaluate context command.\n");
+	case COMP_CTX_STATE:
+		dev_warn(&udev->dev, "WARN: invalid context state for "
+				"evaluate context command.\n");
+		xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
+		ret = -EINVAL;
+		break;
+	case COMP_SUCCESS:
+		dev_dbg(&udev->dev, "Successful evaluate context command\n");
+		ret = 0;
+		break;
+	default:
+		xhci_err(xhci, "ERROR: unexpected command completion "
+				"code 0x%x.\n", virt_dev->cmd_status);
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+/* Issue a configure endpoint command or evaluate context command
+ * and wait for it to finish.
+ */
+static int xhci_configure_endpoint(struct xhci_hcd *xhci,
+		struct usb_device *udev, struct xhci_virt_device *virt_dev,
+		bool ctx_change)
+{
+	int ret;
+	int timeleft;
+	unsigned long flags;
+
+	spin_lock_irqsave(&xhci->lock, flags);
+	if (!ctx_change)
+		ret = xhci_queue_configure_endpoint(xhci, virt_dev->in_ctx->dma,
+				udev->slot_id);
+	else
+		ret = xhci_queue_evaluate_context(xhci, virt_dev->in_ctx->dma,
+				udev->slot_id);
+	if (ret < 0) {
+		spin_unlock_irqrestore(&xhci->lock, flags);
+		xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
+		return -ENOMEM;
+	}
+	xhci_ring_cmd_db(xhci);
+	spin_unlock_irqrestore(&xhci->lock, flags);
+
+	/* Wait for the configure endpoint command to complete */
+	timeleft = wait_for_completion_interruptible_timeout(
+			&virt_dev->cmd_completion,
+			USB_CTRL_SET_TIMEOUT);
+	if (timeleft <= 0) {
+		xhci_warn(xhci, "%s while waiting for %s command\n",
+				timeleft == 0 ? "Timeout" : "Signal",
+				ctx_change == 0 ?
+					"configure endpoint" :
+					"evaluate context");
+		/* FIXME cancel the configure endpoint command */
+		return -ETIME;
+	}
+
+	if (!ctx_change)
+		return xhci_configure_endpoint_result(xhci, udev, virt_dev);
+	return xhci_evaluate_context_result(xhci, udev, virt_dev);
+}
+
 /* Called after one or more calls to xhci_add_endpoint() or
  * xhci_drop_endpoint().  If this call fails, the USB core is expected
  * to call xhci_reset_bandwidth().
@@ -944,8 +1164,6 @@ int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
 {
 	int i;
 	int ret = 0;
-	int timeleft;
-	unsigned long flags;
 	struct xhci_hcd *xhci;
 	struct xhci_virt_device	*virt_dev;
 	struct xhci_input_control_ctx *ctrl_ctx;
@@ -975,56 +1193,7 @@ int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
 	xhci_dbg_ctx(xhci, virt_dev->in_ctx,
 			LAST_CTX_TO_EP_NUM(slot_ctx->dev_info));
 
-	spin_lock_irqsave(&xhci->lock, flags);
-	ret = xhci_queue_configure_endpoint(xhci, virt_dev->in_ctx->dma,
-			udev->slot_id);
-	if (ret < 0) {
-		spin_unlock_irqrestore(&xhci->lock, flags);
-		xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
-		return -ENOMEM;
-	}
-	xhci_ring_cmd_db(xhci);
-	spin_unlock_irqrestore(&xhci->lock, flags);
-
-	/* Wait for the configure endpoint command to complete */
-	timeleft = wait_for_completion_interruptible_timeout(
-			&virt_dev->cmd_completion,
-			USB_CTRL_SET_TIMEOUT);
-	if (timeleft <= 0) {
-		xhci_warn(xhci, "%s while waiting for configure endpoint command\n",
-				timeleft == 0 ? "Timeout" : "Signal");
-		/* FIXME cancel the configure endpoint command */
-		return -ETIME;
-	}
-
-	switch (virt_dev->cmd_status) {
-	case COMP_ENOMEM:
-		dev_warn(&udev->dev, "Not enough host controller resources "
-				"for new device state.\n");
-		ret = -ENOMEM;
-		/* FIXME: can we allocate more resources for the HC? */
-		break;
-	case COMP_BW_ERR:
-		dev_warn(&udev->dev, "Not enough bandwidth "
-				"for new device state.\n");
-		ret = -ENOSPC;
-		/* FIXME: can we go back to the old state? */
-		break;
-	case COMP_TRB_ERR:
-		/* the HCD set up something wrong */
-		dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, add flag = 1, "
-				"and endpoint is not disabled.\n");
-		ret = -EINVAL;
-		break;
-	case COMP_SUCCESS:
-		dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
-		break;
-	default:
-		xhci_err(xhci, "ERROR: unexpected command completion "
-				"code 0x%x.\n", virt_dev->cmd_status);
-		ret = -EINVAL;
-		break;
-	}
+	ret = xhci_configure_endpoint(xhci, udev, virt_dev, false);
 	if (ret) {
 		/* Callee should call reset_bandwidth() */
 		return ret;
@@ -1075,6 +1244,75 @@ void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
 	xhci_zero_in_ctx(xhci, virt_dev);
 }
 
+void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
+		unsigned int slot_id, unsigned int ep_index,
+		struct xhci_dequeue_state *deq_state)
+{
+	struct xhci_container_ctx *in_ctx;
+	struct xhci_input_control_ctx *ctrl_ctx;
+	struct xhci_ep_ctx *ep_ctx;
+	u32 added_ctxs;
+	dma_addr_t addr;
+
+	xhci_endpoint_copy(xhci, xhci->devs[slot_id], ep_index);
+	in_ctx = xhci->devs[slot_id]->in_ctx;
+	ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
+	addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
+			deq_state->new_deq_ptr);
+	if (addr == 0) {
+		xhci_warn(xhci, "WARN Cannot submit config ep after "
+				"reset ep command\n");
+		xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
+				deq_state->new_deq_seg,
+				deq_state->new_deq_ptr);
+		return;
+	}
+	ep_ctx->deq = addr | deq_state->new_cycle_state;
+
+	xhci_slot_copy(xhci, xhci->devs[slot_id]);
+
+	ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
+	added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
+	ctrl_ctx->add_flags = added_ctxs | SLOT_FLAG;
+	ctrl_ctx->drop_flags = added_ctxs;
+
+	xhci_dbg(xhci, "Slot ID %d Input Context:\n", slot_id);
+	xhci_dbg_ctx(xhci, in_ctx, ep_index);
+}
+
+void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
+		struct usb_device *udev,
+		unsigned int ep_index, struct xhci_ring *ep_ring)
+{
+	struct xhci_dequeue_state deq_state;
+
+	xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
+	/* We need to move the HW's dequeue pointer past this TD,
+	 * or it will attempt to resend it on the next doorbell ring.
+	 */
+	xhci_find_new_dequeue_state(xhci, udev->slot_id,
+			ep_index, ep_ring->stopped_td,
+			&deq_state);
+
+	/* HW with the reset endpoint quirk will use the saved dequeue state to
+	 * issue a configure endpoint command later.
+	 */
+	if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
+		xhci_dbg(xhci, "Queueing new dequeue state\n");
+		xhci_queue_new_dequeue_state(xhci, ep_ring,
+				udev->slot_id,
+				ep_index, &deq_state);
+	} else {
+		/* Better hope no one uses the input context between now and the
+		 * reset endpoint completion!
+		 */
+		xhci_dbg(xhci, "Setting up input context for "
+				"configure endpoint command\n");
+		xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
+				ep_index, &deq_state);
+	}
+}
+
 /* Deal with stalled endpoints.  The core should have sent the control message
  * to clear the halt condition.  However, we need to make the xHCI hardware
  * reset its sequence number, since a device will expect a sequence number of
@@ -1089,7 +1327,6 @@ void xhci_endpoint_reset(struct usb_hcd *hcd,
 	unsigned int ep_index;
 	unsigned long flags;
 	int ret;
-	struct xhci_dequeue_state deq_state;
 	struct xhci_ring *ep_ring;
 
 	xhci = hcd_to_xhci(hcd);
@@ -1106,6 +1343,10 @@ void xhci_endpoint_reset(struct usb_hcd *hcd,
 				ep->desc.bEndpointAddress);
 		return;
 	}
+	if (usb_endpoint_xfer_control(&ep->desc)) {
+		xhci_dbg(xhci, "Control endpoint stall already handled.\n");
+		return;
+	}
 
 	xhci_dbg(xhci, "Queueing reset endpoint command\n");
 	spin_lock_irqsave(&xhci->lock, flags);
@@ -1116,16 +1357,7 @@ void xhci_endpoint_reset(struct usb_hcd *hcd,
 	 * command.  Better hope that last command worked!
 	 */
 	if (!ret) {
-		xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
-		/* We need to move the HW's dequeue pointer past this TD,
-		 * or it will attempt to resend it on the next doorbell ring.
-		 */
-		xhci_find_new_dequeue_state(xhci, udev->slot_id,
-				ep_index, ep_ring->stopped_td, &deq_state);
-		xhci_dbg(xhci, "Queueing new dequeue state\n");
-		xhci_queue_new_dequeue_state(xhci, ep_ring,
-				udev->slot_id,
-				ep_index, &deq_state);
+		xhci_cleanup_stalled_ring(xhci, udev, ep_index, ep_ring);
 		kfree(ep_ring->stopped_td);
 		xhci_ring_cmd_db(xhci);
 	}
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index e6b9a1c6002d..21146486fdb2 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -94,6 +94,9 @@ static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
 		val = prev->trbs[TRBS_PER_SEGMENT-1].link.control;
 		val &= ~TRB_TYPE_BITMASK;
 		val |= TRB_TYPE(TRB_LINK);
+		/* Always set the chain bit with 0.95 hardware */
+		if (xhci_link_trb_quirk(xhci))
+			val |= TRB_CHAIN;
 		prev->trbs[TRBS_PER_SEGMENT-1].link.control = val;
 	}
 	xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
@@ -398,15 +401,28 @@ int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *ud
 	/* Step 5 */
 	ep0_ctx->ep_info2 = EP_TYPE(CTRL_EP);
 	/*
-	 * See section 4.3 bullet 6:
-	 * The default Max Packet size for ep0 is "8 bytes for a USB2
-	 * LS/FS/HS device or 512 bytes for a USB3 SS device"
 	 * XXX: Not sure about wireless USB devices.
 	 */
-	if (udev->speed == USB_SPEED_SUPER)
+	switch (udev->speed) {
+	case USB_SPEED_SUPER:
 		ep0_ctx->ep_info2 |= MAX_PACKET(512);
-	else
+		break;
+	case USB_SPEED_HIGH:
+	/* USB core guesses at a 64-byte max packet first for FS devices */
+	case USB_SPEED_FULL:
+		ep0_ctx->ep_info2 |= MAX_PACKET(64);
+		break;
+	case USB_SPEED_LOW:
 		ep0_ctx->ep_info2 |= MAX_PACKET(8);
+		break;
+	case USB_SPEED_VARIABLE:
+		xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
+		return -EINVAL;
+		break;
+	default:
+		/* New speed? */
+		BUG();
+	}
 	/* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
 	ep0_ctx->ep_info2 |= MAX_BURST(0);
 	ep0_ctx->ep_info2 |= ERROR_COUNT(3);
@@ -598,6 +614,44 @@ void xhci_endpoint_zero(struct xhci_hcd *xhci,
 	 */
 }
 
+/* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
+ * Useful when you want to change one particular aspect of the endpoint and then
+ * issue a configure endpoint command.
+ */
+void xhci_endpoint_copy(struct xhci_hcd *xhci,
+		struct xhci_virt_device *vdev, unsigned int ep_index)
+{
+	struct xhci_ep_ctx *out_ep_ctx;
+	struct xhci_ep_ctx *in_ep_ctx;
+
+	out_ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
+	in_ep_ctx = xhci_get_ep_ctx(xhci, vdev->in_ctx, ep_index);
+
+	in_ep_ctx->ep_info = out_ep_ctx->ep_info;
+	in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
+	in_ep_ctx->deq = out_ep_ctx->deq;
+	in_ep_ctx->tx_info = out_ep_ctx->tx_info;
+}
+
+/* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
+ * Useful when you want to change one particular aspect of the endpoint and then
+ * issue a configure endpoint command.  Only the context entries field matters,
+ * but we'll copy the whole thing anyway.
+ */
+void xhci_slot_copy(struct xhci_hcd *xhci, struct xhci_virt_device *vdev)
+{
+	struct xhci_slot_ctx *in_slot_ctx;
+	struct xhci_slot_ctx *out_slot_ctx;
+
+	in_slot_ctx = xhci_get_slot_ctx(xhci, vdev->in_ctx);
+	out_slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
+
+	in_slot_ctx->dev_info = out_slot_ctx->dev_info;
+	in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
+	in_slot_ctx->tt_info = out_slot_ctx->tt_info;
+	in_slot_ctx->dev_state = out_slot_ctx->dev_state;
+}
+
 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
 {
@@ -702,9 +756,11 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci)
 	int i;
 
 	/* Free the Event Ring Segment Table and the actual Event Ring */
-	xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
-	xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
-	xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
+	if (xhci->ir_set) {
+		xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
+		xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
+		xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
+	}
 	size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
 	if (xhci->erst.entries)
 		pci_free_consistent(pdev, size,
@@ -741,9 +797,9 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci)
 				xhci->dcbaa, xhci->dcbaa->dma);
 	xhci->dcbaa = NULL;
 
+	scratchpad_free(xhci);
 	xhci->page_size = 0;
 	xhci->page_shift = 0;
-	scratchpad_free(xhci);
 }
 
 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 592fe7e623f7..8fb308d43bc1 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -24,6 +24,10 @@
 
 #include "xhci.h"
 
+/* Device for a quirk */
+#define PCI_VENDOR_ID_FRESCO_LOGIC	0x1b73
+#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK	0x1000
+
 static const char hcd_name[] = "xhci_hcd";
 
 /* called after powerup, by probe or system-pm "wakeup" */
@@ -62,6 +66,15 @@ static int xhci_pci_setup(struct usb_hcd *hcd)
 	xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
 	xhci_print_registers(xhci);
 
+	/* Look for vendor-specific quirks */
+	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
+			pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
+			pdev->revision == 0x0) {
+			xhci->quirks |= XHCI_RESET_EP_QUIRK;
+			xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
+					" endpoint cmd after reset endpoint\n");
+	}
+
 	/* Make sure the HC is halted. */
 	retval = xhci_halt(xhci);
 	if (retval)
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index aa88a067148b..9874d9a60080 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -172,8 +172,9 @@ static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer
  * have their chain bit cleared (so that each Link TRB is a separate TD).
  *
  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
- * set, but other sections talk about dealing with the chain bit set.
- * Assume section 6.4.4.1 is wrong, and the chain bit can be set in a Link TRB.
+ * set, but other sections talk about dealing with the chain bit set.  This was
+ * fixed in the 0.96 specification errata, but we have to assume that all 0.95
+ * xHCI hardware can't handle the chain bit being cleared on a link TRB.
  */
 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 {
@@ -191,8 +192,14 @@ static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer
 	while (last_trb(xhci, ring, ring->enq_seg, next)) {
 		if (!consumer) {
 			if (ring != xhci->event_ring) {
-				next->link.control &= ~TRB_CHAIN;
-				next->link.control |= chain;
+				/* If we're not dealing with 0.95 hardware,
+				 * carry over the chain bit of the previous TRB
+				 * (which may mean the chain bit is cleared).
+				 */
+				if (!xhci_link_trb_quirk(xhci)) {
+					next->link.control &= ~TRB_CHAIN;
+					next->link.control |= chain;
+				}
 				/* Give this link TRB to the hardware */
 				wmb();
 				if (next->link.control & TRB_CYCLE)
@@ -462,7 +469,6 @@ void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 	 * ring running.
 	 */
 	ep_ring->state |= SET_DEQ_PENDING;
-	xhci_ring_cmd_db(xhci);
 }
 
 /*
@@ -531,6 +537,7 @@ static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 	if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 		xhci_queue_new_dequeue_state(xhci, ep_ring,
 				slot_id, ep_index, &deq_state);
+		xhci_ring_cmd_db(xhci);
 	} else {
 		/* Otherwise just ring the doorbell to restart the ring */
 		ring_ep_doorbell(xhci, slot_id, ep_index);
@@ -644,18 +651,31 @@ static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 {
 	int slot_id;
 	unsigned int ep_index;
+	struct xhci_ring *ep_ring;
 
 	slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 	ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
+	ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
 	/* This command will only fail if the endpoint wasn't halted,
 	 * but we don't care.
 	 */
 	xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
 			(unsigned int) GET_COMP_CODE(event->status));
 
-	/* Clear our internal halted state and restart the ring */
-	xhci->devs[slot_id]->ep_rings[ep_index]->state &= ~EP_HALTED;
-	ring_ep_doorbell(xhci, slot_id, ep_index);
+	/* HW with the reset endpoint quirk needs to have a configure endpoint
+	 * command complete before the endpoint can be used.  Queue that here
+	 * because the HW can't handle two commands being queued in a row.
+	 */
+	if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
+		xhci_dbg(xhci, "Queueing configure endpoint command\n");
+		xhci_queue_configure_endpoint(xhci,
+				xhci->devs[slot_id]->in_ctx->dma, slot_id);
+		xhci_ring_cmd_db(xhci);
+	} else {
+		/* Clear our internal halted state and restart the ring */
+		ep_ring->state &= ~EP_HALTED;
+		ring_ep_doorbell(xhci, slot_id, ep_index);
+	}
 }
 
 static void handle_cmd_completion(struct xhci_hcd *xhci,
@@ -664,6 +684,10 @@ static void handle_cmd_completion(struct xhci_hcd *xhci,
 	int slot_id = TRB_TO_SLOT_ID(event->flags);
 	u64 cmd_dma;
 	dma_addr_t cmd_dequeue_dma;
+	struct xhci_input_control_ctx *ctrl_ctx;
+	unsigned int ep_index;
+	struct xhci_ring *ep_ring;
+	unsigned int ep_state;
 
 	cmd_dma = event->cmd_trb;
 	cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
@@ -691,6 +715,41 @@ static void handle_cmd_completion(struct xhci_hcd *xhci,
 			xhci_free_virt_device(xhci, slot_id);
 		break;
 	case TRB_TYPE(TRB_CONFIG_EP):
+		/*
+		 * Configure endpoint commands can come from the USB core
+		 * configuration or alt setting changes, or because the HW
+		 * needed an extra configure endpoint command after a reset
+		 * endpoint command.  In the latter case, the xHCI driver is
+		 * not waiting on the configure endpoint command.
+		 */
+		ctrl_ctx = xhci_get_input_control_ctx(xhci,
+				xhci->devs[slot_id]->in_ctx);
+		/* Input ctx add_flags are the endpoint index plus one */
+		ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
+		ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
+		if (!ep_ring) {
+			/* This must have been an initial configure endpoint */
+			xhci->devs[slot_id]->cmd_status =
+				GET_COMP_CODE(event->status);
+			complete(&xhci->devs[slot_id]->cmd_completion);
+			break;
+		}
+		ep_state = ep_ring->state;
+		xhci_dbg(xhci, "Completed config ep cmd - last ep index = %d, "
+				"state = %d\n", ep_index, ep_state);
+		if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
+				ep_state & EP_HALTED) {
+			/* Clear our internal halted state and restart ring */
+			xhci->devs[slot_id]->ep_rings[ep_index]->state &=
+				~EP_HALTED;
+			ring_ep_doorbell(xhci, slot_id, ep_index);
+		} else {
+			xhci->devs[slot_id]->cmd_status =
+				GET_COMP_CODE(event->status);
+			complete(&xhci->devs[slot_id]->cmd_completion);
+		}
+		break;
+	case TRB_TYPE(TRB_EVAL_CONTEXT):
 		xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
 		complete(&xhci->devs[slot_id]->cmd_completion);
 		break;
@@ -763,9 +822,11 @@ static struct xhci_segment *trb_in_td(
 	cur_seg = start_seg;
 
 	do {
+		if (start_dma == 0)
+			return 0;
 		/* We may get an event for a Link TRB in the middle of a TD */
 		end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
-				&start_seg->trbs[TRBS_PER_SEGMENT - 1]);
+				&cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
 		/* If the end TRB isn't in this segment, this is set to 0 */
 		end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
 
@@ -792,8 +853,9 @@ static struct xhci_segment *trb_in_td(
 		}
 		cur_seg = cur_seg->next;
 		start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
-	} while (1);
+	} while (cur_seg != start_seg);
 
+	return 0;
 }
 
 /*
@@ -806,6 +868,7 @@ static int handle_tx_event(struct xhci_hcd *xhci,
 {
 	struct xhci_virt_device *xdev;
 	struct xhci_ring *ep_ring;
+	unsigned int slot_id;
 	int ep_index;
 	struct xhci_td *td = 0;
 	dma_addr_t event_dma;
@@ -814,9 +877,11 @@ static int handle_tx_event(struct xhci_hcd *xhci,
 	struct urb *urb = 0;
 	int status = -EINPROGRESS;
 	struct xhci_ep_ctx *ep_ctx;
+	u32 trb_comp_code;
 
 	xhci_dbg(xhci, "In %s\n", __func__);
-	xdev = xhci->devs[TRB_TO_SLOT_ID(event->flags)];
+	slot_id = TRB_TO_SLOT_ID(event->flags);
+	xdev = xhci->devs[slot_id];
 	if (!xdev) {
 		xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
 		return -ENODEV;
@@ -870,7 +935,8 @@ static int handle_tx_event(struct xhci_hcd *xhci,
 			(unsigned int) event->flags);
 
 	/* Look for common error cases */
-	switch (GET_COMP_CODE(event->transfer_len)) {
+	trb_comp_code = GET_COMP_CODE(event->transfer_len);
+	switch (trb_comp_code) {
 	/* Skip codes that require special handling depending on
 	 * transfer type
 	 */
@@ -913,7 +979,7 @@ static int handle_tx_event(struct xhci_hcd *xhci,
 	/* Was this a control transfer? */
 	if (usb_endpoint_xfer_control(&td->urb->ep->desc)) {
 		xhci_debug_trb(xhci, xhci->event_ring->dequeue);
-		switch (GET_COMP_CODE(event->transfer_len)) {
+		switch (trb_comp_code) {
 		case COMP_SUCCESS:
 			if (event_trb == ep_ring->dequeue) {
 				xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n");
@@ -928,8 +994,39 @@ static int handle_tx_event(struct xhci_hcd *xhci,
 			break;
 		case COMP_SHORT_TX:
 			xhci_warn(xhci, "WARN: short transfer on control ep\n");
-			status = -EREMOTEIO;
+			if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
+				status = -EREMOTEIO;
+			else
+				status = 0;
 			break;
+		case COMP_BABBLE:
+			/* The 0.96 spec says a babbling control endpoint
+			 * is not halted. The 0.96 spec says it is.  Some HW
+			 * claims to be 0.95 compliant, but it halts the control
+			 * endpoint anyway.  Check if a babble halted the
+			 * endpoint.
+			 */
+			if (ep_ctx->ep_info != EP_STATE_HALTED)
+				break;
+			/* else fall through */
+		case COMP_STALL:
+			/* Did we transfer part of the data (middle) phase? */
+			if (event_trb != ep_ring->dequeue &&
+					event_trb != td->last_trb)
+				td->urb->actual_length =
+					td->urb->transfer_buffer_length
+					- TRB_LEN(event->transfer_len);
+			else
+				td->urb->actual_length = 0;
+
+			ep_ring->stopped_td = td;
+			ep_ring->stopped_trb = event_trb;
+			xhci_queue_reset_ep(xhci, slot_id, ep_index);
+			xhci_cleanup_stalled_ring(xhci,
+					td->urb->dev,
+					ep_index, ep_ring);
+			xhci_ring_cmd_db(xhci);
+			goto td_cleanup;
 		default:
 			/* Others already handled above */
 			break;
@@ -943,7 +1040,10 @@ static int handle_tx_event(struct xhci_hcd *xhci,
 			if (event_trb == td->last_trb) {
 				if (td->urb->actual_length != 0) {
 					/* Don't overwrite a previously set error code */
-					if (status == -EINPROGRESS || status == 0)
+					if ((status == -EINPROGRESS ||
+								status == 0) &&
+							(td->urb->transfer_flags
+							 & URB_SHORT_NOT_OK))
 						/* Did we already see a short data stage? */
 						status = -EREMOTEIO;
 				} else {
@@ -952,7 +1052,7 @@ static int handle_tx_event(struct xhci_hcd *xhci,
 				}
 			} else {
 			/* Maybe the event was for the data stage? */
-				if (GET_COMP_CODE(event->transfer_len) != COMP_STOP_INVAL) {
+				if (trb_comp_code != COMP_STOP_INVAL) {
 					/* We didn't stop on a link TRB in the middle */
 					td->urb->actual_length =
 						td->urb->transfer_buffer_length -
@@ -964,7 +1064,7 @@ static int handle_tx_event(struct xhci_hcd *xhci,
 			}
 		}
 	} else {
-		switch (GET_COMP_CODE(event->transfer_len)) {
+		switch (trb_comp_code) {
 		case COMP_SUCCESS:
 			/* Double check that the HW transferred everything. */
 			if (event_trb != td->last_trb) {
@@ -975,7 +1075,12 @@ static int handle_tx_event(struct xhci_hcd *xhci,
 				else
 					status = 0;
 			} else {
-				xhci_dbg(xhci, "Successful bulk transfer!\n");
+				if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
+					xhci_dbg(xhci, "Successful bulk "
+							"transfer!\n");
+				else
+					xhci_dbg(xhci, "Successful interrupt "
+							"transfer!\n");
 				status = 0;
 			}
 			break;
@@ -1001,11 +1106,17 @@ static int handle_tx_event(struct xhci_hcd *xhci,
 				td->urb->actual_length =
 					td->urb->transfer_buffer_length -
 					TRB_LEN(event->transfer_len);
-				if (td->urb->actual_length < 0) {
+				if (td->urb->transfer_buffer_length <
+						td->urb->actual_length) {
 					xhci_warn(xhci, "HC gave bad length "
 							"of %d bytes left\n",
 							TRB_LEN(event->transfer_len));
 					td->urb->actual_length = 0;
+					if (td->urb->transfer_flags &
+							URB_SHORT_NOT_OK)
+						status = -EREMOTEIO;
+					else
+						status = 0;
 				}
 				/* Don't overwrite a previously set error code */
 				if (status == -EINPROGRESS) {
@@ -1041,14 +1152,14 @@ static int handle_tx_event(struct xhci_hcd *xhci,
 			/* If the ring didn't stop on a Link or No-op TRB, add
 			 * in the actual bytes transferred from the Normal TRB
 			 */
-			if (GET_COMP_CODE(event->transfer_len) != COMP_STOP_INVAL)
+			if (trb_comp_code != COMP_STOP_INVAL)
 				td->urb->actual_length +=
 					TRB_LEN(cur_trb->generic.field[2]) -
 					TRB_LEN(event->transfer_len);
 		}
 	}
-	if (GET_COMP_CODE(event->transfer_len) == COMP_STOP_INVAL ||
-			GET_COMP_CODE(event->transfer_len) == COMP_STOP) {
+	if (trb_comp_code == COMP_STOP_INVAL ||
+			trb_comp_code == COMP_STOP) {
 		/* The Endpoint Stop Command completion will take care of any
 		 * stopped TDs.  A stopped TD may be restarted, so don't update
 		 * the ring dequeue pointer or take this TD off any lists yet.
@@ -1056,7 +1167,8 @@ static int handle_tx_event(struct xhci_hcd *xhci,
 		ep_ring->stopped_td = td;
 		ep_ring->stopped_trb = event_trb;
 	} else {
-		if (GET_COMP_CODE(event->transfer_len) == COMP_STALL) {
+		if (trb_comp_code == COMP_STALL ||
+				trb_comp_code == COMP_BABBLE) {
 			/* The transfer is completed from the driver's
 			 * perspective, but we need to issue a set dequeue
 			 * command for this stalled endpoint to move the dequeue
@@ -1072,16 +1184,41 @@ static int handle_tx_event(struct xhci_hcd *xhci,
 			inc_deq(xhci, ep_ring, false);
 		}
 
+td_cleanup:
 		/* Clean up the endpoint's TD list */
 		urb = td->urb;
+		/* Do one last check of the actual transfer length.
+		 * If the host controller said we transferred more data than
+		 * the buffer length, urb->actual_length will be a very big
+		 * number (since it's unsigned).  Play it safe and say we didn't
+		 * transfer anything.
+		 */
+		if (urb->actual_length > urb->transfer_buffer_length) {
+			xhci_warn(xhci, "URB transfer length is wrong, "
+					"xHC issue? req. len = %u, "
+					"act. len = %u\n",
+					urb->transfer_buffer_length,
+					urb->actual_length);
+			urb->actual_length = 0;
+			if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
+				status = -EREMOTEIO;
+			else
+				status = 0;
+		}
 		list_del(&td->td_list);
 		/* Was this TD slated to be cancelled but completed anyway? */
 		if (!list_empty(&td->cancelled_td_list)) {
 			list_del(&td->cancelled_td_list);
 			ep_ring->cancels_pending--;
 		}
-		/* Leave the TD around for the reset endpoint function to use */
-		if (GET_COMP_CODE(event->transfer_len) != COMP_STALL) {
+		/* Leave the TD around for the reset endpoint function to use
+		 * (but only if it's not a control endpoint, since we already
+		 * queued the Set TR dequeue pointer command for stalled
+		 * control endpoints).
+		 */
+		if (usb_endpoint_xfer_control(&urb->ep->desc) ||
+			(trb_comp_code != COMP_STALL &&
+				trb_comp_code != COMP_BABBLE)) {
 			kfree(td);
 		}
 		urb->hcpriv = NULL;
@@ -1094,7 +1231,7 @@ cleanup:
 	if (urb) {
 		usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
 		xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n",
-				urb, td->urb->actual_length, status);
+				urb, urb->actual_length, status);
 		spin_unlock(&xhci->lock);
 		usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
 		spin_lock(&xhci->lock);
@@ -1335,6 +1472,47 @@ static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
 	ring_ep_doorbell(xhci, slot_id, ep_index);
 }
 
+/*
+ * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
+ * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
+ * (comprised of sg list entries) can take several service intervals to
+ * transmit.
+ */
+int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
+		struct urb *urb, int slot_id, unsigned int ep_index)
+{
+	struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
+			xhci->devs[slot_id]->out_ctx, ep_index);
+	int xhci_interval;
+	int ep_interval;
+
+	xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
+	ep_interval = urb->interval;
+	/* Convert to microframes */
+	if (urb->dev->speed == USB_SPEED_LOW ||
+			urb->dev->speed == USB_SPEED_FULL)
+		ep_interval *= 8;
+	/* FIXME change this to a warning and a suggestion to use the new API
+	 * to set the polling interval (once the API is added).
+	 */
+	if (xhci_interval != ep_interval) {
+		if (!printk_ratelimit())
+			dev_dbg(&urb->dev->dev, "Driver uses different interval"
+					" (%d microframe%s) than xHCI "
+					"(%d microframe%s)\n",
+					ep_interval,
+					ep_interval == 1 ? "" : "s",
+					xhci_interval,
+					xhci_interval == 1 ? "" : "s");
+		urb->interval = xhci_interval;
+		/* Convert back to frames for LS/FS devices */
+		if (urb->dev->speed == USB_SPEED_LOW ||
+				urb->dev->speed == USB_SPEED_FULL)
+			urb->interval /= 8;
+	}
+	return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
+}
+
 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
 		struct urb *urb, int slot_id, unsigned int ep_index)
 {
@@ -1733,6 +1911,15 @@ int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
 			TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id));
 }
 
+/* Queue an evaluate context command TRB */
+int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
+		u32 slot_id)
+{
+	return queue_command(xhci, lower_32_bits(in_ctx_ptr),
+			upper_32_bits(in_ctx_ptr), 0,
+			TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id));
+}
+
 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
 		unsigned int ep_index)
 {
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index d31d32206ba3..808584153579 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -581,6 +581,7 @@ struct xhci_ep_ctx {
 /* bit 15 is Linear Stream Array */
 /* Interval - period between requests to an endpoint - 125u increments. */
 #define EP_INTERVAL(p)		((p & 0xff) << 16)
+#define EP_INTERVAL_TO_UFRAMES(p)		(1 << (((p) >> 16) & 0xff))
 
 /* ep_info2 bitmasks */
 /*
@@ -589,6 +590,7 @@ struct xhci_ep_ctx {
  */
 #define	FORCE_EVENT	(0x1)
 #define ERROR_COUNT(p)	(((p) & 0x3) << 1)
+#define CTX_TO_EP_TYPE(p)	(((p) >> 3) & 0x7)
 #define EP_TYPE(p)	((p) << 3)
 #define ISOC_OUT_EP	1
 #define BULK_OUT_EP	2
@@ -601,6 +603,8 @@ struct xhci_ep_ctx {
 /* bit 7 is Host Initiate Disable - for disabling stream selection */
 #define MAX_BURST(p)	(((p)&0xff) << 8)
 #define MAX_PACKET(p)	(((p)&0xffff) << 16)
+#define MAX_PACKET_MASK		(0xffff << 16)
+#define MAX_PACKET_DECODED(p)	(((p) >> 16) & 0xffff)
 
 
 /**
@@ -926,6 +930,12 @@ struct xhci_td {
 	union xhci_trb		*last_trb;
 };
 
+struct xhci_dequeue_state {
+	struct xhci_segment *new_deq_seg;
+	union xhci_trb *new_deq_ptr;
+	int new_cycle_state;
+};
+
 struct xhci_ring {
 	struct xhci_segment	*first_seg;
 	union  xhci_trb		*enqueue;
@@ -952,12 +962,6 @@ struct xhci_ring {
 	u32			cycle_state;
 };
 
-struct xhci_dequeue_state {
-	struct xhci_segment *new_deq_seg;
-	union xhci_trb *new_deq_ptr;
-	int new_cycle_state;
-};
-
 struct xhci_erst_entry {
 	/* 64-bit event ring segment address */
 	u64	seg_addr;
@@ -1058,6 +1062,9 @@ struct xhci_hcd {
 	int			noops_submitted;
 	int			noops_handled;
 	int			error_bitmask;
+	unsigned int		quirks;
+#define	XHCI_LINK_TRB_QUIRK	(1 << 0)
+#define XHCI_RESET_EP_QUIRK	(1 << 1)
 };
 
 /* For testing purposes */
@@ -1136,6 +1143,13 @@ static inline void xhci_write_64(struct xhci_hcd *xhci,
 	writel(val_hi, ptr + 1);
 }
 
+static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
+{
+	u32 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
+	return ((HC_VERSION(temp) == 0x95) &&
+			(xhci->quirks & XHCI_LINK_TRB_QUIRK));
+}
+
 /* xHCI debugging */
 void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num);
 void xhci_print_registers(struct xhci_hcd *xhci);
@@ -1158,7 +1172,12 @@ int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device
 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
+unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
+unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
+void xhci_endpoint_copy(struct xhci_hcd *xhci,
+		struct xhci_virt_device *vdev, unsigned int ep_index);
+void xhci_slot_copy(struct xhci_hcd *xhci, struct xhci_virt_device *vdev);
 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
 		struct usb_device *udev, struct usb_host_endpoint *ep,
 		gfp_t mem_flags);
@@ -1205,8 +1224,12 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
 		int slot_id, unsigned int ep_index);
 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
 		int slot_id, unsigned int ep_index);
+int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
+		int slot_id, unsigned int ep_index);
 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
 		u32 slot_id);
+int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
+		u32 slot_id);
 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
 		unsigned int ep_index);
 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
@@ -1215,6 +1238,12 @@ void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 		struct xhci_ring *ep_ring, unsigned int slot_id,
 		unsigned int ep_index, struct xhci_dequeue_state *deq_state);
+void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
+		struct usb_device *udev,
+		unsigned int ep_index, struct xhci_ring *ep_ring);
+void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
+		unsigned int slot_id, unsigned int ep_index,
+		struct xhci_dequeue_state *deq_state);
 
 /* xHCI roothub code */
 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
diff --git a/drivers/usb/misc/appledisplay.c b/drivers/usb/misc/appledisplay.c
index 1d8e39a557d9..62ff5e729110 100644
--- a/drivers/usb/misc/appledisplay.c
+++ b/drivers/usb/misc/appledisplay.c
@@ -72,8 +72,8 @@ struct appledisplay {
 	struct usb_device *udev;	/* usb device */
 	struct urb *urb;		/* usb request block */
 	struct backlight_device *bd;	/* backlight device */
-	char *urbdata;			/* interrupt URB data buffer */
-	char *msgdata;			/* control message data buffer */
+	u8 *urbdata;			/* interrupt URB data buffer */
+	u8 *msgdata;			/* control message data buffer */
 
 	struct delayed_work work;
 	int button_pressed;
diff --git a/drivers/usb/misc/emi62.c b/drivers/usb/misc/emi62.c
index 602ee05ba9ff..59860b328534 100644
--- a/drivers/usb/misc/emi62.c
+++ b/drivers/usb/misc/emi62.c
@@ -167,7 +167,7 @@ static int emi62_load_firmware (struct usb_device *dev)
 			err("%s - error loading firmware: error = %d", __func__, err);
 			goto wraperr;
 		}
-	} while (i > 0);
+	} while (rec);
 
 	/* Assert reset (stop the CPU in the EMI) */
 	err = emi62_set_reset(dev,1);
diff --git a/drivers/usb/mon/mon_bin.c b/drivers/usb/mon/mon_bin.c
index 0f7a30b7d2d1..fb1dd27be76d 100644
--- a/drivers/usb/mon/mon_bin.c
+++ b/drivers/usb/mon/mon_bin.c
@@ -350,12 +350,12 @@ static unsigned int mon_buff_area_alloc_contiguous(struct mon_reader_bin *rp,
 
 /*
  * Return a few (kilo-)bytes to the head of the buffer.
- * This is used if a DMA fetch fails.
+ * This is used if a data fetch fails.
  */
 static void mon_buff_area_shrink(struct mon_reader_bin *rp, unsigned int size)
 {
 
-	size = (size + PKT_ALIGN-1) & ~(PKT_ALIGN-1);
+	/* size &= ~(PKT_ALIGN-1);  -- we're called with aligned size */
 	rp->b_cnt -= size;
 	if (rp->b_in < size)
 		rp->b_in += rp->b_size;
@@ -442,6 +442,7 @@ static void mon_bin_event(struct mon_reader_bin *rp, struct urb *urb,
 	unsigned int urb_length;
 	unsigned int offset;
 	unsigned int length;
+	unsigned int delta;
 	unsigned int ndesc, lendesc;
 	unsigned char dir;
 	struct mon_bin_hdr *ep;
@@ -546,8 +547,10 @@ static void mon_bin_event(struct mon_reader_bin *rp, struct urb *urb,
 	if (length != 0) {
 		ep->flag_data = mon_bin_get_data(rp, offset, urb, length);
 		if (ep->flag_data != 0) {	/* Yes, it's 0x00, not '0' */
-			ep->len_cap = 0;
-			mon_buff_area_shrink(rp, length);
+			delta = (ep->len_cap + PKT_ALIGN-1) & ~(PKT_ALIGN-1);
+			ep->len_cap -= length;
+			delta -= (ep->len_cap + PKT_ALIGN-1) & ~(PKT_ALIGN-1);
+			mon_buff_area_shrink(rp, delta);
 		}
 	} else {
 		ep->flag_data = data_tag;
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index 8b3c4e2ed7b8..74073f9a43f0 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -4,6 +4,7 @@
  * Copyright 2005 Mentor Graphics Corporation
  * Copyright (C) 2005-2006 by Texas Instruments
  * Copyright (C) 2006-2007 Nokia Corporation
+ * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -436,14 +437,6 @@ void musb_g_tx(struct musb *musb, u8 epnum)
 			csr |= MUSB_TXCSR_P_WZC_BITS;
 			csr &= ~MUSB_TXCSR_P_SENTSTALL;
 			musb_writew(epio, MUSB_TXCSR, csr);
-			if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
-				dma->status = MUSB_DMA_STATUS_CORE_ABORT;
-				musb->dma_controller->channel_abort(dma);
-			}
-
-			if (request)
-				musb_g_giveback(musb_ep, request, -EPIPE);
-
 			break;
 		}
 
@@ -582,15 +575,25 @@ void musb_g_tx(struct musb *musb, u8 epnum)
  */
 static void rxstate(struct musb *musb, struct musb_request *req)
 {
-	u16			csr = 0;
 	const u8		epnum = req->epnum;
 	struct usb_request	*request = &req->request;
 	struct musb_ep		*musb_ep = &musb->endpoints[epnum].ep_out;
 	void __iomem		*epio = musb->endpoints[epnum].regs;
 	unsigned		fifo_count = 0;
 	u16			len = musb_ep->packet_sz;
+	u16			csr = musb_readw(epio, MUSB_RXCSR);
 
-	csr = musb_readw(epio, MUSB_RXCSR);
+	/* We shouldn't get here while DMA is active, but we do... */
+	if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
+		DBG(4, "DMA pending...\n");
+		return;
+	}
+
+	if (csr & MUSB_RXCSR_P_SENDSTALL) {
+		DBG(5, "%s stalling, RXCSR %04x\n",
+		    musb_ep->end_point.name, csr);
+		return;
+	}
 
 	if (is_cppi_enabled() && musb_ep->dma) {
 		struct dma_controller	*c = musb->dma_controller;
@@ -761,19 +764,10 @@ void musb_g_rx(struct musb *musb, u8 epnum)
 			csr, dma ? " (dma)" : "", request);
 
 	if (csr & MUSB_RXCSR_P_SENTSTALL) {
-		if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
-			dma->status = MUSB_DMA_STATUS_CORE_ABORT;
-			(void) musb->dma_controller->channel_abort(dma);
-			request->actual += musb_ep->dma->actual_len;
-		}
-
 		csr |= MUSB_RXCSR_P_WZC_BITS;
 		csr &= ~MUSB_RXCSR_P_SENTSTALL;
 		musb_writew(epio, MUSB_RXCSR, csr);
-
-		if (request)
-			musb_g_giveback(musb_ep, request, -EPIPE);
-		goto done;
+		return;
 	}
 
 	if (csr & MUSB_RXCSR_P_OVERRUN) {
@@ -795,7 +789,7 @@ void musb_g_rx(struct musb *musb, u8 epnum)
 		DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
 			"%s busy, csr %04x\n",
 			musb_ep->end_point.name, csr);
-		goto done;
+		return;
 	}
 
 	if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
@@ -826,22 +820,15 @@ void musb_g_rx(struct musb *musb, u8 epnum)
 		if ((request->actual < request->length)
 				&& (musb_ep->dma->actual_len
 					== musb_ep->packet_sz))
-			goto done;
+			return;
 #endif
 		musb_g_giveback(musb_ep, request, 0);
 
 		request = next_request(musb_ep);
 		if (!request)
-			goto done;
-
-		/* don't start more i/o till the stall clears */
-		musb_ep_select(mbase, epnum);
-		csr = musb_readw(epio, MUSB_RXCSR);
-		if (csr & MUSB_RXCSR_P_SENDSTALL)
-			goto done;
+			return;
 	}
 
-
 	/* analyze request if the ep is hot */
 	if (request)
 		rxstate(musb, to_musb_request(request));
@@ -849,8 +836,6 @@ void musb_g_rx(struct musb *musb, u8 epnum)
 		DBG(3, "packet waiting for %s%s request\n",
 				musb_ep->desc ? "" : "inactive ",
 				musb_ep->end_point.name);
-
-done:
 	return;
 }
 
@@ -1244,7 +1229,7 @@ int musb_gadget_set_halt(struct usb_ep *ep, int value)
 	void __iomem		*mbase;
 	unsigned long		flags;
 	u16			csr;
-	struct musb_request	*request = NULL;
+	struct musb_request	*request;
 	int			status = 0;
 
 	if (!ep)
@@ -1260,24 +1245,29 @@ int musb_gadget_set_halt(struct usb_ep *ep, int value)
 
 	musb_ep_select(mbase, epnum);
 
-	/* cannot portably stall with non-empty FIFO */
 	request = to_musb_request(next_request(musb_ep));
-	if (value && musb_ep->is_in) {
-		csr = musb_readw(epio, MUSB_TXCSR);
-		if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
-			DBG(3, "%s fifo busy, cannot halt\n", ep->name);
-			spin_unlock_irqrestore(&musb->lock, flags);
-			return -EAGAIN;
+	if (value) {
+		if (request) {
+			DBG(3, "request in progress, cannot halt %s\n",
+			    ep->name);
+			status = -EAGAIN;
+			goto done;
+		}
+		/* Cannot portably stall with non-empty FIFO */
+		if (musb_ep->is_in) {
+			csr = musb_readw(epio, MUSB_TXCSR);
+			if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
+				DBG(3, "FIFO busy, cannot halt %s\n", ep->name);
+				status = -EAGAIN;
+				goto done;
+			}
 		}
-
 	}
 
 	/* set/clear the stall and toggle bits */
 	DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
 	if (musb_ep->is_in) {
 		csr = musb_readw(epio, MUSB_TXCSR);
-		if (csr & MUSB_TXCSR_FIFONOTEMPTY)
-			csr |= MUSB_TXCSR_FLUSHFIFO;
 		csr |= MUSB_TXCSR_P_WZC_BITS
 			| MUSB_TXCSR_CLRDATATOG;
 		if (value)
@@ -1300,14 +1290,13 @@ int musb_gadget_set_halt(struct usb_ep *ep, int value)
 		musb_writew(epio, MUSB_RXCSR, csr);
 	}
 
-done:
-
 	/* maybe start the first request in the queue */
 	if (!musb_ep->busy && !value && request) {
 		DBG(3, "restarting the request\n");
 		musb_ep_restart(musb, request);
 	}
 
+done:
 	spin_unlock_irqrestore(&musb->lock, flags);
 	return status;
 }
diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c
index 7a6778675ad3..677cc2ee9fd3 100644
--- a/drivers/usb/musb/musb_gadget_ep0.c
+++ b/drivers/usb/musb/musb_gadget_ep0.c
@@ -199,7 +199,6 @@ service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
 static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
 {
 	musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
-	musb->ep0_state = MUSB_EP0_STAGE_SETUP;
 }
 
 /*
@@ -647,7 +646,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
 			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
 			break;
 		default:
-			ERR("SetupEnd came in a wrong ep0stage %s",
+			ERR("SetupEnd came in a wrong ep0stage %s\n",
 			    decode_ep0stage(musb->ep0_state));
 		}
 		csr = musb_readw(regs, MUSB_CSR0);
@@ -770,12 +769,18 @@ setup:
 				handled = service_zero_data_request(
 						musb, &setup);
 
+				/*
+				 * We're expecting no data in any case, so
+				 * always set the DATAEND bit -- doing this
+				 * here helps avoid SetupEnd interrupt coming
+				 * in the idle stage when we're stalling...
+				 */
+				musb->ackpend |= MUSB_CSR0_P_DATAEND;
+
 				/* status stage might be immediate */
-				if (handled > 0) {
-					musb->ackpend |= MUSB_CSR0_P_DATAEND;
+				if (handled > 0)
 					musb->ep0_state =
 						MUSB_EP0_STAGE_STATUSIN;
-				}
 				break;
 
 			/* sequence #1 (IN to host), includes GET_STATUS
diff --git a/drivers/usb/otg/fsl_otg.c b/drivers/usb/otg/fsl_otg.c
index b1454886fd7a..6941e0565c03 100644
--- a/drivers/usb/otg/fsl_otg.c
+++ b/drivers/usb/otg/fsl_otg.c
@@ -41,6 +41,7 @@
 #include <linux/usb/gadget.h>
 #include <linux/workqueue.h>
 #include <linux/time.h>
+#include <linux/usb/fsl_xcvr.h>
 #include <linux/fsl_devices.h>
 #include <linux/platform_device.h>
 #include <linux/irq.h>
@@ -136,7 +137,7 @@ void fsl_otg_dischrg_vbus(int on)
 }
 
 /* A-device driver vbus, controlled through PP bit in PORTSC */
-void fsl_otg_drv_vbus(int on)
+void fsl_otg_drv_vbus(struct fsl_usb2_platform_data *pdata, int on)
 {
 /*	if (on)
 		usb_dr_regs->portsc =
@@ -147,6 +148,8 @@ void fsl_otg_drv_vbus(int on)
 		    cpu_to_le32(le32_to_cpu(usb_dr_regs->portsc) &
 				~PORTSC_W1C_BITS & ~PORTSC_PORT_POWER);
 */
+	if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_power)
+		pdata->xcvr_ops->set_vbus_power(pdata->xcvr_ops, pdata, on);
 }
 
 /*
@@ -438,7 +441,7 @@ int fsl_otg_start_host(struct otg_fsm *fsm, int on)
 				retval = host_pdrv->resume(host_pdev);
 				if (fsm->id) {
 					/* default-b */
-					fsl_otg_drv_vbus(1);
+					fsl_otg_drv_vbus(dev->platform_data, 1);
 					/* Workaround: b_host can't driver
 					 * vbus, but PP in PORTSC needs to
 					 * be 1 for host to work.
@@ -463,7 +466,7 @@ int fsl_otg_start_host(struct otg_fsm *fsm, int on)
 							otg_suspend_state);
 				if (fsm->id)
 					/* default-b */
-					fsl_otg_drv_vbus(0);
+					fsl_otg_drv_vbus(dev->platform_data, 0);
 			}
 			otg_dev->host_working = 0;
 		}
@@ -680,9 +683,10 @@ irqreturn_t fsl_otg_isr_gpio(int irq, void *dev_id)
 		(struct fsl_usb2_platform_data *)dev_id;
 	struct fsl_otg *p_otg;
 	struct otg_transceiver *otg_trans = otg_get_transceiver();
+	int value;
+
 	p_otg = container_of(otg_trans, struct fsl_otg, otg);
 	fsm = &p_otg->fsm;
-	int value;
 
 	if (pdata->id_gpio == 0)
 		return IRQ_NONE;
@@ -782,9 +786,25 @@ irqreturn_t fsl_otg_isr(int irq, void *dev_id)
 	return IRQ_NONE;
 }
 
+static void fsl_otg_fsm_drv_vbus(int on)
+{
+	struct otg_fsm *fsm = &(fsl_otg_dev->fsm);
+	struct otg_transceiver *xceiv = fsm->transceiver;
+	struct device *dev = NULL;
+
+	if (!xceiv->host) {
+		return;
+	}
+
+	dev = xceiv->host->controller;
+
+	fsl_otg_drv_vbus(dev->platform_data, on);
+
+}
+
 static struct otg_fsm_ops fsl_otg_ops = {
 	.chrg_vbus = fsl_otg_chrg_vbus,
-	.drv_vbus = fsl_otg_drv_vbus,
+	.drv_vbus = fsl_otg_fsm_drv_vbus,
 	.loc_conn = fsl_otg_loc_conn,
 	.loc_sof = fsl_otg_loc_sof,
 	.start_pulse = fsl_otg_start_pulse,
diff --git a/drivers/usb/serial/ark3116.c b/drivers/usb/serial/ark3116.c
index aec61880f36c..1a50beb32029 100644
--- a/drivers/usb/serial/ark3116.c
+++ b/drivers/usb/serial/ark3116.c
@@ -35,11 +35,6 @@ static struct usb_device_id id_table [] = {
 };
 MODULE_DEVICE_TABLE(usb, id_table);
 
-struct ark3116_private {
-	spinlock_t lock;
-	u8 termios_initialized;
-};
-
 static inline void ARK3116_SND(struct usb_serial *serial, int seq,
 			       __u8 request, __u8 requesttype,
 			       __u16 value, __u16 index)
@@ -82,22 +77,11 @@ static inline void ARK3116_RCV_QUIET(struct usb_serial *serial,
 static int ark3116_attach(struct usb_serial *serial)
 {
 	char *buf;
-	struct ark3116_private *priv;
-	int i;
-
-	for (i = 0; i < serial->num_ports; ++i) {
-		priv = kzalloc(sizeof(struct ark3116_private), GFP_KERNEL);
-		if (!priv)
-			goto cleanup;
-		spin_lock_init(&priv->lock);
-
-		usb_set_serial_port_data(serial->port[i], priv);
-	}
 
 	buf = kmalloc(1, GFP_KERNEL);
 	if (!buf) {
 		dbg("error kmalloc -> out of mem?");
-		goto cleanup;
+		return -ENOMEM;
 	}
 
 	/* 3 */
@@ -149,13 +133,16 @@ static int ark3116_attach(struct usb_serial *serial)
 
 	kfree(buf);
 	return 0;
+}
 
-cleanup:
-	for (--i; i >= 0; --i) {
-		kfree(usb_get_serial_port_data(serial->port[i]));
-		usb_set_serial_port_data(serial->port[i], NULL);
-	}
-	return -ENOMEM;
+static void ark3116_init_termios(struct tty_struct *tty)
+{
+	struct ktermios *termios = tty->termios;
+	*termios = tty_std_termios;
+	termios->c_cflag = B9600 | CS8
+				      | CREAD | HUPCL | CLOCAL;
+	termios->c_ispeed = 9600;
+	termios->c_ospeed = 9600;
 }
 
 static void ark3116_set_termios(struct tty_struct *tty,
@@ -163,10 +150,8 @@ static void ark3116_set_termios(struct tty_struct *tty,
 				struct ktermios *old_termios)
 {
 	struct usb_serial *serial = port->serial;
-	struct ark3116_private *priv = usb_get_serial_port_data(port);
 	struct ktermios *termios = tty->termios;
 	unsigned int cflag = termios->c_cflag;
-	unsigned long flags;
 	int baud;
 	int ark3116_baud;
 	char *buf;
@@ -176,16 +161,6 @@ static void ark3116_set_termios(struct tty_struct *tty,
 
 	dbg("%s - port %d", __func__, port->number);
 
-	spin_lock_irqsave(&priv->lock, flags);
-	if (!priv->termios_initialized) {
-		*termios = tty_std_termios;
-		termios->c_cflag = B9600 | CS8
-					      | CREAD | HUPCL | CLOCAL;
-		termios->c_ispeed = 9600;
-		termios->c_ospeed = 9600;
-		priv->termios_initialized = 1;
-	}
-	spin_unlock_irqrestore(&priv->lock, flags);
 
 	cflag = termios->c_cflag;
 	termios->c_cflag &= ~(CMSPAR|CRTSCTS);
@@ -455,6 +430,7 @@ static struct usb_serial_driver ark3116_device = {
 	.num_ports =		1,
 	.attach =		ark3116_attach,
 	.set_termios =		ark3116_set_termios,
+	.init_termios =		ark3116_init_termios,
 	.ioctl =		ark3116_ioctl,
 	.tiocmget =		ark3116_tiocmget,
 	.open =			ark3116_open,
diff --git a/drivers/usb/serial/console.c b/drivers/usb/serial/console.c
index 0e4f2e41ace5..3e49b2ed0266 100644
--- a/drivers/usb/serial/console.c
+++ b/drivers/usb/serial/console.c
@@ -16,6 +16,7 @@
 #include <linux/slab.h>
 #include <linux/tty.h>
 #include <linux/console.h>
+#include <linux/serial.h>
 #include <linux/usb.h>
 #include <linux/usb/serial.h>
 
@@ -63,7 +64,7 @@ static int usb_console_setup(struct console *co, char *options)
 	char *s;
 	struct usb_serial *serial;
 	struct usb_serial_port *port;
-	int retval = 0;
+	int retval;
 	struct tty_struct *tty = NULL;
 	struct ktermios *termios = NULL, dummy;
 
@@ -116,13 +117,17 @@ static int usb_console_setup(struct console *co, char *options)
 		return -ENODEV;
 	}
 
-	port = serial->port[0];
+	retval = usb_autopm_get_interface(serial->interface);
+	if (retval)
+		goto error_get_interface;
+
+	port = serial->port[co->index - serial->minor];
 	tty_port_tty_set(&port->port, NULL);
 
 	info->port = port;
 
 	++port->port.count;
-	if (port->port.count == 1) {
+	if (!test_bit(ASYNCB_INITIALIZED, &port->port.flags)) {
 		if (serial->type->set_termios) {
 			/*
 			 * allocate a fake tty so the driver can initialize
@@ -168,6 +173,7 @@ static int usb_console_setup(struct console *co, char *options)
 			kfree(termios);
 			kfree(tty);
 		}
+		set_bit(ASYNCB_INITIALIZED, &port->port.flags);
 	}
 	/* Now that any required fake tty operations are completed restore
 	 * the tty port count */
@@ -175,18 +181,22 @@ static int usb_console_setup(struct console *co, char *options)
 	/* The console is special in terms of closing the device so
 	 * indicate this port is now acting as a system console. */
 	port->console = 1;
-	retval = 0;
 
-out:
+	mutex_unlock(&serial->disc_mutex);
 	return retval;
-free_termios:
+
+ free_termios:
 	kfree(termios);
 	tty_port_tty_set(&port->port, NULL);
-free_tty:
+ free_tty:
 	kfree(tty);
-reset_open_count:
+ reset_open_count:
 	port->port.count = 0;
-	goto out;
+	usb_autopm_put_interface(serial->interface);
+ error_get_interface:
+	usb_serial_put(serial);
+	mutex_unlock(&serial->disc_mutex);
+	return retval;
 }
 
 static void usb_console_write(struct console *co,
diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c
index 985cbcf48bda..2367325e80b0 100644
--- a/drivers/usb/serial/cp210x.c
+++ b/drivers/usb/serial/cp210x.c
@@ -51,6 +51,8 @@ static int cp210x_tiocmset_port(struct usb_serial_port *port, struct file *,
 static void cp210x_break_ctl(struct tty_struct *, int);
 static int cp210x_startup(struct usb_serial *);
 static void cp210x_disconnect(struct usb_serial *);
+static void cp210x_dtr_rts(struct usb_serial_port *p, int on);
+static int cp210x_carrier_raised(struct usb_serial_port *p);
 
 static int debug;
 
@@ -114,6 +116,7 @@ static struct usb_device_id id_table [] = {
 	{ USB_DEVICE(0x166A, 0x0303) }, /* Clipsal 5500PCU C-Bus USB interface */
 	{ USB_DEVICE(0x16D6, 0x0001) }, /* Jablotron serial interface */
 	{ USB_DEVICE(0x18EF, 0xE00F) }, /* ELV USB-I2C-Interface */
+	{ USB_DEVICE(0x413C, 0x9500) }, /* DW700 GPS USB interface */
 	{ } /* Terminating Entry */
 };
 
@@ -143,6 +146,8 @@ static struct usb_serial_driver cp210x_device = {
 	.tiocmset		= cp210x_tiocmset,
 	.attach			= cp210x_startup,
 	.disconnect		= cp210x_disconnect,
+	.dtr_rts		= cp210x_dtr_rts,
+	.carrier_raised		= cp210x_carrier_raised
 };
 
 /* Config request types */
@@ -399,12 +404,6 @@ static int cp210x_open(struct tty_struct *tty, struct usb_serial_port *port,
 
 	/* Configure the termios structure */
 	cp210x_get_termios(tty, port);
-
-	/* Set the DTR and RTS pins low */
-	cp210x_tiocmset_port(tty ? (struct usb_serial_port *) tty->driver_data
-			: port,
-		NULL, TIOCM_DTR | TIOCM_RTS, 0);
-
 	return 0;
 }
 
@@ -753,6 +752,14 @@ static int cp210x_tiocmset_port(struct usb_serial_port *port, struct file *file,
 	return cp210x_set_config(port, CP210X_SET_MHS, &control, 2);
 }
 
+static void cp210x_dtr_rts(struct usb_serial_port *p, int on)
+{
+	if (on)
+		cp210x_tiocmset_port(p, NULL,  TIOCM_DTR|TIOCM_RTS, 0);
+	else
+		cp210x_tiocmset_port(p, NULL,  0, TIOCM_DTR|TIOCM_RTS);
+}
+
 static int cp210x_tiocmget (struct tty_struct *tty, struct file *file)
 {
 	struct usb_serial_port *port = tty->driver_data;
@@ -775,6 +782,15 @@ static int cp210x_tiocmget (struct tty_struct *tty, struct file *file)
 	return result;
 }
 
+static int cp210x_carrier_raised(struct usb_serial_port *p)
+{
+	unsigned int control;
+	cp210x_get_config(p, CP210X_GET_MDMSTS, &control, 1);
+	if (control & CONTROL_DCD)
+		return 1;
+	return 0;
+}
+
 static void cp210x_break_ctl (struct tty_struct *tty, int break_state)
 {
 	struct usb_serial_port *port = tty->driver_data;
diff --git a/drivers/usb/serial/cypress_m8.c b/drivers/usb/serial/cypress_m8.c
index 59adfe123110..27b5a271fe4a 100644
--- a/drivers/usb/serial/cypress_m8.c
+++ b/drivers/usb/serial/cypress_m8.c
@@ -659,15 +659,7 @@ static int cypress_open(struct tty_struct *tty,
 	spin_unlock_irqrestore(&priv->lock, flags);
 
 	/* Set termios */
-	result = cypress_write(tty, port, NULL, 0);
-
-	if (result) {
-		dev_err(&port->dev,
-			"%s - failed setting the control lines - error %d\n",
-							__func__, result);
-		return result;
-	} else
-		dbg("%s - success setting the control lines", __func__);
+	cypress_send(port);
 
 	if (tty)
 		cypress_set_termios(tty, port, &priv->tmp_termios);
@@ -1005,6 +997,8 @@ static void cypress_set_termios(struct tty_struct *tty,
 	dbg("%s - port %d", __func__, port->number);
 
 	spin_lock_irqsave(&priv->lock, flags);
+	/* We can't clean this one up as we don't know the device type
+	   early enough */
 	if (!priv->termios_initialized) {
 		if (priv->chiptype == CT_EARTHMATE) {
 			*(tty->termios) = tty_std_termios;
diff --git a/drivers/usb/serial/digi_acceleport.c b/drivers/usb/serial/digi_acceleport.c
index f4808091c47c..9bd82b487005 100644
--- a/drivers/usb/serial/digi_acceleport.c
+++ b/drivers/usb/serial/digi_acceleport.c
@@ -899,16 +899,16 @@ static void digi_rx_unthrottle(struct tty_struct *tty)
 
 	spin_lock_irqsave(&priv->dp_port_lock, flags);
 
-	/* turn throttle off */
-	priv->dp_throttled = 0;
-	priv->dp_throttle_restart = 0;
-
 	/* restart read chain */
 	if (priv->dp_throttle_restart) {
 		port->read_urb->dev = port->serial->dev;
 		ret = usb_submit_urb(port->read_urb, GFP_ATOMIC);
 	}
 
+	/* turn throttle off */
+	priv->dp_throttled = 0;
+	priv->dp_throttle_restart = 0;
+
 	spin_unlock_irqrestore(&priv->dp_port_lock, flags);
 
 	if (ret)
diff --git a/drivers/usb/serial/empeg.c b/drivers/usb/serial/empeg.c
index 80cb3471adbe..3433f9db4418 100644
--- a/drivers/usb/serial/empeg.c
+++ b/drivers/usb/serial/empeg.c
@@ -90,8 +90,7 @@ static int  empeg_chars_in_buffer(struct tty_struct *tty);
 static void empeg_throttle(struct tty_struct *tty);
 static void empeg_unthrottle(struct tty_struct *tty);
 static int  empeg_startup(struct usb_serial *serial);
-static void empeg_set_termios(struct tty_struct *tty,
-		struct usb_serial_port *port, struct ktermios *old_termios);
+static void empeg_init_termios(struct tty_struct *tty);
 static void empeg_write_bulk_callback(struct urb *urb);
 static void empeg_read_bulk_callback(struct urb *urb);
 
@@ -123,7 +122,7 @@ static struct usb_serial_driver empeg_device = {
 	.throttle =		empeg_throttle,
 	.unthrottle =		empeg_unthrottle,
 	.attach =		empeg_startup,
-	.set_termios =		empeg_set_termios,
+	.init_termios =		empeg_init_termios,
 	.write =		empeg_write,
 	.write_room =		empeg_write_room,
 	.chars_in_buffer =	empeg_chars_in_buffer,
@@ -150,9 +149,6 @@ static int empeg_open(struct tty_struct *tty, struct usb_serial_port *port,
 
 	dbg("%s - port %d", __func__, port->number);
 
-	/* Force default termio settings */
-	empeg_set_termios(tty, port, NULL) ;
-
 	bytes_in = 0;
 	bytes_out = 0;
 
@@ -425,11 +421,9 @@ static int  empeg_startup(struct usb_serial *serial)
 }
 
 
-static void empeg_set_termios(struct tty_struct *tty,
-		struct usb_serial_port *port, struct ktermios *old_termios)
+static void empeg_init_termios(struct tty_struct *tty)
 {
 	struct ktermios *termios = tty->termios;
-	dbg("%s - port %d", __func__, port->number);
 
 	/*
 	 * The empeg-car player wants these particular tty settings.
diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c
index 8fec5d4455c9..84102014ed5b 100644
--- a/drivers/usb/serial/ftdi_sio.c
+++ b/drivers/usb/serial/ftdi_sio.c
@@ -76,13 +76,7 @@ struct ftdi_private {
 	unsigned long last_dtr_rts;	/* saved modem control outputs */
 	wait_queue_head_t delta_msr_wait; /* Used for TIOCMIWAIT */
 	char prev_status, diff_status;        /* Used for TIOCMIWAIT */
-	__u8 rx_flags;		/* receive state flags (throttling) */
-	spinlock_t rx_lock;	/* spinlock for receive state */
-	struct delayed_work rx_work;
 	struct usb_serial_port *port;
-	int rx_processed;
-	unsigned long rx_bytes;
-
 	__u16 interface;	/* FT2232C, FT2232H or FT4232H port interface
 				   (0 for FT232/245) */
 
@@ -176,6 +170,9 @@ static struct usb_device_id id_table_combined [] = {
 	{ USB_DEVICE(FTDI_VID, FTDI_MICRO_CHAMELEON_PID) },
 	{ USB_DEVICE(FTDI_VID, FTDI_RELAIS_PID) },
 	{ USB_DEVICE(FTDI_VID, FTDI_OPENDCC_PID) },
+	{ USB_DEVICE(FTDI_VID, FTDI_OPENDCC_SNIFFER_PID) },
+	{ USB_DEVICE(FTDI_VID, FTDI_OPENDCC_THROTTLE_PID) },
+	{ USB_DEVICE(FTDI_VID, FTDI_OPENDCC_GATEWAY_PID) },
 	{ USB_DEVICE(INTERBIOMETRICS_VID, INTERBIOMETRICS_IOBOARD_PID) },
 	{ USB_DEVICE(INTERBIOMETRICS_VID, INTERBIOMETRICS_MINI_IOBOARD_PID) },
 	{ USB_DEVICE(FTDI_VID, FTDI_SPROG_II) },
@@ -694,6 +691,8 @@ static struct usb_device_id id_table_combined [] = {
 	{ USB_DEVICE(DE_VID, WHT_PID) },
 	{ USB_DEVICE(ADI_VID, ADI_GNICE_PID),
 		.driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
+	{ USB_DEVICE(ADI_VID, ADI_GNICEPLUS_PID),
+		.driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
 	{ USB_DEVICE(JETI_VID, JETI_SPC1201_PID) },
 	{ USB_DEVICE(MARVELL_VID, MARVELL_SHEEVAPLUG_PID),
 		.driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
@@ -702,6 +701,8 @@ static struct usb_device_id id_table_combined [] = {
 	{ USB_DEVICE(BAYER_VID, BAYER_CONTOUR_CABLE_PID) },
 	{ USB_DEVICE(FTDI_VID, MARVELL_OPENRD_PID),
 		.driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
+	{ USB_DEVICE(FTDI_VID, HAMEG_HO820_PID) },
+	{ USB_DEVICE(FTDI_VID, HAMEG_HO870_PID) },
 	{ },					/* Optional parameter entry */
 	{ }					/* Terminating entry */
 };
@@ -730,10 +731,6 @@ static const char *ftdi_chip_name[] = {
 /* Constants for read urb and write urb */
 #define BUFSZ 512
 
-/* rx_flags */
-#define THROTTLED		0x01
-#define ACTUALLY_THROTTLED	0x02
-
 /* Used for TIOCMIWAIT */
 #define FTDI_STATUS_B0_MASK	(FTDI_RS0_CTS | FTDI_RS0_DSR | FTDI_RS0_RI | FTDI_RS0_RLSD)
 #define FTDI_STATUS_B1_MASK	(FTDI_RS_BI)
@@ -757,7 +754,7 @@ static int  ftdi_write_room(struct tty_struct *tty);
 static int  ftdi_chars_in_buffer(struct tty_struct *tty);
 static void ftdi_write_bulk_callback(struct urb *urb);
 static void ftdi_read_bulk_callback(struct urb *urb);
-static void ftdi_process_read(struct work_struct *work);
+static void ftdi_process_read(struct usb_serial_port *port);
 static void ftdi_set_termios(struct tty_struct *tty,
 			struct usb_serial_port *port, struct ktermios *old);
 static int  ftdi_tiocmget(struct tty_struct *tty, struct file *file);
@@ -1228,7 +1225,6 @@ static int set_serial_info(struct tty_struct *tty,
 					(new_serial.flags & ASYNC_FLAGS));
 	priv->custom_divisor = new_serial.custom_divisor;
 
-	tty->low_latency = (priv->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 	write_latency_timer(port);
 
 check_and_exit:
@@ -1521,7 +1517,6 @@ static int ftdi_sio_port_probe(struct usb_serial_port *port)
 	}
 
 	kref_init(&priv->kref);
-	spin_lock_init(&priv->rx_lock);
 	spin_lock_init(&priv->tx_lock);
 	init_waitqueue_head(&priv->delta_msr_wait);
 	/* This will push the characters through immediately rather
@@ -1543,7 +1538,6 @@ static int ftdi_sio_port_probe(struct usb_serial_port *port)
 		port->read_urb->transfer_buffer_length = BUFSZ;
 	}
 
-	INIT_DELAYED_WORK(&priv->rx_work, ftdi_process_read);
 	priv->port = port;
 
 	/* Free port's existing write urb and transfer buffer. */
@@ -1680,6 +1674,26 @@ static int ftdi_sio_port_remove(struct usb_serial_port *port)
 	return 0;
 }
 
+static int ftdi_submit_read_urb(struct usb_serial_port *port, gfp_t mem_flags)
+{
+	struct urb *urb = port->read_urb;
+	struct usb_serial *serial = port->serial;
+	int result;
+
+	usb_fill_bulk_urb(urb, serial->dev,
+			   usb_rcvbulkpipe(serial->dev,
+					port->bulk_in_endpointAddress),
+			   urb->transfer_buffer,
+			   urb->transfer_buffer_length,
+			   ftdi_read_bulk_callback, port);
+	result = usb_submit_urb(urb, mem_flags);
+	if (result)
+		dev_err(&port->dev,
+			"%s - failed submitting read urb, error %d\n",
+							__func__, result);
+	return result;
+}
+
 static int ftdi_open(struct tty_struct *tty,
 			struct usb_serial_port *port, struct file *filp)
 { /* ftdi_open */
@@ -1695,12 +1709,6 @@ static int ftdi_open(struct tty_struct *tty,
 	spin_lock_irqsave(&priv->tx_lock, flags);
 	priv->tx_bytes = 0;
 	spin_unlock_irqrestore(&priv->tx_lock, flags);
-	spin_lock_irqsave(&priv->rx_lock, flags);
-	priv->rx_bytes = 0;
-	spin_unlock_irqrestore(&priv->rx_lock, flags);
-
-	if (tty)
-		tty->low_latency = (priv->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 
 	write_latency_timer(port);
 
@@ -1720,23 +1728,14 @@ static int ftdi_open(struct tty_struct *tty,
 		ftdi_set_termios(tty, port, tty->termios);
 
 	/* Not throttled */
-	spin_lock_irqsave(&priv->rx_lock, flags);
-	priv->rx_flags &= ~(THROTTLED | ACTUALLY_THROTTLED);
-	spin_unlock_irqrestore(&priv->rx_lock, flags);
+	spin_lock_irqsave(&port->lock, flags);
+	port->throttled = 0;
+	port->throttle_req = 0;
+	spin_unlock_irqrestore(&port->lock, flags);
 
 	/* Start reading from the device */
-	priv->rx_processed = 0;
-	usb_fill_bulk_urb(port->read_urb, dev,
-			usb_rcvbulkpipe(dev, port->bulk_in_endpointAddress),
-			port->read_urb->transfer_buffer,
-				port->read_urb->transfer_buffer_length,
-			ftdi_read_bulk_callback, port);
-	result = usb_submit_urb(port->read_urb, GFP_KERNEL);
-	if (result)
-		dev_err(&port->dev,
-			"%s - failed submitting read urb, error %d\n",
-			__func__, result);
-	else
+	result = ftdi_submit_read_urb(port, GFP_KERNEL);
+	if (!result)
 		kref_get(&priv->kref);
 
 	return result;
@@ -1782,10 +1781,6 @@ static void ftdi_close(struct usb_serial_port *port)
 
 	dbg("%s", __func__);
 
-
-	/* cancel any scheduled reading */
-	cancel_delayed_work_sync(&priv->rx_work);
-
 	/* shutdown our bulk read */
 	usb_kill_urb(port->read_urb);
 	kref_put(&priv->kref, ftdi_sio_priv_release);
@@ -1944,7 +1939,7 @@ static void ftdi_write_bulk_callback(struct urb *urb)
 		return;
 	}
 	/* account for transferred data */
-	countback = urb->actual_length;
+	countback = urb->transfer_buffer_length;
 	data_offset = priv->write_offset;
 	if (data_offset > 0) {
 		/* Subtract the control bytes */
@@ -1957,7 +1952,6 @@ static void ftdi_write_bulk_callback(struct urb *urb)
 
 	if (status) {
 		dbg("nonzero write bulk status received: %d", status);
-		return;
 	}
 
 	usb_serial_port_softint(port);
@@ -2008,271 +2002,121 @@ static int ftdi_chars_in_buffer(struct tty_struct *tty)
 	return buffered;
 }
 
-static void ftdi_read_bulk_callback(struct urb *urb)
+static int ftdi_process_packet(struct tty_struct *tty,
+		struct usb_serial_port *port, struct ftdi_private *priv,
+		char *packet, int len)
 {
-	struct usb_serial_port *port = urb->context;
-	struct tty_struct *tty;
-	struct ftdi_private *priv;
-	unsigned long countread;
-	unsigned long flags;
-	int status = urb->status;
-
-	if (urb->number_of_packets > 0) {
-		dev_err(&port->dev, "%s transfer_buffer_length %d "
-			"actual_length %d number of packets %d\n", __func__,
-			urb->transfer_buffer_length,
-			urb->actual_length, urb->number_of_packets);
-		dev_err(&port->dev, "%s transfer_flags %x\n", __func__,
-			urb->transfer_flags);
-	}
+	int i;
+	char status;
+	char flag;
+	char *ch;
 
 	dbg("%s - port %d", __func__, port->number);
 
-	if (port->port.count <= 0)
-		return;
-
-	tty = tty_port_tty_get(&port->port);
-	if (!tty) {
-		dbg("%s - bad tty pointer - exiting", __func__);
-		return;
+	if (len < 2) {
+		dbg("malformed packet");
+		return 0;
 	}
 
-	priv = usb_get_serial_port_data(port);
-	if (!priv) {
-		dbg("%s - bad port private data pointer - exiting", __func__);
-		goto out;
+	/* Compare new line status to the old one, signal if different/
+	   N.B. packet may be processed more than once, but differences
+	   are only processed once.  */
+	status = packet[0] & FTDI_STATUS_B0_MASK;
+	if (status != priv->prev_status) {
+		priv->diff_status |= status ^ priv->prev_status;
+		wake_up_interruptible(&priv->delta_msr_wait);
+		priv->prev_status = status;
 	}
 
-	if (urb != port->read_urb)
-		dev_err(&port->dev, "%s - Not my urb!\n", __func__);
-
-	if (status) {
-		/* This will happen at close every time so it is a dbg not an
-		   err */
-		dbg("(this is ok on close) nonzero read bulk status received: %d", status);
-		goto out;
+	/*
+	 * Although the device uses a bitmask and hence can have multiple
+	 * errors on a packet - the order here sets the priority the error is
+	 * returned to the tty layer.
+	 */
+	flag = TTY_NORMAL;
+	if (packet[1] & FTDI_RS_OE) {
+		flag = TTY_OVERRUN;
+		dbg("OVERRRUN error");
+	}
+	if (packet[1] & FTDI_RS_BI) {
+		flag = TTY_BREAK;
+		dbg("BREAK received");
+		usb_serial_handle_break(port);
+	}
+	if (packet[1] & FTDI_RS_PE) {
+		flag = TTY_PARITY;
+		dbg("PARITY error");
+	}
+	if (packet[1] & FTDI_RS_FE) {
+		flag = TTY_FRAME;
+		dbg("FRAMING error");
 	}
 
-	/* count data bytes, but not status bytes */
-	countread = urb->actual_length;
-	countread -= 2 * DIV_ROUND_UP(countread, priv->max_packet_size);
-	spin_lock_irqsave(&priv->rx_lock, flags);
-	priv->rx_bytes += countread;
-	spin_unlock_irqrestore(&priv->rx_lock, flags);
-
-	ftdi_process_read(&priv->rx_work.work);
-out:
-	tty_kref_put(tty);
-} /* ftdi_read_bulk_callback */
-
+	len -= 2;
+	if (!len)
+		return 0;	/* status only */
+	ch = packet + 2;
+
+	if (!(port->console && port->sysrq) && flag == TTY_NORMAL)
+		tty_insert_flip_string(tty, ch, len);
+	else {
+		for (i = 0; i < len; i++, ch++) {
+			if (!usb_serial_handle_sysrq_char(tty, port, *ch))
+				tty_insert_flip_char(tty, *ch, flag);
+		}
+	}
+	return len;
+}
 
-static void ftdi_process_read(struct work_struct *work)
-{ /* ftdi_process_read */
-	struct ftdi_private *priv =
-		container_of(work, struct ftdi_private, rx_work.work);
-	struct usb_serial_port *port = priv->port;
-	struct urb *urb;
+static void ftdi_process_read(struct usb_serial_port *port)
+{
+	struct urb *urb = port->read_urb;
 	struct tty_struct *tty;
-	char error_flag;
-	unsigned char *data;
-
+	struct ftdi_private *priv = usb_get_serial_port_data(port);
+	char *data = (char *)urb->transfer_buffer;
 	int i;
-	int result;
-	int need_flip;
-	int packet_offset;
-	unsigned long flags;
-
-	dbg("%s - port %d", __func__, port->number);
-
-	if (port->port.count <= 0)
-		return;
+	int len;
+	int count = 0;
 
 	tty = tty_port_tty_get(&port->port);
-	if (!tty) {
-		dbg("%s - bad tty pointer - exiting", __func__);
+	if (!tty)
 		return;
-	}
 
-	priv = usb_get_serial_port_data(port);
-	if (!priv) {
-		dbg("%s - bad port private data pointer - exiting", __func__);
-		goto out;
-	}
-
-	urb = port->read_urb;
-	if (!urb) {
-		dbg("%s - bad read_urb pointer - exiting", __func__);
-		goto out;
+	for (i = 0; i < urb->actual_length; i += priv->max_packet_size) {
+		len = min_t(int, urb->actual_length - i, priv->max_packet_size);
+		count += ftdi_process_packet(tty, port, priv, &data[i], len);
 	}
 
-	data = urb->transfer_buffer;
-
-	if (priv->rx_processed) {
-		dbg("%s - already processed: %d bytes, %d remain", __func__,
-				priv->rx_processed,
-				urb->actual_length - priv->rx_processed);
-	} else {
-		/* The first two bytes of every read packet are status */
-		if (urb->actual_length > 2)
-			usb_serial_debug_data(debug, &port->dev, __func__,
-						urb->actual_length, data);
-		else
-			dbg("Status only: %03oo %03oo", data[0], data[1]);
-	}
-
-
-	/* TO DO -- check for hung up line and handle appropriately: */
-	/*   send hangup  */
-	/* See acm.c - you do a tty_hangup  - eg tty_hangup(tty) */
-	/* if CD is dropped and the line is not CLOCAL then we should hangup */
-
-	need_flip = 0;
-	for (packet_offset = priv->rx_processed;
-		packet_offset < urb->actual_length; packet_offset += priv->max_packet_size) {
-		int length;
-
-		/* Compare new line status to the old one, signal if different/
-		   N.B. packet may be processed more than once, but differences
-		   are only processed once.  */
-		char new_status = data[packet_offset + 0] &
-						FTDI_STATUS_B0_MASK;
-		if (new_status != priv->prev_status) {
-			priv->diff_status |=
-				new_status ^ priv->prev_status;
-			wake_up_interruptible(&priv->delta_msr_wait);
-			priv->prev_status = new_status;
-		}
-
-		length = min_t(u32, priv->max_packet_size, urb->actual_length-packet_offset)-2;
-		if (length < 0) {
-			dev_err(&port->dev, "%s - bad packet length: %d\n",
-				__func__, length+2);
-			length = 0;
-		}
-
-		if (priv->rx_flags & THROTTLED) {
-			dbg("%s - throttled", __func__);
-			break;
-		}
-		if (tty_buffer_request_room(tty, length) < length) {
-			/* break out & wait for throttling/unthrottling to
-			   happen */
-			dbg("%s - receive room low", __func__);
-			break;
-		}
-
-		/* Handle errors and break */
-		error_flag = TTY_NORMAL;
-		/* Although the device uses a bitmask and hence can have
-		   multiple errors on a packet - the order here sets the
-		   priority the error is returned to the tty layer  */
-
-		if (data[packet_offset+1] & FTDI_RS_OE) {
-			error_flag = TTY_OVERRUN;
-			dbg("OVERRRUN error");
-		}
-		if (data[packet_offset+1] & FTDI_RS_BI) {
-			error_flag = TTY_BREAK;
-			dbg("BREAK received");
-			usb_serial_handle_break(port);
-		}
-		if (data[packet_offset+1] & FTDI_RS_PE) {
-			error_flag = TTY_PARITY;
-			dbg("PARITY error");
-		}
-		if (data[packet_offset+1] & FTDI_RS_FE) {
-			error_flag = TTY_FRAME;
-			dbg("FRAMING error");
-		}
-		if (length > 0) {
-			for (i = 2; i < length+2; i++) {
-				/* Note that the error flag is duplicated for
-				   every character received since we don't know
-				   which character it applied to */
-				if (!usb_serial_handle_sysrq_char(tty, port,
-						data[packet_offset + i]))
-					tty_insert_flip_char(tty,
-						data[packet_offset + i],
-						error_flag);
-			}
-			need_flip = 1;
-		}
-
-#ifdef NOT_CORRECT_BUT_KEEPING_IT_FOR_NOW
-		/* if a parity error is detected you get status packets forever
-		   until a character is sent without a parity error.
-		   This doesn't work well since the application receives a
-		   never ending stream of bad data - even though new data
-		   hasn't been sent. Therefore I (bill) have taken this out.
-		   However - this might make sense for framing errors and so on
-		   so I am leaving the code in for now.
-		*/
-		else {
-			if (error_flag != TTY_NORMAL) {
-				dbg("error_flag is not normal");
-				/* In this case it is just status - if that is
-				   an error send a bad character */
-				if (tty->flip.count >= TTY_FLIPBUF_SIZE)
-					tty_flip_buffer_push(tty);
-				tty_insert_flip_char(tty, 0xff, error_flag);
-				need_flip = 1;
-			}
-		}
-#endif
-	} /* "for(packet_offset=0..." */
-
-	/* Low latency */
-	if (need_flip)
+	if (count)
 		tty_flip_buffer_push(tty);
+	tty_kref_put(tty);
+}
 
-	if (packet_offset < urb->actual_length) {
-		/* not completely processed - record progress */
-		priv->rx_processed = packet_offset;
-		dbg("%s - incomplete, %d bytes processed, %d remain",
-				__func__, packet_offset,
-				urb->actual_length - packet_offset);
-		/* check if we were throttled while processing */
-		spin_lock_irqsave(&priv->rx_lock, flags);
-		if (priv->rx_flags & THROTTLED) {
-			priv->rx_flags |= ACTUALLY_THROTTLED;
-			spin_unlock_irqrestore(&priv->rx_lock, flags);
-			dbg("%s - deferring remainder until unthrottled",
-					__func__);
-			goto out;
-		}
-		spin_unlock_irqrestore(&priv->rx_lock, flags);
-		/* if the port is closed stop trying to read */
-		if (port->port.count > 0)
-			/* delay processing of remainder */
-			schedule_delayed_work(&priv->rx_work, 1);
-		else
-			dbg("%s - port is closed", __func__);
-		goto out;
-	}
-
-	/* urb is completely processed */
-	priv->rx_processed = 0;
+static void ftdi_read_bulk_callback(struct urb *urb)
+{
+	struct usb_serial_port *port = urb->context;
+	unsigned long flags;
 
-	/* if the port is closed stop trying to read */
-	if (port->port.count > 0) {
-		/* Continue trying to always read  */
-		usb_fill_bulk_urb(port->read_urb, port->serial->dev,
-			usb_rcvbulkpipe(port->serial->dev,
-					port->bulk_in_endpointAddress),
-			port->read_urb->transfer_buffer,
-			port->read_urb->transfer_buffer_length,
-			ftdi_read_bulk_callback, port);
+	dbg("%s - port %d", __func__, port->number);
 
-		result = usb_submit_urb(port->read_urb, GFP_ATOMIC);
-		if (result)
-			dev_err(&port->dev,
-				"%s - failed resubmitting read urb, error %d\n",
-				__func__, result);
+	if (urb->status) {
+		dbg("%s - nonzero read bulk status received: %d",
+						__func__, urb->status);
+		return;
 	}
-out:
-	tty_kref_put(tty);
-} /* ftdi_process_read */
 
+	usb_serial_debug_data(debug, &port->dev, __func__,
+				urb->actual_length, urb->transfer_buffer);
+	ftdi_process_read(port);
+
+	spin_lock_irqsave(&port->lock, flags);
+	port->throttled = port->throttle_req;
+	if (!port->throttled) {
+		spin_unlock_irqrestore(&port->lock, flags);
+		ftdi_submit_read_urb(port, GFP_ATOMIC);
+	} else
+		spin_unlock_irqrestore(&port->lock, flags);
+}
 
 static void ftdi_break_ctl(struct tty_struct *tty, int break_state)
 {
@@ -2604,33 +2448,31 @@ static int ftdi_ioctl(struct tty_struct *tty, struct file *file,
 static void ftdi_throttle(struct tty_struct *tty)
 {
 	struct usb_serial_port *port = tty->driver_data;
-	struct ftdi_private *priv = usb_get_serial_port_data(port);
 	unsigned long flags;
 
 	dbg("%s - port %d", __func__, port->number);
 
-	spin_lock_irqsave(&priv->rx_lock, flags);
-	priv->rx_flags |= THROTTLED;
-	spin_unlock_irqrestore(&priv->rx_lock, flags);
+	spin_lock_irqsave(&port->lock, flags);
+	port->throttle_req = 1;
+	spin_unlock_irqrestore(&port->lock, flags);
 }
 
-
-static void ftdi_unthrottle(struct tty_struct *tty)
+void ftdi_unthrottle(struct tty_struct *tty)
 {
 	struct usb_serial_port *port = tty->driver_data;
-	struct ftdi_private *priv = usb_get_serial_port_data(port);
-	int actually_throttled;
+	int was_throttled;
 	unsigned long flags;
 
 	dbg("%s - port %d", __func__, port->number);
 
-	spin_lock_irqsave(&priv->rx_lock, flags);
-	actually_throttled = priv->rx_flags & ACTUALLY_THROTTLED;
-	priv->rx_flags &= ~(THROTTLED | ACTUALLY_THROTTLED);
-	spin_unlock_irqrestore(&priv->rx_lock, flags);
+	spin_lock_irqsave(&port->lock, flags);
+	was_throttled = port->throttled;
+	port->throttled = port->throttle_req = 0;
+	spin_unlock_irqrestore(&port->lock, flags);
 
-	if (actually_throttled)
-		schedule_delayed_work(&priv->rx_work, 0);
+	/* Resubmit urb if throttled and open. */
+	if (was_throttled && test_bit(ASYNCB_INITIALIZED, &port->port.flags))
+		ftdi_submit_read_urb(port, GFP_KERNEL);
 }
 
 static int __init ftdi_init(void)
diff --git a/drivers/usb/serial/ftdi_sio.h b/drivers/usb/serial/ftdi_sio.h
index 8c92b88166ae..6f31e0d71898 100644
--- a/drivers/usb/serial/ftdi_sio.h
+++ b/drivers/usb/serial/ftdi_sio.h
@@ -81,6 +81,9 @@
 
 /* OpenDCC (www.opendcc.de) product id */
 #define FTDI_OPENDCC_PID	0xBFD8
+#define FTDI_OPENDCC_SNIFFER_PID	0xBFD9
+#define FTDI_OPENDCC_THROTTLE_PID	0xBFDA
+#define FTDI_OPENDCC_GATEWAY_PID	0xBFDB
 
 /* Sprog II (Andrew Crosland's SprogII DCC interface) */
 #define FTDI_SPROG_II		0xF0C8
@@ -930,6 +933,7 @@
  */
 #define ADI_VID 		0x0456
 #define ADI_GNICE_PID 		0xF000
+#define ADI_GNICEPLUS_PID 	0xF001
 
 /*
  * JETI SPECTROMETER SPECBOS 1201
@@ -968,6 +972,12 @@
 #define MARVELL_OPENRD_PID	0x9e90
 
 /*
+ * Hameg HO820 and HO870 interface (using VID 0x0403)
+ */
+#define        HAMEG_HO820_PID         0xed74
+#define        HAMEG_HO870_PID         0xed71
+
+/*
  *   BmRequestType:  1100 0000b
  *   bRequest:       FTDI_E2_READ
  *   wValue:         0
diff --git a/drivers/usb/serial/generic.c b/drivers/usb/serial/generic.c
index ce57f6a32bdf..6463fee644b9 100644
--- a/drivers/usb/serial/generic.c
+++ b/drivers/usb/serial/generic.c
@@ -480,6 +480,8 @@ void usb_serial_generic_write_bulk_callback(struct urb *urb)
 	dbg("%s - port %d", __func__, port->number);
 
 	if (port->serial->type->max_in_flight_urbs) {
+		kfree(urb->transfer_buffer);
+
 		spin_lock_irqsave(&port->lock, flags);
 		--port->urbs_in_flight;
 		port->tx_bytes_flight -= urb->transfer_buffer_length;
@@ -530,7 +532,7 @@ void usb_serial_generic_unthrottle(struct tty_struct *tty)
 
 	if (was_throttled) {
 		/* Resume reading from device */
-		usb_serial_generic_resubmit_read_urb(port, GFP_KERNEL);
+		flush_and_resubmit_read_urb(port);
 	}
 }
 
diff --git a/drivers/usb/serial/ipaq.c b/drivers/usb/serial/ipaq.c
index 2545d45ce16f..c4d02064e5f1 100644
--- a/drivers/usb/serial/ipaq.c
+++ b/drivers/usb/serial/ipaq.c
@@ -971,6 +971,15 @@ static int ipaq_calc_num_ports(struct usb_serial *serial)
 static int ipaq_startup(struct usb_serial *serial)
 {
 	dbg("%s", __func__);
+
+	/* Some of the devices in ipaq_id_table[] are composite, and we
+	 * shouldn't bind to all the interfaces.  This test will rule out
+	 * some obviously invalid possibilities.
+	 */
+	if (serial->num_bulk_in < serial->num_ports ||
+			serial->num_bulk_out < serial->num_ports)
+		return -ENODEV;
+
 	if (serial->dev->actconfig->desc.bConfigurationValue != 1) {
 		/*
 		 * FIXME: HP iPaq rx3715, possibly others, have 1 config that
diff --git a/drivers/usb/serial/iuu_phoenix.c b/drivers/usb/serial/iuu_phoenix.c
index 96873a7a32b0..af6df6c788b9 100644
--- a/drivers/usb/serial/iuu_phoenix.c
+++ b/drivers/usb/serial/iuu_phoenix.c
@@ -71,7 +71,6 @@ struct iuu_private {
 	spinlock_t lock;	/* store irq state */
 	wait_queue_head_t delta_msr_wait;
 	u8 line_status;
-	u8 termios_initialized;
 	int tiostatus;		/* store IUART SIGNAL for tiocmget call */
 	u8 reset;		/* if 1 reset is needed */
 	int poll;		/* number of poll */
@@ -1018,6 +1017,18 @@ static void iuu_close(struct usb_serial_port *port)
 	}
 }
 
+static void iuu_init_termios(struct tty_struct *tty)
+{
+	*(tty->termios) = tty_std_termios;
+	tty->termios->c_cflag = CLOCAL | CREAD | CS8 | B9600
+				| TIOCM_CTS | CSTOPB | PARENB;
+	tty->termios->c_ispeed = 9600;
+	tty->termios->c_ospeed = 9600;
+	tty->termios->c_lflag = 0;
+	tty->termios->c_oflag = 0;
+	tty->termios->c_iflag = 0;
+}
+
 static int iuu_open(struct tty_struct *tty,
 			struct usb_serial_port *port, struct file *filp)
 {
@@ -1025,7 +1036,6 @@ static int iuu_open(struct tty_struct *tty,
 	u8 *buf;
 	int result;
 	u32 actual;
-	unsigned long flags;
 	struct iuu_private *priv = usb_get_serial_port_data(port);
 
 	dbg("%s -  port %d", __func__, port->number);
@@ -1064,21 +1074,7 @@ static int iuu_open(struct tty_struct *tty,
 			  port->bulk_in_buffer, 512,
 			  NULL, NULL);
 
-	/* set the termios structure */
-	spin_lock_irqsave(&priv->lock, flags);
-	if (tty && !priv->termios_initialized) {
-		*(tty->termios) = tty_std_termios;
-		tty->termios->c_cflag = CLOCAL | CREAD | CS8 | B9600
-					| TIOCM_CTS | CSTOPB | PARENB;
-		tty->termios->c_ispeed = 9600;
-		tty->termios->c_ospeed = 9600;
-		tty->termios->c_lflag = 0;
-		tty->termios->c_oflag = 0;
-		tty->termios->c_iflag = 0;
-		priv->termios_initialized = 1;
-		priv->poll = 0;
-	 }
-	spin_unlock_irqrestore(&priv->lock, flags);
+	priv->poll = 0;
 
 	/* initialize writebuf */
 #define FISH(a, b, c, d) do { \
@@ -1201,6 +1197,7 @@ static struct usb_serial_driver iuu_device = {
 	.tiocmget = iuu_tiocmget,
 	.tiocmset = iuu_tiocmset,
 	.set_termios = iuu_set_termios,
+	.init_termios = iuu_init_termios,
 	.attach = iuu_startup,
 	.release = iuu_release,
 };
diff --git a/drivers/usb/serial/kobil_sct.c b/drivers/usb/serial/kobil_sct.c
index 6db0e561f680..46d47d1463c9 100644
--- a/drivers/usb/serial/kobil_sct.c
+++ b/drivers/usb/serial/kobil_sct.c
@@ -85,7 +85,7 @@ static void kobil_read_int_callback(struct urb *urb);
 static void kobil_write_callback(struct urb *purb);
 static void kobil_set_termios(struct tty_struct *tty,
 			struct usb_serial_port *port, struct ktermios *old);
-
+static void kobil_init_termios(struct tty_struct *tty);
 
 static struct usb_device_id id_table [] = {
 	{ USB_DEVICE(KOBIL_VENDOR_ID, KOBIL_ADAPTER_B_PRODUCT_ID) },
@@ -120,6 +120,7 @@ static struct usb_serial_driver kobil_device = {
 	.release =		kobil_release,
 	.ioctl =		kobil_ioctl,
 	.set_termios =		kobil_set_termios,
+	.init_termios =		kobil_init_termios,
 	.tiocmget =		kobil_tiocmget,
 	.tiocmset =		kobil_tiocmset,
 	.open =			kobil_open,
@@ -210,6 +211,15 @@ static void kobil_release(struct usb_serial *serial)
 		kfree(usb_get_serial_port_data(serial->port[i]));
 }
 
+static void kobil_init_termios(struct tty_struct *tty)
+{
+	/* Default to echo off and other sane device settings */
+	tty->termios->c_lflag = 0;
+	tty->termios->c_lflag &= ~(ISIG | ICANON | ECHO | IEXTEN | XCASE);
+	tty->termios->c_iflag = IGNBRK | IGNPAR | IXOFF;
+	/* do NOT translate CR to CR-NL (0x0A -> 0x0A 0x0D) */
+	tty->termios->c_oflag &= ~ONLCR;
+}
 
 static int kobil_open(struct tty_struct *tty,
 			struct usb_serial_port *port, struct file *filp)
@@ -226,16 +236,6 @@ static int kobil_open(struct tty_struct *tty,
 	/* someone sets the dev to 0 if the close method has been called */
 	port->interrupt_in_urb->dev = port->serial->dev;
 
-	if (tty) {
-
-		/* Default to echo off and other sane device settings */
-		tty->termios->c_lflag = 0;
-		tty->termios->c_lflag &= ~(ISIG | ICANON | ECHO | IEXTEN |
-								 XCASE);
-		tty->termios->c_iflag = IGNBRK | IGNPAR | IXOFF;
-		/* do NOT translate CR to CR-NL (0x0A -> 0x0A 0x0D) */
-		tty->termios->c_oflag &= ~ONLCR;
-	}
 	/* allocate memory for transfer buffer */
 	transfer_buffer = kzalloc(transfer_buffer_length, GFP_KERNEL);
 	if (!transfer_buffer)
diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index c784ddbe7b61..c7b42ca00d56 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -166,6 +166,7 @@ static int  option_resume(struct usb_serial *serial);
 #define HUAWEI_PRODUCT_E143D			0x143D
 #define HUAWEI_PRODUCT_E143E			0x143E
 #define HUAWEI_PRODUCT_E143F			0x143F
+#define HUAWEI_PRODUCT_E14AC			0x14AC
 
 #define QUANTA_VENDOR_ID			0x0408
 #define QUANTA_PRODUCT_Q101			0xEA02
@@ -292,6 +293,7 @@ static int  option_resume(struct usb_serial *serial);
 
 #define TELIT_VENDOR_ID				0x1bc7
 #define TELIT_PRODUCT_UC864E			0x1003
+#define TELIT_PRODUCT_UC864G			0x1004
 
 /* ZTE PRODUCTS */
 #define ZTE_VENDOR_ID				0x19d2
@@ -300,12 +302,14 @@ static int  option_resume(struct usb_serial *serial);
 #define ZTE_PRODUCT_MF626			0x0031
 #define ZTE_PRODUCT_CDMA_TECH			0xfffe
 #define ZTE_PRODUCT_AC8710			0xfff1
+#define ZTE_PRODUCT_AC2726			0xfff5
 
 #define BENQ_VENDOR_ID				0x04a5
 #define BENQ_PRODUCT_H10			0x4068
 
 #define DLINK_VENDOR_ID				0x1186
 #define DLINK_PRODUCT_DWM_652			0x3e04
+#define DLINK_PRODUCT_DWM_652_U5		0xce16
 
 #define QISDA_VENDOR_ID				0x1da5
 #define QISDA_PRODUCT_H21_4512			0x4512
@@ -313,10 +317,14 @@ static int  option_resume(struct usb_serial *serial);
 #define QISDA_PRODUCT_H20_4515			0x4515
 #define QISDA_PRODUCT_H20_4519			0x4519
 
+/* TLAYTECH PRODUCTS */
+#define TLAYTECH_VENDOR_ID			0x20B9
+#define TLAYTECH_PRODUCT_TEU800			0x1682
 
 /* TOSHIBA PRODUCTS */
 #define TOSHIBA_VENDOR_ID			0x0930
 #define TOSHIBA_PRODUCT_HSDPA_MINICARD		0x1302
+#define TOSHIBA_PRODUCT_G450			0x0d45
 
 #define ALINK_VENDOR_ID				0x1e0e
 #define ALINK_PRODUCT_3GU			0x9200
@@ -325,6 +333,13 @@ static int  option_resume(struct usb_serial *serial);
 #define ALCATEL_VENDOR_ID			0x1bbb
 #define ALCATEL_PRODUCT_X060S			0x0000
 
+/* Airplus products */
+#define AIRPLUS_VENDOR_ID			0x1011
+#define AIRPLUS_PRODUCT_MCD650			0x3198
+
+/* Haier products */
+#define HAIER_VENDOR_ID				0x201e
+#define HAIER_PRODUCT_CE100			0x2009
 
 static struct usb_device_id option_ids[] = {
 	{ USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_COLT) },
@@ -423,6 +438,7 @@ static struct usb_device_id option_ids[] = {
 	{ USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E143D, 0xff, 0xff, 0xff) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E143E, 0xff, 0xff, 0xff) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E143F, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E14AC) },
 	{ USB_DEVICE(AMOI_VENDOR_ID, AMOI_PRODUCT_9508) },
 	{ USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_V640) }, /* Novatel Merlin V640/XV620 */
 	{ USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_V620) }, /* Novatel Merlin V620/S620 */
@@ -503,6 +519,7 @@ static struct usb_device_id option_ids[] = {
 	{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x6613)}, /* Onda H600/ZTE MF330 */
 	{ USB_DEVICE(MAXON_VENDOR_ID, 0x6280) }, /* BP3-USB & BP3-EXT HSDPA */
 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_UC864E) },
+	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_UC864G) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_MF622, 0xff, 0xff, 0xff) }, /* ZTE WCDMA products */
 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0002, 0xff, 0xff, 0xff) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0003, 0xff, 0xff, 0xff) },
@@ -564,24 +581,67 @@ static struct usb_device_id option_ids[] = {
 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0086, 0xff, 0xff, 0xff) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x2002, 0xff, 0xff, 0xff) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x2003, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0104, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0106, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0108, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0113, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0117, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0118, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0121, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0122, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0123, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0124, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0125, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0126, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0128, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0142, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0143, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0144, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0145, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0146, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0147, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0148, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0149, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0150, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0151, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0152, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0153, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0154, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0155, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0156, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0157, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0158, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0159, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0160, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0161, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0162, 0xff, 0xff, 0xff) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0014, 0xff, 0xff, 0xff) }, /* ZTE CDMA products */
 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0027, 0xff, 0xff, 0xff) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0059, 0xff, 0xff, 0xff) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0060, 0xff, 0xff, 0xff) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0070, 0xff, 0xff, 0xff) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0073, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0130, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0141, 0xff, 0xff, 0xff) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_CDMA_TECH, 0xff, 0xff, 0xff) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_AC8710, 0xff, 0xff, 0xff) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_AC2726, 0xff, 0xff, 0xff) },
 	{ USB_DEVICE(BENQ_VENDOR_ID, BENQ_PRODUCT_H10) },
 	{ USB_DEVICE(DLINK_VENDOR_ID, DLINK_PRODUCT_DWM_652) },
+	{ USB_DEVICE(ALINK_VENDOR_ID, DLINK_PRODUCT_DWM_652_U5) }, /* Yes, ALINK_VENDOR_ID */
 	{ USB_DEVICE(QISDA_VENDOR_ID, QISDA_PRODUCT_H21_4512) },
 	{ USB_DEVICE(QISDA_VENDOR_ID, QISDA_PRODUCT_H21_4523) },
 	{ USB_DEVICE(QISDA_VENDOR_ID, QISDA_PRODUCT_H20_4515) },
 	{ USB_DEVICE(QISDA_VENDOR_ID, QISDA_PRODUCT_H20_4519) },
+	{ USB_DEVICE(TOSHIBA_VENDOR_ID, TOSHIBA_PRODUCT_G450) },
 	{ USB_DEVICE(TOSHIBA_VENDOR_ID, TOSHIBA_PRODUCT_HSDPA_MINICARD ) }, /* Toshiba 3G HSDPA == Novatel Expedite EU870D MiniCard */
 	{ USB_DEVICE(ALINK_VENDOR_ID, 0x9000) },
+	{ USB_DEVICE(ALINK_VENDOR_ID, 0xce16) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(ALINK_VENDOR_ID, ALINK_PRODUCT_3GU, 0xff, 0xff, 0xff) },
 	{ USB_DEVICE(ALCATEL_VENDOR_ID, ALCATEL_PRODUCT_X060S) },
+	{ USB_DEVICE(AIRPLUS_VENDOR_ID, AIRPLUS_PRODUCT_MCD650) },
+	{ USB_DEVICE(TLAYTECH_VENDOR_ID, TLAYTECH_PRODUCT_TEU800) },
+	{ USB_DEVICE(HAIER_VENDOR_ID, HAIER_PRODUCT_CE100) },
 	{ } /* Terminating entry */
 };
 MODULE_DEVICE_TABLE(usb, option_ids);
diff --git a/drivers/usb/serial/oti6858.c b/drivers/usb/serial/oti6858.c
index 3cece27325e7..ef34cffabdf8 100644
--- a/drivers/usb/serial/oti6858.c
+++ b/drivers/usb/serial/oti6858.c
@@ -146,6 +146,7 @@ static int oti6858_open(struct tty_struct *tty,
 static void oti6858_close(struct usb_serial_port *port);
 static void oti6858_set_termios(struct tty_struct *tty,
 			struct usb_serial_port *port, struct ktermios *old);
+static void oti6858_init_termios(struct tty_struct *tty);
 static int oti6858_ioctl(struct tty_struct *tty, struct file *file,
 			unsigned int cmd, unsigned long arg);
 static void oti6858_read_int_callback(struct urb *urb);
@@ -186,6 +187,7 @@ static struct usb_serial_driver oti6858_device = {
 	.write =		oti6858_write,
 	.ioctl =		oti6858_ioctl,
 	.set_termios =		oti6858_set_termios,
+	.init_termios = 	oti6858_init_termios,
 	.tiocmget =		oti6858_tiocmget,
 	.tiocmset =		oti6858_tiocmset,
 	.read_bulk_callback =	oti6858_read_bulk_callback,
@@ -206,7 +208,6 @@ struct oti6858_private {
 	struct {
 		u8 read_urb_in_use;
 		u8 write_urb_in_use;
-		u8 termios_initialized;
 	} flags;
 	struct delayed_work delayed_write_work;
 
@@ -447,6 +448,14 @@ static int oti6858_chars_in_buffer(struct tty_struct *tty)
 	return chars;
 }
 
+static void oti6858_init_termios(struct tty_struct *tty)
+{
+	*(tty->termios) = tty_std_termios;
+	tty->termios->c_cflag = B38400 | CS8 | CREAD | HUPCL | CLOCAL;
+	tty->termios->c_ispeed = 38400;
+	tty->termios->c_ospeed = 38400;
+}
+
 static void oti6858_set_termios(struct tty_struct *tty,
 		struct usb_serial_port *port, struct ktermios *old_termios)
 {
@@ -464,16 +473,6 @@ static void oti6858_set_termios(struct tty_struct *tty,
 		return;
 	}
 
-	spin_lock_irqsave(&priv->lock, flags);
-	if (!priv->flags.termios_initialized) {
-		*(tty->termios) = tty_std_termios;
-		tty->termios->c_cflag = B38400 | CS8 | CREAD | HUPCL | CLOCAL;
-		tty->termios->c_ispeed = 38400;
-		tty->termios->c_ospeed = 38400;
-		priv->flags.termios_initialized = 1;
-	}
-	spin_unlock_irqrestore(&priv->lock, flags);
-
 	cflag = tty->termios->c_cflag;
 
 	spin_lock_irqsave(&priv->lock, flags);
diff --git a/drivers/usb/serial/pl2303.c b/drivers/usb/serial/pl2303.c
index 3e86815b2705..600097de714f 100644
--- a/drivers/usb/serial/pl2303.c
+++ b/drivers/usb/serial/pl2303.c
@@ -96,6 +96,7 @@ static struct usb_device_id id_table [] = {
 	{ USB_DEVICE(HP_VENDOR_ID, HP_LD220_PRODUCT_ID) },
 	{ USB_DEVICE(CRESSI_VENDOR_ID, CRESSI_EDY_PRODUCT_ID) },
 	{ USB_DEVICE(SONY_VENDOR_ID, SONY_QN3USB_PRODUCT_ID) },
+	{ USB_DEVICE(SANWA_VENDOR_ID, SANWA_PRODUCT_ID) },
 	{ }					/* Terminating entry */
 };
 
@@ -994,13 +995,15 @@ static void pl2303_push_data(struct tty_struct *tty,
 	/* overrun is special, not associated with a char */
 	if (line_status & UART_OVERRUN_ERROR)
 		tty_insert_flip_char(tty, 0, TTY_OVERRUN);
-	if (port->console && port->sysrq) {
+
+	if (tty_flag == TTY_NORMAL && !(port->console && port->sysrq))
+		tty_insert_flip_string(tty, data, urb->actual_length);
+	else {
 		int i;
 		for (i = 0; i < urb->actual_length; ++i)
 			if (!usb_serial_handle_sysrq_char(tty, port, data[i]))
 				tty_insert_flip_char(tty, data[i], tty_flag);
-	} else
-		tty_insert_flip_string(tty, data, urb->actual_length);
+	}
 	tty_flip_buffer_push(tty);
 }
 
diff --git a/drivers/usb/serial/pl2303.h b/drivers/usb/serial/pl2303.h
index ee9505e1dd92..d640dc951568 100644
--- a/drivers/usb/serial/pl2303.h
+++ b/drivers/usb/serial/pl2303.h
@@ -130,3 +130,7 @@
 /* Sony, USB data cable for CMD-Jxx mobile phones */
 #define SONY_VENDOR_ID		0x054c
 #define SONY_QN3USB_PRODUCT_ID	0x0437
+
+/* Sanwa KB-USB2 multimeter cable (ID: 11ad:0001) */
+#define SANWA_VENDOR_ID		0x11ad
+#define SANWA_PRODUCT_ID	0x0001
diff --git a/drivers/usb/serial/sierra.c b/drivers/usb/serial/sierra.c
index f48d05e0acc1..c5fbaa5dde05 100644
--- a/drivers/usb/serial/sierra.c
+++ b/drivers/usb/serial/sierra.c
@@ -287,6 +287,8 @@ static int sierra_send_setup(struct usb_serial_port *port)
 	struct sierra_port_private *portdata;
 	__u16 interface = 0;
 	int val = 0;
+	int do_send = 0;
+	int retval;
 
 	dev_dbg(&port->dev, "%s\n", __func__);
 
@@ -305,10 +307,7 @@ static int sierra_send_setup(struct usb_serial_port *port)
 		 */
 		if (port->interrupt_in_urb) {
 			/* send control message */
-			return usb_control_msg(serial->dev,
-				usb_rcvctrlpipe(serial->dev, 0),
-				0x22, 0x21, val, interface,
-				NULL, 0, USB_CTRL_SET_TIMEOUT);
+			do_send = 1;
 		}
 	}
 
@@ -320,12 +319,18 @@ static int sierra_send_setup(struct usb_serial_port *port)
 			interface = 1;
 		else if (port->bulk_out_endpointAddress == 5)
 			interface = 2;
-		return usb_control_msg(serial->dev,
-			usb_rcvctrlpipe(serial->dev, 0),
-			0x22, 0x21, val, interface,
-			NULL, 0, USB_CTRL_SET_TIMEOUT);
+
+		do_send = 1;
 	}
-	return 0;
+	if (!do_send)
+		return 0;
+
+	usb_autopm_get_interface(serial->interface);
+	retval = usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),
+		0x22, 0x21, val, interface, NULL, 0, USB_CTRL_SET_TIMEOUT);
+	usb_autopm_put_interface(serial->interface);
+
+	return retval;
 }
 
 static void sierra_set_termios(struct tty_struct *tty,
diff --git a/drivers/usb/serial/spcp8x5.c b/drivers/usb/serial/spcp8x5.c
index 3c249d8e8b8e..993a6d5a1b7a 100644
--- a/drivers/usb/serial/spcp8x5.c
+++ b/drivers/usb/serial/spcp8x5.c
@@ -299,7 +299,6 @@ struct spcp8x5_private {
 	wait_queue_head_t	delta_msr_wait;
 	u8 			line_control;
 	u8 			line_status;
-	u8 			termios_initialized;
 };
 
 /* desc : when device plug in,this function would be called.
@@ -498,6 +497,15 @@ static void spcp8x5_close(struct usb_serial_port *port)
 		dev_dbg(&port->dev, "usb_unlink_urb(read_urb) = %d\n", result);
 }
 
+static void spcp8x5_init_termios(struct tty_struct *tty)
+{
+	/* for the 1st time call this function */
+	*(tty->termios) = tty_std_termios;
+	tty->termios->c_cflag = B115200 | CS8 | CREAD | HUPCL | CLOCAL;
+	tty->termios->c_ispeed = 115200;
+	tty->termios->c_ospeed = 115200;
+}
+
 /* set the serial param for transfer. we should check if we really need to
  * transfer. if we set flow control we should do this too. */
 static void spcp8x5_set_termios(struct tty_struct *tty,
@@ -514,16 +522,6 @@ static void spcp8x5_set_termios(struct tty_struct *tty,
 	int i;
 	u8 control;
 
-	/* for the 1st time call this function */
-	spin_lock_irqsave(&priv->lock, flags);
-	if (!priv->termios_initialized) {
-		*(tty->termios) = tty_std_termios;
-		tty->termios->c_cflag = B115200 | CS8 | CREAD | HUPCL | CLOCAL;
-		tty->termios->c_ispeed = 115200;
-		tty->termios->c_ospeed = 115200;
-		priv->termios_initialized = 1;
-	}
-	spin_unlock_irqrestore(&priv->lock, flags);
 
 	/* check that they really want us to change something */
 	if (!tty_termios_hw_change(tty->termios, old_termios))
@@ -1011,6 +1009,7 @@ static struct usb_serial_driver spcp8x5_device = {
 	.carrier_raised		= spcp8x5_carrier_raised,
 	.write 			= spcp8x5_write,
 	.set_termios 		= spcp8x5_set_termios,
+	.init_termios		= spcp8x5_init_termios,
 	.ioctl 			= spcp8x5_ioctl,
 	.tiocmget 		= spcp8x5_tiocmget,
 	.tiocmset 		= spcp8x5_tiocmset,
diff --git a/drivers/usb/serial/usb-serial.c b/drivers/usb/serial/usb-serial.c
index 99188c92068b..3292e0391e28 100644
--- a/drivers/usb/serial/usb-serial.c
+++ b/drivers/usb/serial/usb-serial.c
@@ -43,8 +43,6 @@
 #define DRIVER_AUTHOR "Greg Kroah-Hartman, greg@kroah.com, http://www.kroah.com/linux/"
 #define DRIVER_DESC "USB Serial Driver core"
 
-static void port_free(struct usb_serial_port *port);
-
 /* Driver structure we register with the USB core */
 static struct usb_driver usb_serial_driver = {
 	.name =		"usbserial",
@@ -68,6 +66,11 @@ static struct usb_serial *serial_table[SERIAL_TTY_MINORS];
 static DEFINE_MUTEX(table_lock);
 static LIST_HEAD(usb_serial_driver_list);
 
+/*
+ * Look up the serial structure.  If it is found and it hasn't been
+ * disconnected, return with its disc_mutex held and its refcount
+ * incremented.  Otherwise return NULL.
+ */
 struct usb_serial *usb_serial_get_by_index(unsigned index)
 {
 	struct usb_serial *serial;
@@ -75,8 +78,15 @@ struct usb_serial *usb_serial_get_by_index(unsigned index)
 	mutex_lock(&table_lock);
 	serial = serial_table[index];
 
-	if (serial)
-		kref_get(&serial->kref);
+	if (serial) {
+		mutex_lock(&serial->disc_mutex);
+		if (serial->disconnected) {
+			mutex_unlock(&serial->disc_mutex);
+			serial = NULL;
+		} else {
+			kref_get(&serial->kref);
+		}
+	}
 	mutex_unlock(&table_lock);
 	return serial;
 }
@@ -125,8 +135,10 @@ static void return_serial(struct usb_serial *serial)
 
 	dbg("%s", __func__);
 
+	mutex_lock(&table_lock);
 	for (i = 0; i < serial->num_ports; ++i)
 		serial_table[serial->minor + i] = NULL;
+	mutex_unlock(&table_lock);
 }
 
 static void destroy_serial(struct kref *kref)
@@ -143,163 +155,160 @@ static void destroy_serial(struct kref *kref)
 	if (serial->minor != SERIAL_TTY_NO_MINOR)
 		return_serial(serial);
 
-	serial->type->release(serial);
+	if (serial->attached)
+		serial->type->release(serial);
 
-	for (i = 0; i < serial->num_ports; ++i) {
+	/* Now that nothing is using the ports, they can be freed */
+	for (i = 0; i < serial->num_port_pointers; ++i) {
 		port = serial->port[i];
-		if (port)
+		if (port) {
+			port->serial = NULL;
 			put_device(&port->dev);
-	}
-
-	/* If this is a "fake" port, we have to clean it up here, as it will
-	 * not get cleaned up in port_release() as it was never registered with
-	 * the driver core */
-	if (serial->num_ports < serial->num_port_pointers) {
-		for (i = serial->num_ports;
-					i < serial->num_port_pointers; ++i) {
-			port = serial->port[i];
-			if (port)
-				port_free(port);
 		}
 	}
 
 	usb_put_dev(serial->dev);
-
-	/* free up any memory that we allocated */
 	kfree(serial);
 }
 
 void usb_serial_put(struct usb_serial *serial)
 {
-	mutex_lock(&table_lock);
 	kref_put(&serial->kref, destroy_serial);
-	mutex_unlock(&table_lock);
 }
 
 /*****************************************************************************
  * Driver tty interface functions
  *****************************************************************************/
-static int serial_open (struct tty_struct *tty, struct file *filp)
+
+/**
+ * serial_install - install tty
+ * @driver: the driver (USB in our case)
+ * @tty: the tty being created
+ *
+ * Create the termios objects for this tty.  We use the default
+ * USB serial settings but permit them to be overridden by
+ * serial->type->init_termios.
+ *
+ * This is the first place a new tty gets used.  Hence this is where we
+ * acquire references to the usb_serial structure and the driver module,
+ * where we store a pointer to the port, and where we do an autoresume.
+ * All these actions are reversed in serial_release().
+ */
+static int serial_install(struct tty_driver *driver, struct tty_struct *tty)
 {
+	int idx = tty->index;
 	struct usb_serial *serial;
 	struct usb_serial_port *port;
-	unsigned int portNumber;
-	int retval = 0;
-	int first = 0;
+	int retval = -ENODEV;
 
 	dbg("%s", __func__);
 
-	/* get the serial object associated with this tty pointer */
-	serial = usb_serial_get_by_index(tty->index);
-	if (!serial) {
-		tty->driver_data = NULL;
-		return -ENODEV;
-	}
+	serial = usb_serial_get_by_index(idx);
+	if (!serial)
+		return retval;
 
-	mutex_lock(&serial->disc_mutex);
-	portNumber = tty->index - serial->minor;
-	port = serial->port[portNumber];
-	if (!port || serial->disconnected)
-		retval = -ENODEV;
-	else
-		get_device(&port->dev);
-	/*
-	 * Note: Our locking order requirement does not allow port->mutex
-	 * to be acquired while serial->disc_mutex is held.
-	 */
-	mutex_unlock(&serial->disc_mutex);
+	port = serial->port[idx - serial->minor];
+	if (!port)
+		goto error_no_port;
+	if (!try_module_get(serial->type->driver.owner))
+		goto error_module_get;
+
+	/* perform the standard setup */
+	retval = tty_init_termios(tty);
 	if (retval)
-		goto bailout_serial_put;
+		goto error_init_termios;
 
-	if (mutex_lock_interruptible(&port->mutex)) {
-		retval = -ERESTARTSYS;
-		goto bailout_port_put;
-	}
+	retval = usb_autopm_get_interface(serial->interface);
+	if (retval)
+		goto error_get_interface;
+
+	mutex_unlock(&serial->disc_mutex);
 
-	++port->port.count;
+	/* allow the driver to update the settings */
+	if (serial->type->init_termios)
+		serial->type->init_termios(tty);
 
-	/* set up our port structure making the tty driver
-	 * remember our port object, and us it */
 	tty->driver_data = port;
-	tty_port_tty_set(&port->port, tty);
 
-	/* If the console is attached, the device is already open */
-	if (port->port.count == 1 && !port->console) {
-		first = 1;
-		/* lock this module before we call it
-		 * this may fail, which means we must bail out,
-		 * safe because we are called with BKL held */
-		if (!try_module_get(serial->type->driver.owner)) {
-			retval = -ENODEV;
-			goto bailout_mutex_unlock;
-		}
+	/* Final install (we use the default method) */
+	tty_driver_kref_get(driver);
+	tty->count++;
+	driver->ttys[idx] = tty;
+	return retval;
 
+ error_get_interface:
+ error_init_termios:
+	module_put(serial->type->driver.owner);
+ error_module_get:
+ error_no_port:
+	usb_serial_put(serial);
+	mutex_unlock(&serial->disc_mutex);
+	return retval;
+}
+
+static int serial_open(struct tty_struct *tty, struct file *filp)
+{
+	struct usb_serial_port *port = tty->driver_data;
+	struct usb_serial *serial = port->serial;
+	int retval;
+
+	dbg("%s - port %d", __func__, port->number);
+
+	spin_lock_irq(&port->port.lock);
+	if (!tty_hung_up_p(filp))
+		++port->port.count;
+	spin_unlock_irq(&port->port.lock);
+	tty_port_tty_set(&port->port, tty);
+
+	/* Do the device-specific open only if the hardware isn't
+	 * already initialized.
+	 */
+	if (!test_bit(ASYNCB_INITIALIZED, &port->port.flags)) {
+		if (mutex_lock_interruptible(&port->mutex))
+			return -ERESTARTSYS;
 		mutex_lock(&serial->disc_mutex);
 		if (serial->disconnected)
 			retval = -ENODEV;
 		else
-			retval = usb_autopm_get_interface(serial->interface);
-		if (retval)
-			goto bailout_module_put;
-
-		/* only call the device specific open if this
-		 * is the first time the port is opened */
-		retval = serial->type->open(tty, port, filp);
-		if (retval)
-			goto bailout_interface_put;
+			retval = port->serial->type->open(tty, port, filp);
 		mutex_unlock(&serial->disc_mutex);
+		mutex_unlock(&port->mutex);
+		if (retval)
+			return retval;
 		set_bit(ASYNCB_INITIALIZED, &port->port.flags);
 	}
-	mutex_unlock(&port->mutex);
+
 	/* Now do the correct tty layer semantics */
 	retval = tty_port_block_til_ready(&port->port, tty, filp);
-	if (retval == 0) {
-		if (!first)
-			usb_serial_put(serial);
-		return 0;
-	}
-	mutex_lock(&port->mutex);
-	if (first == 0)
-		goto bailout_mutex_unlock;
-	/* Undo the initial port actions */
-	mutex_lock(&serial->disc_mutex);
-bailout_interface_put:
-	usb_autopm_put_interface(serial->interface);
-bailout_module_put:
-	mutex_unlock(&serial->disc_mutex);
-	module_put(serial->type->driver.owner);
-bailout_mutex_unlock:
-	port->port.count = 0;
-	tty->driver_data = NULL;
-	tty_port_tty_set(&port->port, NULL);
-	mutex_unlock(&port->mutex);
-bailout_port_put:
-	put_device(&port->dev);
-bailout_serial_put:
-	usb_serial_put(serial);
 	return retval;
 }
 
 /**
- *	serial_do_down		-	shut down hardware
- *	@port: port to shut down
- *
- *	Shut down a USB port unless it is the console. We never shut down the
- *	console hardware as it will always be in use.
+ * serial_down - shut down hardware
+ * @port: port to shut down
  *
- *	Don't free any resources at this point
+ * Shut down a USB serial port unless it is the console.  We never
+ * shut down the console hardware as it will always be in use.
  */
-static void serial_do_down(struct usb_serial_port *port)
+static void serial_down(struct usb_serial_port *port)
 {
 	struct usb_serial_driver *drv = port->serial->type;
 	struct usb_serial *serial;
 	struct module *owner;
 
-	/* The console is magical, do not hang up the console hardware
-	   or there will be tears */
+	/*
+	 * The console is magical.  Do not hang up the console hardware
+	 * or there will be tears.
+	 */
 	if (port->console)
 		return;
 
+	/* Don't call the close method if the hardware hasn't been
+	 * initialized.
+	 */
+	if (!test_and_clear_bit(ASYNCB_INITIALIZED, &port->port.flags))
+		return;
+
 	mutex_lock(&port->mutex);
 	serial = port->serial;
 	owner = serial->type->driver.owner;
@@ -310,79 +319,69 @@ static void serial_do_down(struct usb_serial_port *port)
 	mutex_unlock(&port->mutex);
 }
 
-/**
- *	serial_do_free		-	free resources post close/hangup
- *	@port: port to free up
- *
- *	Do the resource freeing and refcount dropping for the port. We must
- *	be careful about ordering and we must avoid freeing up the console.
- */
-
-static void serial_do_free(struct usb_serial_port *port)
+static void serial_hangup(struct tty_struct *tty)
 {
-	struct usb_serial *serial;
-	struct module *owner;
+	struct usb_serial_port *port = tty->driver_data;
 
-	/* The console is magical, do not hang up the console hardware
-	   or there will be tears */
-	if (port->console)
-		return;
+	dbg("%s - port %d", __func__, port->number);
 
-	serial = port->serial;
-	owner = serial->type->driver.owner;
-	put_device(&port->dev);
-	/* Mustn't dereference port any more */
-	mutex_lock(&serial->disc_mutex);
-	if (!serial->disconnected)
-		usb_autopm_put_interface(serial->interface);
-	mutex_unlock(&serial->disc_mutex);
-	usb_serial_put(serial);
-	/* Mustn't dereference serial any more */
-	module_put(owner);
+	serial_down(port);
+	tty_port_hangup(&port->port);
 }
 
 static void serial_close(struct tty_struct *tty, struct file *filp)
 {
 	struct usb_serial_port *port = tty->driver_data;
 
-	if (!port)
-		return;
-
 	dbg("%s - port %d", __func__, port->number);
 
-	/* FIXME:
-	   This leaves a very narrow race. Really we should do the
-	   serial_do_free() on tty->shutdown(), but tty->shutdown can
-	   be called from IRQ context and serial_do_free can sleep.
-
-	   The right fix is probably to make the tty free (which is rare)
-	   and thus tty->shutdown() occur via a work queue and simplify all
-	   the drivers that use it.
-	*/
-	if (tty_hung_up_p(filp)) {
-		/* serial_hangup already called serial_down at this point.
-		   Another user may have already reopened the port but
-		   serial_do_free is refcounted */
-		serial_do_free(port);
+	if (tty_hung_up_p(filp))
 		return;
-	}
-
 	if (tty_port_close_start(&port->port, tty, filp) == 0)
 		return;
-
-	serial_do_down(port);		
+	serial_down(port);
 	tty_port_close_end(&port->port, tty);
 	tty_port_tty_set(&port->port, NULL);
-	serial_do_free(port);
 }
 
-static void serial_hangup(struct tty_struct *tty)
+/**
+ * serial_release - free resources post close/hangup
+ * @port: port to free up
+ *
+ * Do the resource freeing and refcount dropping for the port.
+ * Avoid freeing the console.
+ *
+ * Called when the last tty kref is dropped.
+ */
+static void serial_release(struct tty_struct *tty)
 {
 	struct usb_serial_port *port = tty->driver_data;
-	serial_do_down(port);
-	tty_port_hangup(&port->port);
-	/* We must not free port yet - the USB serial layer depends on it's
-	   continued existence */
+	struct usb_serial *serial;
+	struct module *owner;
+
+	/* The console is magical.  Do not hang up the console hardware
+	 * or there will be tears.
+	 */
+	if (port->console)
+		return;
+
+	dbg("%s - port %d", __func__, port->number);
+
+	/* Standard shutdown processing */
+	tty_shutdown(tty);
+
+	tty->driver_data = NULL;
+
+	serial = port->serial;
+	owner = serial->type->driver.owner;
+
+	mutex_lock(&serial->disc_mutex);
+	if (!serial->disconnected)
+		usb_autopm_put_interface(serial->interface);
+	mutex_unlock(&serial->disc_mutex);
+
+	usb_serial_put(serial);
+	module_put(owner);
 }
 
 static int serial_write(struct tty_struct *tty, const unsigned char *buf,
@@ -527,6 +526,7 @@ static int serial_proc_show(struct seq_file *m, void *v)
 
 		seq_putc(m, '\n');
 		usb_serial_put(serial);
+		mutex_unlock(&serial->disc_mutex);
 	}
 	return 0;
 }
@@ -596,14 +596,6 @@ static void usb_serial_port_work(struct work_struct *work)
 	tty_kref_put(tty);
 }
 
-static void port_release(struct device *dev)
-{
-	struct usb_serial_port *port = to_usb_serial_port(dev);
-
-	dbg ("%s - %s", __func__, dev_name(dev));
-	port_free(port);
-}
-
 static void kill_traffic(struct usb_serial_port *port)
 {
 	usb_kill_urb(port->read_urb);
@@ -623,8 +615,12 @@ static void kill_traffic(struct usb_serial_port *port)
 	usb_kill_urb(port->interrupt_out_urb);
 }
 
-static void port_free(struct usb_serial_port *port)
+static void port_release(struct device *dev)
 {
+	struct usb_serial_port *port = to_usb_serial_port(dev);
+
+	dbg ("%s - %s", __func__, dev_name(dev));
+
 	/*
 	 * Stop all the traffic before cancelling the work, so that
 	 * nobody will restart it by calling usb_serial_port_softint.
@@ -935,6 +931,11 @@ int usb_serial_probe(struct usb_interface *interface,
 		mutex_init(&port->mutex);
 		INIT_WORK(&port->work, usb_serial_port_work);
 		serial->port[i] = port;
+		port->dev.parent = &interface->dev;
+		port->dev.driver = NULL;
+		port->dev.bus = &usb_serial_bus_type;
+		port->dev.release = &port_release;
+		device_initialize(&port->dev);
 	}
 
 	/* set up the endpoint information */
@@ -1060,12 +1061,15 @@ int usb_serial_probe(struct usb_interface *interface,
 		module_put(type->driver.owner);
 		if (retval < 0)
 			goto probe_error;
+		serial->attached = 1;
 		if (retval > 0) {
 			/* quietly accept this device, but don't bind to a
 			   serial port as it's about to disappear */
 			serial->num_ports = 0;
 			goto exit;
 		}
+	} else {
+		serial->attached = 1;
 	}
 
 	if (get_free_serial(serial, num_ports, &minor) == NULL) {
@@ -1077,15 +1081,10 @@ int usb_serial_probe(struct usb_interface *interface,
 	/* register all of the individual ports with the driver core */
 	for (i = 0; i < num_ports; ++i) {
 		port = serial->port[i];
-		port->dev.parent = &interface->dev;
-		port->dev.driver = NULL;
-		port->dev.bus = &usb_serial_bus_type;
-		port->dev.release = &port_release;
-
 		dev_set_name(&port->dev, "ttyUSB%d", port->number);
 		dbg ("%s - registering %s", __func__, dev_name(&port->dev));
 		port->dev_state = PORT_REGISTERING;
-		retval = device_register(&port->dev);
+		retval = device_add(&port->dev);
 		if (retval) {
 			dev_err(&port->dev, "Error registering port device, "
 				"continuing\n");
@@ -1103,39 +1102,7 @@ exit:
 	return 0;
 
 probe_error:
-	for (i = 0; i < num_bulk_in; ++i) {
-		port = serial->port[i];
-		if (!port)
-			continue;
-		usb_free_urb(port->read_urb);
-		kfree(port->bulk_in_buffer);
-	}
-	for (i = 0; i < num_bulk_out; ++i) {
-		port = serial->port[i];
-		if (!port)
-			continue;
-		usb_free_urb(port->write_urb);
-		kfree(port->bulk_out_buffer);
-	}
-	for (i = 0; i < num_interrupt_in; ++i) {
-		port = serial->port[i];
-		if (!port)
-			continue;
-		usb_free_urb(port->interrupt_in_urb);
-		kfree(port->interrupt_in_buffer);
-	}
-	for (i = 0; i < num_interrupt_out; ++i) {
-		port = serial->port[i];
-		if (!port)
-			continue;
-		usb_free_urb(port->interrupt_out_urb);
-		kfree(port->interrupt_out_buffer);
-	}
-
-	/* free up any memory that we allocated */
-	for (i = 0; i < serial->num_port_pointers; ++i)
-		kfree(serial->port[i]);
-	kfree(serial);
+	usb_serial_put(serial);
 	return -EIO;
 }
 EXPORT_SYMBOL_GPL(usb_serial_probe);
@@ -1161,10 +1128,7 @@ void usb_serial_disconnect(struct usb_interface *interface)
 		if (port) {
 			struct tty_struct *tty = tty_port_tty_get(&port->port);
 			if (tty) {
-				/* The hangup will occur asynchronously but
-				   the object refcounts will sort out all the
-				   cleanup */
-				tty_hangup(tty);
+				tty_vhangup(tty);
 				tty_kref_put(tty);
 			}
 			kill_traffic(port);
@@ -1189,8 +1153,7 @@ void usb_serial_disconnect(struct usb_interface *interface)
 	}
 	serial->type->disconnect(serial);
 
-	/* let the last holder of this object
-	 * cause it to be cleaned up */
+	/* let the last holder of this object cause it to be cleaned up */
 	usb_serial_put(serial);
 	dev_info(dev, "device disconnected\n");
 }
@@ -1246,6 +1209,8 @@ static const struct tty_operations serial_ops = {
 	.chars_in_buffer =	serial_chars_in_buffer,
 	.tiocmget =		serial_tiocmget,
 	.tiocmset =		serial_tiocmset,
+	.shutdown = 		serial_release,
+	.install = 		serial_install,
 	.proc_fops =		&serial_proc_fops,
 };
 
diff --git a/drivers/usb/serial/whiteheat.c b/drivers/usb/serial/whiteheat.c
index 8d126dd7a02e..f7232b1bce51 100644
--- a/drivers/usb/serial/whiteheat.c
+++ b/drivers/usb/serial/whiteheat.c
@@ -259,7 +259,7 @@ static int firm_send_command(struct usb_serial_port *port, __u8 command,
 						__u8 *data, __u8 datasize);
 static int firm_open(struct usb_serial_port *port);
 static int firm_close(struct usb_serial_port *port);
-static int firm_setup_port(struct tty_struct *tty);
+static void firm_setup_port(struct tty_struct *tty);
 static int firm_set_rts(struct usb_serial_port *port, __u8 onoff);
 static int firm_set_dtr(struct usb_serial_port *port, __u8 onoff);
 static int firm_set_break(struct usb_serial_port *port, __u8 onoff);
@@ -1211,7 +1211,7 @@ static int firm_close(struct usb_serial_port *port)
 }
 
 
-static int firm_setup_port(struct tty_struct *tty)
+static void firm_setup_port(struct tty_struct *tty)
 {
 	struct usb_serial_port *port = tty->driver_data;
 	struct whiteheat_port_settings port_settings;
@@ -1286,7 +1286,7 @@ static int firm_setup_port(struct tty_struct *tty)
 	port_settings.lloop = 0;
 
 	/* now send the message to the device */
-	return firm_send_command(port, WHITEHEAT_SETUP_PORT,
+	firm_send_command(port, WHITEHEAT_SETUP_PORT,
 			(__u8 *)&port_settings, sizeof(port_settings));
 }
 
diff --git a/drivers/usb/storage/initializers.c b/drivers/usb/storage/initializers.c
index ec17c96371af..105d900150c1 100644
--- a/drivers/usb/storage/initializers.c
+++ b/drivers/usb/storage/initializers.c
@@ -102,5 +102,5 @@ int usb_stor_huawei_e220_init(struct us_data *us)
 				      USB_TYPE_STANDARD | USB_RECIP_DEVICE,
 				      0x01, 0x0, NULL, 0x0, 1000);
 	US_DEBUGP("Huawei mode set result is %d\n", result);
-	return (result ? 0 : -ENODEV);
+	return 0;
 }
diff --git a/drivers/usb/storage/onetouch.c b/drivers/usb/storage/onetouch.c
index 380233bd6a39..80e65f29921c 100644
--- a/drivers/usb/storage/onetouch.c
+++ b/drivers/usb/storage/onetouch.c
@@ -163,7 +163,7 @@ static void usb_onetouch_pm_hook(struct us_data *us, int action)
 			usb_kill_urb(onetouch->irq);
 			break;
 		case US_RESUME:
-			if (usb_submit_urb(onetouch->irq, GFP_KERNEL) != 0)
+			if (usb_submit_urb(onetouch->irq, GFP_NOIO) != 0)
 				dev_err(&onetouch->irq->dev->dev,
 					"usb_submit_urb failed\n");
 			break;
diff --git a/drivers/usb/storage/transport.c b/drivers/usb/storage/transport.c
index e20dc525d177..cc313d16d727 100644
--- a/drivers/usb/storage/transport.c
+++ b/drivers/usb/storage/transport.c
@@ -666,10 +666,11 @@ void usb_stor_invoke_transport(struct scsi_cmnd *srb, struct us_data *us)
 	 * to wait for at least one CHECK_CONDITION to determine
 	 * SANE_SENSE support
 	 */
-	if ((srb->cmnd[0] == ATA_16 || srb->cmnd[0] == ATA_12) &&
+	if (unlikely((srb->cmnd[0] == ATA_16 || srb->cmnd[0] == ATA_12) &&
 	    result == USB_STOR_TRANSPORT_GOOD &&
 	    !(us->fflags & US_FL_SANE_SENSE) &&
-	    !(srb->cmnd[2] & 0x20)) {
+	    !(us->fflags & US_FL_BAD_SENSE) &&
+	    !(srb->cmnd[2] & 0x20))) {
 		US_DEBUGP("-- SAT supported, increasing auto-sense\n");
 		us->fflags |= US_FL_SANE_SENSE;
 	}
@@ -696,7 +697,7 @@ void usb_stor_invoke_transport(struct scsi_cmnd *srb, struct us_data *us)
 		/* device supports and needs bigger sense buffer */
 		if (us->fflags & US_FL_SANE_SENSE)
 			sense_size = ~0;
-
+Retry_Sense:
 		US_DEBUGP("Issuing auto-REQUEST_SENSE\n");
 
 		scsi_eh_prep_cmnd(srb, &ses, NULL, 0, sense_size);
@@ -718,8 +719,30 @@ void usb_stor_invoke_transport(struct scsi_cmnd *srb, struct us_data *us)
 		if (test_bit(US_FLIDX_TIMED_OUT, &us->dflags)) {
 			US_DEBUGP("-- auto-sense aborted\n");
 			srb->result = DID_ABORT << 16;
+
+			/* If SANE_SENSE caused this problem, disable it */
+			if (sense_size != US_SENSE_SIZE) {
+				us->fflags &= ~US_FL_SANE_SENSE;
+				us->fflags |= US_FL_BAD_SENSE;
+			}
 			goto Handle_Errors;
 		}
+
+		/* Some devices claim to support larger sense but fail when
+		 * trying to request it. When a transport failure happens
+		 * using US_FS_SANE_SENSE, we always retry with a standard
+		 * (small) sense request. This fixes some USB GSM modems
+		 */
+		if (temp_result == USB_STOR_TRANSPORT_FAILED &&
+				sense_size != US_SENSE_SIZE) {
+			US_DEBUGP("-- auto-sense failure, retry small sense\n");
+			sense_size = US_SENSE_SIZE;
+			us->fflags &= ~US_FL_SANE_SENSE;
+			us->fflags |= US_FL_BAD_SENSE;
+			goto Retry_Sense;
+		}
+
+		/* Other failures */
 		if (temp_result != USB_STOR_TRANSPORT_GOOD) {
 			US_DEBUGP("-- auto-sense failure\n");
 
@@ -739,6 +762,7 @@ void usb_stor_invoke_transport(struct scsi_cmnd *srb, struct us_data *us)
 		 */
 		if (srb->sense_buffer[7] > (US_SENSE_SIZE - 8) &&
 		    !(us->fflags & US_FL_SANE_SENSE) &&
+		    !(us->fflags & US_FL_BAD_SENSE) &&
 		    (srb->sense_buffer[0] & 0x7C) == 0x70) {
 			US_DEBUGP("-- SANE_SENSE support enabled\n");
 			us->fflags |= US_FL_SANE_SENSE;
@@ -768,17 +792,32 @@ void usb_stor_invoke_transport(struct scsi_cmnd *srb, struct us_data *us)
 		/* set the result so the higher layers expect this data */
 		srb->result = SAM_STAT_CHECK_CONDITION;
 
-		/* If things are really okay, then let's show that.  Zero
-		 * out the sense buffer so the higher layers won't realize
-		 * we did an unsolicited auto-sense. */
-		if (result == USB_STOR_TRANSPORT_GOOD &&
-			/* Filemark 0, ignore EOM, ILI 0, no sense */
+		/* We often get empty sense data.  This could indicate that
+		 * everything worked or that there was an unspecified
+		 * problem.  We have to decide which.
+		 */
+		if (	/* Filemark 0, ignore EOM, ILI 0, no sense */
 				(srb->sense_buffer[2] & 0xaf) == 0 &&
 			/* No ASC or ASCQ */
 				srb->sense_buffer[12] == 0 &&
 				srb->sense_buffer[13] == 0) {
-			srb->result = SAM_STAT_GOOD;
-			srb->sense_buffer[0] = 0x0;
+
+			/* If things are really okay, then let's show that.
+			 * Zero out the sense buffer so the higher layers
+			 * won't realize we did an unsolicited auto-sense.
+			 */
+			if (result == USB_STOR_TRANSPORT_GOOD) {
+				srb->result = SAM_STAT_GOOD;
+				srb->sense_buffer[0] = 0x0;
+
+			/* If there was a problem, report an unspecified
+			 * hardware error to prevent the higher layers from
+			 * entering an infinite retry loop.
+			 */
+			} else {
+				srb->result = DID_ERROR << 16;
+				srb->sense_buffer[2] = HARDWARE_ERROR;
+			}
 		}
 	}
 
diff --git a/drivers/usb/storage/unusual_devs.h b/drivers/usb/storage/unusual_devs.h
index 7477d411959f..5ef11f435330 100644
--- a/drivers/usb/storage/unusual_devs.h
+++ b/drivers/usb/storage/unusual_devs.h
@@ -838,6 +838,13 @@ UNUSUAL_DEV( 0x066f, 0x8000, 0x0001, 0x0001,
 		US_SC_DEVICE, US_PR_DEVICE, NULL,
 		US_FL_FIX_CAPACITY ),
 
+/* Reported by Daniel Kukula <daniel.kuku@gmail.com> */
+UNUSUAL_DEV( 0x067b, 0x1063, 0x0100, 0x0100,
+		"Prolific Technology, Inc.",
+		"Prolific Storage Gadget",
+		US_SC_DEVICE, US_PR_DEVICE, NULL,
+		US_FL_BAD_SENSE ),
+
 /* Reported by Rogerio Brito <rbrito@ime.usp.br> */
 UNUSUAL_DEV( 0x067b, 0x2317, 0x0001, 0x001,
 		"Prolific Technology, Inc.",
@@ -1820,13 +1827,6 @@ UNUSUAL_DEV(  0x2735, 0x100b, 0x0000, 0x9999,
 		US_SC_DEVICE, US_PR_DEVICE, NULL,
 		US_FL_GO_SLOW ),
 
-/* Reported by Rohan Hart <rohan.hart17@gmail.com> */
-UNUSUAL_DEV(  0x2770, 0x915d, 0x0010, 0x0010,
-		"INTOVA",
-		"Pixtreme",
-		US_SC_DEVICE, US_PR_DEVICE, NULL,
-		US_FL_FIX_CAPACITY ),
-
 /* Reported by Frederic Marchal <frederic.marchal@wowcompany.com>
  * Mio Moov 330
  */
diff --git a/drivers/usb/storage/usb.c b/drivers/usb/storage/usb.c
index 11dd37de45c7..f3ba49f62408 100644
--- a/drivers/usb/storage/usb.c
+++ b/drivers/usb/storage/usb.c
@@ -228,6 +228,7 @@ void fill_inquiry_response(struct us_data *us, unsigned char *data,
 	if (data_len<36) // You lose.
 		return;
 
+	memset(data+8, ' ', 28);
 	if(data[0]&0x20) { /* USB device currently not connected. Return
 			      peripheral qualifier 001b ("...however, the
 			      physical device is not currently connected
@@ -237,15 +238,15 @@ void fill_inquiry_response(struct us_data *us, unsigned char *data,
 			      device, it may return zeros or ASCII spaces 
 			      (20h) in those fields until the data is
 			      available from the device."). */
-		memset(data+8,0,28);
 	} else {
 		u16 bcdDevice = le16_to_cpu(us->pusb_dev->descriptor.bcdDevice);
-		memcpy(data+8, us->unusual_dev->vendorName, 
-			strlen(us->unusual_dev->vendorName) > 8 ? 8 :
-			strlen(us->unusual_dev->vendorName));
-		memcpy(data+16, us->unusual_dev->productName, 
-			strlen(us->unusual_dev->productName) > 16 ? 16 :
-			strlen(us->unusual_dev->productName));
+		int n;
+
+		n = strlen(us->unusual_dev->vendorName);
+		memcpy(data+8, us->unusual_dev->vendorName, min(8, n));
+		n = strlen(us->unusual_dev->productName);
+		memcpy(data+16, us->unusual_dev->productName, min(16, n));
+
 		data[32] = 0x30 + ((bcdDevice>>12) & 0x0F);
 		data[33] = 0x30 + ((bcdDevice>>8) & 0x0F);
 		data[34] = 0x30 + ((bcdDevice>>4) & 0x0F);
@@ -432,7 +433,8 @@ static void adjust_quirks(struct us_data *us)
 	u16 vid = le16_to_cpu(us->pusb_dev->descriptor.idVendor);
 	u16 pid = le16_to_cpu(us->pusb_dev->descriptor.idProduct);
 	unsigned f = 0;
-	unsigned int mask = (US_FL_SANE_SENSE | US_FL_FIX_CAPACITY |
+	unsigned int mask = (US_FL_SANE_SENSE | US_FL_BAD_SENSE |
+			US_FL_FIX_CAPACITY |
 			US_FL_CAPACITY_HEURISTICS | US_FL_IGNORE_DEVICE |
 			US_FL_NOT_LOCKABLE | US_FL_MAX_SECTORS_64 |
 			US_FL_CAPACITY_OK | US_FL_IGNORE_RESIDUE |
@@ -462,6 +464,9 @@ static void adjust_quirks(struct us_data *us)
 		case 'a':
 			f |= US_FL_SANE_SENSE;
 			break;
+		case 'b':
+			f |= US_FL_BAD_SENSE;
+			break;
 		case 'c':
 			f |= US_FL_FIX_CAPACITY;
 			break;
diff --git a/drivers/video/backlight/lcd.c b/drivers/video/backlight/lcd.c
index b6449470106c..a482dd7b0311 100644
--- a/drivers/video/backlight/lcd.c
+++ b/drivers/video/backlight/lcd.c
@@ -56,7 +56,7 @@ static int fb_notifier_callback(struct notifier_block *self,
 
 static int lcd_register_fb(struct lcd_device *ld)
 {
-	memset(&ld->fb_notif, 0, sizeof(&ld->fb_notif));
+	memset(&ld->fb_notif, 0, sizeof(ld->fb_notif));
 	ld->fb_notif.notifier_call = fb_notifier_callback;
 	return fb_register_client(&ld->fb_notif);
 }
diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
index 2f50a80b413e..979b5a18588c 100644
--- a/drivers/video/console/Kconfig
+++ b/drivers/video/console/Kconfig
@@ -67,16 +67,9 @@ config SGI_NEWPORT_CONSOLE
 
 #  bool 'IODC console' CONFIG_IODC_CONSOLE
 
-config PROM_CONSOLE
-	bool "PROM console"
-	depends on SPARC
-	help
-	  Say Y to build a console driver for Sun machines that uses the
-	  terminal emulation built into their console PROMS.
-
 config DUMMY_CONSOLE
 	bool
-	depends on PROM_CONSOLE!=y || VGA_CONSOLE!=y || SGI_NEWPORT_CONSOLE!=y 
+	depends on VGA_CONSOLE!=y || SGI_NEWPORT_CONSOLE!=y
 	default y
 
 config DUMMY_CONSOLE_COLUMNS
diff --git a/drivers/video/console/Makefile b/drivers/video/console/Makefile
index ac46cc3f6a2a..a862e9173ebe 100644
--- a/drivers/video/console/Makefile
+++ b/drivers/video/console/Makefile
@@ -22,7 +22,6 @@ font-objs += $(font-objs-y)
 
 obj-$(CONFIG_DUMMY_CONSOLE)       += dummycon.o
 obj-$(CONFIG_SGI_NEWPORT_CONSOLE) += newport_con.o font.o
-obj-$(CONFIG_PROM_CONSOLE)        += promcon.o promcon_tbl.o
 obj-$(CONFIG_STI_CONSOLE)         += sticon.o sticore.o font.o
 obj-$(CONFIG_VGA_CONSOLE)         += vgacon.o
 obj-$(CONFIG_MDA_CONSOLE)         += mdacon.o
@@ -40,14 +39,3 @@ obj-$(CONFIG_FB_STI)              += sticore.o font.o
 ifeq ($(CONFIG_USB_SISUSBVGA_CON),y)
 obj-$(CONFIG_USB_SISUSBVGA)           += font.o
 endif
-
-# Targets that kbuild needs to know about
-targets := promcon_tbl.c
-
-quiet_cmd_conmakehash = CNMKHSH $@
-      cmd_conmakehash = scripts/conmakehash $< | \
-		sed -e '/\#include <[^>]*>/p' -e 's/types/init/' \
-		-e 's/dfont\(_uni.*\]\)/promfont\1 /' > $@
-
-$(obj)/promcon_tbl.c: $(src)/prom.uni
-	$(call cmd,conmakehash)
diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c
index 3a44695b9c09..29ff5ea3cc3c 100644
--- a/drivers/video/console/fbcon.c
+++ b/drivers/video/console/fbcon.c
@@ -114,6 +114,7 @@ static int last_fb_vc = MAX_NR_CONSOLES - 1;
 static int fbcon_is_default = 1; 
 static int fbcon_has_exited;
 static int primary_device = -1;
+static int fbcon_has_console_bind;
 
 #ifdef CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY
 static int map_override;
@@ -544,6 +545,8 @@ static int fbcon_takeover(int show_logo)
 			con2fb_map[i] = -1;
 		}
 		info_idx = -1;
+	} else {
+		fbcon_has_console_bind = 1;
 	}
 
 	return err;
@@ -2923,6 +2926,10 @@ static int fbcon_unbind(void)
 
 	ret = unbind_con_driver(&fb_con, first_fb_vc, last_fb_vc,
 				fbcon_is_default);
+
+	if (!ret)
+		fbcon_has_console_bind = 0;
+
 	return ret;
 }
 #else
@@ -2936,6 +2943,9 @@ static int fbcon_fb_unbind(int idx)
 {
 	int i, new_idx = -1, ret = 0;
 
+	if (!fbcon_has_console_bind)
+		return 0;
+
 	for (i = first_fb_vc; i <= last_fb_vc; i++) {
 		if (con2fb_map[i] != idx &&
 		    con2fb_map[i] != -1) {
diff --git a/drivers/video/matrox/g450_pll.c b/drivers/video/matrox/g450_pll.c
index d42346e7fdda..3dcb6d218f7c 100644
--- a/drivers/video/matrox/g450_pll.c
+++ b/drivers/video/matrox/g450_pll.c
@@ -341,7 +341,8 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
 					M1064_XDVICLKCTRL_C1DVICLKEN |
 					M1064_XDVICLKCTRL_DVILOOPCTL |
 					M1064_XDVICLKCTRL_P1LOOPBWDTCTL;
-				matroxfb_DAC_out(PMINFO M1064_XDVICLKCTRL,tmp);
+				/* Setting this breaks PC systems so don't do it */
+				/* matroxfb_DAC_out(PMINFO M1064_XDVICLKCTRL,tmp); */
 				matroxfb_DAC_out(PMINFO M1064_XPWRCTRL,
 						 xpwrctrl);
 
diff --git a/drivers/video/mxc/Kconfig b/drivers/video/mxc/Kconfig
index 268879626fc2..e86e6d86b978 100644
--- a/drivers/video/mxc/Kconfig
+++ b/drivers/video/mxc/Kconfig
@@ -26,12 +26,17 @@ config FB_MXC_EPSON_VGA_SYNC_PANEL
 
 config FB_MXC_TVOUT_TVE
 	tristate "MXC TVE TV Out Encoder"
-	depends on FB_MXC_SYNC_PANEL
-	depends on MXC_IPU_V3
+        depends on FB_MXC_SYNC_PANEL
+        depends on MXC_IPU_V3
+
+config FB_MXC_LDB
+        tristate "MXC LDB"
+        depends on FB_MXC_SYNC_PANEL
+        depends on MXC_IPU_V3
 
 config FB_MXC_CLAA_WVGA_SYNC_PANEL
-	depends on FB_MXC_SYNC_PANEL
-	tristate "CLAA WVGA Panel"
+        depends on FB_MXC_SYNC_PANEL
+        tristate "CLAA WVGA Panel"
 
 config FB_MXC_CH7026
 	depends on FB_MXC_SYNC_PANEL
@@ -43,12 +48,21 @@ config FB_MXC_TVOUT_CH7024
 
 config FB_MXC_LOW_PWR_DISPLAY
 	bool "Low Power Display Refresh Mode"
-	depends on FB_MXC_SYNC_PANEL && MXC_FB_IRAM
-	default y
+        depends on FB_MXC_SYNC_PANEL && MXC_FB_IRAM
+        default y
+
+config VIDEO_AD9389
+        tristate "Analog Devices AD9389/AD9889 digital video encoders"
+        depends on I2C && FB_MXC_SYNC_PANEL
+        ---help---
+          Support for the AD9389/AD9889 HDMI/DVI Video transmiter.
+
+          To compile this driver as a module, choose M here: the
+          module will be called ad9389.
 
 config FB_MXC_INTERNAL_MEM
-	bool "Framebuffer in Internal RAM"
-	depends on FB_MXC_SYNC_PANEL && MXC_FB_IRAM
+        bool "Framebuffer in Internal RAM"
+        depends on FB_MXC_SYNC_PANEL && MXC_FB_IRAM
 	default y
 
 config FB_MXC_ASYNC_PANEL
@@ -66,9 +80,24 @@ config FB_MXC_EPSON_PANEL
 
 endmenu
 
+config FB_MXC_EINK_PANEL
+        depends on FB_MXC
+        depends on DMA_ENGINE
+        select FB_DEFERRED_IO
+        tristate "E-Ink Panel Framebuffer"
+
+config FB_MXC_EINK_AUTO_UPDATE_MODE
+    bool "E-Ink Auto-update Mode Support"
+    default n
+    depends on FB_MXC_EINK_PANEL
+
+config FB_MXC_ELCDIF_FB
+        depends on FB && ARCH_MXC
+        tristate "Support MXC ELCDIF framebuffer"
+
 choice
-	prompt "Async Panel Interface Type"
-	depends on FB_MXC_ASYNC_PANEL && FB_MXC
+        prompt "Async Panel Interface Type"
+        depends on FB_MXC_ASYNC_PANEL && FB_MXC
 	default FB_MXC_ASYNC_PANEL_IFC_16_BIT
 
 config FB_MXC_ASYNC_PANEL_IFC_8_BIT
diff --git a/drivers/video/mxc/Makefile b/drivers/video/mxc/Makefile
index d2454aac2604..b47b3f77cd80 100644
--- a/drivers/video/mxc/Makefile
+++ b/drivers/video/mxc/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL)   += mxcfb_epson_vga.o
 obj-$(CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL)   += mxcfb_claa_wvga.o
 obj-$(CONFIG_FB_MXC_TVOUT_CH7024)           += ch7024.o
 obj-$(CONFIG_FB_MXC_TVOUT_TVE)              += tve.o
-obj-$(CONFIG_FB_MXC_CH7026)		    		+= mxcfb_ch7026.o
-#obj-$(CONFIG_FB_MODE_HELPERS)				+= mxc_edid.o
+obj-$(CONFIG_FB_MXC_CH7026)                             += mxcfb_ch7026.o
+#obj-$(CONFIG_FB_MODE_HELPERS)                           += mxc_edid.o
+obj-$(CONFIG_VIDEO_AD9389)                      += ad9389.o
diff --git a/drivers/video/mxc/ad9389.c b/drivers/video/mxc/ad9389.c
new file mode 100644
index 000000000000..9765cfd1a17f
--- /dev/null
+++ b/drivers/video/mxc/ad9389.c
@@ -0,0 +1,815 @@
+/*
+ * ad9389.c
+ *
+ * Copyright 2010 - Digi International, Inc. All Rights Reserved.
+ *
+ * Based on ad9889.c driver from Armadeus:
+ * Copyright (C) 2009 Armadeus Systems <nicolas.colombain@armadeus.com>
+ * And also on mxcfb_sii9022.c from Pegatron:
+ * Copyright 2009 Pegatron Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/proc_fs.h>
+#include <linux/fb.h>
+#include <linux/console.h>
+#include <video/ad9389.h>
+
+#define HPD_INT			0x80
+#define MSEN_INT		0x40
+#define	VS_INT			0x20
+#define	AUDIO_FIFO_FULL_INT	0x10
+#define	ITU656_ERR_INT		0x08
+#define EDID_RDY_INT		0x04
+#define EDID_LENGTH		256
+#define DRV_NAME		"ad9389"
+
+
+#define DEBUG
+#define I2C_DBG			0x0001
+#define EDID_DBG		0x0002
+#define REGS_DBG		0x0004
+#define SCREEN_DBG		0x0008
+
+//int debug = I2C_DBG | EDID_DBG | REGS_DBG | SCREEN_DBG;
+int debug = 0;
+#define DBG(flag, fmt, args...)	do {							\
+					if (debug & flag)				\
+						printk(KERN_DEBUG fmt, ## args);	\
+				} while (0)
+
+struct ad9389_dev *pad9389;
+
+
+static inline int ad9389_read_reg(struct i2c_client *client, u8 reg)
+{
+	return i2c_smbus_read_byte_data(client, reg);
+}
+
+static inline int ad9389_write_reg(struct i2c_client *client, u8 reg, u8 val)
+{
+	DBG(I2C_DBG, "I2C WR[%02x] = %02x\n", reg, val);
+	return i2c_smbus_write_byte_data(client, reg, val);
+}
+
+static inline int ad9389_update_reg(struct i2c_client *client, u8 reg, u8 mask, u8 val)
+{
+	u8 regval = i2c_smbus_read_byte_data(client, reg);
+	regval &= ~mask;
+	regval |= val;
+	return ad9389_write_reg(client, reg, regval);
+}
+
+static void ad9389_set_av_mute(struct i2c_client *client, int mute)
+{
+	if (mute) {
+		ad9389_update_reg(client, 0x45, 0x40, 0x40);
+		ad9389_update_reg(client, 0x45, 0x80, 0);
+	} else {
+		ad9389_update_reg(client, 0x45, 0x40, 0x0);
+		ad9389_update_reg(client, 0x45, 0x80, 0x80);
+	}
+}
+
+static void ad9389_set_power_down(struct i2c_client *client, int powerd)
+{
+	ad9389_update_reg(client, 0x41, 0x40, powerd ? 0x40 : 0);
+}
+
+static int ad9389_disp_connected(struct i2c_client *client)
+{
+	return (ad9389_read_reg(client, 0x42) & 0x40) != 0;
+}
+
+static void ad9389_enable_i2s_ch(struct i2c_client *client, u8 enable, u8 ch)
+{
+	u8 mask;
+
+	if (ch > 3)
+		return;
+
+	mask = 0x04 << ch;
+	ad9389_update_reg(client, 0x0c, mask, enable ? mask : 0);
+}
+
+static int ad9389_is_enabled_i2s_ch(struct i2c_client *client, u8 ch)
+{
+	u8 mask;
+
+	if (ch > 3)
+		return -EINVAL;
+
+	mask = 0x04 << ch;
+	return (i2c_smbus_read_byte_data(client, 0x0c) & mask) != 0;
+}
+
+static void ad9389_set_i2s_sf(struct i2c_client *client, int sample_freq)
+{
+	ad9389_update_reg(client, 0x15, 0xf0, sample_freq << 4);
+}
+
+static void ad9389_set_hdmi_mode(struct i2c_client *client, int hdmi)
+{
+	ad9389_update_reg(client, 0xaf, 0x02, hdmi ? 0x02 : 0);
+}
+
+static void ad9389_set_if_cc(struct i2c_client *client, int chcnt)
+{
+	ad9389_update_reg(client, 0x50, 0xe0, chcnt << 5);
+}
+
+static void ad9389_set_spk_map(struct i2c_client *client, int map)
+{
+	ad9389_write_reg(client, 0x51, map);
+}
+
+static void ad9389_set_N(struct i2c_client *client, int N_val)
+{
+	ad9389_write_reg(client, 0x1, N_val >> 16);
+	ad9389_write_reg(client, 0x2, N_val >> 8);
+	ad9389_write_reg(client, 0x3, N_val & 0xff);
+}
+
+static int ad9389_get_N(struct i2c_client *client)
+{
+	int N_val;
+
+	N_val = (ad9389_read_reg(client, 0x1) & 0x0f) << 16;
+	N_val |= (ad9389_read_reg(client, 0x2) << 8);
+	N_val |= ad9389_read_reg(client, 0x3);
+
+	return N_val;
+}
+
+#ifdef USED
+static void ad9389_audio_set_CTS(struct i2c_client *client, int cts)
+{
+	ad9389_update_reg(client, 0x04, 0x0f, (cts >> 16) & 0x0f);
+	ad9389_write_reg(client, 0x05, cts >> 8);
+	ad9389_write_reg(client, 0x6, cts & 0xff);
+}
+
+static void ad9389_set_i2s_nbits(struct i2c_client *client, int bits)
+{
+	if (bits <= 24)
+		ad9389_write_reg(client, 0x0d, bits);
+}
+
+static void ad9389_set_low_freq_vrr(struct i2c_client *client, int lowf)
+{
+	ad9389_update_reg(client, 0x15, 0x01, lowf ? 1 : 0);
+}
+#endif
+
+#ifdef DEBUG
+static void ad9389_dump_edid(u8 *edid)
+{
+	int i;
+
+	if (!(debug & EDID_DBG))
+		return;
+
+	printk("\nEDID data:\n");
+	for (i = 0; i < EDID_LENGTH; i++) {
+		if (i % 8 == 0)
+			printk("\n");
+		printk("%02x ", edid[i]);
+	}
+	printk("\n");
+}
+
+static void ad9389_dump_regs(struct i2c_client *client)
+{
+	int i;
+
+	if (!(debug & REGS_DBG))
+		return;
+
+	printk("\nAD9389 regs:\n");
+	for (i = 0; i < EDID_LENGTH; i++) {
+		if (i % 8 == 0)
+			printk("\n%03x: ", i);
+		printk("%02x ", ad9389_read_reg(client, i));
+	}
+	printk(KERN_DEBUG "\n");
+}
+
+static void fb_dump_modeline( struct fb_videomode *modedb, int num)
+{
+	struct fb_videomode *mode;
+	int i;
+
+	if (!(debug & SCREEN_DBG))
+		return;
+
+	printk(KERN_DEBUG "Monitor/TV supported modelines:\n");
+
+	for (i = 0; i < num; i++) {
+		mode = &modedb[i];
+
+		printk("   \"%dx%d%s%d\" %lu.%02lu ",
+			mode->xres, mode->yres, (mode->vmode & FB_VMODE_INTERLACED) ? "i@" : "@", mode->refresh,
+			(PICOS2KHZ(mode->pixclock) * 1000UL)/1000000,
+			(PICOS2KHZ(mode->pixclock) ) % 1000);
+		printk("%d %d %d %d ",
+			mode->xres,
+			mode->xres + mode->right_margin,
+			mode->xres + mode->right_margin + mode->hsync_len,
+			mode->xres + mode->right_margin + mode->hsync_len + mode->left_margin );
+		printk("%d %d %d %d ",
+			mode->yres,
+			mode->yres + mode->lower_margin,
+			mode->yres + mode->lower_margin + mode->vsync_len,
+			mode->yres + mode->lower_margin + mode->vsync_len + mode->upper_margin );
+		printk("%shsync %svsync\n", (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? "+" : "-",
+			   (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? "+" : "-" );
+	}
+}
+#else
+static void ad9389_dump_edid(u8 *edid) {}
+static void ad9389_dump_regs(struct i2c_client *client) {}
+static void fb_dump_modeline( struct fb_videomode *modedb, int num) {}
+#endif
+
+static int ad9389_read_edid(struct i2c_client *client, u8 *edid)
+{
+	union i2c_smbus_data data;
+	struct ad9389_pdata *config = client->dev.platform_data;
+	struct ad9389_dev *ad9389 = i2c_get_clientdata(client);
+	u8 *pd;
+	int status, i;
+
+	for (i = 0, pd = edid; i < EDID_LENGTH/I2C_SMBUS_BLOCK_MAX; i++, pd += I2C_SMBUS_BLOCK_MAX) {
+		data.block[0] = I2C_SMBUS_BLOCK_MAX;
+		status = i2c_smbus_xfer(ad9389->edid_ram->adapter, config->edid_addr,
+					ad9389->edid_ram->flags,
+					I2C_SMBUS_READ, i*I2C_SMBUS_BLOCK_MAX,
+					I2C_SMBUS_I2C_BLOCK_DATA, &data);
+		if (status < 0)
+			return status;
+		memcpy(pd, &data.block[1], data.block[0]);
+	}
+
+	return 0;
+}
+
+static int ad9389_parse_edid(struct fb_var_screeninfo *einfo, u8 *edid, int *dvi)
+{
+	int ret;
+
+	if (einfo == NULL || edid == NULL || dvi == NULL)
+		return -EINVAL;
+
+	if (edid[1] == 0x00)
+		return -ENOENT;
+
+	/* Assume dvi if no CEA extension */
+	*dvi = 1;
+	if (edid[126] > 0) {
+		/* CEA extensions */
+		if (edid[128] == 0x02 && edid[131] & 0x40) {
+			*dvi = 0;
+		}
+	}
+
+	ret = fb_parse_edid(edid, einfo);
+	if (ret)
+		return -ret;
+
+	/* This is valid for version 1.3 of the EDID */
+	if ((edid[18] == 1) && (edid[19] == 3)) {
+		einfo->height = edid[21] * 10;
+		einfo->width = edid[22] * 10;
+	}
+
+	return 0;
+}
+
+static void ad9389_audio_setup(struct ad9389_dev *ad9389)
+{
+	struct i2c_client *client = ad9389->client;
+
+	/* disable I2S channels */
+	ad9389_enable_i2s_ch(client, 0, 0);
+	ad9389_enable_i2s_ch(client, 0, 1);
+	ad9389_enable_i2s_ch(client, 0, 2);
+	ad9389_enable_i2s_ch(client, 0, 3);
+
+	/* Set sample freq, currently hardcoded to 44KHz */
+	ad9389_set_i2s_sf(client, 0);
+
+	/* By default, enable i2s ch0. Can be modified through the sysfs */
+	ad9389_set_N(client, 6272);
+	ad9389_set_if_cc(client, 1);
+	ad9389_set_spk_map(client, 0);
+	ad9389_enable_i2s_ch(client, 1, 0);
+	ad9389_set_av_mute(client, 0);
+}
+
+
+static void ad9389_fb_init(struct fb_info *info)
+{
+	struct ad9389_dev *ad9389 = pad9389;
+	struct i2c_client *client = ad9389->client;
+	struct ad9389_pdata *pdata = client->dev.platform_data;
+	static struct fb_var_screeninfo var;
+	int ret = 0;
+
+	dev_info(info->dev, "%s\n", __func__);
+
+	if (!ad9389_disp_connected(client)) {
+		ad9389_set_power_down(client, 1);
+		if(pdata->disp_disconnected)
+			pdata->disp_disconnected(ad9389);
+		return;
+	}
+
+	if(pdata->disp_connected)
+		pdata->disp_connected(ad9389);
+
+	dev_info(info->dev, "%s, display connected\n", __func__);
+	memset(&var, 0, sizeof(var));
+
+	/* Disable Power down and set mute to on */
+	ad9389_set_power_down(client, 0);
+	ad9389_set_av_mute(client, 1);
+
+	/* set static reserved registers*/
+	ad9389_write_reg(client,0x0a, 0x01);
+	ad9389_write_reg(client, 0x98, 0x03);
+	ad9389_write_reg(client, 0x9C, 0x38);
+
+	/* Write magic numbers */
+	ad9389_write_reg(client, 0xA2, 0x87);
+	ad9389_write_reg(client, 0xA3, 0x87);
+
+	/* set capture edge */
+	ad9389_write_reg(client, 0xba, 0x60);
+	ad9389_write_reg(client, 0x47, 0x80);
+
+	mdelay(250);
+
+	ret = ad9389_read_edid(ad9389->client, ad9389->edid_data);
+	if (!ret) {
+		ad9389_dump_edid(ad9389->edid_data);
+		ret = ad9389_parse_edid(&var, ad9389->edid_data, &ad9389->dvi);
+		if (!ret) {
+			if (!ad9389->dvi) {
+				ad9389_set_hdmi_mode(client, 1);
+				/* FIXME audio setup should be done once we know the pixclock */
+				ad9389_audio_setup(ad9389);
+			}
+
+			fb_edid_to_monspecs(ad9389->edid_data, &info->monspecs);
+			if (info->monspecs.modedb_len) {
+				fb_dump_modeline(info->monspecs.modedb, info->monspecs.modedb_len);
+				if (pdata->vmode_to_modelist)
+					pdata->vmode_to_modelist(info->monspecs.modedb,
+								 info->monspecs.modedb_len,
+								 &info->modelist, &var);
+				else
+					fb_videomode_to_modelist(info->monspecs.modedb,
+								 info->monspecs.modedb_len,
+								 &info->modelist);
+			}
+		}
+	} else {
+		/* TODO */
+		printk(KERN_WARNING "NO EDID information found, using default mode?\n");
+	}
+
+	ad9389_dump_regs(client);
+
+	if (pdata->vmode_to_var)
+		pdata->vmode_to_var(ad9389, &var);
+
+	var.activate = FB_ACTIVATE_ALL;
+	acquire_console_sem();
+	info->flags |= FBINFO_MISC_USEREVENT;
+	fb_set_var(info, &var);
+	info->flags &= ~FBINFO_MISC_USEREVENT;
+	fb_blank(info, FB_BLANK_UNBLANK);
+	fb_show_logo(info, 0);
+	release_console_sem();
+}
+
+int ad9389_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+	return 0;
+}
+
+static void ad9389_work(struct work_struct *work)
+{
+	struct ad9389_dev *ad9389 = container_of(work, struct ad9389_dev, work);
+	struct i2c_client *client =  ad9389->client;
+	unsigned char irq_reg1;
+	unsigned char irq_reg2;
+
+	dev_dbg(&client->dev, "%s\n", __func__);
+
+	mutex_lock(&ad9389->irq_lock);
+
+	/* Interrupts are disabled here... */
+	irq_reg1 = ad9389_read_reg(client, 0x96);
+	irq_reg2 = ad9389_read_reg(client, 0x97);
+
+	while ((irq_reg1 & 0xc4) | (irq_reg2 & 0xc0)) {
+
+		dev_dbg(&client->dev, "IRQ register %02x/%02x\n",
+			irq_reg1, irq_reg2);
+
+		/* hot plug detections interrupt? */
+		if (irq_reg1 & HPD_INT) {
+			dev_dbg(&client->dev, "HPD irq\n");
+			ad9389_fb_init(ad9389->fbi);
+		}
+
+		/* check for EDID ready flag, then call EDID Handler */
+		if (irq_reg1 & EDID_RDY_INT) {
+			dev_dbg(&client->dev, "EDID_RDY_INT\n");
+		}
+
+		/* ack and check again */
+		ad9389_write_reg(client, 0x96, irq_reg1);
+		ad9389_write_reg(client, 0x97, irq_reg2);
+
+		irq_reg1 = ad9389_read_reg(client, 0x96);
+		irq_reg2 = ad9389_read_reg(client, 0x97);
+	}
+
+	mutex_unlock(&ad9389->irq_lock);
+}
+
+
+static irqreturn_t ad9389_handler(int irq, void *dev_id)
+{
+	struct ad9389_dev *dev = (struct ad9389_dev *) dev_id;
+
+	dev_dbg(&dev->client->dev, "%s\n", __func__);
+	schedule_work(&dev->work);
+
+	return IRQ_HANDLED;
+}
+
+static ssize_t ad9389_show_mute(struct device *dev, struct device_attribute *attr,
+				char *buf)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	int read, ret = 0;
+
+	read = ad9389_read_reg(client, 0x45);
+	if (read & 0x40)
+		ret = snprintf(buf, PAGE_SIZE, "on");
+	else if (read & 0x80)
+	  	ret = snprintf(buf, PAGE_SIZE, "off");
+
+	return ret;
+}
+
+static ssize_t ad9389_store_mute(struct device *dev, struct device_attribute *attr,
+				 const char *buf, size_t count)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	int mute;
+
+	if (!strcmp(buf, "on"))
+	      mute = 1;
+	else if (!strcmp(buf, "off"))
+	      mute = 0;
+	else
+	      return 0;
+
+	ad9389_set_av_mute(client, mute);
+
+	return count;
+}
+
+static ssize_t ad9389_show_N_param(struct device *dev, struct device_attribute *attr,
+				char *buf)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	int N_val;
+
+	N_val = ad9389_get_N(client);
+
+	return snprintf(buf, PAGE_SIZE, "%d", N_val);
+}
+
+static ssize_t ad9389_store_N_param(struct device *dev, struct device_attribute *attr,
+				 const char *buf, size_t count)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	unsigned long N_val;
+
+	N_val = simple_strtoul(buf, NULL, 10);
+	ad9389_set_N(client, N_val);
+
+	return count;
+}
+
+#define	ad9389_show_i2s_ch(num)						\
+static ssize_t ad9389_show_i2s_ch##num(struct device *dev,		\
+				   struct device_attribute *attr,	\
+				   char *buf)				\
+{									\
+	struct i2c_client *client = to_i2c_client(dev);			\
+	int read, ret = 0;						\
+	read = ad9389_is_enabled_i2s_ch(client, num);			\
+	if (read < 0)							\
+		ret = snprintf(buf, PAGE_SIZE, "error");		\
+	else if (read == 1)						\
+		ret = snprintf(buf, PAGE_SIZE, "on");			\
+	else 								\
+	  	ret = snprintf(buf, PAGE_SIZE, "off");			\
+	return ret;							\
+}
+
+#define	ad9389_store_i2s_ch(num)					\
+static ssize_t ad9389_store_i2s_ch##num(struct device *dev,		\
+				    struct device_attribute *attr,	\
+				    const char *buf, size_t count)	\
+{									\
+	struct i2c_client *client = to_i2c_client(dev);			\
+	int enable;							\
+	if (!strcmp(buf, "on"))						\
+		enable = 1;						\
+	else if (!strcmp(buf, "off"))					\
+		enable = 0;						\
+	else								\
+		return 0;						\
+	ad9389_enable_i2s_ch(client, enable, num);			\
+	return count;							\
+}
+
+#define audio_ch(num)			\
+	static DEVICE_ATTR(i2s_ch##num, S_IWUSR | S_IRUGO, ad9389_show_i2s_ch##num, ad9389_store_i2s_ch##num)
+
+static DEVICE_ATTR(mute, S_IWUSR | S_IRUGO, ad9389_show_mute, ad9389_store_mute);
+static DEVICE_ATTR(N_param, S_IWUSR | S_IRUGO, ad9389_show_N_param, ad9389_store_N_param);
+
+ad9389_show_i2s_ch(0)
+ad9389_show_i2s_ch(1)
+ad9389_show_i2s_ch(2)
+ad9389_show_i2s_ch(3)
+ad9389_store_i2s_ch(0)
+ad9389_store_i2s_ch(1)
+ad9389_store_i2s_ch(2)
+ad9389_store_i2s_ch(3)
+audio_ch(0);
+audio_ch(1);
+audio_ch(2);
+audio_ch(3);
+
+static struct attribute *ad9389_attributes[] = {
+	&dev_attr_mute.attr,
+	&dev_attr_i2s_ch0.attr,
+	&dev_attr_i2s_ch1.attr,
+	&dev_attr_i2s_ch2.attr,
+	&dev_attr_i2s_ch3.attr,
+	&dev_attr_N_param.attr,
+	NULL
+};
+
+static const struct attribute_group ad9389_attr_group = {
+	.attrs = ad9389_attributes,
+};
+
+static struct notifier_block nb = {
+	.notifier_call = ad9389_fb_event,
+};
+
+static int ad9389_probe(struct i2c_client *client,
+        const struct i2c_device_id *id)
+{
+	struct ad9389_pdata *pdata = client->dev.platform_data;
+	struct ad9389_dev *ad9389;
+	int ret = -EINVAL;
+
+	/* Sanity checks */
+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+		return -EIO;
+
+	if (!pdata) {
+		printk(KERN_ERR DRV_NAME ": Platform data not supplied\n");
+		return -ENOENT;
+	}
+
+	if (!client->irq) {
+		printk(KERN_ERR DRV_NAME ": Invalid irq value\n");
+		return -ENOENT;
+	}
+
+	ad9389 = kzalloc(sizeof(struct ad9389_dev), GFP_KERNEL);
+	if (ad9389 == NULL)
+		return -ENOMEM;
+
+	ad9389->edid_data = kmalloc(EDID_LENGTH, GFP_KERNEL);
+	if (ad9389->edid_data == NULL) {
+		ret = -ENOMEM;
+		goto err_edid_alloc;
+	}
+
+	pad9389 = ad9389;
+	ad9389->client = client;
+	i2c_set_clientdata(client, ad9389);
+
+	INIT_WORK(&ad9389->work, ad9389_work);
+	mutex_init(&ad9389->irq_lock);
+	mutex_lock(&ad9389->irq_lock);
+
+	/* platform specific initialization (gpio, irq...) */
+	if (pdata->hw_init)
+		pdata->hw_init(ad9389);
+
+	ret = request_irq(client->irq, ad9389_handler,
+			  IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, DRV_NAME, ad9389);
+	if (ret < 0) {
+		printk(KERN_ERR DRV_NAME ": Could not allocate IRQ (n %d)\n", client->irq);
+		goto err_irq;
+	}
+
+	/**
+	 * There is no good way to detect if the chip is present. We assume that its present
+	 * because somebody answered (ack) on the device address...
+	 */
+	ret = ad9389_read_reg(client, 0x00);
+	if (ret < 0) {
+		printk(KERN_WARNING DRV_NAME ": i2c transfer error, (device present?)\n");
+		ret = -ENODEV;
+		goto err_presence;
+	}
+
+	ad9389->chiprev = (u8)ret;
+	ad9389->edid_ram = i2c_new_dummy(client->adapter, pdata->edid_addr);
+	if (!ad9389->edid_ram) {
+		printk(KERN_WARNING DRV_NAME ": can't add i2c device at 0x%x\n", pdata->edid_addr);
+		goto err_presence;
+	}
+
+	/* Register sysfs hooks */
+	ret = sysfs_create_group(&client->dev.kobj, &ad9389_attr_group);
+	if (ret)
+		goto err_sysfs_file;
+
+	ad9389->fbi = registered_fb[pdata->dispif];
+	fb_register_client(&nb);
+
+	/* Ack any active interrupt and enable irqs */
+	ad9389_write_reg(client, 0x94, 0x84);
+	ad9389_write_reg(client, 0x95, 0xc3);
+	ad9389_write_reg(client, 0x96, 0x84);
+	ad9389_write_reg(client, 0x97, 0xc3);
+
+	mutex_unlock(&ad9389->irq_lock);
+
+	ad9389_fb_init(registered_fb[pdata->dispif]);
+
+	printk(KERN_INFO DRV_NAME ": device detected at address 0x%x, chip revision 0x%02x\n",
+	       client->addr << 1, ad9389->chiprev);
+
+	return 0;
+
+err_sysfs_file:
+	i2c_unregister_device(ad9389->edid_ram);
+err_presence:
+	free_irq(client->irq, ad9389);
+err_irq:
+	flush_scheduled_work();
+	if (pdata->hw_deinit)
+		pdata->hw_deinit(ad9389);
+	kfree(ad9389->edid_data);
+err_edid_alloc:
+	kfree(ad9389);
+	pad9389 = NULL;
+	return ret;
+}
+
+static int ad9389_remove(struct i2c_client *client)
+{
+	struct ad9389_pdata *pdata = client->dev.platform_data;
+	struct ad9389_dev *ad9389 = i2c_get_clientdata(client);
+
+	free_irq(client->irq, ad9389);
+	flush_scheduled_work();
+	sysfs_remove_group(&client->dev.kobj, &ad9389_attr_group);
+	i2c_unregister_device(ad9389->edid_ram);
+	fb_unregister_client(&nb);
+	kfree(ad9389->edid_data);
+	kfree(ad9389);
+	pad9389 = NULL;
+
+	if (pdata->hw_deinit)
+		pdata->hw_deinit(ad9389);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int ad9389_suspend(struct i2c_client *client, pm_message_t state)
+{
+	dev_dbg(&client->dev, "PM suspend\n");
+	ad9389_set_power_down(client, 1);
+
+	return 0;
+}
+
+static int ad9389_resume(struct i2c_client *client)
+{
+	struct ad9389_dev *ad9389 = pad9389;
+	int ret;
+	static struct fb_var_screeninfo var;
+
+	dev_dbg(&client->dev, "PM resume\n");
+
+	/* Disable Power down and set mute to on */
+	ad9389_set_power_down(client, 0);
+	ad9389_set_av_mute(client, 1);
+
+	/* set static reserved registers*/
+	ad9389_write_reg(client,0x0a, 0x01);
+	ad9389_write_reg(client, 0x98, 0x03);
+	ad9389_write_reg(client, 0x9C, 0x38);
+
+	/* Write magic numbers */
+	ad9389_write_reg(client, 0xA2, 0x87);
+	ad9389_write_reg(client, 0xA3, 0x87);
+
+	/* set capture edge */
+	ad9389_write_reg(client, 0xba, 0x60);
+	ad9389_write_reg(client, 0x47, 0x80);
+
+	mdelay(250);
+
+	ret = ad9389_read_edid(ad9389->client, ad9389->edid_data);
+	if (!ret) {
+		ad9389_dump_edid(ad9389->edid_data);
+		ret = ad9389_parse_edid(&var, ad9389->edid_data, &ad9389->dvi);
+		if (!ret) {
+			if (!ad9389->dvi) {
+				ad9389_set_hdmi_mode(client, 1);
+				/* FIXME audio setup should be done once we know the pixclock */
+				ad9389_audio_setup(ad9389);
+			}
+		}
+	}
+	return 0;
+}
+#else
+#define ad9389_suspend	NULL
+#define ad9389_resume	NULL
+#endif
+
+
+static struct i2c_device_id ad9389_id[] = {
+	{ "ad9389", 0 },
+	{},
+};
+MODULE_DEVICE_TABLE(i2c, ad9389_id);
+
+static struct i2c_driver ad9389_driver = {
+	.driver = {
+		.name = "ad9389",
+	},
+	.probe		= ad9389_probe,
+	.remove		= ad9389_remove,
+	.suspend	= ad9389_suspend,
+	.resume		= ad9389_resume,
+	.id_table	= ad9389_id,
+
+};
+
+static int __init ad9389_init(void)
+{
+	return i2c_add_driver(&ad9389_driver);
+}
+
+static void __exit ad9389_exit(void)
+{
+	i2c_del_driver(&ad9389_driver);
+}
+
+module_init(ad9389_init);
+module_exit(ad9389_exit);
+
+MODULE_DESCRIPTION("AD9389 hdmi/dvi driver");
+MODULE_AUTHOR("Digi International Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/ccwmx51_display.c b/drivers/video/mxc/ccwmx51_display.c
index 70a5b25f3fe9..212f59e919e4 100755
--- a/drivers/video/mxc/ccwmx51_display.c
+++ b/drivers/video/mxc/ccwmx51_display.c
@@ -22,23 +22,37 @@
 #include <mach/hardware.h>
 #include <mach/mxc.h>
 
+#define MAX_DISPLAYS	2
+#define DISP0_ID	"DISP3 BG"
+#define DISP1_ID	"DISP3 BG - DI1"
+
 static void lcd_poweron(struct ccwmx51_lcd_pdata *plat);
 static void lcd_poweroff(struct ccwmx51_lcd_pdata *plat);
 
-static struct platform_device *plcd_dev;
+static struct platform_device *plcd_dev[MAX_DISPLAYS] = {NULL, NULL};
+
+static int lcd_get_index(struct fb_info *info)
+{
+	if (!strcmp(info->fix.id, DISP0_ID))
+		return 0;
+	else if (!strcmp(info->fix.id, DISP1_ID))
+		return 1;
+	return -1;
+}
 
 static void lcd_init_fb(struct fb_info *info)
 {
-	struct ccwmx51_lcd_pdata *plat = plcd_dev->dev.platform_data;
 	struct fb_var_screeninfo var;
+	struct ccwmx51_lcd_pdata *plat;
+	int i = lcd_get_index(info);
 
-	memset(&var, 0, sizeof(var));
+	if (i < 0)
+		return;
 
+	plat = plcd_dev[i]->dev.platform_data;
+	memset(&var, 0, sizeof(var));
 	fb_videomode_to_var(&var, plat->fb_pdata.mode);
-
 	var.activate = FB_ACTIVATE_ALL;
-	var.yres_virtual = var.yres;
-
 	acquire_console_sem();
 	info->flags |= FBINFO_MISC_USEREVENT;
 	fb_set_var(info, &var);
@@ -74,18 +88,37 @@ static struct notifier_block nb = {
 static int __devinit lcd_sync_probe(struct platform_device *pdev)
 {
 	struct ccwmx51_lcd_pdata *plat = pdev->dev.platform_data;
+	int i;
+
+	if (!plat)
+		return -ENODEV;
 
- 	if (!plat)
- 		return -ENODEV;
+	if (plat->vif < 0 || plat->vif > (MAX_DISPLAYS - 1))
+		return -EINVAL;
 
-	if (plat->reset)
-		plat->reset();
+	if (plat->init)
+		plat->init(plat->vif);
 
-	plcd_dev = pdev;
-	lcd_init_fb(registered_fb[plat->vif]);
-	fb_show_logo(registered_fb[plat->vif], 0);
-	fb_register_client(&nb);
+	plcd_dev[plat->vif] = pdev;
 
+	for (i = 0; i < num_registered_fb; i++) {
+		if ((!strcmp(registered_fb[i]->fix.id, DISP0_ID) && plat->vif == 0) ||
+		    (!strcmp(registered_fb[i]->fix.id, DISP1_ID) && plat->vif == 1)) {
+			lcd_init_fb(registered_fb[i]);
+			/* Clear the screen */
+			memset((char *)registered_fb[i]->screen_base, 0,
+			       registered_fb[i]->fix.smem_len);
+			fb_show_logo(registered_fb[i], 0);
+		}
+	}
+
+	/**
+	 * Register the block notifier only once. The device being notified can be
+	 * retrieved from the received event. There are some issues when the same
+	 * notifier is registered multiple times.
+	 */
+	if (plcd_dev[0] == NULL && plcd_dev[1] == NULL)
+		fb_register_client(&nb);
 	lcd_poweron(plat);
 
 	return 0;
@@ -95,9 +128,14 @@ static int __devexit lcd_sync_remove(struct platform_device *pdev)
 {
 	struct ccwmx51_lcd_pdata *plat = pdev->dev.platform_data;
 
-	fb_unregister_client(&nb);
 	lcd_poweroff(plat);
-	plcd_dev = NULL;
+	if (plat->deinit)
+		plat->deinit(plat->vif);
+
+	plcd_dev[plat->vif] = NULL;
+
+	if (plcd_dev[0] == NULL && plcd_dev[1] == NULL)
+		fb_unregister_client(&nb);
 
 	return 0;
 }
@@ -129,14 +167,14 @@ static struct platform_driver lcd_driver = {
 
 static void lcd_poweron(struct ccwmx51_lcd_pdata *plat)
 {
-	if (plat && plat->bl_enable)
-		plat->bl_enable(0);
+        if (plat && plat->bl_enable)
+                plat->bl_enable(1, plat->vif);
 }
 
 static void lcd_poweroff(struct ccwmx51_lcd_pdata *plat)
 {
-	if (plat && plat->bl_enable)
-		plat->bl_enable(1);
+        if (plat && plat->bl_enable)
+                plat->bl_enable(0, plat->vif);
 }
 
 static int __init lcd_sync_init(void)
diff --git a/drivers/video/mxc/elcdif_regs.h b/drivers/video/mxc/elcdif_regs.h
new file mode 100644
index 000000000000..2eceba5864e0
--- /dev/null
+++ b/drivers/video/mxc/elcdif_regs.h
@@ -0,0 +1,678 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+/*
+ * Based on arch/arm/mach-mx28/include/mach/regs-lcdif.h.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+#ifndef __ELCDIF_REGS_INCLUDED_
+#define __ELCDIF_REGS_INCLUDED_
+
+#define HW_ELCDIF_CTRL	(0x00000000)
+#define HW_ELCDIF_CTRL_SET	(0x00000004)
+#define HW_ELCDIF_CTRL_CLR	(0x00000008)
+#define HW_ELCDIF_CTRL_TOG	(0x0000000c)
+
+#define BM_ELCDIF_CTRL_SFTRST	0x80000000
+#define BM_ELCDIF_CTRL_CLKGATE	0x40000000
+#define BM_ELCDIF_CTRL_YCBCR422_INPUT	0x20000000
+#define BM_ELCDIF_CTRL_READ_WRITEB	0x10000000
+#define BM_ELCDIF_CTRL_WAIT_FOR_VSYNC_EDGE	0x08000000
+#define BM_ELCDIF_CTRL_DATA_SHIFT_DIR	0x04000000
+#define BV_ELCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT  0x0
+#define BV_ELCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT 0x1
+#define BP_ELCDIF_CTRL_SHIFT_NUM_BITS	21
+#define BM_ELCDIF_CTRL_SHIFT_NUM_BITS	0x03E00000
+#define BF_ELCDIF_CTRL_SHIFT_NUM_BITS(v)  \
+		(((v) << 21) & BM_ELCDIF_CTRL_SHIFT_NUM_BITS)
+#define BM_ELCDIF_CTRL_DVI_MODE	0x00100000
+#define BM_ELCDIF_CTRL_BYPASS_COUNT	0x00080000
+#define BM_ELCDIF_CTRL_VSYNC_MODE	0x00040000
+#define BM_ELCDIF_CTRL_DOTCLK_MODE	0x00020000
+#define BM_ELCDIF_CTRL_DATA_SELECT	0x00010000
+#define BV_ELCDIF_CTRL_DATA_SELECT__CMD_MODE  0x0
+#define BV_ELCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1
+#define BP_ELCDIF_CTRL_INPUT_DATA_SWIZZLE	14
+#define BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE	0x0000C000
+#define BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(v)  \
+		(((v) << 14) & BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE)
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP         0x0
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN   0x0
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES  0x1
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP        0x2
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP   0x3
+#define BP_ELCDIF_CTRL_CSC_DATA_SWIZZLE	12
+#define BM_ELCDIF_CTRL_CSC_DATA_SWIZZLE	0x00003000
+#define BF_ELCDIF_CTRL_CSC_DATA_SWIZZLE(v)  \
+		(((v) << 12) & BM_ELCDIF_CTRL_CSC_DATA_SWIZZLE)
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP         0x0
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN   0x0
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES  0x1
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP        0x2
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP   0x3
+#define BP_ELCDIF_CTRL_LCD_DATABUS_WIDTH	10
+#define BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH	0x00000C00
+#define BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(v)  \
+		(((v) << 10) & BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH)
+#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT 0x0
+#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT  0x1
+#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT 0x2
+#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT 0x3
+#define BP_ELCDIF_CTRL_WORD_LENGTH	8
+#define BM_ELCDIF_CTRL_WORD_LENGTH	0x00000300
+#define BF_ELCDIF_CTRL_WORD_LENGTH(v)  \
+		(((v) << 8) & BM_ELCDIF_CTRL_WORD_LENGTH)
+#define BV_ELCDIF_CTRL_WORD_LENGTH__16_BIT 0x0
+#define BV_ELCDIF_CTRL_WORD_LENGTH__8_BIT  0x1
+#define BV_ELCDIF_CTRL_WORD_LENGTH__18_BIT 0x2
+#define BV_ELCDIF_CTRL_WORD_LENGTH__24_BIT 0x3
+#define BM_ELCDIF_CTRL_RGB_TO_YCBCR422_CSC	0x00000080
+#define BM_ELCDIF_CTRL_ENABLE_PXP_HANDSHAKE	0x00000040
+#define BM_ELCDIF_CTRL_ELCDIF_MASTER	0x00000020
+#define BM_ELCDIF_CTRL_RSRVD0	0x00000010
+#define BM_ELCDIF_CTRL_DATA_FORMAT_16_BIT	0x00000008
+#define BM_ELCDIF_CTRL_DATA_FORMAT_18_BIT	0x00000004
+#define BV_ELCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID 0x0
+#define BV_ELCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID 0x1
+#define BM_ELCDIF_CTRL_DATA_FORMAT_24_BIT	0x00000002
+#define BV_ELCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID          0x0
+#define BV_ELCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE 0x1
+#define BM_ELCDIF_CTRL_RUN	0x00000001
+
+#define HW_ELCDIF_CTRL1	(0x00000010)
+#define HW_ELCDIF_CTRL1_SET	(0x00000014)
+#define HW_ELCDIF_CTRL1_CLR	(0x00000018)
+#define HW_ELCDIF_CTRL1_TOG	(0x0000001c)
+
+#define BP_ELCDIF_CTRL1_RSRVD1	28
+#define BM_ELCDIF_CTRL1_RSRVD1	0xF0000000
+#define BF_ELCDIF_CTRL1_RSRVD1(v) \
+		(((v) << 28) & BM_ELCDIF_CTRL1_RSRVD1)
+#define BM_ELCDIF_CTRL1_COMBINE_MPU_WR_STRB	0x08000000
+#define BM_ELCDIF_CTRL1_BM_ERROR_IRQ_EN	0x04000000
+#define BM_ELCDIF_CTRL1_BM_ERROR_IRQ	0x02000000
+#define BV_ELCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_BM_ERROR_IRQ__REQUEST    0x1
+#define BM_ELCDIF_CTRL1_RECOVER_ON_UNDERFLOW	0x01000000
+#define BM_ELCDIF_CTRL1_INTERLACE_FIELDS	0x00800000
+#define BM_ELCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD	0x00400000
+#define BM_ELCDIF_CTRL1_FIFO_CLEAR	0x00200000
+#define BM_ELCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS	0x00100000
+#define BP_ELCDIF_CTRL1_BYTE_PACKING_FORMAT	16
+#define BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT	0x000F0000
+#define BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(v)  \
+		(((v) << 16) & BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT)
+#define BM_ELCDIF_CTRL1_OVERFLOW_IRQ_EN	0x00008000
+#define BM_ELCDIF_CTRL1_UNDERFLOW_IRQ_EN	0x00004000
+#define BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN	0x00002000
+#define BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ_EN	0x00001000
+#define BM_ELCDIF_CTRL1_OVERFLOW_IRQ	0x00000800
+#define BV_ELCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_OVERFLOW_IRQ__REQUEST    0x1
+#define BM_ELCDIF_CTRL1_UNDERFLOW_IRQ	0x00000400
+#define BV_ELCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST    0x1
+#define BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ	0x00000200
+#define BV_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST    0x1
+#define BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ	0x00000100
+#define BV_ELCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST    0x1
+#define BP_ELCDIF_CTRL1_RSRVD0	3
+#define BM_ELCDIF_CTRL1_RSRVD0	0x000000F8
+#define BF_ELCDIF_CTRL1_RSRVD0(v)  \
+		(((v) << 3) & BM_ELCDIF_CTRL1_RSRVD0)
+#define BM_ELCDIF_CTRL1_BUSY_ENABLE	0x00000004
+#define BV_ELCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED 0x0
+#define BV_ELCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED  0x1
+#define BM_ELCDIF_CTRL1_MODE86	0x00000002
+#define BV_ELCDIF_CTRL1_MODE86__8080_MODE 0x0
+#define BV_ELCDIF_CTRL1_MODE86__6800_MODE 0x1
+#define BM_ELCDIF_CTRL1_RESET	0x00000001
+#define BV_ELCDIF_CTRL1_RESET__LCDRESET_LOW  0x0
+#define BV_ELCDIF_CTRL1_RESET__LCDRESET_HIGH 0x1
+
+#define HW_ELCDIF_CTRL2	(0x00000020)
+#define HW_ELCDIF_CTRL2_SET	(0x00000024)
+#define HW_ELCDIF_CTRL2_CLR	(0x00000028)
+#define HW_ELCDIF_CTRL2_TOG	(0x0000002c)
+
+#define BP_ELCDIF_CTRL2_RSRVD5	24
+#define BM_ELCDIF_CTRL2_RSRVD5	0xFF000000
+#define BF_ELCDIF_CTRL2_RSRVD5(v) \
+		(((v) << 24) & BM_ELCDIF_CTRL2_RSRVD5)
+#define BP_ELCDIF_CTRL2_OUTSTANDING_REQS	21
+#define BM_ELCDIF_CTRL2_OUTSTANDING_REQS	0x00E00000
+#define BF_ELCDIF_CTRL2_OUTSTANDING_REQS(v)  \
+		(((v) << 21) & BM_ELCDIF_CTRL2_OUTSTANDING_REQS)
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_1  0x0
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_2  0x1
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_4  0x2
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_8  0x3
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_16 0x4
+#define BM_ELCDIF_CTRL2_BURST_LEN_8	0x00100000
+#define BM_ELCDIF_CTRL2_RSRVD4	0x00080000
+#define BP_ELCDIF_CTRL2_ODD_LINE_PATTERN	16
+#define BM_ELCDIF_CTRL2_ODD_LINE_PATTERN	0x00070000
+#define BF_ELCDIF_CTRL2_ODD_LINE_PATTERN(v)  \
+		(((v) << 16) & BM_ELCDIF_CTRL2_ODD_LINE_PATTERN)
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__RGB 0x0
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__RBG 0x1
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__GBR 0x2
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__GRB 0x3
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__BRG 0x4
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__BGR 0x5
+#define BM_ELCDIF_CTRL2_RSRVD3	0x00008000
+#define BP_ELCDIF_CTRL2_EVEN_LINE_PATTERN	12
+#define BM_ELCDIF_CTRL2_EVEN_LINE_PATTERN	0x00007000
+#define BF_ELCDIF_CTRL2_EVEN_LINE_PATTERN(v)  \
+		(((v) << 12) & BM_ELCDIF_CTRL2_EVEN_LINE_PATTERN)
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__RGB 0x0
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__RBG 0x1
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__GBR 0x2
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__GRB 0x3
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__BRG 0x4
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__BGR 0x5
+#define BM_ELCDIF_CTRL2_RSRVD2	0x00000800
+#define BM_ELCDIF_CTRL2_READ_PACK_DIR	0x00000400
+#define BM_ELCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT	0x00000200
+#define BM_ELCDIF_CTRL2_READ_MODE_6_BIT_INPUT	0x00000100
+#define BM_ELCDIF_CTRL2_RSRVD1	0x00000080
+#define BP_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS	4
+#define BM_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS	0x00000070
+#define BF_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(v)  \
+		(((v) << 4) & BM_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS)
+#define BP_ELCDIF_CTRL2_INITIAL_DUMMY_READ	1
+#define BM_ELCDIF_CTRL2_INITIAL_DUMMY_READ	0x0000000E
+#define BF_ELCDIF_CTRL2_INITIAL_DUMMY_READ(v)  \
+		(((v) << 1) & BM_ELCDIF_CTRL2_INITIAL_DUMMY_READ)
+#define BM_ELCDIF_CTRL2_RSRVD0	0x00000001
+
+#define HW_ELCDIF_TRANSFER_COUNT	(0x00000030)
+
+#define BP_ELCDIF_TRANSFER_COUNT_V_COUNT	16
+#define BM_ELCDIF_TRANSFER_COUNT_V_COUNT	0xFFFF0000
+#define BF_ELCDIF_TRANSFER_COUNT_V_COUNT(v) \
+		(((v) << 16) & BM_ELCDIF_TRANSFER_COUNT_V_COUNT)
+#define BP_ELCDIF_TRANSFER_COUNT_H_COUNT	0
+#define BM_ELCDIF_TRANSFER_COUNT_H_COUNT	0x0000FFFF
+#define BF_ELCDIF_TRANSFER_COUNT_H_COUNT(v)  \
+		(((v) << 0) & BM_ELCDIF_TRANSFER_COUNT_H_COUNT)
+
+#define HW_ELCDIF_CUR_BUF	(0x00000040)
+
+#define BP_ELCDIF_CUR_BUF_ADDR	0
+#define BM_ELCDIF_CUR_BUF_ADDR	0xFFFFFFFF
+#define BF_ELCDIF_CUR_BUF_ADDR(v)	(v)
+
+#define HW_ELCDIF_NEXT_BUF	(0x00000050)
+
+#define BP_ELCDIF_NEXT_BUF_ADDR	0
+#define BM_ELCDIF_NEXT_BUF_ADDR	0xFFFFFFFF
+#define BF_ELCDIF_NEXT_BUF_ADDR(v)	(v)
+
+#define HW_ELCDIF_TIMING	(0x00000060)
+
+#define BP_ELCDIF_TIMING_CMD_HOLD	24
+#define BM_ELCDIF_TIMING_CMD_HOLD	0xFF000000
+#define BF_ELCDIF_TIMING_CMD_HOLD(v) \
+		(((v) << 24) & BM_ELCDIF_TIMING_CMD_HOLD)
+#define BP_ELCDIF_TIMING_CMD_SETUP	16
+#define BM_ELCDIF_TIMING_CMD_SETUP	0x00FF0000
+#define BF_ELCDIF_TIMING_CMD_SETUP(v)  \
+		(((v) << 16) & BM_ELCDIF_TIMING_CMD_SETUP)
+#define BP_ELCDIF_TIMING_DATA_HOLD	8
+#define BM_ELCDIF_TIMING_DATA_HOLD	0x0000FF00
+#define BF_ELCDIF_TIMING_DATA_HOLD(v)  \
+		(((v) << 8) & BM_ELCDIF_TIMING_DATA_HOLD)
+#define BP_ELCDIF_TIMING_DATA_SETUP	0
+#define BM_ELCDIF_TIMING_DATA_SETUP	0x000000FF
+#define BF_ELCDIF_TIMING_DATA_SETUP(v)  \
+		(((v) << 0) & BM_ELCDIF_TIMING_DATA_SETUP)
+
+#define HW_ELCDIF_VDCTRL0	(0x00000070)
+#define HW_ELCDIF_VDCTRL0_SET	(0x00000074)
+#define HW_ELCDIF_VDCTRL0_CLR	(0x00000078)
+#define HW_ELCDIF_VDCTRL0_TOG	(0x0000007c)
+
+#define BP_ELCDIF_VDCTRL0_RSRVD2	30
+#define BM_ELCDIF_VDCTRL0_RSRVD2	0xC0000000
+#define BF_ELCDIF_VDCTRL0_RSRVD2(v) \
+		(((v) << 30) & BM_ELCDIF_VDCTRL0_RSRVD2)
+#define BM_ELCDIF_VDCTRL0_VSYNC_OEB	0x20000000
+#define BV_ELCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT 0x0
+#define BV_ELCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT  0x1
+#define BM_ELCDIF_VDCTRL0_ENABLE_PRESENT	0x10000000
+#define BM_ELCDIF_VDCTRL0_VSYNC_POL	0x08000000
+#define BM_ELCDIF_VDCTRL0_HSYNC_POL	0x04000000
+#define BM_ELCDIF_VDCTRL0_DOTCLK_POL	0x02000000
+#define BM_ELCDIF_VDCTRL0_ENABLE_POL	0x01000000
+#define BP_ELCDIF_VDCTRL0_RSRVD1	22
+#define BM_ELCDIF_VDCTRL0_RSRVD1	0x00C00000
+#define BF_ELCDIF_VDCTRL0_RSRVD1(v)  \
+		(((v) << 22) & BM_ELCDIF_VDCTRL0_RSRVD1)
+#define BM_ELCDIF_VDCTRL0_VSYNC_PERIOD_UNIT	0x00200000
+#define BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT	0x00100000
+#define BM_ELCDIF_VDCTRL0_HALF_LINE	0x00080000
+#define BM_ELCDIF_VDCTRL0_HALF_LINE_MODE	0x00040000
+#define BP_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH	0
+#define BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH	0x0003FFFF
+#define BF_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v)  \
+		(((v) << 0) & BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH)
+
+#define HW_ELCDIF_VDCTRL1	(0x00000080)
+
+#define BP_ELCDIF_VDCTRL1_VSYNC_PERIOD	0
+#define BM_ELCDIF_VDCTRL1_VSYNC_PERIOD	0xFFFFFFFF
+#define BF_ELCDIF_VDCTRL1_VSYNC_PERIOD(v)	(v)
+
+#define HW_ELCDIF_VDCTRL2	(0x00000090)
+
+#define BP_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH	18
+#define BM_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH	0xFFFC0000
+#define BF_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v) \
+		(((v) << 18) & BM_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH)
+#define BP_ELCDIF_VDCTRL2_HSYNC_PERIOD	0
+#define BM_ELCDIF_VDCTRL2_HSYNC_PERIOD	0x0003FFFF
+#define BF_ELCDIF_VDCTRL2_HSYNC_PERIOD(v)  \
+		(((v) << 0) & BM_ELCDIF_VDCTRL2_HSYNC_PERIOD)
+
+#define HW_ELCDIF_VDCTRL3	(0x000000a0)
+
+#define BP_ELCDIF_VDCTRL3_RSRVD0	30
+#define BM_ELCDIF_VDCTRL3_RSRVD0	0xC0000000
+#define BF_ELCDIF_VDCTRL3_RSRVD0(v) \
+		(((v) << 30) & BM_ELCDIF_VDCTRL3_RSRVD0)
+#define BM_ELCDIF_VDCTRL3_MUX_SYNC_SIGNALS	0x20000000
+#define BM_ELCDIF_VDCTRL3_VSYNC_ONLY	0x10000000
+#define BP_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT	16
+#define BM_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT	0x0FFF0000
+#define BF_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v)  \
+		(((v) << 16) & BM_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT)
+#define BP_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT	0
+#define BM_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT	0x0000FFFF
+#define BF_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v)  \
+		(((v) << 0) & BM_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT)
+
+#define HW_ELCDIF_VDCTRL4	(0x000000b0)
+
+#define BP_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL	29
+#define BM_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL	0xE0000000
+#define BF_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL(v) \
+		(((v) << 29) & BM_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL)
+#define BP_ELCDIF_VDCTRL4_RSRVD0	19
+#define BM_ELCDIF_VDCTRL4_RSRVD0	0x1FF80000
+#define BF_ELCDIF_VDCTRL4_RSRVD0(v)  \
+		(((v) << 19) & BM_ELCDIF_VDCTRL4_RSRVD0)
+#define BM_ELCDIF_VDCTRL4_SYNC_SIGNALS_ON	0x00040000
+#define BP_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT	0
+#define BM_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT	0x0003FFFF
+#define BF_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v)  \
+		(((v) << 0) & BM_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT)
+
+#define HW_ELCDIF_DVICTRL0	(0x000000c0)
+
+#define BP_ELCDIF_DVICTRL0_RSRVD1	28
+#define BM_ELCDIF_DVICTRL0_RSRVD1	0xF0000000
+#define BF_ELCDIF_DVICTRL0_RSRVD1(v) \
+		(((v) << 28) & BM_ELCDIF_DVICTRL0_RSRVD1)
+#define BP_ELCDIF_DVICTRL0_H_ACTIVE_CNT	16
+#define BM_ELCDIF_DVICTRL0_H_ACTIVE_CNT	0x0FFF0000
+#define BF_ELCDIF_DVICTRL0_H_ACTIVE_CNT(v)  \
+		(((v) << 16) & BM_ELCDIF_DVICTRL0_H_ACTIVE_CNT)
+#define BP_ELCDIF_DVICTRL0_RSRVD0	12
+#define BM_ELCDIF_DVICTRL0_RSRVD0	0x0000F000
+#define BF_ELCDIF_DVICTRL0_RSRVD0(v)  \
+		(((v) << 12) & BM_ELCDIF_DVICTRL0_RSRVD0)
+#define BP_ELCDIF_DVICTRL0_H_BLANKING_CNT	0
+#define BM_ELCDIF_DVICTRL0_H_BLANKING_CNT	0x00000FFF
+#define BF_ELCDIF_DVICTRL0_H_BLANKING_CNT(v)  \
+		(((v) << 0) & BM_ELCDIF_DVICTRL0_H_BLANKING_CNT)
+
+#define HW_ELCDIF_DVICTRL1	(0x000000d0)
+
+#define BP_ELCDIF_DVICTRL1_RSRVD0	30
+#define BM_ELCDIF_DVICTRL1_RSRVD0	0xC0000000
+#define BF_ELCDIF_DVICTRL1_RSRVD0(v) \
+		(((v) << 30) & BM_ELCDIF_DVICTRL1_RSRVD0)
+#define BP_ELCDIF_DVICTRL1_F1_START_LINE	20
+#define BM_ELCDIF_DVICTRL1_F1_START_LINE	0x3FF00000
+#define BF_ELCDIF_DVICTRL1_F1_START_LINE(v)  \
+		(((v) << 20) & BM_ELCDIF_DVICTRL1_F1_START_LINE)
+#define BP_ELCDIF_DVICTRL1_F1_END_LINE	10
+#define BM_ELCDIF_DVICTRL1_F1_END_LINE	0x000FFC00
+#define BF_ELCDIF_DVICTRL1_F1_END_LINE(v)  \
+		(((v) << 10) & BM_ELCDIF_DVICTRL1_F1_END_LINE)
+#define BP_ELCDIF_DVICTRL1_F2_START_LINE	0
+#define BM_ELCDIF_DVICTRL1_F2_START_LINE	0x000003FF
+#define BF_ELCDIF_DVICTRL1_F2_START_LINE(v)  \
+		(((v) << 0) & BM_ELCDIF_DVICTRL1_F2_START_LINE)
+
+#define HW_ELCDIF_DVICTRL2	(0x000000e0)
+
+#define BP_ELCDIF_DVICTRL2_RSRVD0	30
+#define BM_ELCDIF_DVICTRL2_RSRVD0	0xC0000000
+#define BF_ELCDIF_DVICTRL2_RSRVD0(v) \
+		(((v) << 30) & BM_ELCDIF_DVICTRL2_RSRVD0)
+#define BP_ELCDIF_DVICTRL2_F2_END_LINE	20
+#define BM_ELCDIF_DVICTRL2_F2_END_LINE	0x3FF00000
+#define BF_ELCDIF_DVICTRL2_F2_END_LINE(v)  \
+		(((v) << 20) & BM_ELCDIF_DVICTRL2_F2_END_LINE)
+#define BP_ELCDIF_DVICTRL2_V1_BLANK_START_LINE	10
+#define BM_ELCDIF_DVICTRL2_V1_BLANK_START_LINE	0x000FFC00
+#define BF_ELCDIF_DVICTRL2_V1_BLANK_START_LINE(v)  \
+		(((v) << 10) & BM_ELCDIF_DVICTRL2_V1_BLANK_START_LINE)
+#define BP_ELCDIF_DVICTRL2_V1_BLANK_END_LINE	0
+#define BM_ELCDIF_DVICTRL2_V1_BLANK_END_LINE	0x000003FF
+#define BF_ELCDIF_DVICTRL2_V1_BLANK_END_LINE(v)  \
+		(((v) << 0) & BM_ELCDIF_DVICTRL2_V1_BLANK_END_LINE)
+
+#define HW_ELCDIF_DVICTRL3	(0x000000f0)
+
+#define BP_ELCDIF_DVICTRL3_RSRVD0	30
+#define BM_ELCDIF_DVICTRL3_RSRVD0	0xC0000000
+#define BF_ELCDIF_DVICTRL3_RSRVD0(v) \
+		(((v) << 30) & BM_ELCDIF_DVICTRL3_RSRVD0)
+#define BP_ELCDIF_DVICTRL3_V2_BLANK_START_LINE	20
+#define BM_ELCDIF_DVICTRL3_V2_BLANK_START_LINE	0x3FF00000
+#define BF_ELCDIF_DVICTRL3_V2_BLANK_START_LINE(v)  \
+		(((v) << 20) & BM_ELCDIF_DVICTRL3_V2_BLANK_START_LINE)
+#define BP_ELCDIF_DVICTRL3_V2_BLANK_END_LINE	10
+#define BM_ELCDIF_DVICTRL3_V2_BLANK_END_LINE	0x000FFC00
+#define BF_ELCDIF_DVICTRL3_V2_BLANK_END_LINE(v)  \
+		(((v) << 10) & BM_ELCDIF_DVICTRL3_V2_BLANK_END_LINE)
+#define BP_ELCDIF_DVICTRL3_V_LINES_CNT	0
+#define BM_ELCDIF_DVICTRL3_V_LINES_CNT	0x000003FF
+#define BF_ELCDIF_DVICTRL3_V_LINES_CNT(v)  \
+		(((v) << 0) & BM_ELCDIF_DVICTRL3_V_LINES_CNT)
+
+#define HW_ELCDIF_DVICTRL4	(0x00000100)
+
+#define BP_ELCDIF_DVICTRL4_Y_FILL_VALUE	24
+#define BM_ELCDIF_DVICTRL4_Y_FILL_VALUE	0xFF000000
+#define BF_ELCDIF_DVICTRL4_Y_FILL_VALUE(v) \
+		(((v) << 24) & BM_ELCDIF_DVICTRL4_Y_FILL_VALUE)
+#define BP_ELCDIF_DVICTRL4_CB_FILL_VALUE	16
+#define BM_ELCDIF_DVICTRL4_CB_FILL_VALUE	0x00FF0000
+#define BF_ELCDIF_DVICTRL4_CB_FILL_VALUE(v)  \
+		(((v) << 16) & BM_ELCDIF_DVICTRL4_CB_FILL_VALUE)
+#define BP_ELCDIF_DVICTRL4_CR_FILL_VALUE	8
+#define BM_ELCDIF_DVICTRL4_CR_FILL_VALUE	0x0000FF00
+#define BF_ELCDIF_DVICTRL4_CR_FILL_VALUE(v)  \
+		(((v) << 8) & BM_ELCDIF_DVICTRL4_CR_FILL_VALUE)
+#define BP_ELCDIF_DVICTRL4_H_FILL_CNT	0
+#define BM_ELCDIF_DVICTRL4_H_FILL_CNT	0x000000FF
+#define BF_ELCDIF_DVICTRL4_H_FILL_CNT(v)  \
+		(((v) << 0) & BM_ELCDIF_DVICTRL4_H_FILL_CNT)
+
+#define HW_ELCDIF_CSC_COEFF0	(0x00000110)
+
+#define BP_ELCDIF_CSC_COEFF0_RSRVD1	26
+#define BM_ELCDIF_CSC_COEFF0_RSRVD1	0xFC000000
+#define BF_ELCDIF_CSC_COEFF0_RSRVD1(v) \
+		(((v) << 26) & BM_ELCDIF_CSC_COEFF0_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF0_C0	16
+#define BM_ELCDIF_CSC_COEFF0_C0	0x03FF0000
+#define BF_ELCDIF_CSC_COEFF0_C0(v)  \
+		(((v) << 16) & BM_ELCDIF_CSC_COEFF0_C0)
+#define BP_ELCDIF_CSC_COEFF0_RSRVD0	2
+#define BM_ELCDIF_CSC_COEFF0_RSRVD0	0x0000FFFC
+#define BF_ELCDIF_CSC_COEFF0_RSRVD0(v)  \
+		(((v) << 2) & BM_ELCDIF_CSC_COEFF0_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER	0
+#define BM_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER	0x00000003
+#define BF_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v)  \
+		(((v) << 0) & BM_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER)
+#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD 0x0
+#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD           0x1
+#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL    0x2
+#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED         0x3
+
+#define HW_ELCDIF_CSC_COEFF1	(0x00000120)
+
+#define BP_ELCDIF_CSC_COEFF1_RSRVD1	26
+#define BM_ELCDIF_CSC_COEFF1_RSRVD1	0xFC000000
+#define BF_ELCDIF_CSC_COEFF1_RSRVD1(v) \
+		(((v) << 26) & BM_ELCDIF_CSC_COEFF1_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF1_C2	16
+#define BM_ELCDIF_CSC_COEFF1_C2	0x03FF0000
+#define BF_ELCDIF_CSC_COEFF1_C2(v)  \
+		(((v) << 16) & BM_ELCDIF_CSC_COEFF1_C2)
+#define BP_ELCDIF_CSC_COEFF1_RSRVD0	10
+#define BM_ELCDIF_CSC_COEFF1_RSRVD0	0x0000FC00
+#define BF_ELCDIF_CSC_COEFF1_RSRVD0(v)  \
+		(((v) << 10) & BM_ELCDIF_CSC_COEFF1_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF1_C1	0
+#define BM_ELCDIF_CSC_COEFF1_C1	0x000003FF
+#define BF_ELCDIF_CSC_COEFF1_C1(v)  \
+		(((v) << 0) & BM_ELCDIF_CSC_COEFF1_C1)
+
+#define HW_ELCDIF_CSC_COEFF2	(0x00000130)
+
+#define BP_ELCDIF_CSC_COEFF2_RSRVD1	26
+#define BM_ELCDIF_CSC_COEFF2_RSRVD1	0xFC000000
+#define BF_ELCDIF_CSC_COEFF2_RSRVD1(v) \
+		(((v) << 26) & BM_ELCDIF_CSC_COEFF2_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF2_C4	16
+#define BM_ELCDIF_CSC_COEFF2_C4	0x03FF0000
+#define BF_ELCDIF_CSC_COEFF2_C4(v)  \
+		(((v) << 16) & BM_ELCDIF_CSC_COEFF2_C4)
+#define BP_ELCDIF_CSC_COEFF2_RSRVD0	10
+#define BM_ELCDIF_CSC_COEFF2_RSRVD0	0x0000FC00
+#define BF_ELCDIF_CSC_COEFF2_RSRVD0(v)  \
+		(((v) << 10) & BM_ELCDIF_CSC_COEFF2_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF2_C3	0
+#define BM_ELCDIF_CSC_COEFF2_C3	0x000003FF
+#define BF_ELCDIF_CSC_COEFF2_C3(v)  \
+		(((v) << 0) & BM_ELCDIF_CSC_COEFF2_C3)
+
+#define HW_ELCDIF_CSC_COEFF3	(0x00000140)
+
+#define BP_ELCDIF_CSC_COEFF3_RSRVD1	26
+#define BM_ELCDIF_CSC_COEFF3_RSRVD1	0xFC000000
+#define BF_ELCDIF_CSC_COEFF3_RSRVD1(v) \
+		(((v) << 26) & BM_ELCDIF_CSC_COEFF3_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF3_C6	16
+#define BM_ELCDIF_CSC_COEFF3_C6	0x03FF0000
+#define BF_ELCDIF_CSC_COEFF3_C6(v)  \
+		(((v) << 16) & BM_ELCDIF_CSC_COEFF3_C6)
+#define BP_ELCDIF_CSC_COEFF3_RSRVD0	10
+#define BM_ELCDIF_CSC_COEFF3_RSRVD0	0x0000FC00
+#define BF_ELCDIF_CSC_COEFF3_RSRVD0(v)  \
+		(((v) << 10) & BM_ELCDIF_CSC_COEFF3_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF3_C5	0
+#define BM_ELCDIF_CSC_COEFF3_C5	0x000003FF
+#define BF_ELCDIF_CSC_COEFF3_C5(v)  \
+		(((v) << 0) & BM_ELCDIF_CSC_COEFF3_C5)
+
+#define HW_ELCDIF_CSC_COEFF4	(0x00000150)
+
+#define BP_ELCDIF_CSC_COEFF4_RSRVD1	26
+#define BM_ELCDIF_CSC_COEFF4_RSRVD1	0xFC000000
+#define BF_ELCDIF_CSC_COEFF4_RSRVD1(v) \
+		(((v) << 26) & BM_ELCDIF_CSC_COEFF4_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF4_C8	16
+#define BM_ELCDIF_CSC_COEFF4_C8	0x03FF0000
+#define BF_ELCDIF_CSC_COEFF4_C8(v)  \
+		(((v) << 16) & BM_ELCDIF_CSC_COEFF4_C8)
+#define BP_ELCDIF_CSC_COEFF4_RSRVD0	10
+#define BM_ELCDIF_CSC_COEFF4_RSRVD0	0x0000FC00
+#define BF_ELCDIF_CSC_COEFF4_RSRVD0(v)  \
+		(((v) << 10) & BM_ELCDIF_CSC_COEFF4_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF4_C7	0
+#define BM_ELCDIF_CSC_COEFF4_C7	0x000003FF
+#define BF_ELCDIF_CSC_COEFF4_C7(v)  \
+		(((v) << 0) & BM_ELCDIF_CSC_COEFF4_C7)
+
+#define HW_ELCDIF_CSC_OFFSET	(0x00000160)
+
+#define BP_ELCDIF_CSC_OFFSET_RSRVD1	25
+#define BM_ELCDIF_CSC_OFFSET_RSRVD1	0xFE000000
+#define BF_ELCDIF_CSC_OFFSET_RSRVD1(v) \
+		(((v) << 25) & BM_ELCDIF_CSC_OFFSET_RSRVD1)
+#define BP_ELCDIF_CSC_OFFSET_CBCR_OFFSET	16
+#define BM_ELCDIF_CSC_OFFSET_CBCR_OFFSET	0x01FF0000
+#define BF_ELCDIF_CSC_OFFSET_CBCR_OFFSET(v)  \
+		(((v) << 16) & BM_ELCDIF_CSC_OFFSET_CBCR_OFFSET)
+#define BP_ELCDIF_CSC_OFFSET_RSRVD0	9
+#define BM_ELCDIF_CSC_OFFSET_RSRVD0	0x0000FE00
+#define BF_ELCDIF_CSC_OFFSET_RSRVD0(v)  \
+		(((v) << 9) & BM_ELCDIF_CSC_OFFSET_RSRVD0)
+#define BP_ELCDIF_CSC_OFFSET_Y_OFFSET	0
+#define BM_ELCDIF_CSC_OFFSET_Y_OFFSET	0x000001FF
+#define BF_ELCDIF_CSC_OFFSET_Y_OFFSET(v)  \
+		(((v) << 0) & BM_ELCDIF_CSC_OFFSET_Y_OFFSET)
+
+#define HW_ELCDIF_CSC_LIMIT	(0x00000170)
+
+#define BP_ELCDIF_CSC_LIMIT_CBCR_MIN	24
+#define BM_ELCDIF_CSC_LIMIT_CBCR_MIN	0xFF000000
+#define BF_ELCDIF_CSC_LIMIT_CBCR_MIN(v) \
+		(((v) << 24) & BM_ELCDIF_CSC_LIMIT_CBCR_MIN)
+#define BP_ELCDIF_CSC_LIMIT_CBCR_MAX	16
+#define BM_ELCDIF_CSC_LIMIT_CBCR_MAX	0x00FF0000
+#define BF_ELCDIF_CSC_LIMIT_CBCR_MAX(v)  \
+		(((v) << 16) & BM_ELCDIF_CSC_LIMIT_CBCR_MAX)
+#define BP_ELCDIF_CSC_LIMIT_Y_MIN	8
+#define BM_ELCDIF_CSC_LIMIT_Y_MIN	0x0000FF00
+#define BF_ELCDIF_CSC_LIMIT_Y_MIN(v)  \
+		(((v) << 8) & BM_ELCDIF_CSC_LIMIT_Y_MIN)
+#define BP_ELCDIF_CSC_LIMIT_Y_MAX	0
+#define BM_ELCDIF_CSC_LIMIT_Y_MAX	0x000000FF
+#define BF_ELCDIF_CSC_LIMIT_Y_MAX(v)  \
+		(((v) << 0) & BM_ELCDIF_CSC_LIMIT_Y_MAX)
+
+#define HW_ELCDIF_DATA	(0x00000180)
+
+#define BP_ELCDIF_DATA_DATA_THREE	24
+#define BM_ELCDIF_DATA_DATA_THREE	0xFF000000
+#define BF_ELCDIF_DATA_DATA_THREE(v) \
+		(((v) << 24) & BM_ELCDIF_DATA_DATA_THREE)
+#define BP_ELCDIF_DATA_DATA_TWO	16
+#define BM_ELCDIF_DATA_DATA_TWO	0x00FF0000
+#define BF_ELCDIF_DATA_DATA_TWO(v)  \
+		(((v) << 16) & BM_ELCDIF_DATA_DATA_TWO)
+#define BP_ELCDIF_DATA_DATA_ONE	8
+#define BM_ELCDIF_DATA_DATA_ONE	0x0000FF00
+#define BF_ELCDIF_DATA_DATA_ONE(v)  \
+		(((v) << 8) & BM_ELCDIF_DATA_DATA_ONE)
+#define BP_ELCDIF_DATA_DATA_ZERO	0
+#define BM_ELCDIF_DATA_DATA_ZERO	0x000000FF
+#define BF_ELCDIF_DATA_DATA_ZERO(v)  \
+		(((v) << 0) & BM_ELCDIF_DATA_DATA_ZERO)
+
+#define HW_ELCDIF_BM_ERROR_STAT	(0x00000190)
+
+#define BP_ELCDIF_BM_ERROR_STAT_ADDR	0
+#define BM_ELCDIF_BM_ERROR_STAT_ADDR	0xFFFFFFFF
+#define BF_ELCDIF_BM_ERROR_STAT_ADDR(v)	(v)
+
+#define HW_ELCDIF_CRC_STAT	(0x000001a0)
+
+#define BP_ELCDIF_CRC_STAT_CRC_VALUE	0
+#define BM_ELCDIF_CRC_STAT_CRC_VALUE	0xFFFFFFFF
+#define BF_ELCDIF_CRC_STAT_CRC_VALUE(v)	(v)
+
+#define HW_ELCDIF_STAT	(0x000001b0)
+
+#define BM_ELCDIF_STAT_PRESENT	0x80000000
+#define BM_ELCDIF_STAT_DMA_REQ	0x40000000
+#define BM_ELCDIF_STAT_LFIFO_FULL	0x20000000
+#define BM_ELCDIF_STAT_LFIFO_EMPTY	0x10000000
+#define BM_ELCDIF_STAT_TXFIFO_FULL	0x08000000
+#define BM_ELCDIF_STAT_TXFIFO_EMPTY	0x04000000
+#define BM_ELCDIF_STAT_BUSY	0x02000000
+#define BM_ELCDIF_STAT_DVI_CURRENT_FIELD	0x01000000
+#define BP_ELCDIF_STAT_RSRVD0	9
+#define BM_ELCDIF_STAT_RSRVD0	0x00FFFE00
+#define BF_ELCDIF_STAT_RSRVD0(v)  \
+		(((v) << 9) & BM_ELCDIF_STAT_RSRVD0)
+#define BP_ELCDIF_STAT_LFIFO_COUNT	0
+#define BM_ELCDIF_STAT_LFIFO_COUNT	0x000001FF
+#define BF_ELCDIF_STAT_LFIFO_COUNT(v)  \
+		(((v) << 0) & BM_ELCDIF_STAT_LFIFO_COUNT)
+
+#define HW_ELCDIF_VERSION	(0x000001c0)
+
+#define BP_ELCDIF_VERSION_MAJOR	24
+#define BM_ELCDIF_VERSION_MAJOR	0xFF000000
+#define BF_ELCDIF_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_ELCDIF_VERSION_MAJOR)
+#define BP_ELCDIF_VERSION_MINOR	16
+#define BM_ELCDIF_VERSION_MINOR	0x00FF0000
+#define BF_ELCDIF_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_ELCDIF_VERSION_MINOR)
+#define BP_ELCDIF_VERSION_STEP	0
+#define BM_ELCDIF_VERSION_STEP	0x0000FFFF
+#define BF_ELCDIF_VERSION_STEP(v)  \
+		(((v) << 0) & BM_ELCDIF_VERSION_STEP)
+
+#define HW_ELCDIF_DEBUG0	(0x000001d0)
+
+#define BM_ELCDIF_DEBUG0_STREAMING_END_DETECTED	0x80000000
+#define BM_ELCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT	0x40000000
+#define BM_ELCDIF_DEBUG0_SYNC_SIGNALS_ON_REG	0x20000000
+#define BM_ELCDIF_DEBUG0_DMACMDKICK	0x10000000
+#define BM_ELCDIF_DEBUG0_ENABLE	0x08000000
+#define BM_ELCDIF_DEBUG0_HSYNC	0x04000000
+#define BM_ELCDIF_DEBUG0_VSYNC	0x02000000
+#define BM_ELCDIF_DEBUG0_CUR_FRAME_TX	0x01000000
+#define BM_ELCDIF_DEBUG0_EMPTY_WORD	0x00800000
+#define BP_ELCDIF_DEBUG0_CUR_STATE	16
+#define BM_ELCDIF_DEBUG0_CUR_STATE	0x007F0000
+#define BF_ELCDIF_DEBUG0_CUR_STATE(v)  \
+		(((v) << 16) & BM_ELCDIF_DEBUG0_CUR_STATE)
+#define BM_ELCDIF_DEBUG0_PXP_ELCDIF_B0_READY	0x00008000
+#define BM_ELCDIF_DEBUG0_ELCDIF_PXP_B0_DONE	0x00004000
+#define BM_ELCDIF_DEBUG0_PXP_ELCDIF_B1_READY	0x00002000
+#define BM_ELCDIF_DEBUG0_ELCDIF_PXP_B1_DONE	0x00001000
+#define BP_ELCDIF_DEBUG0_CUR_REQ_STATE	10
+#define BM_ELCDIF_DEBUG0_CUR_REQ_STATE	0x00000C00
+#define BF_ELCDIF_DEBUG0_CUR_REQ_STATE(v)  \
+		(((v) << 10) & BM_ELCDIF_DEBUG0_CUR_REQ_STATE)
+#define BM_ELCDIF_DEBUG0_MST_AVALID	0x00000200
+#define BP_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS	4
+#define BM_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS	0x000001F0
+#define BF_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS(v)  \
+		(((v) << 4) & BM_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS)
+#define BP_ELCDIF_DEBUG0_MST_WORDS	0
+#define BM_ELCDIF_DEBUG0_MST_WORDS	0x0000000F
+#define BF_ELCDIF_DEBUG0_MST_WORDS(v)  \
+		(((v) << 0) & BM_ELCDIF_DEBUG0_MST_WORDS)
+
+#define HW_ELCDIF_DEBUG1	(0x000001e0)
+
+#define BP_ELCDIF_DEBUG1_H_DATA_COUNT	16
+#define BM_ELCDIF_DEBUG1_H_DATA_COUNT	0xFFFF0000
+#define BF_ELCDIF_DEBUG1_H_DATA_COUNT(v) \
+		(((v) << 16) & BM_ELCDIF_DEBUG1_H_DATA_COUNT)
+#define BP_ELCDIF_DEBUG1_V_DATA_COUNT	0
+#define BM_ELCDIF_DEBUG1_V_DATA_COUNT	0x0000FFFF
+#define BF_ELCDIF_DEBUG1_V_DATA_COUNT(v)  \
+		(((v) << 0) & BM_ELCDIF_DEBUG1_V_DATA_COUNT)
+
+#define HW_ELCDIF_DEBUG2	(0x000001f0)
+
+#define BP_ELCDIF_DEBUG2_MST_ADDRESS	0
+#define BM_ELCDIF_DEBUG2_MST_ADDRESS	0xFFFFFFFF
+#define BF_ELCDIF_DEBUG2_MST_ADDRESS(v)	(v)
+#endif /* __ELCDIF_REGS_INCLUDED_ */
diff --git a/drivers/video/mxc/epdc_regs.h b/drivers/video/mxc/epdc_regs.h
new file mode 100644
index 000000000000..1d0635b928ad
--- /dev/null
+++ b/drivers/video/mxc/epdc_regs.h
@@ -0,0 +1,301 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+#ifndef __EPDC_REGS_INCLUDED__
+#define __EPDC_REGS_INCLUDED__
+
+extern void __iomem *epdc_base;
+
+//*************************************
+// Register addresses
+//*************************************
+
+#define EPDC_CTRL			(epdc_base + 0x000)
+#define EPDC_CTRL_SET			(epdc_base + 0x004)
+#define EPDC_CTRL_CLEAR		(epdc_base + 0x008)
+#define EPDC_CTRL_TOGGLE		(epdc_base + 0x00C)
+#define EPDC_WVADDR			(epdc_base + 0x020)
+#define EPDC_WB_ADDR			(epdc_base + 0x030)
+#define EPDC_RES			(epdc_base + 0x040)
+#define EPDC_FORMAT			(epdc_base + 0x050)
+#define EPDC_FORMAT_SET		(epdc_base + 0x054)
+#define EPDC_FORMAT_CLEAR		(epdc_base + 0x058)
+#define EPDC_FORMAT_TOGGLE		(epdc_base + 0x05C)
+#define EPDC_FIFOCTRL			(epdc_base + 0x0A0)
+#define EPDC_FIFOCTRL_SET		(epdc_base + 0x0A4)
+#define EPDC_FIFOCTRL_CLEAR		(epdc_base + 0x0A8)
+#define EPDC_FIFOCTRL_TOGGLE		(epdc_base + 0x0AC)
+#define EPDC_UPD_ADDR			(epdc_base + 0x100)
+#define EPDC_UPD_CORD			(epdc_base + 0x120)
+#define EPDC_UPD_SIZE			(epdc_base + 0x140)
+#define EPDC_UPD_CTRL			(epdc_base + 0x160)
+#define EPDC_UPD_FIXED			(epdc_base + 0x180)
+#define EPDC_TEMP			(epdc_base + 0x1A0)
+#define EPDC_TCE_CTRL			(epdc_base + 0x200)
+#define EPDC_TCE_SDCFG			(epdc_base + 0x220)
+#define EPDC_TCE_GDCFG			(epdc_base + 0x240)
+#define EPDC_TCE_HSCAN1		(epdc_base + 0x260)
+#define EPDC_TCE_HSCAN2		(epdc_base + 0x280)
+#define EPDC_TCE_VSCAN			(epdc_base + 0x2A0)
+#define EPDC_TCE_OE			(epdc_base + 0x2C0)
+#define EPDC_TCE_POLARITY		(epdc_base + 0x2E0)
+#define EPDC_TCE_TIMING1		(epdc_base + 0x300)
+#define EPDC_TCE_TIMING2		(epdc_base + 0x310)
+#define EPDC_TCE_TIMING3		(epdc_base + 0x320)
+#define EPDC_IRQ_MASK			(epdc_base + 0x400)
+#define EPDC_IRQ_MASK_SET		(epdc_base + 0x404)
+#define EPDC_IRQ_MASK_CLEAR		(epdc_base + 0x408)
+#define EPDC_IRQ_MASK_TOGGLE		(epdc_base + 0x40C)
+#define EPDC_IRQ			(epdc_base + 0x420)
+#define EPDC_IRQ_SET			(epdc_base + 0x424)
+#define EPDC_IRQ_CLEAR			(epdc_base + 0x428)
+#define EPDC_IRQ_TOGGLE		(epdc_base + 0x42C)
+#define EPDC_STATUS_LUTS		(epdc_base + 0x440)
+#define EPDC_STATUS_LUTS_SET	(epdc_base + 0x444)
+#define EPDC_STATUS_LUTS_CLEAR	(epdc_base + 0x448)
+#define EPDC_STATUS_LUTS_TOGGLE	(epdc_base + 0x44C)
+#define EPDC_STATUS_NEXTLUT		(epdc_base + 0x460)
+#define EPDC_STATUS_COL		(epdc_base + 0x480)
+#define EPDC_STATUS			(epdc_base + 0x4A0)
+#define EPDC_STATUS_SET		(epdc_base + 0x4A4)
+#define EPDC_STATUS_CLEAR		(epdc_base + 0x4A8)
+#define EPDC_STATUS_TOGGLE		(epdc_base + 0x4AC)
+#define EPDC_DEBUG			(epdc_base + 0x500)
+#define EPDC_DEBUG_LUT0		(epdc_base + 0x540)
+#define EPDC_DEBUG_LUT1		(epdc_base + 0x550)
+#define EPDC_DEBUG_LUT2		(epdc_base + 0x560)
+#define EPDC_DEBUG_LUT3		(epdc_base + 0x570)
+#define EPDC_DEBUG_LUT4		(epdc_base + 0x580)
+#define EPDC_DEBUG_LUT5		(epdc_base + 0x590)
+#define EPDC_DEBUG_LUT6		(epdc_base + 0x5A0)
+#define EPDC_DEBUG_LUT7		(epdc_base + 0x5B0)
+#define EPDC_DEBUG_LUT8		(epdc_base + 0x5C0)
+#define EPDC_DEBUG_LUT9		(epdc_base + 0x5D0)
+#define EPDC_DEBUG_LUT10		(epdc_base + 0x5E0)
+#define EPDC_DEBUG_LUT11		(epdc_base + 0x5F0)
+#define EPDC_DEBUG_LUT12		(epdc_base + 0x600)
+#define EPDC_DEBUG_LUT13		(epdc_base + 0x610)
+#define EPDC_DEBUG_LUT14		(epdc_base + 0x620)
+#define EPDC_DEBUG_LUT15		(epdc_base + 0x630)
+#define EPDC_GPIO			(epdc_base + 0x700)
+#define EPDC_VERSION			(epdc_base + 0x7F0)
+
+/*
+ * Register field definitions
+ */
+
+enum {
+/* EPDC_CTRL field values */
+	EPDC_CTRL_SFTRST = 0x80000000,
+	EPDC_CTRL_CLKGATE = 0x40000000,
+	EPDC_CTRL_SRAM_POWERDOWN = 0x100,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_MASK = 0xC0,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP = 0,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x40,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_SWAP = 0x80,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_BYTE_SWAP = 0xC0,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_MASK = 0x30,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP = 0,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x10,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_SWAP = 0x20,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_BYTE_SWAP = 0x30,
+	EPDC_CTRL_BURST_LEN_8_8 = 0x1,
+	EPDC_CTRL_BURST_LEN_8_16 = 0,
+
+/* EPDC_RES field values */
+	EPDC_RES_VERTICAL_MASK = 0x1FFF0000,
+	EPDC_RES_VERTICAL_OFFSET = 16,
+	EPDC_RES_HORIZONTAL_MASK = 0x1FFF,
+	EPDC_RES_HORIZONTAL_OFFSET = 0,
+
+/* EPDC_FORMAT field values */
+	EPDC_FORMAT_BUF_PIXEL_SCALE_ROUND = 0x1000000,
+	EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK = 0xFF0000,
+	EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET = 16,
+	EPDC_FORMAT_BUF_PIXEL_FORMAT_P2N = 0x200,
+	EPDC_FORMAT_BUF_PIXEL_FORMAT_P3N = 0x300,
+	EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N = 0x400,
+	EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N = 0x500,
+	EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT = 0x0,
+	EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT_VCOM = 0x1,
+	EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT = 0x2,
+	EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT_VCOM = 0x3,
+
+/* EPDC_FIFOCTRL field values */
+	EPDC_FIFOCTRL_ENABLE_PRIORITY = 0x80000000,
+	EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK = 0xFF0000,
+	EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET = 16,
+	EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK = 0xFF00,
+	EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET = 8,
+	EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK = 0xFF,
+	EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET = 0,
+
+/* EPDC_UPD_CORD field values */
+	EPDC_UPD_CORD_YCORD_MASK = 0x1FFF0000,
+	EPDC_UPD_CORD_YCORD_OFFSET = 16,
+	EPDC_UPD_CORD_XCORD_MASK = 0x1FFF,
+	EPDC_UPD_CORD_XCORD_OFFSET = 0,
+
+/* EPDC_UPD_SIZE field values */
+	EPDC_UPD_SIZE_HEIGHT_MASK = 0x1FFF0000,
+	EPDC_UPD_SIZE_HEIGHT_OFFSET = 16,
+	EPDC_UPD_SIZE_WIDTH_MASK = 0x1FFF,
+	EPDC_UPD_SIZE_WIDTH_OFFSET = 0,
+
+/* EPDC_UPD_CTRL field values */
+	EPDC_UPD_CTRL_USE_FIXED = 0x80000000,
+	EPDC_UPD_CTRL_LUT_SEL_MASK = 0xF0000,
+	EPDC_UPD_CTRL_LUT_SEL_OFFSET = 16,
+	EPDC_UPD_CTRL_WAVEFORM_MODE_MASK = 0xFF00,
+	EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET = 8,
+	EPDC_UPD_CTRL_UPDATE_MODE_FULL = 0x1,
+
+/* EPDC_UPD_FIXED field values */
+	EPDC_UPD_FIXED_FIXNP_EN = 0x80000000,
+	EPDC_UPD_FIXED_FIXCP_EN = 0x40000000,
+	EPDC_UPD_FIXED_FIXNP_MASK = 0xFF00,
+	EPDC_UPD_FIXED_FIXNP_OFFSET = 8,
+	EPDC_UPD_FIXED_FIXCP_MASK = 0xFF,
+	EPDC_UPD_FIXED_FIXCP_OFFSET = 0,
+
+/* EPDC_TCE_CTRL field values */
+	EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK = 0x1FF0000,
+	EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET = 16,
+	EPDC_TCE_CTRL_VCOM_VAL_MASK = 0xC00,
+	EPDC_TCE_CTRL_VCOM_VAL_OFFSET = 10,
+	EPDC_TCE_CTRL_VCOM_MODE_AUTO = 0x200,
+	EPDC_TCE_CTRL_VCOM_MODE_MANUAL = 0x000,
+	EPDC_TCE_CTRL_DDR_MODE_ENABLE = 0x100,
+	EPDC_TCE_CTRL_LVDS_MODE_CE_ENABLE = 0x80,
+	EPDC_TCE_CTRL_LVDS_MODE_ENABLE = 0x40,
+	EPDC_TCE_CTRL_SCAN_DIR_1_UP = 0x20,
+	EPDC_TCE_CTRL_SCAN_DIR_0_UP = 0x10,
+	EPDC_TCE_CTRL_DUAL_SCAN_ENABLE = 0x8,
+	EPDC_TCE_CTRL_SDDO_WIDTH_16BIT = 0x4,
+	EPDC_TCE_CTRL_PIXELS_PER_SDCLK_2 = 1,
+	EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4 = 2,
+	EPDC_TCE_CTRL_PIXELS_PER_SDCLK_8 = 3,
+
+/* EPDC_TCE_SDCFG field values */
+	EPDC_TCE_SDCFG_SDCLK_HOLD = 0x200000,
+	EPDC_TCE_SDCFG_SDSHR = 0x100000,
+	EPDC_TCE_SDCFG_NUM_CE_MASK = 0xF0000,
+	EPDC_TCE_SDCFG_NUM_CE_OFFSET = 16,
+	EPDC_TCE_SDCFG_SDDO_REFORMAT_STANDARD = 0,
+	EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS = 0x4000,
+	EPDC_TCE_SDCFG_SDDO_INVERT_ENABLE = 0x2000,
+	EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK = 0x1FFF,
+	EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET = 0,
+
+/* EPDC_TCE_GDCFG field values */
+	EPDC_TCE_SDCFG_GDRL = 0x10,
+	EPDC_TCE_SDCFG_GDOE_MODE_DELAYED_GDCLK = 0x2,
+	EPDC_TCE_SDCFG_GDSP_MODE_FRAME_SYNC = 0x1,
+	EPDC_TCE_SDCFG_GDSP_MODE_ONE_LINE = 0x0,
+
+/* EPDC_TCE_HSCAN1 field values */
+	EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK = 0xFFF0000,
+	EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET = 16,
+	EPDC_TCE_HSCAN1_LINE_SYNC_MASK = 0xFFF,
+	EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET = 0,
+
+/* EPDC_TCE_HSCAN2 field values */
+	EPDC_TCE_HSCAN2_LINE_END_MASK = 0xFFF0000,
+	EPDC_TCE_HSCAN2_LINE_END_OFFSET = 16,
+	EPDC_TCE_HSCAN2_LINE_BEGIN_MASK = 0xFFF,
+	EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET = 0,
+
+/* EPDC_TCE_VSCAN field values */
+	EPDC_TCE_VSCAN_FRAME_END_MASK = 0xFF0000,
+	EPDC_TCE_VSCAN_FRAME_END_OFFSET = 16,
+	EPDC_TCE_VSCAN_FRAME_BEGIN_MASK = 0xFF00,
+	EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET = 8,
+	EPDC_TCE_VSCAN_FRAME_SYNC_MASK = 0xFF,
+	EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET = 0,
+
+/* EPDC_TCE_OE field values */
+	EPDC_TCE_OE_SDOED_WIDTH_MASK = 0xFF000000,
+	EPDC_TCE_OE_SDOED_WIDTH_OFFSET = 24,
+	EPDC_TCE_OE_SDOED_DLY_MASK = 0xFF0000,
+	EPDC_TCE_OE_SDOED_DLY_OFFSET = 16,
+	EPDC_TCE_OE_SDOEZ_WIDTH_MASK = 0xFF00,
+	EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET = 8,
+	EPDC_TCE_OE_SDOEZ_DLY_MASK = 0xFF,
+	EPDC_TCE_OE_SDOEZ_DLY_OFFSET = 0,
+
+/* EPDC_TCE_POLARITY field values */
+	EPDC_TCE_POLARITY_GDSP_POL_ACTIVE_HIGH = 0x10,
+	EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH = 0x8,
+	EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH = 0x4,
+	EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH = 0x2,
+	EPDC_TCE_POLARITY_SDCE_POL_ACTIVE_HIGH = 0x1,
+
+/* EPDC_TCE_TIMING1 field values */
+	EPDC_TCE_TIMING1_SDLE_SHIFT_NONE = 0x00,
+	EPDC_TCE_TIMING1_SDLE_SHIFT_1 = 0x10,
+	EPDC_TCE_TIMING1_SDLE_SHIFT_2 = 0x20,
+	EPDC_TCE_TIMING1_SDLE_SHIFT_3 = 0x30,
+	EPDC_TCE_TIMING1_SDCLK_INVERT = 0x8,
+	EPDC_TCE_TIMING1_SDCLK_SHIFT_NONE = 0,
+	EPDC_TCE_TIMING1_SDCLK_SHIFT_1CYCLE = 1,
+	EPDC_TCE_TIMING1_SDCLK_SHIFT_2CYCLES = 2,
+	EPDC_TCE_TIMING1_SDCLK_SHIFT_3CYCLES = 3,
+
+/* EPDC_TCE_TIMING2 field values */
+	EPDC_TCE_TIMING2_GDCLK_HP_MASK = 0xFFFF0000,
+	EPDC_TCE_TIMING2_GDCLK_HP_OFFSET = 16,
+	EPDC_TCE_TIMING2_GDSP_OFFSET_MASK = 0xFFFF,
+	EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET = 0,
+
+/* EPDC_TCE_TIMING3 field values */
+	EPDC_TCE_TIMING3_GDOE_OFFSET_MASK = 0xFFFF0000,
+	EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET = 16,
+	EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK = 0xFFFF,
+	EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET = 0,
+
+/* EPDC_IRQ_MASK/EPDC_IRQ field values */
+	EPDC_IRQ_WB_CMPLT_IRQ = 0x10000,
+	EPDC_IRQ_LUT_COL_IRQ = 0x20000,
+	EPDC_IRQ_TCE_UNDERRUN_IRQ = 0x40000,
+	EPDC_IRQ_FRAME_END_IRQ = 0x80000,
+	EPDC_IRQ_BUS_ERROR_IRQ = 0x100000,
+	EPDC_IRQ_TCE_IDLE_IRQ = 0x200000,
+
+/* EPDC_STATUS_NEXTLUT field values */
+	EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID = 0x100,
+	EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0xF,
+	EPDC_STATUS_NEXTLUT_NEXT_LUT_OFFSET = 0,
+
+/* EPDC_STATUS field values */
+	EPDC_STATUS_LUTS_UNDERRUN = 0x4,
+	EPDC_STATUS_LUTS_BUSY = 0x2,
+	EPDC_STATUS_WB_BUSY = 0x1,
+
+/* EPDC_DEBUG field values */
+	EPDC_DEBUG_UNDERRUN_RECOVER = 0x2,
+	EPDC_DEBUG_COLLISION_OFF = 0x1,
+
+/* EPDC_GPIO field values */
+	EPDC_GPIO_PWRCOM = 0x40,
+	EPDC_GPIO_PWRCTRL_MASK = 0x3C,
+	EPDC_GPIO_PWRCTRL_OFFSET = 2,
+	EPDC_GPIO_BDR_MASK = 0x3,
+	EPDC_GPIO_BDR_OFFSET = 0,
+};
+
+#endif	/* __EPDC_REGS_INCLUDED__ */
diff --git a/drivers/video/mxc/ldb.c b/drivers/video/mxc/ldb.c
new file mode 100644
index 000000000000..fe58146df3cb
--- /dev/null
+++ b/drivers/video/mxc/ldb.c
@@ -0,0 +1,1448 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*!
+ * @file mxc_ldb.c
+ *
+ * @brief This file contains the LDB driver device interface and fops
+ * functions.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+#include <linux/ldb.h>
+#include <linux/mxcfb.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
+#include <mach/hardware.h>
+
+#define LDB_BGREF_RMODE_MASK		0x00008000
+#define LDB_BGREF_RMODE_INT		0x00008000
+#define LDB_BGREF_RMODE_EXT		0x0
+
+#define LDB_DI1_VS_POL_MASK		0x00000400
+#define LDB_DI1_VS_POL_ACT_LOW		0x00000400
+#define LDB_DI1_VS_POL_ACT_HIGH		0x0
+#define LDB_DI0_VS_POL_MASK		0x00000200
+#define LDB_DI0_VS_POL_ACT_LOW		0x00000200
+#define LDB_DI0_VS_POL_ACT_HIGH		0x0
+
+#define LDB_BIT_MAP_CH1_MASK		0x00000100
+#define LDB_BIT_MAP_CH1_JEIDA		0x00000100
+#define LDB_BIT_MAP_CH1_SPWG		0x0
+#define LDB_BIT_MAP_CH0_MASK		0x00000040
+#define LDB_BIT_MAP_CH0_JEIDA		0x00000040
+#define LDB_BIT_MAP_CH0_SPWG		0x0
+
+#define LDB_DATA_WIDTH_CH1_MASK		0x00000080
+#define LDB_DATA_WIDTH_CH1_24		0x00000080
+#define LDB_DATA_WIDTH_CH1_18		0x0
+#define LDB_DATA_WIDTH_CH0_MASK		0x00000020
+#define LDB_DATA_WIDTH_CH0_24		0x00000020
+#define LDB_DATA_WIDTH_CH0_18		0x0
+
+#define LDB_CH1_MODE_MASK		0x0000000C
+#define LDB_CH1_MODE_EN_TO_DI1		0x0000000C
+#define LDB_CH1_MODE_EN_TO_DI0		0x00000004
+#define LDB_CH1_MODE_DISABLE		0x0
+#define LDB_CH0_MODE_MASK		0x00000003
+#define LDB_CH0_MODE_EN_TO_DI1		0x00000003
+#define LDB_CH0_MODE_EN_TO_DI0		0x00000001
+#define LDB_CH0_MODE_DISABLE		0x0
+
+#define LDB_SPLIT_MODE_EN		0x00000010
+
+enum ldb_chan_mode_opt {
+	LDB_SIN_DI0 = 0,
+	LDB_SIN_DI1 = 1,
+	LDB_SEP = 2,
+	LDB_DUL_DI0 = 3,
+	LDB_DUL_DI1 = 4,
+	LDB_SPL_DI0 = 5,
+	LDB_SPL_DI1 = 6,
+};
+
+static struct ldb_data {
+	struct fb_info *fbi[2];
+	bool ch_working[2];
+	uint32_t chan_mode_opt;
+	uint32_t chan_bit_map[2];
+	uint32_t bgref_rmode;
+	uint32_t base_addr;
+	uint32_t *control_reg;
+	struct clk *ldb_di_clk[2];
+	struct regulator *lvds_bg_reg;
+	struct list_head modelist;
+} ldb;
+
+static struct device *g_ldb_dev;
+static u32 *ldb_reg;
+static bool enabled[2];
+static int g_chan_mode_opt;
+static int g_chan_bit_map[2];
+static bool g_enable_ldb;
+static bool g_boot_cmd;
+
+DEFINE_SPINLOCK(ldb_lock);
+
+struct fb_videomode mxcfb_ldb_modedb[] = {
+	{
+	 "1080P60", 60, 1920, 1080, 7692,
+	 100, 40,
+	 30, 3,
+	 10, 2,
+	 FB_SYNC_EXT,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+	{
+	 "XGA", 60, 1024, 768, 15385,
+	 220, 40,
+	 21, 7,
+	 60, 10,
+	 FB_SYNC_EXT,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+};
+int mxcfb_ldb_modedb_sz = ARRAY_SIZE(mxcfb_ldb_modedb);
+
+static int bits_per_pixel(int pixel_fmt)
+{
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+		return 24;
+		break;
+	case IPU_PIX_FMT_BGR666:
+	case IPU_PIX_FMT_RGB666:
+	case IPU_PIX_FMT_LVDS666:
+		return 18;
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int valid_mode(int pixel_fmt)
+{
+	return ((pixel_fmt == IPU_PIX_FMT_RGB24) ||
+		(pixel_fmt == IPU_PIX_FMT_BGR24) ||
+		(pixel_fmt == IPU_PIX_FMT_LVDS666) ||
+		(pixel_fmt == IPU_PIX_FMT_RGB666) ||
+		(pixel_fmt == IPU_PIX_FMT_BGR666));
+}
+
+static void ldb_disable(int ipu_di)
+{
+	uint32_t reg;
+	int i = 0;
+
+	spin_lock(&ldb_lock);
+
+	switch (ldb.chan_mode_opt) {
+	case LDB_SIN_DI0:
+		if (ipu_di != 0 || !ldb.ch_working[0] || !enabled[0]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		reg = __raw_readl(ldb.control_reg);
+		__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+			     LDB_CH0_MODE_DISABLE,
+			     ldb.control_reg);
+
+		ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+		clk_disable(ldb.ldb_di_clk[0]);
+		clk_put(ldb.ldb_di_clk[0]);
+
+		ldb.ch_working[0] = false;
+		enabled[0] = false;
+		break;
+	case LDB_SIN_DI1:
+		if (ipu_di != 1 || !ldb.ch_working[1] || !enabled[1]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		reg = __raw_readl(ldb.control_reg);
+		__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+			     LDB_CH1_MODE_DISABLE,
+			     ldb.control_reg);
+
+		ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+		clk_disable(ldb.ldb_di_clk[1]);
+		clk_put(ldb.ldb_di_clk[1]);
+
+		ldb.ch_working[1] = false;
+		enabled[1] = false;
+		break;
+	case LDB_SPL_DI0:
+	case LDB_DUL_DI0:
+		if (ipu_di != 0 || !enabled[0]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		for (i = 0; i < 2; i++) {
+			if (ldb.ch_working[i]) {
+				reg = __raw_readl(ldb.control_reg);
+				if (i == 0)
+					__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+						     LDB_CH0_MODE_DISABLE,
+						     ldb.control_reg);
+				else
+					__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+						     LDB_CH1_MODE_DISABLE,
+						     ldb.control_reg);
+
+				if (ldb.chan_mode_opt == LDB_SPL_DI0) {
+					reg = __raw_readl(ldb.control_reg);
+					__raw_writel(reg & ~LDB_SPLIT_MODE_EN,
+						     ldb.control_reg);
+				}
+
+				ldb.ldb_di_clk[i] = clk_get(NULL, i ?
+							"ldb_di1_clk" :
+							"ldb_di0_clk");
+				clk_disable(ldb.ldb_di_clk[i]);
+				clk_put(ldb.ldb_di_clk[i]);
+
+				ldb.ch_working[i] = false;
+			}
+		}
+		enabled[0] = false;
+		break;
+	case LDB_SPL_DI1:
+	case LDB_DUL_DI1:
+		if (ipu_di != 1 || !enabled[1]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		for (i = 0; i < 2; i++) {
+			if (ldb.ch_working[i]) {
+				reg = __raw_readl(ldb.control_reg);
+				if (i == 0)
+					__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+						     LDB_CH0_MODE_DISABLE,
+						     ldb.control_reg);
+				else
+					__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+						     LDB_CH1_MODE_DISABLE,
+						     ldb.control_reg);
+
+				if (ldb.chan_mode_opt == LDB_SPL_DI1) {
+					reg = __raw_readl(ldb.control_reg);
+					__raw_writel(reg & ~LDB_SPLIT_MODE_EN,
+						     ldb.control_reg);
+				}
+
+				ldb.ldb_di_clk[i] = clk_get(NULL, i ?
+							"ldb_di1_clk" :
+							"ldb_di0_clk");
+				clk_disable(ldb.ldb_di_clk[i]);
+				clk_put(ldb.ldb_di_clk[i]);
+
+				ldb.ch_working[i] = false;
+			}
+		}
+		enabled[1] = false;
+		break;
+	case LDB_SEP:
+		if (ldb.ch_working[ipu_di] && enabled[ipu_di]) {
+			reg = __raw_readl(ldb.control_reg);
+			if (ipu_di == 0)
+				__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+					     LDB_CH0_MODE_DISABLE,
+					     ldb.control_reg);
+			else
+				__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+					     LDB_CH1_MODE_DISABLE,
+					     ldb.control_reg);
+
+			ldb.ldb_di_clk[ipu_di] = clk_get(NULL, ipu_di ?
+							       "ldb_di1_clk" :
+							       "ldb_di0_clk");
+			clk_disable(ldb.ldb_di_clk[ipu_di]);
+			clk_put(ldb.ldb_di_clk[ipu_di]);
+
+			ldb.ch_working[ipu_di] = false;
+			enabled[ipu_di] = false;
+		}
+		break;
+	default:
+		break;
+	}
+
+	spin_unlock(&ldb_lock);
+	return;
+}
+
+static void ldb_enable(int ipu_di)
+{
+	uint32_t reg;
+
+	spin_lock(&ldb_lock);
+
+	reg = __raw_readl(ldb.control_reg);
+	switch (ldb.chan_mode_opt) {
+	case LDB_SIN_DI0:
+		if (ldb.ch_working[0] || ipu_di != 0 || enabled[0]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+		clk_enable(ldb.ldb_di_clk[0]);
+		clk_put(ldb.ldb_di_clk[0]);
+		__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+			      LDB_CH0_MODE_EN_TO_DI0, ldb.control_reg);
+		ldb.ch_working[0] = true;
+		enabled[0] = true;
+		break;
+	case LDB_SIN_DI1:
+		if (ldb.ch_working[1] || ipu_di != 1 || enabled[1]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+		clk_enable(ldb.ldb_di_clk[1]);
+		clk_put(ldb.ldb_di_clk[1]);
+		__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+			      LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg);
+		ldb.ch_working[1] = true;
+		enabled[1] = true;
+		break;
+	case LDB_SEP:
+		if (ldb.ch_working[ipu_di] || enabled[ipu_di]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		if (ipu_di == 0) {
+			ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+			clk_enable(ldb.ldb_di_clk[0]);
+			clk_put(ldb.ldb_di_clk[0]);
+			__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+				      LDB_CH0_MODE_EN_TO_DI0,
+				      ldb.control_reg);
+			ldb.ch_working[0] = true;
+		} else {
+			ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+			clk_enable(ldb.ldb_di_clk[1]);
+			clk_put(ldb.ldb_di_clk[1]);
+			__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+				      LDB_CH1_MODE_EN_TO_DI1,
+				      ldb.control_reg);
+			ldb.ch_working[1] = true;
+		}
+		enabled[ipu_di] = true;
+		break;
+	case LDB_DUL_DI0:
+	case LDB_SPL_DI0:
+		if (ipu_di != 0 || enabled[0])
+			return;
+		else
+			goto proc;
+	case LDB_DUL_DI1:
+	case LDB_SPL_DI1:
+		if (ipu_di != 1 || enabled[1])
+			return;
+proc:
+		if (ldb.ch_working[0] || ldb.ch_working[1]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+		ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+		clk_enable(ldb.ldb_di_clk[0]);
+		clk_enable(ldb.ldb_di_clk[1]);
+		clk_put(ldb.ldb_di_clk[0]);
+		clk_put(ldb.ldb_di_clk[1]);
+
+		if (ldb.chan_mode_opt == LDB_DUL_DI0 ||
+		    ldb.chan_mode_opt == LDB_SPL_DI0) {
+			__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+				      LDB_CH0_MODE_EN_TO_DI0,
+				      ldb.control_reg);
+			reg = __raw_readl(ldb.control_reg);
+			__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+				      LDB_CH1_MODE_EN_TO_DI0,
+				      ldb.control_reg);
+		} else if (ldb.chan_mode_opt == LDB_DUL_DI1 ||
+			   ldb.chan_mode_opt == LDB_SPL_DI1) {
+			__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+				      LDB_CH0_MODE_EN_TO_DI1,
+				      ldb.control_reg);
+			reg = __raw_readl(ldb.control_reg);
+			__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+				      LDB_CH1_MODE_EN_TO_DI1,
+				      ldb.control_reg);
+		}
+		if (ldb.chan_mode_opt == LDB_SPL_DI0 ||
+		    ldb.chan_mode_opt == LDB_SPL_DI1) {
+			reg = __raw_readl(ldb.control_reg);
+			__raw_writel(reg | LDB_SPLIT_MODE_EN,
+				      ldb.control_reg);
+		}
+		ldb.ch_working[0] = true;
+		ldb.ch_working[1] = true;
+		enabled[ipu_di] = true;
+		break;
+	default:
+		break;
+	}
+	spin_unlock(&ldb_lock);
+	return;
+}
+
+int ldb_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+	struct fb_event *event = v;
+	struct fb_info *fbi = event->info;
+	mm_segment_t old_fs;
+	int ipu_di = 0;
+
+	switch (val) {
+	case FB_EVENT_BLANK:
+		if (ldb.fbi[0] != fbi && ldb.fbi[1] != fbi)
+			return 0;
+
+		if (fbi->fbops->fb_ioctl) {
+			old_fs = get_fs();
+			set_fs(KERNEL_DS);
+			fbi->fbops->fb_ioctl(fbi,
+					MXCFB_GET_FB_IPU_DI,
+					(unsigned long)&ipu_di);
+			set_fs(old_fs);
+		} else
+			return 0;
+
+		if (*((int *)event->data) == FB_BLANK_UNBLANK)
+			ldb_enable(ipu_di);
+		else
+			ldb_disable(ipu_di);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static struct notifier_block nb = {
+	.notifier_call = ldb_fb_event,
+};
+
+static int mxc_ldb_ioctl(struct inode *inode, struct file *file,
+		unsigned int cmd, unsigned long arg)
+{
+	int ret = 0;
+	uint32_t reg;
+
+	switch (cmd) {
+	case LDB_BGREF_RMODE:
+		{
+		ldb_bgref_parm parm;
+
+		if (copy_from_user(&parm, (ldb_bgref_parm *) arg,
+				   sizeof(ldb_bgref_parm)))
+			return -EFAULT;
+
+		spin_lock(&ldb_lock);
+		reg = __raw_readl(ldb.control_reg);
+		if (parm.bgref_mode == LDB_EXT_REF)
+			__raw_writel((reg & ~LDB_BGREF_RMODE_MASK) |
+				      LDB_BGREF_RMODE_EXT, ldb.control_reg);
+		else if (parm.bgref_mode == LDB_INT_REF)
+			__raw_writel((reg & ~LDB_BGREF_RMODE_MASK) |
+				      LDB_BGREF_RMODE_INT, ldb.control_reg);
+		spin_unlock(&ldb_lock);
+		break;
+		}
+	case LDB_VSYNC_POL:
+		{
+		ldb_vsync_parm parm;
+
+		if (copy_from_user(&parm, (ldb_vsync_parm *) arg,
+				   sizeof(ldb_vsync_parm)))
+			return -EFAULT;
+
+		spin_lock(&ldb_lock);
+		reg = __raw_readl(ldb.control_reg);
+		if (parm.vsync_mode == LDB_VS_ACT_H) {
+			if (parm.di == 0)
+				__raw_writel((reg &
+					~LDB_DI0_VS_POL_MASK) |
+					LDB_DI0_VS_POL_ACT_HIGH,
+					ldb.control_reg);
+			else
+				__raw_writel((reg &
+					~LDB_DI1_VS_POL_MASK) |
+					LDB_DI1_VS_POL_ACT_HIGH,
+					ldb.control_reg);
+		} else if (parm.vsync_mode == LDB_VS_ACT_L) {
+			if (parm.di == 0)
+				__raw_writel((reg &
+					~LDB_DI0_VS_POL_MASK) |
+					LDB_DI0_VS_POL_ACT_LOW,
+					ldb.control_reg);
+			else
+				__raw_writel((reg &
+					~LDB_DI1_VS_POL_MASK) |
+					LDB_DI1_VS_POL_ACT_LOW,
+					ldb.control_reg);
+
+		}
+		spin_unlock(&ldb_lock);
+		break;
+		}
+	case LDB_BIT_MAP:
+		{
+		ldb_bitmap_parm parm;
+
+		if (copy_from_user(&parm, (ldb_bitmap_parm *) arg,
+				   sizeof(ldb_bitmap_parm)))
+			return -EFAULT;
+
+		spin_lock(&ldb_lock);
+		reg = __raw_readl(ldb.control_reg);
+		if (parm.bitmap_mode == LDB_BIT_MAP_SPWG) {
+			if (parm.channel == 0)
+				__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+					      LDB_BIT_MAP_CH0_SPWG,
+					      ldb.control_reg);
+			else
+				__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+					      LDB_BIT_MAP_CH1_SPWG,
+					      ldb.control_reg);
+		} else if (parm.bitmap_mode == LDB_BIT_MAP_JEIDA) {
+			if (parm.channel == 0)
+				__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+					      LDB_BIT_MAP_CH0_JEIDA,
+					      ldb.control_reg);
+			else
+				__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+					      LDB_BIT_MAP_CH1_JEIDA,
+					      ldb.control_reg);
+		}
+		spin_unlock(&ldb_lock);
+		break;
+		}
+	case LDB_DATA_WIDTH:
+		{
+		ldb_data_width_parm parm;
+
+		if (copy_from_user(&parm, (ldb_data_width_parm *) arg,
+				   sizeof(ldb_data_width_parm)))
+			return -EFAULT;
+
+		spin_lock(&ldb_lock);
+		reg = __raw_readl(ldb.control_reg);
+		if (parm.data_width == 24) {
+			if (parm.channel == 0)
+				__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+					      LDB_DATA_WIDTH_CH0_24,
+					      ldb.control_reg);
+			else
+				__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+					      LDB_DATA_WIDTH_CH1_24,
+					      ldb.control_reg);
+		} else if (parm.data_width == 18) {
+			if (parm.channel == 0)
+				__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+					      LDB_DATA_WIDTH_CH0_18,
+					      ldb.control_reg);
+			else
+				__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+					      LDB_DATA_WIDTH_CH1_18,
+					      ldb.control_reg);
+		}
+		spin_unlock(&ldb_lock);
+		break;
+		}
+	case LDB_CHAN_MODE:
+		{
+		ldb_chan_mode_parm parm;
+		struct clk *pll4_clk;
+		unsigned long pll4_rate = 0;
+
+		if (copy_from_user(&parm, (ldb_chan_mode_parm *) arg,
+				   sizeof(ldb_chan_mode_parm)))
+			return -EFAULT;
+
+		spin_lock(&ldb_lock);
+
+		/* TODO:Set the correct pll4 rate for all situations */
+		pll4_clk = clk_get(NULL, "pll4");
+		pll4_rate = clk_get_rate(pll4_clk);
+		pll4_rate = 455000000;
+		clk_set_rate(pll4_clk, pll4_rate);
+		clk_put(pll4_clk);
+
+		reg = __raw_readl(ldb.control_reg);
+		switch (parm.channel_mode) {
+		case LDB_CHAN_MODE_SIN:
+			if (parm.di == 0) {
+				ldb.chan_mode_opt = LDB_SIN_DI0;
+
+				ldb.ldb_di_clk[0] = clk_get(NULL,
+							    "ldb_di0_clk");
+				clk_set_rate(ldb.ldb_di_clk[0], pll4_rate/7);
+				clk_put(ldb.ldb_di_clk[0]);
+
+				__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+					      LDB_CH0_MODE_EN_TO_DI0,
+					      ldb.control_reg);
+			} else {
+				ldb.chan_mode_opt = LDB_SIN_DI1;
+
+				ldb.ldb_di_clk[1] = clk_get(NULL,
+							    "ldb_di1_clk");
+				clk_set_rate(ldb.ldb_di_clk[1], pll4_rate/7);
+				clk_put(ldb.ldb_di_clk[1]);
+
+				__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+					      LDB_CH1_MODE_EN_TO_DI1,
+					      ldb.control_reg);
+			}
+			break;
+		case LDB_CHAN_MODE_SEP:
+			ldb.chan_mode_opt = LDB_SEP;
+
+			ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+			clk_set_rate(ldb.ldb_di_clk[0], pll4_rate/7);
+			clk_put(ldb.ldb_di_clk[0]);
+			ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+			clk_set_rate(ldb.ldb_di_clk[1], pll4_rate/7);
+			clk_put(ldb.ldb_di_clk[1]);
+
+			__raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+					      LDB_CH1_MODE_MASK)) |
+				      LDB_CH0_MODE_EN_TO_DI0 |
+				      LDB_CH1_MODE_EN_TO_DI1,
+				      ldb.control_reg);
+			break;
+		case LDB_CHAN_MODE_DUL:
+		case LDB_CHAN_MODE_SPL:
+			ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+			ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+			if (parm.di == 0) {
+				if (parm.channel_mode == LDB_CHAN_MODE_DUL) {
+					ldb.chan_mode_opt = LDB_DUL_DI0;
+					clk_set_rate(ldb.ldb_di_clk[0],
+						     pll4_rate/7);
+				} else {
+					ldb.chan_mode_opt = LDB_SPL_DI0;
+					clk_set_rate(ldb.ldb_di_clk[0],
+						     2*pll4_rate/7);
+					clk_set_rate(ldb.ldb_di_clk[1],
+						     2*pll4_rate/7);
+					reg = __raw_readl(ldb.control_reg);
+					__raw_writel(reg | LDB_SPLIT_MODE_EN,
+						      ldb.control_reg);
+				}
+
+				reg = __raw_readl(ldb.control_reg);
+				__raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+						      LDB_CH1_MODE_MASK)) |
+					      LDB_CH0_MODE_EN_TO_DI0 |
+					      LDB_CH1_MODE_EN_TO_DI0,
+					      ldb.control_reg);
+			} else {
+				if (parm.channel_mode == LDB_CHAN_MODE_DUL) {
+					ldb.chan_mode_opt = LDB_DUL_DI1;
+					clk_set_rate(ldb.ldb_di_clk[1],
+						     pll4_rate/7);
+				} else {
+					ldb.chan_mode_opt = LDB_SPL_DI1;
+					clk_set_rate(ldb.ldb_di_clk[0],
+						     2*pll4_rate/7);
+					clk_set_rate(ldb.ldb_di_clk[1],
+						     2*pll4_rate/7);
+					reg = __raw_readl(ldb.control_reg);
+					__raw_writel(reg | LDB_SPLIT_MODE_EN,
+						      ldb.control_reg);
+				}
+
+				reg = __raw_readl(ldb.control_reg);
+				__raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+						      LDB_CH1_MODE_MASK)) |
+					      LDB_CH0_MODE_EN_TO_DI1 |
+					      LDB_CH1_MODE_EN_TO_DI1,
+					      ldb.control_reg);
+			}
+			clk_put(ldb.ldb_di_clk[0]);
+			clk_put(ldb.ldb_di_clk[1]);
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+		}
+		spin_unlock(&ldb_lock);
+		break;
+		}
+	case LDB_ENABLE:
+		{
+		int ipu_di;
+
+		if (copy_from_user(&ipu_di, (int *) arg, sizeof(int)))
+			return -EFAULT;
+
+		ldb_enable(ipu_di);
+		break;
+		}
+	case LDB_DISABLE:
+		{
+		int ipu_di;
+
+		if (copy_from_user(&ipu_di, (int *) arg, sizeof(int)))
+			return -EFAULT;
+
+		ldb_disable(ipu_di);
+		break;
+		}
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static int mxc_ldb_open(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static int mxc_ldb_release(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static int mxc_ldb_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	return 0;
+}
+
+static const struct file_operations mxc_ldb_fops = {
+	.owner = THIS_MODULE,
+	.open = mxc_ldb_open,
+	.mmap = mxc_ldb_mmap,
+	.release = mxc_ldb_release,
+	.ioctl = mxc_ldb_ioctl
+};
+
+/*!
+ * This function is called by the driver framework to initialize the LDB
+ * device.
+ *
+ * @param	dev	The device structure for the LDB passed in by the
+ *			driver framework.
+ *
+ * @return      Returns 0 on success or negative error code on error
+ */
+static int ldb_probe(struct platform_device *pdev)
+{
+	int ret = 0, i, ipu_di, ipu_di_pix_fmt[2];
+	bool primary = false, find_1080p = false;
+	struct resource *res;
+	struct ldb_platform_data *plat_data = pdev->dev.platform_data;
+	mm_segment_t old_fs;
+	struct clk *ldb_clk_parent;
+	unsigned long ldb_clk_prate = 455000000;
+	struct fb_var_screeninfo *var[2];
+	uint32_t reg;
+	struct device *temp;
+	int mxc_ldb_major;
+	const struct fb_videomode *mode;
+	struct class *mxc_ldb_class;
+
+	if (g_enable_ldb == false)
+		return -ENODEV;
+
+	spin_lock_init(&ldb_lock);
+
+	g_ldb_dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (IS_ERR(res))
+		return -ENODEV;
+
+	memset(&ldb, 0, sizeof(struct ldb_data));
+	enabled[0] = enabled[1] = false;
+	var[0] = var[1] = NULL;
+	if (g_boot_cmd) {
+		ldb.chan_mode_opt = g_chan_mode_opt;
+		ldb.chan_bit_map[0] = g_chan_bit_map[0];
+		ldb.chan_bit_map[1] = g_chan_bit_map[1];
+	}
+
+	ldb.base_addr = res->start;
+	ldb_reg = ioremap(ldb.base_addr, res->end - res->start + 1);
+	ldb.control_reg = ldb_reg + 2;
+
+	INIT_LIST_HEAD(&ldb.modelist);
+	for (i = 0; i < mxcfb_ldb_modedb_sz; i++)
+		fb_add_videomode(&mxcfb_ldb_modedb[i], &ldb.modelist);
+
+	for (i = 0; i < num_registered_fb; i++) {
+		if ((registered_fb[i]->var.sync & FB_SYNC_EXT) &&
+		    (registered_fb[i]->var.vmode == FB_VMODE_NONINTERLACED)) {
+			ldb.fbi[i] = registered_fb[i];
+
+			mode = fb_match_mode(&ldb.fbi[i]->var, &ldb.modelist);
+			if (mode) {
+				dev_dbg(g_ldb_dev, "fb mode found\n");
+				fb_videomode_to_var(&ldb.fbi[i]->var, mode);
+			} else {
+				dev_warn(g_ldb_dev,
+						"can't find video mode\n");
+				goto err0;
+			}
+			/*
+			 * Default ldb mode:
+			 * 1080p: DI0 split, SPWG
+			 * others: single, SPWG
+			 */
+			if (g_boot_cmd == false) {
+				ldb.chan_bit_map[0] = LDB_BIT_MAP_SPWG;
+				if (fb_mode_is_equal(mode, &mxcfb_ldb_modedb[0])) {
+					ldb.chan_mode_opt = LDB_SPL_DI0;
+					ldb.chan_bit_map[0] = LDB_BIT_MAP_SPWG;
+					ldb.chan_bit_map[1] = LDB_BIT_MAP_SPWG;
+					find_1080p = true;
+					dev_warn(g_ldb_dev, "default split mode\n");
+				} else if (!find_1080p) {
+					if (strcmp(ldb.fbi[i]->fix.id,
+					    "DISP3 BG") == 0) {
+						ldb.chan_mode_opt = LDB_SIN_DI0;
+						ldb.chan_bit_map[0] = LDB_BIT_MAP_SPWG;
+						dev_warn(g_ldb_dev,
+							 "default di0 single mode\n");
+					} else if (strcmp(ldb.fbi[i]->fix.id,
+						   "DISP3 BG - DI1") == 0) {
+						ldb.chan_mode_opt = LDB_SIN_DI1;
+						ldb.chan_bit_map[1] = LDB_BIT_MAP_SPWG;
+						dev_warn(g_ldb_dev,
+							 "default di1 single mode\n");
+					}
+				}
+			}
+
+			acquire_console_sem();
+			fb_blank(ldb.fbi[i], FB_BLANK_POWERDOWN);
+			release_console_sem();
+
+			if (i == 0)
+				primary = true;
+
+			if (ldb.fbi[1] != NULL)
+				break;
+		}
+	}
+
+	/*
+	 * We cannot support two LVDS panel with different pixel clock rates
+	 * except that one's pixel clock rate is two times of the others'.
+	 */
+	if (ldb.fbi[1] && ldb.fbi[0] != NULL) {
+		if (ldb.fbi[0]->var.pixclock != ldb.fbi[1]->var.pixclock &&
+		    ldb.fbi[0]->var.pixclock != 2 * ldb.fbi[1]->var.pixclock &&
+		    ldb.fbi[1]->var.pixclock != 2 * ldb.fbi[0]->var.pixclock)
+			return -EINVAL;
+	}
+
+	ldb.bgref_rmode = plat_data->ext_ref;
+	ldb.lvds_bg_reg = regulator_get(&pdev->dev, plat_data->lvds_bg_reg);
+	if (!IS_ERR(ldb.lvds_bg_reg)) {
+		regulator_set_voltage(ldb.lvds_bg_reg, 2500000, 2500000);
+		regulator_enable(ldb.lvds_bg_reg);
+	}
+
+	for (i = 0; i < 2; i++) {
+		if (ldb.fbi[i] != NULL) {
+			if (strcmp(ldb.fbi[i]->fix.id, "DISP3 BG") == 0)
+				ipu_di = 0;
+			else if (strcmp(ldb.fbi[i]->fix.id, "DISP3 BG - DI1")
+				 == 0)
+				ipu_di = 1;
+			else {
+				dev_err(g_ldb_dev, "Wrong framebuffer\n");
+				goto err0;
+			}
+
+			var[ipu_di] = &ldb.fbi[i]->var;
+			if (ldb.fbi[i]->fbops->fb_ioctl) {
+				old_fs = get_fs();
+				set_fs(KERNEL_DS);
+				ldb.fbi[i]->fbops->fb_ioctl(ldb.fbi[i],
+						MXCFB_GET_DIFMT,
+						(unsigned long)&(ipu_di_pix_fmt[ipu_di]));
+				set_fs(old_fs);
+			} else {
+				dev_err(g_ldb_dev, "Can't get framebuffer "
+						   "information\n");
+				goto err0;
+			}
+
+			if (!valid_mode(ipu_di_pix_fmt[ipu_di])) {
+				dev_err(g_ldb_dev, "Unsupport pixel format "
+						   "for ldb input\n");
+				goto err0;
+			}
+
+			reg = __raw_readl(ldb.control_reg);
+			if (var[ipu_di]->sync & FB_SYNC_VERT_HIGH_ACT) {
+				if (ipu_di == 0)
+					__raw_writel((reg &
+						~LDB_DI0_VS_POL_MASK) |
+						LDB_DI0_VS_POL_ACT_HIGH,
+						ldb.control_reg);
+				else
+					__raw_writel((reg &
+						~LDB_DI1_VS_POL_MASK) |
+						LDB_DI1_VS_POL_ACT_HIGH,
+						ldb.control_reg);
+			} else {
+				if (ipu_di == 0)
+					__raw_writel((reg &
+						~LDB_DI0_VS_POL_MASK) |
+						LDB_DI0_VS_POL_ACT_LOW,
+						ldb.control_reg);
+				else
+					__raw_writel((reg &
+						~LDB_DI1_VS_POL_MASK) |
+						LDB_DI1_VS_POL_ACT_LOW,
+						ldb.control_reg);
+			}
+
+			/* TODO:Set the correct pll4 rate for all situations */
+			if (ipu_di == 1) {
+				ldb.ldb_di_clk[1] =
+					clk_get(&pdev->dev, "ldb_di1_clk");
+				ldb_clk_parent =
+					clk_get_parent(ldb.ldb_di_clk[1]);
+				clk_set_rate(ldb_clk_parent, ldb_clk_prate);
+				clk_put(ldb.ldb_di_clk[1]);
+			} else {
+				ldb.ldb_di_clk[0] =
+					clk_get(&pdev->dev, "ldb_di0_clk");
+				ldb_clk_parent =
+					clk_get_parent(ldb.ldb_di_clk[0]);
+				clk_set_rate(ldb_clk_parent, ldb_clk_prate);
+				clk_put(ldb.ldb_di_clk[0]);
+			}
+		}
+	}
+
+	reg = __raw_readl(ldb.control_reg);
+	if (ldb.bgref_rmode == LDB_EXT_REF)
+		__raw_writel((reg & ~LDB_BGREF_RMODE_MASK) |
+			      LDB_BGREF_RMODE_EXT, ldb.control_reg);
+	else
+		__raw_writel((reg & ~LDB_BGREF_RMODE_MASK) |
+			      LDB_BGREF_RMODE_INT, ldb.control_reg);
+
+	switch (ldb.chan_mode_opt) {
+	case LDB_SIN_DI0:
+		if (var[0] == NULL) {
+			dev_err(g_ldb_dev, "Can't find framebuffer on DI0\n");
+			break;
+		}
+
+		reg = __raw_readl(ldb.control_reg);
+		if (bits_per_pixel(ipu_di_pix_fmt[0]) == 24)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+				      LDB_DATA_WIDTH_CH0_24,
+				      ldb.control_reg);
+		else if (bits_per_pixel(ipu_di_pix_fmt[0]) == 18)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+				      LDB_DATA_WIDTH_CH0_18,
+				      ldb.control_reg);
+
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_JEIDA,
+				      ldb.control_reg);
+
+		ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+		clk_set_rate(ldb.ldb_di_clk[0], ldb_clk_prate/7);
+		clk_enable(ldb.ldb_di_clk[0]);
+		clk_put(ldb.ldb_di_clk[0]);
+
+		reg = __raw_readl(ldb.control_reg);
+		__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+			      LDB_CH0_MODE_EN_TO_DI0, ldb.control_reg);
+		ldb.ch_working[0] = true;
+		break;
+	case LDB_SIN_DI1:
+		if (var[1] == NULL) {
+			dev_err(g_ldb_dev, "Can't find framebuffer on DI1\n");
+			break;
+		}
+
+		reg = __raw_readl(ldb.control_reg);
+		if (bits_per_pixel(ipu_di_pix_fmt[1]) == 24)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) |
+				      LDB_DATA_WIDTH_CH1_24,
+				      ldb.control_reg);
+		else if (bits_per_pixel(ipu_di_pix_fmt[1]) == 18)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) |
+				      LDB_DATA_WIDTH_CH1_18,
+				      ldb.control_reg);
+
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_JEIDA,
+				      ldb.control_reg);
+
+		ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+		clk_set_rate(ldb.ldb_di_clk[1], ldb_clk_prate/7);
+		clk_enable(ldb.ldb_di_clk[1]);
+		clk_put(ldb.ldb_di_clk[1]);
+
+		reg = __raw_readl(ldb.control_reg);
+		__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+			      LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg);
+		ldb.ch_working[1] = true;
+		break;
+	case LDB_SEP:
+		if (var[0] == NULL || var[1] == NULL) {
+			dev_err(g_ldb_dev, "Can't find framebuffers on DI0/1\n");
+			break;
+		}
+
+		reg = __raw_readl(ldb.control_reg);
+		if (bits_per_pixel(ipu_di_pix_fmt[0]) == 24)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+				      LDB_DATA_WIDTH_CH0_24,
+				      ldb.control_reg);
+		else if (bits_per_pixel(ipu_di_pix_fmt[0]) == 18)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+				      LDB_DATA_WIDTH_CH0_18,
+				      ldb.control_reg);
+		reg = __raw_readl(ldb.control_reg);
+		if (bits_per_pixel(ipu_di_pix_fmt[1]) == 24)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) |
+				      LDB_DATA_WIDTH_CH1_24,
+				      ldb.control_reg);
+		else if (bits_per_pixel(ipu_di_pix_fmt[1]) == 18)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) |
+				      LDB_DATA_WIDTH_CH1_18,
+				      ldb.control_reg);
+
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_JEIDA,
+				      ldb.control_reg);
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_JEIDA,
+				      ldb.control_reg);
+
+		ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+		clk_set_rate(ldb.ldb_di_clk[0], ldb_clk_prate/7);
+		clk_enable(ldb.ldb_di_clk[0]);
+		clk_put(ldb.ldb_di_clk[0]);
+		ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+		clk_set_rate(ldb.ldb_di_clk[1], ldb_clk_prate/7);
+		clk_enable(ldb.ldb_di_clk[1]);
+		clk_put(ldb.ldb_di_clk[1]);
+
+		reg = __raw_readl(ldb.control_reg);
+		__raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+				      LDB_CH1_MODE_MASK)) |
+			      LDB_CH0_MODE_EN_TO_DI0 |
+			      LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg);
+		ldb.ch_working[0] = true;
+		ldb.ch_working[1] = true;
+		break;
+	case LDB_DUL_DI0:
+	case LDB_SPL_DI0:
+		if (var[0] == NULL) {
+			dev_err(g_ldb_dev, "Can't find framebuffer on DI0\n");
+			break;
+		}
+
+		reg = __raw_readl(ldb.control_reg);
+		if (bits_per_pixel(ipu_di_pix_fmt[0]) == 24)
+			__raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK |
+					      LDB_DATA_WIDTH_CH1_MASK)) |
+				      LDB_DATA_WIDTH_CH0_24 |
+				      LDB_DATA_WIDTH_CH1_24,
+				      ldb.control_reg);
+		else if (bits_per_pixel(ipu_di_pix_fmt[0]) == 18)
+			__raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK |
+					      LDB_DATA_WIDTH_CH1_MASK)) |
+				      LDB_DATA_WIDTH_CH0_18 |
+				      LDB_DATA_WIDTH_CH1_18,
+				      ldb.control_reg);
+
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_JEIDA,
+				      ldb.control_reg);
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_JEIDA,
+				      ldb.control_reg);
+
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_mode_opt == LDB_SPL_DI0)
+			__raw_writel(reg | LDB_SPLIT_MODE_EN,
+				      ldb.control_reg);
+
+		ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+		ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+		if (ldb.chan_mode_opt == LDB_DUL_DI0) {
+			clk_set_rate(ldb.ldb_di_clk[0], ldb_clk_prate/7);
+		} else {
+			clk_set_rate(ldb.ldb_di_clk[0], 2*ldb_clk_prate/7);
+			clk_set_rate(ldb.ldb_di_clk[1], 2*ldb_clk_prate/7);
+		}
+		clk_enable(ldb.ldb_di_clk[0]);
+		clk_enable(ldb.ldb_di_clk[1]);
+		clk_put(ldb.ldb_di_clk[0]);
+		clk_put(ldb.ldb_di_clk[1]);
+
+		reg = __raw_readl(ldb.control_reg);
+		__raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+				      LDB_CH1_MODE_MASK)) |
+			      LDB_CH0_MODE_EN_TO_DI0 |
+			      LDB_CH1_MODE_EN_TO_DI0, ldb.control_reg);
+		ldb.ch_working[0] = true;
+		ldb.ch_working[1] = true;
+		break;
+	case LDB_DUL_DI1:
+	case LDB_SPL_DI1:
+		if (var[1] == NULL) {
+			dev_err(g_ldb_dev, "Can't find framebuffer on DI1\n");
+			break;
+		}
+
+		reg = __raw_readl(ldb.control_reg);
+		if (bits_per_pixel(ipu_di_pix_fmt[1]) == 24)
+			__raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK |
+					      LDB_DATA_WIDTH_CH1_MASK)) |
+				      LDB_DATA_WIDTH_CH0_24 |
+				      LDB_DATA_WIDTH_CH1_24,
+				      ldb.control_reg);
+		else if (bits_per_pixel(ipu_di_pix_fmt[1]) == 18)
+			__raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK |
+					      LDB_DATA_WIDTH_CH1_MASK)) |
+				      LDB_DATA_WIDTH_CH0_18 |
+				      LDB_DATA_WIDTH_CH1_18,
+				      ldb.control_reg);
+
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_JEIDA,
+				      ldb.control_reg);
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_JEIDA,
+				      ldb.control_reg);
+
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_mode_opt == LDB_SPL_DI1)
+			__raw_writel(reg | LDB_SPLIT_MODE_EN,
+				      ldb.control_reg);
+
+		ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+		ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+		if (ldb.chan_mode_opt == LDB_DUL_DI1) {
+			clk_set_rate(ldb.ldb_di_clk[1], ldb_clk_prate/7);
+		} else {
+			clk_set_rate(ldb.ldb_di_clk[0], 2*ldb_clk_prate/7);
+			clk_set_rate(ldb.ldb_di_clk[1], 2*ldb_clk_prate/7);
+		}
+		clk_enable(ldb.ldb_di_clk[0]);
+		clk_enable(ldb.ldb_di_clk[1]);
+		clk_put(ldb.ldb_di_clk[0]);
+		clk_put(ldb.ldb_di_clk[1]);
+
+		reg = __raw_readl(ldb.control_reg);
+		__raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+				      LDB_CH1_MODE_MASK)) |
+			      LDB_CH0_MODE_EN_TO_DI1 |
+			      LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg);
+		ldb.ch_working[0] = true;
+		ldb.ch_working[1] = true;
+		break;
+	default:
+		break;
+	}
+
+	mxc_ldb_major = register_chrdev(0, "mxc_ldb", &mxc_ldb_fops);
+	if (mxc_ldb_major < 0) {
+		dev_err(g_ldb_dev, "Unable to register MXC LDB as a char "
+				   "device\n");
+		ret = mxc_ldb_major;
+		goto err0;
+	}
+
+	mxc_ldb_class = class_create(THIS_MODULE, "mxc_ldb");
+	if (IS_ERR(mxc_ldb_class)) {
+		dev_err(g_ldb_dev, "Unable to create class for MXC LDB\n");
+		ret = PTR_ERR(mxc_ldb_class);
+		goto err1;
+	}
+
+	temp = device_create(mxc_ldb_class, NULL, MKDEV(mxc_ldb_major, 0),
+			NULL, "mxc_ldb");
+	if (IS_ERR(temp)) {
+		dev_err(g_ldb_dev, "Unable to create class device for "
+				   "MXC LDB\n");
+		ret = PTR_ERR(temp);
+		goto err2;
+	}
+
+	ret = fb_register_client(&nb);
+	if (ret < 0)
+		goto err2;
+
+	if (primary && ldb.fbi[0] != NULL) {
+		acquire_console_sem();
+		fb_blank(ldb.fbi[0], FB_BLANK_UNBLANK);
+		release_console_sem();
+		fb_show_logo(ldb.fbi[0], 0);
+	}
+
+	return ret;
+err2:
+	class_destroy(mxc_ldb_class);
+err1:
+	unregister_chrdev(mxc_ldb_major, "mxc_ldb");
+err0:
+	iounmap(ldb_reg);
+	return ret;
+}
+
+static int ldb_remove(struct platform_device *pdev)
+{
+	int i;
+
+	__raw_writel(0, ldb.control_reg);
+
+	for (i = 0; i < 2; i++) {
+		if (ldb.ch_working[i]) {
+			ldb.ldb_di_clk[i] = clk_get(NULL,
+					    i ? "ldb_di1_clk" : "ldb_di0_clk");
+			clk_disable(ldb.ldb_di_clk[i]);
+			clk_put(ldb.ldb_di_clk[i]);
+			ldb.ch_working[i] = false;
+		}
+	}
+
+	fb_unregister_client(&nb);
+	return 0;
+}
+
+static int ldb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	switch (ldb.chan_mode_opt) {
+	case LDB_SIN_DI0:
+	case LDB_DUL_DI0:
+	case LDB_SPL_DI0:
+		ldb_disable(0);
+		break;
+	case LDB_SIN_DI1:
+	case LDB_DUL_DI1:
+	case LDB_SPL_DI1:
+		ldb_disable(1);
+		break;
+	case LDB_SEP:
+		ldb_disable(0);
+		ldb_disable(1);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int ldb_resume(struct platform_device *pdev)
+{
+	switch (ldb.chan_mode_opt) {
+	case LDB_SIN_DI0:
+	case LDB_DUL_DI0:
+	case LDB_SPL_DI0:
+		ldb_enable(0);
+		break;
+	case LDB_SIN_DI1:
+	case LDB_DUL_DI1:
+	case LDB_SPL_DI1:
+		ldb_enable(1);
+		break;
+	case LDB_SEP:
+		ldb_enable(0);
+		ldb_enable(1);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static struct platform_driver mxcldb_driver = {
+	.driver = {
+		   .name = "mxc_ldb",
+		   },
+	.probe = ldb_probe,
+	.remove = ldb_remove,
+	.suspend = ldb_suspend,
+	.resume = ldb_resume,
+};
+
+/*
+ * Parse user specified options (`lvds=')
+ * example:
+ * lvds=single(separate, dual or split),(di=0 or di=1),
+ *	ch0_map=SPWG or JEIDA,ch1_map=SPWG or JEIDA
+ *
+ */
+static int __init ldb_setup(char *options)
+{
+	g_enable_ldb = true;
+
+	if (!strlen(options))
+		return 1;
+	else if (!strsep(&options, "="))
+		return 1;
+
+	if (!strncmp(options, "single", 6)) {
+		strsep(&options, ",");
+		if (!strncmp(options, "di=0", 4))
+			g_chan_mode_opt = LDB_SIN_DI0;
+		else
+			g_chan_mode_opt = LDB_SIN_DI1;
+	} else if (!strncmp(options, "separate", 8)) {
+		g_chan_mode_opt = LDB_SEP;
+	} else if (!strncmp(options, "dual", 4)) {
+		strsep(&options, ",");
+		if (!strncmp(options, "di=", 3)) {
+			if (simple_strtoul(options + 3, NULL, 0) == 0)
+				g_chan_mode_opt = LDB_DUL_DI0;
+			else
+				g_chan_mode_opt = LDB_DUL_DI1;
+		}
+	} else if (!strncmp(options, "split", 5)) {
+		strsep(&options, ",");
+		if (!strncmp(options, "di=", 3)) {
+			if (simple_strtoul(options + 3, NULL, 0) == 0)
+				g_chan_mode_opt = LDB_SPL_DI0;
+			else
+				g_chan_mode_opt = LDB_SPL_DI1;
+		}
+	} else
+		return 1;
+
+	if ((strsep(&options, ",") != NULL) &&
+	    !strncmp(options, "ch0_map=", 8)) {
+		if (!strncmp(options + 8, "SPWG", 4))
+			g_chan_bit_map[0] = LDB_BIT_MAP_SPWG;
+		else
+			g_chan_bit_map[0] = LDB_BIT_MAP_JEIDA;
+	}
+
+	if (!(g_chan_mode_opt == LDB_SIN_DI0 ||
+	      g_chan_mode_opt == LDB_SIN_DI1) &&
+	    (strsep(&options, ",") != NULL) &&
+	    !strncmp(options, "ch1_map=", 8)) {
+		if (!strncmp(options + 8, "SPWG", 4))
+			g_chan_bit_map[1] = LDB_BIT_MAP_SPWG;
+		else
+			g_chan_bit_map[1] = LDB_BIT_MAP_JEIDA;
+	}
+
+	g_boot_cmd = true;
+
+	return 1;
+}
+__setup("ldb", ldb_setup);
+
+static int __init ldb_init(void)
+{
+	int ret;
+
+	ret = platform_driver_register(&mxcldb_driver);
+	return 0;
+}
+
+static void __exit ldb_uninit(void)
+{
+	platform_driver_unregister(&mxcldb_driver);
+}
+
+module_init(ldb_init);
+module_exit(ldb_uninit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC LDB driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/mxc_elcdif_fb.c b/drivers/video/mxc/mxc_elcdif_fb.c
new file mode 100644
index 000000000000..44587d28c7f9
--- /dev/null
+++ b/drivers/video/mxc/mxc_elcdif_fb.c
@@ -0,0 +1,1438 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+/*
+ * Based on drivers/video/mxc/mxc_ipuv3_fb.c, drivers/video/mxs/lcdif.c
+ *	    and arch/arm/mach-mx28/include/mach/lcdif.h.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/mxcfb.h>
+#include <linux/uaccess.h>
+
+#include <mach/hardware.h>
+
+#include "elcdif_regs.h"
+
+/*  ELCDIF Pixel format definitions */
+/*  Four-character-code (FOURCC) */
+#define fourcc(a, b, c, d) \
+	(((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
+
+/*
+ * ELCDIF RGB Formats
+ */
+#define ELCDIF_PIX_FMT_RGB332  fourcc('R', 'G', 'B', '1')
+#define ELCDIF_PIX_FMT_RGB555  fourcc('R', 'G', 'B', 'O')
+#define ELCDIF_PIX_FMT_RGB565  fourcc('R', 'G', 'B', 'P')
+#define ELCDIF_PIX_FMT_RGB666  fourcc('R', 'G', 'B', '6')
+#define ELCDIF_PIX_FMT_BGR666  fourcc('B', 'G', 'R', '6')
+#define ELCDIF_PIX_FMT_BGR24   fourcc('B', 'G', 'R', '3')
+#define ELCDIF_PIX_FMT_RGB24   fourcc('R', 'G', 'B', '3')
+#define ELCDIF_PIX_FMT_BGR32   fourcc('B', 'G', 'R', '4')
+#define ELCDIF_PIX_FMT_BGRA32  fourcc('B', 'G', 'R', 'A')
+#define ELCDIF_PIX_FMT_RGB32   fourcc('R', 'G', 'B', '4')
+#define ELCDIF_PIX_FMT_RGBA32  fourcc('R', 'G', 'B', 'A')
+#define ELCDIF_PIX_FMT_ABGR32  fourcc('A', 'B', 'G', 'R')
+
+struct mxc_elcdif_fb_data {
+	int is_blank;
+	int output_pix_fmt;
+	int elcdif_mode;
+	ssize_t mem_size;
+	ssize_t map_size;
+	dma_addr_t phys_start;
+	dma_addr_t cur_phys;
+	int dma_irq;
+	int err_irq;
+	void *virt_start;
+	struct completion vsync_complete;
+	struct semaphore flip_sem;
+	u32 pseudo_palette[16];
+};
+
+struct elcdif_signal_cfg {
+	unsigned clk_pol:1;	/* true = falling edge */
+	unsigned enable_pol:1;	/* true = active high */
+	unsigned Hsync_pol:1;	/* true = active high */
+	unsigned Vsync_pol:1;	/* true = active high */
+};
+
+static int mxc_elcdif_fb_blank(int blank, struct fb_info *info);
+static int mxc_elcdif_fb_map_video_memory(struct fb_info *info);
+static int mxc_elcdif_fb_unmap_video_memory(struct fb_info *info);
+static char *fb_mode;
+static unsigned long default_bpp = 16;
+static void __iomem *elcdif_base;
+static struct device *g_elcdif_dev;
+static bool g_elcdif_axi_clk_enable;
+static bool g_elcdif_pix_clk_enable;
+static struct clk *g_elcdif_axi_clk;
+static struct clk *g_elcdif_pix_clk;
+
+static inline void setup_dotclk_panel(u32 pixel_clk,
+				      u16 v_pulse_width,
+				      u16 v_period,
+				      u16 v_wait_cnt,
+				      u16 v_active,
+				      u16 h_pulse_width,
+				      u16 h_period,
+				      u16 h_wait_cnt,
+				      u16 h_active,
+				      int in_pixel_format,
+				      int out_pixel_format,
+				      struct elcdif_signal_cfg sig_cfg,
+				      int enable_present)
+{
+	u32 val, rounded_pixel_clk;
+
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	dev_dbg(g_elcdif_dev, "pixel clk = %d\n", pixel_clk);
+	rounded_pixel_clk = clk_round_rate(g_elcdif_pix_clk, pixel_clk);
+	clk_set_rate(g_elcdif_pix_clk, rounded_pixel_clk);
+
+	__raw_writel(BM_ELCDIF_CTRL_DATA_SHIFT_DIR,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+
+	__raw_writel(BM_ELCDIF_CTRL_SHIFT_NUM_BITS,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+
+	__raw_writel(BF_ELCDIF_CTRL2_OUTSTANDING_REQS
+		    (BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_8),
+		     elcdif_base + HW_ELCDIF_CTRL2_SET);
+
+	/* Recover on underflow */
+	__raw_writel(BM_ELCDIF_CTRL1_RECOVER_ON_UNDERFLOW,
+		     elcdif_base + HW_ELCDIF_CTRL1_SET);
+
+	/* Configure the input pixel format */
+	__raw_writel(BM_ELCDIF_CTRL_WORD_LENGTH |
+		     BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE |
+		     BM_ELCDIF_CTRL_DATA_FORMAT_16_BIT |
+		     BM_ELCDIF_CTRL_DATA_FORMAT_18_BIT |
+		     BM_ELCDIF_CTRL_DATA_FORMAT_24_BIT,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT,
+		     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	switch (in_pixel_format) {
+	case ELCDIF_PIX_FMT_RGB565:
+		__raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0xF),
+			     elcdif_base + HW_ELCDIF_CTRL1_SET);
+		__raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(0) |
+			     BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0),
+			     elcdif_base + HW_ELCDIF_CTRL_SET);
+		break;
+	case ELCDIF_PIX_FMT_RGB24:
+		__raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0xF),
+			     elcdif_base + HW_ELCDIF_CTRL1_SET);
+		__raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) |
+			     BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0),
+			     elcdif_base + HW_ELCDIF_CTRL_SET);
+		break;
+	case ELCDIF_PIX_FMT_RGB32:
+		__raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0x7),
+			     elcdif_base + HW_ELCDIF_CTRL1_SET);
+		__raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) |
+			     BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0),
+			     elcdif_base + HW_ELCDIF_CTRL_SET);
+		break;
+	default:
+		dev_err(g_elcdif_dev, "ELCDIF unsupported input pixel format "
+		       "%d\n", in_pixel_format);
+		break;
+	}
+
+	/* Configure the output pixel format */
+	__raw_writel(BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	switch (out_pixel_format) {
+	case ELCDIF_PIX_FMT_RGB565:
+		__raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(0),
+			     elcdif_base + HW_ELCDIF_CTRL_SET);
+		break;
+	case ELCDIF_PIX_FMT_RGB666:
+		__raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(2),
+			     elcdif_base + HW_ELCDIF_CTRL_SET);
+		break;
+	case ELCDIF_PIX_FMT_RGB24:
+		__raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(3),
+			     elcdif_base + HW_ELCDIF_CTRL_SET);
+		break;
+	default:
+		dev_err(g_elcdif_dev, "ELCDIF unsupported output pixel format "
+		       "%d\n", out_pixel_format);
+		break;
+	}
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_TRANSFER_COUNT);
+	val &= ~(BM_ELCDIF_TRANSFER_COUNT_V_COUNT |
+		 BM_ELCDIF_TRANSFER_COUNT_H_COUNT);
+	val |= BF_ELCDIF_TRANSFER_COUNT_H_COUNT(h_active) |
+	       BF_ELCDIF_TRANSFER_COUNT_V_COUNT(v_active);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_TRANSFER_COUNT);
+
+	__raw_writel(BM_ELCDIF_CTRL_VSYNC_MODE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(BM_ELCDIF_CTRL_WAIT_FOR_VSYNC_EDGE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(BM_ELCDIF_CTRL_DVI_MODE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(BM_ELCDIF_CTRL_DOTCLK_MODE,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+	__raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0);
+	val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_POL |
+		 BM_ELCDIF_VDCTRL0_HSYNC_POL |
+		 BM_ELCDIF_VDCTRL0_ENABLE_POL |
+		 BM_ELCDIF_VDCTRL0_DOTCLK_POL);
+	if (sig_cfg.Vsync_pol)
+		val |= BM_ELCDIF_VDCTRL0_VSYNC_POL;
+	if (sig_cfg.Hsync_pol)
+		val |= BM_ELCDIF_VDCTRL0_HSYNC_POL;
+	if (sig_cfg.clk_pol)
+		val |= BM_ELCDIF_VDCTRL0_DOTCLK_POL;
+	if (sig_cfg.enable_pol)
+		val |= BM_ELCDIF_VDCTRL0_ENABLE_POL;
+	__raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0);
+
+	/* vsync is output */
+	val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0);
+	val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_OEB);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0);
+
+	/*
+	 * need enable sig for true RGB i/f.  Or, if not true RGB, leave it
+	 * zero.
+	 */
+	if (enable_present) {
+		val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0);
+		val |= BM_ELCDIF_VDCTRL0_ENABLE_PRESENT;
+		__raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0);
+	}
+
+	/*
+	 * For DOTCLK mode, count VSYNC_PERIOD in terms of complete hz lines
+	 */
+	val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0);
+	val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
+		 BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT);
+	val |= BM_ELCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
+	       BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT;
+	__raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0);
+
+	__raw_writel(BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH,
+		     elcdif_base + HW_ELCDIF_VDCTRL0_CLR);
+	__raw_writel(v_pulse_width, elcdif_base + HW_ELCDIF_VDCTRL0_SET);
+
+	__raw_writel(BF_ELCDIF_VDCTRL1_VSYNC_PERIOD(v_period),
+		     elcdif_base + HW_ELCDIF_VDCTRL1);
+
+	__raw_writel(BF_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(h_pulse_width) |
+		     BF_ELCDIF_VDCTRL2_HSYNC_PERIOD(h_period),
+		     elcdif_base + HW_ELCDIF_VDCTRL2);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL4);
+	val &= ~BM_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT;
+	val |= BF_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(h_active);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL4);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL3);
+	val &= ~(BM_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT |
+		 BM_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT);
+	val |= BF_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(h_wait_cnt) |
+	       BF_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v_wait_cnt);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL3);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL4);
+	val |= BM_ELCDIF_VDCTRL4_SYNC_SIGNALS_ON;
+	__raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL4);
+
+	return;
+}
+
+static inline void release_dotclk_panel(void)
+{
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	__raw_writel(BM_ELCDIF_CTRL_DOTCLK_MODE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL0);
+	__raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL1);
+	__raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL2);
+	__raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL3);
+
+	return;
+}
+
+static inline void setup_dvi_panel(u16 h_active, u16 v_active,
+				   u16 h_blanking, u16 v_lines,
+				   u16 v1_blank_start, u16 v1_blank_end,
+				   u16 v2_blank_start, u16 v2_blank_end,
+				   u16 f1_start, u16 f1_end,
+				   u16 f2_start, u16 f2_end)
+{
+	u32 val;
+
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	/* 32bit packed format (RGB) */
+	__raw_writel(BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT,
+		     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	__raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0x7) |
+		     BM_ELCDIF_CTRL1_RECOVER_ON_UNDERFLOW,
+		     elcdif_base + HW_ELCDIF_CTRL1_SET);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_TRANSFER_COUNT);
+	val &= ~(BM_ELCDIF_TRANSFER_COUNT_V_COUNT |
+		 BM_ELCDIF_TRANSFER_COUNT_H_COUNT);
+	val |= BF_ELCDIF_TRANSFER_COUNT_H_COUNT(h_active) |
+	       BF_ELCDIF_TRANSFER_COUNT_V_COUNT(v_active);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_TRANSFER_COUNT);
+
+	/* set elcdif to DVI mode */
+	__raw_writel(BM_ELCDIF_CTRL_DVI_MODE,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+	__raw_writel(BM_ELCDIF_CTRL_VSYNC_MODE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(BM_ELCDIF_CTRL_DOTCLK_MODE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+
+	__raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+	/* convert input RGB -> YCbCr */
+	__raw_writel(BM_ELCDIF_CTRL_RGB_TO_YCBCR422_CSC,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+	/* interlace odd and even fields */
+	__raw_writel(BM_ELCDIF_CTRL1_INTERLACE_FIELDS,
+		     elcdif_base + HW_ELCDIF_CTRL1_SET);
+
+	__raw_writel(BM_ELCDIF_CTRL_WORD_LENGTH |
+		     BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE |
+		     BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) |	/* 24 bit */
+		      BM_ELCDIF_CTRL_DATA_SELECT |	/* data mode */
+		      BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0) |	/* no swap */
+		      BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(1),	/* 8 bit */
+		      elcdif_base + HW_ELCDIF_CTRL_SET);
+
+	/* ELCDIF_DVI */
+	/* set frame size */
+	val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL0);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL0);
+
+	/* set start/end of field-1 and start of field-2 */
+	val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL1);
+	val &= ~(BM_ELCDIF_DVICTRL1_F1_START_LINE |
+		 BM_ELCDIF_DVICTRL1_F1_END_LINE |
+		 BM_ELCDIF_DVICTRL1_F2_START_LINE);
+	val |= BF_ELCDIF_DVICTRL1_F1_START_LINE(f1_start) |
+	       BF_ELCDIF_DVICTRL1_F1_END_LINE(f1_end) |
+	       BF_ELCDIF_DVICTRL1_F2_START_LINE(f2_start);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL1);
+
+	/* set first vertical blanking interval and end of filed-2 */
+	val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL2);
+	val &= ~(BM_ELCDIF_DVICTRL2_F2_END_LINE |
+		 BM_ELCDIF_DVICTRL2_V1_BLANK_START_LINE |
+		 BM_ELCDIF_DVICTRL2_V1_BLANK_END_LINE);
+	val |= BF_ELCDIF_DVICTRL2_F2_END_LINE(f2_end) |
+	       BF_ELCDIF_DVICTRL2_V1_BLANK_START_LINE(v1_blank_start) |
+	       BF_ELCDIF_DVICTRL2_V1_BLANK_END_LINE(v1_blank_end);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL2);
+
+	/* set second vertical blanking interval */
+	val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL3);
+	val &= ~(BM_ELCDIF_DVICTRL3_V2_BLANK_START_LINE |
+		      BM_ELCDIF_DVICTRL3_V2_BLANK_END_LINE);
+	val |= BF_ELCDIF_DVICTRL3_V2_BLANK_START_LINE(v2_blank_start) |
+	       BF_ELCDIF_DVICTRL3_V2_BLANK_END_LINE(v2_blank_end);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL3);
+
+	/* fill the rest area black color if the input frame
+	 * is not 720 pixels/line
+	 */
+	if (h_active != 720) {
+		/* the input frame can't be less then (720-256) pixels/line */
+		if (720 - h_active > 0xff)
+			h_active = 720 - 0xff;
+
+		val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL4);
+		val &= ~(BM_ELCDIF_DVICTRL4_H_FILL_CNT |
+			      BM_ELCDIF_DVICTRL4_Y_FILL_VALUE |
+			      BM_ELCDIF_DVICTRL4_CB_FILL_VALUE |
+			      BM_ELCDIF_DVICTRL4_CR_FILL_VALUE);
+		val |= BF_ELCDIF_DVICTRL4_H_FILL_CNT(720 - h_active) |
+		       BF_ELCDIF_DVICTRL4_Y_FILL_VALUE(16) |
+		       BF_ELCDIF_DVICTRL4_CB_FILL_VALUE(128) |
+		       BF_ELCDIF_DVICTRL4_CR_FILL_VALUE(128);
+		__raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL4);
+	}
+
+	/* Color Space Conversion RGB->YCbCr */
+	val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF0);
+	val &= ~(BM_ELCDIF_CSC_COEFF0_C0 |
+		      BM_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER);
+	val |= BF_ELCDIF_CSC_COEFF0_C0(0x41) |
+	       BF_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(3);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF0);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF1);
+	val &= ~(BM_ELCDIF_CSC_COEFF1_C1 | BM_ELCDIF_CSC_COEFF1_C2);
+	val |= BF_ELCDIF_CSC_COEFF1_C1(0x81) |
+	       BF_ELCDIF_CSC_COEFF1_C2(0x19);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF1);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF2);
+	val &= ~(BM_ELCDIF_CSC_COEFF2_C3 | BM_ELCDIF_CSC_COEFF2_C4);
+	val |= BF_ELCDIF_CSC_COEFF2_C3(0x3DB) |
+	       BF_ELCDIF_CSC_COEFF2_C4(0x3B6);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF2);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF3);
+	val &= ~(BM_ELCDIF_CSC_COEFF3_C5 | BM_ELCDIF_CSC_COEFF3_C6);
+	val |= BF_ELCDIF_CSC_COEFF3_C5(0x70) |
+	       BF_ELCDIF_CSC_COEFF3_C6(0x70);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF3);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF4);
+	val &= ~(BM_ELCDIF_CSC_COEFF4_C7 | BM_ELCDIF_CSC_COEFF4_C8);
+	val |= BF_ELCDIF_CSC_COEFF4_C7(0x3A2) |
+	       BF_ELCDIF_CSC_COEFF4_C8(0x3EE);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF4);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_OFFSET);
+	val &= ~(BM_ELCDIF_CSC_OFFSET_CBCR_OFFSET |
+		 BM_ELCDIF_CSC_OFFSET_Y_OFFSET);
+	val |= BF_ELCDIF_CSC_OFFSET_CBCR_OFFSET(0x80) |
+	       BF_ELCDIF_CSC_OFFSET_Y_OFFSET(0x10);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_CSC_OFFSET);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_LIMIT);
+	val &= ~(BM_ELCDIF_CSC_LIMIT_CBCR_MIN |
+		 BM_ELCDIF_CSC_LIMIT_CBCR_MAX |
+		 BM_ELCDIF_CSC_LIMIT_Y_MIN |
+		 BM_ELCDIF_CSC_LIMIT_Y_MAX);
+	val |= BF_ELCDIF_CSC_LIMIT_CBCR_MIN(16) |
+	       BF_ELCDIF_CSC_LIMIT_CBCR_MAX(240) |
+	       BF_ELCDIF_CSC_LIMIT_Y_MIN(16) |
+	       BF_ELCDIF_CSC_LIMIT_Y_MAX(235);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_CSC_LIMIT);
+
+	return;
+}
+
+static inline void release_dvi_panel(void)
+{
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	__raw_writel(BM_ELCDIF_CTRL_DVI_MODE,
+			elcdif_base + HW_ELCDIF_CTRL_CLR);
+	return;
+}
+
+static inline void mxc_init_elcdif(void)
+{
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	__raw_writel(BM_ELCDIF_CTRL_CLKGATE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	/* Reset controller */
+	__raw_writel(BM_ELCDIF_CTRL_SFTRST,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+	udelay(10);
+
+	/* Take controller out of reset */
+	__raw_writel(BM_ELCDIF_CTRL_SFTRST | BM_ELCDIF_CTRL_CLKGATE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+
+	/* Setup the bus protocol */
+	__raw_writel(BM_ELCDIF_CTRL1_MODE86,
+		     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	__raw_writel(BM_ELCDIF_CTRL1_BUSY_ENABLE,
+		     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+
+	/* Take display out of reset */
+	__raw_writel(BM_ELCDIF_CTRL1_RESET,
+		     elcdif_base + HW_ELCDIF_CTRL1_SET);
+
+	/* VSYNC is an input by default */
+	__raw_writel(BM_ELCDIF_VDCTRL0_VSYNC_OEB,
+		     elcdif_base + HW_ELCDIF_VDCTRL0_SET);
+
+	/* Reset display */
+	__raw_writel(BM_ELCDIF_CTRL1_RESET,
+		     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	udelay(10);
+	__raw_writel(BM_ELCDIF_CTRL1_RESET,
+		     elcdif_base + HW_ELCDIF_CTRL1_SET);
+	udelay(10);
+
+	return;
+}
+
+static inline int mxc_elcdif_dma_init(dma_addr_t phys)
+{
+	int ret = 0;
+
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	__raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+
+	__raw_writel(phys, elcdif_base + HW_ELCDIF_CUR_BUF);
+	__raw_writel(phys, elcdif_base + HW_ELCDIF_NEXT_BUF);
+	return ret;
+}
+
+static inline void mxc_elcdif_dma_release(void)
+{
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	__raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	return;
+}
+
+static inline void mxc_elcdif_run(void)
+{
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	__raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+	__raw_writel(BM_ELCDIF_CTRL_RUN,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+	return;
+}
+
+static inline void mxc_elcdif_stop(void)
+{
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	__raw_writel(BM_ELCDIF_CTRL_RUN,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	msleep(1);
+	__raw_writel(BM_ELCDIF_CTRL_CLKGATE, elcdif_base + HW_ELCDIF_CTRL_SET);
+	return;
+}
+
+static int mxc_elcdif_blank_panel(int blank)
+{
+	int ret = 0, count;
+
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	switch (blank) {
+	case FB_BLANK_NORMAL:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_POWERDOWN:
+		__raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT,
+				elcdif_base + HW_ELCDIF_CTRL_CLR);
+		for (count = 10000; count; count--) {
+			if (__raw_readl(elcdif_base + HW_ELCDIF_STAT) &
+			    BM_ELCDIF_STAT_TXFIFO_EMPTY)
+				break;
+			msleep(1);
+		}
+		break;
+
+	case FB_BLANK_UNBLANK:
+		__raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT,
+			      elcdif_base + HW_ELCDIF_CTRL_SET);
+		break;
+
+	default:
+		dev_err(g_elcdif_dev, "unknown blank parameter\n");
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+static int mxc_elcdif_init_panel(void)
+{
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	/*
+	 * Make sure we do a high-to-low transition to reset the panel.
+	 * First make it low for 100 msec, hi for 10 msec, low for 10 msec,
+	 * then hi.
+	 */
+	__raw_writel(BM_ELCDIF_CTRL1_RESET,
+		     elcdif_base + HW_ELCDIF_CTRL1_CLR);	/* low */
+	msleep(100);
+	__raw_writel(BM_ELCDIF_CTRL1_RESET,
+		     elcdif_base + HW_ELCDIF_CTRL1_SET);	/* high */
+	msleep(10);
+	__raw_writel(BM_ELCDIF_CTRL1_RESET,
+		     elcdif_base + HW_ELCDIF_CTRL1_CLR);	/* low */
+
+	/* For the Samsung, Reset must be held low at least 30 uSec
+	 * Therefore, we'll hold it low for about 10 mSec just to be sure.
+	 * Then we'll wait 1 mSec afterwards.
+	 */
+	msleep(10);
+	__raw_writel(BM_ELCDIF_CTRL1_RESET,
+		     elcdif_base + HW_ELCDIF_CTRL1_SET);	/* high */
+	msleep(1);
+
+	return 0;
+}
+
+static uint32_t bpp_to_pixfmt(struct fb_info *fbi)
+{
+	uint32_t pixfmt = 0;
+
+	if (fbi->var.nonstd)
+		return fbi->var.nonstd;
+
+	switch (fbi->var.bits_per_pixel) {
+	case 32:
+		pixfmt = ELCDIF_PIX_FMT_RGB32;
+		break;
+	case 24:
+		pixfmt = ELCDIF_PIX_FMT_RGB24;
+		break;
+	case 18:
+		pixfmt = ELCDIF_PIX_FMT_RGB666;
+		break;
+	case 16:
+		pixfmt = ELCDIF_PIX_FMT_RGB565;
+		break;
+	case 8:
+		pixfmt = ELCDIF_PIX_FMT_RGB332;
+		break;
+	}
+	return pixfmt;
+}
+
+static int mxc_elcdif_fb_set_fix(struct fb_info *info)
+{
+	struct fb_fix_screeninfo *fix = &info->fix;
+	struct fb_var_screeninfo *var = &info->var;
+
+	fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+
+	fix->type = FB_TYPE_PACKED_PIXELS;
+	fix->accel = FB_ACCEL_NONE;
+	fix->visual = FB_VISUAL_TRUECOLOR;
+	fix->xpanstep = 1;
+	fix->ypanstep = 1;
+
+	return 0;
+}
+
+static irqreturn_t lcd_irq_handler(int irq, void *dev_id)
+{
+	struct mxc_elcdif_fb_data *data = dev_id;
+	u32 status_lcd = __raw_readl(elcdif_base + HW_ELCDIF_CTRL1);
+	dev_dbg(g_elcdif_dev, "%s: irq %d\n", __func__, irq);
+
+	if (status_lcd & BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ) {
+		dev_dbg(g_elcdif_dev, "%s: VSYNC irq\n", __func__);
+		__raw_writel(BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ,
+			     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+		complete(&data->vsync_complete);
+	}
+	if (status_lcd & BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ) {
+		dev_dbg(g_elcdif_dev, "%s: frame done irq\n", __func__);
+		__raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ,
+			     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+		up(&data->flip_sem);
+	}
+	if (status_lcd & BM_ELCDIF_CTRL1_UNDERFLOW_IRQ) {
+		dev_dbg(g_elcdif_dev, "%s: underflow irq\n", __func__);
+		__raw_writel(BM_ELCDIF_CTRL1_UNDERFLOW_IRQ,
+			     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	}
+	if (status_lcd & BM_ELCDIF_CTRL1_OVERFLOW_IRQ) {
+		dev_dbg(g_elcdif_dev, "%s: overflow irq\n", __func__);
+		__raw_writel(BM_ELCDIF_CTRL1_OVERFLOW_IRQ,
+			     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	}
+	return IRQ_HANDLED;
+}
+
+static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf)
+{
+	chan &= 0xffff;
+	chan >>= 16 - bf->length;
+	return chan << bf->offset;
+}
+
+static int mxc_elcdif_fb_setcolreg(u_int regno, u_int red, u_int green,
+				 u_int blue, u_int transp,
+				 struct fb_info *fbi)
+{
+	unsigned int val;
+	int ret = 1;
+
+	/*
+	 * If greyscale is true, then we convert the RGB value
+	 * to greyscale no matter what visual we are using.
+	 */
+	if (fbi->var.grayscale)
+		red = green = blue = (19595 * red + 38470 * green +
+				      7471 * blue) >> 16;
+	switch (fbi->fix.visual) {
+	case FB_VISUAL_TRUECOLOR:
+		/*
+		 * 16-bit True Colour.  We encode the RGB value
+		 * according to the RGB bitfield information.
+		 */
+		if (regno < 16) {
+			u32 *pal = fbi->pseudo_palette;
+
+			val = _chan_to_field(red, &fbi->var.red);
+			val |= _chan_to_field(green, &fbi->var.green);
+			val |= _chan_to_field(blue, &fbi->var.blue);
+
+			pal[regno] = val;
+			ret = 0;
+		}
+		break;
+
+	case FB_VISUAL_STATIC_PSEUDOCOLOR:
+	case FB_VISUAL_PSEUDOCOLOR:
+		break;
+	}
+	return ret;
+}
+
+/*
+ * This routine actually sets the video mode. It's in here where we
+ * the hardware state info->par and fix which can be affected by the
+ * change in par. For this driver it doesn't do much.
+ *
+ */
+static int mxc_elcdif_fb_set_par(struct fb_info *fbi)
+{
+	struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par;
+	struct elcdif_signal_cfg sig_cfg;
+	int mem_len;
+
+	dev_dbg(fbi->device, "Reconfiguring framebuffer\n");
+
+	sema_init(&data->flip_sem, 1);
+
+	/* release prev panel */
+	if (!g_elcdif_pix_clk_enable) {
+		clk_enable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = true;
+	}
+	mxc_elcdif_blank_panel(FB_BLANK_POWERDOWN);
+	mxc_elcdif_stop();
+	release_dotclk_panel();
+	mxc_elcdif_dma_release();
+	mxc_elcdif_fb_set_fix(fbi);
+	if (g_elcdif_pix_clk_enable) {
+		clk_disable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = false;
+	}
+
+	mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
+	if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
+		if (fbi->fix.smem_start)
+			mxc_elcdif_fb_unmap_video_memory(fbi);
+
+		if (mxc_elcdif_fb_map_video_memory(fbi) < 0)
+			return -ENOMEM;
+	}
+
+	if (data->is_blank)
+		return 0;
+
+	/* init next panel */
+	if (!g_elcdif_pix_clk_enable) {
+		clk_enable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = true;
+	}
+	mxc_init_elcdif();
+	mxc_elcdif_init_panel();
+
+	dev_dbg(fbi->device, "pixclock = %ul Hz\n",
+		(u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
+
+	memset(&sig_cfg, 0, sizeof(sig_cfg));
+	if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
+		sig_cfg.Hsync_pol = true;
+	if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
+		sig_cfg.Vsync_pol = true;
+	if (fbi->var.sync & FB_SYNC_CLK_LAT_FALL)
+		sig_cfg.clk_pol = true;
+	if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT))
+		sig_cfg.enable_pol = true;
+
+	setup_dotclk_panel((PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
+			   fbi->var.vsync_len,
+			   fbi->var.upper_margin +
+			   fbi->var.yres + fbi->var.lower_margin,
+			   fbi->var.upper_margin,
+			   fbi->var.yres,
+			   fbi->var.hsync_len,
+			   fbi->var.left_margin +
+			   fbi->var.xres + fbi->var.right_margin,
+			   fbi->var.left_margin,
+			   fbi->var.xres,
+			   bpp_to_pixfmt(fbi),
+			   data->output_pix_fmt,
+			   sig_cfg,
+			   1);
+	mxc_elcdif_dma_init(fbi->fix.smem_start);
+	mxc_elcdif_run();
+	mxc_elcdif_blank_panel(FB_BLANK_UNBLANK);
+
+	fbi->mode = (struct fb_videomode *)fb_match_mode(&fbi->var,
+							 &fbi->modelist);
+	return 0;
+}
+
+static int mxc_elcdif_fb_check_var(struct fb_var_screeninfo *var,
+				 struct fb_info *info)
+{
+	if (var->xres_virtual < var->xres)
+		var->xres_virtual = var->xres;
+	if (var->yres_virtual < var->yres)
+		var->yres_virtual = var->yres;
+
+	if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
+	    (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8))
+		var->bits_per_pixel = default_bpp;
+
+	switch (var->bits_per_pixel) {
+	case 8:
+		var->red.length = 3;
+		var->red.offset = 5;
+		var->red.msb_right = 0;
+
+		var->green.length = 3;
+		var->green.offset = 2;
+		var->green.msb_right = 0;
+
+		var->blue.length = 2;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 16:
+		var->red.length = 5;
+		var->red.offset = 11;
+		var->red.msb_right = 0;
+
+		var->green.length = 6;
+		var->green.offset = 5;
+		var->green.msb_right = 0;
+
+		var->blue.length = 5;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 24:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 32:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 8;
+		var->transp.offset = 24;
+		var->transp.msb_right = 0;
+		break;
+	}
+
+	var->height = -1;
+	var->width = -1;
+	var->grayscale = 0;
+
+	return 0;
+}
+
+static int mxc_elcdif_fb_wait_for_vsync(u32 channel, struct fb_info *info)
+{
+	struct mxc_elcdif_fb_data *data =
+				(struct mxc_elcdif_fb_data *)info->par;
+	int ret = 0;
+
+	if (data->is_blank) {
+		dev_err(info->device, "can't wait for VSYNC when fb "
+			"is blank\n");
+		return -EINVAL;
+	}
+
+	init_completion(&data->vsync_complete);
+
+	__raw_writel(BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ_EN,
+		elcdif_base + HW_ELCDIF_CTRL1_SET);
+	ret = wait_for_completion_interruptible_timeout(
+				&data->vsync_complete, 1 * HZ);
+	if (ret == 0) {
+		dev_err(info->device,
+			"MXC ELCDIF wait for vsync: timeout %d\n",
+			ret);
+		ret = -ETIME;
+	} else if (ret > 0) {
+		ret = 0;
+	}
+	__raw_writel(BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ_EN,
+		elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	if (!ret) {
+		dev_err(info->device, "wait for vsync timed out\n");
+		ret = -ETIMEDOUT;
+	}
+	return ret;
+}
+
+static int mxc_elcdif_fb_ioctl(struct fb_info *info, unsigned int cmd,
+			unsigned long arg)
+{
+	u32 channel = 0;
+	int ret = -EINVAL;
+
+	switch (cmd) {
+	case MXCFB_WAIT_FOR_VSYNC:
+		if (!get_user(channel, (__u32 __user *) arg))
+			ret = mxc_elcdif_fb_wait_for_vsync(channel, info);
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+static int mxc_elcdif_fb_blank(int blank, struct fb_info *info)
+{
+	struct mxc_elcdif_fb_data *data =
+				(struct mxc_elcdif_fb_data *)info->par;
+	int ret = 0;
+
+	if (data->is_blank == (blank != FB_BLANK_UNBLANK))
+		return ret;
+
+	if (blank == FB_BLANK_UNBLANK) {
+		if (!g_elcdif_pix_clk_enable) {
+			clk_enable(g_elcdif_pix_clk);
+			g_elcdif_pix_clk_enable = true;
+		}
+	}
+	ret = mxc_elcdif_blank_panel(blank);
+	if (ret == 0)
+		data->is_blank = (blank != FB_BLANK_UNBLANK);
+	else
+		return ret;
+
+	if (data->is_blank) {
+		if (g_elcdif_axi_clk_enable) {
+			clk_disable(g_elcdif_axi_clk);
+			g_elcdif_axi_clk_enable = false;
+		}
+		if (g_elcdif_pix_clk_enable) {
+			clk_disable(g_elcdif_pix_clk);
+			g_elcdif_pix_clk_enable = false;
+		}
+	} else {
+		if (!g_elcdif_axi_clk_enable) {
+			clk_enable(g_elcdif_axi_clk);
+			g_elcdif_axi_clk_enable = true;
+		}
+		if (!g_elcdif_pix_clk_enable) {
+			clk_enable(g_elcdif_pix_clk);
+			g_elcdif_pix_clk_enable = true;
+		}
+	}
+
+	return ret;
+}
+
+static int mxc_elcdif_fb_pan_display(struct fb_var_screeninfo *var,
+				struct fb_info *info)
+{
+	struct mxc_elcdif_fb_data *data =
+				(struct mxc_elcdif_fb_data *)info->par;
+	int ret = 0;
+	unsigned long base;
+
+	if (data->is_blank) {
+		dev_err(info->device, "can't do pan display when fb "
+			"is blank\n");
+		return -EINVAL;
+	}
+
+	if (var->xoffset > 0) {
+		dev_dbg(info->device, "x panning not supported\n");
+		return -EINVAL;
+	}
+
+	if ((var->yoffset + var->yres > var->yres_virtual)) {
+		dev_err(info->device, "y panning exceeds\n");
+		return -EINVAL;
+	}
+
+	/* update framebuffer visual */
+	base = (var->yoffset * var->xres_virtual + var->xoffset);
+	base *= (var->bits_per_pixel) / 8;
+	base += info->fix.smem_start;
+
+	__raw_writel(base, elcdif_base + HW_ELCDIF_NEXT_BUF);
+
+	init_completion(&data->vsync_complete);
+
+	/*
+	 * Wait for an interrupt or we will lose frame
+	 * if we call pan-dislay too fast.
+	 */
+	__raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ,
+		elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	__raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN,
+		elcdif_base + HW_ELCDIF_CTRL1_SET);
+	down(&data->flip_sem);
+	__raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN,
+		elcdif_base + HW_ELCDIF_CTRL1_CLR);
+
+	return ret;
+}
+
+static struct fb_ops mxc_elcdif_fb_ops = {
+	.owner = THIS_MODULE,
+	.fb_check_var = mxc_elcdif_fb_check_var,
+	.fb_set_par = mxc_elcdif_fb_set_par,
+	.fb_setcolreg = mxc_elcdif_fb_setcolreg,
+	.fb_ioctl = mxc_elcdif_fb_ioctl,
+	.fb_blank = mxc_elcdif_fb_blank,
+	.fb_pan_display = mxc_elcdif_fb_pan_display,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+};
+
+/*!
+ * Allocates the DRAM memory for the frame buffer.      This buffer is remapped
+ * into a non-cached, non-buffered, memory region to allow palette and pixel
+ * writes to occur without flushing the cache.  Once this area is remapped,
+ * all virtual memory access to the video memory should occur at the new region.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @return      Error code indicating success or failure
+ */
+static int mxc_elcdif_fb_map_video_memory(struct fb_info *fbi)
+{
+	if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length)
+		fbi->fix.smem_len = fbi->var.yres_virtual *
+				    fbi->fix.line_length;
+
+	fbi->screen_base = dma_alloc_writecombine(fbi->device,
+				fbi->fix.smem_len,
+				(dma_addr_t *)&fbi->fix.smem_start,
+				GFP_DMA);
+	if (fbi->screen_base == 0) {
+		dev_err(fbi->device, "Unable to allocate framebuffer memory\n");
+		fbi->fix.smem_len = 0;
+		fbi->fix.smem_start = 0;
+		return -EBUSY;
+	}
+
+	dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n",
+		(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
+
+	fbi->screen_size = fbi->fix.smem_len;
+
+	/* Clear the screen */
+	memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
+
+	return 0;
+}
+
+/*!
+ * De-allocates the DRAM memory for the frame buffer.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @return      Error code indicating success or failure
+ */
+static int mxc_elcdif_fb_unmap_video_memory(struct fb_info *fbi)
+{
+	dma_free_writecombine(fbi->device, fbi->fix.smem_len,
+			      fbi->screen_base, fbi->fix.smem_start);
+	fbi->screen_base = 0;
+	fbi->fix.smem_start = 0;
+	fbi->fix.smem_len = 0;
+	return 0;
+}
+
+static int mxc_elcdif_fb_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct mxc_elcdif_fb_data *data;
+	struct resource *res;
+	struct fb_info *fbi;
+	struct mxc_fb_platform_data *pdata = pdev->dev.platform_data;
+
+	fbi = framebuffer_alloc(sizeof(struct mxc_elcdif_fb_data), &pdev->dev);
+	if (fbi == NULL) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	data = (struct mxc_elcdif_fb_data *)fbi->par;
+	data->is_blank = false;
+
+	fbi->var.activate = FB_ACTIVATE_NOW;
+	fbi->fbops = &mxc_elcdif_fb_ops;
+	fbi->flags = FBINFO_FLAG_DEFAULT;
+	fbi->pseudo_palette = data->pseudo_palette;
+
+	ret = fb_alloc_cmap(&fbi->cmap, 16, 0);
+	if (ret)
+		goto out;
+
+	g_elcdif_dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "cannot get IRQ resource\n");
+		ret = -ENODEV;
+		goto err0;
+	}
+	data->dma_irq = res->start;
+
+	ret = request_irq(data->dma_irq, lcd_irq_handler, 0,
+			  "mxc_elcdif_fb", data);
+	if (ret) {
+		dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
+				data->dma_irq, ret);
+		goto err0;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		ret = -ENODEV;
+		goto err1;
+	}
+	elcdif_base = ioremap(res->start, SZ_4K);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (res) {
+		fbi->fix.smem_len = res->end - res->start + 1;
+		fbi->fix.smem_start = res->start;
+		fbi->screen_base = ioremap(fbi->fix.smem_start,
+					   fbi->fix.smem_len);
+	}
+
+	strcpy(fbi->fix.id, "mxc_elcdif_fb");
+
+	fbi->var.xres = 800;
+	fbi->var.yres = 480;
+
+	if (pdata && !data->output_pix_fmt)
+		data->output_pix_fmt = pdata->interface_pix_fmt;
+
+	if (pdata && pdata->mode && pdata->num_modes)
+		fb_videomode_to_modelist(pdata->mode, pdata->num_modes,
+				&fbi->modelist);
+
+	if (!fb_mode && pdata && pdata->mode_str)
+		fb_mode = pdata->mode_str;
+
+	if (fb_mode) {
+		ret = fb_find_mode(&fbi->var, fbi, fb_mode, NULL, 0, NULL,
+				   default_bpp);
+		if ((!ret || (ret > 2)) && pdata && pdata->mode &&
+		    pdata->num_modes)
+			fb_find_mode(&fbi->var, fbi, fb_mode, pdata->mode,
+					pdata->num_modes, NULL, default_bpp);
+	}
+
+	mxc_elcdif_fb_check_var(&fbi->var, fbi);
+
+	fbi->var.xres_virtual = fbi->var.xres;
+	fbi->var.yres_virtual = fbi->var.yres * 3;
+
+	mxc_elcdif_fb_set_fix(fbi);
+
+	if (!res || !res->end)
+		if (mxc_elcdif_fb_map_video_memory(fbi) < 0) {
+			ret = -ENOMEM;
+			goto err2;
+		}
+
+	g_elcdif_axi_clk = clk_get(g_elcdif_dev, "elcdif_axi");
+	if (g_elcdif_axi_clk == NULL) {
+		dev_err(&pdev->dev, "can't get ELCDIF axi clk\n");
+		ret = -ENODEV;
+		goto err3;
+	}
+	g_elcdif_pix_clk = clk_get(g_elcdif_dev, "elcdif_pix");
+	if (g_elcdif_pix_clk == NULL) {
+		dev_err(&pdev->dev, "can't get ELCDIF pix clk\n");
+		ret = -ENODEV;
+		goto err3;
+	}
+	/*
+	 * Set an appropriate pixel clk rate first, so that we can
+	 * access ELCDIF registers.
+	 */
+	clk_set_rate(g_elcdif_pix_clk, 25000000);
+
+	ret = register_framebuffer(fbi);
+	if (ret)
+		goto err3;
+
+	platform_set_drvdata(pdev, fbi);
+
+	return 0;
+err3:
+	mxc_elcdif_fb_unmap_video_memory(fbi);
+err2:
+	iounmap(elcdif_base);
+err1:
+	free_irq(data->dma_irq, data);
+err0:
+	fb_dealloc_cmap(&fbi->cmap);
+	framebuffer_release(fbi);
+out:
+	return ret;
+}
+
+static int mxc_elcdif_fb_remove(struct platform_device *pdev)
+{
+	struct fb_info *fbi = platform_get_drvdata(pdev);
+	struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par;
+
+	mxc_elcdif_fb_blank(FB_BLANK_POWERDOWN, fbi);
+	mxc_elcdif_stop();
+	release_dotclk_panel();
+	mxc_elcdif_dma_release();
+
+	if (g_elcdif_axi_clk_enable) {
+		clk_disable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = false;
+	}
+	if (g_elcdif_pix_clk_enable) {
+		clk_disable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = false;
+	}
+	clk_put(g_elcdif_axi_clk);
+	clk_put(g_elcdif_pix_clk);
+
+	free_irq(data->dma_irq, data);
+	mxc_elcdif_fb_unmap_video_memory(fbi);
+
+	if (&fbi->cmap)
+		fb_dealloc_cmap(&fbi->cmap);
+
+	unregister_framebuffer(fbi);
+	framebuffer_release(fbi);
+
+	platform_set_drvdata(pdev, NULL);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxc_elcdif_fb_suspend(struct platform_device *pdev,
+			       pm_message_t state)
+{
+	struct fb_info *fbi = platform_get_drvdata(pdev);
+	struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par;
+	int saved_blank;
+
+	acquire_console_sem();
+	fb_set_suspend(fbi, 1);
+	saved_blank = data->is_blank;
+	mxc_elcdif_fb_blank(FB_BLANK_POWERDOWN, fbi);
+	data->is_blank = saved_blank;
+	if (!g_elcdif_pix_clk_enable) {
+		clk_enable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = true;
+	}
+	mxc_elcdif_stop();
+	mxc_elcdif_dma_release();
+	if (g_elcdif_pix_clk_enable) {
+		clk_disable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = false;
+	}
+
+	return 0;
+}
+
+static int mxc_elcdif_fb_resume(struct platform_device *pdev)
+{
+	struct fb_info *fbi = platform_get_drvdata(pdev);
+	struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par;
+
+	acquire_console_sem();
+	if (!g_elcdif_pix_clk_enable) {
+		clk_enable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = true;
+	}
+	mxc_init_elcdif();
+	mxc_elcdif_init_panel();
+	mxc_elcdif_dma_init(fbi->fix.smem_start);
+	mxc_elcdif_run();
+	if (g_elcdif_pix_clk_enable) {
+		clk_disable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = false;
+	}
+	if (!data->is_blank)
+		mxc_elcdif_fb_blank(FB_BLANK_UNBLANK, fbi);
+	fb_set_suspend(fbi, 0);
+	release_console_sem();
+
+	return 0;
+}
+#else
+#define	mxc_elcdif_fb_suspend	NULL
+#define	mxc_elcdif_fb_resume	NULL
+#endif
+
+static struct platform_driver mxc_elcdif_fb_driver = {
+	.probe		= mxc_elcdif_fb_probe,
+	.remove		= mxc_elcdif_fb_remove,
+	.suspend	= mxc_elcdif_fb_suspend,
+	.resume		= mxc_elcdif_fb_resume,
+	.driver		= {
+		.name   = "mxc_elcdif_fb",
+		.owner	= THIS_MODULE,
+	},
+};
+
+/*
+ * Parse user specified options (`video=trident:')
+ * example:
+ * 	video=trident:800x600,bpp=16,noaccel
+ */
+int mxc_elcdif_fb_setup(char *options)
+{
+	char *opt;
+	if (!options || !*options)
+		return 0;
+	while ((opt = strsep(&options, ",")) != NULL) {
+		if (!*opt)
+			continue;
+
+		if (!strncmp(opt, "bpp=", 4))
+			default_bpp = simple_strtoul(opt + 4, NULL, 0);
+		else
+			fb_mode = opt;
+	}
+	return 0;
+}
+
+static int __init mxc_elcdif_fb_init(void)
+{
+	char *option = NULL;
+
+	if (fb_get_options("mxc_elcdif_fb", &option))
+		return -ENODEV;
+	mxc_elcdif_fb_setup(option);
+
+	return platform_driver_register(&mxc_elcdif_fb_driver);
+}
+
+static void __exit mxc_elcdif_fb_exit(void)
+{
+	platform_driver_unregister(&mxc_elcdif_fb_driver);
+}
+
+module_init(mxc_elcdif_fb_init);
+module_exit(mxc_elcdif_fb_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC ELCDIF Framebuffer Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/mxc_epdc_fb.c b/drivers/video/mxc/mxc_epdc_fb.c
new file mode 100644
index 000000000000..27f9faa64e53
--- /dev/null
+++ b/drivers/video/mxc/mxc_epdc_fb.c
@@ -0,0 +1,3079 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+/*
+ * Based on STMP378X LCDIF
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*#define		NO_POWERDOWN*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/uaccess.h>
+#include <linux/cpufreq.h>
+#include <linux/firmware.h>
+#include <linux/kthread.h>
+#include <linux/dmaengine.h>
+#include <linux/pxp_dma.h>
+#include <linux/mxcfb.h>
+#include <linux/gpio.h>
+#include <linux/regulator/driver.h>
+
+#include "epdc_regs.h"
+
+/*
+ * Enable this define to have a default panel
+ * loaded during driver initialization
+ */
+/*#define DEFAULT_PANEL_HW_INIT*/
+
+#define NUM_SCREENS	2
+#define EPDC_NUM_LUTS 16
+#define EPDC_MAX_NUM_UPDATES 20
+#define INVALID_LUT -1
+#define TEMP_USE_DEFAULT 8
+#define INIT_UPDATE_MARKER 0x12345678
+#define PAN_UPDATE_MARKER 0x12345679
+
+#define LUT_UPDATE_NONE	0
+#define LUT_UPDATE_NEW	1
+#define LUT_UPDATE_COLLISION	2
+
+#define POWER_STATE_OFF	0
+#define POWER_STATE_ON	1
+
+static unsigned long default_bpp = 16;
+
+struct mxc_epdc_platform_fb_entry {
+	char name[16];
+	u16 x_res;
+	u16 y_res;
+	u16 bpp;
+	u32 cycle_time_ns;
+	struct list_head link;
+};
+
+struct mxc_epdc_platform_fb_data {
+	struct list_head list;
+	struct mxc_epdc_platform_fb_entry *cur;
+};
+
+struct update_marker_data {
+	u32 update_marker;
+	struct completion update_completion;
+	int lut_num;
+};
+
+/* This structure represents a list node containing both
+ * a memory region allocated as an output buffer for the PxP
+ * update processing task, and the update description (mode, region, etc.) */
+struct update_data_list {
+	struct list_head list;
+	struct mxcfb_update_data upd_data;	/* Update parameters */
+	dma_addr_t phys_addr;			/* Pointer to phys address of processed Y buf */
+	void *virt_addr;
+	u32 epdc_offs;				/* Add to buffer pointer to resolve alignment */
+	u32 size;
+	int lut_num;				/* Assigned before update is processed into working buffer */
+	int collision_mask;			/* Set when update results in collision */
+						/* Represents other LUTs that we collide with */
+	struct update_marker_data *upd_marker_data;
+	bool is_collision;
+};
+
+struct mxc_epdc_fb_data {
+	struct fb_info info;
+	u32 pseudo_palette[16];
+	struct list_head list;
+	struct mxc_epdc_platform_fb_entry *cur;
+	int blank;
+	ssize_t mem_size;
+	ssize_t map_size;
+	dma_addr_t phys_start;
+	u32 fb_offset;
+	int native_width;
+	int native_height;
+	int epdc_irq;
+	struct device *dev;
+	wait_queue_head_t vsync_wait_q;
+	u32 vsync_count;
+	void *par;
+	int power_state;
+	struct clk *epdc_clk_axi;
+	struct clk *epdc_clk_pix;
+	struct regulator *display_regulator;
+	struct regulator *vcom_regulator;
+
+	/* FB elements related to EPDC updates */
+	bool in_init;
+	bool hw_ready;
+	bool waiting_for_idle;
+	u32 auto_mode;
+	struct update_data_list *upd_buf_queue;
+	struct update_data_list *upd_buf_free_list;
+	struct update_data_list *upd_buf_collision_list;
+	struct update_data_list *cur_update;
+	spinlock_t queue_lock;
+	int trt_entries;
+	u8 *temp_range_bounds;
+	struct mxcfb_waveform_modes wv_modes;
+	u32 *waveform_buffer_virt;
+	u32 waveform_buffer_phys;
+	u32 waveform_buffer_size;
+	u32 *working_buffer_virt;
+	u32 working_buffer_phys;
+	u32 working_buffer_size;
+	struct update_marker_data update_marker_array[EPDC_MAX_NUM_UPDATES];
+	u32 lut_update_type[EPDC_NUM_LUTS];
+	struct completion updates_done;
+	struct work_struct epdc_done_work;
+	struct mutex power_mutex;
+	bool powering_down;
+
+	/* FB elements related to PxP DMA */
+	struct completion pxp_tx_cmpl;
+	struct pxp_channel *pxp_chan;
+	struct pxp_config_data pxp_conf;
+	struct dma_async_tx_descriptor *txd;
+	dma_cookie_t cookie;
+	struct scatterlist sg[2];
+	struct mutex pxp_mutex; /* protects access to PxP */
+};
+
+struct waveform_data_header {
+	unsigned int wi0;
+	unsigned int wi1;
+	unsigned int wi2;
+	unsigned int wi3;
+	unsigned int wi4;
+	unsigned int wi5;
+	unsigned int wi6;
+	unsigned int xwia:24;
+	unsigned int cs1:8;
+	unsigned int wmta:24;
+	unsigned int fvsn:8;
+	unsigned int luts:8;
+	unsigned int mc:8;
+	unsigned int trc:8;
+	unsigned int reserved0_0:8;
+	unsigned int eb:8;
+	unsigned int sb:8;
+	unsigned int reserved0_1:8;
+	unsigned int reserved0_2:8;
+	unsigned int reserved0_3:8;
+	unsigned int reserved0_4:8;
+	unsigned int reserved0_5:8;
+	unsigned int cs2:8;
+};
+
+struct mxcfb_waveform_data_file {
+	struct waveform_data_header wdh;
+	u32 *data;	/* Temperature Range Table + Waveform Data */
+};
+
+void __iomem *epdc_base;
+
+#define NUM_PANELS 1
+
+static struct fb_videomode panel_modes[NUM_PANELS] = {
+	{
+	 /* 800x600 @ 60 Hz , pixel clk @ 20MHz */
+	 "E-INK SVGA", 60, 800, 600, 50000, 8, 142, 4, 10, 20, 4,
+	 0,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+};
+
+/*
+ * This is a temporary placeholder
+ * Ultimately, this declaration will be off in a panel-specific file,
+ * and will include implementations for all of the panel functions
+ */
+static struct mxc_epdc_platform_fb_entry ed060sc4_fb_entry = {
+	.name = "ed060sc4",
+	.x_res = 800,
+	.y_res = 600,
+	.bpp = 16,
+	.cycle_time_ns = 200,
+};
+
+/* forward declaration */
+static int mxc_epdc_fb_blank(int blank, struct fb_info *info);
+static int mxc_epdc_fb_init_hw(struct fb_info *info);
+static int pxp_process_update(struct mxc_epdc_fb_data *fb_data,
+			      struct mxcfb_rect *update_region);
+static int pxp_complete_update(struct mxc_epdc_fb_data *fb_data, u32 *hist_stat);
+
+static void draw_mode0(struct mxc_epdc_fb_data *fb_data);
+
+#ifdef DEBUG
+static void dump_pxp_config(struct mxc_epdc_fb_data *fb_data,
+			    struct pxp_config_data *pxp_conf)
+{
+	dev_err(fb_data->dev, "S0 fmt 0x%x",
+		pxp_conf->s0_param.pixel_fmt);
+	dev_err(fb_data->dev, "S0 width 0x%x",
+		pxp_conf->s0_param.width);
+	dev_err(fb_data->dev, "S0 height 0x%x",
+		pxp_conf->s0_param.height);
+	dev_err(fb_data->dev, "S0 ckey 0x%x",
+		pxp_conf->s0_param.color_key);
+	dev_err(fb_data->dev, "S0 ckey en 0x%x",
+		pxp_conf->s0_param.color_key_enable);
+
+	dev_err(fb_data->dev, "OL0 combine en 0x%x",
+		pxp_conf->ol_param[0].combine_enable);
+	dev_err(fb_data->dev, "OL0 fmt 0x%x",
+		pxp_conf->ol_param[0].pixel_fmt);
+	dev_err(fb_data->dev, "OL0 width 0x%x",
+		pxp_conf->ol_param[0].width);
+	dev_err(fb_data->dev, "OL0 height 0x%x",
+		pxp_conf->ol_param[0].height);
+	dev_err(fb_data->dev, "OL0 ckey 0x%x",
+		pxp_conf->ol_param[0].color_key);
+	dev_err(fb_data->dev, "OL0 ckey en 0x%x",
+		pxp_conf->ol_param[0].color_key_enable);
+	dev_err(fb_data->dev, "OL0 alpha 0x%x",
+		pxp_conf->ol_param[0].global_alpha);
+	dev_err(fb_data->dev, "OL0 alpha en 0x%x",
+		pxp_conf->ol_param[0].global_alpha_enable);
+	dev_err(fb_data->dev, "OL0 local alpha en 0x%x",
+		pxp_conf->ol_param[0].local_alpha_enable);
+
+	dev_err(fb_data->dev, "Out fmt 0x%x",
+		pxp_conf->out_param.pixel_fmt);
+	dev_err(fb_data->dev, "Out width 0x%x",
+		pxp_conf->out_param.width);
+	dev_err(fb_data->dev, "Out height 0x%x",
+		pxp_conf->out_param.height);
+
+	dev_err(fb_data->dev,
+		"drect left 0x%x right 0x%x width 0x%x height 0x%x",
+		pxp_conf->proc_data.drect.left, pxp_conf->proc_data.drect.top,
+		pxp_conf->proc_data.drect.width,
+		pxp_conf->proc_data.drect.height);
+	dev_err(fb_data->dev,
+		"srect left 0x%x right 0x%x width 0x%x height 0x%x",
+		pxp_conf->proc_data.srect.left, pxp_conf->proc_data.srect.top,
+		pxp_conf->proc_data.srect.width,
+		pxp_conf->proc_data.srect.height);
+	dev_err(fb_data->dev, "Scaling en 0x%x", pxp_conf->proc_data.scaling);
+	dev_err(fb_data->dev, "HFlip en 0x%x", pxp_conf->proc_data.hflip);
+	dev_err(fb_data->dev, "VFlip en 0x%x", pxp_conf->proc_data.vflip);
+	dev_err(fb_data->dev, "Rotation 0x%x", pxp_conf->proc_data.rotate);
+	dev_err(fb_data->dev, "BG Color 0x%x", pxp_conf->proc_data.bgcolor);
+}
+
+static void dump_epdc_reg(void)
+{
+	printk(KERN_DEBUG "\n\n");
+	printk(KERN_DEBUG "EPDC_CTRL 0x%x\n", __raw_readl(EPDC_CTRL));
+	printk(KERN_DEBUG "EPDC_WVADDR 0x%x\n", __raw_readl(EPDC_WVADDR));
+	printk(KERN_DEBUG "EPDC_WB_ADDR 0x%x\n", __raw_readl(EPDC_WB_ADDR));
+	printk(KERN_DEBUG "EPDC_RES 0x%x\n", __raw_readl(EPDC_RES));
+	printk(KERN_DEBUG "EPDC_FORMAT 0x%x\n", __raw_readl(EPDC_FORMAT));
+	printk(KERN_DEBUG "EPDC_FIFOCTRL 0x%x\n", __raw_readl(EPDC_FIFOCTRL));
+	printk(KERN_DEBUG "EPDC_UPD_ADDR 0x%x\n", __raw_readl(EPDC_UPD_ADDR));
+	printk(KERN_DEBUG "EPDC_UPD_FIXED 0x%x\n", __raw_readl(EPDC_UPD_FIXED));
+	printk(KERN_DEBUG "EPDC_UPD_CORD 0x%x\n", __raw_readl(EPDC_UPD_CORD));
+	printk(KERN_DEBUG "EPDC_UPD_SIZE 0x%x\n", __raw_readl(EPDC_UPD_SIZE));
+	printk(KERN_DEBUG "EPDC_UPD_CTRL 0x%x\n", __raw_readl(EPDC_UPD_CTRL));
+	printk(KERN_DEBUG "EPDC_TEMP 0x%x\n", __raw_readl(EPDC_TEMP));
+	printk(KERN_DEBUG "EPDC_TCE_CTRL 0x%x\n", __raw_readl(EPDC_TCE_CTRL));
+	printk(KERN_DEBUG "EPDC_TCE_SDCFG 0x%x\n", __raw_readl(EPDC_TCE_SDCFG));
+	printk(KERN_DEBUG "EPDC_TCE_GDCFG 0x%x\n", __raw_readl(EPDC_TCE_GDCFG));
+	printk(KERN_DEBUG "EPDC_TCE_HSCAN1 0x%x\n", __raw_readl(EPDC_TCE_HSCAN1));
+	printk(KERN_DEBUG "EPDC_TCE_HSCAN2 0x%x\n", __raw_readl(EPDC_TCE_HSCAN2));
+	printk(KERN_DEBUG "EPDC_TCE_VSCAN 0x%x\n", __raw_readl(EPDC_TCE_VSCAN));
+	printk(KERN_DEBUG "EPDC_TCE_OE 0x%x\n", __raw_readl(EPDC_TCE_OE));
+	printk(KERN_DEBUG "EPDC_TCE_POLARITY 0x%x\n", __raw_readl(EPDC_TCE_POLARITY));
+	printk(KERN_DEBUG "EPDC_TCE_TIMING1 0x%x\n", __raw_readl(EPDC_TCE_TIMING1));
+	printk(KERN_DEBUG "EPDC_TCE_TIMING2 0x%x\n", __raw_readl(EPDC_TCE_TIMING2));
+	printk(KERN_DEBUG "EPDC_TCE_TIMING3 0x%x\n", __raw_readl(EPDC_TCE_TIMING3));
+	printk(KERN_DEBUG "EPDC_IRQ_MASK 0x%x\n", __raw_readl(EPDC_IRQ_MASK));
+	printk(KERN_DEBUG "EPDC_IRQ 0x%x\n", __raw_readl(EPDC_IRQ));
+	printk(KERN_DEBUG "EPDC_STATUS_LUTS 0x%x\n", __raw_readl(EPDC_STATUS_LUTS));
+	printk(KERN_DEBUG "EPDC_STATUS_NEXTLUT 0x%x\n", __raw_readl(EPDC_STATUS_NEXTLUT));
+	printk(KERN_DEBUG "EPDC_STATUS_COL 0x%x\n", __raw_readl(EPDC_STATUS_COL));
+	printk(KERN_DEBUG "EPDC_STATUS 0x%x\n", __raw_readl(EPDC_STATUS));
+	printk(KERN_DEBUG "EPDC_DEBUG 0x%x\n", __raw_readl(EPDC_DEBUG));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT0 0x%x\n", __raw_readl(EPDC_DEBUG_LUT0));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT1 0x%x\n", __raw_readl(EPDC_DEBUG_LUT1));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT2 0x%x\n", __raw_readl(EPDC_DEBUG_LUT2));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT3 0x%x\n", __raw_readl(EPDC_DEBUG_LUT3));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT4 0x%x\n", __raw_readl(EPDC_DEBUG_LUT4));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT5 0x%x\n", __raw_readl(EPDC_DEBUG_LUT5));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT6 0x%x\n", __raw_readl(EPDC_DEBUG_LUT6));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT7 0x%x\n", __raw_readl(EPDC_DEBUG_LUT7));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT8 0x%x\n", __raw_readl(EPDC_DEBUG_LUT8));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT9 0x%x\n", __raw_readl(EPDC_DEBUG_LUT9));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT10 0x%x\n", __raw_readl(EPDC_DEBUG_LUT10));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT11 0x%x\n", __raw_readl(EPDC_DEBUG_LUT11));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT12 0x%x\n", __raw_readl(EPDC_DEBUG_LUT12));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT13 0x%x\n", __raw_readl(EPDC_DEBUG_LUT13));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT14 0x%x\n", __raw_readl(EPDC_DEBUG_LUT14));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT15 0x%x\n", __raw_readl(EPDC_DEBUG_LUT15));
+	printk(KERN_DEBUG "EPDC_GPIO 0x%x\n", __raw_readl(EPDC_GPIO));
+	printk(KERN_DEBUG "EPDC_VERSION 0x%x\n", __raw_readl(EPDC_VERSION));
+	printk(KERN_DEBUG "\n\n");
+}
+
+static void dump_update_data(struct device *dev,
+			     struct update_data_list *upd_data_list)
+{
+	dev_err(dev,
+		"X = %d, Y = %d, Width = %d, Height = %d, WaveMode = %d, LUT = %d, Coll Mask = %d\n",
+		upd_data_list->upd_data.update_region.left,
+		upd_data_list->upd_data.update_region.top,
+		upd_data_list->upd_data.update_region.width,
+		upd_data_list->upd_data.update_region.height,
+		upd_data_list->upd_data.waveform_mode, upd_data_list->lut_num,
+		upd_data_list->collision_mask);
+}
+
+static void dump_collision_list(struct mxc_epdc_fb_data *fb_data)
+{
+	struct update_data_list *plist;
+
+	dev_err(fb_data->dev, "Collision List:\n");
+	if (list_empty(&fb_data->upd_buf_collision_list->list))
+		dev_err(fb_data->dev, "Empty");
+	list_for_each_entry(plist, &fb_data->upd_buf_collision_list->list, list) {
+		dev_err(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
+			(u32)plist->virt_addr, plist->phys_addr);
+		dump_update_data(fb_data->dev, plist);
+	}
+}
+
+static void dump_free_list(struct mxc_epdc_fb_data *fb_data)
+{
+	struct update_data_list *plist;
+
+	dev_err(fb_data->dev, "Free List:\n");
+	if (list_empty(&fb_data->upd_buf_free_list->list))
+		dev_err(fb_data->dev, "Empty");
+	list_for_each_entry(plist, &fb_data->upd_buf_free_list->list, list) {
+		dev_err(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
+			(u32)plist->virt_addr, plist->phys_addr);
+		dump_update_data(fb_data->dev, plist);
+	}
+}
+
+static void dump_queue(struct mxc_epdc_fb_data *fb_data)
+{
+	struct update_data_list *plist;
+
+	dev_err(fb_data->dev, "Queue:\n");
+	if (list_empty(&fb_data->upd_buf_queue->list))
+		dev_err(fb_data->dev, "Empty");
+	list_for_each_entry(plist, &fb_data->upd_buf_queue->list, list) {
+		dev_err(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
+			(u32)plist->virt_addr, plist->phys_addr);
+		dump_update_data(fb_data->dev, plist);
+	}
+}
+
+static void dump_all_updates(struct mxc_epdc_fb_data *fb_data)
+{
+	dump_free_list(fb_data);
+	dump_queue(fb_data);
+	dump_collision_list(fb_data);
+	dev_err(fb_data->dev, "Current update being processed:\n");
+	if (fb_data->cur_update == NULL)
+		dev_err(fb_data->dev, "No current update\n");
+	else
+		dump_update_data(fb_data->dev, fb_data->cur_update);
+}
+#else
+static inline void dump_pxp_config(struct mxc_epdc_fb_data *fb_data,
+				   struct pxp_config_data *pxp_conf) {}
+static inline void dump_epdc_reg(void) {}
+static inline void dump_update_data(struct device *dev,
+			     struct update_data_list *upd_data_list) {}
+static inline void dump_collision_list(struct mxc_epdc_fb_data *fb_data) {}
+static inline void dump_free_list(struct mxc_epdc_fb_data *fb_data) {}
+static inline void dump_queue(struct mxc_epdc_fb_data *fb_data) {}
+static inline void dump_all_updates(struct mxc_epdc_fb_data *fb_data) {}
+
+#endif
+
+void check_waveform(u32 *wv_buf_orig, u32 *wv_buf_cur, u32 wv_buf_size)
+{
+	int i;
+	bool is_mismatch = false;
+	for (i = 0; i < wv_buf_size; i++) {
+		if (wv_buf_orig[i] != wv_buf_cur[i]) {
+			is_mismatch = true;
+			printk
+			    ("Waveform mismatch - wv_buf_orig[%d] = 0x%x, wv_buf_cur[%d] = 0x%x\n",
+			     i, wv_buf_orig[i], i, wv_buf_cur[i]);
+		}
+	}
+
+	if (!is_mismatch)
+		printk("No mismatches!\n");
+}
+
+static struct fb_var_screeninfo mxc_epdc_fb_default __devinitdata = {
+	.activate = FB_ACTIVATE_TEST,
+	.height = -1,
+	.width = -1,
+	.pixclock = 20000,
+	.left_margin = 8,
+	.right_margin = 142,
+	.upper_margin = 4,
+	.lower_margin = 10,
+	.hsync_len = 20,
+	.vsync_len = 4,
+	.vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_fix_screeninfo mxc_epdc_fb_fix __devinitdata = {
+	.id = "mxc_epdc_fb",
+	.type = FB_TYPE_PACKED_PIXELS,
+	.visual = FB_VISUAL_TRUECOLOR,
+	.xpanstep = 0,
+	.ypanstep = 0,
+	.ywrapstep = 0,
+	.accel = FB_ACCEL_NONE,
+	.line_length = 800 * 2,
+};
+
+/********************************************************
+ * Start Low-Level EPDC Functions
+ ********************************************************/
+
+static inline void epdc_lut_complete_intr(u32 lut_num, bool enable)
+{
+	if (enable)
+		__raw_writel(1 << lut_num, EPDC_IRQ_MASK_SET);
+	else
+		__raw_writel(1 << lut_num, EPDC_IRQ_MASK_CLEAR);
+}
+
+static inline void epdc_working_buf_intr(bool enable)
+{
+	if (enable)
+		__raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_SET);
+	else
+		__raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_CLEAR);
+}
+
+static inline void epdc_clear_working_buf_irq(void)
+{
+	__raw_writel(EPDC_IRQ_WB_CMPLT_IRQ | EPDC_IRQ_LUT_COL_IRQ,
+		     EPDC_IRQ_CLEAR);
+}
+
+static inline void epdc_set_temp(u32 temp)
+{
+	__raw_writel(temp, EPDC_TEMP);
+}
+
+static inline void epdc_set_screen_res(u32 width, u32 height)
+{
+	u32 val = (height << EPDC_RES_VERTICAL_OFFSET) | width;
+	__raw_writel(val, EPDC_RES);
+}
+
+static inline void epdc_set_update_addr(u32 addr)
+{
+	__raw_writel(addr, EPDC_UPD_ADDR);
+}
+
+static inline void epdc_set_update_coord(u32 x, u32 y)
+{
+	u32 val = (y << EPDC_UPD_CORD_YCORD_OFFSET) | x;
+	__raw_writel(val, EPDC_UPD_CORD);
+}
+
+static inline void epdc_set_update_dimensions(u32 width, u32 height)
+{
+	u32 val = (height << EPDC_UPD_SIZE_HEIGHT_OFFSET) | width;
+	__raw_writel(val, EPDC_UPD_SIZE);
+}
+
+static void epdc_submit_update(u32 lut_num, u32 waveform_mode, u32 update_mode,
+			       bool use_test_mode, u32 np_val)
+{
+	u32 reg_val = 0;
+
+	if (use_test_mode) {
+		reg_val |=
+		    ((np_val << EPDC_UPD_FIXED_FIXNP_OFFSET) &
+		     EPDC_UPD_FIXED_FIXNP_MASK) | EPDC_UPD_FIXED_FIXNP_EN;
+
+		__raw_writel(reg_val, EPDC_UPD_FIXED);
+
+		reg_val = EPDC_UPD_CTRL_USE_FIXED;
+	} else {
+		__raw_writel(reg_val, EPDC_UPD_FIXED);
+	}
+
+	reg_val |=
+	    ((lut_num << EPDC_UPD_CTRL_LUT_SEL_OFFSET) &
+	     EPDC_UPD_CTRL_LUT_SEL_MASK) |
+	    ((waveform_mode << EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET) &
+	     EPDC_UPD_CTRL_WAVEFORM_MODE_MASK) |
+	    update_mode;
+
+	__raw_writel(reg_val, EPDC_UPD_CTRL);
+}
+
+static inline bool epdc_is_lut_complete(u32 lut_num)
+{
+	u32 val = __raw_readl(EPDC_IRQ);
+	bool is_compl = val & (1 << lut_num) ? true : false;
+
+	return is_compl;
+}
+
+static inline void epdc_clear_lut_complete_irq(u32 lut_num)
+{
+	__raw_writel(1 << lut_num, EPDC_IRQ_CLEAR);
+}
+
+static inline bool epdc_is_lut_active(u32 lut_num)
+{
+	u32 val = __raw_readl(EPDC_STATUS_LUTS);
+	bool is_active = val & (1 << lut_num) ? true : false;
+
+	return is_active;
+}
+
+static inline bool epdc_any_luts_active(void)
+{
+	bool any_active = __raw_readl(EPDC_STATUS_LUTS) ? true : false;
+
+	return any_active;
+}
+
+static inline bool epdc_any_luts_available(void)
+{
+	bool luts_available =
+	    (__raw_readl(EPDC_STATUS_NEXTLUT) &
+	     EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID) ? true : false;
+	return luts_available;
+}
+
+static inline int epdc_get_next_lut(void)
+{
+	u32 val =
+	    __raw_readl(EPDC_STATUS_NEXTLUT) &
+	    EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK;
+	return val;
+}
+
+static inline bool epdc_is_working_buffer_busy(void)
+{
+	u32 val = __raw_readl(EPDC_STATUS);
+	bool is_busy = (val & EPDC_STATUS_WB_BUSY) ? true : false;
+
+	return is_busy;
+}
+
+static inline bool epdc_is_working_buffer_complete(void)
+{
+	u32 val = __raw_readl(EPDC_IRQ);
+	bool is_compl = (val & EPDC_IRQ_WB_CMPLT_IRQ) ? true : false;
+
+	return is_compl;
+}
+
+static inline bool epdc_is_collision(void)
+{
+	u32 val = __raw_readl(EPDC_IRQ);
+	return (val & EPDC_IRQ_LUT_COL_IRQ) ? true : false;
+}
+
+static inline int epdc_get_colliding_luts(void)
+{
+	u32 val = __raw_readl(EPDC_STATUS_COL);
+	return val;
+}
+
+static void epdc_set_horizontal_timing(u32 horiz_start, u32 horiz_end,
+				       u32 hsync_width, u32 hsync_line_length)
+{
+	u32 reg_val =
+	    ((hsync_width << EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET) &
+	     EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK)
+	    | ((hsync_line_length << EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET) &
+	       EPDC_TCE_HSCAN1_LINE_SYNC_MASK);
+	__raw_writel(reg_val, EPDC_TCE_HSCAN1);
+
+	reg_val =
+	    ((horiz_start << EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET) &
+	     EPDC_TCE_HSCAN2_LINE_BEGIN_MASK)
+	    | ((horiz_end << EPDC_TCE_HSCAN2_LINE_END_OFFSET) &
+	       EPDC_TCE_HSCAN2_LINE_END_MASK);
+	__raw_writel(reg_val, EPDC_TCE_HSCAN2);
+}
+
+static void epdc_set_vertical_timing(u32 vert_start, u32 vert_end,
+				     u32 vsync_width)
+{
+	u32 reg_val =
+	    ((vert_start << EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET) &
+	     EPDC_TCE_VSCAN_FRAME_BEGIN_MASK)
+	    | ((vert_end << EPDC_TCE_VSCAN_FRAME_END_OFFSET) &
+	       EPDC_TCE_VSCAN_FRAME_END_MASK)
+	    | ((vsync_width << EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET) &
+	       EPDC_TCE_VSCAN_FRAME_SYNC_MASK);
+	__raw_writel(reg_val, EPDC_TCE_VSCAN);
+}
+
+void epdc_init_settings(struct mxc_epdc_fb_data *fb_data)
+{
+	struct mxc_epdc_platform_fb_entry *pentry = fb_data->cur;
+	struct fb_var_screeninfo *screeninfo = &fb_data->info.var;
+	u32 reg_val;
+
+	/* Reset */
+	__raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_SET);
+	while (!(__raw_readl(EPDC_CTRL) & EPDC_CTRL_CLKGATE))
+		;
+	__raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_CLEAR);
+
+	/* Enable clock gating (clear to enable) */
+	__raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_CLEAR);
+	while (__raw_readl(EPDC_CTRL) & (EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
+		;
+
+	/* EPDC_CTRL */
+	reg_val = __raw_readl(EPDC_CTRL);
+	reg_val &= ~EPDC_CTRL_UPD_DATA_SWIZZLE_MASK;
+	reg_val |= EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP;
+	reg_val &= ~EPDC_CTRL_LUT_DATA_SWIZZLE_MASK;
+	reg_val |= EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP;
+	__raw_writel(reg_val, EPDC_CTRL_SET);
+
+	/* EPDC_FORMAT - 2bit TFT and 4bit Buf pixel format */
+	reg_val = EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT
+	    | EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N
+	    | ((0x0 << EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET) &
+	       EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK);
+	__raw_writel(reg_val, EPDC_FORMAT);
+
+	/* EPDC_FIFOCTRL (disabled) */
+	reg_val =
+	    ((100 << EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET) &
+	     EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK)
+	    | ((200 << EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET) &
+	       EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK)
+	    | ((100 << EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET) &
+	       EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK);
+	__raw_writel(reg_val, EPDC_FIFOCTRL);
+
+	/* EPDC_TEMP - 8 for room temperature */
+	epdc_set_temp(8);
+
+	/* EPDC_RES */
+	epdc_set_screen_res(pentry->x_res, pentry->y_res);
+
+	/*
+	 * EPDC_TCE_CTRL
+	 * VSCAN_HOLDOFF = 4
+	 * VCOM_MODE = MANUAL
+	 * VCOM_VAL = 0
+	 * DDR_MODE = DISABLED
+	 * LVDS_MODE_CE = DISABLED
+	 * LVDS_MODE = DISABLED
+	 * DUAL_SCAN = DISABLED
+	 * SDDO_WIDTH = 8bit
+	 * PIXELS_PER_SDCLK = 4
+	 */
+	reg_val =
+	    ((4 << EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET) &
+	     EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK)
+	    | EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4;
+	__raw_writel(reg_val, EPDC_TCE_CTRL);
+
+	/* EPDC_TCE_HSCAN */
+	epdc_set_horizontal_timing(screeninfo->left_margin,
+				   screeninfo->right_margin,
+				   screeninfo->hsync_len,
+				   screeninfo->hsync_len);
+
+	/* EPDC_TCE_VSCAN */
+	epdc_set_vertical_timing(screeninfo->upper_margin,
+				 screeninfo->lower_margin,
+				 screeninfo->vsync_len);
+
+	/* EPDC_TCE_OE */
+	reg_val =
+	    ((10 << EPDC_TCE_OE_SDOED_WIDTH_OFFSET) &
+	     EPDC_TCE_OE_SDOED_WIDTH_MASK)
+	    | ((20 << EPDC_TCE_OE_SDOED_DLY_OFFSET) &
+	       EPDC_TCE_OE_SDOED_DLY_MASK)
+	    | ((10 << EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET) &
+	       EPDC_TCE_OE_SDOEZ_WIDTH_MASK)
+	    | ((20 << EPDC_TCE_OE_SDOEZ_DLY_OFFSET) &
+	       EPDC_TCE_OE_SDOEZ_DLY_MASK);
+	__raw_writel(reg_val, EPDC_TCE_OE);
+
+	/* EPDC_TCE_TIMING1 */
+	__raw_writel(0x0, EPDC_TCE_TIMING1);
+
+	/* EPDC_TCE_TIMING2 */
+	reg_val =
+	    ((480 << EPDC_TCE_TIMING2_GDCLK_HP_OFFSET) &
+	     EPDC_TCE_TIMING2_GDCLK_HP_MASK)
+	    | ((20 << EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET) &
+	       EPDC_TCE_TIMING2_GDSP_OFFSET_MASK);
+	__raw_writel(reg_val, EPDC_TCE_TIMING2);
+
+	/* EPDC_TCE_TIMING3 */
+	reg_val =
+	    ((0 << EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET) &
+	     EPDC_TCE_TIMING3_GDOE_OFFSET_MASK)
+	    | ((1 << EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET) &
+	       EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK);
+	__raw_writel(reg_val, EPDC_TCE_TIMING3);
+
+	/*
+	 * EPDC_TCE_SDCFG
+	 * SDCLK_HOLD = 1
+	 * SDSHR = 1
+	 * NUM_CE = 1
+	 * SDDO_REFORMAT = FLIP_PIXELS
+	 * SDDO_INVERT = DISABLED
+	 * PIXELS_PER_CE = display horizontal resolution
+	 */
+	reg_val = EPDC_TCE_SDCFG_SDCLK_HOLD | EPDC_TCE_SDCFG_SDSHR
+	    | ((1 << EPDC_TCE_SDCFG_NUM_CE_OFFSET) & EPDC_TCE_SDCFG_NUM_CE_MASK)
+	    | EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS
+	    | ((pentry->x_res << EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET) &
+	       EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK);
+	__raw_writel(reg_val, EPDC_TCE_SDCFG);
+
+	/*
+	 * EPDC_TCE_GDCFG
+	 * GDRL = 1
+	 * GDOE_MODE = 0;
+	 * GDSP_MODE = 0;
+	 */
+	reg_val = EPDC_TCE_SDCFG_GDRL;
+	__raw_writel(reg_val, EPDC_TCE_GDCFG);
+
+	/*
+	 * EPDC_TCE_POLARITY
+	 * SDCE_POL = ACTIVE LOW
+	 * SDLE_POL = ACTIVE HIGH
+	 * SDOE_POL = ACTIVE HIGH
+	 * GDOE_POL = ACTIVE HIGH
+	 * GDSP_POL = ACTIVE LOW
+	 */
+	reg_val = EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH
+	    | EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH
+	    | EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH;
+	__raw_writel(reg_val, EPDC_TCE_POLARITY);
+
+	/* EPDC_IRQ_MASK */
+	__raw_writel(EPDC_IRQ_TCE_UNDERRUN_IRQ, EPDC_IRQ_MASK);
+
+	/*
+	 * EPDC_GPIO
+	 * PWRCOM = ?
+	 * PWRCTRL = ?
+	 * BDR = ?
+	 */
+	reg_val = ((0 << EPDC_GPIO_PWRCTRL_OFFSET) & EPDC_GPIO_PWRCTRL_MASK)
+	    | ((0 << EPDC_GPIO_BDR_OFFSET) & EPDC_GPIO_BDR_MASK);
+	__raw_writel(reg_val, EPDC_GPIO);
+}
+
+static void epdc_powerup(struct mxc_epdc_fb_data *fb_data)
+{
+	mutex_lock(&fb_data->power_mutex);
+
+	/*
+	 * If power down request is pending, clear
+	 * powering_down to cancel the request.
+	 */
+	if (fb_data->powering_down)
+		fb_data->powering_down = false;
+
+	if (fb_data->power_state == POWER_STATE_ON) {
+		mutex_unlock(&fb_data->power_mutex);
+		return;
+	}
+
+	dev_dbg(fb_data->dev, "EPDC Powerup\n");
+
+	/* Enable clocks to EPDC */
+	clk_enable(fb_data->epdc_clk_axi);
+	clk_enable(fb_data->epdc_clk_pix);
+
+	__raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_CLEAR);
+
+	/* Enable power to the EPD panel */
+	regulator_enable(fb_data->display_regulator);
+	regulator_enable(fb_data->vcom_regulator);
+
+	fb_data->power_state = POWER_STATE_ON;
+
+	mutex_unlock(&fb_data->power_mutex);
+}
+
+static void epdc_powerdown(struct mxc_epdc_fb_data *fb_data)
+{
+	mutex_lock(&fb_data->power_mutex);
+
+	/* If powering_down has been cleared, a powerup
+	 * request is pre-empting this powerdown request.
+	 */
+	if (!fb_data->powering_down
+		|| (fb_data->power_state == POWER_STATE_OFF)) {
+		mutex_unlock(&fb_data->power_mutex);
+		return;
+	}
+
+	dev_dbg(fb_data->dev, "EPDC Powerdown\n");
+
+	/* Disable power to the EPD panel */
+	regulator_disable(fb_data->vcom_regulator);
+	regulator_disable(fb_data->display_regulator);
+
+	/* Disable clocks to EPDC */
+	__raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_SET);
+	clk_disable(fb_data->epdc_clk_pix);
+	clk_disable(fb_data->epdc_clk_axi);
+
+	fb_data->power_state = POWER_STATE_OFF;
+	fb_data->powering_down = false;
+
+	mutex_unlock(&fb_data->power_mutex);
+}
+
+static void epdc_init_sequence(struct mxc_epdc_fb_data *fb_data)
+{
+	/* Initialize EPDC, passing pointer to EPDC registers */
+	epdc_init_settings(fb_data);
+	__raw_writel(fb_data->waveform_buffer_phys, EPDC_WVADDR);
+	__raw_writel(fb_data->working_buffer_phys, EPDC_WB_ADDR);
+	epdc_powerup(fb_data);
+	draw_mode0(fb_data);
+	epdc_powerdown(fb_data);
+}
+
+static int mxc_epdc_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
+{
+	u32 len;
+	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
+
+	if (offset < info->fix.smem_len) {
+		/* mapping framebuffer memory */
+		len = info->fix.smem_len - offset;
+		vma->vm_pgoff = (info->fix.smem_start + offset) >> PAGE_SHIFT;
+	} else
+		return -EINVAL;
+
+	len = PAGE_ALIGN(len);
+	if (vma->vm_end - vma->vm_start > len)
+		return -EINVAL;
+
+	/* make buffers bufferable */
+	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+	vma->vm_flags |= VM_IO | VM_RESERVED;
+
+	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+			    vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
+		dev_dbg(info->device, "mmap remap_pfn_range failed\n");
+		return -ENOBUFS;
+	}
+
+	return 0;
+}
+
+static int mxc_epdc_fb_setcolreg(u_int regno, u_int red, u_int green,
+				 u_int blue, u_int transp, struct fb_info *info)
+{
+	if (regno >= 256)	/* no. of hw registers */
+		return 1;
+	/*
+	 * Program hardware... do anything you want with transp
+	 */
+
+	/* grayscale works only partially under directcolor */
+	if (info->var.grayscale) {
+		/* grayscale = 0.30*R + 0.59*G + 0.11*B */
+		red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
+	}
+
+#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16)
+	switch (info->fix.visual) {
+	case FB_VISUAL_TRUECOLOR:
+	case FB_VISUAL_PSEUDOCOLOR:
+		red = CNVT_TOHW(red, info->var.red.length);
+		green = CNVT_TOHW(green, info->var.green.length);
+		blue = CNVT_TOHW(blue, info->var.blue.length);
+		transp = CNVT_TOHW(transp, info->var.transp.length);
+		break;
+	case FB_VISUAL_DIRECTCOLOR:
+		red = CNVT_TOHW(red, 8);	/* expect 8 bit DAC */
+		green = CNVT_TOHW(green, 8);
+		blue = CNVT_TOHW(blue, 8);
+		/* hey, there is bug in transp handling... */
+		transp = CNVT_TOHW(transp, 8);
+		break;
+	}
+#undef CNVT_TOHW
+	/* Truecolor has hardware independent palette */
+	if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+
+		if (regno >= 16)
+			return 1;
+
+		((u32 *) (info->pseudo_palette))[regno] =
+		    (red << info->var.red.offset) |
+		    (green << info->var.green.offset) |
+		    (blue << info->var.blue.offset) |
+		    (transp << info->var.transp.offset);
+	}
+	return 0;
+}
+
+static void adjust_coordinates(struct mxc_epdc_fb_data *fb_data, struct mxcfb_rect *update_region)
+{
+	struct fb_var_screeninfo *screeninfo = &fb_data->info.var;
+	u32 rotation = fb_data->info.var.rotate;
+	u32 temp;
+
+	switch (rotation) {
+	case FB_ROTATE_UR:
+		/* No adjustment needed */
+		break;
+	case FB_ROTATE_CW:
+		temp = update_region->top;
+		update_region->top = update_region->left;
+		update_region->left = screeninfo->yres - (temp + update_region->height);
+		temp = update_region->width;
+		update_region->width = update_region->height;
+		update_region->height = temp;
+		break;
+	case FB_ROTATE_UD:
+		update_region->top = screeninfo->yres - (update_region->top + update_region->height);
+		update_region->left = screeninfo->xres - (update_region->left + update_region->width);
+		break;
+	case FB_ROTATE_CCW:
+		temp = update_region->left;
+		update_region->left = update_region->top;
+		update_region->top = screeninfo->xres - (temp + update_region->width);
+		temp = update_region->width;
+		update_region->width = update_region->height;
+		update_region->height = temp;
+		break;
+	}
+}
+
+/*
+ * Set fixed framebuffer parameters based on variable settings.
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxc_epdc_fb_set_fix(struct fb_info *info)
+{
+	struct fb_fix_screeninfo *fix = &info->fix;
+	struct fb_var_screeninfo *var = &info->var;
+
+	fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+
+	fix->type = FB_TYPE_PACKED_PIXELS;
+	fix->accel = FB_ACCEL_NONE;
+	fix->visual = FB_VISUAL_TRUECOLOR;
+	fix->xpanstep = 1;
+	fix->ypanstep = 1;
+
+	return 0;
+}
+
+/*
+ * This routine actually sets the video mode. It's in here where we
+ * the hardware state info->par and fix which can be affected by the
+ * change in par. For this driver it doesn't do much.
+ *
+ */
+static int mxc_epdc_fb_set_par(struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	struct pxp_config_data *pxp_conf = &fb_data->pxp_conf;
+	struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
+	struct fb_var_screeninfo *screeninfo = &fb_data->info.var;
+	int i;
+	int ret;
+
+	/*
+	 * Update PxP config data (used to process FB regions for updates)
+	 * based on FB info and processing tasks required
+	 */
+
+	/* Initialize non-channel-specific PxP parameters */
+	proc_data->drect.left = proc_data->srect.left = 0;
+	proc_data->drect.top = proc_data->srect.top = 0;
+	proc_data->drect.width = proc_data->srect.width = screeninfo->xres;
+	proc_data->drect.height = proc_data->srect.height = screeninfo->yres;
+	proc_data->scaling = 0;
+	proc_data->hflip = 0;
+	proc_data->vflip = 0;
+	proc_data->rotate = screeninfo->rotate;
+	proc_data->bgcolor = 0;
+	proc_data->overlay_state = 0;
+	proc_data->lut_transform = PXP_LUT_NONE;
+
+	/*
+	 * configure S0 channel parameters
+	 * Parameters should match FB format/width/height
+	 */
+	if (screeninfo->grayscale) {
+		pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_GREY;
+		if (screeninfo->grayscale == GRAYSCALE_8BIT_INVERTED)
+			proc_data->lut_transform = PXP_LUT_INVERT;
+	} else {
+		switch (screeninfo->bits_per_pixel) {
+		case 16:
+			pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
+			break;
+		case 24:
+			pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB24;
+			break;
+		case 32:
+			pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB32;
+			break;
+		default:
+			pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
+			break;
+		}
+	}
+	pxp_conf->s0_param.width = screeninfo->xres;
+	pxp_conf->s0_param.height = screeninfo->yres;
+	pxp_conf->s0_param.color_key = -1;
+	pxp_conf->s0_param.color_key_enable = false;
+
+	/*
+	 * Initialize Output channel parameters
+	 * Output is Y-only greyscale
+	 * Output width/height will vary based on update region size
+	 */
+	pxp_conf->out_param.width = screeninfo->xres;
+	pxp_conf->out_param.height = screeninfo->yres;
+	pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_GREY;
+
+	/*
+	 * If HW not yet initialized, check to see if we are being sent
+	 * an initialization request.
+	 */
+	if (!fb_data->hw_ready) {
+		for (i = 0; i < NUM_PANELS; i++) {
+			/* Check resolution for a match with supported panel types */
+			if ((screeninfo->xres != panel_modes[i].xres) ||
+				(screeninfo->yres != panel_modes[i].yres))
+				continue;
+
+			/* Found a match - Grab timing params */
+			screeninfo->left_margin = panel_modes[i].left_margin;
+			screeninfo->right_margin = panel_modes[i].right_margin;
+			screeninfo->upper_margin = panel_modes[i].upper_margin;
+			screeninfo->lower_margin = panel_modes[i].lower_margin;
+			screeninfo->hsync_len = panel_modes[i].hsync_len;
+			screeninfo->vsync_len = panel_modes[i].vsync_len;
+
+			/* Initialize EPDC settings and init panel */
+			ret =
+			    mxc_epdc_fb_init_hw((struct fb_info *)fb_data);
+			if (ret) {
+				dev_err(fb_data->dev, "Failed to load panel waveform data\n");
+				return ret;
+			}
+
+			break;
+		}
+	}
+
+	mxc_epdc_fb_set_fix(info);
+
+	return 0;
+}
+
+static int mxc_epdc_fb_check_var(struct fb_var_screeninfo *var,
+				 struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+
+	if (!var->xres)
+		var->xres = 1;
+	if (!var->yres)
+		var->yres = 1;
+
+	if (var->xres_virtual < var->xoffset + var->xres)
+		var->xres_virtual = var->xoffset + var->xres;
+	if (var->yres_virtual < var->yoffset + var->yres)
+		var->yres_virtual = var->yoffset + var->yres;
+
+	if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
+	    (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8))
+		var->bits_per_pixel = default_bpp;
+
+	switch (var->bits_per_pixel) {
+	case 8:
+		if (var->grayscale != 0) {
+			/*
+			 * For 8-bit grayscale, R, G, and B offset are equal.
+			 *
+			 */
+			var->red.length = 8;
+			var->red.offset = 0;
+			var->red.msb_right = 0;
+
+			var->green.length = 8;
+			var->green.offset = 0;
+			var->green.msb_right = 0;
+
+			var->blue.length = 8;
+			var->blue.offset = 0;
+			var->blue.msb_right = 0;
+
+			var->transp.length = 0;
+			var->transp.offset = 0;
+			var->transp.msb_right = 0;
+		} else {
+			var->red.length = 3;
+			var->red.offset = 5;
+			var->red.msb_right = 0;
+
+			var->green.length = 3;
+			var->green.offset = 2;
+			var->green.msb_right = 0;
+
+			var->blue.length = 2;
+			var->blue.offset = 0;
+			var->blue.msb_right = 0;
+
+			var->transp.length = 0;
+			var->transp.offset = 0;
+			var->transp.msb_right = 0;
+		}
+		break;
+	case 16:
+		var->red.length = 5;
+		var->red.offset = 11;
+		var->red.msb_right = 0;
+
+		var->green.length = 6;
+		var->green.offset = 5;
+		var->green.msb_right = 0;
+
+		var->blue.length = 5;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 24:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 32:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 8;
+		var->transp.offset = 24;
+		var->transp.msb_right = 0;
+		break;
+	}
+
+	switch (var->rotate) {
+	case FB_ROTATE_UR:
+	case FB_ROTATE_UD:
+		var->xres = var->xres_virtual = fb_data->native_width;
+		var->yres = fb_data->native_height;
+		var->yres_virtual = var->yres * 2;
+		break;
+	case FB_ROTATE_CW:
+	case FB_ROTATE_CCW:
+		var->xres = var->xres_virtual = fb_data->native_height;
+		var->yres = fb_data->native_width;
+		var->yres_virtual = var->yres * 2;
+		break;
+	default:
+		/* Invalid rotation value */
+		var->rotate = 0;
+		dev_dbg(fb_data->dev, "Invalid rotation request\n");
+		return -EINVAL;
+	}
+
+	var->height = -1;
+	var->width = -1;
+
+	return 0;
+}
+
+static int mxc_epdc_fb_get_temp_index(struct mxc_epdc_fb_data *fb_data, int temp)
+{
+	int i;
+	int index = -1;
+
+	if (fb_data->trt_entries == 0) {
+		dev_err(fb_data->dev,
+			"No TRT exists...using default temp index\n");
+		return TEMP_USE_DEFAULT;
+	}
+
+	/* Search temperature ranges for a match */
+	for (i = 0; i < fb_data->trt_entries - 1; i++) {
+		if ((temp >= fb_data->temp_range_bounds[i])
+			&& (temp < fb_data->temp_range_bounds[i+1])) {
+			index = i;
+			break;
+		}
+	}
+
+	if (index < 0) {
+		dev_err(fb_data->dev,
+			"No TRT index match...using default temp index\n");
+		return TEMP_USE_DEFAULT;
+	}
+
+	dev_dbg(fb_data->dev, "Using temperature index %d\n", index);
+
+	return index;
+}
+
+static int mxc_epdc_fb_set_temperature(int temperature, struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	int temp_index;
+
+	if (temperature != TEMP_USE_AMBIENT) {
+		temp_index = mxc_epdc_fb_get_temp_index(fb_data, temperature);
+		epdc_set_temp(temp_index);
+	}
+
+	return 0;
+}
+
+static int mxc_epdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+
+	dev_dbg(fb_data->dev, "Setting auto update mode to %d\n", auto_mode);
+
+	if ((auto_mode == AUTO_UPDATE_MODE_AUTOMATIC_MODE)
+		|| (auto_mode == AUTO_UPDATE_MODE_REGION_MODE))
+		fb_data->auto_mode = auto_mode;
+	else {
+		dev_err(fb_data->dev, "Invalid auto update mode parameter.\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int mxc_epdc_fb_send_update(struct mxcfb_update_data *upd_data,
+				   struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	struct update_data_list *upd_data_list = NULL;
+	struct mxcfb_rect *screen_upd_region; /* Region on screen to update */
+	struct mxcfb_rect *src_upd_region; /* Region of src buffer for update */
+	struct mxcfb_rect pxp_upd_region;
+	u32 src_width;
+	unsigned long flags;
+	int i;
+	u32 offset_from_8, bytes_per_pixel;
+	u32 post_rotation_xcoord, post_rotation_ycoord, width_pxp_blocks;
+	u32 pxp_input_offs, pxp_output_offs, pxp_output_shift;
+	int adj_left, adj_top;
+	u32 hist_stat = 0;
+	int temp_index;
+	bool wait_for_power = false;
+
+	int ret;
+
+	/* Has EPDC HW been initialized? */
+	if (!fb_data->hw_ready) {
+		dev_err(fb_data->dev, "Display HW not properly initialized.  Aborting update.\n");
+		return -EPERM;
+	}
+
+	/* Check validity of update params */
+	if ((upd_data->update_mode != UPDATE_MODE_PARTIAL) &&
+		(upd_data->update_mode != UPDATE_MODE_FULL)) {
+		dev_err(fb_data->dev,
+			"Update mode 0x%x is invalid.  Aborting update.\n",
+			upd_data->update_mode);
+		return -EINVAL;
+	}
+	if ((upd_data->waveform_mode > 255) &&
+		(upd_data->waveform_mode != WAVEFORM_MODE_AUTO)) {
+		dev_err(fb_data->dev,
+			"Update waveform mode 0x%x is invalid.  Aborting update.\n",
+			upd_data->waveform_mode);
+		return -EINVAL;
+	}
+	if ((upd_data->update_region.left + upd_data->update_region.width > fb_data->info.var.xres) ||
+		(upd_data->update_region.top + upd_data->update_region.height > fb_data->info.var.yres)) {
+		dev_err(fb_data->dev,
+			"Update region is outside bounds of framebuffer.  Aborting update.\n");
+		return -EINVAL;
+	}
+	if (upd_data->use_alt_buffer &&
+		((upd_data->update_region.width != upd_data->alt_buffer_data.alt_update_region.width) ||
+		(upd_data->update_region.height != upd_data->alt_buffer_data.alt_update_region.height))) {
+		dev_err(fb_data->dev,
+			"Alternate update region dimensions must match screen update region dimensions.\n");
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&fb_data->queue_lock, flags);
+
+	/*
+	 * If we are waiting to go into suspend, or the FB is blanked,
+	 * we do not accept new updates
+	 */
+	if ((fb_data->waiting_for_idle) || (fb_data->blank != FB_BLANK_UNBLANK)) {
+		dev_dbg(fb_data->dev, "EPDC not active.  Update request abort.\n");
+		spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+		return -EPERM;
+	}
+
+	/*
+	 * Get available intermediate (PxP output) buffer to hold
+	 * processed update region
+	 */
+	if (list_empty(&fb_data->upd_buf_free_list->list)) {
+		dev_err(fb_data->dev, "No free intermediate buffers available.\n");
+		spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+		return -ENOMEM;
+	}
+
+	/* Grab first available buffer and delete it from the free list */
+	upd_data_list =
+	    list_entry(fb_data->upd_buf_free_list->list.next,
+		       struct update_data_list, list);
+
+	list_del_init(&upd_data_list->list);
+
+	/*
+	 * We can release lock on queues now
+	 * that we have grabbed the one we need
+	 */
+	spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+
+	/* copy update parameters to the current update data object */
+	memcpy(&upd_data_list->upd_data, upd_data,
+	       sizeof(struct mxcfb_update_data));
+	memcpy(&upd_data_list->upd_data.update_region, &upd_data->update_region,
+	       sizeof(struct mxcfb_rect));
+
+	/*
+	 * Hold on to original screen update region, which we
+	 * will ultimately use when telling EPDC where to update on panel
+	 */
+	screen_upd_region = &upd_data_list->upd_data.update_region;
+
+	/*
+	 * Gotta do a whole bunch of buffer ptr manipulation to
+	 * work around HW restrictions for PxP & EPDC
+	 */
+
+	/*
+	 * Are we using FB or an alternate (overlay)
+	 * buffer for source of update?
+	 */
+	if (upd_data->use_alt_buffer) {
+		src_width = upd_data->alt_buffer_data.width;
+		src_upd_region = &upd_data->alt_buffer_data.alt_update_region;
+	} else {
+		src_width = fb_data->info.var.xres;
+		src_upd_region = screen_upd_region;
+	}
+
+	/*
+	 * Compute buffer offset to account for
+	 * PxP limitation (must read 8x8 pixel blocks)
+	 */
+	offset_from_8 = src_upd_region->left & 0x7;
+	bytes_per_pixel = fb_data->info.var.bits_per_pixel/8;
+	if ((offset_from_8 * fb_data->info.var.bits_per_pixel/8 % 4) != 0) {
+		/* Leave a gap between PxP input addr and update region pixels */
+		pxp_input_offs =
+			(src_upd_region->top * src_width + src_upd_region->left)
+			* bytes_per_pixel & 0xFFFFFFFC;
+		/* Update region should change to reflect relative position to input ptr */
+		pxp_upd_region.top = 0;
+		pxp_upd_region.left = (offset_from_8 & 0x3) % bytes_per_pixel;
+	} else {
+		pxp_input_offs =
+			(src_upd_region->top * src_width + src_upd_region->left)
+			* bytes_per_pixel;
+		/* Update region should change to reflect relative position to input ptr */
+		pxp_upd_region.top = 0;
+		pxp_upd_region.left = 0;
+	}
+
+	/* Update region to meet 8x8 pixel requirement */
+	adj_left = pxp_upd_region.left & 0x7;
+	adj_top = pxp_upd_region.top & 0x7;
+	pxp_upd_region.width = ALIGN(src_upd_region->width + adj_left, 8);
+	pxp_upd_region.height = ALIGN(src_upd_region->height + adj_top, 8);
+	pxp_upd_region.top &= ~0x7;
+	pxp_upd_region.left &= ~0x7;
+
+	switch (fb_data->info.var.rotate) {
+	case FB_ROTATE_UR:
+	default:
+		post_rotation_xcoord = pxp_upd_region.left;
+		post_rotation_ycoord = pxp_upd_region.top;
+		width_pxp_blocks = pxp_upd_region.width;
+		break;
+	case FB_ROTATE_CW:
+		width_pxp_blocks = pxp_upd_region.height;
+		post_rotation_xcoord = width_pxp_blocks - src_upd_region->height;
+		post_rotation_ycoord = pxp_upd_region.left;
+		break;
+	case FB_ROTATE_UD:
+		width_pxp_blocks = pxp_upd_region.width;
+		post_rotation_xcoord = width_pxp_blocks - src_upd_region->width - pxp_upd_region.left;
+		post_rotation_ycoord = pxp_upd_region.height - src_upd_region->height - pxp_upd_region.top;
+		break;
+	case FB_ROTATE_CCW:
+		width_pxp_blocks = pxp_upd_region.height;
+		post_rotation_xcoord = pxp_upd_region.top;
+		post_rotation_ycoord = pxp_upd_region.width - src_upd_region->width - pxp_upd_region.left;
+		break;
+	}
+
+	pxp_output_offs = post_rotation_ycoord * width_pxp_blocks
+		+ post_rotation_xcoord;
+
+	pxp_output_shift = ALIGN(pxp_output_offs, 8) - pxp_output_offs;
+
+	upd_data_list->epdc_offs = pxp_output_offs + pxp_output_shift;
+
+	/* Source address either comes from alternate buffer
+	   provided in update data, or from the framebuffer. */
+	if (upd_data->use_alt_buffer)
+		sg_dma_address(&fb_data->sg[0]) =
+			upd_data->alt_buffer_data.phys_addr + pxp_input_offs;
+	else {
+		sg_dma_address(&fb_data->sg[0]) =
+			fb_data->info.fix.smem_start + fb_data->fb_offset
+			+ pxp_input_offs;
+		sg_set_page(&fb_data->sg[0],
+			virt_to_page(fb_data->info.screen_base),
+			fb_data->info.fix.smem_len,
+			offset_in_page(fb_data->info.screen_base));
+	}
+
+	/* Update sg[1] to point to output of PxP proc task */
+	sg_dma_address(&fb_data->sg[1]) = upd_data_list->phys_addr + pxp_output_offs;
+	sg_set_page(&fb_data->sg[1], virt_to_page(upd_data_list->virt_addr),
+		    upd_data_list->size,
+		    offset_in_page(upd_data_list->virt_addr));
+
+	mutex_lock(&fb_data->pxp_mutex);
+
+	/* This is a blocking call, so upon return PxP tx should be done */
+	ret = pxp_process_update(fb_data, &pxp_upd_region);
+	if (ret) {
+		dev_err(fb_data->dev, "Unable to submit PxP update task.\n");
+		mutex_unlock(&fb_data->pxp_mutex);
+		return ret;
+	}
+
+	mutex_unlock(&fb_data->pxp_mutex);
+
+	/* If needed, enable EPDC HW while ePxP is processing */
+	if ((fb_data->power_state == POWER_STATE_OFF)
+		|| fb_data->powering_down) {
+		wait_for_power = true;
+		epdc_powerup(fb_data);
+	}
+
+	mutex_lock(&fb_data->pxp_mutex);
+
+	/* This is a blocking call, so upon return PxP tx should be done */
+	ret = pxp_complete_update(fb_data, &hist_stat);
+	if (ret) {
+		dev_err(fb_data->dev, "Unable to complete PxP update task.\n");
+		mutex_unlock(&fb_data->pxp_mutex);
+		return ret;
+	}
+
+	mutex_unlock(&fb_data->pxp_mutex);
+
+	/* Grab lock for queue manipulation and update submission */
+	spin_lock_irqsave(&fb_data->queue_lock, flags);
+
+	/* Update coordinates for rotation */
+	adjust_coordinates(fb_data, &upd_data_list->upd_data.update_region);
+
+	/* Update waveform mode from PxP histogram results */
+	if (upd_data_list->upd_data.waveform_mode == WAVEFORM_MODE_AUTO) {
+		if (hist_stat & 0x1)
+			upd_data_list->upd_data.waveform_mode =
+				fb_data->wv_modes.mode_du;
+		else if (hist_stat & 0x2)
+			upd_data_list->upd_data.waveform_mode =
+				fb_data->wv_modes.mode_gc4;
+		else if (hist_stat & 0x4)
+			upd_data_list->upd_data.waveform_mode =
+				fb_data->wv_modes.mode_gc8;
+		else if (hist_stat & 0x8)
+			upd_data_list->upd_data.waveform_mode =
+				fb_data->wv_modes.mode_gc16;
+		else
+			upd_data_list->upd_data.waveform_mode =
+				fb_data->wv_modes.mode_gc32;
+
+		/* Pass selected waveform mode back to user */
+		upd_data->waveform_mode = upd_data_list->upd_data.waveform_mode;
+
+		dev_dbg(fb_data->dev, "hist_stat = 0x%x, new waveform = 0x%x\n",
+			hist_stat, upd_data_list->upd_data.waveform_mode);
+	}
+
+	/* If marker specified, associate it with a completion */
+	if (upd_data->update_marker != 0) {
+		/* Find available update marker and set it up */
+		for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) {
+			/* Marker value set to 0 signifies it is not currently in use */
+			if (fb_data->update_marker_array[i].update_marker == 0) {
+				fb_data->update_marker_array[i].update_marker = upd_data->update_marker;
+				init_completion(&fb_data->update_marker_array[i].update_completion);
+				upd_data_list->upd_marker_data = &fb_data->update_marker_array[i];
+				break;
+			}
+		}
+	} else {
+		if (upd_data_list->upd_marker_data)
+			upd_data_list->upd_marker_data->update_marker = 0;
+	}
+
+	upd_data_list->is_collision = false;
+
+	/*
+	 * Is the working buffer idle?
+	 * If either the working buffer is busy, or there are no LUTs available,
+	 * then we return and let the ISR handle the update later
+	 */
+	if ((fb_data->cur_update != NULL) || !epdc_any_luts_available()) {
+		/* Add processed Y buffer to update list */
+		list_add_tail(&upd_data_list->list,
+			      &fb_data->upd_buf_queue->list);
+
+		/* Return and allow the udpate to be submitted by the ISR. */
+		spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+		return 0;
+	}
+
+	/* Save current update */
+	fb_data->cur_update = upd_data_list;
+
+	/* LUTs are available, so we get one here */
+	upd_data_list->lut_num = epdc_get_next_lut();
+
+	/* Associate LUT with update marker */
+	if (upd_data_list->upd_marker_data)
+		if (upd_data_list->upd_marker_data->update_marker != 0)
+			upd_data_list->upd_marker_data->lut_num = upd_data_list->lut_num;
+
+	/* Mark LUT as containing new update */
+	fb_data->lut_update_type[upd_data_list->lut_num] = LUT_UPDATE_NEW;
+
+	/* Clear status and Enable LUT complete and WB complete IRQs */
+	epdc_working_buf_intr(true);
+	epdc_lut_complete_intr(fb_data->cur_update->lut_num, true);
+
+	/* Program EPDC update to process buffer */
+	epdc_set_update_addr(upd_data_list->phys_addr + upd_data_list->epdc_offs);
+	epdc_set_update_coord(screen_upd_region->left, screen_upd_region->top);
+	epdc_set_update_dimensions(screen_upd_region->width, screen_upd_region->height);
+	if (upd_data_list->upd_data.temp != TEMP_USE_AMBIENT) {
+		temp_index = mxc_epdc_fb_get_temp_index(fb_data, upd_data_list->upd_data.temp);
+		epdc_set_temp(temp_index);
+	}
+	epdc_submit_update(upd_data_list->lut_num,
+			   upd_data_list->upd_data.waveform_mode,
+			   upd_data_list->upd_data.update_mode, false, 0);
+
+	spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+
+	return 0;
+}
+
+static int mxc_epdc_fb_wait_update_complete(u32 update_marker,
+					    struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	int ret;
+	int i;
+
+	/* 0 is an invalid update_marker value */
+	if (update_marker == 0)
+		return -EINVAL;
+
+	/* Wait for completion associated with update_marker requested */
+	for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) {
+		if (fb_data->update_marker_array[i].update_marker == update_marker) {
+			dev_dbg(fb_data->dev, "Waiting for marker %d\n", update_marker);
+			ret = wait_for_completion_timeout(&fb_data->update_marker_array[i].update_completion, msecs_to_jiffies(5000));
+			if (!ret)
+				dev_err(fb_data->dev, "Timed out waiting for update completion\n");
+
+			dev_dbg(fb_data->dev, "marker %d signalled!\n", update_marker);
+
+			/* Reset marker so it can be reused */
+			fb_data->update_marker_array[i].update_marker = 0;
+
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static int mxc_epdc_fb_ioctl(struct fb_info *info, unsigned int cmd,
+			     unsigned long arg)
+{
+	void __user *argp = (void __user *)arg;
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	struct mxcfb_waveform_modes modes;
+	int temperature;
+	u32 auto_mode = 0;
+	struct mxcfb_update_data upd_data;
+	u32 update_marker = 0;
+	int ret = -EINVAL;
+
+	switch (cmd) {
+	case MXCFB_SET_WAVEFORM_MODES:
+		if (!copy_from_user(&modes, argp, sizeof(modes))) {
+			memcpy(&fb_data->wv_modes, &modes, sizeof(modes));
+			ret = 0;
+		}
+		break;
+	case MXCFB_SET_TEMPERATURE:
+		if (!get_user(temperature, (int32_t __user *) arg))
+			ret =
+			    mxc_epdc_fb_set_temperature(temperature,
+							info);
+		break;
+	case MXCFB_SET_AUTO_UPDATE_MODE:
+		if (!get_user(auto_mode, (__u32 __user *) arg))
+			ret =
+			    mxc_epdc_fb_set_auto_update(auto_mode, info);
+		break;
+	case MXCFB_SEND_UPDATE:
+		if (!copy_from_user(&upd_data, argp, sizeof(upd_data))) {
+			ret = mxc_epdc_fb_send_update(&upd_data, info);
+			if (ret == 0 && copy_to_user(argp, &upd_data, sizeof(upd_data)))
+				ret = -EFAULT;
+		} else {
+			ret = -EFAULT;
+		}
+
+		break;
+	case MXCFB_WAIT_FOR_UPDATE_COMPLETE:
+		if (!get_user(update_marker, (__u32 __user *) arg))
+			ret =
+			    mxc_epdc_fb_wait_update_complete(update_marker,
+							     info);
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+static void mxc_epdc_fb_update_pages(struct mxc_epdc_fb_data *fb_data,
+				     u16 y1, u16 y2)
+{
+	struct mxcfb_update_data update;
+
+	/* Do partial screen update, Update full horizontal lines */
+	update.update_region.left = 0;
+	update.update_region.width = fb_data->info.var.xres;
+	update.update_region.top = y1;
+	update.update_region.height = y2 - y1;
+	update.waveform_mode = WAVEFORM_MODE_AUTO;
+	update.update_mode = UPDATE_MODE_FULL;
+	update.update_marker = 0;
+	update.temp = TEMP_USE_AMBIENT;
+	update.use_alt_buffer = false;
+
+	mxc_epdc_fb_send_update(&update, &fb_data->info);
+}
+
+/* this is called back from the deferred io workqueue */
+static void mxc_epdc_fb_deferred_io(struct fb_info *info,
+				    struct list_head *pagelist)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	struct page *page;
+	unsigned long beg, end;
+	int y1, y2, miny, maxy;
+
+	if (fb_data->auto_mode != AUTO_UPDATE_MODE_AUTOMATIC_MODE)
+		return;
+
+	miny = INT_MAX;
+	maxy = 0;
+	list_for_each_entry(page, pagelist, lru) {
+		beg = page->index << PAGE_SHIFT;
+		end = beg + PAGE_SIZE - 1;
+		y1 = beg / info->fix.line_length;
+		y2 = end / info->fix.line_length;
+		if (y2 >= info->var.yres)
+			y2 = info->var.yres - 1;
+		if (miny > y1)
+			miny = y1;
+		if (maxy < y2)
+			maxy = y2;
+	}
+
+	mxc_epdc_fb_update_pages(fb_data, miny, maxy);
+}
+
+static void mxc_epdc_fb_disable(struct mxc_epdc_fb_data *fb_data)
+{
+	unsigned long flags;
+	/* Grab queue lock to prevent any new updates from being submitted */
+
+	spin_lock_irqsave(&fb_data->queue_lock, flags);
+
+	/* If any updates in flight, we must wait for them to complete */
+	if (!(list_empty(&fb_data->upd_buf_collision_list->list) &&
+		list_empty(&fb_data->upd_buf_queue->list) &&
+		(fb_data->cur_update == NULL))) {
+		/* Initialize event signalling updates are done */
+		init_completion(&fb_data->updates_done);
+		fb_data->waiting_for_idle = true;
+
+		spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+		/* Wait for any currently active updates to complete */
+		wait_for_completion_timeout(&fb_data->updates_done, msecs_to_jiffies(2000));
+		spin_lock_irqsave(&fb_data->queue_lock, flags);
+		fb_data->waiting_for_idle = false;
+	}
+
+	spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+}
+
+static int mxc_epdc_fb_blank(int blank, struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+
+	dev_dbg(fb_data->dev, "blank = %d\n", blank);
+
+	if (fb_data->blank == blank)
+		return 0;
+
+	fb_data->blank = blank;
+
+	switch (blank) {
+	case FB_BLANK_POWERDOWN:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_NORMAL:
+		mxc_epdc_fb_disable(fb_data);
+		break;
+	case FB_BLANK_UNBLANK:
+		epdc_powerup(fb_data);
+		mxc_epdc_fb_set_par(info);
+		break;
+	}
+	return 0;
+}
+
+static int mxc_epdc_fb_pan_display(struct fb_var_screeninfo *var,
+				   struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	struct mxcfb_update_data update;
+	int ret = 0;
+	u_int y_bottom;
+
+	dev_dbg(info->device, "%s: var->xoffset %d, info->var.xoffset %d\n",
+		 __func__, var->xoffset, info->var.xoffset);
+	/* check if var is valid; also, xpan is not supported */
+	if (!var || (var->xoffset != info->var.xoffset) ||
+	    (var->yoffset + var->yres > var->yres_virtual)) {
+		dev_dbg(info->device, "x panning not supported\n");
+		return -EINVAL;
+	}
+
+	if ((info->var.xoffset == var->xoffset) &&
+	    (info->var.yoffset == var->yoffset))
+		return 0;	/* No change, do nothing */
+
+	y_bottom = var->yoffset;
+
+	if (!(var->vmode & FB_VMODE_YWRAP))
+		y_bottom += var->yres;
+
+	if (y_bottom > info->var.yres_virtual)
+		return -EINVAL;
+
+	fb_data->fb_offset = (var->yoffset * var->xres_virtual + var->xoffset)
+		* (var->bits_per_pixel) / 8;
+
+	/* Update to new view of FB */
+	update.update_region.left = 0;
+	update.update_region.width = fb_data->info.var.xres;
+	update.update_region.top = 0;
+	update.update_region.height = fb_data->info.var.yres;
+	update.waveform_mode = WAVEFORM_MODE_AUTO;
+	update.update_mode = UPDATE_MODE_FULL;
+	update.update_marker = PAN_UPDATE_MARKER;
+	update.temp = TEMP_USE_AMBIENT;
+	update.use_alt_buffer = false;
+
+	mxc_epdc_fb_send_update(&update, &fb_data->info);
+
+	/* Block on initial update */
+	ret = mxc_epdc_fb_wait_update_complete(update.update_marker, info);
+	if (ret < 0)
+		dev_err(fb_data->dev,
+			"Wait for update complete failed.  Error = 0x%x", ret);
+
+	info->var.xoffset = var->xoffset;
+	info->var.yoffset = var->yoffset;
+
+	if (var->vmode & FB_VMODE_YWRAP)
+		info->var.vmode |= FB_VMODE_YWRAP;
+	else
+		info->var.vmode &= ~FB_VMODE_YWRAP;
+
+	return ret;
+}
+
+static struct fb_ops mxc_epdc_fb_ops = {
+	.owner = THIS_MODULE,
+	.fb_check_var = mxc_epdc_fb_check_var,
+	.fb_set_par = mxc_epdc_fb_set_par,
+	.fb_setcolreg = mxc_epdc_fb_setcolreg,
+	.fb_pan_display = mxc_epdc_fb_pan_display,
+	.fb_ioctl = mxc_epdc_fb_ioctl,
+	.fb_mmap = mxc_epdc_fb_mmap,
+	.fb_blank = mxc_epdc_fb_blank,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+};
+
+static struct fb_deferred_io mxc_epdc_fb_defio = {
+	.delay = HZ / 2,
+	.deferred_io = mxc_epdc_fb_deferred_io,
+};
+
+static void epdc_done_work_func(struct work_struct *work)
+{
+	struct mxc_epdc_fb_data *fb_data =
+		container_of(work, struct mxc_epdc_fb_data, epdc_done_work);
+	epdc_powerdown(fb_data);
+}
+
+static bool is_free_list_full(struct mxc_epdc_fb_data *fb_data)
+{
+	int count = 0;
+	struct update_data_list *plist;
+
+	/* Count buffers in free buffer list */
+	list_for_each_entry(plist, &fb_data->upd_buf_free_list->list, list)
+		count++;
+
+	/* Check to see if all buffers are in this list */
+	if (count == EPDC_MAX_NUM_UPDATES)
+		return true;
+	else
+		return false;
+}
+
+static irqreturn_t mxc_epdc_irq_handler(int irq, void *dev_id)
+{
+	struct mxc_epdc_fb_data *fb_data = dev_id;
+	struct update_data_list *collision_update;
+	struct mxcfb_rect *next_upd_region;
+	unsigned long flags;
+	int temp_index;
+	u32 luts_completed_mask;
+	u32 temp_mask;
+	u32 lut;
+	bool ignore_collision = false;
+	int i, j;
+
+	/*
+	 * If we just completed one-time panel init, bypass
+	 * queue handling, clear interrupt and return
+	 */
+	if (fb_data->in_init) {
+		if (epdc_is_working_buffer_complete()) {
+			epdc_working_buf_intr(false);
+			epdc_clear_working_buf_irq();
+			dev_dbg(fb_data->dev, "Cleared WB for init update\n");
+		}
+
+		if (epdc_is_lut_complete(0)) {
+			epdc_lut_complete_intr(0, false);
+			epdc_clear_lut_complete_irq(0);
+			fb_data->in_init = false;
+			dev_dbg(fb_data->dev, "Cleared LUT complete for init update\n");
+		}
+
+		return IRQ_HANDLED;
+	}
+
+	if (!(__raw_readl(EPDC_IRQ_MASK) & __raw_readl(EPDC_IRQ)))
+		return IRQ_HANDLED;
+
+	if (__raw_readl(EPDC_IRQ) & EPDC_IRQ_TCE_UNDERRUN_IRQ) {
+		dev_err(fb_data->dev, "TCE underrun!  Panel may lock up.\n");
+		return IRQ_HANDLED;
+	}
+
+	/* Protect access to buffer queues and to update HW */
+	spin_lock_irqsave(&fb_data->queue_lock, flags);
+
+	/* Free any LUTs that have completed */
+	luts_completed_mask = 0;
+	for (i = 0; i < EPDC_NUM_LUTS; i++) {
+		if (!epdc_is_lut_complete(i))
+			continue;
+
+		dev_dbg(fb_data->dev, "\nLUT %d completed\n", i);
+
+		/* Disable IRQ for completed LUT */
+		epdc_lut_complete_intr(i, false);
+
+		/*
+		 * Go through all updates in the collision list and
+		 * unmask any updates that were colliding with
+		 * the completed LUT.
+		 */
+		list_for_each_entry(collision_update,
+				    &fb_data->upd_buf_collision_list->
+				    list, list) {
+			collision_update->collision_mask =
+			    collision_update->collision_mask & ~(1 << i);
+		}
+
+		epdc_clear_lut_complete_irq(i);
+
+		luts_completed_mask |= 1 << i;
+
+		fb_data->lut_update_type[i] = LUT_UPDATE_NONE;
+
+		/* Signal completion if anyone waiting on this LUT */
+		for (j = 0; j < EPDC_MAX_NUM_UPDATES; j++) {
+			if (fb_data->update_marker_array[j].lut_num != i)
+				continue;
+
+			/* Signal completion of update */
+			dev_dbg(fb_data->dev,
+				"Signaling marker %d\n",
+				fb_data->update_marker_array[j].update_marker);
+			complete(&fb_data->update_marker_array[j].update_completion);
+			/* Ensure this doesn't get signaled again inadvertently */
+			fb_data->update_marker_array[j].lut_num = INVALID_LUT;
+		}
+	}
+
+	/* Check to see if all updates have completed */
+	if (is_free_list_full(fb_data) &&
+		(fb_data->cur_update == NULL) &&
+		!epdc_any_luts_active()) {
+
+#ifndef NO_POWERDOWN
+		/*
+		 * Set variable to prevent overlapping
+		  * enable/disable requests
+		  */
+		fb_data->powering_down = true;
+
+		/* Schedule task to disable EPDC HW until next update */
+		schedule_work(&fb_data->epdc_done_work);
+#endif
+
+		if (fb_data->waiting_for_idle)
+			complete(&fb_data->updates_done);
+	}
+
+	/* Is Working Buffer busy? */
+	if (epdc_is_working_buffer_busy()) {
+		/* Can't submit another update until WB is done */
+		spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+		return IRQ_HANDLED;
+	}
+
+	/*
+	 * Were we waiting on working buffer?
+	 * If so, update queues and check for collisions
+	 */
+	if (fb_data->cur_update != NULL) {
+		dev_dbg(fb_data->dev, "\nWorking buffer completed\n");
+
+		/* Was there a collision? */
+		if (epdc_is_collision()) {
+			/* Check list of colliding LUTs, and add to our collision mask */
+			fb_data->cur_update->collision_mask =
+			    epdc_get_colliding_luts();
+
+			dev_dbg(fb_data->dev, "\nCollision mask = 0x%x\n",
+			       epdc_get_colliding_luts());
+
+			/* Clear collisions that just completed */
+			fb_data->cur_update->collision_mask &= ~luts_completed_mask;
+
+			/*
+			 * If this is a re-collision, AND we re-collide
+			 * with only new updates, then we don't want
+			 * to re-submit it again.
+			 */
+			if (fb_data->cur_update->is_collision) {
+				/*
+				 * Check whether collided LUTs are
+				 * new updates or resubmitted collisions
+				 */
+				temp_mask = fb_data->cur_update->collision_mask;
+				lut = 0;
+				while (temp_mask != 0) {
+					if ((temp_mask & 0x1) &&
+						(fb_data->lut_update_type[lut] == LUT_UPDATE_NEW)) {
+						dev_dbg(fb_data->dev, "Ignoring collision with new update.\n");
+						ignore_collision = true;
+						break;
+					}
+					lut++;
+					temp_mask = temp_mask >> 1;
+				}
+			}
+
+			if (ignore_collision) {
+				/* Add to free buffer list */
+				list_add_tail(&fb_data->cur_update->list,
+					 &fb_data->upd_buf_free_list->list);
+			} else {
+				/*
+				 * If update has a marker, clear the LUT, since we
+				 * don't want to signal that it is complete.
+				 */
+				if (fb_data->cur_update->upd_marker_data)
+					if (fb_data->cur_update->upd_marker_data->update_marker != 0)
+						fb_data->cur_update->upd_marker_data->lut_num = INVALID_LUT;
+
+				fb_data->cur_update->is_collision = true;
+
+				/* Move to collision list */
+				list_add_tail(&fb_data->cur_update->list,
+					 &fb_data->upd_buf_collision_list->list);
+			}
+		} else {
+			/* Add to free buffer list */
+			list_add_tail(&fb_data->cur_update->list,
+				 &fb_data->upd_buf_free_list->list);
+		}
+		/* Clear current update */
+		fb_data->cur_update = NULL;
+
+		/* Clear IRQ for working buffer */
+		epdc_working_buf_intr(false);
+		epdc_clear_working_buf_irq();
+	}
+
+	/* Check to see if any LUTs are free */
+	if (!epdc_any_luts_available()) {
+		dev_dbg(fb_data->dev, "No luts available.\n");
+		spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+		return IRQ_HANDLED;
+	}
+
+	/*
+	 * Are any of our collision updates able to go now?
+	 * Go through all updates in the collision list and check to see
+	 * if the collision mask has been fully cleared
+	 */
+	list_for_each_entry(collision_update,
+			    &fb_data->upd_buf_collision_list->list, list) {
+
+		if (collision_update->collision_mask != 0)
+			continue;
+
+		dev_dbg(fb_data->dev, "A collision update is ready to go!\n");
+		/*
+		 * We have a collision cleared, so select it
+		 * and we will retry the update
+		 */
+		fb_data->cur_update = collision_update;
+		list_del_init(&fb_data->cur_update->list);
+		break;
+	}
+
+	/*
+	 * If we didn't find a collision update ready to go,
+	 * we try to grab one from the update queue
+	 */
+	if (fb_data->cur_update == NULL) {
+		/* Is update list empty? */
+		if (list_empty(&fb_data->upd_buf_queue->list)) {
+			dev_dbg(fb_data->dev, "No pending updates.\n");
+
+			/* No updates pending, so we are done */
+			spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+			return IRQ_HANDLED;
+		} else {
+			dev_dbg(fb_data->dev, "Found a pending update!\n");
+
+			/* Process next item in update list */
+			fb_data->cur_update =
+			    list_entry(fb_data->upd_buf_queue->list.next,
+				       struct update_data_list, list);
+			list_del_init(&fb_data->cur_update->list);
+		}
+	}
+
+	/* LUTs are available, so we get one here */
+	fb_data->cur_update->lut_num = epdc_get_next_lut();
+
+	/* Associate LUT with update marker */
+	if ((fb_data->cur_update->upd_marker_data)
+		&& (fb_data->cur_update->upd_marker_data->update_marker != 0))
+		fb_data->cur_update->upd_marker_data->lut_num =
+						fb_data->cur_update->lut_num;
+
+	/* Mark LUT as containing new update */
+	if (fb_data->cur_update->is_collision)
+		fb_data->lut_update_type[fb_data->cur_update->lut_num] = LUT_UPDATE_COLLISION;
+	else
+		fb_data->lut_update_type[fb_data->cur_update->lut_num] = LUT_UPDATE_NEW;
+
+	/* Enable Collision and WB complete IRQs */
+	epdc_working_buf_intr(true);
+	epdc_lut_complete_intr(fb_data->cur_update->lut_num, true);
+
+	/* Program EPDC update to process buffer */
+	next_upd_region = &fb_data->cur_update->upd_data.update_region;
+	if (fb_data->cur_update->upd_data.temp != TEMP_USE_AMBIENT) {
+		temp_index = mxc_epdc_fb_get_temp_index(fb_data, fb_data->cur_update->upd_data.temp);
+		epdc_set_temp(temp_index);
+	}
+	epdc_set_update_addr(fb_data->cur_update->phys_addr + fb_data->cur_update->epdc_offs);
+	epdc_set_update_coord(next_upd_region->left, next_upd_region->top);
+	epdc_set_update_dimensions(next_upd_region->width,
+				   next_upd_region->height);
+	epdc_submit_update(fb_data->cur_update->lut_num,
+			   fb_data->cur_update->upd_data.waveform_mode,
+			   fb_data->cur_update->upd_data.update_mode, false, 0);
+
+	/* Release buffer queues */
+	spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+static void draw_mode0(struct mxc_epdc_fb_data *fb_data)
+{
+	u32 *upd_buf_ptr;
+	int i;
+
+	upd_buf_ptr = (u32 *)fb_data->info.screen_base;
+
+	epdc_working_buf_intr(true);
+	epdc_lut_complete_intr(0, true);
+	fb_data->in_init = true;
+
+	/* Program EPDC update to process buffer */
+	epdc_set_update_addr(fb_data->phys_start);
+	epdc_set_update_coord(0, 0);
+	epdc_set_update_dimensions(fb_data->info.var.xres,
+				   fb_data->info.var.yres);
+	epdc_submit_update(0, fb_data->wv_modes.mode_init, UPDATE_MODE_FULL, true, 0xFF);
+
+	dev_dbg(fb_data->dev, "Mode0 update - Waiting for LUT to complete...\n");
+
+	/* Will timeout after ~4-5 seconds */
+
+	for (i = 0; i < 40; i++) {
+		if (!epdc_is_lut_active(0)) {
+			dev_dbg(fb_data->dev, "Mode0 init complete\n");
+			return;
+		}
+		msleep(100);
+	}
+
+	dev_err(fb_data->dev, "Mode0 init failed!\n");
+
+	return;
+}
+
+static int mxc_epdc_fb_init_hw(struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	u32 wv_buf_size;
+	const struct firmware *fw;
+	struct mxcfb_update_data update;
+	struct mxcfb_waveform_data_file *wv_file;
+	int wv_data_offs;
+	int ret;
+	int i;
+
+	ret = request_firmware(&fw, "imx/epdc.fw", fb_data->dev);
+	if (ret) {
+		printk(KERN_ERR "Failed to load image imx/epdc.ihex err %d\n",
+		       ret);
+		return ret;
+	}
+
+	wv_file = (struct mxcfb_waveform_data_file *)fw->data;
+
+	/* Get size and allocate temperature range table */
+	fb_data->trt_entries = wv_file->wdh.trc + 1;
+	fb_data->temp_range_bounds = kzalloc(fb_data->trt_entries, GFP_KERNEL);
+
+	for (i = 0; i < fb_data->trt_entries; i++)
+		dev_dbg(fb_data->dev, "trt entry #%d = 0x%x\n", i, *((u8 *)&wv_file->data + i));
+
+	/* Copy TRT data */
+	memcpy(fb_data->temp_range_bounds, &wv_file->data, fb_data->trt_entries);
+
+	/* Get offset and size for waveform data */
+	wv_data_offs = sizeof(wv_file->wdh) + fb_data->trt_entries + 1;
+	wv_buf_size = fw->size - wv_data_offs;
+
+	/* Allocate memory for waveform data */
+	fb_data->waveform_buffer_virt = dma_alloc_coherent(fb_data->dev, wv_buf_size,
+						  &fb_data->waveform_buffer_phys,
+						  GFP_DMA);
+	if (fb_data->waveform_buffer_virt == NULL) {
+		dev_err(fb_data->dev, "Can't allocate mem for waveform!\n");
+		ret = -ENOMEM;
+	}
+
+	memcpy(fb_data->waveform_buffer_virt, (u8 *)(fw->data) + wv_data_offs, wv_buf_size);
+	check_waveform((u32 *)(fw->data + wv_data_offs),
+		fb_data->waveform_buffer_virt, wv_buf_size / 4);
+
+	release_firmware(fw);
+
+	/* Enable clocks to access EPDC regs */
+	clk_enable(fb_data->epdc_clk_axi);
+
+	/* Enable pix clk for EPDC */
+	clk_enable(fb_data->epdc_clk_pix);
+	clk_set_rate(fb_data->epdc_clk_pix, 17700000);
+
+	epdc_init_sequence(fb_data);
+
+	/* Enable clocks to access EPDC regs */
+	clk_disable(fb_data->epdc_clk_axi);
+	clk_disable(fb_data->epdc_clk_pix);
+
+	fb_data->hw_ready = true;
+
+	update.update_region.left = 0;
+	update.update_region.width = info->var.xres;
+	update.update_region.top = 0;
+	update.update_region.height = info->var.yres;
+	update.update_mode = UPDATE_MODE_FULL;
+	update.waveform_mode = WAVEFORM_MODE_AUTO;
+	update.update_marker = INIT_UPDATE_MARKER;
+	update.temp = TEMP_USE_AMBIENT;
+	update.use_alt_buffer = false;
+
+	mxc_epdc_fb_send_update(&update, info);
+
+	/* Block on initial update */
+	ret = mxc_epdc_fb_wait_update_complete(update.update_marker, info);
+	if (ret < 0)
+		dev_err(fb_data->dev,
+			"Wait for update complete failed.  Error = 0x%x", ret);
+
+	return 0;
+}
+
+static ssize_t store_update(struct device *device,
+			     struct device_attribute *attr,
+			     const char *buf, size_t count)
+{
+	struct mxcfb_update_data update;
+	struct fb_info *info = dev_get_drvdata(device);
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+
+	if (strncmp(buf, "direct", 6) == 0)
+		update.waveform_mode = fb_data->wv_modes.mode_du;
+	else if (strncmp(buf, "gc16", 4) == 0)
+		update.waveform_mode = fb_data->wv_modes.mode_gc16;
+	else if (strncmp(buf, "gc4", 3) == 0)
+		update.waveform_mode = fb_data->wv_modes.mode_gc4;
+
+	/* Now, request full screen update */
+	update.update_region.left = 0;
+	update.update_region.width = info->var.xres;
+	update.update_region.top = 0;
+	update.update_region.height = info->var.yres;
+	update.update_mode = UPDATE_MODE_FULL;
+	update.temp = TEMP_USE_AMBIENT;
+	update.update_marker = 0;
+	update.use_alt_buffer = false;
+
+	mxc_epdc_fb_send_update(&update, info);
+
+	return count;
+}
+
+static struct device_attribute fb_attrs[] = {
+	__ATTR(update, S_IRUGO|S_IWUSR, NULL, store_update),
+};
+
+int __devinit mxc_epdc_fb_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct mxc_epdc_fb_data *fb_data;
+	struct resource *res;
+	struct fb_info *info;
+	struct mxc_epdc_platform_fb_data *pdata;
+	struct mxc_epdc_platform_fb_entry *pentry;
+	struct pxp_config_data *pxp_conf;
+	struct pxp_proc_data *proc_data;
+	struct scatterlist *sg;
+	struct update_data_list *upd_list;
+	struct update_data_list *plist, *temp_list;
+	int i;
+
+	fb_data = (struct mxc_epdc_fb_data *)framebuffer_alloc(
+			sizeof(struct mxc_epdc_fb_data), &pdev->dev);
+	if (fb_data == NULL) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	fb_data->dev = &pdev->dev;
+	/* We want to use hard-coded structure defined in this file */
+	pentry = &ed060sc4_fb_entry;
+	fb_data->cur = pentry;
+	platform_set_drvdata(pdev, fb_data);
+	info = &fb_data->info;
+
+	/* Allocate color map for the FB */
+	ret = fb_alloc_cmap(&info->cmap, 256, 0);
+	if (ret)
+		goto out_fbdata;
+
+	dev_dbg(&pdev->dev, "resolution %dx%d, bpp %d\n", pentry->x_res,
+		pentry->y_res, pentry->bpp);
+
+	fb_data->mem_size = pentry->x_res * pentry->y_res * pentry->bpp/8;
+
+	fb_data->map_size = PAGE_ALIGN(fb_data->mem_size) * NUM_SCREENS;
+	dev_dbg(&pdev->dev, "memory to allocate: %d\n", fb_data->map_size);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		ret = -ENODEV;
+		goto out_cmap;
+	}
+
+	epdc_base = ioremap(res->start, SZ_4K);
+	if (epdc_base == NULL) {
+		ret = -ENOMEM;
+		goto out_cmap;
+	}
+
+	/* Allocate FB memory */
+	info->screen_base = dma_alloc_writecombine(&pdev->dev,
+						  fb_data->map_size,
+						  &fb_data->phys_start,
+						  GFP_KERNEL);
+
+	if (info->screen_base == NULL) {
+		ret = -ENOMEM;
+		goto out_mapregs;
+	}
+	dev_dbg(&pdev->dev, "allocated at %p:0x%x\n", info->screen_base,
+		fb_data->phys_start);
+
+	mxc_epdc_fb_default.bits_per_pixel = pentry->bpp;
+	mxc_epdc_fb_default.xres = pentry->x_res;
+	mxc_epdc_fb_default.yres = pentry->y_res;
+	mxc_epdc_fb_default.xres_virtual = pentry->x_res;
+	mxc_epdc_fb_default.yres_virtual = pentry->y_res * 2; /* FB doubled in virtual space */
+
+	mxc_epdc_fb_fix.smem_start = fb_data->phys_start;
+	mxc_epdc_fb_fix.smem_len = mxc_epdc_fb_default.yres_virtual
+				* pentry->x_res * 2 * pentry->bpp / 8;
+	mxc_epdc_fb_fix.ypanstep = 0;
+
+	switch (pentry->bpp) {
+	case 32:
+	case 24:
+		mxc_epdc_fb_default.red.offset = 16;
+		mxc_epdc_fb_default.red.length = 8;
+		mxc_epdc_fb_default.green.offset = 8;
+		mxc_epdc_fb_default.green.length = 8;
+		mxc_epdc_fb_default.blue.offset = 0;
+		mxc_epdc_fb_default.blue.length = 8;
+		break;
+
+	case 16:
+		mxc_epdc_fb_default.red.offset = 11;
+		mxc_epdc_fb_default.red.length = 5;
+		mxc_epdc_fb_default.green.offset = 5;
+		mxc_epdc_fb_default.green.length = 6;
+		mxc_epdc_fb_default.blue.offset = 0;
+		mxc_epdc_fb_default.blue.length = 5;
+		break;
+
+	default:
+		dev_err(&pdev->dev, "unsupported bitwidth %d\n", pentry->bpp);
+		ret = -EINVAL;
+		goto out_dma_fb;
+	}
+
+	fb_data->native_width = pentry->x_res;
+	fb_data->native_height = pentry->y_res;
+
+	info->fbops = &mxc_epdc_fb_ops;
+	info->var = mxc_epdc_fb_default;
+	info->fix = mxc_epdc_fb_fix;
+	info->var.activate = FB_ACTIVATE_NOW;
+	info->pseudo_palette = fb_data->pseudo_palette;
+	info->screen_size = info->fix.smem_len;
+	fb_data->par = NULL;
+	info->flags = FBINFO_FLAG_DEFAULT;
+
+	mxc_epdc_fb_set_fix(info);
+
+	fb_data->auto_mode = AUTO_UPDATE_MODE_REGION_MODE;
+
+	init_waitqueue_head(&fb_data->vsync_wait_q);
+	fb_data->vsync_count = 0;
+
+	fb_data->fb_offset = 0;
+
+	/* Allocate head objects for our lists */
+	fb_data->upd_buf_queue =
+	    kzalloc(sizeof(struct update_data_list), GFP_KERNEL);
+	fb_data->upd_buf_collision_list =
+	    kzalloc(sizeof(struct update_data_list), GFP_KERNEL);
+	fb_data->upd_buf_free_list =
+	    kzalloc(sizeof(struct update_data_list), GFP_KERNEL);
+	if ((fb_data->upd_buf_queue == NULL) || (fb_data->upd_buf_free_list == NULL)
+	    || (fb_data->upd_buf_collision_list == NULL)) {
+		ret = -ENOMEM;
+		goto out_dma_fb;
+	}
+
+	/*
+	 * Initialize lists for update requests, update collisions,
+	 * and available update (PxP output) buffers
+	 */
+	INIT_LIST_HEAD(&fb_data->upd_buf_queue->list);
+	INIT_LIST_HEAD(&fb_data->upd_buf_free_list->list);
+	INIT_LIST_HEAD(&fb_data->upd_buf_collision_list->list);
+
+	/* Allocate update buffers and add them to the list */
+	for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) {
+		upd_list = kzalloc(sizeof(*upd_list), GFP_KERNEL);
+		if (upd_list == NULL) {
+			ret = -ENOMEM;
+			goto out_upd_buffers;
+		}
+
+		/* Clear update data structure */
+		memset(&upd_list->upd_data, 0,
+		       sizeof(struct mxcfb_update_data));
+
+		/*
+		 * Each update buffer is 1 byte per pixel, and can
+		 * be as big as the full-screen frame buffer
+		 */
+		upd_list->size = info->var.xres * info->var.yres;
+
+		/* Allocate memory for PxP output buffer */
+		upd_list->virt_addr =
+		    dma_alloc_coherent(fb_data->info.device, upd_list->size,
+				       &upd_list->phys_addr, GFP_DMA);
+		if (upd_list->virt_addr == NULL) {
+			kfree(upd_list);
+			ret = -ENOMEM;
+			goto out_upd_buffers;
+		}
+
+		/* Add newly allocated buffer to free list */
+		list_add(&upd_list->list, &fb_data->upd_buf_free_list->list);
+
+		dev_dbg(fb_data->info.device, "allocated %d bytes @ 0x%08X\n",
+			upd_list->size, upd_list->phys_addr);
+	}
+
+	fb_data->working_buffer_size = pentry->y_res * pentry->x_res * 2;
+	/* Allocate memory for EPDC working buffer */
+	fb_data->working_buffer_virt =
+	    dma_alloc_coherent(&pdev->dev, fb_data->working_buffer_size,
+			       &fb_data->working_buffer_phys, GFP_DMA);
+	if (fb_data->working_buffer_virt == NULL) {
+		dev_err(&pdev->dev, "Can't allocate mem for working buf!\n");
+		ret = -ENOMEM;
+		goto out_upd_buffers;
+	}
+
+	fb_data->epdc_clk_axi = clk_get(fb_data->dev, "epdc_axi");
+	fb_data->epdc_clk_pix = clk_get(fb_data->dev, "epdc_pix");
+
+	clk_set_rate(fb_data->epdc_clk_axi, 200000000);
+
+	fb_data->in_init = false;
+
+	fb_data->hw_ready = false;
+
+	/*
+	 * Set default waveform mode values.
+	 * Should be overwritten via ioctl.
+	 */
+	fb_data->wv_modes.mode_init = 0;
+	fb_data->wv_modes.mode_du = 1;
+	fb_data->wv_modes.mode_gc4 = 3;
+	fb_data->wv_modes.mode_gc8 = 2;
+	fb_data->wv_modes.mode_gc16 = 2;
+	fb_data->wv_modes.mode_gc32 = 2;
+
+	/* Initialize markers */
+	for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) {
+		fb_data->update_marker_array[i].update_marker = 0;
+		fb_data->update_marker_array[i].lut_num = INVALID_LUT;
+	}
+
+	/* Initialize all LUTs to inactive */
+	for (i = 0; i < EPDC_NUM_LUTS; i++)
+		fb_data->lut_update_type[i] = LUT_UPDATE_NONE;
+
+	/* Retrieve EPDC IRQ num */
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "cannot get IRQ resource\n");
+		ret = -ENODEV;
+		goto out_dma_work_buf;
+	}
+	fb_data->epdc_irq = res->start;
+
+	/* Register IRQ handler */
+	ret = request_irq(fb_data->epdc_irq, mxc_epdc_irq_handler, 0,
+			"fb_dma", fb_data);
+	if (ret) {
+		dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
+			fb_data->epdc_irq, ret);
+		goto out_dma_work_buf;
+	}
+
+	INIT_WORK(&fb_data->epdc_done_work, epdc_done_work_func);
+
+	info->fbdefio = &mxc_epdc_fb_defio;
+#ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE
+	fb_deferred_io_init(info);
+#endif
+
+	/* get pmic regulators */
+	fb_data->display_regulator = regulator_get(NULL, "DISPLAY");
+	if (IS_ERR(fb_data->display_regulator)) {
+		dev_err(&pdev->dev, "Unable to get display PMIC regulator."
+			"err = 0x%x\n", fb_data->display_regulator);
+		goto out_dma_work_buf;
+	}
+	fb_data->vcom_regulator = regulator_get(NULL, "VCOM");
+	if (IS_ERR(fb_data->vcom_regulator)) {
+		regulator_put(fb_data->display_regulator);
+		dev_err(&pdev->dev, "Unable to get VCOM regulator."
+			"err = 0x%x\n", fb_data->vcom_regulator);
+		goto out_dma_work_buf;
+	}
+
+	if (device_create_file(info->dev, &fb_attrs[0]))
+		dev_err(&pdev->dev, "Unable to create file from fb_attrs\n");
+
+	fb_data->cur_update = NULL;
+
+	spin_lock_init(&fb_data->queue_lock);
+
+	mutex_init(&fb_data->pxp_mutex);
+
+	mutex_init(&fb_data->power_mutex);
+
+	/* PxP DMA interface */
+	dmaengine_get();
+
+	/*
+	 * Fill out PxP config data structure based on FB info and
+	 * processing tasks required
+	 */
+	pxp_conf = &fb_data->pxp_conf;
+	proc_data = &pxp_conf->proc_data;
+
+	/* Initialize non-channel-specific PxP parameters */
+	proc_data->drect.left = proc_data->srect.left = 0;
+	proc_data->drect.top = proc_data->srect.top = 0;
+	proc_data->drect.width = proc_data->srect.width = fb_data->info.var.xres;
+	proc_data->drect.height = proc_data->srect.height = fb_data->info.var.yres;
+	proc_data->scaling = 0;
+	proc_data->hflip = 0;
+	proc_data->vflip = 0;
+	proc_data->rotate = 0;
+	proc_data->bgcolor = 0;
+	proc_data->overlay_state = 0;
+	proc_data->lut_transform = PXP_LUT_NONE;
+
+	/*
+	 * We initially configure PxP for RGB->YUV conversion,
+	 * and only write out Y component of the result.
+	 */
+
+	/*
+	 * Initialize S0 channel parameters
+	 * Parameters should match FB format/width/height
+	 */
+	pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
+	pxp_conf->s0_param.width = fb_data->info.var.xres;
+	pxp_conf->s0_param.height = fb_data->info.var.yres;
+	pxp_conf->s0_param.color_key = -1;
+	pxp_conf->s0_param.color_key_enable = false;
+
+	/*
+	 * Initialize OL0 channel parameters
+	 * No overlay will be used for PxP operation
+	 */
+	 for (i = 0; i < 8; i++) {
+		pxp_conf->ol_param[i].combine_enable = false;
+		pxp_conf->ol_param[i].width = 0;
+		pxp_conf->ol_param[i].height = 0;
+		pxp_conf->ol_param[i].pixel_fmt = PXP_PIX_FMT_RGB565;
+		pxp_conf->ol_param[i].color_key_enable = false;
+		pxp_conf->ol_param[i].color_key = -1;
+		pxp_conf->ol_param[i].global_alpha_enable = false;
+		pxp_conf->ol_param[i].global_alpha = 0;
+		pxp_conf->ol_param[i].local_alpha_enable = false;
+	}
+
+	/*
+	 * Initialize Output channel parameters
+	 * Output is Y-only greyscale
+	 * Output width/height will vary based on update region size
+	 */
+	pxp_conf->out_param.width = fb_data->info.var.xres;
+	pxp_conf->out_param.height = fb_data->info.var.yres;
+	pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_GREY;
+
+	/*
+	 * Ensure this is set to NULL here...we will initialize pxp_chan
+	 * later in our thread.
+	 */
+	fb_data->pxp_chan = NULL;
+
+	/* Initialize Scatter-gather list containing 2 buffer addresses. */
+	sg = fb_data->sg;
+	sg_init_table(sg, 2);
+
+	/*
+	 * For use in PxP transfers:
+	 * sg[0] holds the FB buffer pointer
+	 * sg[1] holds the Output buffer pointer (configured before TX request)
+	 */
+	sg_dma_address(&sg[0]) = info->fix.smem_start;
+	sg_set_page(&sg[0], virt_to_page(info->screen_base),
+		    info->fix.smem_len, offset_in_page(info->screen_base));
+
+	fb_data->waiting_for_idle = false;
+	fb_data->blank = FB_BLANK_UNBLANK;
+	fb_data->power_state = POWER_STATE_OFF;
+	fb_data->powering_down = false;
+
+	/* Register FB */
+	ret = register_framebuffer(info);
+	if (ret) {
+		dev_err(&pdev->dev,
+			"register_framebuffer failed with error %d\n", ret);
+		goto out_irq;
+	}
+
+#ifdef DEFAULT_PANEL_HW_INIT
+	ret = mxc_epdc_fb_init_hw((struct fb_info *)fb_data);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to read firmware!\n");
+		goto out_dmaengine;
+	}
+#endif
+
+	goto out;
+
+out_dmaengine:
+	dmaengine_put();
+	unregister_framebuffer(&fb_data->info);
+out_irq:
+	free_irq(fb_data->epdc_irq, fb_data);
+out_dma_work_buf:
+	dma_free_writecombine(&pdev->dev, pentry->y_res * pentry->x_res / 2,
+		fb_data->working_buffer_virt, fb_data->working_buffer_phys);
+out_upd_buffers:
+	list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list->list, list) {
+		list_del(&plist->list);
+		dma_free_writecombine(&pdev->dev, plist->size, plist->virt_addr,
+				      plist->phys_addr);
+		kfree(plist);
+	}
+out_dma_fb:
+	dma_free_writecombine(&pdev->dev, fb_data->map_size, info->screen_base,
+			      fb_data->phys_start);
+
+out_mapregs:
+	iounmap(epdc_base);
+out_cmap:
+	fb_dealloc_cmap(&info->cmap);
+out_fbdata:
+	kfree(fb_data);
+out:
+	return ret;
+}
+
+static int mxc_epdc_fb_remove(struct platform_device *pdev)
+{
+	struct update_data_list *plist, *temp_list;
+	struct mxc_epdc_fb_data *fb_data = platform_get_drvdata(pdev);
+
+	mxc_epdc_fb_blank(FB_BLANK_POWERDOWN, &fb_data->info);
+
+	regulator_put(fb_data->display_regulator);
+	regulator_put(fb_data->vcom_regulator);
+
+	unregister_framebuffer(&fb_data->info);
+	free_irq(fb_data->epdc_irq, fb_data);
+
+	dma_free_writecombine(&pdev->dev, fb_data->working_buffer_size, fb_data->working_buffer_virt,
+			      fb_data->working_buffer_phys);
+	dma_free_writecombine(&pdev->dev, fb_data->waveform_buffer_size, fb_data->waveform_buffer_virt,
+			      fb_data->waveform_buffer_phys);
+	list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list->list, list) {
+		list_del(&plist->list);
+		dma_free_writecombine(&pdev->dev, plist->size, plist->virt_addr,
+				      plist->phys_addr);
+		kfree(plist);
+	}
+	dma_free_writecombine(&pdev->dev, fb_data->map_size, fb_data->info.screen_base,
+			      fb_data->phys_start);
+
+	/* Release PxP-related resources */
+	if (fb_data->pxp_chan != NULL)
+		dma_release_channel(&fb_data->pxp_chan->dma_chan);
+
+	dmaengine_put();
+
+	iounmap(epdc_base);
+
+#ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE
+	fb_deferred_io_cleanup(&fb_data->info);
+#endif
+	fb_dealloc_cmap(&fb_data->info.cmap);
+
+	framebuffer_release(&fb_data->info);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxc_epdc_fb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct mxc_epdc_fb_data *data = platform_get_drvdata(pdev);
+	int ret;
+
+	ret = mxc_epdc_fb_blank(FB_BLANK_POWERDOWN, &data->info);
+	if (ret)
+		goto out;
+
+out:
+	return ret;
+}
+
+static int mxc_epdc_fb_resume(struct platform_device *pdev)
+{
+	struct mxc_epdc_fb_data *data = platform_get_drvdata(pdev);
+
+	mxc_epdc_fb_blank(FB_BLANK_UNBLANK, &data->info);
+	return 0;
+}
+#else
+#define mxc_epdc_fb_suspend	NULL
+#define mxc_epdc_fb_resume	NULL
+#endif
+
+static struct platform_driver mxc_epdc_fb_driver = {
+	.probe = mxc_epdc_fb_probe,
+	.remove = mxc_epdc_fb_remove,
+	.suspend = mxc_epdc_fb_suspend,
+	.resume = mxc_epdc_fb_resume,
+	.driver = {
+		   .name = "mxc_epdc_fb",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+/* Callback function triggered after PxP receives an EOF interrupt */
+static void pxp_dma_done(void *arg)
+{
+	struct pxp_tx_desc *tx_desc = to_tx_desc(arg);
+	struct dma_chan *chan = tx_desc->txd.chan;
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+	struct mxc_epdc_fb_data *fb_data = pxp_chan->client;
+
+	/* This call will signal wait_for_completion_timeout() in send_buffer_to_pxp */
+	complete(&fb_data->pxp_tx_cmpl);
+}
+
+/* Function to request PXP DMA channel */
+static int pxp_chan_init(struct mxc_epdc_fb_data *fb_data)
+{
+	dma_cap_mask_t mask;
+	struct dma_chan *chan;
+
+	/*
+	 * Request a free channel
+	 */
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+	dma_cap_set(DMA_PRIVATE, mask);
+	chan = dma_request_channel(mask, NULL, NULL);
+	if (!chan) {
+		dev_err(fb_data->dev, "Unsuccessfully received channel!!!!\n");
+		return -EBUSY;
+	}
+
+	dev_dbg(fb_data->dev, "Successfully received channel.\n");
+
+	fb_data->pxp_chan = to_pxp_channel(chan);
+
+	dev_dbg(fb_data->dev, "dma_chan = 0x%x\n", fb_data->pxp_chan->dma_chan);
+
+	fb_data->pxp_chan->client = fb_data;
+
+	init_completion(&fb_data->pxp_tx_cmpl);
+
+	return 0;
+}
+
+/*
+ * Function to call PxP DMA driver and send our latest FB update region
+ * through the PxP and out to an intermediate buffer.
+ * Note: This is a blocking call, so upon return the PxP tx should be complete.
+ */
+static int pxp_process_update(struct mxc_epdc_fb_data *fb_data,
+			      struct mxcfb_rect *update_region)
+{
+	dma_cookie_t cookie;
+	struct scatterlist *sg = fb_data->sg;
+	struct dma_chan *dma_chan;
+	struct pxp_tx_desc *desc;
+	struct dma_async_tx_descriptor *txd;
+	struct pxp_config_data *pxp_conf = &fb_data->pxp_conf;
+	struct pxp_proc_data *proc_data = &fb_data->pxp_conf.proc_data;
+	int i, ret;
+
+	dev_dbg(fb_data->dev, "Starting PxP Send Buffer\n");
+
+	/* First, check to see that we have acquired a PxP Channel object */
+	if (fb_data->pxp_chan == NULL) {
+		/*
+		 * PxP Channel has not yet been created and initialized,
+		 * so let's go ahead and try
+		 */
+		ret = pxp_chan_init(fb_data);
+		if (ret) {
+			/*
+			 * PxP channel init failed, and we can't use the
+			 * PxP until the PxP DMA driver has loaded, so we abort
+			 */
+			dev_err(fb_data->dev, "PxP chan init failed\n");
+			return -ENODEV;
+		}
+	}
+
+	/*
+	 * Init completion, so that we
+	 * can be properly informed of the completion
+	 * of the PxP task when it is done.
+	 */
+	init_completion(&fb_data->pxp_tx_cmpl);
+
+	dev_dbg(fb_data->dev, "sg[0] = 0x%x, sg[1] = 0x%x\n",
+		sg_dma_address(&sg[0]), sg_dma_address(&sg[1]));
+
+	dma_chan = &fb_data->pxp_chan->dma_chan;
+
+	txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg, 2,
+						     DMA_TO_DEVICE,
+						     DMA_PREP_INTERRUPT);
+	if (!txd) {
+		dev_err(fb_data->info.device,
+			"Error preparing a DMA transaction descriptor.\n");
+		return -EIO;
+	}
+
+	txd->callback_param = txd;
+	txd->callback = pxp_dma_done;
+
+	/*
+	 * Configure PxP for processing of new update region
+	 * The rest of our config params were set up in
+	 * probe() and should not need to be changed.
+	 */
+	proc_data->srect.top = update_region->top;
+	proc_data->srect.left = update_region->left;
+	proc_data->srect.width = update_region->width;
+	proc_data->srect.height = update_region->height;
+
+	/*
+	 * Because only YUV/YCbCr image can be scaled, configure
+	 * drect equivalent to srect, as such do not perform scaling.
+	 */
+	proc_data->drect.top = 0;
+	proc_data->drect.left = 0;
+	proc_data->drect.width = proc_data->srect.width;
+	proc_data->drect.height = proc_data->srect.height;
+
+	/* PXP expects rotation in terms of degrees */
+	proc_data->rotate = fb_data->info.var.rotate * 90;
+	if (proc_data->rotate > 270)
+		proc_data->rotate = 0;
+
+	pxp_conf->out_param.width = update_region->width;
+	pxp_conf->out_param.height = update_region->height;
+
+	desc = to_tx_desc(txd);
+	int length = desc->len;
+	for (i = 0; i < length; i++) {
+		if (i == 0) {/* S0 */
+			memcpy(&desc->proc_data, proc_data, sizeof(struct pxp_proc_data));
+			pxp_conf->s0_param.paddr = sg_dma_address(&sg[0]);
+			memcpy(&desc->layer_param.s0_param, &pxp_conf->s0_param,
+				sizeof(struct pxp_layer_param));
+		} else if (i == 1) {
+			pxp_conf->out_param.paddr = sg_dma_address(&sg[1]);
+			memcpy(&desc->layer_param.out_param, &pxp_conf->out_param,
+				sizeof(struct pxp_layer_param));
+		}
+		/* TODO: OverLay */
+
+		desc = desc->next;
+	}
+
+	/* Submitting our TX starts the PxP processing task */
+	cookie = txd->tx_submit(txd);
+	dev_dbg(fb_data->info.device, "%d: Submit %p #%d\n", __LINE__, txd,
+		cookie);
+	if (cookie < 0) {
+		dev_err(fb_data->info.device, "Error sending FB through PxP\n");
+		return -EIO;
+	}
+
+	fb_data->txd = txd;
+
+	/* trigger ePxP */
+	dma_async_issue_pending(dma_chan);
+
+	return 0;
+}
+
+static int pxp_complete_update(struct mxc_epdc_fb_data *fb_data, u32 *hist_stat)
+{
+	int ret;
+	/*
+	 * Wait for completion event, which will be set
+	 * through our TX callback function.
+	 */
+	ret = wait_for_completion_timeout(&fb_data->pxp_tx_cmpl, HZ / 10);
+	if (ret <= 0) {
+		dev_info(fb_data->info.device,
+			 "PxP operation failed due to %s\n",
+			 ret < 0 ? "user interrupt" : "timeout");
+		dma_release_channel(&fb_data->pxp_chan->dma_chan);
+		fb_data->pxp_chan = NULL;
+		return ret ? : -ETIMEDOUT;
+	}
+
+	*hist_stat = to_tx_desc(fb_data->txd)->hist_status;
+	dma_release_channel(&fb_data->pxp_chan->dma_chan);
+	fb_data->pxp_chan = NULL;
+
+	dev_dbg(fb_data->dev, "TX completed\n");
+
+	return 0;
+}
+
+static int __init mxc_epdc_fb_init(void)
+{
+	return platform_driver_register(&mxc_epdc_fb_driver);
+}
+late_initcall(mxc_epdc_fb_init);
+
+
+static void __exit mxc_epdc_fb_exit(void)
+{
+	platform_driver_unregister(&mxc_epdc_fb_driver);
+}
+module_exit(mxc_epdc_fb_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC EPDC framebuffer driver");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("fb");
diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c
index 76c6d523c291..be907a956365 100644
--- a/drivers/video/mxc/mxc_ipuv3_fb.c
+++ b/drivers/video/mxc/mxc_ipuv3_fb.c
@@ -22,7 +22,6 @@
  *
  * @ingroup Framebuffer
  */
-
 /*!
  * Include files
  */
@@ -47,6 +46,9 @@
 #include <asm/mach-types.h>
 #include <asm/uaccess.h>
 #include <mach/hardware.h>
+#include <linux/suspend.h>
+
+static int vt_switch;
 
 /*
  * Driver name
@@ -56,11 +58,14 @@
  * Structure containing the MXC specific framebuffer information.
  */
 struct mxcfb_info {
+	char *fb_mode_str;
+	int default_bpp;
 	int cur_blank;
 	int next_blank;
 	ipu_channel_t ipu_ch;
 	int ipu_di;
 	u32 ipu_di_pix_fmt;
+	bool ipu_ext_clk;
 	bool overlay;
 	bool alpha_chan_en;
 	dma_addr_t alpha_phy_addr0;
@@ -74,6 +79,8 @@ struct mxcfb_info {
 
 	u32 pseudo_palette[16];
 
+	bool wait4vsync;
+	uint32_t waitcnt;
 	struct semaphore flip_sem;
 	struct semaphore alpha_flip_sem;
 	struct completion vsync_complete;
@@ -93,12 +100,9 @@ enum {
 	BOTH_OFF
 };
 
-static char *fb_mode;
-static unsigned long default_bpp = 16;
 static bool g_dp_in_use;
 LIST_HEAD(fb_alloc_list);
 static struct fb_info *mxcfb_info[3];
-static int ext_clk_used;
 
 static uint32_t bpp_to_pixfmt(struct fb_info *fbi)
 {
@@ -125,6 +129,7 @@ static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id);
 static int mxcfb_blank(int blank, struct fb_info *info);
 static int mxcfb_map_video_memory(struct fb_info *fbi);
 static int mxcfb_unmap_video_memory(struct fb_info *fbi);
+static int mxcfb_option_setup(struct fb_info *info, char *options);
 
 /*
  * Set fixed framebuffer parameters based on variable settings.
@@ -175,20 +180,33 @@ static int _setup_disp_channel1(struct fb_info *fbi)
 			}
 		}
 	}
-	if (fbi->var.vmode & FB_VMODE_INTERLACED) {
-		params.mem_dp_bg_sync.interlaced = true;
-		params.mem_dp_bg_sync.out_pixel_fmt =
-			IPU_PIX_FMT_YUV444;
+	if (mxc_fbi->ipu_ch == MEM_DC_SYNC) {
+		if (fbi->var.vmode & FB_VMODE_INTERLACED) {
+			params.mem_dc_sync.interlaced = true;
+			params.mem_dc_sync.out_pixel_fmt =
+				IPU_PIX_FMT_YUV444;
+		} else {
+			if (mxc_fbi->ipu_di_pix_fmt)
+				params.mem_dc_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
+			else
+				params.mem_dc_sync.out_pixel_fmt = IPU_PIX_FMT_RGB666;
+		}
+		params.mem_dc_sync.in_pixel_fmt = bpp_to_pixfmt(fbi);
 	} else {
-		if (mxc_fbi->ipu_di_pix_fmt)
-			params.mem_dp_bg_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
-		else
-			params.mem_dp_bg_sync.out_pixel_fmt = IPU_PIX_FMT_RGB666;
+		if (fbi->var.vmode & FB_VMODE_INTERLACED) {
+			params.mem_dp_bg_sync.interlaced = true;
+			params.mem_dp_bg_sync.out_pixel_fmt =
+				IPU_PIX_FMT_YUV444;
+		} else {
+			if (mxc_fbi->ipu_di_pix_fmt)
+				params.mem_dp_bg_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
+			else
+				params.mem_dp_bg_sync.out_pixel_fmt = IPU_PIX_FMT_RGB666;
+		}
+		params.mem_dp_bg_sync.in_pixel_fmt = bpp_to_pixfmt(fbi);
+		if (mxc_fbi->alpha_chan_en)
+			params.mem_dp_bg_sync.alpha_chan_en = true;
 	}
-	params.mem_dp_bg_sync.in_pixel_fmt = bpp_to_pixfmt(fbi);
-	if (mxc_fbi->alpha_chan_en)
-		params.mem_dp_bg_sync.alpha_chan_en = true;
-
 	ipu_init_channel(mxc_fbi->ipu_ch, &params);
 
 	return 0;
@@ -201,10 +219,12 @@ static int _setup_disp_channel2(struct fb_info *fbi)
 	int fb_stride;
 
 	switch (bpp_to_pixfmt(fbi)) {
-	case V4L2_PIX_FMT_YUV420:
-	case V4L2_PIX_FMT_YVU420:
-	case V4L2_PIX_FMT_NV12:
-	case V4L2_PIX_FMT_YUV422P:
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YVU420P:
+	case IPU_PIX_FMT_NV12:
+	case IPU_PIX_FMT_YUV422P:
+	case IPU_PIX_FMT_YVU422P:
+	case IPU_PIX_FMT_YUV420P:
 		fb_stride = fbi->var.xres_virtual;
 		break;
 	default:
@@ -327,8 +347,11 @@ static int mxcfb_set_par(struct fb_info *fbi)
 		}
 	}
 
+#if !(defined(CONFIG_CCWMX51_DISP0) && defined(CONFIG_CCWMX51_DISP1))
+	/* FIXME this lines of code doesnt allow to run the dual head... */
 	if (mxc_fbi->next_blank != FB_BLANK_UNBLANK)
 		return retval;
+#endif
 
 	_setup_disp_channel1(fbi);
 
@@ -347,7 +370,7 @@ static int mxcfb_set_par(struct fb_info *fbi)
 		}
 		if (fbi->var.vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */
 			sig_cfg.odd_field_first = true;
-		if ((fbi->var.sync & FB_SYNC_EXT) || ext_clk_used)
+		if ((fbi->var.sync & FB_SYNC_EXT) || mxc_fbi->ipu_ext_clk)
 			sig_cfg.ext_clk = true;
 		if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
 			sig_cfg.Hsync_pol = true;
@@ -545,6 +568,7 @@ static int swap_channels(struct fb_info *fbi)
  */
 static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 {
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
 	u32 vtotal;
 	u32 htotal;
 
@@ -554,8 +578,9 @@ static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 		var->yres_virtual = var->yres;
 
 	if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
-	    (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8))
-		var->bits_per_pixel = default_bpp;
+	    (var->bits_per_pixel != 16) && (var->bits_per_pixel != 12) &&
+	    (var->bits_per_pixel != 8))
+		var->bits_per_pixel = mxc_fbi->default_bpp;
 
 	switch (var->bits_per_pixel) {
 	case 8:
@@ -891,10 +916,10 @@ static int mxcfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
 				break;
 			}
 
-			down(&mxc_fbi->flip_sem);
 			init_completion(&mxc_fbi->vsync_complete);
 
 			ipu_clear_irq(mxc_fbi->ipu_ch_irq);
+			mxc_fbi->wait4vsync = 1;
 			ipu_enable_irq(mxc_fbi->ipu_ch_irq);
 			retval = wait_for_completion_interruptible_timeout(
 				&mxc_fbi->vsync_complete, 1 * HZ);
@@ -902,6 +927,7 @@ static int mxcfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
 				dev_err(fbi->device,
 					"MXCFB_WAIT_FOR_VSYNC: timeout %d\n",
 					retval);
+				mxc_fbi->wait4vsync = 0;
 				retval = -ETIME;
 			} else if (retval > 0) {
 				retval = 0;
@@ -1032,6 +1058,24 @@ static int mxcfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
 				return -EFAULT;
 			break;
 		}
+	case MXCFB_GET_DIFMT:
+		{
+			struct mxcfb_info *mxc_fbi =
+				(struct mxcfb_info *)fbi->par;
+
+			if (put_user(mxc_fbi->ipu_di_pix_fmt, argp))
+				return -EFAULT;
+			break;
+		}
+	case MXCFB_GET_FB_IPU_DI:
+		{
+			struct mxcfb_info *mxc_fbi =
+				(struct mxcfb_info *)fbi->par;
+
+			if (put_user(mxc_fbi->ipu_di, argp))
+				return -EFAULT;
+			break;
+		}
 	default:
 		retval = -EINVAL;
 	}
@@ -1122,12 +1166,9 @@ mxcfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 		return -EINVAL;
 
 	base = (var->yoffset * var->xres_virtual + var->xoffset);
-	base *= (var->bits_per_pixel) / 8;
+	base = (var->bits_per_pixel) * base / 8;
 	base += info->fix.smem_start;
 
-	dev_dbg(info->device, "Updating SDC %s buf %d address=0x%08lX\n",
-		info->fix.id, mxc_fbi->cur_ipu_buf, base);
-
 	/* Check if DP local alpha is enabled and find the graphic fb */
 	if (mxc_fbi->ipu_ch == MEM_BG_SYNC || mxc_fbi->ipu_ch == MEM_FG_SYNC) {
 		for (i = 0; i < num_registered_fb; i++) {
@@ -1152,9 +1193,12 @@ mxcfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 	}
 
 	down(&mxc_fbi->flip_sem);
-	init_completion(&mxc_fbi->vsync_complete);
 
 	mxc_fbi->cur_ipu_buf = !mxc_fbi->cur_ipu_buf;
+
+	dev_dbg(info->device, "Updating SDC %s buf %d address=0x%08lX\n",
+		info->fix.id, mxc_fbi->cur_ipu_buf, base);
+
 	if (ipu_update_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
 				      mxc_fbi->cur_ipu_buf, base) == 0) {
 		/* Update the DP local alpha buffer only for graphic plane */
@@ -1176,6 +1220,10 @@ mxcfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 		dev_err(info->device,
 			"Error updating SDC buf %d to address=0x%08lX\n",
 			mxc_fbi->cur_ipu_buf, base);
+		mxc_fbi->cur_ipu_buf = !mxc_fbi->cur_ipu_buf;
+		ipu_clear_irq(mxc_fbi->ipu_ch_irq);
+		ipu_enable_irq(mxc_fbi->ipu_ch_irq);
+		return -EBUSY;
 	}
 
 	dev_dbg(info->device, "Update complete\n");
@@ -1269,9 +1317,29 @@ static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id)
 	struct fb_info *fbi = dev_id;
 	struct mxcfb_info *mxc_fbi = fbi->par;
 
-	complete(&mxc_fbi->vsync_complete);
-	up(&mxc_fbi->flip_sem);
-	ipu_disable_irq(irq);
+	if (mxc_fbi->wait4vsync) {
+		complete(&mxc_fbi->vsync_complete);
+		ipu_disable_irq(irq);
+		mxc_fbi->wait4vsync = 0;
+	} else {
+		if (!ipu_check_buffer_busy(mxc_fbi->ipu_ch,
+				IPU_INPUT_BUFFER, mxc_fbi->cur_ipu_buf)
+				|| (mxc_fbi->waitcnt > 2)) {
+			/*
+			 * This interrupt come after pan display select
+			 * cur_ipu_buf buffer, this buffer should become
+			 * idle after show. If it keep busy, clear it manually.
+			 */
+			if (mxc_fbi->waitcnt > 2)
+				ipu_clear_buffer_ready(mxc_fbi->ipu_ch,
+						IPU_INPUT_BUFFER,
+						mxc_fbi->cur_ipu_buf);
+			up(&mxc_fbi->flip_sem);
+			ipu_disable_irq(irq);
+			mxc_fbi->waitcnt = 0;
+		} else
+			mxc_fbi->waitcnt++;
+	}
 	return IRQ_HANDLED;
 }
 
@@ -1443,6 +1511,7 @@ static ssize_t swap_disp_chan(struct device *dev,
 	struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par;
 	struct mxcfb_info *fg_mxcfbi = NULL;
 
+	acquire_console_sem();
 	/* swap only happen between DP-BG and DC, while DP-FG disable */
 	if (((mxcfbi->ipu_ch == MEM_BG_SYNC) &&
 	     (strstr(buf, "1-layer-fb") != NULL)) ||
@@ -1462,6 +1531,7 @@ static ssize_t swap_disp_chan(struct device *dev,
 			fg_mxcfbi->cur_blank == FB_BLANK_UNBLANK) {
 			dev_err(dev,
 				"Can not switch while fb2(fb-fg) is on.\n");
+			release_console_sem();
 			return count;
 		}
 
@@ -1469,6 +1539,7 @@ static ssize_t swap_disp_chan(struct device *dev,
 			dev_err(dev, "Swap display channel failed.\n");
 	}
 
+	release_console_sem();
 	return count;
 }
 DEVICE_ATTR(fsl_disp_property, 644, show_disp_chan, swap_disp_chan);
@@ -1487,6 +1558,8 @@ static int mxcfb_probe(struct platform_device *pdev)
 	struct mxcfb_info *mxcfbi;
 	struct mxc_fb_platform_data *plat_data = pdev->dev.platform_data;
 	struct resource *res;
+	char *options, *mstr;
+	char name[] = "mxcdi0fb";
 	int ret = 0;
 
 	/*
@@ -1499,6 +1572,13 @@ static int mxcfb_probe(struct platform_device *pdev)
 	}
 	mxcfbi = (struct mxcfb_info *)fbi->par;
 
+	name[5] += pdev->id;
+	if (fb_get_options(name, &options))
+		return -ENODEV;
+
+	if (options)
+		mxcfb_option_setup(fbi, options);
+
 	if (!g_dp_in_use) {
 		mxcfbi->ipu_ch_irq = IPU_IRQ_BG_SYNC_EOF;
 		mxcfbi->ipu_ch = MEM_BG_SYNC;
@@ -1579,22 +1659,46 @@ static int mxcfb_probe(struct platform_device *pdev)
 	fbi->var.xres = 240;
 	fbi->var.yres = 320;
 
-	if (!fb_mode && plat_data && plat_data->mode_str)
-		fb_find_mode(&fbi->var, fbi, plat_data->mode_str, NULL, 0, NULL,
-			     default_bpp);
-
-	if (fb_mode)
-		fb_find_mode(&fbi->var, fbi, fb_mode, NULL, 0, NULL,
-			     default_bpp);
+	if (!mxcfbi->default_bpp)
+#ifdef CONFIG_CCWMX51_DEFAULT_VIDEO_BPP
+		mxcfbi->default_bpp = CONFIG_CCWMX51_DEFAULT_VIDEO_BPP;
+#else
+		mxcfbi->default_bpp = 16;
+#endif
 
-	if (plat_data) {
+	if (plat_data && !mxcfbi->ipu_di_pix_fmt)
 		mxcfbi->ipu_di_pix_fmt = plat_data->interface_pix_fmt;
-		if (!fb_mode && plat_data->mode)
-			fb_videomode_to_var(&fbi->var, plat_data->mode);
+
+	if (plat_data && plat_data->mode && plat_data->num_modes)
+		fb_videomode_to_modelist(plat_data->mode, plat_data->num_modes,
+				&fbi->modelist);
+
+	if (!mxcfbi->fb_mode_str && plat_data && plat_data->mode_str)
+		mxcfbi->fb_mode_str = plat_data->mode_str;
+
+	if (mxcfbi->fb_mode_str) {
+#ifdef CONFIG_MODULE_CCXMX51
+		if ((mstr = strstr(mxcfbi->fb_mode_str, "VGA@")) != NULL)
+			mxcfbi->fb_mode_str = mstr + 4;
+#endif
+		ret = fb_find_mode(&fbi->var, fbi, mxcfbi->fb_mode_str, NULL, 0, NULL,
+				mxcfbi->default_bpp);
+		if ((!ret || (ret > 2)) && plat_data && plat_data->mode && plat_data->num_modes)
+			fb_find_mode(&fbi->var, fbi, mxcfbi->fb_mode_str, plat_data->mode,
+					plat_data->num_modes, NULL, mxcfbi->default_bpp);
+#ifdef CONFIG_MODULE_CCXMX51
+		/* This improves the VGA modes on the CCWi-i.MX51 */
+		if (mstr != NULL) {
+			mxcfbi->ipu_ext_clk = true;
+			fbi->var.sync |= FB_SYNC_CLK_LAT_FALL;
+		}
+#endif
 	}
 
 	mxcfb_check_var(&fbi->var, fbi);
 
+	pm_set_vt_switch(vt_switch);
+
 	/* Default Y virtual size is 2x panel size */
 	fbi->var.yres_virtual = fbi->var.yres * 3;
 
@@ -1662,28 +1766,71 @@ static struct platform_driver mxcfb_driver = {
 /*
  * Parse user specified options (`video=trident:')
  * example:
- * 	video=trident:800x600,bpp=16,noaccel
+ * 	video=mxcdi0fb:RGB24, 1024x768M-16@60,bpp=16,noaccel
  */
-int mxcfb_setup(char *options)
+static int mxcfb_option_setup(struct fb_info *info, char *options)
 {
+	struct mxcfb_info *mxcfbi = info->par;
 	char *opt;
+
 	if (!options || !*options)
 		return 0;
+
 	while ((opt = strsep(&options, ",")) != NULL) {
 		if (!*opt)
 			continue;
+
+		if (!strncmp(opt, "RGB24", 5)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_RGB24;
+			continue;
+		}
+		if (!strncmp(opt, "BGR24", 5)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_BGR24;
+			continue;
+		}
+		if (!strncmp(opt, "RGB565", 6)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_RGB565;
+			continue;
+		}
+		if (!strncmp(opt, "RGB666", 6)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_RGB666;
+			continue;
+		}
+		if (!strncmp(opt, "YUV444", 6)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_YUV444;
+			continue;
+		}
+		if (!strncmp(opt, "LVDS666", 7)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_LVDS666;
+			continue;
+		}
+		if (!strncmp(opt, "YUYV16", 6)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_YUYV;
+			continue;
+		}
+		if (!strncmp(opt, "UYVY16", 6)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_UYVY;
+			continue;
+		}
+		if (!strncmp(opt, "YVYU16", 6)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_YVYU;
+			continue;
+		}
+		if (!strncmp(opt, "VYUY16", 6)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_VYUY;
+			continue;
+		}
 		if (!strncmp(opt, "ext_clk", 7)) {
-			ext_clk_used = true;
+			mxcfbi->ipu_ext_clk = true;
 			continue;
-		} else
-			ext_clk_used = false;
-
+		}
 		if (!strncmp(opt, "bpp=", 4))
-			default_bpp = simple_strtoul(opt + 4, NULL, 0);
+			mxcfbi->default_bpp =
+				simple_strtoul(opt + 4, NULL, 0);
 		else
-			fb_mode = opt;
-
+			mxcfbi->fb_mode_str = opt;
 	}
+
 	return 0;
 }
 
@@ -1696,19 +1843,7 @@ int mxcfb_setup(char *options)
  */
 int __init mxcfb_init(void)
 {
-	int ret = 0;
-#ifndef MODULE
-	char *option = NULL;
-#endif
-
-#ifndef MODULE
-	if (fb_get_options("mxcfb", &option))
-		return -ENODEV;
-	mxcfb_setup(option);
-#endif
-
-	ret = platform_driver_register(&mxcfb_driver);
-	return ret;
+	return platform_driver_register(&mxcfb_driver);
 }
 
 void mxcfb_exit(void)
@@ -1716,6 +1851,9 @@ void mxcfb_exit(void)
 	platform_driver_unregister(&mxcfb_driver);
 }
 
+module_param(vt_switch, int, 0);
+MODULE_PARM_DESC(vt_switch, "enable VT switch during suspend/resume");
+
 module_init(mxcfb_init);
 module_exit(mxcfb_exit);
 
diff --git a/drivers/video/mxc/mxcfb_claa_wvga.c b/drivers/video/mxc/mxcfb_claa_wvga.c
index bd5ff7b83f8c..8f696c19e7d9 100644
--- a/drivers/video/mxc/mxcfb_claa_wvga.c
+++ b/drivers/video/mxc/mxcfb_claa_wvga.c
@@ -48,8 +48,8 @@ static int lcd_on;
 
 static struct fb_videomode video_modes[] = {
 	{
-	 /* 800x480 @ 55 Hz , pixel clk @ 25MHz */
-	 "CLAA-WVGA", 55, 800, 480, 40000, 40, 40, 5, 5, 20, 10,
+	 /* 800x480 @ 57 Hz , pixel clk @ 27MHz */
+	 "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10,
 	 FB_SYNC_CLK_LAT_FALL,
 	 FB_VMODE_NONINTERLACED,
 	 0,},
@@ -77,13 +77,14 @@ static int lcd_fb_event(struct notifier_block *nb, unsigned long val, void *v)
 {
 	struct fb_event *event = v;
 
-	if (strcmp(event->info->fix.id, "DISP3 BG")) {
+	if (strcmp(event->info->fix.id, "DISP3 BG") &&
+	    strcmp(event->info->fix.id, "mxc_elcdif_fb"))
 		return 0;
-	}
 
 	switch (val) {
 	case FB_EVENT_FB_REGISTERED:
 		lcd_init_fb(event->info);
+		fb_show_logo(event->info, 0);
 		lcd_poweron();
 		break;
 	case FB_EVENT_BLANK:
@@ -133,7 +134,8 @@ static int __devinit lcd_probe(struct platform_device *pdev)
 	}
 
 	for (i = 0; i < num_registered_fb; i++) {
-		if (strcmp(registered_fb[i]->fix.id, "DISP3 BG") == 0) {
+		if (strcmp(registered_fb[i]->fix.id, "DISP3 BG") == 0 ||
+		    strcmp(registered_fb[i]->fix.id, "mxc_elcdif_fb") == 0) {
 			lcd_init_fb(registered_fb[i]);
 			fb_show_logo(registered_fb[i], 0);
 			lcd_poweron();
diff --git a/drivers/video/mxc/tve.c b/drivers/video/mxc/tve.c
index 2d2929c0cbd9..b1982f868e8c 100644
--- a/drivers/video/mxc/tve.c
+++ b/drivers/video/mxc/tve.c
@@ -68,6 +68,8 @@ static int enabled;		/* enable power on or not */
 DEFINE_SPINLOCK(tve_lock);
 
 static struct fb_info *tve_fbi;
+static struct fb_modelist tve_modelist;
+static bool g_enable_tve;
 
 struct tve_data {
 	struct platform_device *pdev;
@@ -77,6 +79,7 @@ struct tve_data {
 	int detect;
 	void *base;
 	int irq;
+	int blank;
 	struct clk *clk;
 	struct regulator *dac_reg;
 	struct regulator *dig_reg;
@@ -221,40 +224,50 @@ static int _is_tvout_mode_hd_compatible(void)
 static int tve_setup(int mode)
 {
 	u32 reg;
-	struct clk *pll3_clk;
-	unsigned long pll3_clock_rate = 216000000, di1_clock_rate = 27000000;
+	struct clk *tve_parent_clk;
+	unsigned long parent_clock_rate = 216000000, di1_clock_rate = 27000000;
+	unsigned long tve_clock_rate = 216000000;
 	struct clk *ipu_di1_clk;
 	unsigned long lock_flags;
 
-	if (tve.cur_mode == mode)
-		return 0;
-
 	spin_lock_irqsave(&tve_lock, lock_flags);
 
-	tve.cur_mode = mode;
-
 	switch (mode) {
 	case TVOUT_FMT_PAL:
 	case TVOUT_FMT_NTSC:
-		pll3_clock_rate = 216000000;
+		parent_clock_rate = 216000000;
 		di1_clock_rate = 27000000;
 		break;
 	case TVOUT_FMT_720P60:
-		pll3_clock_rate = 297000000;
+		parent_clock_rate = 297000000;
+		if (cpu_is_mx53())
+			tve_clock_rate = 297000000;
 		di1_clock_rate = 74250000;
 		break;
 	}
 	if (enabled)
 		clk_disable(tve.clk);
 
-	pll3_clk = clk_get(NULL, "pll3");
+	tve_parent_clk = clk_get_parent(tve.clk);
 	ipu_di1_clk = clk_get(NULL, "ipu_di1_clk");
 
-	clk_disable(pll3_clk);
-	clk_set_rate(pll3_clk, pll3_clock_rate);
-	clk_set_rate(ipu_di1_clk, di1_clock_rate);
+	clk_disable(tve_parent_clk);
+	clk_set_rate(tve_parent_clk, parent_clock_rate);
+
+	if (cpu_is_mx53())
+		clk_set_rate(tve.clk, tve_clock_rate);
 
 	clk_enable(tve.clk);
+	clk_set_rate(ipu_di1_clk, di1_clock_rate);
+
+	if (tve.cur_mode == mode) {
+		if (!enabled)
+			clk_disable(tve.clk);
+		spin_unlock_irqrestore(&tve_lock, lock_flags);
+		return 0;
+	}
+
+	tve.cur_mode = mode;
 
 	/* select output video format */
 	if (mode == TVOUT_FMT_PAL) {
@@ -497,6 +510,17 @@ static irqreturn_t tve_detect_handler(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
+/* Re-construct clk for tve display */
+static inline void tve_recfg_fb(struct fb_info *fbi)
+{
+	struct fb_var_screeninfo var;
+
+	memset(&var, 0, sizeof(var));
+	fb_videomode_to_var(&var, fbi->mode);
+	fbi->flags &= ~FBINFO_MISC_USEREVENT;
+	fb_set_var(fbi, &var);
+}
+
 int tve_fb_event(struct notifier_block *nb, unsigned long val, void *v)
 {
 	struct fb_event *event = v;
@@ -509,9 +533,9 @@ int tve_fb_event(struct notifier_block *nb, unsigned long val, void *v)
 			break;
 
 		tve_fbi = fbi;
-		fb_add_videomode(&video_modes[0], &tve_fbi->modelist);
-		fb_add_videomode(&video_modes[1], &tve_fbi->modelist);
-		fb_add_videomode(&video_modes[2], &tve_fbi->modelist);
+		fb_add_videomode(&video_modes[0], &tve_modelist.list);
+		fb_add_videomode(&video_modes[1], &tve_modelist.list);
+		fb_add_videomode(&video_modes[2], &tve_modelist.list);
 		break;
 	case FB_EVENT_MODE_CHANGE:
 	{
@@ -525,7 +549,7 @@ int tve_fb_event(struct notifier_block *nb, unsigned long val, void *v)
 
 		fb_var_to_videomode(&cur_mode, &fbi->var);
 
-		list_for_each(pos, &tve_fbi->modelist) {
+		list_for_each(pos, &tve_modelist.list) {
 			modelist = list_entry(pos, struct fb_modelist, list);
 			mode = &modelist->mode;
 			if (fb_mode_is_equal(&cur_mode, mode)) {
@@ -564,31 +588,33 @@ int tve_fb_event(struct notifier_block *nb, unsigned long val, void *v)
 			return 0;
 
 		if (*((int *)event->data) == FB_BLANK_UNBLANK) {
-			if (fb_mode_is_equal(fbi->mode, &video_modes[0])) {
-				if (tve.cur_mode != TVOUT_FMT_NTSC) {
+			if (tve.blank != FB_BLANK_UNBLANK) {
+				if (fb_mode_is_equal(fbi->mode, &video_modes[0])) {
 					tve_disable();
 					tve_setup(TVOUT_FMT_NTSC);
-				}
-				tve_enable();
-			} else if (fb_mode_is_equal(fbi->mode,
-					&video_modes[1])) {
-				if (tve.cur_mode != TVOUT_FMT_PAL) {
+					tve_enable();
+					tve_recfg_fb(fbi);
+				} else if (fb_mode_is_equal(fbi->mode,
+							&video_modes[1])) {
 					tve_disable();
 					tve_setup(TVOUT_FMT_PAL);
-				}
-				tve_enable();
-			} else if (fb_mode_is_equal(fbi->mode,
-					&video_modes[2])) {
-				if (tve.cur_mode != TVOUT_FMT_720P60) {
+					tve_enable();
+					tve_recfg_fb(fbi);
+				} else if (fb_mode_is_equal(fbi->mode,
+							&video_modes[2])) {
 					tve_disable();
 					tve_setup(TVOUT_FMT_720P60);
+					tve_enable();
+					tve_recfg_fb(fbi);
+				} else {
+					tve_setup(TVOUT_FMT_OFF);
 				}
-				tve_enable();
-			} else {
-				tve_setup(TVOUT_FMT_OFF);
+				tve.blank = FB_BLANK_UNBLANK;
 			}
-		} else
+		} else {
 			tve_disable();
+			tve.blank = FB_BLANK_POWERDOWN;
+		}
 		break;
 	}
 	return 0;
@@ -652,6 +678,11 @@ static int tve_probe(struct platform_device *pdev)
 	struct tve_platform_data *plat_data = pdev->dev.platform_data;
 	u32 conf_reg;
 
+	if (g_enable_tve == false)
+		return -ENODEV;
+
+	INIT_LIST_HEAD(&tve_modelist.list);
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (res == NULL)
 		return -ENOMEM;
@@ -699,9 +730,9 @@ static int tve_probe(struct platform_device *pdev)
 	}
 
 	if (tve_fbi != NULL) {
-		fb_add_videomode(&video_modes[0], &tve_fbi->modelist);
-		fb_add_videomode(&video_modes[1], &tve_fbi->modelist);
-		fb_add_videomode(&video_modes[2], &tve_fbi->modelist);
+		fb_add_videomode(&video_modes[0], &tve_modelist.list);
+		fb_add_videomode(&video_modes[1], &tve_modelist.list);
+		fb_add_videomode(&video_modes[2], &tve_modelist.list);
 	}
 
 	tve.dac_reg = regulator_get(&pdev->dev, plat_data->dac_reg);
@@ -748,22 +779,40 @@ static int tve_probe(struct platform_device *pdev)
 
 	clk_disable(tve.clk);
 
+	ret = fb_register_client(&nb);
+	if (ret < 0)
+		goto err2;
+
+	tve.blank = -1;
+
 	/* is primary display? */
 	if (primary) {
-		struct fb_event event;
+		struct fb_var_screeninfo var;
+		const struct fb_videomode *mode;
+
+		memset(&var, 0, sizeof(var));
+		mode = fb_match_mode(&tve_fbi->var, &tve_modelist.list);
+		if (mode) {
+			pr_debug("TVE: fb mode found\n");
+			fb_videomode_to_var(&var, mode);
+		} else {
+			pr_warning("TVE: can not find video mode\n");
+			goto done;
+		}
+		acquire_console_sem();
+		tve_fbi->flags |= FBINFO_MISC_USEREVENT;
+		fb_set_var(tve_fbi, &var);
+		tve_fbi->flags &= ~FBINFO_MISC_USEREVENT;
+		release_console_sem();
 
-		event.info = tve_fbi;
-		tve_fb_event(NULL, FB_EVENT_MODE_CHANGE, &event);
 		acquire_console_sem();
 		fb_blank(tve_fbi, FB_BLANK_UNBLANK);
 		release_console_sem();
+
 		fb_show_logo(tve_fbi, 0);
 	}
 
-	ret = fb_register_client(&nb);
-	if (ret < 0)
-		goto err2;
-
+done:
 	return 0;
 err2:
 	device_remove_file(&pdev->dev, &dev_attr_headphone);
@@ -842,6 +891,14 @@ static struct platform_driver tve_driver = {
 	.resume = tve_resume,
 };
 
+static int __init enable_tve_setup(char *options)
+{
+	g_enable_tve = true;
+
+	return 1;
+}
+__setup("tve", enable_tve_setup);
+
 static int __init tve_init(void)
 {
 	return platform_driver_register(&tve_driver);
diff --git a/drivers/video/mxs/Kconfig b/drivers/video/mxs/Kconfig
index aef4aa59dcad..35b896e95d4f 100644
--- a/drivers/video/mxs/Kconfig
+++ b/drivers/video/mxs/Kconfig
@@ -20,3 +20,9 @@ config FB_MXS_LCD_LMS430
 	default y if ARCH_MX23
 	---help---
 	  Use LMS430 dotclock LCD panel for MXS
+
+config FB_MXS_TVENC
+	depends on ARCH_MXS
+	bool "TVENC"
+	---help---
+	  Use TVOUT encoder for MXS
diff --git a/drivers/video/mxs/Makefile b/drivers/video/mxs/Makefile
index a9580add3757..fbab953718c7 100644
--- a/drivers/video/mxs/Makefile
+++ b/drivers/video/mxs/Makefile
@@ -2,3 +2,5 @@ obj-$(CONFIG_ARCH_MXS)				+= lcdif.o
 obj-$(CONFIG_FB_MXS)				+= mxsfb.o
 obj-$(CONFIG_FB_MXS_LCD_43WVF1G)		+= lcd_43wvf1g.o
 obj-$(CONFIG_FB_MXS_LCD_LMS430)			+= lcd_lms430.o
+# TVOUT support
+obj-$(CONFIG_FB_MXS_TVENC)			+= tvenc.o
diff --git a/drivers/video/mxs/regs-tvenc.h b/drivers/video/mxs/regs-tvenc.h
new file mode 100644
index 000000000000..bd2493e2dee5
--- /dev/null
+++ b/drivers/video/mxs/regs-tvenc.h
@@ -0,0 +1,583 @@
+/*
+ * Freescale TVENC Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.00
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___TVENC_H
+#define __ARCH_ARM___TVENC_H
+
+
+#define HW_TVENC_CTRL	(0x00000000)
+#define HW_TVENC_CTRL_SET	(0x00000004)
+#define HW_TVENC_CTRL_CLR	(0x00000008)
+#define HW_TVENC_CTRL_TOG	(0x0000000c)
+
+#define BM_TVENC_CTRL_SFTRST	0x80000000
+#define BM_TVENC_CTRL_CLKGATE	0x40000000
+#define BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT	0x20000000
+#define BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT	0x10000000
+#define BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT	0x08000000
+#define BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT	0x04000000
+#define BP_TVENC_CTRL_RSRVD1	6
+#define BM_TVENC_CTRL_RSRVD1	0x03FFFFC0
+#define BF_TVENC_CTRL_RSRVD1(v)  \
+		(((v) << 6) & BM_TVENC_CTRL_RSRVD1)
+#define BM_TVENC_CTRL_DAC_FIFO_NO_WRITE	0x00000020
+#define BM_TVENC_CTRL_DAC_FIFO_NO_READ	0x00000010
+#define BM_TVENC_CTRL_DAC_DATA_FIFO_RST	0x00000008
+#define BP_TVENC_CTRL_RSRVD2	1
+#define BM_TVENC_CTRL_RSRVD2	0x00000006
+#define BF_TVENC_CTRL_RSRVD2(v)  \
+		(((v) << 1) & BM_TVENC_CTRL_RSRVD2)
+#define BM_TVENC_CTRL_DAC_MUX_MODE	0x00000001
+
+#define HW_TVENC_CONFIG	(0x00000010)
+#define HW_TVENC_CONFIG_SET	(0x00000014)
+#define HW_TVENC_CONFIG_CLR	(0x00000018)
+#define HW_TVENC_CONFIG_TOG	(0x0000001c)
+
+#define BP_TVENC_CONFIG_RSRVD5	28
+#define BM_TVENC_CONFIG_RSRVD5	0xF0000000
+#define BF_TVENC_CONFIG_RSRVD5(v) \
+		(((v) << 28) & BM_TVENC_CONFIG_RSRVD5)
+#define BM_TVENC_CONFIG_DEFAULT_PICFORM	0x08000000
+#define BP_TVENC_CONFIG_YDEL_ADJ	24
+#define BM_TVENC_CONFIG_YDEL_ADJ	0x07000000
+#define BF_TVENC_CONFIG_YDEL_ADJ(v)  \
+		(((v) << 24) & BM_TVENC_CONFIG_YDEL_ADJ)
+#define BM_TVENC_CONFIG_RSRVD4	0x00800000
+#define BM_TVENC_CONFIG_RSRVD3	0x00400000
+#define BM_TVENC_CONFIG_ADD_YPBPR_PED	0x00200000
+#define BM_TVENC_CONFIG_PAL_SHAPE	0x00100000
+#define BM_TVENC_CONFIG_NO_PED	0x00080000
+#define BM_TVENC_CONFIG_COLOR_BAR_EN	0x00040000
+#define BP_TVENC_CONFIG_YGAIN_SEL	16
+#define BM_TVENC_CONFIG_YGAIN_SEL	0x00030000
+#define BF_TVENC_CONFIG_YGAIN_SEL(v)  \
+		(((v) << 16) & BM_TVENC_CONFIG_YGAIN_SEL)
+#define BP_TVENC_CONFIG_CGAIN	14
+#define BM_TVENC_CONFIG_CGAIN	0x0000C000
+#define BF_TVENC_CONFIG_CGAIN(v)  \
+		(((v) << 14) & BM_TVENC_CONFIG_CGAIN)
+#define BP_TVENC_CONFIG_CLK_PHS	12
+#define BM_TVENC_CONFIG_CLK_PHS	0x00003000
+#define BF_TVENC_CONFIG_CLK_PHS(v)  \
+		(((v) << 12) & BM_TVENC_CONFIG_CLK_PHS)
+#define BM_TVENC_CONFIG_RSRVD2	0x00000800
+#define BM_TVENC_CONFIG_FSYNC_ENBL	0x00000400
+#define BM_TVENC_CONFIG_FSYNC_PHS	0x00000200
+#define BM_TVENC_CONFIG_HSYNC_PHS	0x00000100
+#define BM_TVENC_CONFIG_VSYNC_PHS	0x00000080
+#define BP_TVENC_CONFIG_SYNC_MODE	4
+#define BM_TVENC_CONFIG_SYNC_MODE	0x00000070
+#define BF_TVENC_CONFIG_SYNC_MODE(v)  \
+		(((v) << 4) & BM_TVENC_CONFIG_SYNC_MODE)
+#define BM_TVENC_CONFIG_RSRVD1	0x00000008
+#define BP_TVENC_CONFIG_ENCD_MODE	0
+#define BM_TVENC_CONFIG_ENCD_MODE	0x00000007
+#define BF_TVENC_CONFIG_ENCD_MODE(v)  \
+		(((v) << 0) & BM_TVENC_CONFIG_ENCD_MODE)
+
+#define HW_TVENC_FILTCTRL	(0x00000020)
+#define HW_TVENC_FILTCTRL_SET	(0x00000024)
+#define HW_TVENC_FILTCTRL_CLR	(0x00000028)
+#define HW_TVENC_FILTCTRL_TOG	(0x0000002c)
+
+#define BP_TVENC_FILTCTRL_RSRVD1	20
+#define BM_TVENC_FILTCTRL_RSRVD1	0xFFF00000
+#define BF_TVENC_FILTCTRL_RSRVD1(v) \
+		(((v) << 20) & BM_TVENC_FILTCTRL_RSRVD1)
+#define BM_TVENC_FILTCTRL_YSHARP_BW	0x00080000
+#define BM_TVENC_FILTCTRL_YD_OFFSETSEL	0x00040000
+#define BM_TVENC_FILTCTRL_SEL_YLPF	0x00020000
+#define BM_TVENC_FILTCTRL_SEL_CLPF	0x00010000
+#define BM_TVENC_FILTCTRL_SEL_YSHARP	0x00008000
+#define BM_TVENC_FILTCTRL_YLPF_COEFSEL	0x00004000
+#define BM_TVENC_FILTCTRL_COEFSEL_CLPF	0x00002000
+#define BM_TVENC_FILTCTRL_YS_GAINSGN	0x00001000
+#define BP_TVENC_FILTCTRL_YS_GAINSEL	10
+#define BM_TVENC_FILTCTRL_YS_GAINSEL	0x00000C00
+#define BF_TVENC_FILTCTRL_YS_GAINSEL(v)  \
+		(((v) << 10) & BM_TVENC_FILTCTRL_YS_GAINSEL)
+#define BM_TVENC_FILTCTRL_RSRVD2	0x00000200
+#define BM_TVENC_FILTCTRL_RSRVD3	0x00000100
+#define BP_TVENC_FILTCTRL_RSRVD4	0
+#define BM_TVENC_FILTCTRL_RSRVD4	0x000000FF
+#define BF_TVENC_FILTCTRL_RSRVD4(v)  \
+		(((v) << 0) & BM_TVENC_FILTCTRL_RSRVD4)
+
+#define HW_TVENC_SYNCOFFSET	(0x00000030)
+#define HW_TVENC_SYNCOFFSET_SET	(0x00000034)
+#define HW_TVENC_SYNCOFFSET_CLR	(0x00000038)
+#define HW_TVENC_SYNCOFFSET_TOG	(0x0000003c)
+
+#define BM_TVENC_SYNCOFFSET_RSRVD1	0x80000000
+#define BP_TVENC_SYNCOFFSET_HSO	20
+#define BM_TVENC_SYNCOFFSET_HSO	0x7FF00000
+#define BF_TVENC_SYNCOFFSET_HSO(v)  \
+		(((v) << 20) & BM_TVENC_SYNCOFFSET_HSO)
+#define BP_TVENC_SYNCOFFSET_VSO	10
+#define BM_TVENC_SYNCOFFSET_VSO	0x000FFC00
+#define BF_TVENC_SYNCOFFSET_VSO(v)  \
+		(((v) << 10) & BM_TVENC_SYNCOFFSET_VSO)
+#define BP_TVENC_SYNCOFFSET_HLC	0
+#define BM_TVENC_SYNCOFFSET_HLC	0x000003FF
+#define BF_TVENC_SYNCOFFSET_HLC(v)  \
+		(((v) << 0) & BM_TVENC_SYNCOFFSET_HLC)
+
+#define HW_TVENC_HTIMINGSYNC0	(0x00000040)
+#define HW_TVENC_HTIMINGSYNC0_SET	(0x00000044)
+#define HW_TVENC_HTIMINGSYNC0_CLR	(0x00000048)
+#define HW_TVENC_HTIMINGSYNC0_TOG	(0x0000004c)
+
+#define BP_TVENC_HTIMINGSYNC0_RSRVD2	26
+#define BM_TVENC_HTIMINGSYNC0_RSRVD2	0xFC000000
+#define BF_TVENC_HTIMINGSYNC0_RSRVD2(v) \
+		(((v) << 26) & BM_TVENC_HTIMINGSYNC0_RSRVD2)
+#define BP_TVENC_HTIMINGSYNC0_SYNC_END	16
+#define BM_TVENC_HTIMINGSYNC0_SYNC_END	0x03FF0000
+#define BF_TVENC_HTIMINGSYNC0_SYNC_END(v)  \
+		(((v) << 16) & BM_TVENC_HTIMINGSYNC0_SYNC_END)
+#define BP_TVENC_HTIMINGSYNC0_RSRVD1	10
+#define BM_TVENC_HTIMINGSYNC0_RSRVD1	0x0000FC00
+#define BF_TVENC_HTIMINGSYNC0_RSRVD1(v)  \
+		(((v) << 10) & BM_TVENC_HTIMINGSYNC0_RSRVD1)
+#define BP_TVENC_HTIMINGSYNC0_SYNC_STRT	0
+#define BM_TVENC_HTIMINGSYNC0_SYNC_STRT	0x000003FF
+#define BF_TVENC_HTIMINGSYNC0_SYNC_STRT(v)  \
+		(((v) << 0) & BM_TVENC_HTIMINGSYNC0_SYNC_STRT)
+
+#define HW_TVENC_HTIMINGSYNC1	(0x00000050)
+#define HW_TVENC_HTIMINGSYNC1_SET	(0x00000054)
+#define HW_TVENC_HTIMINGSYNC1_CLR	(0x00000058)
+#define HW_TVENC_HTIMINGSYNC1_TOG	(0x0000005c)
+
+#define BP_TVENC_HTIMINGSYNC1_RSRVD2	26
+#define BM_TVENC_HTIMINGSYNC1_RSRVD2	0xFC000000
+#define BF_TVENC_HTIMINGSYNC1_RSRVD2(v) \
+		(((v) << 26) & BM_TVENC_HTIMINGSYNC1_RSRVD2)
+#define BP_TVENC_HTIMINGSYNC1_SYNC_EQEND	16
+#define BM_TVENC_HTIMINGSYNC1_SYNC_EQEND	0x03FF0000
+#define BF_TVENC_HTIMINGSYNC1_SYNC_EQEND(v)  \
+		(((v) << 16) & BM_TVENC_HTIMINGSYNC1_SYNC_EQEND)
+#define BP_TVENC_HTIMINGSYNC1_RSRVD1	10
+#define BM_TVENC_HTIMINGSYNC1_RSRVD1	0x0000FC00
+#define BF_TVENC_HTIMINGSYNC1_RSRVD1(v)  \
+		(((v) << 10) & BM_TVENC_HTIMINGSYNC1_RSRVD1)
+#define BP_TVENC_HTIMINGSYNC1_SYNC_SREND	0
+#define BM_TVENC_HTIMINGSYNC1_SYNC_SREND	0x000003FF
+#define BF_TVENC_HTIMINGSYNC1_SYNC_SREND(v)  \
+		(((v) << 0) & BM_TVENC_HTIMINGSYNC1_SYNC_SREND)
+
+#define HW_TVENC_HTIMINGACTIVE	(0x00000060)
+#define HW_TVENC_HTIMINGACTIVE_SET	(0x00000064)
+#define HW_TVENC_HTIMINGACTIVE_CLR	(0x00000068)
+#define HW_TVENC_HTIMINGACTIVE_TOG	(0x0000006c)
+
+#define BP_TVENC_HTIMINGACTIVE_RSRVD2	26
+#define BM_TVENC_HTIMINGACTIVE_RSRVD2	0xFC000000
+#define BF_TVENC_HTIMINGACTIVE_RSRVD2(v) \
+		(((v) << 26) & BM_TVENC_HTIMINGACTIVE_RSRVD2)
+#define BP_TVENC_HTIMINGACTIVE_ACTV_END	16
+#define BM_TVENC_HTIMINGACTIVE_ACTV_END	0x03FF0000
+#define BF_TVENC_HTIMINGACTIVE_ACTV_END(v)  \
+		(((v) << 16) & BM_TVENC_HTIMINGACTIVE_ACTV_END)
+#define BP_TVENC_HTIMINGACTIVE_RSRVD1	10
+#define BM_TVENC_HTIMINGACTIVE_RSRVD1	0x0000FC00
+#define BF_TVENC_HTIMINGACTIVE_RSRVD1(v)  \
+		(((v) << 10) & BM_TVENC_HTIMINGACTIVE_RSRVD1)
+#define BP_TVENC_HTIMINGACTIVE_ACTV_STRT	0
+#define BM_TVENC_HTIMINGACTIVE_ACTV_STRT	0x000003FF
+#define BF_TVENC_HTIMINGACTIVE_ACTV_STRT(v)  \
+		(((v) << 0) & BM_TVENC_HTIMINGACTIVE_ACTV_STRT)
+
+#define HW_TVENC_HTIMINGBURST0	(0x00000070)
+#define HW_TVENC_HTIMINGBURST0_SET	(0x00000074)
+#define HW_TVENC_HTIMINGBURST0_CLR	(0x00000078)
+#define HW_TVENC_HTIMINGBURST0_TOG	(0x0000007c)
+
+#define BP_TVENC_HTIMINGBURST0_RSRVD2	26
+#define BM_TVENC_HTIMINGBURST0_RSRVD2	0xFC000000
+#define BF_TVENC_HTIMINGBURST0_RSRVD2(v) \
+		(((v) << 26) & BM_TVENC_HTIMINGBURST0_RSRVD2)
+#define BP_TVENC_HTIMINGBURST0_WBRST_STRT	16
+#define BM_TVENC_HTIMINGBURST0_WBRST_STRT	0x03FF0000
+#define BF_TVENC_HTIMINGBURST0_WBRST_STRT(v)  \
+		(((v) << 16) & BM_TVENC_HTIMINGBURST0_WBRST_STRT)
+#define BP_TVENC_HTIMINGBURST0_RSRVD1	10
+#define BM_TVENC_HTIMINGBURST0_RSRVD1	0x0000FC00
+#define BF_TVENC_HTIMINGBURST0_RSRVD1(v)  \
+		(((v) << 10) & BM_TVENC_HTIMINGBURST0_RSRVD1)
+#define BP_TVENC_HTIMINGBURST0_NBRST_STRT	0
+#define BM_TVENC_HTIMINGBURST0_NBRST_STRT	0x000003FF
+#define BF_TVENC_HTIMINGBURST0_NBRST_STRT(v)  \
+		(((v) << 0) & BM_TVENC_HTIMINGBURST0_NBRST_STRT)
+
+#define HW_TVENC_HTIMINGBURST1	(0x00000080)
+#define HW_TVENC_HTIMINGBURST1_SET	(0x00000084)
+#define HW_TVENC_HTIMINGBURST1_CLR	(0x00000088)
+#define HW_TVENC_HTIMINGBURST1_TOG	(0x0000008c)
+
+#define BP_TVENC_HTIMINGBURST1_RSRVD1	10
+#define BM_TVENC_HTIMINGBURST1_RSRVD1	0xFFFFFC00
+#define BF_TVENC_HTIMINGBURST1_RSRVD1(v) \
+		(((v) << 10) & BM_TVENC_HTIMINGBURST1_RSRVD1)
+#define BP_TVENC_HTIMINGBURST1_BRST_END	0
+#define BM_TVENC_HTIMINGBURST1_BRST_END	0x000003FF
+#define BF_TVENC_HTIMINGBURST1_BRST_END(v)  \
+		(((v) << 0) & BM_TVENC_HTIMINGBURST1_BRST_END)
+
+#define HW_TVENC_VTIMING0	(0x00000090)
+#define HW_TVENC_VTIMING0_SET	(0x00000094)
+#define HW_TVENC_VTIMING0_CLR	(0x00000098)
+#define HW_TVENC_VTIMING0_TOG	(0x0000009c)
+
+#define BP_TVENC_VTIMING0_RSRVD3	26
+#define BM_TVENC_VTIMING0_RSRVD3	0xFC000000
+#define BF_TVENC_VTIMING0_RSRVD3(v) \
+		(((v) << 26) & BM_TVENC_VTIMING0_RSRVD3)
+#define BP_TVENC_VTIMING0_VSTRT_PREEQ	16
+#define BM_TVENC_VTIMING0_VSTRT_PREEQ	0x03FF0000
+#define BF_TVENC_VTIMING0_VSTRT_PREEQ(v)  \
+		(((v) << 16) & BM_TVENC_VTIMING0_VSTRT_PREEQ)
+#define BP_TVENC_VTIMING0_RSRVD2	14
+#define BM_TVENC_VTIMING0_RSRVD2	0x0000C000
+#define BF_TVENC_VTIMING0_RSRVD2(v)  \
+		(((v) << 14) & BM_TVENC_VTIMING0_RSRVD2)
+#define BP_TVENC_VTIMING0_VSTRT_ACTV	8
+#define BM_TVENC_VTIMING0_VSTRT_ACTV	0x00003F00
+#define BF_TVENC_VTIMING0_VSTRT_ACTV(v)  \
+		(((v) << 8) & BM_TVENC_VTIMING0_VSTRT_ACTV)
+#define BP_TVENC_VTIMING0_RSRVD1	6
+#define BM_TVENC_VTIMING0_RSRVD1	0x000000C0
+#define BF_TVENC_VTIMING0_RSRVD1(v)  \
+		(((v) << 6) & BM_TVENC_VTIMING0_RSRVD1)
+#define BP_TVENC_VTIMING0_VSTRT_SUBPH	0
+#define BM_TVENC_VTIMING0_VSTRT_SUBPH	0x0000003F
+#define BF_TVENC_VTIMING0_VSTRT_SUBPH(v)  \
+		(((v) << 0) & BM_TVENC_VTIMING0_VSTRT_SUBPH)
+
+#define HW_TVENC_VTIMING1	(0x000000a0)
+#define HW_TVENC_VTIMING1_SET	(0x000000a4)
+#define HW_TVENC_VTIMING1_CLR	(0x000000a8)
+#define HW_TVENC_VTIMING1_TOG	(0x000000ac)
+
+#define BP_TVENC_VTIMING1_RSRVD3	30
+#define BM_TVENC_VTIMING1_RSRVD3	0xC0000000
+#define BF_TVENC_VTIMING1_RSRVD3(v) \
+		(((v) << 30) & BM_TVENC_VTIMING1_RSRVD3)
+#define BP_TVENC_VTIMING1_VSTRT_POSTEQ	24
+#define BM_TVENC_VTIMING1_VSTRT_POSTEQ	0x3F000000
+#define BF_TVENC_VTIMING1_VSTRT_POSTEQ(v)  \
+		(((v) << 24) & BM_TVENC_VTIMING1_VSTRT_POSTEQ)
+#define BP_TVENC_VTIMING1_RSRVD2	22
+#define BM_TVENC_VTIMING1_RSRVD2	0x00C00000
+#define BF_TVENC_VTIMING1_RSRVD2(v)  \
+		(((v) << 22) & BM_TVENC_VTIMING1_RSRVD2)
+#define BP_TVENC_VTIMING1_VSTRT_SERRA	16
+#define BM_TVENC_VTIMING1_VSTRT_SERRA	0x003F0000
+#define BF_TVENC_VTIMING1_VSTRT_SERRA(v)  \
+		(((v) << 16) & BM_TVENC_VTIMING1_VSTRT_SERRA)
+#define BP_TVENC_VTIMING1_RSRVD1	10
+#define BM_TVENC_VTIMING1_RSRVD1	0x0000FC00
+#define BF_TVENC_VTIMING1_RSRVD1(v)  \
+		(((v) << 10) & BM_TVENC_VTIMING1_RSRVD1)
+#define BP_TVENC_VTIMING1_LAST_FLD_LN	0
+#define BM_TVENC_VTIMING1_LAST_FLD_LN	0x000003FF
+#define BF_TVENC_VTIMING1_LAST_FLD_LN(v)  \
+		(((v) << 0) & BM_TVENC_VTIMING1_LAST_FLD_LN)
+
+#define HW_TVENC_MISC	(0x000000b0)
+#define HW_TVENC_MISC_SET	(0x000000b4)
+#define HW_TVENC_MISC_CLR	(0x000000b8)
+#define HW_TVENC_MISC_TOG	(0x000000bc)
+
+#define BP_TVENC_MISC_RSRVD3	25
+#define BM_TVENC_MISC_RSRVD3	0xFE000000
+#define BF_TVENC_MISC_RSRVD3(v) \
+		(((v) << 25) & BM_TVENC_MISC_RSRVD3)
+#define BP_TVENC_MISC_LPF_RST_OFF	16
+#define BM_TVENC_MISC_LPF_RST_OFF	0x01FF0000
+#define BF_TVENC_MISC_LPF_RST_OFF(v)  \
+		(((v) << 16) & BM_TVENC_MISC_LPF_RST_OFF)
+#define BP_TVENC_MISC_RSRVD2	12
+#define BM_TVENC_MISC_RSRVD2	0x0000F000
+#define BF_TVENC_MISC_RSRVD2(v)  \
+		(((v) << 12) & BM_TVENC_MISC_RSRVD2)
+#define BM_TVENC_MISC_NTSC_LN_CNT	0x00000800
+#define BM_TVENC_MISC_PAL_FSC_PHASE_ALT	0x00000400
+#define BP_TVENC_MISC_FSC_PHASE_RST	8
+#define BM_TVENC_MISC_FSC_PHASE_RST	0x00000300
+#define BF_TVENC_MISC_FSC_PHASE_RST(v)  \
+		(((v) << 8) & BM_TVENC_MISC_FSC_PHASE_RST)
+#define BP_TVENC_MISC_BRUCHB	6
+#define BM_TVENC_MISC_BRUCHB	0x000000C0
+#define BF_TVENC_MISC_BRUCHB(v)  \
+		(((v) << 6) & BM_TVENC_MISC_BRUCHB)
+#define BP_TVENC_MISC_AGC_LVL_CTRL	4
+#define BM_TVENC_MISC_AGC_LVL_CTRL	0x00000030
+#define BF_TVENC_MISC_AGC_LVL_CTRL(v)  \
+		(((v) << 4) & BM_TVENC_MISC_AGC_LVL_CTRL)
+#define BM_TVENC_MISC_RSRVD1	0x00000008
+#define BM_TVENC_MISC_CS_INVERT_CTRL	0x00000004
+#define BP_TVENC_MISC_Y_BLANK_CTRL	0
+#define BM_TVENC_MISC_Y_BLANK_CTRL	0x00000003
+#define BF_TVENC_MISC_Y_BLANK_CTRL(v)  \
+		(((v) << 0) & BM_TVENC_MISC_Y_BLANK_CTRL)
+
+#define HW_TVENC_COLORSUB0	(0x000000c0)
+#define HW_TVENC_COLORSUB0_SET	(0x000000c4)
+#define HW_TVENC_COLORSUB0_CLR	(0x000000c8)
+#define HW_TVENC_COLORSUB0_TOG	(0x000000cc)
+
+#define BP_TVENC_COLORSUB0_PHASE_INC	0
+#define BM_TVENC_COLORSUB0_PHASE_INC	0xFFFFFFFF
+#define BF_TVENC_COLORSUB0_PHASE_INC(v)	(v)
+
+#define HW_TVENC_COLORSUB1	(0x000000d0)
+#define HW_TVENC_COLORSUB1_SET	(0x000000d4)
+#define HW_TVENC_COLORSUB1_CLR	(0x000000d8)
+#define HW_TVENC_COLORSUB1_TOG	(0x000000dc)
+
+#define BP_TVENC_COLORSUB1_PHASE_OFFSET	0
+#define BM_TVENC_COLORSUB1_PHASE_OFFSET	0xFFFFFFFF
+#define BF_TVENC_COLORSUB1_PHASE_OFFSET(v)	(v)
+
+#define HW_TVENC_COPYPROTECT	(0x000000e0)
+#define HW_TVENC_COPYPROTECT_SET	(0x000000e4)
+#define HW_TVENC_COPYPROTECT_CLR	(0x000000e8)
+#define HW_TVENC_COPYPROTECT_TOG	(0x000000ec)
+
+#define BP_TVENC_COPYPROTECT_RSRVD1	16
+#define BM_TVENC_COPYPROTECT_RSRVD1	0xFFFF0000
+#define BF_TVENC_COPYPROTECT_RSRVD1(v) \
+		(((v) << 16) & BM_TVENC_COPYPROTECT_RSRVD1)
+#define BM_TVENC_COPYPROTECT_WSS_ENBL	0x00008000
+#define BM_TVENC_COPYPROTECT_CGMS_ENBL	0x00004000
+#define BP_TVENC_COPYPROTECT_WSS_CGMS_DATA	0
+#define BM_TVENC_COPYPROTECT_WSS_CGMS_DATA	0x00003FFF
+#define BF_TVENC_COPYPROTECT_WSS_CGMS_DATA(v)  \
+		(((v) << 0) & BM_TVENC_COPYPROTECT_WSS_CGMS_DATA)
+
+#define HW_TVENC_CLOSEDCAPTION	(0x000000f0)
+#define HW_TVENC_CLOSEDCAPTION_SET	(0x000000f4)
+#define HW_TVENC_CLOSEDCAPTION_CLR	(0x000000f8)
+#define HW_TVENC_CLOSEDCAPTION_TOG	(0x000000fc)
+
+#define BP_TVENC_CLOSEDCAPTION_RSRVD1	20
+#define BM_TVENC_CLOSEDCAPTION_RSRVD1	0xFFF00000
+#define BF_TVENC_CLOSEDCAPTION_RSRVD1(v) \
+		(((v) << 20) & BM_TVENC_CLOSEDCAPTION_RSRVD1)
+#define BP_TVENC_CLOSEDCAPTION_CC_ENBL	18
+#define BM_TVENC_CLOSEDCAPTION_CC_ENBL	0x000C0000
+#define BF_TVENC_CLOSEDCAPTION_CC_ENBL(v)  \
+		(((v) << 18) & BM_TVENC_CLOSEDCAPTION_CC_ENBL)
+#define BP_TVENC_CLOSEDCAPTION_CC_FILL	16
+#define BM_TVENC_CLOSEDCAPTION_CC_FILL	0x00030000
+#define BF_TVENC_CLOSEDCAPTION_CC_FILL(v)  \
+		(((v) << 16) & BM_TVENC_CLOSEDCAPTION_CC_FILL)
+#define BP_TVENC_CLOSEDCAPTION_CC_DATA	0
+#define BM_TVENC_CLOSEDCAPTION_CC_DATA	0x0000FFFF
+#define BF_TVENC_CLOSEDCAPTION_CC_DATA(v)  \
+		(((v) << 0) & BM_TVENC_CLOSEDCAPTION_CC_DATA)
+
+#define HW_TVENC_COLORBURST	(0x00000140)
+#define HW_TVENC_COLORBURST_SET	(0x00000144)
+#define HW_TVENC_COLORBURST_CLR	(0x00000148)
+#define HW_TVENC_COLORBURST_TOG	(0x0000014c)
+
+#define BP_TVENC_COLORBURST_NBA	24
+#define BM_TVENC_COLORBURST_NBA	0xFF000000
+#define BF_TVENC_COLORBURST_NBA(v) \
+		(((v) << 24) & BM_TVENC_COLORBURST_NBA)
+#define BP_TVENC_COLORBURST_PBA	16
+#define BM_TVENC_COLORBURST_PBA	0x00FF0000
+#define BF_TVENC_COLORBURST_PBA(v)  \
+		(((v) << 16) & BM_TVENC_COLORBURST_PBA)
+#define BP_TVENC_COLORBURST_RSRVD1	12
+#define BM_TVENC_COLORBURST_RSRVD1	0x0000F000
+#define BF_TVENC_COLORBURST_RSRVD1(v)  \
+		(((v) << 12) & BM_TVENC_COLORBURST_RSRVD1)
+#define BP_TVENC_COLORBURST_RSRVD2	0
+#define BM_TVENC_COLORBURST_RSRVD2	0x00000FFF
+#define BF_TVENC_COLORBURST_RSRVD2(v)  \
+		(((v) << 0) & BM_TVENC_COLORBURST_RSRVD2)
+
+#define HW_TVENC_MACROVISION0	(0x00000150)
+#define HW_TVENC_MACROVISION0_SET	(0x00000154)
+#define HW_TVENC_MACROVISION0_CLR	(0x00000158)
+#define HW_TVENC_MACROVISION0_TOG	(0x0000015c)
+
+#define BP_TVENC_MACROVISION0_DATA	0
+#define BM_TVENC_MACROVISION0_DATA	0xFFFFFFFF
+#define BF_TVENC_MACROVISION0_DATA(v)	(v)
+
+#define HW_TVENC_MACROVISION1	(0x00000160)
+#define HW_TVENC_MACROVISION1_SET	(0x00000164)
+#define HW_TVENC_MACROVISION1_CLR	(0x00000168)
+#define HW_TVENC_MACROVISION1_TOG	(0x0000016c)
+
+#define BP_TVENC_MACROVISION1_DATA	0
+#define BM_TVENC_MACROVISION1_DATA	0xFFFFFFFF
+#define BF_TVENC_MACROVISION1_DATA(v)	(v)
+
+#define HW_TVENC_MACROVISION2	(0x00000170)
+#define HW_TVENC_MACROVISION2_SET	(0x00000174)
+#define HW_TVENC_MACROVISION2_CLR	(0x00000178)
+#define HW_TVENC_MACROVISION2_TOG	(0x0000017c)
+
+#define BP_TVENC_MACROVISION2_DATA	0
+#define BM_TVENC_MACROVISION2_DATA	0xFFFFFFFF
+#define BF_TVENC_MACROVISION2_DATA(v)	(v)
+
+#define HW_TVENC_MACROVISION3	(0x00000180)
+#define HW_TVENC_MACROVISION3_SET	(0x00000184)
+#define HW_TVENC_MACROVISION3_CLR	(0x00000188)
+#define HW_TVENC_MACROVISION3_TOG	(0x0000018c)
+
+#define BP_TVENC_MACROVISION3_DATA	0
+#define BM_TVENC_MACROVISION3_DATA	0xFFFFFFFF
+#define BF_TVENC_MACROVISION3_DATA(v)	(v)
+
+#define HW_TVENC_MACROVISION4	(0x00000190)
+#define HW_TVENC_MACROVISION4_SET	(0x00000194)
+#define HW_TVENC_MACROVISION4_CLR	(0x00000198)
+#define HW_TVENC_MACROVISION4_TOG	(0x0000019c)
+
+#define BP_TVENC_MACROVISION4_RSRVD2	24
+#define BM_TVENC_MACROVISION4_RSRVD2	0xFF000000
+#define BF_TVENC_MACROVISION4_RSRVD2(v) \
+		(((v) << 24) & BM_TVENC_MACROVISION4_RSRVD2)
+#define BP_TVENC_MACROVISION4_MACV_TST	16
+#define BM_TVENC_MACROVISION4_MACV_TST	0x00FF0000
+#define BF_TVENC_MACROVISION4_MACV_TST(v)  \
+		(((v) << 16) & BM_TVENC_MACROVISION4_MACV_TST)
+#define BP_TVENC_MACROVISION4_RSRVD1	11
+#define BM_TVENC_MACROVISION4_RSRVD1	0x0000F800
+#define BF_TVENC_MACROVISION4_RSRVD1(v)  \
+		(((v) << 11) & BM_TVENC_MACROVISION4_RSRVD1)
+#define BP_TVENC_MACROVISION4_DATA	0
+#define BM_TVENC_MACROVISION4_DATA	0x000007FF
+#define BF_TVENC_MACROVISION4_DATA(v)  \
+		(((v) << 0) & BM_TVENC_MACROVISION4_DATA)
+
+#define HW_TVENC_DACCTRL	(0x000001a0)
+#define HW_TVENC_DACCTRL_SET	(0x000001a4)
+#define HW_TVENC_DACCTRL_CLR	(0x000001a8)
+#define HW_TVENC_DACCTRL_TOG	(0x000001ac)
+
+#define BM_TVENC_DACCTRL_TEST3	0x80000000
+#define BM_TVENC_DACCTRL_RSRVD1	0x40000000
+#define BM_TVENC_DACCTRL_RSRVD2	0x20000000
+#define BM_TVENC_DACCTRL_JACK1_DIS_DET_EN	0x10000000
+#define BM_TVENC_DACCTRL_TEST2	0x08000000
+#define BM_TVENC_DACCTRL_RSRVD3	0x04000000
+#define BM_TVENC_DACCTRL_RSRVD4	0x02000000
+#define BM_TVENC_DACCTRL_JACK1_DET_EN	0x01000000
+#define BM_TVENC_DACCTRL_TEST1	0x00800000
+#define BM_TVENC_DACCTRL_DISABLE_GND_DETECT	0x00400000
+#define BP_TVENC_DACCTRL_JACK_DIS_ADJ	20
+#define BM_TVENC_DACCTRL_JACK_DIS_ADJ	0x00300000
+#define BF_TVENC_DACCTRL_JACK_DIS_ADJ(v)  \
+		(((v) << 20) & BM_TVENC_DACCTRL_JACK_DIS_ADJ)
+#define BM_TVENC_DACCTRL_GAINDN	0x00080000
+#define BM_TVENC_DACCTRL_GAINUP	0x00040000
+#define BM_TVENC_DACCTRL_INVERT_CLK	0x00020000
+#define BM_TVENC_DACCTRL_SELECT_CLK	0x00010000
+#define BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE	0x00008000
+#define BM_TVENC_DACCTRL_RSRVD5	0x00004000
+#define BM_TVENC_DACCTRL_RSRVD6	0x00002000
+#define BM_TVENC_DACCTRL_PWRUP1	0x00001000
+#define BM_TVENC_DACCTRL_WELL_TOVDD	0x00000800
+#define BM_TVENC_DACCTRL_RSRVD7	0x00000400
+#define BM_TVENC_DACCTRL_RSRVD8	0x00000200
+#define BM_TVENC_DACCTRL_DUMP_TOVDD1	0x00000100
+#define BM_TVENC_DACCTRL_LOWER_SIGNAL	0x00000080
+#define BP_TVENC_DACCTRL_RVAL	4
+#define BM_TVENC_DACCTRL_RVAL	0x00000070
+#define BF_TVENC_DACCTRL_RVAL(v)  \
+		(((v) << 4) & BM_TVENC_DACCTRL_RVAL)
+#define BM_TVENC_DACCTRL_NO_INTERNAL_TERM	0x00000008
+#define BM_TVENC_DACCTRL_HALF_CURRENT	0x00000004
+#define BP_TVENC_DACCTRL_CASC_ADJ	0
+#define BM_TVENC_DACCTRL_CASC_ADJ	0x00000003
+#define BF_TVENC_DACCTRL_CASC_ADJ(v)  \
+		(((v) << 0) & BM_TVENC_DACCTRL_CASC_ADJ)
+
+#define HW_TVENC_DACSTATUS	(0x000001b0)
+#define HW_TVENC_DACSTATUS_SET	(0x000001b4)
+#define HW_TVENC_DACSTATUS_CLR	(0x000001b8)
+#define HW_TVENC_DACSTATUS_TOG	(0x000001bc)
+
+#define BP_TVENC_DACSTATUS_RSRVD1	13
+#define BM_TVENC_DACSTATUS_RSRVD1	0xFFFFE000
+#define BF_TVENC_DACSTATUS_RSRVD1(v) \
+		(((v) << 13) & BM_TVENC_DACSTATUS_RSRVD1)
+#define BM_TVENC_DACSTATUS_RSRVD2	0x00001000
+#define BM_TVENC_DACSTATUS_RSRVD3	0x00000800
+#define BM_TVENC_DACSTATUS_JACK1_DET_STATUS	0x00000400
+#define BM_TVENC_DACSTATUS_RSRVD4	0x00000200
+#define BM_TVENC_DACSTATUS_RSRVD5	0x00000100
+#define BM_TVENC_DACSTATUS_JACK1_GROUNDED	0x00000080
+#define BM_TVENC_DACSTATUS_RSRVD6	0x00000040
+#define BM_TVENC_DACSTATUS_RSRVD7	0x00000020
+#define BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ	0x00000010
+#define BM_TVENC_DACSTATUS_RSRVD8	0x00000008
+#define BM_TVENC_DACSTATUS_RSRVD9	0x00000004
+#define BM_TVENC_DACSTATUS_JACK1_DET_IRQ	0x00000002
+#define BM_TVENC_DACSTATUS_ENIRQ_JACK	0x00000001
+
+#define HW_TVENC_VDACTEST	(0x000001c0)
+#define HW_TVENC_VDACTEST_SET	(0x000001c4)
+#define HW_TVENC_VDACTEST_CLR	(0x000001c8)
+#define HW_TVENC_VDACTEST_TOG	(0x000001cc)
+
+#define BP_TVENC_VDACTEST_RSRVD1	14
+#define BM_TVENC_VDACTEST_RSRVD1	0xFFFFC000
+#define BF_TVENC_VDACTEST_RSRVD1(v) \
+		(((v) << 14) & BM_TVENC_VDACTEST_RSRVD1)
+#define BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN	0x00002000
+#define BM_TVENC_VDACTEST_BYPASS_PIX_INT	0x00001000
+#define BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP	0x00000800
+#define BM_TVENC_VDACTEST_TEST_FIFO_FULL	0x00000400
+#define BP_TVENC_VDACTEST_DATA	0
+#define BM_TVENC_VDACTEST_DATA	0x000003FF
+#define BF_TVENC_VDACTEST_DATA(v)  \
+		(((v) << 0) & BM_TVENC_VDACTEST_DATA)
+
+#define HW_TVENC_VERSION	(0x000001d0)
+
+#define BP_TVENC_VERSION_MAJOR	24
+#define BM_TVENC_VERSION_MAJOR	0xFF000000
+#define BF_TVENC_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_TVENC_VERSION_MAJOR)
+#define BP_TVENC_VERSION_MINOR	16
+#define BM_TVENC_VERSION_MINOR	0x00FF0000
+#define BF_TVENC_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_TVENC_VERSION_MINOR)
+#define BP_TVENC_VERSION_STEP	0
+#define BM_TVENC_VERSION_STEP	0x0000FFFF
+#define BF_TVENC_VERSION_STEP(v)  \
+		(((v) << 0) & BM_TVENC_VERSION_STEP)
+#endif /* __ARCH_ARM___TVENC_H */
diff --git a/drivers/video/mxs/tvenc.c b/drivers/video/mxs/tvenc.c
new file mode 100644
index 000000000000..7aaa1fd013b0
--- /dev/null
+++ b/drivers/video/mxs/tvenc.c
@@ -0,0 +1,279 @@
+/*
+ * Freescale STMP378X dvi panel initialization
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/* #define DEBUG */
+
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <mach/regs-lcdif.h>
+#include <mach/regs-lradc.h>
+#include <mach/regs-pwm.h>
+#include <mach/regs-apbh.h>
+#include <mach/gpio.h>
+#include <mach/lcdif.h>
+#include "regs-tvenc.h"
+
+enum {
+	TVENC_MODE_OFF = 0,
+	TVENC_MODE_NTSC,
+	TVENC_MODE_PAL,
+};
+
+#define REGS_TVENC_BASE (IO_ADDRESS(TVENC_PHYS_ADDR))
+
+/* NTSC 720x480 mode */
+#define NTSC_X_RES	720
+#define NTSC_Y_RES	480
+#define NTSC_H_BLANKING	262
+#define NTSC_V_LINES	525
+
+/* PAL 720x576 mode */
+#define PAL_X_RES	720
+#define PAL_Y_RES	576
+#define PAL_H_BLANKING	274
+#define PAL_V_LINES	625
+
+/* frame size */
+#define DVI_H_BLANKING(m)	(m == TVENC_MODE_NTSC ? \
+				      NTSC_H_BLANKING : PAL_H_BLANKING)
+#define DVI_V_LINES(m)		(m == TVENC_MODE_NTSC ? \
+				      NTSC_V_LINES : PAL_V_LINES)
+#define DVI_H_ACTIVE(m)		(m == TVENC_MODE_NTSC ? NTSC_X_RES : PAL_X_RES)
+#define DVI_V_ACTIVE(m)		(m == TVENC_MODE_NTSC ? NTSC_Y_RES : PAL_Y_RES)
+/* fileds range */
+#define DVI_F1_START(m)		1
+#define DVI_F1_END(m)		(DVI_V_LINES(m) / 2)
+#define DVI_F2_START(m)		(DVI_F1_END(m) + 1)
+#define DVI_F2_END(m)		DVI_V_LINES(m)
+/* blanking range */
+#define DVI_V1_BLANK_START(m)	DVI_F1_END(m)
+#define DVI_V1_BLANK_END(m)	(DVI_V1_BLANK_START(m) + \
+				 (DVI_V_LINES(m) - DVI_V_ACTIVE(m)) / 2)
+#define DVI_V2_BLANK_START(m)	DVI_F2_END(m)
+#define DVI_V2_BLANK_END(m)	((DVI_V2_BLANK_START(m) + \
+				 (DVI_V_LINES(m) - DVI_V_ACTIVE(m)) / 2 - 1) % \
+				 DVI_V_LINES(m))
+
+static struct clk *lcd_clk;
+static struct clk *clk_tv108M_ng;
+static struct clk *clk_tv27M;
+
+static int tvenc_mode;
+
+static void init_tvenc_hw(int mode)
+{
+	/* Reset module */
+	__raw_writel(BM_TVENC_CTRL_SFTRST, REGS_TVENC_BASE + HW_TVENC_CTRL_SET);
+	udelay(10);
+
+	/* Take module out of reset */
+	__raw_writel(BM_TVENC_CTRL_SFTRST | BM_TVENC_CTRL_CLKGATE,
+			REGS_TVENC_BASE + HW_TVENC_CTRL_CLR);
+
+	if (mode == TVENC_MODE_NTSC) {
+		/* Config NTSC-M mode, 8-bit Y/C in, SYNC out */
+		__raw_writel(BM_TVENC_CONFIG_SYNC_MODE |
+				BM_TVENC_CONFIG_PAL_SHAPE |
+				BM_TVENC_CONFIG_YGAIN_SEL |
+				BM_TVENC_CONFIG_CGAIN,
+				REGS_TVENC_BASE + HW_TVENC_CONFIG_CLR);
+		__raw_writel(BM_TVENC_CONFIG_FSYNC_PHS |
+			      BF_TVENC_CONFIG_SYNC_MODE(0x4),
+			      REGS_TVENC_BASE + HW_TVENC_CONFIG_SET);
+
+		/* 859 pixels/line for NTSC */
+		__raw_writel(857, REGS_TVENC_BASE + HW_TVENC_SYNCOFFSET);
+
+		__raw_writel(0x21F07C1F, REGS_TVENC_BASE + HW_TVENC_COLORSUB0);
+		__raw_writel(BM_TVENC_COLORBURST_NBA |
+				BM_TVENC_COLORBURST_PBA,
+				REGS_TVENC_BASE + HW_TVENC_COLORBURST_CLR);
+		__raw_writel(BF_TVENC_COLORBURST_NBA(0xc8) |
+			      BF_TVENC_COLORBURST_PBA(0x0),
+			      REGS_TVENC_BASE + HW_TVENC_COLORBURST_SET);
+	} else if (mode == TVENC_MODE_PAL) {
+		/* Config PAL-B mode, 8-bit Y/C in, SYNC out */
+		__raw_writel(BM_TVENC_CONFIG_SYNC_MODE |
+				BM_TVENC_CONFIG_ENCD_MODE |
+				BM_TVENC_CONFIG_YGAIN_SEL |
+				BM_TVENC_CONFIG_CGAIN |
+				BM_TVENC_CONFIG_FSYNC_PHS,
+				REGS_TVENC_BASE + HW_TVENC_CONFIG_CLR);
+		__raw_writel(BM_TVENC_CONFIG_PAL_SHAPE |
+			      BF_TVENC_CONFIG_YGAIN_SEL(0x1)
+			      | BF_TVENC_CONFIG_CGAIN(0x1)
+			      | BF_TVENC_CONFIG_ENCD_MODE(0x1)
+			      | BF_TVENC_CONFIG_SYNC_MODE(0x4),
+			      REGS_TVENC_BASE + HW_TVENC_CONFIG_SET);
+
+		/* 863 pixels/line for PAL */
+		__raw_writel(863, REGS_TVENC_BASE + HW_TVENC_SYNCOFFSET);
+
+		__raw_writel(0x2A098ACB, REGS_TVENC_BASE + HW_TVENC_COLORSUB0);
+		__raw_writel(BM_TVENC_COLORBURST_NBA |
+				BM_TVENC_COLORBURST_PBA,
+				REGS_TVENC_BASE + HW_TVENC_COLORBURST_CLR);
+		__raw_writel(BF_TVENC_COLORBURST_NBA(0xd6) |
+			      BF_TVENC_COLORBURST_PBA(0x2a),
+			      REGS_TVENC_BASE + HW_TVENC_COLORBURST_SET);
+	}
+
+	/* Power up DAC */
+	__raw_writel(BM_TVENC_DACCTRL_GAINDN |
+		     BM_TVENC_DACCTRL_GAINUP |
+		     BM_TVENC_DACCTRL_PWRUP1 |
+		     BM_TVENC_DACCTRL_DUMP_TOVDD1 |
+		     BF_TVENC_DACCTRL_RVAL(0x3),
+		     REGS_TVENC_BASE + HW_TVENC_DACCTRL);
+
+	/* set all to zero is a requirement for NTSC */
+	__raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION0);
+	__raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION1);
+	__raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION2);
+	__raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION3);
+	__raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION4);
+}
+
+static int init_panel(struct device *dev, dma_addr_t phys, int memsize,
+		      struct mxs_platform_fb_entry *pentry)
+{
+	int ret = 0;
+
+	lcd_clk = clk_get(dev, "lcdif");
+	clk_enable(lcd_clk);
+	clk_set_rate(lcd_clk, 1000000000 / pentry->cycle_time_ns);/* kHz */
+
+	clk_tv108M_ng = clk_get(NULL, "tv108M_ng");
+	clk_tv27M = clk_get(NULL, "tv27M");
+	clk_enable(clk_tv108M_ng);
+	clk_enable(clk_tv27M);
+
+	tvenc_mode = pentry->x_res == NTSC_Y_RES ? TVENC_MODE_NTSC :
+	    TVENC_MODE_PAL;
+
+	init_tvenc_hw(tvenc_mode);
+
+	setup_dvi_panel(DVI_H_ACTIVE(tvenc_mode), DVI_V_ACTIVE(tvenc_mode),
+			DVI_H_BLANKING(tvenc_mode), DVI_V_LINES(tvenc_mode),
+			DVI_V1_BLANK_START(tvenc_mode),
+			DVI_V1_BLANK_END(tvenc_mode),
+			DVI_V2_BLANK_START(tvenc_mode),
+			DVI_V2_BLANK_END(tvenc_mode),
+			DVI_F1_START(tvenc_mode), DVI_F1_END(tvenc_mode),
+			DVI_F2_START(tvenc_mode), DVI_F2_END(tvenc_mode));
+
+	ret = mxs_lcdif_dma_init(dev, phys, memsize);
+	mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_INIT, pentry);
+
+	return ret;
+}
+
+static void release_panel(struct device *dev,
+			  struct mxs_platform_fb_entry *pentry)
+{
+	mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_RELEASE, pentry);
+	release_dvi_panel();
+
+	mxs_lcdif_dma_release();
+
+	clk_disable(clk_tv108M_ng);
+	clk_disable(clk_tv27M);
+	clk_disable(lcd_clk);
+	clk_put(clk_tv108M_ng);
+	clk_put(clk_tv27M);
+	clk_put(lcd_clk);
+}
+
+static int blank_panel(int blank)
+{
+	int ret = 0, count;
+
+	switch (blank) {
+	case FB_BLANK_NORMAL:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_POWERDOWN:
+		__raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT,
+				REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+
+		/* Wait until current transfer is complete, max 30ms */
+		for (count = 30000; count > 0; count--) {
+			if (__raw_readl(REGS_LCDIF_BASE + HW_LCDIF_STAT) &
+			    BM_LCDIF_STAT_TXFIFO_EMPTY)
+				break;
+			udelay(1);
+		}
+		break;
+
+	case FB_BLANK_UNBLANK:
+		__raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT,
+			      REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static struct mxs_platform_fb_entry ntsc_fb_entry = {
+	.name = "tvenc_ntsc",
+	/* x/y swapped */
+	.x_res = NTSC_Y_RES,
+	.y_res = NTSC_X_RES,
+	.bpp = 32,
+	/* the pix_clk should be near 27Mhz for proper syncronization */
+	.cycle_time_ns = 37,
+	.lcd_type = MXS_LCD_PANEL_DVI,
+	.init_panel = init_panel,
+	.release_panel = release_panel,
+	.blank_panel = blank_panel,
+	.run_panel = mxs_lcdif_run,
+	.pan_display = mxs_lcdif_pan_display,
+};
+
+static struct mxs_platform_fb_entry pal_fb_entry = {
+	.name = "tvenc_pal",
+	/* x/y swapped */
+	.x_res = PAL_Y_RES,
+	.y_res = PAL_X_RES,
+	.bpp = 32,
+	/* the pix_clk should be near 27Mhz for proper syncronization */
+	.cycle_time_ns = 37,
+	.lcd_type = MXS_LCD_PANEL_DVI,
+	.init_panel = init_panel,
+	.release_panel = release_panel,
+	.blank_panel = blank_panel,
+	.run_panel = mxs_lcdif_run,
+	.pan_display = mxs_lcdif_pan_display,
+};
+
+static int __init register_devices(void)
+{
+	struct platform_device *pdev;
+	pdev = mxs_get_device("mxs-fb", 0);
+	if (pdev == NULL || IS_ERR(pdev))
+		return -ENODEV;
+
+	mxs_lcd_register_entry(&ntsc_fb_entry, pdev->dev.platform_data);
+	mxs_lcd_register_entry(&pal_fb_entry, pdev->dev.platform_data);
+	return 0;
+}
+
+subsys_initcall(register_devices);
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 5a72083dc67c..adf9632c6b1f 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -1036,7 +1036,7 @@ static int s3c_fb_resume(struct platform_device *pdev)
 
 static struct platform_driver s3c_fb_driver = {
 	.probe		= s3c_fb_probe,
-	.remove		= s3c_fb_remove,
+	.remove		= __devexit_p(s3c_fb_remove),
 	.suspend	= s3c_fb_suspend,
 	.resume		= s3c_fb_resume,
 	.driver		= {
diff --git a/drivers/video/sis/vstruct.h b/drivers/video/sis/vstruct.h
index 705c85360526..bef4aae388d0 100644
--- a/drivers/video/sis/vstruct.h
+++ b/drivers/video/sis/vstruct.h
@@ -342,7 +342,7 @@ struct SiS_Private
 	unsigned short			SiS_RY4COE;
 	unsigned short			SiS_LCDHDES;
 	unsigned short			SiS_LCDVDES;
-	unsigned short			SiS_DDC_Port;
+	SISIOADDRESS			SiS_DDC_Port;
 	unsigned short			SiS_DDC_Index;
 	unsigned short			SiS_DDC_Data;
 	unsigned short			SiS_DDC_NData;
diff --git a/drivers/video/uvesafb.c b/drivers/video/uvesafb.c
index ca5b4643a401..e35232a18571 100644
--- a/drivers/video/uvesafb.c
+++ b/drivers/video/uvesafb.c
@@ -67,12 +67,14 @@ static DEFINE_MUTEX(uvfb_lock);
  * find the kernel part of the task struct, copy the registers and
  * the buffer contents and then complete the task.
  */
-static void uvesafb_cn_callback(void *data)
+static void uvesafb_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp)
 {
-	struct cn_msg *msg = data;
 	struct uvesafb_task *utask;
 	struct uvesafb_ktask *task;
 
+	if (!cap_raised(nsp->eff_cap, CAP_SYS_ADMIN))
+		return;
+
 	if (msg->seq >= UVESAFB_TASKS_MAX)
 		return;
 
diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index a882f2606515..0ffff9ed4eb0 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -281,6 +281,9 @@ static void *vring_get_buf(struct virtqueue *_vq, unsigned int *len)
 		return NULL;
 	}
 
+	/* Only get used array entries after they have been exposed by host. */
+	rmb();
+
 	i = vq->vring.used->ring[vq->last_used_idx%vq->vring.num].id;
 	*len = vq->vring.used->ring[vq->last_used_idx%vq->vring.num].len;
 
diff --git a/drivers/w1/w1_netlink.c b/drivers/w1/w1_netlink.c
index fdf72851c574..45c126fea31d 100644
--- a/drivers/w1/w1_netlink.c
+++ b/drivers/w1/w1_netlink.c
@@ -306,9 +306,8 @@ static int w1_netlink_send_error(struct cn_msg *rcmsg, struct w1_netlink_msg *rm
 	return error;
 }
 
-static void w1_cn_callback(void *data)
+static void w1_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp)
 {
-	struct cn_msg *msg = data;
 	struct w1_netlink_msg *m = (struct w1_netlink_msg *)(msg + 1);
 	struct w1_netlink_cmd *cmd;
 	struct w1_slave *sl;
diff --git a/drivers/watchdog/mxc_wdt.c b/drivers/watchdog/mxc_wdt.c
index 3626a51e557d..0114fab70253 100644
--- a/drivers/watchdog/mxc_wdt.c
+++ b/drivers/watchdog/mxc_wdt.c
@@ -200,7 +200,7 @@ mxc_wdt_ioctl(struct inode *inode, struct file *file,
 
 	switch (cmd) {
 	default:
-		return -ENOIOCTLCMD;
+		return -ENOTTY;
 	case WDIOC_GETSUPPORT:
 		return copy_to_user((struct watchdog_info __user *)arg, &ident,
 				    sizeof(ident));
diff --git a/drivers/watchdog/riowd.c b/drivers/watchdog/riowd.c
index 1e8f02f440e6..d3c824dc2358 100644
--- a/drivers/watchdog/riowd.c
+++ b/drivers/watchdog/riowd.c
@@ -206,7 +206,7 @@ static int __devinit riowd_probe(struct of_device *op,
 
 	dev_set_drvdata(&op->dev, p);
 	riowd_device = p;
-	err = 0;
+	return 0;
 
 out_iounmap:
 	of_iounmap(&op->resource[0], p->regs, 2);
diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
index ec2a39b1e26f..7c284342f30f 100644
--- a/drivers/xen/Makefile
+++ b/drivers/xen/Makefile
@@ -1,6 +1,9 @@
 obj-y	+= grant-table.o features.o events.o manage.o
 obj-y	+= xenbus/
 
+nostackp := $(call cc-option, -fno-stack-protector)
+CFLAGS_features.o			:= $(nostackp)
+
 obj-$(CONFIG_HOTPLUG_CPU)	+= cpu_hotplug.o
 obj-$(CONFIG_XEN_XENCOMM)	+= xencomm.o
 obj-$(CONFIG_XEN_BALLOON)	+= balloon.o
diff --git a/drivers/xen/balloon.c b/drivers/xen/balloon.c
index f5bbd9e83416..1b7123eb5d7b 100644
--- a/drivers/xen/balloon.c
+++ b/drivers/xen/balloon.c
@@ -96,11 +96,7 @@ static struct balloon_stats balloon_stats;
 /* We increase/decrease in batches which fit in a page */
 static unsigned long frame_list[PAGE_SIZE / sizeof(unsigned long)];
 
-/* VM /proc information for memory */
-extern unsigned long totalram_pages;
-
 #ifdef CONFIG_HIGHMEM
-extern unsigned long totalhigh_pages;
 #define inc_totalhigh_pages() (totalhigh_pages++)
 #define dec_totalhigh_pages() (totalhigh_pages--)
 #else